VirtualBox

source: vbox/trunk/include/iprt/x86.h@ 82968

Last change on this file since 82968 was 82968, checked in by vboxsync, 5 years ago

Copyright year updates by scm.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 172.8 KB
Line 
1/** @file
2 * IPRT - X86 and AMD64 Structures and Definitions.
3 *
4 * @note x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2020 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * The contents of this file may alternatively be used under the terms
19 * of the Common Development and Distribution License Version 1.0
20 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21 * VirtualBox OSE distribution, in which case the provisions of the
22 * CDDL are applicable instead of those of the GPL.
23 *
24 * You may elect to license modified versions of this file under the
25 * terms and conditions of either the GPL or the CDDL or both.
26 */
27
28#ifndef IPRT_INCLUDED_x86_h
29#define IPRT_INCLUDED_x86_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#ifndef VBOX_FOR_DTRACE_LIB
35# include <iprt/types.h>
36# include <iprt/assert.h>
37#else
38# pragma D depends_on library vbox-types.d
39#endif
40
41/* Workaround for Solaris sys/regset.h defining CS, DS */
42#ifdef RT_OS_SOLARIS
43# undef CS
44# undef DS
45#endif
46
47/** @defgroup grp_rt_x86 x86 Types and Definitions
48 * @ingroup grp_rt
49 * @{
50 */
51
52#ifndef VBOX_FOR_DTRACE_LIB
53/**
54 * EFLAGS Bits.
55 */
56typedef struct X86EFLAGSBITS
57{
58 /** Bit 0 - CF - Carry flag - Status flag. */
59 unsigned u1CF : 1;
60 /** Bit 1 - 1 - Reserved flag. */
61 unsigned u1Reserved0 : 1;
62 /** Bit 2 - PF - Parity flag - Status flag. */
63 unsigned u1PF : 1;
64 /** Bit 3 - 0 - Reserved flag. */
65 unsigned u1Reserved1 : 1;
66 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
67 unsigned u1AF : 1;
68 /** Bit 5 - 0 - Reserved flag. */
69 unsigned u1Reserved2 : 1;
70 /** Bit 6 - ZF - Zero flag - Status flag. */
71 unsigned u1ZF : 1;
72 /** Bit 7 - SF - Signed flag - Status flag. */
73 unsigned u1SF : 1;
74 /** Bit 8 - TF - Trap flag - System flag. */
75 unsigned u1TF : 1;
76 /** Bit 9 - IF - Interrupt flag - System flag. */
77 unsigned u1IF : 1;
78 /** Bit 10 - DF - Direction flag - Control flag. */
79 unsigned u1DF : 1;
80 /** Bit 11 - OF - Overflow flag - Status flag. */
81 unsigned u1OF : 1;
82 /** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
83 unsigned u2IOPL : 2;
84 /** Bit 14 - NT - Nested task flag - System flag. */
85 unsigned u1NT : 1;
86 /** Bit 15 - 0 - Reserved flag. */
87 unsigned u1Reserved3 : 1;
88 /** Bit 16 - RF - Resume flag - System flag. */
89 unsigned u1RF : 1;
90 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
91 unsigned u1VM : 1;
92 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
93 unsigned u1AC : 1;
94 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
95 unsigned u1VIF : 1;
96 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
97 unsigned u1VIP : 1;
98 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
99 unsigned u1ID : 1;
100 /** Bit 22-31 - 0 - Reserved flag. */
101 unsigned u10Reserved4 : 10;
102} X86EFLAGSBITS;
103/** Pointer to EFLAGS bits. */
104typedef X86EFLAGSBITS *PX86EFLAGSBITS;
105/** Pointer to const EFLAGS bits. */
106typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
107#endif /* !VBOX_FOR_DTRACE_LIB */
108
109/**
110 * EFLAGS.
111 */
112typedef union X86EFLAGS
113{
114 /** The plain unsigned view. */
115 uint32_t u;
116#ifndef VBOX_FOR_DTRACE_LIB
117 /** The bitfield view. */
118 X86EFLAGSBITS Bits;
119#endif
120 /** The 8-bit view. */
121 uint8_t au8[4];
122 /** The 16-bit view. */
123 uint16_t au16[2];
124 /** The 32-bit view. */
125 uint32_t au32[1];
126 /** The 32-bit view. */
127 uint32_t u32;
128} X86EFLAGS;
129/** Pointer to EFLAGS. */
130typedef X86EFLAGS *PX86EFLAGS;
131/** Pointer to const EFLAGS. */
132typedef const X86EFLAGS *PCX86EFLAGS;
133
134/**
135 * RFLAGS (32 upper bits are reserved).
136 */
137typedef union X86RFLAGS
138{
139 /** The plain unsigned view. */
140 uint64_t u;
141#ifndef VBOX_FOR_DTRACE_LIB
142 /** The bitfield view. */
143 X86EFLAGSBITS Bits;
144#endif
145 /** The 8-bit view. */
146 uint8_t au8[8];
147 /** The 16-bit view. */
148 uint16_t au16[4];
149 /** The 32-bit view. */
150 uint32_t au32[2];
151 /** The 64-bit view. */
152 uint64_t au64[1];
153 /** The 64-bit view. */
154 uint64_t u64;
155} X86RFLAGS;
156/** Pointer to RFLAGS. */
157typedef X86RFLAGS *PX86RFLAGS;
158/** Pointer to const RFLAGS. */
159typedef const X86RFLAGS *PCX86RFLAGS;
160
161
162/** @name EFLAGS
163 * @{
164 */
165/** Bit 0 - CF - Carry flag - Status flag. */
166#define X86_EFL_CF RT_BIT_32(0)
167#define X86_EFL_CF_BIT 0
168/** Bit 1 - Reserved, reads as 1. */
169#define X86_EFL_1 RT_BIT_32(1)
170/** Bit 2 - PF - Parity flag - Status flag. */
171#define X86_EFL_PF RT_BIT_32(2)
172/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
173#define X86_EFL_AF RT_BIT_32(4)
174#define X86_EFL_AF_BIT 4
175/** Bit 6 - ZF - Zero flag - Status flag. */
176#define X86_EFL_ZF RT_BIT_32(6)
177#define X86_EFL_ZF_BIT 6
178/** Bit 7 - SF - Signed flag - Status flag. */
179#define X86_EFL_SF RT_BIT_32(7)
180#define X86_EFL_SF_BIT 7
181/** Bit 8 - TF - Trap flag - System flag. */
182#define X86_EFL_TF RT_BIT_32(8)
183/** Bit 9 - IF - Interrupt flag - System flag. */
184#define X86_EFL_IF RT_BIT_32(9)
185/** Bit 10 - DF - Direction flag - Control flag. */
186#define X86_EFL_DF RT_BIT_32(10)
187/** Bit 11 - OF - Overflow flag - Status flag. */
188#define X86_EFL_OF RT_BIT_32(11)
189#define X86_EFL_OF_BIT 11
190/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
191#define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
192/** Bit 14 - NT - Nested task flag - System flag. */
193#define X86_EFL_NT RT_BIT_32(14)
194/** Bit 16 - RF - Resume flag - System flag. */
195#define X86_EFL_RF RT_BIT_32(16)
196/** Bit 17 - VM - Virtual 8086 mode - System flag. */
197#define X86_EFL_VM RT_BIT_32(17)
198/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
199#define X86_EFL_AC RT_BIT_32(18)
200/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
201#define X86_EFL_VIF RT_BIT_32(19)
202/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
203#define X86_EFL_VIP RT_BIT_32(20)
204/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
205#define X86_EFL_ID RT_BIT_32(21)
206/** All live bits. */
207#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
208/** Read as 1 bits. */
209#define X86_EFL_RA1_MASK RT_BIT_32(1)
210/** IOPL shift. */
211#define X86_EFL_IOPL_SHIFT 12
212/** The IOPL level from the flags. */
213#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
214/** Bits restored by popf */
215#define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
216 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
217/** Bits restored by popf */
218#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
219 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
220/** The status bits commonly updated by arithmetic instructions. */
221#define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
222/** @} */
223
224
225/** CPUID Feature information - ECX.
226 * CPUID query with EAX=1.
227 */
228#ifndef VBOX_FOR_DTRACE_LIB
229typedef struct X86CPUIDFEATECX
230{
231 /** Bit 0 - SSE3 - Supports SSE3 or not. */
232 unsigned u1SSE3 : 1;
233 /** Bit 1 - PCLMULQDQ. */
234 unsigned u1PCLMULQDQ : 1;
235 /** Bit 2 - DS Area 64-bit layout. */
236 unsigned u1DTE64 : 1;
237 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
238 unsigned u1Monitor : 1;
239 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
240 unsigned u1CPLDS : 1;
241 /** Bit 5 - VMX - Virtual Machine Technology. */
242 unsigned u1VMX : 1;
243 /** Bit 6 - SMX: Safer Mode Extensions. */
244 unsigned u1SMX : 1;
245 /** Bit 7 - EST - Enh. SpeedStep Tech. */
246 unsigned u1EST : 1;
247 /** Bit 8 - TM2 - Terminal Monitor 2. */
248 unsigned u1TM2 : 1;
249 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
250 unsigned u1SSSE3 : 1;
251 /** Bit 10 - CNTX-ID - L1 Context ID. */
252 unsigned u1CNTXID : 1;
253 /** Bit 11 - Reserved. */
254 unsigned u1Reserved1 : 1;
255 /** Bit 12 - FMA. */
256 unsigned u1FMA : 1;
257 /** Bit 13 - CX16 - CMPXCHG16B. */
258 unsigned u1CX16 : 1;
259 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
260 unsigned u1TPRUpdate : 1;
261 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
262 unsigned u1PDCM : 1;
263 /** Bit 16 - Reserved. */
264 unsigned u1Reserved2 : 1;
265 /** Bit 17 - PCID - Process-context identifiers. */
266 unsigned u1PCID : 1;
267 /** Bit 18 - Direct Cache Access. */
268 unsigned u1DCA : 1;
269 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
270 unsigned u1SSE4_1 : 1;
271 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
272 unsigned u1SSE4_2 : 1;
273 /** Bit 21 - x2APIC. */
274 unsigned u1x2APIC : 1;
275 /** Bit 22 - MOVBE - Supports MOVBE. */
276 unsigned u1MOVBE : 1;
277 /** Bit 23 - POPCNT - Supports POPCNT. */
278 unsigned u1POPCNT : 1;
279 /** Bit 24 - TSC-Deadline. */
280 unsigned u1TSCDEADLINE : 1;
281 /** Bit 25 - AES. */
282 unsigned u1AES : 1;
283 /** Bit 26 - XSAVE - Supports XSAVE. */
284 unsigned u1XSAVE : 1;
285 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
286 unsigned u1OSXSAVE : 1;
287 /** Bit 28 - AVX - Supports AVX instruction extensions. */
288 unsigned u1AVX : 1;
289 /** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
290 unsigned u1F16C : 1;
291 /** Bit 30 - RDRAND - Supports RDRAND. */
292 unsigned u1RDRAND : 1;
293 /** Bit 31 - Hypervisor present (we're a guest). */
294 unsigned u1HVP : 1;
295} X86CPUIDFEATECX;
296#else /* VBOX_FOR_DTRACE_LIB */
297typedef uint32_t X86CPUIDFEATECX;
298#endif /* VBOX_FOR_DTRACE_LIB */
299/** Pointer to CPUID Feature Information - ECX. */
300typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
301/** Pointer to const CPUID Feature Information - ECX. */
302typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
303
304
305/** CPUID Feature Information - EDX.
306 * CPUID query with EAX=1.
307 */
308#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
309typedef struct X86CPUIDFEATEDX
310{
311 /** Bit 0 - FPU - x87 FPU on Chip. */
312 unsigned u1FPU : 1;
313 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
314 unsigned u1VME : 1;
315 /** Bit 2 - DE - Debugging extensions. */
316 unsigned u1DE : 1;
317 /** Bit 3 - PSE - Page Size Extension. */
318 unsigned u1PSE : 1;
319 /** Bit 4 - TSC - Time Stamp Counter. */
320 unsigned u1TSC : 1;
321 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
322 unsigned u1MSR : 1;
323 /** Bit 6 - PAE - Physical Address Extension. */
324 unsigned u1PAE : 1;
325 /** Bit 7 - MCE - Machine Check Exception. */
326 unsigned u1MCE : 1;
327 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
328 unsigned u1CX8 : 1;
329 /** Bit 9 - APIC - APIC On-Chip. */
330 unsigned u1APIC : 1;
331 /** Bit 10 - Reserved. */
332 unsigned u1Reserved1 : 1;
333 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
334 unsigned u1SEP : 1;
335 /** Bit 12 - MTRR - Memory Type Range Registers. */
336 unsigned u1MTRR : 1;
337 /** Bit 13 - PGE - PTE Global Bit. */
338 unsigned u1PGE : 1;
339 /** Bit 14 - MCA - Machine Check Architecture. */
340 unsigned u1MCA : 1;
341 /** Bit 15 - CMOV - Conditional Move Instructions. */
342 unsigned u1CMOV : 1;
343 /** Bit 16 - PAT - Page Attribute Table. */
344 unsigned u1PAT : 1;
345 /** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
346 unsigned u1PSE36 : 1;
347 /** Bit 18 - PSN - Processor Serial Number. */
348 unsigned u1PSN : 1;
349 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
350 unsigned u1CLFSH : 1;
351 /** Bit 20 - Reserved. */
352 unsigned u1Reserved2 : 1;
353 /** Bit 21 - DS - Debug Store. */
354 unsigned u1DS : 1;
355 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
356 unsigned u1ACPI : 1;
357 /** Bit 23 - MMX - Intel MMX 'Technology'. */
358 unsigned u1MMX : 1;
359 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
360 unsigned u1FXSR : 1;
361 /** Bit 25 - SSE - SSE Support. */
362 unsigned u1SSE : 1;
363 /** Bit 26 - SSE2 - SSE2 Support. */
364 unsigned u1SSE2 : 1;
365 /** Bit 27 - SS - Self Snoop. */
366 unsigned u1SS : 1;
367 /** Bit 28 - HTT - Hyper-Threading Technology. */
368 unsigned u1HTT : 1;
369 /** Bit 29 - TM - Thermal Monitor. */
370 unsigned u1TM : 1;
371 /** Bit 30 - Reserved - . */
372 unsigned u1Reserved3 : 1;
373 /** Bit 31 - PBE - Pending Break Enabled. */
374 unsigned u1PBE : 1;
375} X86CPUIDFEATEDX;
376#else /* VBOX_FOR_DTRACE_LIB */
377typedef uint32_t X86CPUIDFEATEDX;
378#endif /* VBOX_FOR_DTRACE_LIB */
379/** Pointer to CPUID Feature Information - EDX. */
380typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
381/** Pointer to const CPUID Feature Information - EDX. */
382typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
383
384/** @name CPUID Vendor information.
385 * CPUID query with EAX=0.
386 * @{
387 */
388#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
389#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
390#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
391
392#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
393#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
394#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
395
396#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
397#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
398#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
399
400#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
401#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
402#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
403
404#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
405#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
406#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
407/** @} */
408
409
410/** @name CPUID Feature information.
411 * CPUID query with EAX=1.
412 * @{
413 */
414/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
415#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
416/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
417#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
418/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
419#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
420/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
421#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
422/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
423#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
424/** ECX Bit 5 - VMX - Virtual Machine Technology. */
425#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
426/** ECX Bit 6 - SMX - Safer Mode Extensions. */
427#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
428/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
429#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
430/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
431#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
432/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
433#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
434/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
435#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
436/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
437 * See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
438#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
439/** ECX Bit 12 - FMA. */
440#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
441/** ECX Bit 13 - CX16 - CMPXCHG16B. */
442#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
443/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
444#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
445/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
446#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
447/** ECX Bit 17 - PCID - Process-context identifiers. */
448#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
449/** ECX Bit 18 - DCA - Direct Cache Access. */
450#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
451/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
452#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
453/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
454#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
455/** ECX Bit 21 - x2APIC support. */
456#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
457/** ECX Bit 22 - MOVBE instruction. */
458#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
459/** ECX Bit 23 - POPCNT instruction. */
460#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
461/** ECX Bir 24 - TSC-Deadline. */
462#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
463/** ECX Bit 25 - AES instructions. */
464#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
465/** ECX Bit 26 - XSAVE instruction. */
466#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
467/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
468#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
469/** ECX Bit 28 - AVX. */
470#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
471/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
472#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
473/** ECX Bit 30 - RDRAND instruction. */
474#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
475/** ECX Bit 31 - Hypervisor Present (software only). */
476#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
477
478
479/** Bit 0 - FPU - x87 FPU on Chip. */
480#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
481/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
482#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
483/** Bit 2 - DE - Debugging extensions. */
484#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
485/** Bit 3 - PSE - Page Size Extension. */
486#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
487#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /**< Bit number for X86_CPUID_FEATURE_EDX_PSE. */
488/** Bit 4 - TSC - Time Stamp Counter. */
489#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
490/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
491#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
492/** Bit 6 - PAE - Physical Address Extension. */
493#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
494#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /**< Bit number for X86_CPUID_FEATURE_EDX_PAE. */
495/** Bit 7 - MCE - Machine Check Exception. */
496#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
497/** Bit 8 - CX8 - CMPXCHG8B instruction. */
498#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
499/** Bit 9 - APIC - APIC On-Chip. */
500#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
501/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
502#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
503/** Bit 12 - MTRR - Memory Type Range Registers. */
504#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
505/** Bit 13 - PGE - PTE Global Bit. */
506#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
507/** Bit 14 - MCA - Machine Check Architecture. */
508#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
509/** Bit 15 - CMOV - Conditional Move Instructions. */
510#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
511/** Bit 16 - PAT - Page Attribute Table. */
512#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
513/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
514#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
515/** Bit 18 - PSN - Processor Serial Number. */
516#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
517/** Bit 19 - CLFSH - CLFLUSH Instruction. */
518#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
519/** Bit 21 - DS - Debug Store. */
520#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
521/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
522#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
523/** Bit 23 - MMX - Intel MMX Technology. */
524#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
525/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
526#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
527/** Bit 25 - SSE - SSE Support. */
528#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
529/** Bit 26 - SSE2 - SSE2 Support. */
530#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
531/** Bit 27 - SS - Self Snoop. */
532#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
533/** Bit 28 - HTT - Hyper-Threading Technology. */
534#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
535/** Bit 29 - TM - Therm. Monitor. */
536#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
537/** Bit 31 - PBE - Pending Break Enabled. */
538#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
539/** @} */
540
541/** @name CPUID mwait/monitor information.
542 * CPUID query with EAX=5.
543 * @{
544 */
545/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
546#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
547/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
548#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
549/** @} */
550
551
552/** @name CPUID Structured Extended Feature information.
553 * CPUID query with EAX=7.
554 * @{
555 */
556/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
557#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
558/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
559#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
560/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
561#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
562/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
563#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
564/** EBX Bit 4 - HLE - Hardware Lock Elision. */
565#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
566/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
567#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
568/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
569#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
570/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
571#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
572/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
573#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
574/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
575#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
576/** EBX Bit 10 - INVPCID - Supports INVPCID. */
577#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
578/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
579#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
580/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
581#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
582/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
583#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
584/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
585#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
586/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
587#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
588/** EBX Bit 16 - AVX512F - Supports AVX512F. */
589#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
590/** EBX Bit 18 - RDSEED - Supports RDSEED. */
591#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
592/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
593#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
594/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
595#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
596/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
597#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
598/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
599#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
600/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
601#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
602/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
603#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
604/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
605#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
606/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
607#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
608
609/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
610#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
611/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
612#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
613/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
614#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
615/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
616#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
617/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
618#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
619/** ECX Bit 22 - RDPID - Support pread process ID. */
620#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
621/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
622#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
623
624/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
625#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
626/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
627 * IBPB command in IA32_PRED_CMD. */
628#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
629/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
630#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
631/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
632#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
633/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
634#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
635
636/** @} */
637
638
639/** @name CPUID Extended Feature information.
640 * CPUID query with EAX=0x80000001.
641 * @{
642 */
643/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
644#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
645
646/** EDX Bit 11 - SYSCALL/SYSRET. */
647#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
648/** EDX Bit 20 - No-Execute/Execute-Disable. */
649#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
650/** EDX Bit 26 - 1 GB large page. */
651#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
652/** EDX Bit 27 - RDTSCP. */
653#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
654/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
655#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
656/** @}*/
657
658/** @name CPUID AMD Feature information.
659 * CPUID query with EAX=0x80000001.
660 * @{
661 */
662/** Bit 0 - FPU - x87 FPU on Chip. */
663#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
664/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
665#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
666/** Bit 2 - DE - Debugging extensions. */
667#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
668/** Bit 3 - PSE - Page Size Extension. */
669#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
670/** Bit 4 - TSC - Time Stamp Counter. */
671#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
672/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
673#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
674/** Bit 6 - PAE - Physical Address Extension. */
675#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
676/** Bit 7 - MCE - Machine Check Exception. */
677#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
678/** Bit 8 - CX8 - CMPXCHG8B instruction. */
679#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
680/** Bit 9 - APIC - APIC On-Chip. */
681#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
682/** Bit 12 - MTRR - Memory Type Range Registers. */
683#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
684/** Bit 13 - PGE - PTE Global Bit. */
685#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
686/** Bit 14 - MCA - Machine Check Architecture. */
687#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
688/** Bit 15 - CMOV - Conditional Move Instructions. */
689#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
690/** Bit 16 - PAT - Page Attribute Table. */
691#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
692/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
693#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
694/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
695#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
696/** Bit 23 - MMX - Intel MMX Technology. */
697#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
698/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
699#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
700/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
701#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
702/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
703#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
704/** Bit 31 - 3DNOW - AMD 3DNow. */
705#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
706
707/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
708#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
709/** Bit 2 - SVM - AMD VM extensions. */
710#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
711/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
712#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
713/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
714#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
715/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
716#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
717/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
718#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
719/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
720#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
721/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
722#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
723/** Bit 9 - OSVW - AMD OS visible workaround. */
724#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
725/** Bit 10 - IBS - Instruct based sampling. */
726#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
727/** Bit 11 - XOP - Extended operation support (see APM6). */
728#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
729/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
730#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
731/** Bit 13 - WDT - AMD Watchdog timer support. */
732#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
733/** Bit 15 - LWP - Lightweight profiling support. */
734#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
735/** Bit 16 - FMA4 - Four operand FMA instruction support. */
736#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
737/** Bit 19 - NodeId - Indicates support for
738 * MSR_C001_100C[NodeId,NodesPerProcessr]. */
739#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
740/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
741#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
742/** Bit 22 - TopologyExtensions - . */
743#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
744/** @} */
745
746
747/** @name CPUID AMD Feature information.
748 * CPUID query with EAX=0x80000007.
749 * @{
750 */
751/** Bit 0 - TS - Temperature Sensor. */
752#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
753/** Bit 1 - FID - Frequency ID Control. */
754#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
755/** Bit 2 - VID - Voltage ID Control. */
756#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
757/** Bit 3 - TTP - THERMTRIP. */
758#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
759/** Bit 4 - TM - Hardware Thermal Control. */
760#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
761/** Bit 5 - STC - Software Thermal Control. */
762#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
763/** Bit 6 - MC - 100 Mhz Multiplier Control. */
764#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
765/** Bit 7 - HWPSTATE - Hardware P-State Control. */
766#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
767/** Bit 8 - TSCINVAR - TSC Invariant. */
768#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
769/** Bit 9 - CPB - TSC Invariant. */
770#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
771/** Bit 10 - EffFreqRO - MPERF/APERF. */
772#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
773/** Bit 11 - PFI - Processor feedback interface (see EAX). */
774#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
775/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
776#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
777/** @} */
778
779
780/** @name CPUID AMD extended feature extensions ID (EBX).
781 * CPUID query with EAX=0x80000008.
782 * @{
783 */
784/** Bit 0 - CLZERO - Clear zero instruction. */
785#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
786/** Bit 1 - IRPerf - Instructions retired count support. */
787#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
788/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
789#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
790/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
791#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
792/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
793#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
794/* AMD pipeline length: 9 feature bits ;-) */
795/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
796#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
797/** @} */
798
799
800/** @name CPUID AMD SVM Feature information.
801 * CPUID query with EAX=0x8000000a.
802 * @{
803 */
804/** Bit 0 - NP - Nested Paging supported. */
805#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
806/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
807#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
808/** Bit 2 - SVML - SVM locking bit supported. */
809#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
810/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
811#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
812/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
813#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
814/** Bit 5 - VmcbClean - Support VMCB clean bits. */
815#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
816/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
817 * VMCB.TLB_Control is supported. */
818#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
819/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
820#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
821/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
822#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
823/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
824 * intercept filter cycle count threshold. */
825#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
826/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
827#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
828/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
829#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
830/** Bit 16 - VGIF - Supports virtualized GIF. */
831#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
832/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
833#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
834
835/** @} */
836
837
838/** @name CR0
839 * @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
840 * reserved flags.
841 * @{ */
842/** Bit 0 - PE - Protection Enabled */
843#define X86_CR0_PE RT_BIT_32(0)
844#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
845/** Bit 1 - MP - Monitor Coprocessor */
846#define X86_CR0_MP RT_BIT_32(1)
847#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
848/** Bit 2 - EM - Emulation. */
849#define X86_CR0_EM RT_BIT_32(2)
850#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
851/** Bit 3 - TS - Task Switch. */
852#define X86_CR0_TS RT_BIT_32(3)
853#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
854/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
855#define X86_CR0_ET RT_BIT_32(4)
856#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
857/** Bit 5 - NE - Numeric error (486+). */
858#define X86_CR0_NE RT_BIT_32(5)
859#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
860/** Bit 16 - WP - Write Protect (486+). */
861#define X86_CR0_WP RT_BIT_32(16)
862#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
863/** Bit 18 - AM - Alignment Mask (486+). */
864#define X86_CR0_AM RT_BIT_32(18)
865#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
866/** Bit 29 - NW - Not Write-though (486+). */
867#define X86_CR0_NW RT_BIT_32(29)
868#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
869/** Bit 30 - WP - Cache Disable (486+). */
870#define X86_CR0_CD RT_BIT_32(30)
871#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
872/** Bit 31 - PG - Paging. */
873#define X86_CR0_PG RT_BIT_32(31)
874#define X86_CR0_PAGING RT_BIT_32(31)
875#define X86_CR0_BIT_PG 31 /**< Bit number of X86_CR0_PG */
876/** @} */
877
878
879/** @name CR3
880 * @{ */
881/** Bit 3 - PWT - Page-level Writes Transparent. */
882#define X86_CR3_PWT RT_BIT_32(3)
883/** Bit 4 - PCD - Page-level Cache Disable. */
884#define X86_CR3_PCD RT_BIT_32(4)
885/** Bits 12-31 - - Page directory page number. */
886#define X86_CR3_PAGE_MASK (0xfffff000)
887/** Bits 5-31 - - PAE Page directory page number. */
888#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
889/** Bits 12-51 - - AMD64 Page directory page number. */
890#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
891/** @} */
892
893
894/** @name CR4
895 * @{ */
896/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
897#define X86_CR4_VME RT_BIT_32(0)
898/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
899#define X86_CR4_PVI RT_BIT_32(1)
900/** Bit 2 - TSD - Time Stamp Disable. */
901#define X86_CR4_TSD RT_BIT_32(2)
902/** Bit 3 - DE - Debugging Extensions. */
903#define X86_CR4_DE RT_BIT_32(3)
904/** Bit 4 - PSE - Page Size Extension. */
905#define X86_CR4_PSE RT_BIT_32(4)
906/** Bit 5 - PAE - Physical Address Extension. */
907#define X86_CR4_PAE RT_BIT_32(5)
908/** Bit 6 - MCE - Machine-Check Enable. */
909#define X86_CR4_MCE RT_BIT_32(6)
910/** Bit 7 - PGE - Page Global Enable. */
911#define X86_CR4_PGE RT_BIT_32(7)
912/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
913#define X86_CR4_PCE RT_BIT_32(8)
914/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
915#define X86_CR4_OSFXSR RT_BIT_32(9)
916/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
917#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
918/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
919#define X86_CR4_UMIP RT_BIT_32(11)
920/** Bit 13 - VMXE - VMX mode is enabled. */
921#define X86_CR4_VMXE RT_BIT_32(13)
922/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
923#define X86_CR4_SMXE RT_BIT_32(14)
924/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
925#define X86_CR4_FSGSBASE RT_BIT_32(16)
926/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
927#define X86_CR4_PCIDE RT_BIT_32(17)
928/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
929 * extended states. */
930#define X86_CR4_OSXSAVE RT_BIT_32(18)
931/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
932#define X86_CR4_SMEP RT_BIT_32(20)
933/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
934#define X86_CR4_SMAP RT_BIT_32(21)
935/** Bit 22 - PKE - Protection Key Enable. */
936#define X86_CR4_PKE RT_BIT_32(22)
937/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
938#define X86_CR4_CET RT_BIT_32(23)
939/** @} */
940
941
942/** @name DR6
943 * @{ */
944/** Bit 0 - B0 - Breakpoint 0 condition detected. */
945#define X86_DR6_B0 RT_BIT_32(0)
946/** Bit 1 - B1 - Breakpoint 1 condition detected. */
947#define X86_DR6_B1 RT_BIT_32(1)
948/** Bit 2 - B2 - Breakpoint 2 condition detected. */
949#define X86_DR6_B2 RT_BIT_32(2)
950/** Bit 3 - B3 - Breakpoint 3 condition detected. */
951#define X86_DR6_B3 RT_BIT_32(3)
952/** Mask of all the Bx bits. */
953#define X86_DR6_B_MASK UINT64_C(0x0000000f)
954/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
955#define X86_DR6_BD RT_BIT_32(13)
956/** Bit 14 - BS - Single step */
957#define X86_DR6_BS RT_BIT_32(14)
958/** Bit 15 - BT - Task switch. (TSS T bit.) */
959#define X86_DR6_BT RT_BIT_32(15)
960/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
961#define X86_DR6_RTM RT_BIT_32(16)
962/** Value of DR6 after powerup/reset. */
963#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
964/** Bits which must be 1s in DR6. */
965#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
966/** Bits which must be 1s in DR6, when RTM is supported. */
967#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
968/** Bits which must be 0s in DR6. */
969#define X86_DR6_RAZ_MASK RT_BIT_64(12)
970/** Bits which must be 0s on writes to DR6. */
971#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
972/** @} */
973
974/** Get the DR6.Bx bit for a the given breakpoint. */
975#define X86_DR6_B(iBp) RT_BIT_64(iBp)
976
977
978/** @name DR7
979 * @{ */
980/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
981#define X86_DR7_L0 RT_BIT_32(0)
982/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
983#define X86_DR7_G0 RT_BIT_32(1)
984/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
985#define X86_DR7_L1 RT_BIT_32(2)
986/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
987#define X86_DR7_G1 RT_BIT_32(3)
988/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
989#define X86_DR7_L2 RT_BIT_32(4)
990/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
991#define X86_DR7_G2 RT_BIT_32(5)
992/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
993#define X86_DR7_L3 RT_BIT_32(6)
994/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
995#define X86_DR7_G3 RT_BIT_32(7)
996/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
997#define X86_DR7_LE RT_BIT_32(8)
998/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
999#define X86_DR7_GE RT_BIT_32(9)
1000
1001/** L0, L1, L2, and L3. */
1002#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1003/** L0, L1, L2, and L3. */
1004#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1005
1006/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1007 * Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1008#define X86_DR7_RTM RT_BIT_32(11)
1009/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1010 * Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1011 * May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1012 * instruction is executed.
1013 * @see http://www.rcollins.org/secrets/DR7.html */
1014#define X86_DR7_ICE_IR RT_BIT_32(12)
1015/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1016 * any DR register is accessed. */
1017#define X86_DR7_GD RT_BIT_32(13)
1018/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1019 * Pentium. */
1020#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1021/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1022#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1023/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
1024#define X86_DR7_RW0_MASK (3 << 16)
1025/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
1026#define X86_DR7_LEN0_MASK (3 << 18)
1027/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
1028#define X86_DR7_RW1_MASK (3 << 20)
1029/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
1030#define X86_DR7_LEN1_MASK (3 << 22)
1031/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
1032#define X86_DR7_RW2_MASK (3 << 24)
1033/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
1034#define X86_DR7_LEN2_MASK (3 << 26)
1035/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
1036#define X86_DR7_RW3_MASK (3 << 28)
1037/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
1038#define X86_DR7_LEN3_MASK (3 << 30)
1039
1040/** Bits which reads as 1s. */
1041#define X86_DR7_RA1_MASK RT_BIT_32(10)
1042/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1043#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1044/** Bits which must be 0s when writing to DR7. */
1045#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1046
1047/** Calcs the L bit of Nth breakpoint.
1048 * @param iBp The breakpoint number [0..3].
1049 */
1050#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1051
1052/** Calcs the G bit of Nth breakpoint.
1053 * @param iBp The breakpoint number [0..3].
1054 */
1055#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1056
1057/** Calcs the L and G bits of Nth breakpoint.
1058 * @param iBp The breakpoint number [0..3].
1059 */
1060#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1061
1062/** @name Read/Write values.
1063 * @{ */
1064/** Break on instruction fetch only. */
1065#define X86_DR7_RW_EO UINT32_C(0)
1066/** Break on write only. */
1067#define X86_DR7_RW_WO UINT32_C(1)
1068/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1069#define X86_DR7_RW_IO UINT32_C(2)
1070/** Break on read or write (but not instruction fetches). */
1071#define X86_DR7_RW_RW UINT32_C(3)
1072/** @} */
1073
1074/** Shifts a X86_DR7_RW_* value to its right place.
1075 * @param iBp The breakpoint number [0..3].
1076 * @param fRw One of the X86_DR7_RW_* value.
1077 */
1078#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1079
1080/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1081 * one of the X86_DR7_RW_XXX constants).
1082 *
1083 * @returns X86_DR7_RW_XXX
1084 * @param uDR7 DR7 value
1085 * @param iBp The breakpoint number [0..3].
1086 */
1087#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1088
1089/** R/W0, R/W1, R/W2, and R/W3. */
1090#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1091
1092#ifndef VBOX_FOR_DTRACE_LIB
1093/** Checks if there are any I/O breakpoint types configured in the RW
1094 * registers. Does NOT check if these are enabled, sorry. */
1095# define X86_DR7_ANY_RW_IO(uDR7) \
1096 ( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1097 && ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1098AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1099AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1100AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1101AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1102AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1103AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1104AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1105AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1106AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1107#endif /* !VBOX_FOR_DTRACE_LIB */
1108
1109/** @name Length values.
1110 * @{ */
1111#define X86_DR7_LEN_BYTE UINT32_C(0)
1112#define X86_DR7_LEN_WORD UINT32_C(1)
1113#define X86_DR7_LEN_QWORD UINT32_C(2) /**< AMD64 long mode only. */
1114#define X86_DR7_LEN_DWORD UINT32_C(3)
1115/** @} */
1116
1117/** Shifts a X86_DR7_LEN_* value to its right place.
1118 * @param iBp The breakpoint number [0..3].
1119 * @param cb One of the X86_DR7_LEN_* values.
1120 */
1121#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1122
1123/** Fetch the breakpoint length bits from the DR7 value.
1124 * @param uDR7 DR7 value
1125 * @param iBp The breakpoint number [0..3].
1126 */
1127#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1128
1129/** Mask used to check if any breakpoints are enabled. */
1130#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1131
1132/** LEN0, LEN1, LEN2, and LEN3. */
1133#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1134/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1135#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1136
1137/** Value of DR7 after powerup/reset. */
1138#define X86_DR7_INIT_VAL 0x400
1139/** @} */
1140
1141
1142/** @name Machine Specific Registers
1143 * @{
1144 */
1145/** Machine check address register (P5). */
1146#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1147/** Machine check type register (P5). */
1148#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1149/** Time Stamp Counter. */
1150#define MSR_IA32_TSC 0x10
1151#define MSR_IA32_CESR UINT32_C(0x00000011)
1152#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1153#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1154
1155#define MSR_IA32_PLATFORM_ID 0x17
1156
1157#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1158# define MSR_IA32_APICBASE 0x1b
1159/** Local APIC enabled. */
1160# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1161/** X2APIC enabled (requires the EN bit to be set). */
1162# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1163/** The processor is the boot strap processor (BSP). */
1164# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1165/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1166 * width. */
1167# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1168/** The default physical base address of the APIC. */
1169# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1170/** Gets the physical base address from the MSR. */
1171# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1172#endif
1173
1174/** Undocumented intel MSR for reporting thread and core counts.
1175 * Judging from the XNU sources, it seems to be introduced in Nehalem. The
1176 * first 16 bits is the thread count. The next 16 bits the core count, except
1177 * on Westmere where it seems it's only the next 4 bits for some reason. */
1178#define MSR_CORE_THREAD_COUNT 0x35
1179
1180/** CPU Feature control. */
1181#define MSR_IA32_FEATURE_CONTROL 0x3A
1182/** Feature control - Lock MSR from writes (R/W0). */
1183#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1184/** Feature control - Enable VMX inside SMX operation (R/WL). */
1185#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1186/** Feature control - Enable VMX outside SMX operation (R/WL). */
1187#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1188/** Feature control - SENTER local functions enable (R/WL). */
1189#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1190#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1191#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1192#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1193#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1194#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1195#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1196/** Feature control - SENTER global enable (R/WL). */
1197#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1198/** Feature control - SGX launch control enable (R/WL). */
1199#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1200/** Feature control - SGX global enable (R/WL). */
1201#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1202/** Feature control - LMCE on (R/WL). */
1203#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1204
1205/** Per-processor TSC adjust MSR. */
1206#define MSR_IA32_TSC_ADJUST 0x3B
1207
1208/** Spectre control register.
1209 * Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1210#define MSR_IA32_SPEC_CTRL 0x48
1211/** IBRS - Indirect branch restricted speculation. */
1212#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1213/** STIBP - Single thread indirect branch predictors. */
1214#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1215
1216/** Prediction command register.
1217 * Write only, logical processor scope, no state since write only. */
1218#define MSR_IA32_PRED_CMD 0x49
1219/** IBPB - Indirect branch prediction barrie when written as 1. */
1220#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1221
1222/** BIOS update trigger (microcode update). */
1223#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1224
1225/** BIOS update signature (microcode). */
1226#define MSR_IA32_BIOS_SIGN_ID 0x8B
1227
1228/** SMM monitor control. */
1229#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1230/** SMM control - Valid. */
1231#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1232/** SMM control - VMXOFF unblocks SMI. */
1233#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1234/** SMM control - MSEG base physical address. */
1235#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1236
1237/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1238#define MSR_IA32_SMBASE 0x9E
1239
1240/** General performance counter no. 0. */
1241#define MSR_IA32_PMC0 0xC1
1242/** General performance counter no. 1. */
1243#define MSR_IA32_PMC1 0xC2
1244/** General performance counter no. 2. */
1245#define MSR_IA32_PMC2 0xC3
1246/** General performance counter no. 3. */
1247#define MSR_IA32_PMC3 0xC4
1248/** General performance counter no. 4. */
1249#define MSR_IA32_PMC4 0xC5
1250/** General performance counter no. 5. */
1251#define MSR_IA32_PMC5 0xC6
1252/** General performance counter no. 6. */
1253#define MSR_IA32_PMC6 0xC7
1254/** General performance counter no. 7. */
1255#define MSR_IA32_PMC7 0xC8
1256
1257/** Nehalem power control. */
1258#define MSR_IA32_PLATFORM_INFO 0xCE
1259
1260/** Get FSB clock status (Intel-specific). */
1261#define MSR_IA32_FSB_CLOCK_STS 0xCD
1262
1263/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1264#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1265
1266/** C0 Maximum Frequency Clock Count */
1267#define MSR_IA32_MPERF 0xE7
1268/** C0 Actual Frequency Clock Count */
1269#define MSR_IA32_APERF 0xE8
1270
1271/** MTRR Capabilities. */
1272#define MSR_IA32_MTRR_CAP 0xFE
1273
1274/** Architecture capabilities (bugfixes). */
1275#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1276/** CPU is no subject to meltdown problems. */
1277#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1278/** CPU has better IBRS and you can leave it on all the time. */
1279#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1280/** CPU has return stack buffer (RSB) override. */
1281#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1282/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1283 * This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1284#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1285/** CPU does not suffer from MDS issues. */
1286#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
1287
1288/** Flush command register. */
1289#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1290/** Flush the level 1 data cache when this bit is written. */
1291#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1292
1293/** Cache control/info. */
1294#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1295
1296#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1297/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1298 * R0 SS == CS + 8
1299 * R3 CS == CS + 16
1300 * R3 SS == CS + 24
1301 */
1302#define MSR_IA32_SYSENTER_CS 0x174
1303/** SYSENTER_ESP - the R0 ESP. */
1304#define MSR_IA32_SYSENTER_ESP 0x175
1305/** SYSENTER_EIP - the R0 EIP. */
1306#define MSR_IA32_SYSENTER_EIP 0x176
1307#endif
1308
1309/** Machine Check Global Capabilities Register. */
1310#define MSR_IA32_MCG_CAP 0x179
1311/** Machine Check Global Status Register. */
1312#define MSR_IA32_MCG_STATUS 0x17A
1313/** Machine Check Global Control Register. */
1314#define MSR_IA32_MCG_CTRL 0x17B
1315
1316/** Page Attribute Table. */
1317#define MSR_IA32_CR_PAT 0x277
1318/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1319 * "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1320#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1321
1322/** Performance event select MSRs. (Intel only) */
1323#define MSR_IA32_PERFEVTSEL0 0x186
1324#define MSR_IA32_PERFEVTSEL1 0x187
1325#define MSR_IA32_PERFEVTSEL2 0x188
1326#define MSR_IA32_PERFEVTSEL3 0x189
1327
1328/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1329 * The 16th bit whether flex ratio is being used, in which case bits 15:8
1330 * holds a ratio that Apple takes for TSC granularity.
1331 *
1332 * @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1333#define MSR_FLEX_RATIO 0x194
1334/** Performance state value and starting with Intel core more.
1335 * Apple uses the >=core features to determine TSC granularity on older CPUs. */
1336#define MSR_IA32_PERF_STATUS 0x198
1337#define MSR_IA32_PERF_CTL 0x199
1338#define MSR_IA32_THERM_STATUS 0x19c
1339
1340/** Offcore response event select registers. */
1341#define MSR_OFFCORE_RSP_0 0x1a6
1342#define MSR_OFFCORE_RSP_1 0x1a7
1343
1344/** Enable misc. processor features (R/W). */
1345#define MSR_IA32_MISC_ENABLE 0x1A0
1346/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1347#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1348/** Automatic Thermal Control Circuit Enable (R/W). */
1349#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1350/** Performance Monitoring Available (R). */
1351#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1352/** Branch Trace Storage Unavailable (R/O). */
1353#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1354/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1355#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1356/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1357#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1358/** If MONITOR/MWAIT is supported (R/W). */
1359#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1360/** Limit CPUID Maxval to 3 leafs (R/W). */
1361#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1362/** When set to 1, xTPR messages are disabled (R/W). */
1363#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1364/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1365#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1366
1367/** Trace/Profile Resource Control (R/W) */
1368#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1369/** Last branch record. */
1370#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1371/** Branch trace flag (single step on branches). */
1372#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1373/** Performance monitoring pin control (AMD only). */
1374#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1375#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1376#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1377#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1378/** Trace message enable (Intel only). */
1379#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1380/** Branch trace store (Intel only). */
1381#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1382/** Branch trace interrupt (Intel only). */
1383#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1384/** Branch trace off in privileged code (Intel only). */
1385#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1386/** Branch trace off in user code (Intel only). */
1387#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1388/** Freeze LBR on PMI flag (Intel only). */
1389#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1390/** Freeze PERFMON on PMI flag (Intel only). */
1391#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1392/** Freeze while SMM enabled (Intel only). */
1393#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1394/** Advanced debugging of RTM regions (Intel only). */
1395#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1396/** Debug control MSR valid bits (Intel only). */
1397#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR | MSR_IA32_DEBUGCTL_BTF | MSR_IA32_DEBUGCTL_TR \
1398 | MSR_IA32_DEBUGCTL_BTS | MSR_IA32_DEBUGCTL_BTINT | MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1399 | MSR_IA32_DEBUGCTL_BTS_OFF_USER | MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1400 | MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI | MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1401 | MSR_IA32_DEBUGCTL_RTM)
1402
1403/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1404 * @{ */
1405#define MSR_P4_LASTBRANCH_0 0x1db
1406#define MSR_P4_LASTBRANCH_1 0x1dc
1407#define MSR_P4_LASTBRANCH_2 0x1dd
1408#define MSR_P4_LASTBRANCH_3 0x1de
1409
1410/** LBR Top-of-stack MSR (index to most recent record). */
1411#define MSR_P4_LASTBRANCH_TOS 0x1da
1412/** @} */
1413
1414/** @name Last branch registers for Core 2 and related Xeons.
1415 * @{ */
1416#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
1417#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
1418#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
1419#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
1420
1421#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
1422#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
1423#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
1424#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
1425
1426/** LBR Top-of-stack MSR (index to most recent record). */
1427#define MSR_CORE2_LASTBRANCH_TOS 0x1c9
1428/** @} */
1429
1430/** @name Last branch registers.
1431 * @{ */
1432#define MSR_LASTBRANCH_0_FROM_IP 0x680
1433#define MSR_LASTBRANCH_1_FROM_IP 0x681
1434#define MSR_LASTBRANCH_2_FROM_IP 0x682
1435#define MSR_LASTBRANCH_3_FROM_IP 0x683
1436#define MSR_LASTBRANCH_4_FROM_IP 0x684
1437#define MSR_LASTBRANCH_5_FROM_IP 0x685
1438#define MSR_LASTBRANCH_6_FROM_IP 0x686
1439#define MSR_LASTBRANCH_7_FROM_IP 0x687
1440#define MSR_LASTBRANCH_8_FROM_IP 0x688
1441#define MSR_LASTBRANCH_9_FROM_IP 0x689
1442#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1443#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1444#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1445#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1446#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1447#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1448#define MSR_LASTBRANCH_16_FROM_IP 0x690
1449#define MSR_LASTBRANCH_17_FROM_IP 0x691
1450#define MSR_LASTBRANCH_18_FROM_IP 0x692
1451#define MSR_LASTBRANCH_19_FROM_IP 0x693
1452#define MSR_LASTBRANCH_20_FROM_IP 0x694
1453#define MSR_LASTBRANCH_21_FROM_IP 0x695
1454#define MSR_LASTBRANCH_22_FROM_IP 0x696
1455#define MSR_LASTBRANCH_23_FROM_IP 0x697
1456#define MSR_LASTBRANCH_24_FROM_IP 0x698
1457#define MSR_LASTBRANCH_25_FROM_IP 0x699
1458#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1459#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1460#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1461#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1462#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1463#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1464
1465#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1466#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1467#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1468#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1469#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1470#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1471#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1472#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1473#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1474#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1475#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1476#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1477#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1478#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1479#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1480#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1481#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1482#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1483#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1484#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1485#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1486#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1487#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1488#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1489#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1490#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1491#define MSR_LASTBRANCH_26_TO_IP 0x6da
1492#define MSR_LASTBRANCH_27_TO_IP 0x6db
1493#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1494#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1495#define MSR_LASTBRANCH_30_TO_IP 0x6de
1496#define MSR_LASTBRANCH_31_TO_IP 0x6df
1497
1498/** LBR Top-of-stack MSR (index to most recent record). */
1499#define MSR_LASTBRANCH_TOS 0x1c9
1500/** @} */
1501
1502/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
1503#define IA32_TSX_CTRL 0x122
1504
1505#define IA32_MTRR_PHYSBASE0 0x200
1506#define IA32_MTRR_PHYSMASK0 0x201
1507#define IA32_MTRR_PHYSBASE1 0x202
1508#define IA32_MTRR_PHYSMASK1 0x203
1509#define IA32_MTRR_PHYSBASE2 0x204
1510#define IA32_MTRR_PHYSMASK2 0x205
1511#define IA32_MTRR_PHYSBASE3 0x206
1512#define IA32_MTRR_PHYSMASK3 0x207
1513#define IA32_MTRR_PHYSBASE4 0x208
1514#define IA32_MTRR_PHYSMASK4 0x209
1515#define IA32_MTRR_PHYSBASE5 0x20a
1516#define IA32_MTRR_PHYSMASK5 0x20b
1517#define IA32_MTRR_PHYSBASE6 0x20c
1518#define IA32_MTRR_PHYSMASK6 0x20d
1519#define IA32_MTRR_PHYSBASE7 0x20e
1520#define IA32_MTRR_PHYSMASK7 0x20f
1521#define IA32_MTRR_PHYSBASE8 0x210
1522#define IA32_MTRR_PHYSMASK8 0x211
1523#define IA32_MTRR_PHYSBASE9 0x212
1524#define IA32_MTRR_PHYSMASK9 0x213
1525
1526/** Fixed range MTRRs.
1527 * @{ */
1528#define IA32_MTRR_FIX64K_00000 0x250
1529#define IA32_MTRR_FIX16K_80000 0x258
1530#define IA32_MTRR_FIX16K_A0000 0x259
1531#define IA32_MTRR_FIX4K_C0000 0x268
1532#define IA32_MTRR_FIX4K_C8000 0x269
1533#define IA32_MTRR_FIX4K_D0000 0x26a
1534#define IA32_MTRR_FIX4K_D8000 0x26b
1535#define IA32_MTRR_FIX4K_E0000 0x26c
1536#define IA32_MTRR_FIX4K_E8000 0x26d
1537#define IA32_MTRR_FIX4K_F0000 0x26e
1538#define IA32_MTRR_FIX4K_F8000 0x26f
1539/** @} */
1540
1541/** MTRR Default Range. */
1542#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1543
1544/** Global performance counter control facilities (Intel only). */
1545#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1546#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1547#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1548
1549/** Precise Event Based sampling (Intel only). */
1550#define MSR_IA32_PEBS_ENABLE 0x3F1
1551
1552#define MSR_IA32_MC0_CTL 0x400
1553#define MSR_IA32_MC0_STATUS 0x401
1554
1555/** Basic VMX information. */
1556#define MSR_IA32_VMX_BASIC 0x480
1557/** Allowed settings for pin-based VM execution controls. */
1558#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1559/** Allowed settings for proc-based VM execution controls. */
1560#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1561/** Allowed settings for the VM-exit controls. */
1562#define MSR_IA32_VMX_EXIT_CTLS 0x483
1563/** Allowed settings for the VM-entry controls. */
1564#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1565/** Misc VMX info. */
1566#define MSR_IA32_VMX_MISC 0x485
1567/** Fixed cleared bits in CR0. */
1568#define MSR_IA32_VMX_CR0_FIXED0 0x486
1569/** Fixed set bits in CR0. */
1570#define MSR_IA32_VMX_CR0_FIXED1 0x487
1571/** Fixed cleared bits in CR4. */
1572#define MSR_IA32_VMX_CR4_FIXED0 0x488
1573/** Fixed set bits in CR4. */
1574#define MSR_IA32_VMX_CR4_FIXED1 0x489
1575/** Information for enumerating fields in the VMCS. */
1576#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1577/** Allowed settings for secondary proc-based VM execution controls */
1578#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1579/** EPT capabilities. */
1580#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1581/** Allowed settings of all pin-based VM execution controls. */
1582#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1583/** Allowed settings of all proc-based VM execution controls. */
1584#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1585/** Allowed settings of all VMX exit controls. */
1586#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1587/** Allowed settings of all VMX entry controls. */
1588#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1589/** Allowed settings for the VM-function controls. */
1590#define MSR_IA32_VMX_VMFUNC 0x491
1591
1592/** Intel PT - Enable and control for trace packet generation. */
1593#define MSR_IA32_RTIT_CTL 0x570
1594
1595/** DS Save Area (R/W). */
1596#define MSR_IA32_DS_AREA 0x600
1597/** Running Average Power Limit (RAPL) power units. */
1598#define MSR_RAPL_POWER_UNIT 0x606
1599/** Package C3 Interrupt Response Limit. */
1600#define MSR_PKGC3_IRTL 0x60a
1601/** Package C6/C7S Interrupt Response Limit 1. */
1602#define MSR_PKGC_IRTL1 0x60b
1603/** Package C6/C7S Interrupt Response Limit 2. */
1604#define MSR_PKGC_IRTL2 0x60c
1605/** Package C2 Residency Counter. */
1606#define MSR_PKG_C2_RESIDENCY 0x60d
1607/** PKG RAPL Power Limit Control. */
1608#define MSR_PKG_POWER_LIMIT 0x610
1609/** PKG Energy Status. */
1610#define MSR_PKG_ENERGY_STATUS 0x611
1611/** PKG Perf Status. */
1612#define MSR_PKG_PERF_STATUS 0x613
1613/** PKG RAPL Parameters. */
1614#define MSR_PKG_POWER_INFO 0x614
1615/** DRAM RAPL Power Limit Control. */
1616#define MSR_DRAM_POWER_LIMIT 0x618
1617/** DRAM Energy Status. */
1618#define MSR_DRAM_ENERGY_STATUS 0x619
1619/** DRAM Performance Throttling Status. */
1620#define MSR_DRAM_PERF_STATUS 0x61b
1621/** DRAM RAPL Parameters. */
1622#define MSR_DRAM_POWER_INFO 0x61c
1623/** Package C10 Residency Counter. */
1624#define MSR_PKG_C10_RESIDENCY 0x632
1625/** PP0 Energy Status. */
1626#define MSR_PP0_ENERGY_STATUS 0x639
1627/** PP1 Energy Status. */
1628#define MSR_PP1_ENERGY_STATUS 0x641
1629/** Turbo Activation Ratio. */
1630#define MSR_TURBO_ACTIVATION_RATIO 0x64c
1631/** Core Performance Limit Reasons. */
1632#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
1633
1634/** X2APIC MSR range start. */
1635#define MSR_IA32_X2APIC_START 0x800
1636/** X2APIC MSR - APIC ID Register. */
1637#define MSR_IA32_X2APIC_ID 0x802
1638/** X2APIC MSR - APIC Version Register. */
1639#define MSR_IA32_X2APIC_VERSION 0x803
1640/** X2APIC MSR - Task Priority Register. */
1641#define MSR_IA32_X2APIC_TPR 0x808
1642/** X2APIC MSR - Processor Priority register. */
1643#define MSR_IA32_X2APIC_PPR 0x80A
1644/** X2APIC MSR - End Of Interrupt register. */
1645#define MSR_IA32_X2APIC_EOI 0x80B
1646/** X2APIC MSR - Logical Destination Register. */
1647#define MSR_IA32_X2APIC_LDR 0x80D
1648/** X2APIC MSR - Spurious Interrupt Vector Register. */
1649#define MSR_IA32_X2APIC_SVR 0x80F
1650/** X2APIC MSR - In-service Register (bits 31:0). */
1651#define MSR_IA32_X2APIC_ISR0 0x810
1652/** X2APIC MSR - In-service Register (bits 63:32). */
1653#define MSR_IA32_X2APIC_ISR1 0x811
1654/** X2APIC MSR - In-service Register (bits 95:64). */
1655#define MSR_IA32_X2APIC_ISR2 0x812
1656/** X2APIC MSR - In-service Register (bits 127:96). */
1657#define MSR_IA32_X2APIC_ISR3 0x813
1658/** X2APIC MSR - In-service Register (bits 159:128). */
1659#define MSR_IA32_X2APIC_ISR4 0x814
1660/** X2APIC MSR - In-service Register (bits 191:160). */
1661#define MSR_IA32_X2APIC_ISR5 0x815
1662/** X2APIC MSR - In-service Register (bits 223:192). */
1663#define MSR_IA32_X2APIC_ISR6 0x816
1664/** X2APIC MSR - In-service Register (bits 255:224). */
1665#define MSR_IA32_X2APIC_ISR7 0x817
1666/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1667#define MSR_IA32_X2APIC_TMR0 0x818
1668/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1669#define MSR_IA32_X2APIC_TMR1 0x819
1670/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1671#define MSR_IA32_X2APIC_TMR2 0x81A
1672/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1673#define MSR_IA32_X2APIC_TMR3 0x81B
1674/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1675#define MSR_IA32_X2APIC_TMR4 0x81C
1676/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1677#define MSR_IA32_X2APIC_TMR5 0x81D
1678/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1679#define MSR_IA32_X2APIC_TMR6 0x81E
1680/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1681#define MSR_IA32_X2APIC_TMR7 0x81F
1682/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1683#define MSR_IA32_X2APIC_IRR0 0x820
1684/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1685#define MSR_IA32_X2APIC_IRR1 0x821
1686/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1687#define MSR_IA32_X2APIC_IRR2 0x822
1688/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1689#define MSR_IA32_X2APIC_IRR3 0x823
1690/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1691#define MSR_IA32_X2APIC_IRR4 0x824
1692/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1693#define MSR_IA32_X2APIC_IRR5 0x825
1694/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1695#define MSR_IA32_X2APIC_IRR6 0x826
1696/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1697#define MSR_IA32_X2APIC_IRR7 0x827
1698/** X2APIC MSR - Error Status Register. */
1699#define MSR_IA32_X2APIC_ESR 0x828
1700/** X2APIC MSR - LVT CMCI Register. */
1701#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1702/** X2APIC MSR - Interrupt Command Register. */
1703#define MSR_IA32_X2APIC_ICR 0x830
1704/** X2APIC MSR - LVT Timer Register. */
1705#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1706/** X2APIC MSR - LVT Thermal Sensor Register. */
1707#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1708/** X2APIC MSR - LVT Performance Counter Register. */
1709#define MSR_IA32_X2APIC_LVT_PERF 0x834
1710/** X2APIC MSR - LVT LINT0 Register. */
1711#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1712/** X2APIC MSR - LVT LINT1 Register. */
1713#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1714/** X2APIC MSR - LVT Error Register . */
1715#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1716/** X2APIC MSR - Timer Initial Count Register. */
1717#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1718/** X2APIC MSR - Timer Current Count Register. */
1719#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1720/** X2APIC MSR - Timer Divide Configuration Register. */
1721#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1722/** X2APIC MSR - Self IPI. */
1723#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1724/** X2APIC MSR range end. */
1725#define MSR_IA32_X2APIC_END 0x8FF
1726/** X2APIC MSR - LVT start range. */
1727#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1728/** X2APIC MSR - LVT end range (inclusive). */
1729#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1730
1731/** K6 EFER - Extended Feature Enable Register. */
1732#define MSR_K6_EFER UINT32_C(0xc0000080)
1733/** @todo document EFER */
1734/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1735#define MSR_K6_EFER_SCE RT_BIT_32(0)
1736/** Bit 8 - LME - Long mode enabled. (R/W) */
1737#define MSR_K6_EFER_LME RT_BIT_32(8)
1738#define MSR_K6_EFER_BIT_LME 8 /**< Bit number of MSR_K6_EFER_LME */
1739/** Bit 10 - LMA - Long mode active. (R) */
1740#define MSR_K6_EFER_LMA RT_BIT_32(10)
1741#define MSR_K6_EFER_BIT_LMA 10 /**< Bit number of MSR_K6_EFER_LMA */
1742/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1743#define MSR_K6_EFER_NXE RT_BIT_32(11)
1744#define MSR_K6_EFER_BIT_NXE 11 /**< Bit number of MSR_K6_EFER_NXE */
1745/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1746#define MSR_K6_EFER_SVME RT_BIT_32(12)
1747/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1748#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1749/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
1750#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1751/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1752#define MSR_K6_EFER_TCE RT_BIT_32(15)
1753/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
1754#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
1755
1756/** K6 STAR - SYSCALL/RET targets. */
1757#define MSR_K6_STAR UINT32_C(0xc0000081)
1758/** Shift value for getting the SYSRET CS and SS value. */
1759#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1760/** Shift value for getting the SYSCALL CS and SS value. */
1761#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1762/** Selector mask for use after shifting. */
1763#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1764/** The mask which give the SYSCALL EIP. */
1765#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1766/** K6 WHCR - Write Handling Control Register. */
1767#define MSR_K6_WHCR UINT32_C(0xc0000082)
1768/** K6 UWCCR - UC/WC Cacheability Control Register. */
1769#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1770/** K6 PSOR - Processor State Observability Register. */
1771#define MSR_K6_PSOR UINT32_C(0xc0000087)
1772/** K6 PFIR - Page Flush/Invalidate Register. */
1773#define MSR_K6_PFIR UINT32_C(0xc0000088)
1774
1775/** Performance counter MSRs. (AMD only) */
1776#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1777#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1778#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1779#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1780#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1781#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1782#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1783#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1784
1785/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1786#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1787/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1788#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1789/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1790#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1791/** K8 FS.base - The 64-bit base FS register. */
1792#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1793/** K8 GS.base - The 64-bit base GS register. */
1794#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1795/** K8 KernelGSbase - Used with SWAPGS. */
1796#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1797/** K8 TSC_AUX - Used with RDTSCP. */
1798#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1799#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1800#define MSR_K8_HWCR UINT32_C(0xc0010015)
1801#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1802#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1803#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1804#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1805#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1806#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1807/** North bridge config? See BIOS & Kernel dev guides for
1808 * details. */
1809#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1810
1811/** Hypertransport interrupt pending register.
1812 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1813#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1814
1815/** SVM Control. */
1816#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1817/** Disables HDT (Hardware Debug Tool) and certain internal debug
1818 * features. */
1819#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1820/** If set, non-intercepted INIT signals are converted to \#SX
1821 * exceptions. */
1822#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1823/** Disables A20 masking. */
1824#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1825/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1826#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1827/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1828 * clear, EFER.SVME can be written normally. */
1829#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1830
1831#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1832#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1833/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1834 * host state during world switch. */
1835#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1836
1837/** @} */
1838
1839
1840/** @name Page Table / Directory / Directory Pointers / L4.
1841 * @{
1842 */
1843
1844/** Page table/directory entry as an unsigned integer. */
1845typedef uint32_t X86PGUINT;
1846/** Pointer to a page table/directory table entry as an unsigned integer. */
1847typedef X86PGUINT *PX86PGUINT;
1848/** Pointer to an const page table/directory table entry as an unsigned integer. */
1849typedef X86PGUINT const *PCX86PGUINT;
1850
1851/** Number of entries in a 32-bit PT/PD. */
1852#define X86_PG_ENTRIES 1024
1853
1854
1855/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1856typedef uint64_t X86PGPAEUINT;
1857/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1858typedef X86PGPAEUINT *PX86PGPAEUINT;
1859/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1860typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1861
1862/** Number of entries in a PAE PT/PD. */
1863#define X86_PG_PAE_ENTRIES 512
1864/** Number of entries in a PAE PDPT. */
1865#define X86_PG_PAE_PDPE_ENTRIES 4
1866
1867/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1868#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1869/** Number of entries in an AMD64 PDPT.
1870 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1871#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1872
1873/** The size of a default page. */
1874#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1875/** The page shift of a default page. */
1876#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1877/** The default page offset mask. */
1878#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1879/** The default page base mask for virtual addresses. */
1880#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1881/** The default page base mask for virtual addresses - 32bit version. */
1882#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1883
1884/** The size of a 4KB page. */
1885#define X86_PAGE_4K_SIZE _4K
1886/** The page shift of a 4KB page. */
1887#define X86_PAGE_4K_SHIFT 12
1888/** The 4KB page offset mask. */
1889#define X86_PAGE_4K_OFFSET_MASK 0xfff
1890/** The 4KB page base mask for virtual addresses. */
1891#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1892/** The 4KB page base mask for virtual addresses - 32bit version. */
1893#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1894
1895/** The size of a 2MB page. */
1896#define X86_PAGE_2M_SIZE _2M
1897/** The page shift of a 2MB page. */
1898#define X86_PAGE_2M_SHIFT 21
1899/** The 2MB page offset mask. */
1900#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1901/** The 2MB page base mask for virtual addresses. */
1902#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1903/** The 2MB page base mask for virtual addresses - 32bit version. */
1904#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1905
1906/** The size of a 4MB page. */
1907#define X86_PAGE_4M_SIZE _4M
1908/** The page shift of a 4MB page. */
1909#define X86_PAGE_4M_SHIFT 22
1910/** The 4MB page offset mask. */
1911#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1912/** The 4MB page base mask for virtual addresses. */
1913#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1914/** The 4MB page base mask for virtual addresses - 32bit version. */
1915#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1916
1917/** The size of a 1GB page. */
1918#define X86_PAGE_1G_SIZE _1G
1919/** The page shift of a 1GB page. */
1920#define X86_PAGE_1G_SHIFT 30
1921/** The 1GB page offset mask. */
1922#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
1923/** The 1GB page base mask for virtual addresses. */
1924#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
1925
1926/**
1927 * Check if the given address is canonical.
1928 */
1929#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1930
1931
1932/** @name Page Table Entry
1933 * @{
1934 */
1935/** Bit 0 - P - Present bit. */
1936#define X86_PTE_BIT_P 0
1937/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1938#define X86_PTE_BIT_RW 1
1939/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1940#define X86_PTE_BIT_US 2
1941/** Bit 3 - PWT - Page level write thru bit. */
1942#define X86_PTE_BIT_PWT 3
1943/** Bit 4 - PCD - Page level cache disable bit. */
1944#define X86_PTE_BIT_PCD 4
1945/** Bit 5 - A - Access bit. */
1946#define X86_PTE_BIT_A 5
1947/** Bit 6 - D - Dirty bit. */
1948#define X86_PTE_BIT_D 6
1949/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1950#define X86_PTE_BIT_PAT 7
1951/** Bit 8 - G - Global flag. */
1952#define X86_PTE_BIT_G 8
1953/** Bits 63 - NX - PAE/LM - No execution flag. */
1954#define X86_PTE_PAE_BIT_NX 63
1955
1956/** Bit 0 - P - Present bit mask. */
1957#define X86_PTE_P RT_BIT_32(0)
1958/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1959#define X86_PTE_RW RT_BIT_32(1)
1960/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
1961#define X86_PTE_US RT_BIT_32(2)
1962/** Bit 3 - PWT - Page level write thru bit mask. */
1963#define X86_PTE_PWT RT_BIT_32(3)
1964/** Bit 4 - PCD - Page level cache disable bit mask. */
1965#define X86_PTE_PCD RT_BIT_32(4)
1966/** Bit 5 - A - Access bit mask. */
1967#define X86_PTE_A RT_BIT_32(5)
1968/** Bit 6 - D - Dirty bit mask. */
1969#define X86_PTE_D RT_BIT_32(6)
1970/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
1971#define X86_PTE_PAT RT_BIT_32(7)
1972/** Bit 8 - G - Global bit mask. */
1973#define X86_PTE_G RT_BIT_32(8)
1974
1975/** Bits 9-11 - - Available for use to system software. */
1976#define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1977/** Bits 12-31 - - Physical Page number of the next level. */
1978#define X86_PTE_PG_MASK ( 0xfffff000 )
1979
1980/** Bits 12-51 - - PAE - Physical Page number of the next level. */
1981#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
1982/** Bits 63 - NX - PAE/LM - No execution flag. */
1983#define X86_PTE_PAE_NX RT_BIT_64(63)
1984/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
1985#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
1986/** Bits 63-52 - - PAE - MBZ bits when no NX. */
1987#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
1988/** No bits - - LM - MBZ bits when NX is active. */
1989#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
1990/** Bits 63 - - LM - MBZ bits when no NX. */
1991#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
1992
1993/**
1994 * Page table entry.
1995 */
1996typedef struct X86PTEBITS
1997{
1998 /** Flags whether(=1) or not the page is present. */
1999 uint32_t u1Present : 1;
2000 /** Read(=0) / Write(=1) flag. */
2001 uint32_t u1Write : 1;
2002 /** User(=1) / Supervisor (=0) flag. */
2003 uint32_t u1User : 1;
2004 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2005 uint32_t u1WriteThru : 1;
2006 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2007 uint32_t u1CacheDisable : 1;
2008 /** Accessed flag.
2009 * Indicates that the page have been read or written to. */
2010 uint32_t u1Accessed : 1;
2011 /** Dirty flag.
2012 * Indicates that the page has been written to. */
2013 uint32_t u1Dirty : 1;
2014 /** Reserved / If PAT enabled, bit 2 of the index. */
2015 uint32_t u1PAT : 1;
2016 /** Global flag. (Ignored in all but final level.) */
2017 uint32_t u1Global : 1;
2018 /** Available for use to system software. */
2019 uint32_t u3Available : 3;
2020 /** Physical Page number of the next level. */
2021 uint32_t u20PageNo : 20;
2022} X86PTEBITS;
2023#ifndef VBOX_FOR_DTRACE_LIB
2024AssertCompileSize(X86PTEBITS, 4);
2025#endif
2026/** Pointer to a page table entry. */
2027typedef X86PTEBITS *PX86PTEBITS;
2028/** Pointer to a const page table entry. */
2029typedef const X86PTEBITS *PCX86PTEBITS;
2030
2031/**
2032 * Page table entry.
2033 */
2034typedef union X86PTE
2035{
2036 /** Unsigned integer view */
2037 X86PGUINT u;
2038 /** Bit field view. */
2039 X86PTEBITS n;
2040 /** 32-bit view. */
2041 uint32_t au32[1];
2042 /** 16-bit view. */
2043 uint16_t au16[2];
2044 /** 8-bit view. */
2045 uint8_t au8[4];
2046} X86PTE;
2047#ifndef VBOX_FOR_DTRACE_LIB
2048AssertCompileSize(X86PTE, 4);
2049#endif
2050/** Pointer to a page table entry. */
2051typedef X86PTE *PX86PTE;
2052/** Pointer to a const page table entry. */
2053typedef const X86PTE *PCX86PTE;
2054
2055
2056/**
2057 * PAE page table entry.
2058 */
2059typedef struct X86PTEPAEBITS
2060{
2061 /** Flags whether(=1) or not the page is present. */
2062 uint32_t u1Present : 1;
2063 /** Read(=0) / Write(=1) flag. */
2064 uint32_t u1Write : 1;
2065 /** User(=1) / Supervisor(=0) flag. */
2066 uint32_t u1User : 1;
2067 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2068 uint32_t u1WriteThru : 1;
2069 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2070 uint32_t u1CacheDisable : 1;
2071 /** Accessed flag.
2072 * Indicates that the page have been read or written to. */
2073 uint32_t u1Accessed : 1;
2074 /** Dirty flag.
2075 * Indicates that the page has been written to. */
2076 uint32_t u1Dirty : 1;
2077 /** Reserved / If PAT enabled, bit 2 of the index. */
2078 uint32_t u1PAT : 1;
2079 /** Global flag. (Ignored in all but final level.) */
2080 uint32_t u1Global : 1;
2081 /** Available for use to system software. */
2082 uint32_t u3Available : 3;
2083 /** Physical Page number of the next level - Low Part. Don't use this. */
2084 uint32_t u20PageNoLow : 20;
2085 /** Physical Page number of the next level - High Part. Don't use this. */
2086 uint32_t u20PageNoHigh : 20;
2087 /** MBZ bits */
2088 uint32_t u11Reserved : 11;
2089 /** No Execute flag. */
2090 uint32_t u1NoExecute : 1;
2091} X86PTEPAEBITS;
2092#ifndef VBOX_FOR_DTRACE_LIB
2093AssertCompileSize(X86PTEPAEBITS, 8);
2094#endif
2095/** Pointer to a page table entry. */
2096typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2097/** Pointer to a page table entry. */
2098typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2099
2100/**
2101 * PAE Page table entry.
2102 */
2103typedef union X86PTEPAE
2104{
2105 /** Unsigned integer view */
2106 X86PGPAEUINT u;
2107 /** Bit field view. */
2108 X86PTEPAEBITS n;
2109 /** 32-bit view. */
2110 uint32_t au32[2];
2111 /** 16-bit view. */
2112 uint16_t au16[4];
2113 /** 8-bit view. */
2114 uint8_t au8[8];
2115} X86PTEPAE;
2116#ifndef VBOX_FOR_DTRACE_LIB
2117AssertCompileSize(X86PTEPAE, 8);
2118#endif
2119/** Pointer to a PAE page table entry. */
2120typedef X86PTEPAE *PX86PTEPAE;
2121/** Pointer to a const PAE page table entry. */
2122typedef const X86PTEPAE *PCX86PTEPAE;
2123/** @} */
2124
2125/**
2126 * Page table.
2127 */
2128typedef struct X86PT
2129{
2130 /** PTE Array. */
2131 X86PTE a[X86_PG_ENTRIES];
2132} X86PT;
2133#ifndef VBOX_FOR_DTRACE_LIB
2134AssertCompileSize(X86PT, 4096);
2135#endif
2136/** Pointer to a page table. */
2137typedef X86PT *PX86PT;
2138/** Pointer to a const page table. */
2139typedef const X86PT *PCX86PT;
2140
2141/** The page shift to get the PT index. */
2142#define X86_PT_SHIFT 12
2143/** The PT index mask (apply to a shifted page address). */
2144#define X86_PT_MASK 0x3ff
2145
2146
2147/**
2148 * Page directory.
2149 */
2150typedef struct X86PTPAE
2151{
2152 /** PTE Array. */
2153 X86PTEPAE a[X86_PG_PAE_ENTRIES];
2154} X86PTPAE;
2155#ifndef VBOX_FOR_DTRACE_LIB
2156AssertCompileSize(X86PTPAE, 4096);
2157#endif
2158/** Pointer to a page table. */
2159typedef X86PTPAE *PX86PTPAE;
2160/** Pointer to a const page table. */
2161typedef const X86PTPAE *PCX86PTPAE;
2162
2163/** The page shift to get the PA PTE index. */
2164#define X86_PT_PAE_SHIFT 12
2165/** The PAE PT index mask (apply to a shifted page address). */
2166#define X86_PT_PAE_MASK 0x1ff
2167
2168
2169/** @name 4KB Page Directory Entry
2170 * @{
2171 */
2172/** Bit 0 - P - Present bit. */
2173#define X86_PDE_P RT_BIT_32(0)
2174/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2175#define X86_PDE_RW RT_BIT_32(1)
2176/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2177#define X86_PDE_US RT_BIT_32(2)
2178/** Bit 3 - PWT - Page level write thru bit. */
2179#define X86_PDE_PWT RT_BIT_32(3)
2180/** Bit 4 - PCD - Page level cache disable bit. */
2181#define X86_PDE_PCD RT_BIT_32(4)
2182/** Bit 5 - A - Access bit. */
2183#define X86_PDE_A RT_BIT_32(5)
2184/** Bit 7 - PS - Page size attribute.
2185 * Clear mean 4KB pages, set means large pages (2/4MB). */
2186#define X86_PDE_PS RT_BIT_32(7)
2187/** Bits 9-11 - - Available for use to system software. */
2188#define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2189/** Bits 12-31 - - Physical Page number of the next level. */
2190#define X86_PDE_PG_MASK ( 0xfffff000 )
2191
2192/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2193#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2194/** Bits 63 - NX - PAE/LM - No execution flag. */
2195#define X86_PDE_PAE_NX RT_BIT_64(63)
2196/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2197#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2198/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2199#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2200/** Bit 7 - - LM - MBZ bits when NX is active. */
2201#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2202/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2203#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2204
2205/**
2206 * Page directory entry.
2207 */
2208typedef struct X86PDEBITS
2209{
2210 /** Flags whether(=1) or not the page is present. */
2211 uint32_t u1Present : 1;
2212 /** Read(=0) / Write(=1) flag. */
2213 uint32_t u1Write : 1;
2214 /** User(=1) / Supervisor (=0) flag. */
2215 uint32_t u1User : 1;
2216 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2217 uint32_t u1WriteThru : 1;
2218 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2219 uint32_t u1CacheDisable : 1;
2220 /** Accessed flag.
2221 * Indicates that the page has been read or written to. */
2222 uint32_t u1Accessed : 1;
2223 /** Reserved / Ignored (dirty bit). */
2224 uint32_t u1Reserved0 : 1;
2225 /** Size bit if PSE is enabled - in any event it's 0. */
2226 uint32_t u1Size : 1;
2227 /** Reserved / Ignored (global bit). */
2228 uint32_t u1Reserved1 : 1;
2229 /** Available for use to system software. */
2230 uint32_t u3Available : 3;
2231 /** Physical Page number of the next level. */
2232 uint32_t u20PageNo : 20;
2233} X86PDEBITS;
2234#ifndef VBOX_FOR_DTRACE_LIB
2235AssertCompileSize(X86PDEBITS, 4);
2236#endif
2237/** Pointer to a page directory entry. */
2238typedef X86PDEBITS *PX86PDEBITS;
2239/** Pointer to a const page directory entry. */
2240typedef const X86PDEBITS *PCX86PDEBITS;
2241
2242
2243/**
2244 * PAE page directory entry.
2245 */
2246typedef struct X86PDEPAEBITS
2247{
2248 /** Flags whether(=1) or not the page is present. */
2249 uint32_t u1Present : 1;
2250 /** Read(=0) / Write(=1) flag. */
2251 uint32_t u1Write : 1;
2252 /** User(=1) / Supervisor (=0) flag. */
2253 uint32_t u1User : 1;
2254 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2255 uint32_t u1WriteThru : 1;
2256 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2257 uint32_t u1CacheDisable : 1;
2258 /** Accessed flag.
2259 * Indicates that the page has been read or written to. */
2260 uint32_t u1Accessed : 1;
2261 /** Reserved / Ignored (dirty bit). */
2262 uint32_t u1Reserved0 : 1;
2263 /** Size bit if PSE is enabled - in any event it's 0. */
2264 uint32_t u1Size : 1;
2265 /** Reserved / Ignored (global bit). / */
2266 uint32_t u1Reserved1 : 1;
2267 /** Available for use to system software. */
2268 uint32_t u3Available : 3;
2269 /** Physical Page number of the next level - Low Part. Don't use! */
2270 uint32_t u20PageNoLow : 20;
2271 /** Physical Page number of the next level - High Part. Don't use! */
2272 uint32_t u20PageNoHigh : 20;
2273 /** MBZ bits */
2274 uint32_t u11Reserved : 11;
2275 /** No Execute flag. */
2276 uint32_t u1NoExecute : 1;
2277} X86PDEPAEBITS;
2278#ifndef VBOX_FOR_DTRACE_LIB
2279AssertCompileSize(X86PDEPAEBITS, 8);
2280#endif
2281/** Pointer to a page directory entry. */
2282typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2283/** Pointer to a const page directory entry. */
2284typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2285
2286/** @} */
2287
2288
2289/** @name 2/4MB Page Directory Entry
2290 * @{
2291 */
2292/** Bit 0 - P - Present bit. */
2293#define X86_PDE4M_P RT_BIT_32(0)
2294/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2295#define X86_PDE4M_RW RT_BIT_32(1)
2296/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2297#define X86_PDE4M_US RT_BIT_32(2)
2298/** Bit 3 - PWT - Page level write thru bit. */
2299#define X86_PDE4M_PWT RT_BIT_32(3)
2300/** Bit 4 - PCD - Page level cache disable bit. */
2301#define X86_PDE4M_PCD RT_BIT_32(4)
2302/** Bit 5 - A - Access bit. */
2303#define X86_PDE4M_A RT_BIT_32(5)
2304/** Bit 6 - D - Dirty bit. */
2305#define X86_PDE4M_D RT_BIT_32(6)
2306/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2307#define X86_PDE4M_PS RT_BIT_32(7)
2308/** Bit 8 - G - Global flag. */
2309#define X86_PDE4M_G RT_BIT_32(8)
2310/** Bits 9-11 - AVL - Available for use to system software. */
2311#define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2312/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2313#define X86_PDE4M_PAT RT_BIT_32(12)
2314/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2315#define X86_PDE4M_PAT_SHIFT (12 - 7)
2316/** Bits 22-31 - - Physical Page number. */
2317#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2318/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2319#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2320/** The number of bits to the high part of the page number. */
2321#define X86_PDE4M_PG_HIGH_SHIFT 19
2322/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2323#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2324
2325/** Bits 21-51 - - PAE/LM - Physical Page number.
2326 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2327#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2328/** Bits 63 - NX - PAE/LM - No execution flag. */
2329#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2330/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2331#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2332/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2333#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2334/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2335#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2336/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2337#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2338
2339/**
2340 * 4MB page directory entry.
2341 */
2342typedef struct X86PDE4MBITS
2343{
2344 /** Flags whether(=1) or not the page is present. */
2345 uint32_t u1Present : 1;
2346 /** Read(=0) / Write(=1) flag. */
2347 uint32_t u1Write : 1;
2348 /** User(=1) / Supervisor (=0) flag. */
2349 uint32_t u1User : 1;
2350 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2351 uint32_t u1WriteThru : 1;
2352 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2353 uint32_t u1CacheDisable : 1;
2354 /** Accessed flag.
2355 * Indicates that the page have been read or written to. */
2356 uint32_t u1Accessed : 1;
2357 /** Dirty flag.
2358 * Indicates that the page has been written to. */
2359 uint32_t u1Dirty : 1;
2360 /** Page size flag - always 1 for 4MB entries. */
2361 uint32_t u1Size : 1;
2362 /** Global flag. */
2363 uint32_t u1Global : 1;
2364 /** Available for use to system software. */
2365 uint32_t u3Available : 3;
2366 /** Reserved / If PAT enabled, bit 2 of the index. */
2367 uint32_t u1PAT : 1;
2368 /** Bits 32-39 of the page number on AMD64.
2369 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2370 uint32_t u8PageNoHigh : 8;
2371 /** Reserved. */
2372 uint32_t u1Reserved : 1;
2373 /** Physical Page number of the page. */
2374 uint32_t u10PageNo : 10;
2375} X86PDE4MBITS;
2376#ifndef VBOX_FOR_DTRACE_LIB
2377AssertCompileSize(X86PDE4MBITS, 4);
2378#endif
2379/** Pointer to a page table entry. */
2380typedef X86PDE4MBITS *PX86PDE4MBITS;
2381/** Pointer to a const page table entry. */
2382typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2383
2384
2385/**
2386 * 2MB PAE page directory entry.
2387 */
2388typedef struct X86PDE2MPAEBITS
2389{
2390 /** Flags whether(=1) or not the page is present. */
2391 uint32_t u1Present : 1;
2392 /** Read(=0) / Write(=1) flag. */
2393 uint32_t u1Write : 1;
2394 /** User(=1) / Supervisor(=0) flag. */
2395 uint32_t u1User : 1;
2396 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2397 uint32_t u1WriteThru : 1;
2398 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2399 uint32_t u1CacheDisable : 1;
2400 /** Accessed flag.
2401 * Indicates that the page have been read or written to. */
2402 uint32_t u1Accessed : 1;
2403 /** Dirty flag.
2404 * Indicates that the page has been written to. */
2405 uint32_t u1Dirty : 1;
2406 /** Page size flag - always 1 for 2MB entries. */
2407 uint32_t u1Size : 1;
2408 /** Global flag. */
2409 uint32_t u1Global : 1;
2410 /** Available for use to system software. */
2411 uint32_t u3Available : 3;
2412 /** Reserved / If PAT enabled, bit 2 of the index. */
2413 uint32_t u1PAT : 1;
2414 /** Reserved. */
2415 uint32_t u9Reserved : 9;
2416 /** Physical Page number of the next level - Low part. Don't use! */
2417 uint32_t u10PageNoLow : 10;
2418 /** Physical Page number of the next level - High part. Don't use! */
2419 uint32_t u20PageNoHigh : 20;
2420 /** MBZ bits */
2421 uint32_t u11Reserved : 11;
2422 /** No Execute flag. */
2423 uint32_t u1NoExecute : 1;
2424} X86PDE2MPAEBITS;
2425#ifndef VBOX_FOR_DTRACE_LIB
2426AssertCompileSize(X86PDE2MPAEBITS, 8);
2427#endif
2428/** Pointer to a 2MB PAE page table entry. */
2429typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2430/** Pointer to a 2MB PAE page table entry. */
2431typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2432
2433/** @} */
2434
2435/**
2436 * Page directory entry.
2437 */
2438typedef union X86PDE
2439{
2440 /** Unsigned integer view. */
2441 X86PGUINT u;
2442 /** Normal view. */
2443 X86PDEBITS n;
2444 /** 4MB view (big). */
2445 X86PDE4MBITS b;
2446 /** 8 bit unsigned integer view. */
2447 uint8_t au8[4];
2448 /** 16 bit unsigned integer view. */
2449 uint16_t au16[2];
2450 /** 32 bit unsigned integer view. */
2451 uint32_t au32[1];
2452} X86PDE;
2453#ifndef VBOX_FOR_DTRACE_LIB
2454AssertCompileSize(X86PDE, 4);
2455#endif
2456/** Pointer to a page directory entry. */
2457typedef X86PDE *PX86PDE;
2458/** Pointer to a const page directory entry. */
2459typedef const X86PDE *PCX86PDE;
2460
2461/**
2462 * PAE page directory entry.
2463 */
2464typedef union X86PDEPAE
2465{
2466 /** Unsigned integer view. */
2467 X86PGPAEUINT u;
2468 /** Normal view. */
2469 X86PDEPAEBITS n;
2470 /** 2MB page view (big). */
2471 X86PDE2MPAEBITS b;
2472 /** 8 bit unsigned integer view. */
2473 uint8_t au8[8];
2474 /** 16 bit unsigned integer view. */
2475 uint16_t au16[4];
2476 /** 32 bit unsigned integer view. */
2477 uint32_t au32[2];
2478} X86PDEPAE;
2479#ifndef VBOX_FOR_DTRACE_LIB
2480AssertCompileSize(X86PDEPAE, 8);
2481#endif
2482/** Pointer to a page directory entry. */
2483typedef X86PDEPAE *PX86PDEPAE;
2484/** Pointer to a const page directory entry. */
2485typedef const X86PDEPAE *PCX86PDEPAE;
2486
2487/**
2488 * Page directory.
2489 */
2490typedef struct X86PD
2491{
2492 /** PDE Array. */
2493 X86PDE a[X86_PG_ENTRIES];
2494} X86PD;
2495#ifndef VBOX_FOR_DTRACE_LIB
2496AssertCompileSize(X86PD, 4096);
2497#endif
2498/** Pointer to a page directory. */
2499typedef X86PD *PX86PD;
2500/** Pointer to a const page directory. */
2501typedef const X86PD *PCX86PD;
2502
2503/** The page shift to get the PD index. */
2504#define X86_PD_SHIFT 22
2505/** The PD index mask (apply to a shifted page address). */
2506#define X86_PD_MASK 0x3ff
2507
2508
2509/**
2510 * PAE page directory.
2511 */
2512typedef struct X86PDPAE
2513{
2514 /** PDE Array. */
2515 X86PDEPAE a[X86_PG_PAE_ENTRIES];
2516} X86PDPAE;
2517#ifndef VBOX_FOR_DTRACE_LIB
2518AssertCompileSize(X86PDPAE, 4096);
2519#endif
2520/** Pointer to a PAE page directory. */
2521typedef X86PDPAE *PX86PDPAE;
2522/** Pointer to a const PAE page directory. */
2523typedef const X86PDPAE *PCX86PDPAE;
2524
2525/** The page shift to get the PAE PD index. */
2526#define X86_PD_PAE_SHIFT 21
2527/** The PAE PD index mask (apply to a shifted page address). */
2528#define X86_PD_PAE_MASK 0x1ff
2529
2530
2531/** @name Page Directory Pointer Table Entry (PAE)
2532 * @{
2533 */
2534/** Bit 0 - P - Present bit. */
2535#define X86_PDPE_P RT_BIT_32(0)
2536/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2537#define X86_PDPE_RW RT_BIT_32(1)
2538/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2539#define X86_PDPE_US RT_BIT_32(2)
2540/** Bit 3 - PWT - Page level write thru bit. */
2541#define X86_PDPE_PWT RT_BIT_32(3)
2542/** Bit 4 - PCD - Page level cache disable bit. */
2543#define X86_PDPE_PCD RT_BIT_32(4)
2544/** Bit 5 - A - Access bit. Long Mode only. */
2545#define X86_PDPE_A RT_BIT_32(5)
2546/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2547#define X86_PDPE_LM_PS RT_BIT_32(7)
2548/** Bits 9-11 - - Available for use to system software. */
2549#define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2550/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2551#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2552/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2553#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2554/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2555#define X86_PDPE_LM_NX RT_BIT_64(63)
2556/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2557#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2558/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2559#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2560/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2561#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2562/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2563#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2564
2565
2566/**
2567 * Page directory pointer table entry.
2568 */
2569typedef struct X86PDPEBITS
2570{
2571 /** Flags whether(=1) or not the page is present. */
2572 uint32_t u1Present : 1;
2573 /** Chunk of reserved bits. */
2574 uint32_t u2Reserved : 2;
2575 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2576 uint32_t u1WriteThru : 1;
2577 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2578 uint32_t u1CacheDisable : 1;
2579 /** Chunk of reserved bits. */
2580 uint32_t u4Reserved : 4;
2581 /** Available for use to system software. */
2582 uint32_t u3Available : 3;
2583 /** Physical Page number of the next level - Low Part. Don't use! */
2584 uint32_t u20PageNoLow : 20;
2585 /** Physical Page number of the next level - High Part. Don't use! */
2586 uint32_t u20PageNoHigh : 20;
2587 /** MBZ bits */
2588 uint32_t u12Reserved : 12;
2589} X86PDPEBITS;
2590#ifndef VBOX_FOR_DTRACE_LIB
2591AssertCompileSize(X86PDPEBITS, 8);
2592#endif
2593/** Pointer to a page directory pointer table entry. */
2594typedef X86PDPEBITS *PX86PTPEBITS;
2595/** Pointer to a const page directory pointer table entry. */
2596typedef const X86PDPEBITS *PCX86PTPEBITS;
2597
2598/**
2599 * Page directory pointer table entry. AMD64 version
2600 */
2601typedef struct X86PDPEAMD64BITS
2602{
2603 /** Flags whether(=1) or not the page is present. */
2604 uint32_t u1Present : 1;
2605 /** Read(=0) / Write(=1) flag. */
2606 uint32_t u1Write : 1;
2607 /** User(=1) / Supervisor (=0) flag. */
2608 uint32_t u1User : 1;
2609 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2610 uint32_t u1WriteThru : 1;
2611 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2612 uint32_t u1CacheDisable : 1;
2613 /** Accessed flag.
2614 * Indicates that the page have been read or written to. */
2615 uint32_t u1Accessed : 1;
2616 /** Chunk of reserved bits. */
2617 uint32_t u3Reserved : 3;
2618 /** Available for use to system software. */
2619 uint32_t u3Available : 3;
2620 /** Physical Page number of the next level - Low Part. Don't use! */
2621 uint32_t u20PageNoLow : 20;
2622 /** Physical Page number of the next level - High Part. Don't use! */
2623 uint32_t u20PageNoHigh : 20;
2624 /** MBZ bits */
2625 uint32_t u11Reserved : 11;
2626 /** No Execute flag. */
2627 uint32_t u1NoExecute : 1;
2628} X86PDPEAMD64BITS;
2629#ifndef VBOX_FOR_DTRACE_LIB
2630AssertCompileSize(X86PDPEAMD64BITS, 8);
2631#endif
2632/** Pointer to a page directory pointer table entry. */
2633typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2634/** Pointer to a const page directory pointer table entry. */
2635typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2636
2637/**
2638 * Page directory pointer table entry for 1GB page. (AMD64 only)
2639 */
2640typedef struct X86PDPE1GB
2641{
2642 /** 0: Flags whether(=1) or not the page is present. */
2643 uint32_t u1Present : 1;
2644 /** 1: Read(=0) / Write(=1) flag. */
2645 uint32_t u1Write : 1;
2646 /** 2: User(=1) / Supervisor (=0) flag. */
2647 uint32_t u1User : 1;
2648 /** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2649 uint32_t u1WriteThru : 1;
2650 /** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2651 uint32_t u1CacheDisable : 1;
2652 /** 5: Accessed flag.
2653 * Indicates that the page have been read or written to. */
2654 uint32_t u1Accessed : 1;
2655 /** 6: Dirty flag for 1GB pages. */
2656 uint32_t u1Dirty : 1;
2657 /** 7: Indicates 1GB page if set. */
2658 uint32_t u1Size : 1;
2659 /** 8: Global 1GB page. */
2660 uint32_t u1Global: 1;
2661 /** 9-11: Available for use to system software. */
2662 uint32_t u3Available : 3;
2663 /** 12: PAT bit for 1GB page. */
2664 uint32_t u1PAT : 1;
2665 /** 13-29: MBZ bits. */
2666 uint32_t u17Reserved : 17;
2667 /** 30-31: Physical page number - Low Part. Don't use! */
2668 uint32_t u2PageNoLow : 2;
2669 /** 32-51: Physical Page number of the next level - High Part. Don't use! */
2670 uint32_t u20PageNoHigh : 20;
2671 /** 52-62: MBZ bits */
2672 uint32_t u11Reserved : 11;
2673 /** 63: No Execute flag. */
2674 uint32_t u1NoExecute : 1;
2675} X86PDPE1GB;
2676#ifndef VBOX_FOR_DTRACE_LIB
2677AssertCompileSize(X86PDPE1GB, 8);
2678#endif
2679/** Pointer to a page directory pointer table entry for a 1GB page. */
2680typedef X86PDPE1GB *PX86PDPE1GB;
2681/** Pointer to a const page directory pointer table entry for a 1GB page. */
2682typedef const X86PDPE1GB *PCX86PDPE1GB;
2683
2684/**
2685 * Page directory pointer table entry.
2686 */
2687typedef union X86PDPE
2688{
2689 /** Unsigned integer view. */
2690 X86PGPAEUINT u;
2691 /** Normal view. */
2692 X86PDPEBITS n;
2693 /** AMD64 view. */
2694 X86PDPEAMD64BITS lm;
2695 /** AMD64 big view. */
2696 X86PDPE1GB b;
2697 /** 8 bit unsigned integer view. */
2698 uint8_t au8[8];
2699 /** 16 bit unsigned integer view. */
2700 uint16_t au16[4];
2701 /** 32 bit unsigned integer view. */
2702 uint32_t au32[2];
2703} X86PDPE;
2704#ifndef VBOX_FOR_DTRACE_LIB
2705AssertCompileSize(X86PDPE, 8);
2706#endif
2707/** Pointer to a page directory pointer table entry. */
2708typedef X86PDPE *PX86PDPE;
2709/** Pointer to a const page directory pointer table entry. */
2710typedef const X86PDPE *PCX86PDPE;
2711
2712
2713/**
2714 * Page directory pointer table.
2715 */
2716typedef struct X86PDPT
2717{
2718 /** PDE Array. */
2719 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2720} X86PDPT;
2721#ifndef VBOX_FOR_DTRACE_LIB
2722AssertCompileSize(X86PDPT, 4096);
2723#endif
2724/** Pointer to a page directory pointer table. */
2725typedef X86PDPT *PX86PDPT;
2726/** Pointer to a const page directory pointer table. */
2727typedef const X86PDPT *PCX86PDPT;
2728
2729/** The page shift to get the PDPT index. */
2730#define X86_PDPT_SHIFT 30
2731/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2732#define X86_PDPT_MASK_PAE 0x3
2733/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2734#define X86_PDPT_MASK_AMD64 0x1ff
2735
2736/** @} */
2737
2738
2739/** @name Page Map Level-4 Entry (Long Mode PAE)
2740 * @{
2741 */
2742/** Bit 0 - P - Present bit. */
2743#define X86_PML4E_P RT_BIT_32(0)
2744/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2745#define X86_PML4E_RW RT_BIT_32(1)
2746/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2747#define X86_PML4E_US RT_BIT_32(2)
2748/** Bit 3 - PWT - Page level write thru bit. */
2749#define X86_PML4E_PWT RT_BIT_32(3)
2750/** Bit 4 - PCD - Page level cache disable bit. */
2751#define X86_PML4E_PCD RT_BIT_32(4)
2752/** Bit 5 - A - Access bit. */
2753#define X86_PML4E_A RT_BIT_32(5)
2754/** Bits 9-11 - - Available for use to system software. */
2755#define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2756/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2757#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2758/** Bits 8, 7 - - MBZ bits when NX is active. */
2759#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2760/** Bits 63, 7 - - MBZ bits when no NX. */
2761#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2762/** Bits 63 - NX - PAE - No execution flag. */
2763#define X86_PML4E_NX RT_BIT_64(63)
2764
2765/**
2766 * Page Map Level-4 Entry
2767 */
2768typedef struct X86PML4EBITS
2769{
2770 /** Flags whether(=1) or not the page is present. */
2771 uint32_t u1Present : 1;
2772 /** Read(=0) / Write(=1) flag. */
2773 uint32_t u1Write : 1;
2774 /** User(=1) / Supervisor (=0) flag. */
2775 uint32_t u1User : 1;
2776 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2777 uint32_t u1WriteThru : 1;
2778 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2779 uint32_t u1CacheDisable : 1;
2780 /** Accessed flag.
2781 * Indicates that the page have been read or written to. */
2782 uint32_t u1Accessed : 1;
2783 /** Chunk of reserved bits. */
2784 uint32_t u3Reserved : 3;
2785 /** Available for use to system software. */
2786 uint32_t u3Available : 3;
2787 /** Physical Page number of the next level - Low Part. Don't use! */
2788 uint32_t u20PageNoLow : 20;
2789 /** Physical Page number of the next level - High Part. Don't use! */
2790 uint32_t u20PageNoHigh : 20;
2791 /** MBZ bits */
2792 uint32_t u11Reserved : 11;
2793 /** No Execute flag. */
2794 uint32_t u1NoExecute : 1;
2795} X86PML4EBITS;
2796#ifndef VBOX_FOR_DTRACE_LIB
2797AssertCompileSize(X86PML4EBITS, 8);
2798#endif
2799/** Pointer to a page map level-4 entry. */
2800typedef X86PML4EBITS *PX86PML4EBITS;
2801/** Pointer to a const page map level-4 entry. */
2802typedef const X86PML4EBITS *PCX86PML4EBITS;
2803
2804/**
2805 * Page Map Level-4 Entry.
2806 */
2807typedef union X86PML4E
2808{
2809 /** Unsigned integer view. */
2810 X86PGPAEUINT u;
2811 /** Normal view. */
2812 X86PML4EBITS n;
2813 /** 8 bit unsigned integer view. */
2814 uint8_t au8[8];
2815 /** 16 bit unsigned integer view. */
2816 uint16_t au16[4];
2817 /** 32 bit unsigned integer view. */
2818 uint32_t au32[2];
2819} X86PML4E;
2820#ifndef VBOX_FOR_DTRACE_LIB
2821AssertCompileSize(X86PML4E, 8);
2822#endif
2823/** Pointer to a page map level-4 entry. */
2824typedef X86PML4E *PX86PML4E;
2825/** Pointer to a const page map level-4 entry. */
2826typedef const X86PML4E *PCX86PML4E;
2827
2828
2829/**
2830 * Page Map Level-4.
2831 */
2832typedef struct X86PML4
2833{
2834 /** PDE Array. */
2835 X86PML4E a[X86_PG_PAE_ENTRIES];
2836} X86PML4;
2837#ifndef VBOX_FOR_DTRACE_LIB
2838AssertCompileSize(X86PML4, 4096);
2839#endif
2840/** Pointer to a page map level-4. */
2841typedef X86PML4 *PX86PML4;
2842/** Pointer to a const page map level-4. */
2843typedef const X86PML4 *PCX86PML4;
2844
2845/** The page shift to get the PML4 index. */
2846#define X86_PML4_SHIFT 39
2847/** The PML4 index mask (apply to a shifted page address). */
2848#define X86_PML4_MASK 0x1ff
2849
2850/** @} */
2851
2852/** @} */
2853
2854/**
2855 * Intel PCID invalidation types.
2856 */
2857/** Individual address invalidation. */
2858#define X86_INVPCID_TYPE_INDV_ADDR 0
2859/** Single-context invalidation. */
2860#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
2861/** All-context including globals invalidation. */
2862#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
2863/** All-context excluding globals invalidation. */
2864#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
2865/** The maximum valid invalidation type value. */
2866#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
2867
2868/**
2869 * 32-bit protected mode FSTENV image.
2870 */
2871typedef struct X86FSTENV32P
2872{
2873 uint16_t FCW;
2874 uint16_t padding1;
2875 uint16_t FSW;
2876 uint16_t padding2;
2877 uint16_t FTW;
2878 uint16_t padding3;
2879 uint32_t FPUIP;
2880 uint16_t FPUCS;
2881 uint16_t FOP;
2882 uint32_t FPUDP;
2883 uint16_t FPUDS;
2884 uint16_t padding4;
2885} X86FSTENV32P;
2886/** Pointer to a 32-bit protected mode FSTENV image. */
2887typedef X86FSTENV32P *PX86FSTENV32P;
2888/** Pointer to a const 32-bit protected mode FSTENV image. */
2889typedef X86FSTENV32P const *PCX86FSTENV32P;
2890
2891
2892/**
2893 * 80-bit MMX/FPU register type.
2894 */
2895typedef struct X86FPUMMX
2896{
2897 uint8_t reg[10];
2898} X86FPUMMX;
2899#ifndef VBOX_FOR_DTRACE_LIB
2900AssertCompileSize(X86FPUMMX, 10);
2901#endif
2902/** Pointer to a 80-bit MMX/FPU register type. */
2903typedef X86FPUMMX *PX86FPUMMX;
2904/** Pointer to a const 80-bit MMX/FPU register type. */
2905typedef const X86FPUMMX *PCX86FPUMMX;
2906
2907/** FPU (x87) register. */
2908typedef union X86FPUREG
2909{
2910 /** MMX view. */
2911 uint64_t mmx;
2912 /** FPU view - todo. */
2913 X86FPUMMX fpu;
2914 /** Extended precision floating point view. */
2915 RTFLOAT80U r80;
2916 /** Extended precision floating point view v2 */
2917 RTFLOAT80U2 r80Ex;
2918 /** 8-bit view. */
2919 uint8_t au8[16];
2920 /** 16-bit view. */
2921 uint16_t au16[8];
2922 /** 32-bit view. */
2923 uint32_t au32[4];
2924 /** 64-bit view. */
2925 uint64_t au64[2];
2926 /** 128-bit view. (yeah, very helpful) */
2927 uint128_t au128[1];
2928} X86FPUREG;
2929#ifndef VBOX_FOR_DTRACE_LIB
2930AssertCompileSize(X86FPUREG, 16);
2931#endif
2932/** Pointer to a FPU register. */
2933typedef X86FPUREG *PX86FPUREG;
2934/** Pointer to a const FPU register. */
2935typedef X86FPUREG const *PCX86FPUREG;
2936
2937/**
2938 * XMM register union.
2939 */
2940typedef union X86XMMREG
2941{
2942 /** XMM Register view. */
2943 uint128_t xmm;
2944 /** 8-bit view. */
2945 uint8_t au8[16];
2946 /** 16-bit view. */
2947 uint16_t au16[8];
2948 /** 32-bit view. */
2949 uint32_t au32[4];
2950 /** 64-bit view. */
2951 uint64_t au64[2];
2952 /** 128-bit view. (yeah, very helpful) */
2953 uint128_t au128[1];
2954#ifndef VBOX_FOR_DTRACE_LIB
2955 /** Confusing nested 128-bit union view (this is what xmm should've been). */
2956 RTUINT128U uXmm;
2957#endif
2958} X86XMMREG;
2959#ifndef VBOX_FOR_DTRACE_LIB
2960AssertCompileSize(X86XMMREG, 16);
2961#endif
2962/** Pointer to an XMM register state. */
2963typedef X86XMMREG *PX86XMMREG;
2964/** Pointer to a const XMM register state. */
2965typedef X86XMMREG const *PCX86XMMREG;
2966
2967/**
2968 * YMM register union.
2969 */
2970typedef union X86YMMREG
2971{
2972 /** 8-bit view. */
2973 uint8_t au8[32];
2974 /** 16-bit view. */
2975 uint16_t au16[16];
2976 /** 32-bit view. */
2977 uint32_t au32[8];
2978 /** 64-bit view. */
2979 uint64_t au64[4];
2980 /** 128-bit view. (yeah, very helpful) */
2981 uint128_t au128[2];
2982 /** XMM sub register view. */
2983 X86XMMREG aXmm[2];
2984} X86YMMREG;
2985#ifndef VBOX_FOR_DTRACE_LIB
2986AssertCompileSize(X86YMMREG, 32);
2987#endif
2988/** Pointer to an YMM register state. */
2989typedef X86YMMREG *PX86YMMREG;
2990/** Pointer to a const YMM register state. */
2991typedef X86YMMREG const *PCX86YMMREG;
2992
2993/**
2994 * ZMM register union.
2995 */
2996typedef union X86ZMMREG
2997{
2998 /** 8-bit view. */
2999 uint8_t au8[64];
3000 /** 16-bit view. */
3001 uint16_t au16[32];
3002 /** 32-bit view. */
3003 uint32_t au32[16];
3004 /** 64-bit view. */
3005 uint64_t au64[8];
3006 /** 128-bit view. (yeah, very helpful) */
3007 uint128_t au128[4];
3008 /** XMM sub register view. */
3009 X86XMMREG aXmm[4];
3010 /** YMM sub register view. */
3011 X86YMMREG aYmm[2];
3012} X86ZMMREG;
3013#ifndef VBOX_FOR_DTRACE_LIB
3014AssertCompileSize(X86ZMMREG, 64);
3015#endif
3016/** Pointer to an ZMM register state. */
3017typedef X86ZMMREG *PX86ZMMREG;
3018/** Pointer to a const ZMM register state. */
3019typedef X86ZMMREG const *PCX86ZMMREG;
3020
3021
3022/**
3023 * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3024 * @todo verify this...
3025 */
3026#pragma pack(1)
3027typedef struct X86FPUSTATE
3028{
3029 /** 0x00 - Control word. */
3030 uint16_t FCW;
3031 /** 0x02 - Alignment word */
3032 uint16_t Dummy1;
3033 /** 0x04 - Status word. */
3034 uint16_t FSW;
3035 /** 0x06 - Alignment word */
3036 uint16_t Dummy2;
3037 /** 0x08 - Tag word */
3038 uint16_t FTW;
3039 /** 0x0a - Alignment word */
3040 uint16_t Dummy3;
3041
3042 /** 0x0c - Instruction pointer. */
3043 uint32_t FPUIP;
3044 /** 0x10 - Code selector. */
3045 uint16_t CS;
3046 /** 0x12 - Opcode. */
3047 uint16_t FOP;
3048 /** 0x14 - FOO. */
3049 uint32_t FPUOO;
3050 /** 0x18 - FOS. */
3051 uint32_t FPUOS;
3052 /** 0x1c - FPU register. */
3053 X86FPUREG regs[8];
3054} X86FPUSTATE;
3055#pragma pack()
3056/** Pointer to a FPU state. */
3057typedef X86FPUSTATE *PX86FPUSTATE;
3058/** Pointer to a const FPU state. */
3059typedef const X86FPUSTATE *PCX86FPUSTATE;
3060
3061/**
3062 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3063 */
3064#pragma pack(1)
3065typedef struct X86FXSTATE
3066{
3067 /** 0x00 - Control word. */
3068 uint16_t FCW;
3069 /** 0x02 - Status word. */
3070 uint16_t FSW;
3071 /** 0x04 - Tag word. (The upper byte is always zero.) */
3072 uint16_t FTW;
3073 /** 0x06 - Opcode. */
3074 uint16_t FOP;
3075 /** 0x08 - Instruction pointer. */
3076 uint32_t FPUIP;
3077 /** 0x0c - Code selector. */
3078 uint16_t CS;
3079 uint16_t Rsrvd1;
3080 /** 0x10 - Data pointer. */
3081 uint32_t FPUDP;
3082 /** 0x14 - Data segment */
3083 uint16_t DS;
3084 /** 0x16 */
3085 uint16_t Rsrvd2;
3086 /** 0x18 */
3087 uint32_t MXCSR;
3088 /** 0x1c */
3089 uint32_t MXCSR_MASK;
3090 /** 0x20 - FPU registers. */
3091 X86FPUREG aRegs[8];
3092 /** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3093 X86XMMREG aXMM[16];
3094 /* - offset 416 - */
3095 uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3096 /* - offset 464 - Software usable reserved bits. */
3097 uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3098} X86FXSTATE;
3099#pragma pack()
3100/** Pointer to a FPU Extended state. */
3101typedef X86FXSTATE *PX86FXSTATE;
3102/** Pointer to a const FPU Extended state. */
3103typedef const X86FXSTATE *PCX86FXSTATE;
3104
3105/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3106 * magic. Don't forget to update x86.mac if you change this! */
3107#define X86_OFF_FXSTATE_RSVD 0x1d0
3108/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3109 * forget to update x86.mac if you change this!
3110 * @todo r=bird: This has nothing what-so-ever to do here.... */
3111#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3112#ifndef VBOX_FOR_DTRACE_LIB
3113AssertCompileSize(X86FXSTATE, 512);
3114AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3115#endif
3116
3117/** @name FPU status word flags.
3118 * @{ */
3119/** Exception Flag: Invalid operation. */
3120#define X86_FSW_IE RT_BIT_32(0)
3121/** Exception Flag: Denormalized operand. */
3122#define X86_FSW_DE RT_BIT_32(1)
3123/** Exception Flag: Zero divide. */
3124#define X86_FSW_ZE RT_BIT_32(2)
3125/** Exception Flag: Overflow. */
3126#define X86_FSW_OE RT_BIT_32(3)
3127/** Exception Flag: Underflow. */
3128#define X86_FSW_UE RT_BIT_32(4)
3129/** Exception Flag: Precision. */
3130#define X86_FSW_PE RT_BIT_32(5)
3131/** Stack fault. */
3132#define X86_FSW_SF RT_BIT_32(6)
3133/** Error summary status. */
3134#define X86_FSW_ES RT_BIT_32(7)
3135/** Mask of exceptions flags, excluding the summary bit. */
3136#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3137/** Mask of exceptions flags, including the summary bit. */
3138#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3139/** Condition code 0. */
3140#define X86_FSW_C0 RT_BIT_32(8)
3141/** Condition code 1. */
3142#define X86_FSW_C1 RT_BIT_32(9)
3143/** Condition code 2. */
3144#define X86_FSW_C2 RT_BIT_32(10)
3145/** Top of the stack mask. */
3146#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3147/** TOP shift value. */
3148#define X86_FSW_TOP_SHIFT 11
3149/** Mask for getting TOP value after shifting it right. */
3150#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3151/** Get the TOP value. */
3152#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3153/** Condition code 3. */
3154#define X86_FSW_C3 RT_BIT_32(14)
3155/** Mask of exceptions flags, including the summary bit. */
3156#define X86_FSW_C_MASK UINT16_C(0x4700)
3157/** FPU busy. */
3158#define X86_FSW_B RT_BIT_32(15)
3159/** @} */
3160
3161
3162/** @name FPU control word flags.
3163 * @{ */
3164/** Exception Mask: Invalid operation. */
3165#define X86_FCW_IM RT_BIT_32(0)
3166/** Exception Mask: Denormalized operand. */
3167#define X86_FCW_DM RT_BIT_32(1)
3168/** Exception Mask: Zero divide. */
3169#define X86_FCW_ZM RT_BIT_32(2)
3170/** Exception Mask: Overflow. */
3171#define X86_FCW_OM RT_BIT_32(3)
3172/** Exception Mask: Underflow. */
3173#define X86_FCW_UM RT_BIT_32(4)
3174/** Exception Mask: Precision. */
3175#define X86_FCW_PM RT_BIT_32(5)
3176/** Mask all exceptions, the value typically loaded (by for instance fninit).
3177 * @remarks This includes reserved bit 6. */
3178#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3179/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3180#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3181/** Precision control mask. */
3182#define X86_FCW_PC_MASK UINT16_C(0x0300)
3183/** Precision control: 24-bit. */
3184#define X86_FCW_PC_24 UINT16_C(0x0000)
3185/** Precision control: Reserved. */
3186#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3187/** Precision control: 53-bit. */
3188#define X86_FCW_PC_53 UINT16_C(0x0200)
3189/** Precision control: 64-bit. */
3190#define X86_FCW_PC_64 UINT16_C(0x0300)
3191/** Rounding control mask. */
3192#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3193/** Rounding control: To nearest. */
3194#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3195/** Rounding control: Down. */
3196#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3197/** Rounding control: Up. */
3198#define X86_FCW_RC_UP UINT16_C(0x0800)
3199/** Rounding control: Towards zero. */
3200#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3201/** Bits which should be zero, apparently. */
3202#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3203/** @} */
3204
3205/** @name SSE MXCSR
3206 * @{ */
3207/** Exception Flag: Invalid operation. */
3208#define X86_MXCSR_IE RT_BIT_32(0)
3209/** Exception Flag: Denormalized operand. */
3210#define X86_MXCSR_DE RT_BIT_32(1)
3211/** Exception Flag: Zero divide. */
3212#define X86_MXCSR_ZE RT_BIT_32(2)
3213/** Exception Flag: Overflow. */
3214#define X86_MXCSR_OE RT_BIT_32(3)
3215/** Exception Flag: Underflow. */
3216#define X86_MXCSR_UE RT_BIT_32(4)
3217/** Exception Flag: Precision. */
3218#define X86_MXCSR_PE RT_BIT_32(5)
3219
3220/** Denormals are zero. */
3221#define X86_MXCSR_DAZ RT_BIT_32(6)
3222
3223/** Exception Mask: Invalid operation. */
3224#define X86_MXCSR_IM RT_BIT_32(7)
3225/** Exception Mask: Denormalized operand. */
3226#define X86_MXCSR_DM RT_BIT_32(8)
3227/** Exception Mask: Zero divide. */
3228#define X86_MXCSR_ZM RT_BIT_32(9)
3229/** Exception Mask: Overflow. */
3230#define X86_MXCSR_OM RT_BIT_32(10)
3231/** Exception Mask: Underflow. */
3232#define X86_MXCSR_UM RT_BIT_32(11)
3233/** Exception Mask: Precision. */
3234#define X86_MXCSR_PM RT_BIT_32(12)
3235
3236/** Rounding control mask. */
3237#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
3238/** Rounding control: To nearest. */
3239#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
3240/** Rounding control: Down. */
3241#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
3242/** Rounding control: Up. */
3243#define X86_MXCSR_RC_UP UINT16_C(0x4000)
3244/** Rounding control: Towards zero. */
3245#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
3246
3247/** Flush-to-zero for masked underflow. */
3248#define X86_MXCSR_FZ RT_BIT_32(15)
3249
3250/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3251#define X86_MXCSR_MM RT_BIT_32(17)
3252/** @} */
3253
3254/**
3255 * XSAVE header.
3256 */
3257typedef struct X86XSAVEHDR
3258{
3259 /** XTATE_BV - Bitmap indicating whether a component is in the state. */
3260 uint64_t bmXState;
3261 /** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3262 uint64_t bmXComp;
3263 /** Reserved for furture extensions, probably MBZ. */
3264 uint64_t au64Reserved[6];
3265} X86XSAVEHDR;
3266#ifndef VBOX_FOR_DTRACE_LIB
3267AssertCompileSize(X86XSAVEHDR, 64);
3268#endif
3269/** Pointer to an XSAVE header. */
3270typedef X86XSAVEHDR *PX86XSAVEHDR;
3271/** Pointer to a const XSAVE header. */
3272typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3273
3274
3275/**
3276 * The high 128-bit YMM register state (XSAVE_C_YMM).
3277 * (The lower 128-bits being in X86FXSTATE.)
3278 */
3279typedef struct X86XSAVEYMMHI
3280{
3281 /** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3282 X86XMMREG aYmmHi[16];
3283} X86XSAVEYMMHI;
3284#ifndef VBOX_FOR_DTRACE_LIB
3285AssertCompileSize(X86XSAVEYMMHI, 256);
3286#endif
3287/** Pointer to a high 128-bit YMM register state. */
3288typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3289/** Pointer to a const high 128-bit YMM register state. */
3290typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3291
3292/**
3293 * Intel MPX bound registers state (XSAVE_C_BNDREGS).
3294 */
3295typedef struct X86XSAVEBNDREGS
3296{
3297 /** Array of registers (BND0...BND3). */
3298 struct
3299 {
3300 /** Lower bound. */
3301 uint64_t uLowerBound;
3302 /** Upper bound. */
3303 uint64_t uUpperBound;
3304 } aRegs[4];
3305} X86XSAVEBNDREGS;
3306#ifndef VBOX_FOR_DTRACE_LIB
3307AssertCompileSize(X86XSAVEBNDREGS, 64);
3308#endif
3309/** Pointer to a MPX bound register state. */
3310typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3311/** Pointer to a const MPX bound register state. */
3312typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3313
3314/**
3315 * Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3316 */
3317typedef struct X86XSAVEBNDCFG
3318{
3319 uint64_t fConfig;
3320 uint64_t fStatus;
3321} X86XSAVEBNDCFG;
3322#ifndef VBOX_FOR_DTRACE_LIB
3323AssertCompileSize(X86XSAVEBNDCFG, 16);
3324#endif
3325/** Pointer to a MPX bound config and status register state. */
3326typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3327/** Pointer to a const MPX bound config and status register state. */
3328typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3329
3330/**
3331 * AVX-512 opmask state (XSAVE_C_OPMASK).
3332 */
3333typedef struct X86XSAVEOPMASK
3334{
3335 /** The K0..K7 values. */
3336 uint64_t aKRegs[8];
3337} X86XSAVEOPMASK;
3338#ifndef VBOX_FOR_DTRACE_LIB
3339AssertCompileSize(X86XSAVEOPMASK, 64);
3340#endif
3341/** Pointer to a AVX-512 opmask state. */
3342typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3343/** Pointer to a const AVX-512 opmask state. */
3344typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3345
3346/**
3347 * ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3348 */
3349typedef struct X86XSAVEZMMHI256
3350{
3351 /** Upper 256-bits of ZMM0-15. */
3352 X86YMMREG aHi256Regs[16];
3353} X86XSAVEZMMHI256;
3354#ifndef VBOX_FOR_DTRACE_LIB
3355AssertCompileSize(X86XSAVEZMMHI256, 512);
3356#endif
3357/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3358typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3359/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3360typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3361
3362/**
3363 * ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3364 */
3365typedef struct X86XSAVEZMM16HI
3366{
3367 /** ZMM16 thru ZMM31. */
3368 X86ZMMREG aRegs[16];
3369} X86XSAVEZMM16HI;
3370#ifndef VBOX_FOR_DTRACE_LIB
3371AssertCompileSize(X86XSAVEZMM16HI, 1024);
3372#endif
3373/** Pointer to a state comprising ZMM16-32. */
3374typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3375/** Pointer to a const state comprising ZMM16-32. */
3376typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3377
3378/**
3379 * AMD Light weight profiling state (XSAVE_C_LWP).
3380 *
3381 * We probably won't play with this as AMD seems to be dropping from their "zen"
3382 * processor micro architecture.
3383 */
3384typedef struct X86XSAVELWP
3385{
3386 /** Details when needed. */
3387 uint64_t auLater[128/8];
3388} X86XSAVELWP;
3389#ifndef VBOX_FOR_DTRACE_LIB
3390AssertCompileSize(X86XSAVELWP, 128);
3391#endif
3392
3393
3394/**
3395 * x86 FPU/SSE/AVX/XXXX state.
3396 *
3397 * Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3398 * changes to this structure.
3399 */
3400typedef struct X86XSAVEAREA
3401{
3402 /** The x87 and SSE region (or legacy region if you like). */
3403 X86FXSTATE x87;
3404 /** The XSAVE header. */
3405 X86XSAVEHDR Hdr;
3406 /** Beyond the header, there isn't really a fixed layout, but we can
3407 generally assume the YMM (AVX) register extensions are present and
3408 follows immediately. */
3409 union
3410 {
3411 /** The high 128-bit AVX registers for easy access by IEM.
3412 * @note This ASSUMES they will always be here... */
3413 X86XSAVEYMMHI YmmHi;
3414
3415 /** This is a typical layout on intel CPUs (good for debuggers). */
3416 struct
3417 {
3418 X86XSAVEYMMHI YmmHi;
3419 X86XSAVEBNDREGS BndRegs;
3420 X86XSAVEBNDCFG BndCfg;
3421 uint8_t abFudgeToMatchDocs[0xB0];
3422 X86XSAVEOPMASK Opmask;
3423 X86XSAVEZMMHI256 ZmmHi256;
3424 X86XSAVEZMM16HI Zmm16Hi;
3425 } Intel;
3426
3427 /** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3428 struct
3429 {
3430 X86XSAVEYMMHI YmmHi;
3431 X86XSAVELWP Lwp;
3432 } AmdBd;
3433
3434 /** To enbling static deployments that have a reasonable chance of working for
3435 * the next 3-6 CPU generations without running short on space, we allocate a
3436 * lot of extra space here, making the structure a round 8KB in size. This
3437 * leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3438 * 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3439 uint8_t ab[8192 - 512 - 64];
3440 } u;
3441} X86XSAVEAREA;
3442#ifndef VBOX_FOR_DTRACE_LIB
3443AssertCompileSize(X86XSAVEAREA, 8192);
3444AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /*2112 => total 0xa80 (2688) */);
3445AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3446AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3447AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3448AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3449AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3450AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3451AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3452#endif
3453/** Pointer to a XSAVE area. */
3454typedef X86XSAVEAREA *PX86XSAVEAREA;
3455/** Pointer to a const XSAVE area. */
3456typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3457
3458
3459/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3460 * @{ */
3461/** Bit 0 - x87 - Legacy FPU state (bit number) */
3462#define XSAVE_C_X87_BIT 0
3463/** Bit 0 - x87 - Legacy FPU state. */
3464#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3465/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3466#define XSAVE_C_SSE_BIT 1
3467/** Bit 1 - SSE - 128-bit SSE state. */
3468#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3469/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3470#define XSAVE_C_YMM_BIT 2
3471/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3472#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3473/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3474#define XSAVE_C_BNDREGS_BIT 3
3475/** Bit 3 - BNDREGS - MPX bound register state. */
3476#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3477/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3478#define XSAVE_C_BNDCSR_BIT 4
3479/** Bit 4 - BNDCSR - MPX bound config and status state. */
3480#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3481/** Bit 5 - Opmask - opmask state (bit number). */
3482#define XSAVE_C_OPMASK_BIT 5
3483/** Bit 5 - Opmask - opmask state. */
3484#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3485/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3486#define XSAVE_C_ZMM_HI256_BIT 6
3487/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3488#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3489/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3490#define XSAVE_C_ZMM_16HI_BIT 7
3491/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3492#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3493/** Bit 9 - PKRU - Protection-key state (bit number). */
3494#define XSAVE_C_PKRU_BIT 9
3495/** Bit 9 - PKRU - Protection-key state. */
3496#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3497/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3498#define XSAVE_C_LWP_BIT 62
3499/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3500#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3501/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3502#define XSAVE_C_X_BIT 63
3503/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3504#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3505/** @} */
3506
3507
3508
3509/** @name Selector Descriptor
3510 * @{
3511 */
3512
3513#ifndef VBOX_FOR_DTRACE_LIB
3514/**
3515 * Descriptor attributes (as seen by VT-x).
3516 */
3517typedef struct X86DESCATTRBITS
3518{
3519 /** 00 - Segment Type. */
3520 unsigned u4Type : 4;
3521 /** 04 - Descriptor Type. System(=0) or code/data selector */
3522 unsigned u1DescType : 1;
3523 /** 05 - Descriptor Privilege level. */
3524 unsigned u2Dpl : 2;
3525 /** 07 - Flags selector present(=1) or not. */
3526 unsigned u1Present : 1;
3527 /** 08 - Segment limit 16-19. */
3528 unsigned u4LimitHigh : 4;
3529 /** 0c - Available for system software. */
3530 unsigned u1Available : 1;
3531 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3532 unsigned u1Long : 1;
3533 /** 0e - This flags meaning depends on the segment type. Try make sense out
3534 * of the intel manual yourself. */
3535 unsigned u1DefBig : 1;
3536 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
3537 * clear byte. */
3538 unsigned u1Granularity : 1;
3539 /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3540 unsigned u1Unusable : 1;
3541} X86DESCATTRBITS;
3542#endif /* !VBOX_FOR_DTRACE_LIB */
3543
3544/** @name X86DESCATTR masks
3545 * @{ */
3546#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3547#define X86DESCATTR_DT UINT32_C(0x00000010)
3548#define X86DESCATTR_DPL UINT32_C(0x00000060)
3549#define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL value. */
3550#define X86DESCATTR_P UINT32_C(0x00000080)
3551#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3552#define X86DESCATTR_AVL UINT32_C(0x00001000)
3553#define X86DESCATTR_L UINT32_C(0x00002000)
3554#define X86DESCATTR_D UINT32_C(0x00004000)
3555#define X86DESCATTR_G UINT32_C(0x00008000)
3556#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3557/** @} */
3558
3559#pragma pack(1)
3560typedef union X86DESCATTR
3561{
3562 /** Unsigned integer view. */
3563 uint32_t u;
3564#ifndef VBOX_FOR_DTRACE_LIB
3565 /** Normal view. */
3566 X86DESCATTRBITS n;
3567#endif
3568} X86DESCATTR;
3569#pragma pack()
3570/** Pointer to descriptor attributes. */
3571typedef X86DESCATTR *PX86DESCATTR;
3572/** Pointer to const descriptor attributes. */
3573typedef const X86DESCATTR *PCX86DESCATTR;
3574
3575#ifndef VBOX_FOR_DTRACE_LIB
3576
3577/**
3578 * Generic descriptor table entry
3579 */
3580#pragma pack(1)
3581typedef struct X86DESCGENERIC
3582{
3583 /** 00 - Limit - Low word. */
3584 unsigned u16LimitLow : 16;
3585 /** 10 - Base address - low word.
3586 * Don't try set this to 24 because MSC is doing stupid things then. */
3587 unsigned u16BaseLow : 16;
3588 /** 20 - Base address - first 8 bits of high word. */
3589 unsigned u8BaseHigh1 : 8;
3590 /** 28 - Segment Type. */
3591 unsigned u4Type : 4;
3592 /** 2c - Descriptor Type. System(=0) or code/data selector */
3593 unsigned u1DescType : 1;
3594 /** 2d - Descriptor Privilege level. */
3595 unsigned u2Dpl : 2;
3596 /** 2f - Flags selector present(=1) or not. */
3597 unsigned u1Present : 1;
3598 /** 30 - Segment limit 16-19. */
3599 unsigned u4LimitHigh : 4;
3600 /** 34 - Available for system software. */
3601 unsigned u1Available : 1;
3602 /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3603 unsigned u1Long : 1;
3604 /** 36 - This flags meaning depends on the segment type. Try make sense out
3605 * of the intel manual yourself. */
3606 unsigned u1DefBig : 1;
3607 /** 37 - Granularity of the limit. If set 4KB granularity is used, if
3608 * clear byte. */
3609 unsigned u1Granularity : 1;
3610 /** 38 - Base address - highest 8 bits. */
3611 unsigned u8BaseHigh2 : 8;
3612} X86DESCGENERIC;
3613#pragma pack()
3614/** Pointer to a generic descriptor entry. */
3615typedef X86DESCGENERIC *PX86DESCGENERIC;
3616/** Pointer to a const generic descriptor entry. */
3617typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3618
3619/** @name Bit offsets of X86DESCGENERIC members.
3620 * @{*/
3621#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
3622#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
3623#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
3624#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
3625#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
3626#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
3627#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
3628#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
3629#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
3630#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
3631#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
3632#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
3633#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
3634/** @} */
3635
3636
3637/** @name LAR mask
3638 * @{ */
3639#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3640#define X86LAR_F_DT UINT16_C( 0x1000)
3641#define X86LAR_F_DPL UINT16_C( 0x6000)
3642#define X86LAR_F_DPL_SHIFT 13 /**< Shift count for the DPL value. */
3643#define X86LAR_F_P UINT16_C( 0x8000)
3644#define X86LAR_F_AVL UINT32_C(0x00100000)
3645#define X86LAR_F_L UINT32_C(0x00200000)
3646#define X86LAR_F_D UINT32_C(0x00400000)
3647#define X86LAR_F_G UINT32_C(0x00800000)
3648/** @} */
3649
3650
3651/**
3652 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3653 */
3654typedef struct X86DESCGATE
3655{
3656 /** 00 - Target code segment offset - Low word.
3657 * Ignored if task-gate. */
3658 unsigned u16OffsetLow : 16;
3659 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3660 * TSS selector if task-gate. */
3661 unsigned u16Sel : 16;
3662 /** 20 - Number of parameters for a call-gate.
3663 * Ignored if interrupt-, trap- or task-gate. */
3664 unsigned u5ParmCount : 5;
3665 /** 25 - Reserved / ignored. */
3666 unsigned u3Reserved : 3;
3667 /** 28 - Segment Type. */
3668 unsigned u4Type : 4;
3669 /** 2c - Descriptor Type (0 = system). */
3670 unsigned u1DescType : 1;
3671 /** 2d - Descriptor Privilege level. */
3672 unsigned u2Dpl : 2;
3673 /** 2f - Flags selector present(=1) or not. */
3674 unsigned u1Present : 1;
3675 /** 30 - Target code segment offset - High word.
3676 * Ignored if task-gate. */
3677 unsigned u16OffsetHigh : 16;
3678} X86DESCGATE;
3679/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3680typedef X86DESCGATE *PX86DESCGATE;
3681/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3682typedef const X86DESCGATE *PCX86DESCGATE;
3683
3684#endif /* VBOX_FOR_DTRACE_LIB */
3685
3686/**
3687 * Descriptor table entry.
3688 */
3689#pragma pack(1)
3690typedef union X86DESC
3691{
3692#ifndef VBOX_FOR_DTRACE_LIB
3693 /** Generic descriptor view. */
3694 X86DESCGENERIC Gen;
3695 /** Gate descriptor view. */
3696 X86DESCGATE Gate;
3697#endif
3698
3699 /** 8 bit unsigned integer view. */
3700 uint8_t au8[8];
3701 /** 16 bit unsigned integer view. */
3702 uint16_t au16[4];
3703 /** 32 bit unsigned integer view. */
3704 uint32_t au32[2];
3705 /** 64 bit unsigned integer view. */
3706 uint64_t au64[1];
3707 /** Unsigned integer view. */
3708 uint64_t u;
3709} X86DESC;
3710#ifndef VBOX_FOR_DTRACE_LIB
3711AssertCompileSize(X86DESC, 8);
3712#endif
3713#pragma pack()
3714/** Pointer to descriptor table entry. */
3715typedef X86DESC *PX86DESC;
3716/** Pointer to const descriptor table entry. */
3717typedef const X86DESC *PCX86DESC;
3718
3719/** @def X86DESC_BASE
3720 * Return the base address of a descriptor.
3721 */
3722#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
3723 ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3724 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3725 | ( (a_pDesc)->Gen.u16BaseLow ) )
3726
3727/** @def X86DESC_LIMIT
3728 * Return the limit of a descriptor.
3729 */
3730#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
3731 ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3732 | ( (a_pDesc)->Gen.u16LimitLow ) )
3733
3734/** @def X86DESC_LIMIT_G
3735 * Return the limit of a descriptor with the granularity bit taken into account.
3736 * @returns Selector limit (uint32_t).
3737 * @param a_pDesc Pointer to the descriptor.
3738 */
3739#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
3740 ( (a_pDesc)->Gen.u1Granularity \
3741 ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
3742 : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
3743 )
3744
3745/** @def X86DESC_GET_HID_ATTR
3746 * Get the descriptor attributes for the hidden register.
3747 */
3748#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
3749 ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3750
3751#ifndef VBOX_FOR_DTRACE_LIB
3752
3753/**
3754 * 64 bits generic descriptor table entry
3755 * Note: most of these bits have no meaning in long mode.
3756 */
3757#pragma pack(1)
3758typedef struct X86DESC64GENERIC
3759{
3760 /** Limit - Low word - *IGNORED*. */
3761 uint32_t u16LimitLow : 16;
3762 /** Base address - low word. - *IGNORED*
3763 * Don't try set this to 24 because MSC is doing stupid things then. */
3764 uint32_t u16BaseLow : 16;
3765 /** Base address - first 8 bits of high word. - *IGNORED* */
3766 uint32_t u8BaseHigh1 : 8;
3767 /** Segment Type. */
3768 uint32_t u4Type : 4;
3769 /** Descriptor Type. System(=0) or code/data selector */
3770 uint32_t u1DescType : 1;
3771 /** Descriptor Privilege level. */
3772 uint32_t u2Dpl : 2;
3773 /** Flags selector present(=1) or not. */
3774 uint32_t u1Present : 1;
3775 /** Segment limit 16-19. - *IGNORED* */
3776 uint32_t u4LimitHigh : 4;
3777 /** Available for system software. - *IGNORED* */
3778 uint32_t u1Available : 1;
3779 /** Long mode flag. */
3780 uint32_t u1Long : 1;
3781 /** This flags meaning depends on the segment type. Try make sense out
3782 * of the intel manual yourself. */
3783 uint32_t u1DefBig : 1;
3784 /** Granularity of the limit. If set 4KB granularity is used, if
3785 * clear byte. - *IGNORED* */
3786 uint32_t u1Granularity : 1;
3787 /** Base address - highest 8 bits. - *IGNORED* */
3788 uint32_t u8BaseHigh2 : 8;
3789 /** Base address - bits 63-32. */
3790 uint32_t u32BaseHigh3 : 32;
3791 uint32_t u8Reserved : 8;
3792 uint32_t u5Zeros : 5;
3793 uint32_t u19Reserved : 19;
3794} X86DESC64GENERIC;
3795#pragma pack()
3796/** Pointer to a generic descriptor entry. */
3797typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3798/** Pointer to a const generic descriptor entry. */
3799typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3800
3801/**
3802 * System descriptor table entry (64 bits)
3803 *
3804 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3805 */
3806#pragma pack(1)
3807typedef struct X86DESC64SYSTEM
3808{
3809 /** Limit - Low word. */
3810 uint32_t u16LimitLow : 16;
3811 /** Base address - low word.
3812 * Don't try set this to 24 because MSC is doing stupid things then. */
3813 uint32_t u16BaseLow : 16;
3814 /** Base address - first 8 bits of high word. */
3815 uint32_t u8BaseHigh1 : 8;
3816 /** Segment Type. */
3817 uint32_t u4Type : 4;
3818 /** Descriptor Type. System(=0) or code/data selector */
3819 uint32_t u1DescType : 1;
3820 /** Descriptor Privilege level. */
3821 uint32_t u2Dpl : 2;
3822 /** Flags selector present(=1) or not. */
3823 uint32_t u1Present : 1;
3824 /** Segment limit 16-19. */
3825 uint32_t u4LimitHigh : 4;
3826 /** Available for system software. */
3827 uint32_t u1Available : 1;
3828 /** Reserved - 0. */
3829 uint32_t u1Reserved : 1;
3830 /** This flags meaning depends on the segment type. Try make sense out
3831 * of the intel manual yourself. */
3832 uint32_t u1DefBig : 1;
3833 /** Granularity of the limit. If set 4KB granularity is used, if
3834 * clear byte. */
3835 uint32_t u1Granularity : 1;
3836 /** Base address - bits 31-24. */
3837 uint32_t u8BaseHigh2 : 8;
3838 /** Base address - bits 63-32. */
3839 uint32_t u32BaseHigh3 : 32;
3840 uint32_t u8Reserved : 8;
3841 uint32_t u5Zeros : 5;
3842 uint32_t u19Reserved : 19;
3843} X86DESC64SYSTEM;
3844#pragma pack()
3845/** Pointer to a system descriptor entry. */
3846typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3847/** Pointer to a const system descriptor entry. */
3848typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3849
3850/**
3851 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3852 */
3853typedef struct X86DESC64GATE
3854{
3855 /** Target code segment offset - Low word. */
3856 uint32_t u16OffsetLow : 16;
3857 /** Target code segment selector. */
3858 uint32_t u16Sel : 16;
3859 /** Interrupt stack table for interrupt- and trap-gates.
3860 * Ignored by call-gates. */
3861 uint32_t u3IST : 3;
3862 /** Reserved / ignored. */
3863 uint32_t u5Reserved : 5;
3864 /** Segment Type. */
3865 uint32_t u4Type : 4;
3866 /** Descriptor Type (0 = system). */
3867 uint32_t u1DescType : 1;
3868 /** Descriptor Privilege level. */
3869 uint32_t u2Dpl : 2;
3870 /** Flags selector present(=1) or not. */
3871 uint32_t u1Present : 1;
3872 /** Target code segment offset - High word.
3873 * Ignored if task-gate. */
3874 uint32_t u16OffsetHigh : 16;
3875 /** Target code segment offset - Top dword.
3876 * Ignored if task-gate. */
3877 uint32_t u32OffsetTop : 32;
3878 /** Reserved / ignored / must be zero.
3879 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3880 uint32_t u32Reserved : 32;
3881} X86DESC64GATE;
3882AssertCompileSize(X86DESC64GATE, 16);
3883/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3884typedef X86DESC64GATE *PX86DESC64GATE;
3885/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3886typedef const X86DESC64GATE *PCX86DESC64GATE;
3887
3888#endif /* VBOX_FOR_DTRACE_LIB */
3889
3890/**
3891 * Descriptor table entry.
3892 */
3893#pragma pack(1)
3894typedef union X86DESC64
3895{
3896#ifndef VBOX_FOR_DTRACE_LIB
3897 /** Generic descriptor view. */
3898 X86DESC64GENERIC Gen;
3899 /** System descriptor view. */
3900 X86DESC64SYSTEM System;
3901 /** Gate descriptor view. */
3902 X86DESC64GATE Gate;
3903#endif
3904
3905 /** 8 bit unsigned integer view. */
3906 uint8_t au8[16];
3907 /** 16 bit unsigned integer view. */
3908 uint16_t au16[8];
3909 /** 32 bit unsigned integer view. */
3910 uint32_t au32[4];
3911 /** 64 bit unsigned integer view. */
3912 uint64_t au64[2];
3913} X86DESC64;
3914#ifndef VBOX_FOR_DTRACE_LIB
3915AssertCompileSize(X86DESC64, 16);
3916#endif
3917#pragma pack()
3918/** Pointer to descriptor table entry. */
3919typedef X86DESC64 *PX86DESC64;
3920/** Pointer to const descriptor table entry. */
3921typedef const X86DESC64 *PCX86DESC64;
3922
3923/** @def X86DESC64_BASE
3924 * Return the base of a 64-bit descriptor.
3925 */
3926#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
3927 ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3928 | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3929 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3930 | ( (a_pDesc)->Gen.u16BaseLow ) )
3931
3932
3933
3934/** @name Host system descriptor table entry - Use with care!
3935 * @{ */
3936/** Host system descriptor table entry. */
3937#if HC_ARCH_BITS == 64
3938typedef X86DESC64 X86DESCHC;
3939#else
3940typedef X86DESC X86DESCHC;
3941#endif
3942/** Pointer to a host system descriptor table entry. */
3943#if HC_ARCH_BITS == 64
3944typedef PX86DESC64 PX86DESCHC;
3945#else
3946typedef PX86DESC PX86DESCHC;
3947#endif
3948/** Pointer to a const host system descriptor table entry. */
3949#if HC_ARCH_BITS == 64
3950typedef PCX86DESC64 PCX86DESCHC;
3951#else
3952typedef PCX86DESC PCX86DESCHC;
3953#endif
3954/** @} */
3955
3956
3957/** @name Selector Descriptor Types.
3958 * @{
3959 */
3960
3961/** @name Non-System Selector Types.
3962 * @{ */
3963/** Code(=set)/Data(=clear) bit. */
3964#define X86_SEL_TYPE_CODE 8
3965/** Memory(=set)/System(=clear) bit. */
3966#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
3967/** Accessed bit. */
3968#define X86_SEL_TYPE_ACCESSED 1
3969/** Expand down bit (for data selectors only). */
3970#define X86_SEL_TYPE_DOWN 4
3971/** Conforming bit (for code selectors only). */
3972#define X86_SEL_TYPE_CONF 4
3973/** Write bit (for data selectors only). */
3974#define X86_SEL_TYPE_WRITE 2
3975/** Read bit (for code selectors only). */
3976#define X86_SEL_TYPE_READ 2
3977/** The bit number of the code segment read bit (relative to u4Type). */
3978#define X86_SEL_TYPE_READ_BIT 1
3979
3980/** Read only selector type. */
3981#define X86_SEL_TYPE_RO 0
3982/** Accessed read only selector type. */
3983#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
3984/** Read write selector type. */
3985#define X86_SEL_TYPE_RW 2
3986/** Accessed read write selector type. */
3987#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
3988/** Expand down read only selector type. */
3989#define X86_SEL_TYPE_RO_DOWN 4
3990/** Accessed expand down read only selector type. */
3991#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
3992/** Expand down read write selector type. */
3993#define X86_SEL_TYPE_RW_DOWN 6
3994/** Accessed expand down read write selector type. */
3995#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
3996/** Execute only selector type. */
3997#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
3998/** Accessed execute only selector type. */
3999#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4000/** Execute and read selector type. */
4001#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
4002/** Accessed execute and read selector type. */
4003#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4004/** Conforming execute only selector type. */
4005#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
4006/** Accessed Conforming execute only selector type. */
4007#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4008/** Conforming execute and write selector type. */
4009#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
4010/** Accessed Conforming execute and write selector type. */
4011#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4012/** @} */
4013
4014
4015/** @name System Selector Types.
4016 * @{ */
4017/** The TSS busy bit mask. */
4018#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4019
4020/** Undefined system selector type. */
4021#define X86_SEL_TYPE_SYS_UNDEFINED 0
4022/** 286 TSS selector. */
4023#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4024/** LDT selector. */
4025#define X86_SEL_TYPE_SYS_LDT 2
4026/** 286 TSS selector - Busy. */
4027#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4028/** 286 Callgate selector. */
4029#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4030/** Taskgate selector. */
4031#define X86_SEL_TYPE_SYS_TASK_GATE 5
4032/** 286 Interrupt gate selector. */
4033#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4034/** 286 Trapgate selector. */
4035#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4036/** Undefined system selector. */
4037#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4038/** 386 TSS selector. */
4039#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4040/** Undefined system selector. */
4041#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4042/** 386 TSS selector - Busy. */
4043#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4044/** 386 Callgate selector. */
4045#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4046/** Undefined system selector. */
4047#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4048/** 386 Interruptgate selector. */
4049#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4050/** 386 Trapgate selector. */
4051#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4052/** @} */
4053
4054/** @name AMD64 System Selector Types.
4055 * @{ */
4056/** LDT selector. */
4057#define AMD64_SEL_TYPE_SYS_LDT 2
4058/** TSS selector - Busy. */
4059#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4060/** TSS selector - Busy. */
4061#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4062/** Callgate selector. */
4063#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4064/** Interruptgate selector. */
4065#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4066/** Trapgate selector. */
4067#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4068/** @} */
4069
4070/** @} */
4071
4072
4073/** @name Descriptor Table Entry Flag Masks.
4074 * These are for the 2nd 32-bit word of a descriptor.
4075 * @{ */
4076/** Bits 8-11 - TYPE - Descriptor type mask. */
4077#define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
4078/** Bit 12 - S - System (=0) or Code/Data (=1). */
4079#define X86_DESC_S RT_BIT_32(12)
4080/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4081#define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
4082/** Bit 15 - P - Present. */
4083#define X86_DESC_P RT_BIT_32(15)
4084/** Bit 20 - AVL - Available for system software. */
4085#define X86_DESC_AVL RT_BIT_32(20)
4086/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4087#define X86_DESC_DB RT_BIT_32(22)
4088/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4089 * used, if clear byte. */
4090#define X86_DESC_G RT_BIT_32(23)
4091/** @} */
4092
4093/** @} */
4094
4095
4096/** @name Task Segments.
4097 * @{
4098 */
4099
4100/**
4101 * The minimum TSS descriptor limit for 286 tasks.
4102 */
4103#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4104
4105/**
4106 * The minimum TSS descriptor segment limit for 386 tasks.
4107 */
4108#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4109
4110/**
4111 * 16-bit Task Segment (TSS).
4112 */
4113#pragma pack(1)
4114typedef struct X86TSS16
4115{
4116 /** Back link to previous task. (static) */
4117 RTSEL selPrev;
4118 /** Ring-0 stack pointer. (static) */
4119 uint16_t sp0;
4120 /** Ring-0 stack segment. (static) */
4121 RTSEL ss0;
4122 /** Ring-1 stack pointer. (static) */
4123 uint16_t sp1;
4124 /** Ring-1 stack segment. (static) */
4125 RTSEL ss1;
4126 /** Ring-2 stack pointer. (static) */
4127 uint16_t sp2;
4128 /** Ring-2 stack segment. (static) */
4129 RTSEL ss2;
4130 /** IP before task switch. */
4131 uint16_t ip;
4132 /** FLAGS before task switch. */
4133 uint16_t flags;
4134 /** AX before task switch. */
4135 uint16_t ax;
4136 /** CX before task switch. */
4137 uint16_t cx;
4138 /** DX before task switch. */
4139 uint16_t dx;
4140 /** BX before task switch. */
4141 uint16_t bx;
4142 /** SP before task switch. */
4143 uint16_t sp;
4144 /** BP before task switch. */
4145 uint16_t bp;
4146 /** SI before task switch. */
4147 uint16_t si;
4148 /** DI before task switch. */
4149 uint16_t di;
4150 /** ES before task switch. */
4151 RTSEL es;
4152 /** CS before task switch. */
4153 RTSEL cs;
4154 /** SS before task switch. */
4155 RTSEL ss;
4156 /** DS before task switch. */
4157 RTSEL ds;
4158 /** LDTR before task switch. */
4159 RTSEL selLdt;
4160} X86TSS16;
4161#ifndef VBOX_FOR_DTRACE_LIB
4162AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4163#endif
4164#pragma pack()
4165/** Pointer to a 16-bit task segment. */
4166typedef X86TSS16 *PX86TSS16;
4167/** Pointer to a const 16-bit task segment. */
4168typedef const X86TSS16 *PCX86TSS16;
4169
4170
4171/**
4172 * 32-bit Task Segment (TSS).
4173 */
4174#pragma pack(1)
4175typedef struct X86TSS32
4176{
4177 /** Back link to previous task. (static) */
4178 RTSEL selPrev;
4179 uint16_t padding1;
4180 /** Ring-0 stack pointer. (static) */
4181 uint32_t esp0;
4182 /** Ring-0 stack segment. (static) */
4183 RTSEL ss0;
4184 uint16_t padding_ss0;
4185 /** Ring-1 stack pointer. (static) */
4186 uint32_t esp1;
4187 /** Ring-1 stack segment. (static) */
4188 RTSEL ss1;
4189 uint16_t padding_ss1;
4190 /** Ring-2 stack pointer. (static) */
4191 uint32_t esp2;
4192 /** Ring-2 stack segment. (static) */
4193 RTSEL ss2;
4194 uint16_t padding_ss2;
4195 /** Page directory for the task. (static) */
4196 uint32_t cr3;
4197 /** EIP before task switch. */
4198 uint32_t eip;
4199 /** EFLAGS before task switch. */
4200 uint32_t eflags;
4201 /** EAX before task switch. */
4202 uint32_t eax;
4203 /** ECX before task switch. */
4204 uint32_t ecx;
4205 /** EDX before task switch. */
4206 uint32_t edx;
4207 /** EBX before task switch. */
4208 uint32_t ebx;
4209 /** ESP before task switch. */
4210 uint32_t esp;
4211 /** EBP before task switch. */
4212 uint32_t ebp;
4213 /** ESI before task switch. */
4214 uint32_t esi;
4215 /** EDI before task switch. */
4216 uint32_t edi;
4217 /** ES before task switch. */
4218 RTSEL es;
4219 uint16_t padding_es;
4220 /** CS before task switch. */
4221 RTSEL cs;
4222 uint16_t padding_cs;
4223 /** SS before task switch. */
4224 RTSEL ss;
4225 uint16_t padding_ss;
4226 /** DS before task switch. */
4227 RTSEL ds;
4228 uint16_t padding_ds;
4229 /** FS before task switch. */
4230 RTSEL fs;
4231 uint16_t padding_fs;
4232 /** GS before task switch. */
4233 RTSEL gs;
4234 uint16_t padding_gs;
4235 /** LDTR before task switch. */
4236 RTSEL selLdt;
4237 uint16_t padding_ldt;
4238 /** Debug trap flag */
4239 uint16_t fDebugTrap;
4240 /** Offset relative to the TSS of the start of the I/O Bitmap
4241 * and the end of the interrupt redirection bitmap. */
4242 uint16_t offIoBitmap;
4243} X86TSS32;
4244#pragma pack()
4245/** Pointer to task segment. */
4246typedef X86TSS32 *PX86TSS32;
4247/** Pointer to const task segment. */
4248typedef const X86TSS32 *PCX86TSS32;
4249#ifndef VBOX_FOR_DTRACE_LIB
4250AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4251AssertCompileMemberOffset(X86TSS32, cr3, 28);
4252AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4253#endif
4254
4255/**
4256 * 64-bit Task segment.
4257 */
4258#pragma pack(1)
4259typedef struct X86TSS64
4260{
4261 /** Reserved. */
4262 uint32_t u32Reserved;
4263 /** Ring-0 stack pointer. (static) */
4264 uint64_t rsp0;
4265 /** Ring-1 stack pointer. (static) */
4266 uint64_t rsp1;
4267 /** Ring-2 stack pointer. (static) */
4268 uint64_t rsp2;
4269 /** Reserved. */
4270 uint32_t u32Reserved2[2];
4271 /* IST */
4272 uint64_t ist1;
4273 uint64_t ist2;
4274 uint64_t ist3;
4275 uint64_t ist4;
4276 uint64_t ist5;
4277 uint64_t ist6;
4278 uint64_t ist7;
4279 /* Reserved. */
4280 uint16_t u16Reserved[5];
4281 /** Offset relative to the TSS of the start of the I/O Bitmap
4282 * and the end of the interrupt redirection bitmap. */
4283 uint16_t offIoBitmap;
4284} X86TSS64;
4285#pragma pack()
4286/** Pointer to a 64-bit task segment. */
4287typedef X86TSS64 *PX86TSS64;
4288/** Pointer to a const 64-bit task segment. */
4289typedef const X86TSS64 *PCX86TSS64;
4290#ifndef VBOX_FOR_DTRACE_LIB
4291AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4292#endif
4293
4294/** @} */
4295
4296
4297/** @name Selectors.
4298 * @{
4299 */
4300
4301/**
4302 * The shift used to convert a selector from and to index an index (C).
4303 */
4304#define X86_SEL_SHIFT 3
4305
4306/**
4307 * The mask used to mask off the table indicator and RPL of an selector.
4308 */
4309#define X86_SEL_MASK 0xfff8U
4310
4311/**
4312 * The mask used to mask off the RPL of an selector.
4313 * This is suitable for checking for NULL selectors.
4314 */
4315#define X86_SEL_MASK_OFF_RPL 0xfffcU
4316
4317/**
4318 * The bit indicating that a selector is in the LDT and not in the GDT.
4319 */
4320#define X86_SEL_LDT 0x0004U
4321
4322/**
4323 * The bit mask for getting the RPL of a selector.
4324 */
4325#define X86_SEL_RPL 0x0003U
4326
4327/**
4328 * The mask covering both RPL and LDT.
4329 * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4330 * checks.
4331 */
4332#define X86_SEL_RPL_LDT 0x0007U
4333
4334/** @} */
4335
4336
4337/**
4338 * x86 Exceptions/Faults/Traps.
4339 */
4340typedef enum X86XCPT
4341{
4342 /** \#DE - Divide error. */
4343 X86_XCPT_DE = 0x00,
4344 /** \#DB - Debug event (single step, DRx, ..) */
4345 X86_XCPT_DB = 0x01,
4346 /** NMI - Non-Maskable Interrupt */
4347 X86_XCPT_NMI = 0x02,
4348 /** \#BP - Breakpoint (INT3). */
4349 X86_XCPT_BP = 0x03,
4350 /** \#OF - Overflow (INTO). */
4351 X86_XCPT_OF = 0x04,
4352 /** \#BR - Bound range exceeded (BOUND). */
4353 X86_XCPT_BR = 0x05,
4354 /** \#UD - Undefined opcode. */
4355 X86_XCPT_UD = 0x06,
4356 /** \#NM - Device not available (math coprocessor device). */
4357 X86_XCPT_NM = 0x07,
4358 /** \#DF - Double fault. */
4359 X86_XCPT_DF = 0x08,
4360 /** ??? - Coprocessor segment overrun (obsolete). */
4361 X86_XCPT_CO_SEG_OVERRUN = 0x09,
4362 /** \#TS - Taskswitch (TSS). */
4363 X86_XCPT_TS = 0x0a,
4364 /** \#NP - Segment no present. */
4365 X86_XCPT_NP = 0x0b,
4366 /** \#SS - Stack segment fault. */
4367 X86_XCPT_SS = 0x0c,
4368 /** \#GP - General protection fault. */
4369 X86_XCPT_GP = 0x0d,
4370 /** \#PF - Page fault. */
4371 X86_XCPT_PF = 0x0e,
4372 /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4373 /** \#MF - Math fault (FPU). */
4374 X86_XCPT_MF = 0x10,
4375 /** \#AC - Alignment check. */
4376 X86_XCPT_AC = 0x11,
4377 /** \#MC - Machine check. */
4378 X86_XCPT_MC = 0x12,
4379 /** \#XF - SIMD Floating-Point Exception. */
4380 X86_XCPT_XF = 0x13,
4381 /** \#VE - Virtualization Exception (Intel only). */
4382 X86_XCPT_VE = 0x14,
4383 /** \#CP - Control Protection Exception (Intel only). */
4384 X86_XCPT_CP = 0x15,
4385 /** \#VC - VMM Communication Exception (AMD only). */
4386 X86_XCPT_VC = 0x1d,
4387 /** \#SX - Security Exception (AMD only). */
4388 X86_XCPT_SX = 0x1e
4389} X86XCPT;
4390/** Pointer to a x86 exception code. */
4391typedef X86XCPT *PX86XCPT;
4392/** Pointer to a const x86 exception code. */
4393typedef const X86XCPT *PCX86XCPT;
4394/** The last valid (currently reserved) exception value. */
4395#define X86_XCPT_LAST 0x1f
4396
4397
4398/** @name Trap Error Codes
4399 * @{
4400 */
4401/** External indicator. */
4402#define X86_TRAP_ERR_EXTERNAL 1
4403/** IDT indicator. */
4404#define X86_TRAP_ERR_IDT 2
4405/** Descriptor table indicator - If set LDT, if clear GDT. */
4406#define X86_TRAP_ERR_TI 4
4407/** Mask for getting the selector. */
4408#define X86_TRAP_ERR_SEL_MASK 0xfff8
4409/** Shift for getting the selector table index (C type index). */
4410#define X86_TRAP_ERR_SEL_SHIFT 3
4411/** @} */
4412
4413
4414/** @name \#PF Trap Error Codes
4415 * @{
4416 */
4417/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4418#define X86_TRAP_PF_P RT_BIT_32(0)
4419/** Bit 1 - R/W - Read (clear) or write (set) access. */
4420#define X86_TRAP_PF_RW RT_BIT_32(1)
4421/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4422#define X86_TRAP_PF_US RT_BIT_32(2)
4423/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4424#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4425/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4426#define X86_TRAP_PF_ID RT_BIT_32(4)
4427/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4428#define X86_TRAP_PF_PK RT_BIT_32(5)
4429/** @} */
4430
4431#pragma pack(1)
4432/**
4433 * 16-bit IDTR.
4434 */
4435typedef struct X86IDTR16
4436{
4437 /** Offset. */
4438 uint16_t offSel;
4439 /** Selector. */
4440 uint16_t uSel;
4441} X86IDTR16, *PX86IDTR16;
4442#pragma pack()
4443
4444#pragma pack(1)
4445/**
4446 * 32-bit IDTR/GDTR.
4447 */
4448typedef struct X86XDTR32
4449{
4450 /** Size of the descriptor table. */
4451 uint16_t cb;
4452 /** Address of the descriptor table. */
4453#ifndef VBOX_FOR_DTRACE_LIB
4454 uint32_t uAddr;
4455#else
4456 uint16_t au16Addr[2];
4457#endif
4458} X86XDTR32, *PX86XDTR32;
4459#pragma pack()
4460
4461#pragma pack(1)
4462/**
4463 * 64-bit IDTR/GDTR.
4464 */
4465typedef struct X86XDTR64
4466{
4467 /** Size of the descriptor table. */
4468 uint16_t cb;
4469 /** Address of the descriptor table. */
4470#ifndef VBOX_FOR_DTRACE_LIB
4471 uint64_t uAddr;
4472#else
4473 uint16_t au16Addr[4];
4474#endif
4475} X86XDTR64, *PX86XDTR64;
4476#pragma pack()
4477
4478
4479/** @name ModR/M
4480 * @{ */
4481#define X86_MODRM_RM_MASK UINT8_C(0x07)
4482#define X86_MODRM_REG_MASK UINT8_C(0x38)
4483#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4484#define X86_MODRM_REG_SHIFT 3
4485#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4486#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4487#define X86_MODRM_MOD_SHIFT 6
4488#ifndef VBOX_FOR_DTRACE_LIB
4489AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
4490AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4491AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4492/** @def X86_MODRM_MAKE
4493 * @param a_Mod The mod value (0..3).
4494 * @param a_Reg The register value (0..7).
4495 * @param a_RegMem The register or memory value (0..7). */
4496# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
4497#endif
4498/** @} */
4499
4500/** @name SIB
4501 * @{ */
4502#define X86_SIB_BASE_MASK UINT8_C(0x07)
4503#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4504#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4505#define X86_SIB_INDEX_SHIFT 3
4506#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4507#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4508#define X86_SIB_SCALE_SHIFT 6
4509#ifndef VBOX_FOR_DTRACE_LIB
4510AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
4511AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4512AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4513#endif
4514/** @} */
4515
4516/** @name General register indexes.
4517 * @{ */
4518#define X86_GREG_xAX 0
4519#define X86_GREG_xCX 1
4520#define X86_GREG_xDX 2
4521#define X86_GREG_xBX 3
4522#define X86_GREG_xSP 4
4523#define X86_GREG_xBP 5
4524#define X86_GREG_xSI 6
4525#define X86_GREG_xDI 7
4526#define X86_GREG_x8 8
4527#define X86_GREG_x9 9
4528#define X86_GREG_x10 10
4529#define X86_GREG_x11 11
4530#define X86_GREG_x12 12
4531#define X86_GREG_x13 13
4532#define X86_GREG_x14 14
4533#define X86_GREG_x15 15
4534/** @} */
4535/** General register count. */
4536#define X86_GREG_COUNT 16
4537
4538/** @name X86_SREG_XXX - Segment register indexes.
4539 * @{ */
4540#define X86_SREG_ES 0
4541#define X86_SREG_CS 1
4542#define X86_SREG_SS 2
4543#define X86_SREG_DS 3
4544#define X86_SREG_FS 4
4545#define X86_SREG_GS 5
4546/** @} */
4547/** Segment register count. */
4548#define X86_SREG_COUNT 6
4549
4550
4551/** @name X86_OP_XXX - Prefixes
4552 * @{ */
4553#define X86_OP_PRF_CS UINT8_C(0x2e)
4554#define X86_OP_PRF_SS UINT8_C(0x36)
4555#define X86_OP_PRF_DS UINT8_C(0x3e)
4556#define X86_OP_PRF_ES UINT8_C(0x26)
4557#define X86_OP_PRF_FS UINT8_C(0x64)
4558#define X86_OP_PRF_GS UINT8_C(0x65)
4559#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4560#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4561#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4562#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4563#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4564#define X86_OP_REX_B UINT8_C(0x41)
4565#define X86_OP_REX_X UINT8_C(0x42)
4566#define X86_OP_REX_R UINT8_C(0x44)
4567#define X86_OP_REX_W UINT8_C(0x48)
4568/** @} */
4569
4570
4571/** @} */
4572
4573#endif /* !IPRT_INCLUDED_x86_h */
4574
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette