x86.h@ 85524

Last change on this file since 85524 was 85450, checked in by vboxsync, 5 years ago
HostDrivers/Support: Added reading the SMM address/mask MSRs while reading the rest of the AMD-V MSRs from the host.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 175.3 KB

Line
1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2020 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef IPRT_INCLUDED_x86_h
29	#define IPRT_INCLUDED_x86_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef VBOX_FOR_DTRACE_LIB
35	# include <iprt/types.h>
36	# include <iprt/assert.h>
37	#else
38	# pragma D depends_on library vbox-types.d
39	#endif
40
41	/* Workaround for Solaris sys/regset.h defining CS, DS */
42	#ifdef RT_OS_SOLARIS
43	# undef CS
44	# undef DS
45	#endif
46
47	/** @defgroup grp_rt_x86 x86 Types and Definitions
48	* @ingroup grp_rt
49	* @{
50	*/
51
52	#ifndef VBOX_FOR_DTRACE_LIB
53	/**
54	* EFLAGS Bits.
55	*/
56	typedef struct X86EFLAGSBITS
57	{
58	/** Bit 0 - CF - Carry flag - Status flag. */
59	unsigned u1CF : 1;
60	/** Bit 1 - 1 - Reserved flag. */
61	unsigned u1Reserved0 : 1;
62	/** Bit 2 - PF - Parity flag - Status flag. */
63	unsigned u1PF : 1;
64	/** Bit 3 - 0 - Reserved flag. */
65	unsigned u1Reserved1 : 1;
66	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
67	unsigned u1AF : 1;
68	/** Bit 5 - 0 - Reserved flag. */
69	unsigned u1Reserved2 : 1;
70	/** Bit 6 - ZF - Zero flag - Status flag. */
71	unsigned u1ZF : 1;
72	/** Bit 7 - SF - Signed flag - Status flag. */
73	unsigned u1SF : 1;
74	/** Bit 8 - TF - Trap flag - System flag. */
75	unsigned u1TF : 1;
76	/** Bit 9 - IF - Interrupt flag - System flag. */
77	unsigned u1IF : 1;
78	/** Bit 10 - DF - Direction flag - Control flag. */
79	unsigned u1DF : 1;
80	/** Bit 11 - OF - Overflow flag - Status flag. */
81	unsigned u1OF : 1;
82	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
83	unsigned u2IOPL : 2;
84	/** Bit 14 - NT - Nested task flag - System flag. */
85	unsigned u1NT : 1;
86	/** Bit 15 - 0 - Reserved flag. */
87	unsigned u1Reserved3 : 1;
88	/** Bit 16 - RF - Resume flag - System flag. */
89	unsigned u1RF : 1;
90	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
91	unsigned u1VM : 1;
92	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
93	unsigned u1AC : 1;
94	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
95	unsigned u1VIF : 1;
96	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
97	unsigned u1VIP : 1;
98	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
99	unsigned u1ID : 1;
100	/** Bit 22-31 - 0 - Reserved flag. */
101	unsigned u10Reserved4 : 10;
102	} X86EFLAGSBITS;
103	/** Pointer to EFLAGS bits. */
104	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
105	/** Pointer to const EFLAGS bits. */
106	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
107	#endif /* !VBOX_FOR_DTRACE_LIB */
108
109	/**
110	* EFLAGS.
111	*/
112	typedef union X86EFLAGS
113	{
114	/** The plain unsigned view. */
115	uint32_t u;
116	#ifndef VBOX_FOR_DTRACE_LIB
117	/** The bitfield view. */
118	X86EFLAGSBITS Bits;
119	#endif
120	/** The 8-bit view. */
121	uint8_t au8[4];
122	/** The 16-bit view. */
123	uint16_t au16[2];
124	/** The 32-bit view. */
125	uint32_t au32[1];
126	/** The 32-bit view. */
127	uint32_t u32;
128	} X86EFLAGS;
129	/** Pointer to EFLAGS. */
130	typedef X86EFLAGS *PX86EFLAGS;
131	/** Pointer to const EFLAGS. */
132	typedef const X86EFLAGS *PCX86EFLAGS;
133
134	/**
135	* RFLAGS (32 upper bits are reserved).
136	*/
137	typedef union X86RFLAGS
138	{
139	/** The plain unsigned view. */
140	uint64_t u;
141	#ifndef VBOX_FOR_DTRACE_LIB
142	/** The bitfield view. */
143	X86EFLAGSBITS Bits;
144	#endif
145	/** The 8-bit view. */
146	uint8_t au8[8];
147	/** The 16-bit view. */
148	uint16_t au16[4];
149	/** The 32-bit view. */
150	uint32_t au32[2];
151	/** The 64-bit view. */
152	uint64_t au64[1];
153	/** The 64-bit view. */
154	uint64_t u64;
155	} X86RFLAGS;
156	/** Pointer to RFLAGS. */
157	typedef X86RFLAGS *PX86RFLAGS;
158	/** Pointer to const RFLAGS. */
159	typedef const X86RFLAGS *PCX86RFLAGS;
160
161
162	/** @name EFLAGS
163	* @{
164	*/
165	/** Bit 0 - CF - Carry flag - Status flag. */
166	#define X86_EFL_CF RT_BIT_32(0)
167	#define X86_EFL_CF_BIT 0
168	/** Bit 1 - Reserved, reads as 1. */
169	#define X86_EFL_1 RT_BIT_32(1)
170	/** Bit 2 - PF - Parity flag - Status flag. */
171	#define X86_EFL_PF RT_BIT_32(2)
172	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
173	#define X86_EFL_AF RT_BIT_32(4)
174	#define X86_EFL_AF_BIT 4
175	/** Bit 6 - ZF - Zero flag - Status flag. */
176	#define X86_EFL_ZF RT_BIT_32(6)
177	#define X86_EFL_ZF_BIT 6
178	/** Bit 7 - SF - Signed flag - Status flag. */
179	#define X86_EFL_SF RT_BIT_32(7)
180	#define X86_EFL_SF_BIT 7
181	/** Bit 8 - TF - Trap flag - System flag. */
182	#define X86_EFL_TF RT_BIT_32(8)
183	/** Bit 9 - IF - Interrupt flag - System flag. */
184	#define X86_EFL_IF RT_BIT_32(9)
185	/** Bit 10 - DF - Direction flag - Control flag. */
186	#define X86_EFL_DF RT_BIT_32(10)
187	/** Bit 11 - OF - Overflow flag - Status flag. */
188	#define X86_EFL_OF RT_BIT_32(11)
189	#define X86_EFL_OF_BIT 11
190	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
191	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
192	/** Bit 14 - NT - Nested task flag - System flag. */
193	#define X86_EFL_NT RT_BIT_32(14)
194	/** Bit 16 - RF - Resume flag - System flag. */
195	#define X86_EFL_RF RT_BIT_32(16)
196	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
197	#define X86_EFL_VM RT_BIT_32(17)
198	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
199	#define X86_EFL_AC RT_BIT_32(18)
200	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
201	#define X86_EFL_VIF RT_BIT_32(19)
202	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
203	#define X86_EFL_VIP RT_BIT_32(20)
204	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
205	#define X86_EFL_ID RT_BIT_32(21)
206	/** All live bits. */
207	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
208	/** Read as 1 bits. */
209	#define X86_EFL_RA1_MASK RT_BIT_32(1)
210	/** IOPL shift. */
211	#define X86_EFL_IOPL_SHIFT 12
212	/** The IOPL level from the flags. */
213	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
214	/** Bits restored by popf */
215	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
216	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
217	/** Bits restored by popf */
218	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
219	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
220	/** The status bits commonly updated by arithmetic instructions. */
221	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
222	/** @} */
223
224
225	/** CPUID Feature information - ECX.
226	* CPUID query with EAX=1.
227	*/
228	#ifndef VBOX_FOR_DTRACE_LIB
229	typedef struct X86CPUIDFEATECX
230	{
231	/** Bit 0 - SSE3 - Supports SSE3 or not. */
232	unsigned u1SSE3 : 1;
233	/** Bit 1 - PCLMULQDQ. */
234	unsigned u1PCLMULQDQ : 1;
235	/** Bit 2 - DS Area 64-bit layout. */
236	unsigned u1DTE64 : 1;
237	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
238	unsigned u1Monitor : 1;
239	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
240	unsigned u1CPLDS : 1;
241	/** Bit 5 - VMX - Virtual Machine Technology. */
242	unsigned u1VMX : 1;
243	/** Bit 6 - SMX: Safer Mode Extensions. */
244	unsigned u1SMX : 1;
245	/** Bit 7 - EST - Enh. SpeedStep Tech. */
246	unsigned u1EST : 1;
247	/** Bit 8 - TM2 - Terminal Monitor 2. */
248	unsigned u1TM2 : 1;
249	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
250	unsigned u1SSSE3 : 1;
251	/** Bit 10 - CNTX-ID - L1 Context ID. */
252	unsigned u1CNTXID : 1;
253	/** Bit 11 - Reserved. */
254	unsigned u1Reserved1 : 1;
255	/** Bit 12 - FMA. */
256	unsigned u1FMA : 1;
257	/** Bit 13 - CX16 - CMPXCHG16B. */
258	unsigned u1CX16 : 1;
259	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
260	unsigned u1TPRUpdate : 1;
261	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
262	unsigned u1PDCM : 1;
263	/** Bit 16 - Reserved. */
264	unsigned u1Reserved2 : 1;
265	/** Bit 17 - PCID - Process-context identifiers. */
266	unsigned u1PCID : 1;
267	/** Bit 18 - Direct Cache Access. */
268	unsigned u1DCA : 1;
269	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
270	unsigned u1SSE4_1 : 1;
271	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
272	unsigned u1SSE4_2 : 1;
273	/** Bit 21 - x2APIC. */
274	unsigned u1x2APIC : 1;
275	/** Bit 22 - MOVBE - Supports MOVBE. */
276	unsigned u1MOVBE : 1;
277	/** Bit 23 - POPCNT - Supports POPCNT. */
278	unsigned u1POPCNT : 1;
279	/** Bit 24 - TSC-Deadline. */
280	unsigned u1TSCDEADLINE : 1;
281	/** Bit 25 - AES. */
282	unsigned u1AES : 1;
283	/** Bit 26 - XSAVE - Supports XSAVE. */
284	unsigned u1XSAVE : 1;
285	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
286	unsigned u1OSXSAVE : 1;
287	/** Bit 28 - AVX - Supports AVX instruction extensions. */
288	unsigned u1AVX : 1;
289	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
290	unsigned u1F16C : 1;
291	/** Bit 30 - RDRAND - Supports RDRAND. */
292	unsigned u1RDRAND : 1;
293	/** Bit 31 - Hypervisor present (we're a guest). */
294	unsigned u1HVP : 1;
295	} X86CPUIDFEATECX;
296	#else /* VBOX_FOR_DTRACE_LIB */
297	typedef uint32_t X86CPUIDFEATECX;
298	#endif /* VBOX_FOR_DTRACE_LIB */
299	/** Pointer to CPUID Feature Information - ECX. */
300	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
301	/** Pointer to const CPUID Feature Information - ECX. */
302	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
303
304
305	/** CPUID Feature Information - EDX.
306	* CPUID query with EAX=1.
307	*/
308	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
309	typedef struct X86CPUIDFEATEDX
310	{
311	/** Bit 0 - FPU - x87 FPU on Chip. */
312	unsigned u1FPU : 1;
313	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
314	unsigned u1VME : 1;
315	/** Bit 2 - DE - Debugging extensions. */
316	unsigned u1DE : 1;
317	/** Bit 3 - PSE - Page Size Extension. */
318	unsigned u1PSE : 1;
319	/** Bit 4 - TSC - Time Stamp Counter. */
320	unsigned u1TSC : 1;
321	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
322	unsigned u1MSR : 1;
323	/** Bit 6 - PAE - Physical Address Extension. */
324	unsigned u1PAE : 1;
325	/** Bit 7 - MCE - Machine Check Exception. */
326	unsigned u1MCE : 1;
327	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
328	unsigned u1CX8 : 1;
329	/** Bit 9 - APIC - APIC On-Chip. */
330	unsigned u1APIC : 1;
331	/** Bit 10 - Reserved. */
332	unsigned u1Reserved1 : 1;
333	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
334	unsigned u1SEP : 1;
335	/** Bit 12 - MTRR - Memory Type Range Registers. */
336	unsigned u1MTRR : 1;
337	/** Bit 13 - PGE - PTE Global Bit. */
338	unsigned u1PGE : 1;
339	/** Bit 14 - MCA - Machine Check Architecture. */
340	unsigned u1MCA : 1;
341	/** Bit 15 - CMOV - Conditional Move Instructions. */
342	unsigned u1CMOV : 1;
343	/** Bit 16 - PAT - Page Attribute Table. */
344	unsigned u1PAT : 1;
345	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
346	unsigned u1PSE36 : 1;
347	/** Bit 18 - PSN - Processor Serial Number. */
348	unsigned u1PSN : 1;
349	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
350	unsigned u1CLFSH : 1;
351	/** Bit 20 - Reserved. */
352	unsigned u1Reserved2 : 1;
353	/** Bit 21 - DS - Debug Store. */
354	unsigned u1DS : 1;
355	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
356	unsigned u1ACPI : 1;
357	/** Bit 23 - MMX - Intel MMX 'Technology'. */
358	unsigned u1MMX : 1;
359	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
360	unsigned u1FXSR : 1;
361	/** Bit 25 - SSE - SSE Support. */
362	unsigned u1SSE : 1;
363	/** Bit 26 - SSE2 - SSE2 Support. */
364	unsigned u1SSE2 : 1;
365	/** Bit 27 - SS - Self Snoop. */
366	unsigned u1SS : 1;
367	/** Bit 28 - HTT - Hyper-Threading Technology. */
368	unsigned u1HTT : 1;
369	/** Bit 29 - TM - Thermal Monitor. */
370	unsigned u1TM : 1;
371	/** Bit 30 - Reserved - . */
372	unsigned u1Reserved3 : 1;
373	/** Bit 31 - PBE - Pending Break Enabled. */
374	unsigned u1PBE : 1;
375	} X86CPUIDFEATEDX;
376	#else /* VBOX_FOR_DTRACE_LIB */
377	typedef uint32_t X86CPUIDFEATEDX;
378	#endif /* VBOX_FOR_DTRACE_LIB */
379	/** Pointer to CPUID Feature Information - EDX. */
380	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
381	/** Pointer to const CPUID Feature Information - EDX. */
382	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
383
384	/** @name CPUID Vendor information.
385	* CPUID query with EAX=0.
386	* @{
387	*/
388	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
389	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
390	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
391
392	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
393	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
394	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
395
396	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
397	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
398	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
399
400	#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
401	#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
402	#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
403
404	#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
405	#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
406	#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
407	/** @} */
408
409
410	/** @name CPUID Feature information.
411	* CPUID query with EAX=1.
412	* @{
413	*/
414	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
415	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
416	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
417	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
418	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
419	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
420	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
421	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
422	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
423	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
424	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
425	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
426	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
427	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
428	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
429	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
430	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
431	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
432	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
433	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
434	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
435	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
436	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
437	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
438	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
439	/** ECX Bit 12 - FMA. */
440	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
441	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
442	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
443	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
444	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
445	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
446	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
447	/** ECX Bit 17 - PCID - Process-context identifiers. */
448	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
449	/** ECX Bit 18 - DCA - Direct Cache Access. */
450	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
451	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
452	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
453	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
454	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
455	/** ECX Bit 21 - x2APIC support. */
456	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
457	/** ECX Bit 22 - MOVBE instruction. */
458	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
459	/** ECX Bit 23 - POPCNT instruction. */
460	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
461	/** ECX Bir 24 - TSC-Deadline. */
462	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
463	/** ECX Bit 25 - AES instructions. */
464	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
465	/** ECX Bit 26 - XSAVE instruction. */
466	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
467	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
468	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
469	/** ECX Bit 28 - AVX. */
470	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
471	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
472	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
473	/** ECX Bit 30 - RDRAND instruction. */
474	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
475	/** ECX Bit 31 - Hypervisor Present (software only). */
476	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
477
478
479	/** Bit 0 - FPU - x87 FPU on Chip. */
480	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
481	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
482	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
483	/** Bit 2 - DE - Debugging extensions. */
484	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
485	/** Bit 3 - PSE - Page Size Extension. */
486	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
487	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
488	/** Bit 4 - TSC - Time Stamp Counter. */
489	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
490	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
491	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
492	/** Bit 6 - PAE - Physical Address Extension. */
493	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
494	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
495	/** Bit 7 - MCE - Machine Check Exception. */
496	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
497	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
498	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
499	/** Bit 9 - APIC - APIC On-Chip. */
500	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
501	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
502	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
503	/** Bit 12 - MTRR - Memory Type Range Registers. */
504	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
505	/** Bit 13 - PGE - PTE Global Bit. */
506	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
507	/** Bit 14 - MCA - Machine Check Architecture. */
508	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
509	/** Bit 15 - CMOV - Conditional Move Instructions. */
510	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
511	/** Bit 16 - PAT - Page Attribute Table. */
512	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
513	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
514	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
515	/** Bit 18 - PSN - Processor Serial Number. */
516	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
517	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
518	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
519	/** Bit 21 - DS - Debug Store. */
520	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
521	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
522	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
523	/** Bit 23 - MMX - Intel MMX Technology. */
524	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
525	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
526	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
527	/** Bit 25 - SSE - SSE Support. */
528	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
529	/** Bit 26 - SSE2 - SSE2 Support. */
530	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
531	/** Bit 27 - SS - Self Snoop. */
532	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
533	/** Bit 28 - HTT - Hyper-Threading Technology. */
534	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
535	/** Bit 29 - TM - Therm. Monitor. */
536	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
537	/** Bit 31 - PBE - Pending Break Enabled. */
538	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
539	/** @} */
540
541	/** @name CPUID mwait/monitor information.
542	* CPUID query with EAX=5.
543	* @{
544	*/
545	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
546	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
547	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
548	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
549	/** @} */
550
551
552	/** @name CPUID Structured Extended Feature information.
553	* CPUID query with EAX=7.
554	* @{
555	*/
556	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
557	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
558	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
559	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
560	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
561	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
562	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
563	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
564	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
565	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
566	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
567	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
568	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
569	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
570	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
571	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
572	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
573	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
574	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
575	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
576	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
577	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
578	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
579	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
580	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
581	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
582	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
583	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
584	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
585	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
586	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
587	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
588	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
589	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
590	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
591	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
592	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
593	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
594	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
595	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
596	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
597	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
598	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
599	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
600	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
601	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
602	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
603	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
604	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
605	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
606	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
607	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
608
609	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
610	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
611	/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
612	#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
613	/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
614	#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
615	/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
616	#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
617	/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
618	#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
619	/** ECX Bit 22 - RDPID - Support pread process ID. */
620	#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
621	/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
622	#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
623
624	/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
625	#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
626	/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
627	* IBPB command in IA32_PRED_CMD. */
628	#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
629	/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
630	#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
631	/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
632	#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
633	/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
634	#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
635	/** EDX Bit 31 - SSBD - Supports the SSBD flag in IA32_SPEC_CTRL. */
636	#define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
637
638	/** @} */
639
640
641	/** @name CPUID Extended Feature information.
642	* CPUID query with EAX=0x80000001.
643	* @{
644	*/
645	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
646	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
647
648	/** EDX Bit 11 - SYSCALL/SYSRET. */
649	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
650	/** EDX Bit 20 - No-Execute/Execute-Disable. */
651	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
652	/** EDX Bit 26 - 1 GB large page. */
653	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
654	/** EDX Bit 27 - RDTSCP. */
655	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
656	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
657	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
658	/** @}*/
659
660	/** @name CPUID AMD Feature information.
661	* CPUID query with EAX=0x80000001.
662	* @{
663	*/
664	/** Bit 0 - FPU - x87 FPU on Chip. */
665	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
666	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
667	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
668	/** Bit 2 - DE - Debugging extensions. */
669	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
670	/** Bit 3 - PSE - Page Size Extension. */
671	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
672	/** Bit 4 - TSC - Time Stamp Counter. */
673	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
674	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
675	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
676	/** Bit 6 - PAE - Physical Address Extension. */
677	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
678	/** Bit 7 - MCE - Machine Check Exception. */
679	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
680	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
681	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
682	/** Bit 9 - APIC - APIC On-Chip. */
683	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
684	/** Bit 12 - MTRR - Memory Type Range Registers. */
685	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
686	/** Bit 13 - PGE - PTE Global Bit. */
687	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
688	/** Bit 14 - MCA - Machine Check Architecture. */
689	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
690	/** Bit 15 - CMOV - Conditional Move Instructions. */
691	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
692	/** Bit 16 - PAT - Page Attribute Table. */
693	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
694	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
695	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
696	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
697	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
698	/** Bit 23 - MMX - Intel MMX Technology. */
699	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
700	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
701	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
702	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
703	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
704	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
705	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
706	/** Bit 31 - 3DNOW - AMD 3DNow. */
707	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
708
709	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
710	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
711	/** Bit 2 - SVM - AMD VM extensions. */
712	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
713	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
714	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
715	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
716	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
717	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
718	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
719	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
720	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
721	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
722	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
723	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
724	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
725	/** Bit 9 - OSVW - AMD OS visible workaround. */
726	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
727	/** Bit 10 - IBS - Instruct based sampling. */
728	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
729	/** Bit 11 - XOP - Extended operation support (see APM6). */
730	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
731	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
732	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
733	/** Bit 13 - WDT - AMD Watchdog timer support. */
734	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
735	/** Bit 15 - LWP - Lightweight profiling support. */
736	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
737	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
738	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
739	/** Bit 19 - NodeId - Indicates support for
740	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
741	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
742	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
743	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
744	/** Bit 22 - TopologyExtensions - . */
745	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
746	/** @} */
747
748
749	/** @name CPUID AMD Feature information.
750	* CPUID query with EAX=0x80000007.
751	* @{
752	*/
753	/** Bit 0 - TS - Temperature Sensor. */
754	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
755	/** Bit 1 - FID - Frequency ID Control. */
756	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
757	/** Bit 2 - VID - Voltage ID Control. */
758	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
759	/** Bit 3 - TTP - THERMTRIP. */
760	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
761	/** Bit 4 - TM - Hardware Thermal Control. */
762	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
763	/** Bit 5 - STC - Software Thermal Control. */
764	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
765	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
766	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
767	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
768	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
769	/** Bit 8 - TSCINVAR - TSC Invariant. */
770	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
771	/** Bit 9 - CPB - TSC Invariant. */
772	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
773	/** Bit 10 - EffFreqRO - MPERF/APERF. */
774	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
775	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
776	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
777	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
778	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
779	/** @} */
780
781
782	/** @name CPUID AMD extended feature extensions ID (EBX).
783	* CPUID query with EAX=0x80000008.
784	* @{
785	*/
786	/** Bit 0 - CLZERO - Clear zero instruction. */
787	#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
788	/** Bit 1 - IRPerf - Instructions retired count support. */
789	#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
790	/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
791	#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
792	/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
793	#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
794	/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
795	#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
796	/* AMD pipeline length: 9 feature bits ;-) */
797	/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
798	#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
799	/** Bit 14 - IBRS - Supports the IBRS bit in IA32_SPEC_CTRL. */
800	#define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
801	/** Bit 15 - STIBP - Supports the STIBP bit in IA32_SPEC_CTRL. */
802	#define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
803	/** Bit 16 - IBRS always on mode - IBRS should be set once during boot only. */
804	#define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
805	/** Bit 17 - STIBP always on mode - STIBP should be set once during boot only. */
806	#define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
807	/** Bit 18 - IBRS preferred - IBRS is preferred over software mitigations. */
808	#define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
809	/** Bit 24 - Speculative Store Bypass Disable supported in SPEC_CTL. */
810	#define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
811	/** Bit 25 - Speculative Store Bypass Disable supported in VIRT_SPEC_CTL. */
812	#define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
813	/** Bit 26 - Speculative Store Bypass Disable not required. */
814	#define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
815	/** @} */
816
817
818	/** @name CPUID AMD SVM Feature information.
819	* CPUID query with EAX=0x8000000a.
820	* @{
821	*/
822	/** Bit 0 - NP - Nested Paging supported. */
823	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
824	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
825	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
826	/** Bit 2 - SVML - SVM locking bit supported. */
827	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
828	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
829	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
830	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
831	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
832	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
833	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
834	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
835	* VMCB.TLB_Control is supported. */
836	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
837	/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
838	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
839	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
840	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
841	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
842	* intercept filter cycle count threshold. */
843	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
844	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
845	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
846	/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
847	#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
848	/** Bit 16 - VGIF - Supports virtualized GIF. */
849	#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
850	/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
851	#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
852
853	/** @} */
854
855
856	/** @name CR0
857	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
858	* reserved flags.
859	* @{ */
860	/** Bit 0 - PE - Protection Enabled */
861	#define X86_CR0_PE RT_BIT_32(0)
862	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
863	/** Bit 1 - MP - Monitor Coprocessor */
864	#define X86_CR0_MP RT_BIT_32(1)
865	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
866	/** Bit 2 - EM - Emulation. */
867	#define X86_CR0_EM RT_BIT_32(2)
868	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
869	/** Bit 3 - TS - Task Switch. */
870	#define X86_CR0_TS RT_BIT_32(3)
871	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
872	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
873	#define X86_CR0_ET RT_BIT_32(4)
874	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
875	/** Bit 5 - NE - Numeric error (486+). */
876	#define X86_CR0_NE RT_BIT_32(5)
877	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
878	/** Bit 16 - WP - Write Protect (486+). */
879	#define X86_CR0_WP RT_BIT_32(16)
880	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
881	/** Bit 18 - AM - Alignment Mask (486+). */
882	#define X86_CR0_AM RT_BIT_32(18)
883	#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
884	/** Bit 29 - NW - Not Write-though (486+). */
885	#define X86_CR0_NW RT_BIT_32(29)
886	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
887	/** Bit 30 - WP - Cache Disable (486+). */
888	#define X86_CR0_CD RT_BIT_32(30)
889	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
890	/** Bit 31 - PG - Paging. */
891	#define X86_CR0_PG RT_BIT_32(31)
892	#define X86_CR0_PAGING RT_BIT_32(31)
893	#define X86_CR0_BIT_PG 31 /*< Bit number of X86_CR0_PG /
894	/** @} */
895
896
897	/** @name CR3
898	* @{ */
899	/** Bit 3 - PWT - Page-level Writes Transparent. */
900	#define X86_CR3_PWT RT_BIT_32(3)
901	/** Bit 4 - PCD - Page-level Cache Disable. */
902	#define X86_CR3_PCD RT_BIT_32(4)
903	/** Bits 12-31 - - Page directory page number. */
904	#define X86_CR3_PAGE_MASK (0xfffff000)
905	/** Bits 5-31 - - PAE Page directory page number. */
906	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
907	/** Bits 12-51 - - AMD64 Page directory page number. */
908	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
909	/** @} */
910
911
912	/** @name CR4
913	* @{ */
914	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
915	#define X86_CR4_VME RT_BIT_32(0)
916	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
917	#define X86_CR4_PVI RT_BIT_32(1)
918	/** Bit 2 - TSD - Time Stamp Disable. */
919	#define X86_CR4_TSD RT_BIT_32(2)
920	/** Bit 3 - DE - Debugging Extensions. */
921	#define X86_CR4_DE RT_BIT_32(3)
922	/** Bit 4 - PSE - Page Size Extension. */
923	#define X86_CR4_PSE RT_BIT_32(4)
924	/** Bit 5 - PAE - Physical Address Extension. */
925	#define X86_CR4_PAE RT_BIT_32(5)
926	/** Bit 6 - MCE - Machine-Check Enable. */
927	#define X86_CR4_MCE RT_BIT_32(6)
928	/** Bit 7 - PGE - Page Global Enable. */
929	#define X86_CR4_PGE RT_BIT_32(7)
930	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
931	#define X86_CR4_PCE RT_BIT_32(8)
932	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
933	#define X86_CR4_OSFXSR RT_BIT_32(9)
934	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
935	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
936	/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
937	#define X86_CR4_UMIP RT_BIT_32(11)
938	/** Bit 13 - VMXE - VMX mode is enabled. */
939	#define X86_CR4_VMXE RT_BIT_32(13)
940	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
941	#define X86_CR4_SMXE RT_BIT_32(14)
942	/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
943	#define X86_CR4_FSGSBASE RT_BIT_32(16)
944	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
945	#define X86_CR4_PCIDE RT_BIT_32(17)
946	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
947	* extended states. */
948	#define X86_CR4_OSXSAVE RT_BIT_32(18)
949	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
950	#define X86_CR4_SMEP RT_BIT_32(20)
951	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
952	#define X86_CR4_SMAP RT_BIT_32(21)
953	/** Bit 22 - PKE - Protection Key Enable. */
954	#define X86_CR4_PKE RT_BIT_32(22)
955	/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
956	#define X86_CR4_CET RT_BIT_32(23)
957	/** @} */
958
959
960	/** @name DR6
961	* @{ */
962	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
963	#define X86_DR6_B0 RT_BIT_32(0)
964	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
965	#define X86_DR6_B1 RT_BIT_32(1)
966	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
967	#define X86_DR6_B2 RT_BIT_32(2)
968	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
969	#define X86_DR6_B3 RT_BIT_32(3)
970	/** Mask of all the Bx bits. */
971	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
972	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
973	#define X86_DR6_BD RT_BIT_32(13)
974	/** Bit 14 - BS - Single step */
975	#define X86_DR6_BS RT_BIT_32(14)
976	/** Bit 15 - BT - Task switch. (TSS T bit.) */
977	#define X86_DR6_BT RT_BIT_32(15)
978	/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
979	#define X86_DR6_RTM RT_BIT_32(16)
980	/** Value of DR6 after powerup/reset. */
981	#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
982	/** Bits which must be 1s in DR6. */
983	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
984	/** Bits which must be 1s in DR6, when RTM is supported. */
985	#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
986	/** Bits which must be 0s in DR6. */
987	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
988	/** Bits which must be 0s on writes to DR6. */
989	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
990	/** @} */
991
992	/** Get the DR6.Bx bit for a the given breakpoint. */
993	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
994
995
996	/** @name DR7
997	* @{ */
998	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
999	#define X86_DR7_L0 RT_BIT_32(0)
1000	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
1001	#define X86_DR7_G0 RT_BIT_32(1)
1002	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
1003	#define X86_DR7_L1 RT_BIT_32(2)
1004	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
1005	#define X86_DR7_G1 RT_BIT_32(3)
1006	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
1007	#define X86_DR7_L2 RT_BIT_32(4)
1008	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
1009	#define X86_DR7_G2 RT_BIT_32(5)
1010	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
1011	#define X86_DR7_L3 RT_BIT_32(6)
1012	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
1013	#define X86_DR7_G3 RT_BIT_32(7)
1014	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1015	#define X86_DR7_LE RT_BIT_32(8)
1016	/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1017	#define X86_DR7_GE RT_BIT_32(9)
1018
1019	/** L0, L1, L2, and L3. */
1020	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1021	/** L0, L1, L2, and L3. */
1022	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1023
1024	/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1025	* Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1026	#define X86_DR7_RTM RT_BIT_32(11)
1027	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1028	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1029	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1030	* instruction is executed.
1031	* @see http://www.rcollins.org/secrets/DR7.html */
1032	#define X86_DR7_ICE_IR RT_BIT_32(12)
1033	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1034	* any DR register is accessed. */
1035	#define X86_DR7_GD RT_BIT_32(13)
1036	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1037	* Pentium. */
1038	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1039	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1040	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1041	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
1042	#define X86_DR7_RW0_MASK (3 << 16)
1043	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
1044	#define X86_DR7_LEN0_MASK (3 << 18)
1045	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
1046	#define X86_DR7_RW1_MASK (3 << 20)
1047	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
1048	#define X86_DR7_LEN1_MASK (3 << 22)
1049	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
1050	#define X86_DR7_RW2_MASK (3 << 24)
1051	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
1052	#define X86_DR7_LEN2_MASK (3 << 26)
1053	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
1054	#define X86_DR7_RW3_MASK (3 << 28)
1055	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
1056	#define X86_DR7_LEN3_MASK (3 << 30)
1057
1058	/** Bits which reads as 1s. */
1059	#define X86_DR7_RA1_MASK RT_BIT_32(10)
1060	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1061	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1062	/** Bits which must be 0s when writing to DR7. */
1063	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1064
1065	/** Calcs the L bit of Nth breakpoint.
1066	* @param iBp The breakpoint number [0..3].
1067	*/
1068	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1069
1070	/** Calcs the G bit of Nth breakpoint.
1071	* @param iBp The breakpoint number [0..3].
1072	*/
1073	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1074
1075	/** Calcs the L and G bits of Nth breakpoint.
1076	* @param iBp The breakpoint number [0..3].
1077	*/
1078	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1079
1080	/** @name Read/Write values.
1081	* @{ */
1082	/** Break on instruction fetch only. */
1083	#define X86_DR7_RW_EO UINT32_C(0)
1084	/** Break on write only. */
1085	#define X86_DR7_RW_WO UINT32_C(1)
1086	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1087	#define X86_DR7_RW_IO UINT32_C(2)
1088	/** Break on read or write (but not instruction fetches). */
1089	#define X86_DR7_RW_RW UINT32_C(3)
1090	/** @} */
1091
1092	/** Shifts a X86_DR7_RW_* value to its right place.
1093	* @param iBp The breakpoint number [0..3].
1094	* @param fRw One of the X86_DR7_RW_* value.
1095	*/
1096	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1097
1098	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1099	* one of the X86_DR7_RW_XXX constants).
1100	*
1101	* @returns X86_DR7_RW_XXX
1102	* @param uDR7 DR7 value
1103	* @param iBp The breakpoint number [0..3].
1104	*/
1105	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1106
1107	/** R/W0, R/W1, R/W2, and R/W3. */
1108	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1109
1110	#ifndef VBOX_FOR_DTRACE_LIB
1111	/** Checks if there are any I/O breakpoint types configured in the RW
1112	* registers. Does NOT check if these are enabled, sorry. */
1113	# define X86_DR7_ANY_RW_IO(uDR7) \
1114	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1115	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1116	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1117	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1118	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1119	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1120	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1121	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1122	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1123	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1124	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1125	#endif /* !VBOX_FOR_DTRACE_LIB */
1126
1127	/** @name Length values.
1128	* @{ */
1129	#define X86_DR7_LEN_BYTE UINT32_C(0)
1130	#define X86_DR7_LEN_WORD UINT32_C(1)
1131	#define X86_DR7_LEN_QWORD UINT32_C(2) /*< AMD64 long mode only. /
1132	#define X86_DR7_LEN_DWORD UINT32_C(3)
1133	/** @} */
1134
1135	/** Shifts a X86_DR7_LEN_* value to its right place.
1136	* @param iBp The breakpoint number [0..3].
1137	* @param cb One of the X86_DR7_LEN_* values.
1138	*/
1139	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1140
1141	/** Fetch the breakpoint length bits from the DR7 value.
1142	* @param uDR7 DR7 value
1143	* @param iBp The breakpoint number [0..3].
1144	*/
1145	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1146
1147	/** Mask used to check if any breakpoints are enabled. */
1148	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1149
1150	/** LEN0, LEN1, LEN2, and LEN3. */
1151	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1152	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1153	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1154
1155	/** Value of DR7 after powerup/reset. */
1156	#define X86_DR7_INIT_VAL 0x400
1157	/** @} */
1158
1159
1160	/** @name Machine Specific Registers
1161	* @{
1162	*/
1163	/** Machine check address register (P5). */
1164	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1165	/** Machine check type register (P5). */
1166	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1167	/** Time Stamp Counter. */
1168	#define MSR_IA32_TSC 0x10
1169	#define MSR_IA32_CESR UINT32_C(0x00000011)
1170	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1171	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1172
1173	#define MSR_IA32_PLATFORM_ID 0x17
1174
1175	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1176	# define MSR_IA32_APICBASE 0x1b
1177	/** Local APIC enabled. */
1178	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1179	/** X2APIC enabled (requires the EN bit to be set). */
1180	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1181	/** The processor is the boot strap processor (BSP). */
1182	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1183	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1184	* width. */
1185	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1186	/** The default physical base address of the APIC. */
1187	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1188	/** Gets the physical base address from the MSR. */
1189	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1190	#endif
1191
1192	/** Undocumented intel MSR for reporting thread and core counts.
1193	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1194	* first 16 bits is the thread count. The next 16 bits the core count, except
1195	* on Westmere where it seems it's only the next 4 bits for some reason. */
1196	#define MSR_CORE_THREAD_COUNT 0x35
1197
1198	/** CPU Feature control. */
1199	#define MSR_IA32_FEATURE_CONTROL 0x3A
1200	/** Feature control - Lock MSR from writes (R/W0). */
1201	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1202	/** Feature control - Enable VMX inside SMX operation (R/WL). */
1203	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1204	/** Feature control - Enable VMX outside SMX operation (R/WL). */
1205	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1206	/** Feature control - SENTER local functions enable (R/WL). */
1207	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1208	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1209	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1210	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1211	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1212	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1213	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1214	/** Feature control - SENTER global enable (R/WL). */
1215	#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1216	/** Feature control - SGX launch control enable (R/WL). */
1217	#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1218	/** Feature control - SGX global enable (R/WL). */
1219	#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1220	/** Feature control - LMCE on (R/WL). */
1221	#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1222
1223	/** Per-processor TSC adjust MSR. */
1224	#define MSR_IA32_TSC_ADJUST 0x3B
1225
1226	/** Spectre control register.
1227	* Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1228	#define MSR_IA32_SPEC_CTRL 0x48
1229	/** IBRS - Indirect branch restricted speculation. */
1230	#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1231	/** STIBP - Single thread indirect branch predictors. */
1232	#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1233	/** SSBD - Speculative Store Bypass Disable. */
1234	#define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2)
1235
1236	/** Prediction command register.
1237	* Write only, logical processor scope, no state since write only. */
1238	#define MSR_IA32_PRED_CMD 0x49
1239	/** IBPB - Indirect branch prediction barrie when written as 1. */
1240	#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1241
1242	/** BIOS update trigger (microcode update). */
1243	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1244
1245	/** BIOS update signature (microcode). */
1246	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1247
1248	/** SMM monitor control. */
1249	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1250	/** SMM control - Valid. */
1251	#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1252	/** SMM control - VMXOFF unblocks SMI. */
1253	#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1254	/** SMM control - MSEG base physical address. */
1255	#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1256
1257	/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1258	#define MSR_IA32_SMBASE 0x9E
1259
1260	/** General performance counter no. 0. */
1261	#define MSR_IA32_PMC0 0xC1
1262	/** General performance counter no. 1. */
1263	#define MSR_IA32_PMC1 0xC2
1264	/** General performance counter no. 2. */
1265	#define MSR_IA32_PMC2 0xC3
1266	/** General performance counter no. 3. */
1267	#define MSR_IA32_PMC3 0xC4
1268	/** General performance counter no. 4. */
1269	#define MSR_IA32_PMC4 0xC5
1270	/** General performance counter no. 5. */
1271	#define MSR_IA32_PMC5 0xC6
1272	/** General performance counter no. 6. */
1273	#define MSR_IA32_PMC6 0xC7
1274	/** General performance counter no. 7. */
1275	#define MSR_IA32_PMC7 0xC8
1276
1277	/** Nehalem power control. */
1278	#define MSR_IA32_PLATFORM_INFO 0xCE
1279
1280	/** Get FSB clock status (Intel-specific). */
1281	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1282
1283	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1284	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1285
1286	/** C0 Maximum Frequency Clock Count */
1287	#define MSR_IA32_MPERF 0xE7
1288	/** C0 Actual Frequency Clock Count */
1289	#define MSR_IA32_APERF 0xE8
1290
1291	/** MTRR Capabilities. */
1292	#define MSR_IA32_MTRR_CAP 0xFE
1293
1294	/** Architecture capabilities (bugfixes). */
1295	#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1296	/** CPU is no subject to meltdown problems. */
1297	#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1298	/** CPU has better IBRS and you can leave it on all the time. */
1299	#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1300	/** CPU has return stack buffer (RSB) override. */
1301	#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1302	/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1303	* This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1304	#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1305	/** CPU does not suffer from MDS issues. */
1306	#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
1307
1308	/** Flush command register. */
1309	#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1310	/** Flush the level 1 data cache when this bit is written. */
1311	#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1312
1313	/** Cache control/info. */
1314	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1315
1316	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1317	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1318	* R0 SS == CS + 8
1319	* R3 CS == CS + 16
1320	* R3 SS == CS + 24
1321	*/
1322	#define MSR_IA32_SYSENTER_CS 0x174
1323	/** SYSENTER_ESP - the R0 ESP. */
1324	#define MSR_IA32_SYSENTER_ESP 0x175
1325	/** SYSENTER_EIP - the R0 EIP. */
1326	#define MSR_IA32_SYSENTER_EIP 0x176
1327	#endif
1328
1329	/** Machine Check Global Capabilities Register. */
1330	#define MSR_IA32_MCG_CAP 0x179
1331	/** Machine Check Global Status Register. */
1332	#define MSR_IA32_MCG_STATUS 0x17A
1333	/** Machine Check Global Control Register. */
1334	#define MSR_IA32_MCG_CTRL 0x17B
1335
1336	/** Page Attribute Table. */
1337	#define MSR_IA32_CR_PAT 0x277
1338	/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1339	* "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1340	#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1341
1342	/** Performance event select MSRs. (Intel only) */
1343	#define MSR_IA32_PERFEVTSEL0 0x186
1344	#define MSR_IA32_PERFEVTSEL1 0x187
1345	#define MSR_IA32_PERFEVTSEL2 0x188
1346	#define MSR_IA32_PERFEVTSEL3 0x189
1347
1348	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1349	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1350	* holds a ratio that Apple takes for TSC granularity.
1351	*
1352	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1353	#define MSR_FLEX_RATIO 0x194
1354	/** Performance state value and starting with Intel core more.
1355	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1356	#define MSR_IA32_PERF_STATUS 0x198
1357	#define MSR_IA32_PERF_CTL 0x199
1358	#define MSR_IA32_THERM_STATUS 0x19c
1359
1360	/** Offcore response event select registers. */
1361	#define MSR_OFFCORE_RSP_0 0x1a6
1362	#define MSR_OFFCORE_RSP_1 0x1a7
1363
1364	/** Enable misc. processor features (R/W). */
1365	#define MSR_IA32_MISC_ENABLE 0x1A0
1366	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1367	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1368	/** Automatic Thermal Control Circuit Enable (R/W). */
1369	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1370	/** Performance Monitoring Available (R). */
1371	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1372	/** Branch Trace Storage Unavailable (R/O). */
1373	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1374	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1375	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1376	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1377	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1378	/** If MONITOR/MWAIT is supported (R/W). */
1379	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1380	/** Limit CPUID Maxval to 3 leafs (R/W). */
1381	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1382	/** When set to 1, xTPR messages are disabled (R/W). */
1383	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1384	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1385	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1386
1387	/** Trace/Profile Resource Control (R/W) */
1388	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1389	/** Last branch record. */
1390	#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1391	/** Branch trace flag (single step on branches). */
1392	#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1393	/** Performance monitoring pin control (AMD only). */
1394	#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1395	#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1396	#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1397	#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1398	/** Trace message enable (Intel only). */
1399	#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1400	/** Branch trace store (Intel only). */
1401	#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1402	/** Branch trace interrupt (Intel only). */
1403	#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1404	/** Branch trace off in privileged code (Intel only). */
1405	#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1406	/** Branch trace off in user code (Intel only). */
1407	#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1408	/** Freeze LBR on PMI flag (Intel only). */
1409	#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1410	/** Freeze PERFMON on PMI flag (Intel only). */
1411	#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1412	/** Freeze while SMM enabled (Intel only). */
1413	#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1414	/** Advanced debugging of RTM regions (Intel only). */
1415	#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1416	/** Debug control MSR valid bits (Intel only). */
1417	#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR \| MSR_IA32_DEBUGCTL_BTF \| MSR_IA32_DEBUGCTL_TR \
1418	\| MSR_IA32_DEBUGCTL_BTS \| MSR_IA32_DEBUGCTL_BTINT \| MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1419	\| MSR_IA32_DEBUGCTL_BTS_OFF_USER \| MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1420	\| MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI \| MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1421	\| MSR_IA32_DEBUGCTL_RTM)
1422
1423	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1424	* @{ */
1425	#define MSR_P4_LASTBRANCH_0 0x1db
1426	#define MSR_P4_LASTBRANCH_1 0x1dc
1427	#define MSR_P4_LASTBRANCH_2 0x1dd
1428	#define MSR_P4_LASTBRANCH_3 0x1de
1429
1430	/** LBR Top-of-stack MSR (index to most recent record). */
1431	#define MSR_P4_LASTBRANCH_TOS 0x1da
1432	/** @} */
1433
1434	/** @name Last branch registers for Core 2 and related Xeons.
1435	* @{ */
1436	#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
1437	#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
1438	#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
1439	#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
1440
1441	#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
1442	#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
1443	#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
1444	#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
1445
1446	/** LBR Top-of-stack MSR (index to most recent record). */
1447	#define MSR_CORE2_LASTBRANCH_TOS 0x1c9
1448	/** @} */
1449
1450	/** @name Last branch registers.
1451	* @{ */
1452	#define MSR_LASTBRANCH_0_FROM_IP 0x680
1453	#define MSR_LASTBRANCH_1_FROM_IP 0x681
1454	#define MSR_LASTBRANCH_2_FROM_IP 0x682
1455	#define MSR_LASTBRANCH_3_FROM_IP 0x683
1456	#define MSR_LASTBRANCH_4_FROM_IP 0x684
1457	#define MSR_LASTBRANCH_5_FROM_IP 0x685
1458	#define MSR_LASTBRANCH_6_FROM_IP 0x686
1459	#define MSR_LASTBRANCH_7_FROM_IP 0x687
1460	#define MSR_LASTBRANCH_8_FROM_IP 0x688
1461	#define MSR_LASTBRANCH_9_FROM_IP 0x689
1462	#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1463	#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1464	#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1465	#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1466	#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1467	#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1468	#define MSR_LASTBRANCH_16_FROM_IP 0x690
1469	#define MSR_LASTBRANCH_17_FROM_IP 0x691
1470	#define MSR_LASTBRANCH_18_FROM_IP 0x692
1471	#define MSR_LASTBRANCH_19_FROM_IP 0x693
1472	#define MSR_LASTBRANCH_20_FROM_IP 0x694
1473	#define MSR_LASTBRANCH_21_FROM_IP 0x695
1474	#define MSR_LASTBRANCH_22_FROM_IP 0x696
1475	#define MSR_LASTBRANCH_23_FROM_IP 0x697
1476	#define MSR_LASTBRANCH_24_FROM_IP 0x698
1477	#define MSR_LASTBRANCH_25_FROM_IP 0x699
1478	#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1479	#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1480	#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1481	#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1482	#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1483	#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1484
1485	#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1486	#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1487	#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1488	#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1489	#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1490	#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1491	#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1492	#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1493	#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1494	#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1495	#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1496	#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1497	#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1498	#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1499	#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1500	#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1501	#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1502	#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1503	#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1504	#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1505	#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1506	#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1507	#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1508	#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1509	#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1510	#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1511	#define MSR_LASTBRANCH_26_TO_IP 0x6da
1512	#define MSR_LASTBRANCH_27_TO_IP 0x6db
1513	#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1514	#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1515	#define MSR_LASTBRANCH_30_TO_IP 0x6de
1516	#define MSR_LASTBRANCH_31_TO_IP 0x6df
1517
1518	/** LBR Top-of-stack MSR (index to most recent record). */
1519	#define MSR_LASTBRANCH_TOS 0x1c9
1520	/** @} */
1521
1522	/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
1523	#define MSR_IA32_TSX_CTRL 0x122
1524
1525	/** Variable range MTRRs.
1526	* @{ */
1527	#define MSR_IA32_MTRR_PHYSBASE0 0x200
1528	#define MSR_IA32_MTRR_PHYSMASK0 0x201
1529	#define MSR_IA32_MTRR_PHYSBASE1 0x202
1530	#define MSR_IA32_MTRR_PHYSMASK1 0x203
1531	#define MSR_IA32_MTRR_PHYSBASE2 0x204
1532	#define MSR_IA32_MTRR_PHYSMASK2 0x205
1533	#define MSR_IA32_MTRR_PHYSBASE3 0x206
1534	#define MSR_IA32_MTRR_PHYSMASK3 0x207
1535	#define MSR_IA32_MTRR_PHYSBASE4 0x208
1536	#define MSR_IA32_MTRR_PHYSMASK4 0x209
1537	#define MSR_IA32_MTRR_PHYSBASE5 0x20a
1538	#define MSR_IA32_MTRR_PHYSMASK5 0x20b
1539	#define MSR_IA32_MTRR_PHYSBASE6 0x20c
1540	#define MSR_IA32_MTRR_PHYSMASK6 0x20d
1541	#define MSR_IA32_MTRR_PHYSBASE7 0x20e
1542	#define MSR_IA32_MTRR_PHYSMASK7 0x20f
1543	#define MSR_IA32_MTRR_PHYSBASE8 0x210
1544	#define MSR_IA32_MTRR_PHYSMASK8 0x211
1545	#define MSR_IA32_MTRR_PHYSBASE9 0x212
1546	#define MSR_IA32_MTRR_PHYSMASK9 0x213
1547	/** @} */
1548
1549	/** Fixed range MTRRs.
1550	* @{ */
1551	#define MSR_IA32_MTRR_FIX64K_00000 0x250
1552	#define MSR_IA32_MTRR_FIX16K_80000 0x258
1553	#define MSR_IA32_MTRR_FIX16K_A0000 0x259
1554	#define MSR_IA32_MTRR_FIX4K_C0000 0x268
1555	#define MSR_IA32_MTRR_FIX4K_C8000 0x269
1556	#define MSR_IA32_MTRR_FIX4K_D0000 0x26a
1557	#define MSR_IA32_MTRR_FIX4K_D8000 0x26b
1558	#define MSR_IA32_MTRR_FIX4K_E0000 0x26c
1559	#define MSR_IA32_MTRR_FIX4K_E8000 0x26d
1560	#define MSR_IA32_MTRR_FIX4K_F0000 0x26e
1561	#define MSR_IA32_MTRR_FIX4K_F8000 0x26f
1562	/** @} */
1563
1564	/** MTRR Default Range. */
1565	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1566
1567	/** Global performance counter control facilities (Intel only). */
1568	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1569	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1570	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1571
1572	/** Precise Event Based sampling (Intel only). */
1573	#define MSR_IA32_PEBS_ENABLE 0x3F1
1574
1575	#define MSR_IA32_MC0_CTL 0x400
1576	#define MSR_IA32_MC0_STATUS 0x401
1577
1578	/** Basic VMX information. */
1579	#define MSR_IA32_VMX_BASIC 0x480
1580	/** Allowed settings for pin-based VM execution controls. */
1581	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1582	/** Allowed settings for proc-based VM execution controls. */
1583	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1584	/** Allowed settings for the VM-exit controls. */
1585	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1586	/** Allowed settings for the VM-entry controls. */
1587	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1588	/** Misc VMX info. */
1589	#define MSR_IA32_VMX_MISC 0x485
1590	/** Fixed cleared bits in CR0. */
1591	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1592	/** Fixed set bits in CR0. */
1593	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1594	/** Fixed cleared bits in CR4. */
1595	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1596	/** Fixed set bits in CR4. */
1597	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1598	/** Information for enumerating fields in the VMCS. */
1599	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1600	/** Allowed settings for secondary proc-based VM execution controls */
1601	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1602	/** EPT capabilities. */
1603	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1604	/** Allowed settings of all pin-based VM execution controls. */
1605	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1606	/** Allowed settings of all proc-based VM execution controls. */
1607	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1608	/** Allowed settings of all VMX exit controls. */
1609	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1610	/** Allowed settings of all VMX entry controls. */
1611	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1612	/** Allowed settings for the VM-function controls. */
1613	#define MSR_IA32_VMX_VMFUNC 0x491
1614
1615	/** Intel PT - Enable and control for trace packet generation. */
1616	#define MSR_IA32_RTIT_CTL 0x570
1617
1618	/** DS Save Area (R/W). */
1619	#define MSR_IA32_DS_AREA 0x600
1620	/** Running Average Power Limit (RAPL) power units. */
1621	#define MSR_RAPL_POWER_UNIT 0x606
1622	/** Package C3 Interrupt Response Limit. */
1623	#define MSR_PKGC3_IRTL 0x60a
1624	/** Package C6/C7S Interrupt Response Limit 1. */
1625	#define MSR_PKGC_IRTL1 0x60b
1626	/** Package C6/C7S Interrupt Response Limit 2. */
1627	#define MSR_PKGC_IRTL2 0x60c
1628	/** Package C2 Residency Counter. */
1629	#define MSR_PKG_C2_RESIDENCY 0x60d
1630	/** PKG RAPL Power Limit Control. */
1631	#define MSR_PKG_POWER_LIMIT 0x610
1632	/** PKG Energy Status. */
1633	#define MSR_PKG_ENERGY_STATUS 0x611
1634	/** PKG Perf Status. */
1635	#define MSR_PKG_PERF_STATUS 0x613
1636	/** PKG RAPL Parameters. */
1637	#define MSR_PKG_POWER_INFO 0x614
1638	/** DRAM RAPL Power Limit Control. */
1639	#define MSR_DRAM_POWER_LIMIT 0x618
1640	/** DRAM Energy Status. */
1641	#define MSR_DRAM_ENERGY_STATUS 0x619
1642	/** DRAM Performance Throttling Status. */
1643	#define MSR_DRAM_PERF_STATUS 0x61b
1644	/** DRAM RAPL Parameters. */
1645	#define MSR_DRAM_POWER_INFO 0x61c
1646	/** Package C10 Residency Counter. */
1647	#define MSR_PKG_C10_RESIDENCY 0x632
1648	/** PP0 Energy Status. */
1649	#define MSR_PP0_ENERGY_STATUS 0x639
1650	/** PP1 Energy Status. */
1651	#define MSR_PP1_ENERGY_STATUS 0x641
1652	/** Turbo Activation Ratio. */
1653	#define MSR_TURBO_ACTIVATION_RATIO 0x64c
1654	/** Core Performance Limit Reasons. */
1655	#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
1656
1657	/** X2APIC MSR range start. */
1658	#define MSR_IA32_X2APIC_START 0x800
1659	/** X2APIC MSR - APIC ID Register. */
1660	#define MSR_IA32_X2APIC_ID 0x802
1661	/** X2APIC MSR - APIC Version Register. */
1662	#define MSR_IA32_X2APIC_VERSION 0x803
1663	/** X2APIC MSR - Task Priority Register. */
1664	#define MSR_IA32_X2APIC_TPR 0x808
1665	/** X2APIC MSR - Processor Priority register. */
1666	#define MSR_IA32_X2APIC_PPR 0x80A
1667	/** X2APIC MSR - End Of Interrupt register. */
1668	#define MSR_IA32_X2APIC_EOI 0x80B
1669	/** X2APIC MSR - Logical Destination Register. */
1670	#define MSR_IA32_X2APIC_LDR 0x80D
1671	/** X2APIC MSR - Spurious Interrupt Vector Register. */
1672	#define MSR_IA32_X2APIC_SVR 0x80F
1673	/** X2APIC MSR - In-service Register (bits 31:0). */
1674	#define MSR_IA32_X2APIC_ISR0 0x810
1675	/** X2APIC MSR - In-service Register (bits 63:32). */
1676	#define MSR_IA32_X2APIC_ISR1 0x811
1677	/** X2APIC MSR - In-service Register (bits 95:64). */
1678	#define MSR_IA32_X2APIC_ISR2 0x812
1679	/** X2APIC MSR - In-service Register (bits 127:96). */
1680	#define MSR_IA32_X2APIC_ISR3 0x813
1681	/** X2APIC MSR - In-service Register (bits 159:128). */
1682	#define MSR_IA32_X2APIC_ISR4 0x814
1683	/** X2APIC MSR - In-service Register (bits 191:160). */
1684	#define MSR_IA32_X2APIC_ISR5 0x815
1685	/** X2APIC MSR - In-service Register (bits 223:192). */
1686	#define MSR_IA32_X2APIC_ISR6 0x816
1687	/** X2APIC MSR - In-service Register (bits 255:224). */
1688	#define MSR_IA32_X2APIC_ISR7 0x817
1689	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1690	#define MSR_IA32_X2APIC_TMR0 0x818
1691	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1692	#define MSR_IA32_X2APIC_TMR1 0x819
1693	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1694	#define MSR_IA32_X2APIC_TMR2 0x81A
1695	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1696	#define MSR_IA32_X2APIC_TMR3 0x81B
1697	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1698	#define MSR_IA32_X2APIC_TMR4 0x81C
1699	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1700	#define MSR_IA32_X2APIC_TMR5 0x81D
1701	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1702	#define MSR_IA32_X2APIC_TMR6 0x81E
1703	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1704	#define MSR_IA32_X2APIC_TMR7 0x81F
1705	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1706	#define MSR_IA32_X2APIC_IRR0 0x820
1707	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1708	#define MSR_IA32_X2APIC_IRR1 0x821
1709	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1710	#define MSR_IA32_X2APIC_IRR2 0x822
1711	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1712	#define MSR_IA32_X2APIC_IRR3 0x823
1713	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1714	#define MSR_IA32_X2APIC_IRR4 0x824
1715	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1716	#define MSR_IA32_X2APIC_IRR5 0x825
1717	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1718	#define MSR_IA32_X2APIC_IRR6 0x826
1719	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1720	#define MSR_IA32_X2APIC_IRR7 0x827
1721	/** X2APIC MSR - Error Status Register. */
1722	#define MSR_IA32_X2APIC_ESR 0x828
1723	/** X2APIC MSR - LVT CMCI Register. */
1724	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1725	/** X2APIC MSR - Interrupt Command Register. */
1726	#define MSR_IA32_X2APIC_ICR 0x830
1727	/** X2APIC MSR - LVT Timer Register. */
1728	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1729	/** X2APIC MSR - LVT Thermal Sensor Register. */
1730	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1731	/** X2APIC MSR - LVT Performance Counter Register. */
1732	#define MSR_IA32_X2APIC_LVT_PERF 0x834
1733	/** X2APIC MSR - LVT LINT0 Register. */
1734	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1735	/** X2APIC MSR - LVT LINT1 Register. */
1736	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1737	/** X2APIC MSR - LVT Error Register . */
1738	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1739	/** X2APIC MSR - Timer Initial Count Register. */
1740	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1741	/** X2APIC MSR - Timer Current Count Register. */
1742	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1743	/** X2APIC MSR - Timer Divide Configuration Register. */
1744	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1745	/** X2APIC MSR - Self IPI. */
1746	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1747	/** X2APIC MSR range end. */
1748	#define MSR_IA32_X2APIC_END 0x8FF
1749	/** X2APIC MSR - LVT start range. */
1750	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1751	/** X2APIC MSR - LVT end range (inclusive). */
1752	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1753
1754	/** K6 EFER - Extended Feature Enable Register. */
1755	#define MSR_K6_EFER UINT32_C(0xc0000080)
1756	/** @todo document EFER */
1757	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1758	#define MSR_K6_EFER_SCE RT_BIT_32(0)
1759	/** Bit 8 - LME - Long mode enabled. (R/W) */
1760	#define MSR_K6_EFER_LME RT_BIT_32(8)
1761	#define MSR_K6_EFER_BIT_LME 8 /*< Bit number of MSR_K6_EFER_LME /
1762	/** Bit 10 - LMA - Long mode active. (R) */
1763	#define MSR_K6_EFER_LMA RT_BIT_32(10)
1764	#define MSR_K6_EFER_BIT_LMA 10 /*< Bit number of MSR_K6_EFER_LMA /
1765	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1766	#define MSR_K6_EFER_NXE RT_BIT_32(11)
1767	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
1768	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1769	#define MSR_K6_EFER_SVME RT_BIT_32(12)
1770	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1771	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1772	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1773	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1774	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1775	#define MSR_K6_EFER_TCE RT_BIT_32(15)
1776	/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
1777	#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
1778
1779	/** K6 STAR - SYSCALL/RET targets. */
1780	#define MSR_K6_STAR UINT32_C(0xc0000081)
1781	/** Shift value for getting the SYSRET CS and SS value. */
1782	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1783	/** Shift value for getting the SYSCALL CS and SS value. */
1784	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1785	/** Selector mask for use after shifting. */
1786	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1787	/** The mask which give the SYSCALL EIP. */
1788	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1789	/** K6 WHCR - Write Handling Control Register. */
1790	#define MSR_K6_WHCR UINT32_C(0xc0000082)
1791	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1792	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1793	/** K6 PSOR - Processor State Observability Register. */
1794	#define MSR_K6_PSOR UINT32_C(0xc0000087)
1795	/** K6 PFIR - Page Flush/Invalidate Register. */
1796	#define MSR_K6_PFIR UINT32_C(0xc0000088)
1797
1798	/** Performance counter MSRs. (AMD only) */
1799	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1800	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1801	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1802	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1803	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1804	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1805	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1806	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1807
1808	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1809	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1810	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1811	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1812	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1813	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1814	/** K8 FS.base - The 64-bit base FS register. */
1815	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1816	/** K8 GS.base - The 64-bit base GS register. */
1817	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1818	/** K8 KernelGSbase - Used with SWAPGS. */
1819	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1820	/** K8 TSC_AUX - Used with RDTSCP. */
1821	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1822	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1823	#define MSR_K8_HWCR UINT32_C(0xc0010015)
1824	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1825	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1826	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1827	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1828	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1829	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1830
1831	/** SMM MSRs. */
1832	#define MSR_K7_SMBASE UINT32_C(0xc0010111)
1833	#define MSR_K7_SMM_ADDR UINT32_C(0xc0010112)
1834	#define MSR_K7_SMM_MASK UINT32_C(0xc0010113)
1835
1836	/** North bridge config? See BIOS & Kernel dev guides for
1837	* details. */
1838	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1839
1840	/** Hypertransport interrupt pending register.
1841	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1842	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1843
1844	/** SVM Control. */
1845	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1846	/** Disables HDT (Hardware Debug Tool) and certain internal debug
1847	* features. */
1848	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1849	/** If set, non-intercepted INIT signals are converted to \#SX
1850	* exceptions. */
1851	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1852	/** Disables A20 masking. */
1853	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1854	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1855	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1856	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1857	* clear, EFER.SVME can be written normally. */
1858	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1859
1860	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1861	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1862	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1863	* host state during world switch. */
1864	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1865
1866	/** Virtualized speculation control for AMD processors.
1867	*
1868	* Unified interface among different CPU generations.
1869	* The VMM will set any architectural MSRs based on the CPU.
1870	* See "White Paper: AMD64 Technology Speculative Store Bypass Disable 5.21.18"
1871	* (12441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf) */
1872	#define MSR_AMD_VIRT_SPEC_CTL UINT32_C(0xc001011f)
1873	/** Speculative Store Bypass Disable. */
1874	# define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
1875
1876	/** @} */
1877
1878
1879	/** @name Page Table / Directory / Directory Pointers / L4.
1880	* @{
1881	*/
1882
1883	/** Page table/directory entry as an unsigned integer. */
1884	typedef uint32_t X86PGUINT;
1885	/** Pointer to a page table/directory table entry as an unsigned integer. */
1886	typedef X86PGUINT *PX86PGUINT;
1887	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1888	typedef X86PGUINT const *PCX86PGUINT;
1889
1890	/** Number of entries in a 32-bit PT/PD. */
1891	#define X86_PG_ENTRIES 1024
1892
1893
1894	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1895	typedef uint64_t X86PGPAEUINT;
1896	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1897	typedef X86PGPAEUINT *PX86PGPAEUINT;
1898	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1899	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1900
1901	/** Number of entries in a PAE PT/PD. */
1902	#define X86_PG_PAE_ENTRIES 512
1903	/** Number of entries in a PAE PDPT. */
1904	#define X86_PG_PAE_PDPE_ENTRIES 4
1905
1906	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1907	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1908	/** Number of entries in an AMD64 PDPT.
1909	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1910	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1911
1912	/** The size of a default page. */
1913	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1914	/** The page shift of a default page. */
1915	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1916	/** The default page offset mask. */
1917	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1918	/** The default page base mask for virtual addresses. */
1919	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1920	/** The default page base mask for virtual addresses - 32bit version. */
1921	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1922
1923	/** The size of a 4KB page. */
1924	#define X86_PAGE_4K_SIZE _4K
1925	/** The page shift of a 4KB page. */
1926	#define X86_PAGE_4K_SHIFT 12
1927	/** The 4KB page offset mask. */
1928	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1929	/** The 4KB page base mask for virtual addresses. */
1930	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1931	/** The 4KB page base mask for virtual addresses - 32bit version. */
1932	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1933
1934	/** The size of a 2MB page. */
1935	#define X86_PAGE_2M_SIZE _2M
1936	/** The page shift of a 2MB page. */
1937	#define X86_PAGE_2M_SHIFT 21
1938	/** The 2MB page offset mask. */
1939	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1940	/** The 2MB page base mask for virtual addresses. */
1941	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1942	/** The 2MB page base mask for virtual addresses - 32bit version. */
1943	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1944
1945	/** The size of a 4MB page. */
1946	#define X86_PAGE_4M_SIZE _4M
1947	/** The page shift of a 4MB page. */
1948	#define X86_PAGE_4M_SHIFT 22
1949	/** The 4MB page offset mask. */
1950	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1951	/** The 4MB page base mask for virtual addresses. */
1952	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1953	/** The 4MB page base mask for virtual addresses - 32bit version. */
1954	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1955
1956	/** The size of a 1GB page. */
1957	#define X86_PAGE_1G_SIZE _1G
1958	/** The page shift of a 1GB page. */
1959	#define X86_PAGE_1G_SHIFT 30
1960	/** The 1GB page offset mask. */
1961	#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
1962	/** The 1GB page base mask for virtual addresses. */
1963	#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
1964
1965	/**
1966	* Check if the given address is canonical.
1967	*/
1968	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1969
1970
1971	/** @name Page Table Entry
1972	* @{
1973	*/
1974	/** Bit 0 - P - Present bit. */
1975	#define X86_PTE_BIT_P 0
1976	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1977	#define X86_PTE_BIT_RW 1
1978	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1979	#define X86_PTE_BIT_US 2
1980	/** Bit 3 - PWT - Page level write thru bit. */
1981	#define X86_PTE_BIT_PWT 3
1982	/** Bit 4 - PCD - Page level cache disable bit. */
1983	#define X86_PTE_BIT_PCD 4
1984	/** Bit 5 - A - Access bit. */
1985	#define X86_PTE_BIT_A 5
1986	/** Bit 6 - D - Dirty bit. */
1987	#define X86_PTE_BIT_D 6
1988	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
1989	#define X86_PTE_BIT_PAT 7
1990	/** Bit 8 - G - Global flag. */
1991	#define X86_PTE_BIT_G 8
1992	/** Bits 63 - NX - PAE/LM - No execution flag. */
1993	#define X86_PTE_PAE_BIT_NX 63
1994
1995	/** Bit 0 - P - Present bit mask. */
1996	#define X86_PTE_P RT_BIT_32(0)
1997	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
1998	#define X86_PTE_RW RT_BIT_32(1)
1999	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
2000	#define X86_PTE_US RT_BIT_32(2)
2001	/** Bit 3 - PWT - Page level write thru bit mask. */
2002	#define X86_PTE_PWT RT_BIT_32(3)
2003	/** Bit 4 - PCD - Page level cache disable bit mask. */
2004	#define X86_PTE_PCD RT_BIT_32(4)
2005	/** Bit 5 - A - Access bit mask. */
2006	#define X86_PTE_A RT_BIT_32(5)
2007	/** Bit 6 - D - Dirty bit mask. */
2008	#define X86_PTE_D RT_BIT_32(6)
2009	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
2010	#define X86_PTE_PAT RT_BIT_32(7)
2011	/** Bit 8 - G - Global bit mask. */
2012	#define X86_PTE_G RT_BIT_32(8)
2013
2014	/** Bits 9-11 - - Available for use to system software. */
2015	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2016	/** Bits 12-31 - - Physical Page number of the next level. */
2017	#define X86_PTE_PG_MASK ( 0xfffff000 )
2018
2019	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2020	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2021	/** Bits 63 - NX - PAE/LM - No execution flag. */
2022	#define X86_PTE_PAE_NX RT_BIT_64(63)
2023	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
2024	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
2025	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
2026	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
2027	/** No bits - - LM - MBZ bits when NX is active. */
2028	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
2029	/** Bits 63 - - LM - MBZ bits when no NX. */
2030	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
2031
2032	/**
2033	* Page table entry.
2034	*/
2035	typedef struct X86PTEBITS
2036	{
2037	/** Flags whether(=1) or not the page is present. */
2038	uint32_t u1Present : 1;
2039	/** Read(=0) / Write(=1) flag. */
2040	uint32_t u1Write : 1;
2041	/** User(=1) / Supervisor (=0) flag. */
2042	uint32_t u1User : 1;
2043	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2044	uint32_t u1WriteThru : 1;
2045	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2046	uint32_t u1CacheDisable : 1;
2047	/** Accessed flag.
2048	* Indicates that the page have been read or written to. */
2049	uint32_t u1Accessed : 1;
2050	/** Dirty flag.
2051	* Indicates that the page has been written to. */
2052	uint32_t u1Dirty : 1;
2053	/** Reserved / If PAT enabled, bit 2 of the index. */
2054	uint32_t u1PAT : 1;
2055	/** Global flag. (Ignored in all but final level.) */
2056	uint32_t u1Global : 1;
2057	/** Available for use to system software. */
2058	uint32_t u3Available : 3;
2059	/** Physical Page number of the next level. */
2060	uint32_t u20PageNo : 20;
2061	} X86PTEBITS;
2062	#ifndef VBOX_FOR_DTRACE_LIB
2063	AssertCompileSize(X86PTEBITS, 4);
2064	#endif
2065	/** Pointer to a page table entry. */
2066	typedef X86PTEBITS *PX86PTEBITS;
2067	/** Pointer to a const page table entry. */
2068	typedef const X86PTEBITS *PCX86PTEBITS;
2069
2070	/**
2071	* Page table entry.
2072	*/
2073	typedef union X86PTE
2074	{
2075	/** Unsigned integer view */
2076	X86PGUINT u;
2077	/** Bit field view. */
2078	X86PTEBITS n;
2079	/** 32-bit view. */
2080	uint32_t au32[1];
2081	/** 16-bit view. */
2082	uint16_t au16[2];
2083	/** 8-bit view. */
2084	uint8_t au8[4];
2085	} X86PTE;
2086	#ifndef VBOX_FOR_DTRACE_LIB
2087	AssertCompileSize(X86PTE, 4);
2088	#endif
2089	/** Pointer to a page table entry. */
2090	typedef X86PTE *PX86PTE;
2091	/** Pointer to a const page table entry. */
2092	typedef const X86PTE *PCX86PTE;
2093
2094
2095	/**
2096	* PAE page table entry.
2097	*/
2098	typedef struct X86PTEPAEBITS
2099	{
2100	/** Flags whether(=1) or not the page is present. */
2101	uint32_t u1Present : 1;
2102	/** Read(=0) / Write(=1) flag. */
2103	uint32_t u1Write : 1;
2104	/** User(=1) / Supervisor(=0) flag. */
2105	uint32_t u1User : 1;
2106	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2107	uint32_t u1WriteThru : 1;
2108	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2109	uint32_t u1CacheDisable : 1;
2110	/** Accessed flag.
2111	* Indicates that the page have been read or written to. */
2112	uint32_t u1Accessed : 1;
2113	/** Dirty flag.
2114	* Indicates that the page has been written to. */
2115	uint32_t u1Dirty : 1;
2116	/** Reserved / If PAT enabled, bit 2 of the index. */
2117	uint32_t u1PAT : 1;
2118	/** Global flag. (Ignored in all but final level.) */
2119	uint32_t u1Global : 1;
2120	/** Available for use to system software. */
2121	uint32_t u3Available : 3;
2122	/** Physical Page number of the next level - Low Part. Don't use this. */
2123	uint32_t u20PageNoLow : 20;
2124	/** Physical Page number of the next level - High Part. Don't use this. */
2125	uint32_t u20PageNoHigh : 20;
2126	/** MBZ bits */
2127	uint32_t u11Reserved : 11;
2128	/** No Execute flag. */
2129	uint32_t u1NoExecute : 1;
2130	} X86PTEPAEBITS;
2131	#ifndef VBOX_FOR_DTRACE_LIB
2132	AssertCompileSize(X86PTEPAEBITS, 8);
2133	#endif
2134	/** Pointer to a page table entry. */
2135	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2136	/** Pointer to a page table entry. */
2137	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2138
2139	/**
2140	* PAE Page table entry.
2141	*/
2142	typedef union X86PTEPAE
2143	{
2144	/** Unsigned integer view */
2145	X86PGPAEUINT u;
2146	/** Bit field view. */
2147	X86PTEPAEBITS n;
2148	/** 32-bit view. */
2149	uint32_t au32[2];
2150	/** 16-bit view. */
2151	uint16_t au16[4];
2152	/** 8-bit view. */
2153	uint8_t au8[8];
2154	} X86PTEPAE;
2155	#ifndef VBOX_FOR_DTRACE_LIB
2156	AssertCompileSize(X86PTEPAE, 8);
2157	#endif
2158	/** Pointer to a PAE page table entry. */
2159	typedef X86PTEPAE *PX86PTEPAE;
2160	/** Pointer to a const PAE page table entry. */
2161	typedef const X86PTEPAE *PCX86PTEPAE;
2162	/** @} */
2163
2164	/**
2165	* Page table.
2166	*/
2167	typedef struct X86PT
2168	{
2169	/** PTE Array. */
2170	X86PTE a[X86_PG_ENTRIES];
2171	} X86PT;
2172	#ifndef VBOX_FOR_DTRACE_LIB
2173	AssertCompileSize(X86PT, 4096);
2174	#endif
2175	/** Pointer to a page table. */
2176	typedef X86PT *PX86PT;
2177	/** Pointer to a const page table. */
2178	typedef const X86PT *PCX86PT;
2179
2180	/** The page shift to get the PT index. */
2181	#define X86_PT_SHIFT 12
2182	/** The PT index mask (apply to a shifted page address). */
2183	#define X86_PT_MASK 0x3ff
2184
2185
2186	/**
2187	* Page directory.
2188	*/
2189	typedef struct X86PTPAE
2190	{
2191	/** PTE Array. */
2192	X86PTEPAE a[X86_PG_PAE_ENTRIES];
2193	} X86PTPAE;
2194	#ifndef VBOX_FOR_DTRACE_LIB
2195	AssertCompileSize(X86PTPAE, 4096);
2196	#endif
2197	/** Pointer to a page table. */
2198	typedef X86PTPAE *PX86PTPAE;
2199	/** Pointer to a const page table. */
2200	typedef const X86PTPAE *PCX86PTPAE;
2201
2202	/** The page shift to get the PA PTE index. */
2203	#define X86_PT_PAE_SHIFT 12
2204	/** The PAE PT index mask (apply to a shifted page address). */
2205	#define X86_PT_PAE_MASK 0x1ff
2206
2207
2208	/** @name 4KB Page Directory Entry
2209	* @{
2210	*/
2211	/** Bit 0 - P - Present bit. */
2212	#define X86_PDE_P RT_BIT_32(0)
2213	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2214	#define X86_PDE_RW RT_BIT_32(1)
2215	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2216	#define X86_PDE_US RT_BIT_32(2)
2217	/** Bit 3 - PWT - Page level write thru bit. */
2218	#define X86_PDE_PWT RT_BIT_32(3)
2219	/** Bit 4 - PCD - Page level cache disable bit. */
2220	#define X86_PDE_PCD RT_BIT_32(4)
2221	/** Bit 5 - A - Access bit. */
2222	#define X86_PDE_A RT_BIT_32(5)
2223	/** Bit 7 - PS - Page size attribute.
2224	* Clear mean 4KB pages, set means large pages (2/4MB). */
2225	#define X86_PDE_PS RT_BIT_32(7)
2226	/** Bits 9-11 - - Available for use to system software. */
2227	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2228	/** Bits 12-31 - - Physical Page number of the next level. */
2229	#define X86_PDE_PG_MASK ( 0xfffff000 )
2230
2231	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2232	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2233	/** Bits 63 - NX - PAE/LM - No execution flag. */
2234	#define X86_PDE_PAE_NX RT_BIT_64(63)
2235	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2236	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2237	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2238	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2239	/** Bit 7 - - LM - MBZ bits when NX is active. */
2240	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2241	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2242	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2243
2244	/**
2245	* Page directory entry.
2246	*/
2247	typedef struct X86PDEBITS
2248	{
2249	/** Flags whether(=1) or not the page is present. */
2250	uint32_t u1Present : 1;
2251	/** Read(=0) / Write(=1) flag. */
2252	uint32_t u1Write : 1;
2253	/** User(=1) / Supervisor (=0) flag. */
2254	uint32_t u1User : 1;
2255	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2256	uint32_t u1WriteThru : 1;
2257	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2258	uint32_t u1CacheDisable : 1;
2259	/** Accessed flag.
2260	* Indicates that the page has been read or written to. */
2261	uint32_t u1Accessed : 1;
2262	/** Reserved / Ignored (dirty bit). */
2263	uint32_t u1Reserved0 : 1;
2264	/** Size bit if PSE is enabled - in any event it's 0. */
2265	uint32_t u1Size : 1;
2266	/** Reserved / Ignored (global bit). */
2267	uint32_t u1Reserved1 : 1;
2268	/** Available for use to system software. */
2269	uint32_t u3Available : 3;
2270	/** Physical Page number of the next level. */
2271	uint32_t u20PageNo : 20;
2272	} X86PDEBITS;
2273	#ifndef VBOX_FOR_DTRACE_LIB
2274	AssertCompileSize(X86PDEBITS, 4);
2275	#endif
2276	/** Pointer to a page directory entry. */
2277	typedef X86PDEBITS *PX86PDEBITS;
2278	/** Pointer to a const page directory entry. */
2279	typedef const X86PDEBITS *PCX86PDEBITS;
2280
2281
2282	/**
2283	* PAE page directory entry.
2284	*/
2285	typedef struct X86PDEPAEBITS
2286	{
2287	/** Flags whether(=1) or not the page is present. */
2288	uint32_t u1Present : 1;
2289	/** Read(=0) / Write(=1) flag. */
2290	uint32_t u1Write : 1;
2291	/** User(=1) / Supervisor (=0) flag. */
2292	uint32_t u1User : 1;
2293	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2294	uint32_t u1WriteThru : 1;
2295	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2296	uint32_t u1CacheDisable : 1;
2297	/** Accessed flag.
2298	* Indicates that the page has been read or written to. */
2299	uint32_t u1Accessed : 1;
2300	/** Reserved / Ignored (dirty bit). */
2301	uint32_t u1Reserved0 : 1;
2302	/** Size bit if PSE is enabled - in any event it's 0. */
2303	uint32_t u1Size : 1;
2304	/** Reserved / Ignored (global bit). / */
2305	uint32_t u1Reserved1 : 1;
2306	/** Available for use to system software. */
2307	uint32_t u3Available : 3;
2308	/** Physical Page number of the next level - Low Part. Don't use! */
2309	uint32_t u20PageNoLow : 20;
2310	/** Physical Page number of the next level - High Part. Don't use! */
2311	uint32_t u20PageNoHigh : 20;
2312	/** MBZ bits */
2313	uint32_t u11Reserved : 11;
2314	/** No Execute flag. */
2315	uint32_t u1NoExecute : 1;
2316	} X86PDEPAEBITS;
2317	#ifndef VBOX_FOR_DTRACE_LIB
2318	AssertCompileSize(X86PDEPAEBITS, 8);
2319	#endif
2320	/** Pointer to a page directory entry. */
2321	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2322	/** Pointer to a const page directory entry. */
2323	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2324
2325	/** @} */
2326
2327
2328	/** @name 2/4MB Page Directory Entry
2329	* @{
2330	*/
2331	/** Bit 0 - P - Present bit. */
2332	#define X86_PDE4M_P RT_BIT_32(0)
2333	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2334	#define X86_PDE4M_RW RT_BIT_32(1)
2335	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2336	#define X86_PDE4M_US RT_BIT_32(2)
2337	/** Bit 3 - PWT - Page level write thru bit. */
2338	#define X86_PDE4M_PWT RT_BIT_32(3)
2339	/** Bit 4 - PCD - Page level cache disable bit. */
2340	#define X86_PDE4M_PCD RT_BIT_32(4)
2341	/** Bit 5 - A - Access bit. */
2342	#define X86_PDE4M_A RT_BIT_32(5)
2343	/** Bit 6 - D - Dirty bit. */
2344	#define X86_PDE4M_D RT_BIT_32(6)
2345	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2346	#define X86_PDE4M_PS RT_BIT_32(7)
2347	/** Bit 8 - G - Global flag. */
2348	#define X86_PDE4M_G RT_BIT_32(8)
2349	/** Bits 9-11 - AVL - Available for use to system software. */
2350	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2351	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2352	#define X86_PDE4M_PAT RT_BIT_32(12)
2353	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2354	#define X86_PDE4M_PAT_SHIFT (12 - 7)
2355	/** Bits 22-31 - - Physical Page number. */
2356	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2357	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2358	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2359	/** The number of bits to the high part of the page number. */
2360	#define X86_PDE4M_PG_HIGH_SHIFT 19
2361	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2362	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2363
2364	/** Bits 21-51 - - PAE/LM - Physical Page number.
2365	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2366	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2367	/** Bits 63 - NX - PAE/LM - No execution flag. */
2368	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2369	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2370	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2371	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2372	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2373	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2374	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2375	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2376	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2377
2378	/**
2379	* 4MB page directory entry.
2380	*/
2381	typedef struct X86PDE4MBITS
2382	{
2383	/** Flags whether(=1) or not the page is present. */
2384	uint32_t u1Present : 1;
2385	/** Read(=0) / Write(=1) flag. */
2386	uint32_t u1Write : 1;
2387	/** User(=1) / Supervisor (=0) flag. */
2388	uint32_t u1User : 1;
2389	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2390	uint32_t u1WriteThru : 1;
2391	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2392	uint32_t u1CacheDisable : 1;
2393	/** Accessed flag.
2394	* Indicates that the page have been read or written to. */
2395	uint32_t u1Accessed : 1;
2396	/** Dirty flag.
2397	* Indicates that the page has been written to. */
2398	uint32_t u1Dirty : 1;
2399	/** Page size flag - always 1 for 4MB entries. */
2400	uint32_t u1Size : 1;
2401	/** Global flag. */
2402	uint32_t u1Global : 1;
2403	/** Available for use to system software. */
2404	uint32_t u3Available : 3;
2405	/** Reserved / If PAT enabled, bit 2 of the index. */
2406	uint32_t u1PAT : 1;
2407	/** Bits 32-39 of the page number on AMD64.
2408	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2409	uint32_t u8PageNoHigh : 8;
2410	/** Reserved. */
2411	uint32_t u1Reserved : 1;
2412	/** Physical Page number of the page. */
2413	uint32_t u10PageNo : 10;
2414	} X86PDE4MBITS;
2415	#ifndef VBOX_FOR_DTRACE_LIB
2416	AssertCompileSize(X86PDE4MBITS, 4);
2417	#endif
2418	/** Pointer to a page table entry. */
2419	typedef X86PDE4MBITS *PX86PDE4MBITS;
2420	/** Pointer to a const page table entry. */
2421	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2422
2423
2424	/**
2425	* 2MB PAE page directory entry.
2426	*/
2427	typedef struct X86PDE2MPAEBITS
2428	{
2429	/** Flags whether(=1) or not the page is present. */
2430	uint32_t u1Present : 1;
2431	/** Read(=0) / Write(=1) flag. */
2432	uint32_t u1Write : 1;
2433	/** User(=1) / Supervisor(=0) flag. */
2434	uint32_t u1User : 1;
2435	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2436	uint32_t u1WriteThru : 1;
2437	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2438	uint32_t u1CacheDisable : 1;
2439	/** Accessed flag.
2440	* Indicates that the page have been read or written to. */
2441	uint32_t u1Accessed : 1;
2442	/** Dirty flag.
2443	* Indicates that the page has been written to. */
2444	uint32_t u1Dirty : 1;
2445	/** Page size flag - always 1 for 2MB entries. */
2446	uint32_t u1Size : 1;
2447	/** Global flag. */
2448	uint32_t u1Global : 1;
2449	/** Available for use to system software. */
2450	uint32_t u3Available : 3;
2451	/** Reserved / If PAT enabled, bit 2 of the index. */
2452	uint32_t u1PAT : 1;
2453	/** Reserved. */
2454	uint32_t u9Reserved : 9;
2455	/** Physical Page number of the next level - Low part. Don't use! */
2456	uint32_t u10PageNoLow : 10;
2457	/** Physical Page number of the next level - High part. Don't use! */
2458	uint32_t u20PageNoHigh : 20;
2459	/** MBZ bits */
2460	uint32_t u11Reserved : 11;
2461	/** No Execute flag. */
2462	uint32_t u1NoExecute : 1;
2463	} X86PDE2MPAEBITS;
2464	#ifndef VBOX_FOR_DTRACE_LIB
2465	AssertCompileSize(X86PDE2MPAEBITS, 8);
2466	#endif
2467	/** Pointer to a 2MB PAE page table entry. */
2468	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2469	/** Pointer to a 2MB PAE page table entry. */
2470	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2471
2472	/** @} */
2473
2474	/**
2475	* Page directory entry.
2476	*/
2477	typedef union X86PDE
2478	{
2479	/** Unsigned integer view. */
2480	X86PGUINT u;
2481	/** Normal view. */
2482	X86PDEBITS n;
2483	/** 4MB view (big). */
2484	X86PDE4MBITS b;
2485	/** 8 bit unsigned integer view. */
2486	uint8_t au8[4];
2487	/** 16 bit unsigned integer view. */
2488	uint16_t au16[2];
2489	/** 32 bit unsigned integer view. */
2490	uint32_t au32[1];
2491	} X86PDE;
2492	#ifndef VBOX_FOR_DTRACE_LIB
2493	AssertCompileSize(X86PDE, 4);
2494	#endif
2495	/** Pointer to a page directory entry. */
2496	typedef X86PDE *PX86PDE;
2497	/** Pointer to a const page directory entry. */
2498	typedef const X86PDE *PCX86PDE;
2499
2500	/**
2501	* PAE page directory entry.
2502	*/
2503	typedef union X86PDEPAE
2504	{
2505	/** Unsigned integer view. */
2506	X86PGPAEUINT u;
2507	/** Normal view. */
2508	X86PDEPAEBITS n;
2509	/** 2MB page view (big). */
2510	X86PDE2MPAEBITS b;
2511	/** 8 bit unsigned integer view. */
2512	uint8_t au8[8];
2513	/** 16 bit unsigned integer view. */
2514	uint16_t au16[4];
2515	/** 32 bit unsigned integer view. */
2516	uint32_t au32[2];
2517	} X86PDEPAE;
2518	#ifndef VBOX_FOR_DTRACE_LIB
2519	AssertCompileSize(X86PDEPAE, 8);
2520	#endif
2521	/** Pointer to a page directory entry. */
2522	typedef X86PDEPAE *PX86PDEPAE;
2523	/** Pointer to a const page directory entry. */
2524	typedef const X86PDEPAE *PCX86PDEPAE;
2525
2526	/**
2527	* Page directory.
2528	*/
2529	typedef struct X86PD
2530	{
2531	/** PDE Array. */
2532	X86PDE a[X86_PG_ENTRIES];
2533	} X86PD;
2534	#ifndef VBOX_FOR_DTRACE_LIB
2535	AssertCompileSize(X86PD, 4096);
2536	#endif
2537	/** Pointer to a page directory. */
2538	typedef X86PD *PX86PD;
2539	/** Pointer to a const page directory. */
2540	typedef const X86PD *PCX86PD;
2541
2542	/** The page shift to get the PD index. */
2543	#define X86_PD_SHIFT 22
2544	/** The PD index mask (apply to a shifted page address). */
2545	#define X86_PD_MASK 0x3ff
2546
2547
2548	/**
2549	* PAE page directory.
2550	*/
2551	typedef struct X86PDPAE
2552	{
2553	/** PDE Array. */
2554	X86PDEPAE a[X86_PG_PAE_ENTRIES];
2555	} X86PDPAE;
2556	#ifndef VBOX_FOR_DTRACE_LIB
2557	AssertCompileSize(X86PDPAE, 4096);
2558	#endif
2559	/** Pointer to a PAE page directory. */
2560	typedef X86PDPAE *PX86PDPAE;
2561	/** Pointer to a const PAE page directory. */
2562	typedef const X86PDPAE *PCX86PDPAE;
2563
2564	/** The page shift to get the PAE PD index. */
2565	#define X86_PD_PAE_SHIFT 21
2566	/** The PAE PD index mask (apply to a shifted page address). */
2567	#define X86_PD_PAE_MASK 0x1ff
2568
2569
2570	/** @name Page Directory Pointer Table Entry (PAE)
2571	* @{
2572	*/
2573	/** Bit 0 - P - Present bit. */
2574	#define X86_PDPE_P RT_BIT_32(0)
2575	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2576	#define X86_PDPE_RW RT_BIT_32(1)
2577	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2578	#define X86_PDPE_US RT_BIT_32(2)
2579	/** Bit 3 - PWT - Page level write thru bit. */
2580	#define X86_PDPE_PWT RT_BIT_32(3)
2581	/** Bit 4 - PCD - Page level cache disable bit. */
2582	#define X86_PDPE_PCD RT_BIT_32(4)
2583	/** Bit 5 - A - Access bit. Long Mode only. */
2584	#define X86_PDPE_A RT_BIT_32(5)
2585	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2586	#define X86_PDPE_LM_PS RT_BIT_32(7)
2587	/** Bits 9-11 - - Available for use to system software. */
2588	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2589	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2590	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2591	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2592	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2593	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2594	#define X86_PDPE_LM_NX RT_BIT_64(63)
2595	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2596	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2597	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2598	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2599	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2600	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2601	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2602	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2603
2604
2605	/**
2606	* Page directory pointer table entry.
2607	*/
2608	typedef struct X86PDPEBITS
2609	{
2610	/** Flags whether(=1) or not the page is present. */
2611	uint32_t u1Present : 1;
2612	/** Chunk of reserved bits. */
2613	uint32_t u2Reserved : 2;
2614	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2615	uint32_t u1WriteThru : 1;
2616	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2617	uint32_t u1CacheDisable : 1;
2618	/** Chunk of reserved bits. */
2619	uint32_t u4Reserved : 4;
2620	/** Available for use to system software. */
2621	uint32_t u3Available : 3;
2622	/** Physical Page number of the next level - Low Part. Don't use! */
2623	uint32_t u20PageNoLow : 20;
2624	/** Physical Page number of the next level - High Part. Don't use! */
2625	uint32_t u20PageNoHigh : 20;
2626	/** MBZ bits */
2627	uint32_t u12Reserved : 12;
2628	} X86PDPEBITS;
2629	#ifndef VBOX_FOR_DTRACE_LIB
2630	AssertCompileSize(X86PDPEBITS, 8);
2631	#endif
2632	/** Pointer to a page directory pointer table entry. */
2633	typedef X86PDPEBITS *PX86PTPEBITS;
2634	/** Pointer to a const page directory pointer table entry. */
2635	typedef const X86PDPEBITS *PCX86PTPEBITS;
2636
2637	/**
2638	* Page directory pointer table entry. AMD64 version
2639	*/
2640	typedef struct X86PDPEAMD64BITS
2641	{
2642	/** Flags whether(=1) or not the page is present. */
2643	uint32_t u1Present : 1;
2644	/** Read(=0) / Write(=1) flag. */
2645	uint32_t u1Write : 1;
2646	/** User(=1) / Supervisor (=0) flag. */
2647	uint32_t u1User : 1;
2648	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2649	uint32_t u1WriteThru : 1;
2650	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2651	uint32_t u1CacheDisable : 1;
2652	/** Accessed flag.
2653	* Indicates that the page have been read or written to. */
2654	uint32_t u1Accessed : 1;
2655	/** Chunk of reserved bits. */
2656	uint32_t u3Reserved : 3;
2657	/** Available for use to system software. */
2658	uint32_t u3Available : 3;
2659	/** Physical Page number of the next level - Low Part. Don't use! */
2660	uint32_t u20PageNoLow : 20;
2661	/** Physical Page number of the next level - High Part. Don't use! */
2662	uint32_t u20PageNoHigh : 20;
2663	/** MBZ bits */
2664	uint32_t u11Reserved : 11;
2665	/** No Execute flag. */
2666	uint32_t u1NoExecute : 1;
2667	} X86PDPEAMD64BITS;
2668	#ifndef VBOX_FOR_DTRACE_LIB
2669	AssertCompileSize(X86PDPEAMD64BITS, 8);
2670	#endif
2671	/** Pointer to a page directory pointer table entry. */
2672	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2673	/** Pointer to a const page directory pointer table entry. */
2674	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2675
2676	/**
2677	* Page directory pointer table entry for 1GB page. (AMD64 only)
2678	*/
2679	typedef struct X86PDPE1GB
2680	{
2681	/** 0: Flags whether(=1) or not the page is present. */
2682	uint32_t u1Present : 1;
2683	/** 1: Read(=0) / Write(=1) flag. */
2684	uint32_t u1Write : 1;
2685	/** 2: User(=1) / Supervisor (=0) flag. */
2686	uint32_t u1User : 1;
2687	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2688	uint32_t u1WriteThru : 1;
2689	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2690	uint32_t u1CacheDisable : 1;
2691	/** 5: Accessed flag.
2692	* Indicates that the page have been read or written to. */
2693	uint32_t u1Accessed : 1;
2694	/** 6: Dirty flag for 1GB pages. */
2695	uint32_t u1Dirty : 1;
2696	/** 7: Indicates 1GB page if set. */
2697	uint32_t u1Size : 1;
2698	/** 8: Global 1GB page. */
2699	uint32_t u1Global: 1;
2700	/** 9-11: Available for use to system software. */
2701	uint32_t u3Available : 3;
2702	/** 12: PAT bit for 1GB page. */
2703	uint32_t u1PAT : 1;
2704	/** 13-29: MBZ bits. */
2705	uint32_t u17Reserved : 17;
2706	/** 30-31: Physical page number - Low Part. Don't use! */
2707	uint32_t u2PageNoLow : 2;
2708	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
2709	uint32_t u20PageNoHigh : 20;
2710	/** 52-62: MBZ bits */
2711	uint32_t u11Reserved : 11;
2712	/** 63: No Execute flag. */
2713	uint32_t u1NoExecute : 1;
2714	} X86PDPE1GB;
2715	#ifndef VBOX_FOR_DTRACE_LIB
2716	AssertCompileSize(X86PDPE1GB, 8);
2717	#endif
2718	/** Pointer to a page directory pointer table entry for a 1GB page. */
2719	typedef X86PDPE1GB *PX86PDPE1GB;
2720	/** Pointer to a const page directory pointer table entry for a 1GB page. */
2721	typedef const X86PDPE1GB *PCX86PDPE1GB;
2722
2723	/**
2724	* Page directory pointer table entry.
2725	*/
2726	typedef union X86PDPE
2727	{
2728	/** Unsigned integer view. */
2729	X86PGPAEUINT u;
2730	/** Normal view. */
2731	X86PDPEBITS n;
2732	/** AMD64 view. */
2733	X86PDPEAMD64BITS lm;
2734	/** AMD64 big view. */
2735	X86PDPE1GB b;
2736	/** 8 bit unsigned integer view. */
2737	uint8_t au8[8];
2738	/** 16 bit unsigned integer view. */
2739	uint16_t au16[4];
2740	/** 32 bit unsigned integer view. */
2741	uint32_t au32[2];
2742	} X86PDPE;
2743	#ifndef VBOX_FOR_DTRACE_LIB
2744	AssertCompileSize(X86PDPE, 8);
2745	#endif
2746	/** Pointer to a page directory pointer table entry. */
2747	typedef X86PDPE *PX86PDPE;
2748	/** Pointer to a const page directory pointer table entry. */
2749	typedef const X86PDPE *PCX86PDPE;
2750
2751
2752	/**
2753	* Page directory pointer table.
2754	*/
2755	typedef struct X86PDPT
2756	{
2757	/** PDE Array. */
2758	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2759	} X86PDPT;
2760	#ifndef VBOX_FOR_DTRACE_LIB
2761	AssertCompileSize(X86PDPT, 4096);
2762	#endif
2763	/** Pointer to a page directory pointer table. */
2764	typedef X86PDPT *PX86PDPT;
2765	/** Pointer to a const page directory pointer table. */
2766	typedef const X86PDPT *PCX86PDPT;
2767
2768	/** The page shift to get the PDPT index. */
2769	#define X86_PDPT_SHIFT 30
2770	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2771	#define X86_PDPT_MASK_PAE 0x3
2772	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2773	#define X86_PDPT_MASK_AMD64 0x1ff
2774
2775	/** @} */
2776
2777
2778	/** @name Page Map Level-4 Entry (Long Mode PAE)
2779	* @{
2780	*/
2781	/** Bit 0 - P - Present bit. */
2782	#define X86_PML4E_P RT_BIT_32(0)
2783	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2784	#define X86_PML4E_RW RT_BIT_32(1)
2785	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2786	#define X86_PML4E_US RT_BIT_32(2)
2787	/** Bit 3 - PWT - Page level write thru bit. */
2788	#define X86_PML4E_PWT RT_BIT_32(3)
2789	/** Bit 4 - PCD - Page level cache disable bit. */
2790	#define X86_PML4E_PCD RT_BIT_32(4)
2791	/** Bit 5 - A - Access bit. */
2792	#define X86_PML4E_A RT_BIT_32(5)
2793	/** Bits 9-11 - - Available for use to system software. */
2794	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2795	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2796	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2797	/** Bits 8, 7 - - MBZ bits when NX is active. */
2798	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2799	/** Bits 63, 7 - - MBZ bits when no NX. */
2800	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2801	/** Bits 63 - NX - PAE - No execution flag. */
2802	#define X86_PML4E_NX RT_BIT_64(63)
2803
2804	/**
2805	* Page Map Level-4 Entry
2806	*/
2807	typedef struct X86PML4EBITS
2808	{
2809	/** Flags whether(=1) or not the page is present. */
2810	uint32_t u1Present : 1;
2811	/** Read(=0) / Write(=1) flag. */
2812	uint32_t u1Write : 1;
2813	/** User(=1) / Supervisor (=0) flag. */
2814	uint32_t u1User : 1;
2815	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2816	uint32_t u1WriteThru : 1;
2817	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2818	uint32_t u1CacheDisable : 1;
2819	/** Accessed flag.
2820	* Indicates that the page have been read or written to. */
2821	uint32_t u1Accessed : 1;
2822	/** Chunk of reserved bits. */
2823	uint32_t u3Reserved : 3;
2824	/** Available for use to system software. */
2825	uint32_t u3Available : 3;
2826	/** Physical Page number of the next level - Low Part. Don't use! */
2827	uint32_t u20PageNoLow : 20;
2828	/** Physical Page number of the next level - High Part. Don't use! */
2829	uint32_t u20PageNoHigh : 20;
2830	/** MBZ bits */
2831	uint32_t u11Reserved : 11;
2832	/** No Execute flag. */
2833	uint32_t u1NoExecute : 1;
2834	} X86PML4EBITS;
2835	#ifndef VBOX_FOR_DTRACE_LIB
2836	AssertCompileSize(X86PML4EBITS, 8);
2837	#endif
2838	/** Pointer to a page map level-4 entry. */
2839	typedef X86PML4EBITS *PX86PML4EBITS;
2840	/** Pointer to a const page map level-4 entry. */
2841	typedef const X86PML4EBITS *PCX86PML4EBITS;
2842
2843	/**
2844	* Page Map Level-4 Entry.
2845	*/
2846	typedef union X86PML4E
2847	{
2848	/** Unsigned integer view. */
2849	X86PGPAEUINT u;
2850	/** Normal view. */
2851	X86PML4EBITS n;
2852	/** 8 bit unsigned integer view. */
2853	uint8_t au8[8];
2854	/** 16 bit unsigned integer view. */
2855	uint16_t au16[4];
2856	/** 32 bit unsigned integer view. */
2857	uint32_t au32[2];
2858	} X86PML4E;
2859	#ifndef VBOX_FOR_DTRACE_LIB
2860	AssertCompileSize(X86PML4E, 8);
2861	#endif
2862	/** Pointer to a page map level-4 entry. */
2863	typedef X86PML4E *PX86PML4E;
2864	/** Pointer to a const page map level-4 entry. */
2865	typedef const X86PML4E *PCX86PML4E;
2866
2867
2868	/**
2869	* Page Map Level-4.
2870	*/
2871	typedef struct X86PML4
2872	{
2873	/** PDE Array. */
2874	X86PML4E a[X86_PG_PAE_ENTRIES];
2875	} X86PML4;
2876	#ifndef VBOX_FOR_DTRACE_LIB
2877	AssertCompileSize(X86PML4, 4096);
2878	#endif
2879	/** Pointer to a page map level-4. */
2880	typedef X86PML4 *PX86PML4;
2881	/** Pointer to a const page map level-4. */
2882	typedef const X86PML4 *PCX86PML4;
2883
2884	/** The page shift to get the PML4 index. */
2885	#define X86_PML4_SHIFT 39
2886	/** The PML4 index mask (apply to a shifted page address). */
2887	#define X86_PML4_MASK 0x1ff
2888
2889	/** @} */
2890
2891	/** @} */
2892
2893	/**
2894	* Intel PCID invalidation types.
2895	*/
2896	/** Individual address invalidation. */
2897	#define X86_INVPCID_TYPE_INDV_ADDR 0
2898	/** Single-context invalidation. */
2899	#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
2900	/** All-context including globals invalidation. */
2901	#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
2902	/** All-context excluding globals invalidation. */
2903	#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
2904	/** The maximum valid invalidation type value. */
2905	#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
2906
2907	/**
2908	* 32-bit protected mode FSTENV image.
2909	*/
2910	typedef struct X86FSTENV32P
2911	{
2912	uint16_t FCW; /*< 0x00 /
2913	uint16_t padding1; /*< 0x02 /
2914	uint16_t FSW; /*< 0x04 /
2915	uint16_t padding2; /*< 0x06 /
2916	uint16_t FTW; /*< 0x08 /
2917	uint16_t padding3; /*< 0x0a /
2918	uint32_t FPUIP; /*< 0x0c /
2919	uint16_t FPUCS; /*< 0x10 /
2920	uint16_t FOP; /*< 0x12 /
2921	uint32_t FPUDP; /*< 0x14 /
2922	uint16_t FPUDS; /*< 0x18 /
2923	uint16_t padding4; /*< 0x1a /
2924	} X86FSTENV32P;
2925	#ifndef VBOX_FOR_DTRACE_LIB
2926	AssertCompileSize(X86FSTENV32P, 0x1c);
2927	#endif
2928	/** Pointer to a 32-bit protected mode FSTENV image. */
2929	typedef X86FSTENV32P *PX86FSTENV32P;
2930	/** Pointer to a const 32-bit protected mode FSTENV image. */
2931	typedef X86FSTENV32P const *PCX86FSTENV32P;
2932
2933
2934	/**
2935	* 80-bit MMX/FPU register type.
2936	*/
2937	typedef struct X86FPUMMX
2938	{
2939	uint8_t reg[10];
2940	} X86FPUMMX;
2941	#ifndef VBOX_FOR_DTRACE_LIB
2942	AssertCompileSize(X86FPUMMX, 10);
2943	#endif
2944	/** Pointer to a 80-bit MMX/FPU register type. */
2945	typedef X86FPUMMX *PX86FPUMMX;
2946	/** Pointer to a const 80-bit MMX/FPU register type. */
2947	typedef const X86FPUMMX *PCX86FPUMMX;
2948
2949	/** FPU (x87) register. */
2950	typedef union X86FPUREG
2951	{
2952	/** MMX view. */
2953	uint64_t mmx;
2954	/** FPU view - todo. */
2955	X86FPUMMX fpu;
2956	/** Extended precision floating point view. */
2957	RTFLOAT80U r80;
2958	/** Extended precision floating point view v2 */
2959	RTFLOAT80U2 r80Ex;
2960	/** 8-bit view. */
2961	uint8_t au8[16];
2962	/** 16-bit view. */
2963	uint16_t au16[8];
2964	/** 32-bit view. */
2965	uint32_t au32[4];
2966	/** 64-bit view. */
2967	uint64_t au64[2];
2968	/** 128-bit view. (yeah, very helpful) */
2969	uint128_t au128[1];
2970	} X86FPUREG;
2971	#ifndef VBOX_FOR_DTRACE_LIB
2972	AssertCompileSize(X86FPUREG, 16);
2973	#endif
2974	/** Pointer to a FPU register. */
2975	typedef X86FPUREG *PX86FPUREG;
2976	/** Pointer to a const FPU register. */
2977	typedef X86FPUREG const *PCX86FPUREG;
2978
2979	/**
2980	* XMM register union.
2981	*/
2982	typedef union X86XMMREG
2983	{
2984	/** XMM Register view. */
2985	uint128_t xmm;
2986	/** 8-bit view. */
2987	uint8_t au8[16];
2988	/** 16-bit view. */
2989	uint16_t au16[8];
2990	/** 32-bit view. */
2991	uint32_t au32[4];
2992	/** 64-bit view. */
2993	uint64_t au64[2];
2994	/** 128-bit view. (yeah, very helpful) */
2995	uint128_t au128[1];
2996	#ifndef VBOX_FOR_DTRACE_LIB
2997	/** Confusing nested 128-bit union view (this is what xmm should've been). */
2998	RTUINT128U uXmm;
2999	#endif
3000	} X86XMMREG;
3001	#ifndef VBOX_FOR_DTRACE_LIB
3002	AssertCompileSize(X86XMMREG, 16);
3003	#endif
3004	/** Pointer to an XMM register state. */
3005	typedef X86XMMREG *PX86XMMREG;
3006	/** Pointer to a const XMM register state. */
3007	typedef X86XMMREG const *PCX86XMMREG;
3008
3009	/**
3010	* YMM register union.
3011	*/
3012	typedef union X86YMMREG
3013	{
3014	/** 8-bit view. */
3015	uint8_t au8[32];
3016	/** 16-bit view. */
3017	uint16_t au16[16];
3018	/** 32-bit view. */
3019	uint32_t au32[8];
3020	/** 64-bit view. */
3021	uint64_t au64[4];
3022	/** 128-bit view. (yeah, very helpful) */
3023	uint128_t au128[2];
3024	/** XMM sub register view. */
3025	X86XMMREG aXmm[2];
3026	} X86YMMREG;
3027	#ifndef VBOX_FOR_DTRACE_LIB
3028	AssertCompileSize(X86YMMREG, 32);
3029	#endif
3030	/** Pointer to an YMM register state. */
3031	typedef X86YMMREG *PX86YMMREG;
3032	/** Pointer to a const YMM register state. */
3033	typedef X86YMMREG const *PCX86YMMREG;
3034
3035	/**
3036	* ZMM register union.
3037	*/
3038	typedef union X86ZMMREG
3039	{
3040	/** 8-bit view. */
3041	uint8_t au8[64];
3042	/** 16-bit view. */
3043	uint16_t au16[32];
3044	/** 32-bit view. */
3045	uint32_t au32[16];
3046	/** 64-bit view. */
3047	uint64_t au64[8];
3048	/** 128-bit view. (yeah, very helpful) */
3049	uint128_t au128[4];
3050	/** XMM sub register view. */
3051	X86XMMREG aXmm[4];
3052	/** YMM sub register view. */
3053	X86YMMREG aYmm[2];
3054	} X86ZMMREG;
3055	#ifndef VBOX_FOR_DTRACE_LIB
3056	AssertCompileSize(X86ZMMREG, 64);
3057	#endif
3058	/** Pointer to an ZMM register state. */
3059	typedef X86ZMMREG *PX86ZMMREG;
3060	/** Pointer to a const ZMM register state. */
3061	typedef X86ZMMREG const *PCX86ZMMREG;
3062
3063
3064	/**
3065	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3066	* @todo verify this...
3067	*/
3068	#pragma pack(1)
3069	typedef struct X86FPUSTATE
3070	{
3071	/** 0x00 - Control word. */
3072	uint16_t FCW;
3073	/** 0x02 - Alignment word */
3074	uint16_t Dummy1;
3075	/** 0x04 - Status word. */
3076	uint16_t FSW;
3077	/** 0x06 - Alignment word */
3078	uint16_t Dummy2;
3079	/** 0x08 - Tag word */
3080	uint16_t FTW;
3081	/** 0x0a - Alignment word */
3082	uint16_t Dummy3;
3083
3084	/** 0x0c - Instruction pointer. */
3085	uint32_t FPUIP;
3086	/** 0x10 - Code selector. */
3087	uint16_t CS;
3088	/** 0x12 - Opcode. */
3089	uint16_t FOP;
3090	/** 0x14 - FOO. */
3091	uint32_t FPUOO;
3092	/** 0x18 - FOS. */
3093	uint32_t FPUOS;
3094	/** 0x1c - FPU register. */
3095	X86FPUREG regs[8];
3096	} X86FPUSTATE;
3097	#pragma pack()
3098	/** Pointer to a FPU state. */
3099	typedef X86FPUSTATE *PX86FPUSTATE;
3100	/** Pointer to a const FPU state. */
3101	typedef const X86FPUSTATE *PCX86FPUSTATE;
3102
3103	/**
3104	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3105	*/
3106	#pragma pack(1)
3107	typedef struct X86FXSTATE
3108	{
3109	/** 0x00 - Control word. */
3110	uint16_t FCW;
3111	/** 0x02 - Status word. */
3112	uint16_t FSW;
3113	/** 0x04 - Tag word. (The upper byte is always zero.) */
3114	uint16_t FTW;
3115	/** 0x06 - Opcode. */
3116	uint16_t FOP;
3117	/** 0x08 - Instruction pointer. */
3118	uint32_t FPUIP;
3119	/** 0x0c - Code selector. */
3120	uint16_t CS;
3121	uint16_t Rsrvd1;
3122	/** 0x10 - Data pointer. */
3123	uint32_t FPUDP;
3124	/** 0x14 - Data segment */
3125	uint16_t DS;
3126	/** 0x16 */
3127	uint16_t Rsrvd2;
3128	/** 0x18 */
3129	uint32_t MXCSR;
3130	/** 0x1c */
3131	uint32_t MXCSR_MASK;
3132	/** 0x20 - FPU registers. */
3133	X86FPUREG aRegs[8];
3134	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3135	X86XMMREG aXMM[16];
3136	/* - offset 416 - */
3137	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3138	/* - offset 464 - Software usable reserved bits. */
3139	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3140	} X86FXSTATE;
3141	#pragma pack()
3142	/** Pointer to a FPU Extended state. */
3143	typedef X86FXSTATE *PX86FXSTATE;
3144	/** Pointer to a const FPU Extended state. */
3145	typedef const X86FXSTATE *PCX86FXSTATE;
3146
3147	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3148	* magic. Don't forget to update x86.mac if you change this! */
3149	#define X86_OFF_FXSTATE_RSVD 0x1d0
3150	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3151	* forget to update x86.mac if you change this!
3152	* @todo r=bird: This has nothing what-so-ever to do here.... */
3153	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3154	#ifndef VBOX_FOR_DTRACE_LIB
3155	AssertCompileSize(X86FXSTATE, 512);
3156	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3157	#endif
3158
3159	/** @name FPU status word flags.
3160	* @{ */
3161	/** Exception Flag: Invalid operation. */
3162	#define X86_FSW_IE RT_BIT_32(0)
3163	/** Exception Flag: Denormalized operand. */
3164	#define X86_FSW_DE RT_BIT_32(1)
3165	/** Exception Flag: Zero divide. */
3166	#define X86_FSW_ZE RT_BIT_32(2)
3167	/** Exception Flag: Overflow. */
3168	#define X86_FSW_OE RT_BIT_32(3)
3169	/** Exception Flag: Underflow. */
3170	#define X86_FSW_UE RT_BIT_32(4)
3171	/** Exception Flag: Precision. */
3172	#define X86_FSW_PE RT_BIT_32(5)
3173	/** Stack fault. */
3174	#define X86_FSW_SF RT_BIT_32(6)
3175	/** Error summary status. */
3176	#define X86_FSW_ES RT_BIT_32(7)
3177	/** Mask of exceptions flags, excluding the summary bit. */
3178	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3179	/** Mask of exceptions flags, including the summary bit. */
3180	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3181	/** Condition code 0. */
3182	#define X86_FSW_C0 RT_BIT_32(8)
3183	/** Condition code 1. */
3184	#define X86_FSW_C1 RT_BIT_32(9)
3185	/** Condition code 2. */
3186	#define X86_FSW_C2 RT_BIT_32(10)
3187	/** Top of the stack mask. */
3188	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3189	/** TOP shift value. */
3190	#define X86_FSW_TOP_SHIFT 11
3191	/** Mask for getting TOP value after shifting it right. */
3192	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3193	/** Get the TOP value. */
3194	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3195	/** Condition code 3. */
3196	#define X86_FSW_C3 RT_BIT_32(14)
3197	/** Mask of exceptions flags, including the summary bit. */
3198	#define X86_FSW_C_MASK UINT16_C(0x4700)
3199	/** FPU busy. */
3200	#define X86_FSW_B RT_BIT_32(15)
3201	/** @} */
3202
3203
3204	/** @name FPU control word flags.
3205	* @{ */
3206	/** Exception Mask: Invalid operation. */
3207	#define X86_FCW_IM RT_BIT_32(0)
3208	/** Exception Mask: Denormalized operand. */
3209	#define X86_FCW_DM RT_BIT_32(1)
3210	/** Exception Mask: Zero divide. */
3211	#define X86_FCW_ZM RT_BIT_32(2)
3212	/** Exception Mask: Overflow. */
3213	#define X86_FCW_OM RT_BIT_32(3)
3214	/** Exception Mask: Underflow. */
3215	#define X86_FCW_UM RT_BIT_32(4)
3216	/** Exception Mask: Precision. */
3217	#define X86_FCW_PM RT_BIT_32(5)
3218	/** Mask all exceptions, the value typically loaded (by for instance fninit).
3219	* @remarks This includes reserved bit 6. */
3220	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3221	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3222	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3223	/** Precision control mask. */
3224	#define X86_FCW_PC_MASK UINT16_C(0x0300)
3225	/** Precision control: 24-bit. */
3226	#define X86_FCW_PC_24 UINT16_C(0x0000)
3227	/** Precision control: Reserved. */
3228	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3229	/** Precision control: 53-bit. */
3230	#define X86_FCW_PC_53 UINT16_C(0x0200)
3231	/** Precision control: 64-bit. */
3232	#define X86_FCW_PC_64 UINT16_C(0x0300)
3233	/** Rounding control mask. */
3234	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3235	/** Rounding control: To nearest. */
3236	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3237	/** Rounding control: Down. */
3238	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3239	/** Rounding control: Up. */
3240	#define X86_FCW_RC_UP UINT16_C(0x0800)
3241	/** Rounding control: Towards zero. */
3242	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3243	/** Bits which should be zero, apparently. */
3244	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3245	/** @} */
3246
3247	/** @name SSE MXCSR
3248	* @{ */
3249	/** Exception Flag: Invalid operation. */
3250	#define X86_MXCSR_IE RT_BIT_32(0)
3251	/** Exception Flag: Denormalized operand. */
3252	#define X86_MXCSR_DE RT_BIT_32(1)
3253	/** Exception Flag: Zero divide. */
3254	#define X86_MXCSR_ZE RT_BIT_32(2)
3255	/** Exception Flag: Overflow. */
3256	#define X86_MXCSR_OE RT_BIT_32(3)
3257	/** Exception Flag: Underflow. */
3258	#define X86_MXCSR_UE RT_BIT_32(4)
3259	/** Exception Flag: Precision. */
3260	#define X86_MXCSR_PE RT_BIT_32(5)
3261
3262	/** Denormals are zero. */
3263	#define X86_MXCSR_DAZ RT_BIT_32(6)
3264
3265	/** Exception Mask: Invalid operation. */
3266	#define X86_MXCSR_IM RT_BIT_32(7)
3267	/** Exception Mask: Denormalized operand. */
3268	#define X86_MXCSR_DM RT_BIT_32(8)
3269	/** Exception Mask: Zero divide. */
3270	#define X86_MXCSR_ZM RT_BIT_32(9)
3271	/** Exception Mask: Overflow. */
3272	#define X86_MXCSR_OM RT_BIT_32(10)
3273	/** Exception Mask: Underflow. */
3274	#define X86_MXCSR_UM RT_BIT_32(11)
3275	/** Exception Mask: Precision. */
3276	#define X86_MXCSR_PM RT_BIT_32(12)
3277
3278	/** Rounding control mask. */
3279	#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
3280	/** Rounding control: To nearest. */
3281	#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
3282	/** Rounding control: Down. */
3283	#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
3284	/** Rounding control: Up. */
3285	#define X86_MXCSR_RC_UP UINT16_C(0x4000)
3286	/** Rounding control: Towards zero. */
3287	#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
3288
3289	/** Flush-to-zero for masked underflow. */
3290	#define X86_MXCSR_FZ RT_BIT_32(15)
3291
3292	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3293	#define X86_MXCSR_MM RT_BIT_32(17)
3294	/** @} */
3295
3296	/**
3297	* XSAVE header.
3298	*/
3299	typedef struct X86XSAVEHDR
3300	{
3301	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
3302	uint64_t bmXState;
3303	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3304	uint64_t bmXComp;
3305	/** Reserved for furture extensions, probably MBZ. */
3306	uint64_t au64Reserved[6];
3307	} X86XSAVEHDR;
3308	#ifndef VBOX_FOR_DTRACE_LIB
3309	AssertCompileSize(X86XSAVEHDR, 64);
3310	#endif
3311	/** Pointer to an XSAVE header. */
3312	typedef X86XSAVEHDR *PX86XSAVEHDR;
3313	/** Pointer to a const XSAVE header. */
3314	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3315
3316
3317	/**
3318	* The high 128-bit YMM register state (XSAVE_C_YMM).
3319	* (The lower 128-bits being in X86FXSTATE.)
3320	*/
3321	typedef struct X86XSAVEYMMHI
3322	{
3323	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3324	X86XMMREG aYmmHi[16];
3325	} X86XSAVEYMMHI;
3326	#ifndef VBOX_FOR_DTRACE_LIB
3327	AssertCompileSize(X86XSAVEYMMHI, 256);
3328	#endif
3329	/** Pointer to a high 128-bit YMM register state. */
3330	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3331	/** Pointer to a const high 128-bit YMM register state. */
3332	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3333
3334	/**
3335	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
3336	*/
3337	typedef struct X86XSAVEBNDREGS
3338	{
3339	/** Array of registers (BND0...BND3). */
3340	struct
3341	{
3342	/** Lower bound. */
3343	uint64_t uLowerBound;
3344	/** Upper bound. */
3345	uint64_t uUpperBound;
3346	} aRegs[4];
3347	} X86XSAVEBNDREGS;
3348	#ifndef VBOX_FOR_DTRACE_LIB
3349	AssertCompileSize(X86XSAVEBNDREGS, 64);
3350	#endif
3351	/** Pointer to a MPX bound register state. */
3352	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3353	/** Pointer to a const MPX bound register state. */
3354	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3355
3356	/**
3357	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3358	*/
3359	typedef struct X86XSAVEBNDCFG
3360	{
3361	uint64_t fConfig;
3362	uint64_t fStatus;
3363	} X86XSAVEBNDCFG;
3364	#ifndef VBOX_FOR_DTRACE_LIB
3365	AssertCompileSize(X86XSAVEBNDCFG, 16);
3366	#endif
3367	/** Pointer to a MPX bound config and status register state. */
3368	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3369	/** Pointer to a const MPX bound config and status register state. */
3370	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3371
3372	/**
3373	* AVX-512 opmask state (XSAVE_C_OPMASK).
3374	*/
3375	typedef struct X86XSAVEOPMASK
3376	{
3377	/** The K0..K7 values. */
3378	uint64_t aKRegs[8];
3379	} X86XSAVEOPMASK;
3380	#ifndef VBOX_FOR_DTRACE_LIB
3381	AssertCompileSize(X86XSAVEOPMASK, 64);
3382	#endif
3383	/** Pointer to a AVX-512 opmask state. */
3384	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3385	/** Pointer to a const AVX-512 opmask state. */
3386	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3387
3388	/**
3389	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3390	*/
3391	typedef struct X86XSAVEZMMHI256
3392	{
3393	/** Upper 256-bits of ZMM0-15. */
3394	X86YMMREG aHi256Regs[16];
3395	} X86XSAVEZMMHI256;
3396	#ifndef VBOX_FOR_DTRACE_LIB
3397	AssertCompileSize(X86XSAVEZMMHI256, 512);
3398	#endif
3399	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3400	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3401	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3402	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3403
3404	/**
3405	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3406	*/
3407	typedef struct X86XSAVEZMM16HI
3408	{
3409	/** ZMM16 thru ZMM31. */
3410	X86ZMMREG aRegs[16];
3411	} X86XSAVEZMM16HI;
3412	#ifndef VBOX_FOR_DTRACE_LIB
3413	AssertCompileSize(X86XSAVEZMM16HI, 1024);
3414	#endif
3415	/** Pointer to a state comprising ZMM16-32. */
3416	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3417	/** Pointer to a const state comprising ZMM16-32. */
3418	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3419
3420	/**
3421	* AMD Light weight profiling state (XSAVE_C_LWP).
3422	*
3423	* We probably won't play with this as AMD seems to be dropping from their "zen"
3424	* processor micro architecture.
3425	*/
3426	typedef struct X86XSAVELWP
3427	{
3428	/** Details when needed. */
3429	uint64_t auLater[128/8];
3430	} X86XSAVELWP;
3431	#ifndef VBOX_FOR_DTRACE_LIB
3432	AssertCompileSize(X86XSAVELWP, 128);
3433	#endif
3434
3435
3436	/**
3437	* x86 FPU/SSE/AVX/XXXX state.
3438	*
3439	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3440	* changes to this structure.
3441	*/
3442	typedef struct X86XSAVEAREA
3443	{
3444	/** The x87 and SSE region (or legacy region if you like). */
3445	X86FXSTATE x87;
3446	/** The XSAVE header. */
3447	X86XSAVEHDR Hdr;
3448	/** Beyond the header, there isn't really a fixed layout, but we can
3449	generally assume the YMM (AVX) register extensions are present and
3450	follows immediately. */
3451	union
3452	{
3453	/** The high 128-bit AVX registers for easy access by IEM.
3454	* @note This ASSUMES they will always be here... */
3455	X86XSAVEYMMHI YmmHi;
3456
3457	/** This is a typical layout on intel CPUs (good for debuggers). */
3458	struct
3459	{
3460	X86XSAVEYMMHI YmmHi;
3461	X86XSAVEBNDREGS BndRegs;
3462	X86XSAVEBNDCFG BndCfg;
3463	uint8_t abFudgeToMatchDocs[0xB0];
3464	X86XSAVEOPMASK Opmask;
3465	X86XSAVEZMMHI256 ZmmHi256;
3466	X86XSAVEZMM16HI Zmm16Hi;
3467	} Intel;
3468
3469	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3470	struct
3471	{
3472	X86XSAVEYMMHI YmmHi;
3473	X86XSAVELWP Lwp;
3474	} AmdBd;
3475
3476	/** To enbling static deployments that have a reasonable chance of working for
3477	* the next 3-6 CPU generations without running short on space, we allocate a
3478	* lot of extra space here, making the structure a round 8KB in size. This
3479	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3480	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3481	uint8_t ab[8192 - 512 - 64];
3482	} u;
3483	} X86XSAVEAREA;
3484	#ifndef VBOX_FOR_DTRACE_LIB
3485	AssertCompileSize(X86XSAVEAREA, 8192);
3486	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
3487	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3488	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3489	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3490	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3491	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3492	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3493	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3494	#endif
3495	/** Pointer to a XSAVE area. */
3496	typedef X86XSAVEAREA *PX86XSAVEAREA;
3497	/** Pointer to a const XSAVE area. */
3498	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3499
3500
3501	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3502	* @{ */
3503	/** Bit 0 - x87 - Legacy FPU state (bit number) */
3504	#define XSAVE_C_X87_BIT 0
3505	/** Bit 0 - x87 - Legacy FPU state. */
3506	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3507	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3508	#define XSAVE_C_SSE_BIT 1
3509	/** Bit 1 - SSE - 128-bit SSE state. */
3510	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3511	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3512	#define XSAVE_C_YMM_BIT 2
3513	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3514	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3515	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3516	#define XSAVE_C_BNDREGS_BIT 3
3517	/** Bit 3 - BNDREGS - MPX bound register state. */
3518	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3519	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3520	#define XSAVE_C_BNDCSR_BIT 4
3521	/** Bit 4 - BNDCSR - MPX bound config and status state. */
3522	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3523	/** Bit 5 - Opmask - opmask state (bit number). */
3524	#define XSAVE_C_OPMASK_BIT 5
3525	/** Bit 5 - Opmask - opmask state. */
3526	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3527	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3528	#define XSAVE_C_ZMM_HI256_BIT 6
3529	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3530	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3531	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3532	#define XSAVE_C_ZMM_16HI_BIT 7
3533	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3534	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3535	/** Bit 9 - PKRU - Protection-key state (bit number). */
3536	#define XSAVE_C_PKRU_BIT 9
3537	/** Bit 9 - PKRU - Protection-key state. */
3538	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3539	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3540	#define XSAVE_C_LWP_BIT 62
3541	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3542	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3543	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3544	#define XSAVE_C_X_BIT 63
3545	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3546	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3547	/** @} */
3548
3549
3550
3551	/** @name Selector Descriptor
3552	* @{
3553	*/
3554
3555	#ifndef VBOX_FOR_DTRACE_LIB
3556	/**
3557	* Descriptor attributes (as seen by VT-x).
3558	*/
3559	typedef struct X86DESCATTRBITS
3560	{
3561	/** 00 - Segment Type. */
3562	unsigned u4Type : 4;
3563	/** 04 - Descriptor Type. System(=0) or code/data selector */
3564	unsigned u1DescType : 1;
3565	/** 05 - Descriptor Privilege level. */
3566	unsigned u2Dpl : 2;
3567	/** 07 - Flags selector present(=1) or not. */
3568	unsigned u1Present : 1;
3569	/** 08 - Segment limit 16-19. */
3570	unsigned u4LimitHigh : 4;
3571	/** 0c - Available for system software. */
3572	unsigned u1Available : 1;
3573	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3574	unsigned u1Long : 1;
3575	/** 0e - This flags meaning depends on the segment type. Try make sense out
3576	* of the intel manual yourself. */
3577	unsigned u1DefBig : 1;
3578	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
3579	* clear byte. */
3580	unsigned u1Granularity : 1;
3581	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3582	unsigned u1Unusable : 1;
3583	} X86DESCATTRBITS;
3584	#endif /* !VBOX_FOR_DTRACE_LIB */
3585
3586	/** @name X86DESCATTR masks
3587	* @{ */
3588	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3589	#define X86DESCATTR_DT UINT32_C(0x00000010)
3590	#define X86DESCATTR_DPL UINT32_C(0x00000060)
3591	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
3592	#define X86DESCATTR_P UINT32_C(0x00000080)
3593	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3594	#define X86DESCATTR_AVL UINT32_C(0x00001000)
3595	#define X86DESCATTR_L UINT32_C(0x00002000)
3596	#define X86DESCATTR_D UINT32_C(0x00004000)
3597	#define X86DESCATTR_G UINT32_C(0x00008000)
3598	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3599	/** @} */
3600
3601	#pragma pack(1)
3602	typedef union X86DESCATTR
3603	{
3604	/** Unsigned integer view. */
3605	uint32_t u;
3606	#ifndef VBOX_FOR_DTRACE_LIB
3607	/** Normal view. */
3608	X86DESCATTRBITS n;
3609	#endif
3610	} X86DESCATTR;
3611	#pragma pack()
3612	/** Pointer to descriptor attributes. */
3613	typedef X86DESCATTR *PX86DESCATTR;
3614	/** Pointer to const descriptor attributes. */
3615	typedef const X86DESCATTR *PCX86DESCATTR;
3616
3617	#ifndef VBOX_FOR_DTRACE_LIB
3618
3619	/**
3620	* Generic descriptor table entry
3621	*/
3622	#pragma pack(1)
3623	typedef struct X86DESCGENERIC
3624	{
3625	/** 00 - Limit - Low word. */
3626	unsigned u16LimitLow : 16;
3627	/** 10 - Base address - low word.
3628	* Don't try set this to 24 because MSC is doing stupid things then. */
3629	unsigned u16BaseLow : 16;
3630	/** 20 - Base address - first 8 bits of high word. */
3631	unsigned u8BaseHigh1 : 8;
3632	/** 28 - Segment Type. */
3633	unsigned u4Type : 4;
3634	/** 2c - Descriptor Type. System(=0) or code/data selector */
3635	unsigned u1DescType : 1;
3636	/** 2d - Descriptor Privilege level. */
3637	unsigned u2Dpl : 2;
3638	/** 2f - Flags selector present(=1) or not. */
3639	unsigned u1Present : 1;
3640	/** 30 - Segment limit 16-19. */
3641	unsigned u4LimitHigh : 4;
3642	/** 34 - Available for system software. */
3643	unsigned u1Available : 1;
3644	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3645	unsigned u1Long : 1;
3646	/** 36 - This flags meaning depends on the segment type. Try make sense out
3647	* of the intel manual yourself. */
3648	unsigned u1DefBig : 1;
3649	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
3650	* clear byte. */
3651	unsigned u1Granularity : 1;
3652	/** 38 - Base address - highest 8 bits. */
3653	unsigned u8BaseHigh2 : 8;
3654	} X86DESCGENERIC;
3655	#pragma pack()
3656	/** Pointer to a generic descriptor entry. */
3657	typedef X86DESCGENERIC *PX86DESCGENERIC;
3658	/** Pointer to a const generic descriptor entry. */
3659	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3660
3661	/** @name Bit offsets of X86DESCGENERIC members.
3662	* @{*/
3663	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
3664	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
3665	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
3666	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
3667	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
3668	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
3669	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
3670	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
3671	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
3672	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
3673	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
3674	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
3675	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
3676	/** @} */
3677
3678
3679	/** @name LAR mask
3680	* @{ */
3681	#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3682	#define X86LAR_F_DT UINT16_C( 0x1000)
3683	#define X86LAR_F_DPL UINT16_C( 0x6000)
3684	#define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
3685	#define X86LAR_F_P UINT16_C( 0x8000)
3686	#define X86LAR_F_AVL UINT32_C(0x00100000)
3687	#define X86LAR_F_L UINT32_C(0x00200000)
3688	#define X86LAR_F_D UINT32_C(0x00400000)
3689	#define X86LAR_F_G UINT32_C(0x00800000)
3690	/** @} */
3691
3692
3693	/**
3694	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3695	*/
3696	typedef struct X86DESCGATE
3697	{
3698	/** 00 - Target code segment offset - Low word.
3699	* Ignored if task-gate. */
3700	unsigned u16OffsetLow : 16;
3701	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3702	* TSS selector if task-gate. */
3703	unsigned u16Sel : 16;
3704	/** 20 - Number of parameters for a call-gate.
3705	* Ignored if interrupt-, trap- or task-gate. */
3706	unsigned u5ParmCount : 5;
3707	/** 25 - Reserved / ignored. */
3708	unsigned u3Reserved : 3;
3709	/** 28 - Segment Type. */
3710	unsigned u4Type : 4;
3711	/** 2c - Descriptor Type (0 = system). */
3712	unsigned u1DescType : 1;
3713	/** 2d - Descriptor Privilege level. */
3714	unsigned u2Dpl : 2;
3715	/** 2f - Flags selector present(=1) or not. */
3716	unsigned u1Present : 1;
3717	/** 30 - Target code segment offset - High word.
3718	* Ignored if task-gate. */
3719	unsigned u16OffsetHigh : 16;
3720	} X86DESCGATE;
3721	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3722	typedef X86DESCGATE *PX86DESCGATE;
3723	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3724	typedef const X86DESCGATE *PCX86DESCGATE;
3725
3726	#endif /* VBOX_FOR_DTRACE_LIB */
3727
3728	/**
3729	* Descriptor table entry.
3730	*/
3731	#pragma pack(1)
3732	typedef union X86DESC
3733	{
3734	#ifndef VBOX_FOR_DTRACE_LIB
3735	/** Generic descriptor view. */
3736	X86DESCGENERIC Gen;
3737	/** Gate descriptor view. */
3738	X86DESCGATE Gate;
3739	#endif
3740
3741	/** 8 bit unsigned integer view. */
3742	uint8_t au8[8];
3743	/** 16 bit unsigned integer view. */
3744	uint16_t au16[4];
3745	/** 32 bit unsigned integer view. */
3746	uint32_t au32[2];
3747	/** 64 bit unsigned integer view. */
3748	uint64_t au64[1];
3749	/** Unsigned integer view. */
3750	uint64_t u;
3751	} X86DESC;
3752	#ifndef VBOX_FOR_DTRACE_LIB
3753	AssertCompileSize(X86DESC, 8);
3754	#endif
3755	#pragma pack()
3756	/** Pointer to descriptor table entry. */
3757	typedef X86DESC *PX86DESC;
3758	/** Pointer to const descriptor table entry. */
3759	typedef const X86DESC *PCX86DESC;
3760
3761	/** @def X86DESC_BASE
3762	* Return the base address of a descriptor.
3763	*/
3764	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
3765	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3766	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3767	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3768
3769	/** @def X86DESC_LIMIT
3770	* Return the limit of a descriptor.
3771	*/
3772	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
3773	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3774	\| ( (a_pDesc)->Gen.u16LimitLow ) )
3775
3776	/** @def X86DESC_LIMIT_G
3777	* Return the limit of a descriptor with the granularity bit taken into account.
3778	* @returns Selector limit (uint32_t).
3779	* @param a_pDesc Pointer to the descriptor.
3780	*/
3781	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
3782	( (a_pDesc)->Gen.u1Granularity \
3783	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
3784	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
3785	)
3786
3787	/** @def X86DESC_GET_HID_ATTR
3788	* Get the descriptor attributes for the hidden register.
3789	*/
3790	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
3791	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3792
3793	#ifndef VBOX_FOR_DTRACE_LIB
3794
3795	/**
3796	* 64 bits generic descriptor table entry
3797	* Note: most of these bits have no meaning in long mode.
3798	*/
3799	#pragma pack(1)
3800	typedef struct X86DESC64GENERIC
3801	{
3802	/** Limit - Low word - IGNORED. */
3803	uint32_t u16LimitLow : 16;
3804	/** Base address - low word. - IGNORED
3805	* Don't try set this to 24 because MSC is doing stupid things then. */
3806	uint32_t u16BaseLow : 16;
3807	/** Base address - first 8 bits of high word. - IGNORED */
3808	uint32_t u8BaseHigh1 : 8;
3809	/** Segment Type. */
3810	uint32_t u4Type : 4;
3811	/** Descriptor Type. System(=0) or code/data selector */
3812	uint32_t u1DescType : 1;
3813	/** Descriptor Privilege level. */
3814	uint32_t u2Dpl : 2;
3815	/** Flags selector present(=1) or not. */
3816	uint32_t u1Present : 1;
3817	/** Segment limit 16-19. - IGNORED */
3818	uint32_t u4LimitHigh : 4;
3819	/** Available for system software. - IGNORED */
3820	uint32_t u1Available : 1;
3821	/** Long mode flag. */
3822	uint32_t u1Long : 1;
3823	/** This flags meaning depends on the segment type. Try make sense out
3824	* of the intel manual yourself. */
3825	uint32_t u1DefBig : 1;
3826	/** Granularity of the limit. If set 4KB granularity is used, if
3827	* clear byte. - IGNORED */
3828	uint32_t u1Granularity : 1;
3829	/** Base address - highest 8 bits. - IGNORED */
3830	uint32_t u8BaseHigh2 : 8;
3831	/** Base address - bits 63-32. */
3832	uint32_t u32BaseHigh3 : 32;
3833	uint32_t u8Reserved : 8;
3834	uint32_t u5Zeros : 5;
3835	uint32_t u19Reserved : 19;
3836	} X86DESC64GENERIC;
3837	#pragma pack()
3838	/** Pointer to a generic descriptor entry. */
3839	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3840	/** Pointer to a const generic descriptor entry. */
3841	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3842
3843	/**
3844	* System descriptor table entry (64 bits)
3845	*
3846	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3847	*/
3848	#pragma pack(1)
3849	typedef struct X86DESC64SYSTEM
3850	{
3851	/** Limit - Low word. */
3852	uint32_t u16LimitLow : 16;
3853	/** Base address - low word.
3854	* Don't try set this to 24 because MSC is doing stupid things then. */
3855	uint32_t u16BaseLow : 16;
3856	/** Base address - first 8 bits of high word. */
3857	uint32_t u8BaseHigh1 : 8;
3858	/** Segment Type. */
3859	uint32_t u4Type : 4;
3860	/** Descriptor Type. System(=0) or code/data selector */
3861	uint32_t u1DescType : 1;
3862	/** Descriptor Privilege level. */
3863	uint32_t u2Dpl : 2;
3864	/** Flags selector present(=1) or not. */
3865	uint32_t u1Present : 1;
3866	/** Segment limit 16-19. */
3867	uint32_t u4LimitHigh : 4;
3868	/** Available for system software. */
3869	uint32_t u1Available : 1;
3870	/** Reserved - 0. */
3871	uint32_t u1Reserved : 1;
3872	/** This flags meaning depends on the segment type. Try make sense out
3873	* of the intel manual yourself. */
3874	uint32_t u1DefBig : 1;
3875	/** Granularity of the limit. If set 4KB granularity is used, if
3876	* clear byte. */
3877	uint32_t u1Granularity : 1;
3878	/** Base address - bits 31-24. */
3879	uint32_t u8BaseHigh2 : 8;
3880	/** Base address - bits 63-32. */
3881	uint32_t u32BaseHigh3 : 32;
3882	uint32_t u8Reserved : 8;
3883	uint32_t u5Zeros : 5;
3884	uint32_t u19Reserved : 19;
3885	} X86DESC64SYSTEM;
3886	#pragma pack()
3887	/** Pointer to a system descriptor entry. */
3888	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3889	/** Pointer to a const system descriptor entry. */
3890	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3891
3892	/**
3893	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3894	*/
3895	typedef struct X86DESC64GATE
3896	{
3897	/** Target code segment offset - Low word. */
3898	uint32_t u16OffsetLow : 16;
3899	/** Target code segment selector. */
3900	uint32_t u16Sel : 16;
3901	/** Interrupt stack table for interrupt- and trap-gates.
3902	* Ignored by call-gates. */
3903	uint32_t u3IST : 3;
3904	/** Reserved / ignored. */
3905	uint32_t u5Reserved : 5;
3906	/** Segment Type. */
3907	uint32_t u4Type : 4;
3908	/** Descriptor Type (0 = system). */
3909	uint32_t u1DescType : 1;
3910	/** Descriptor Privilege level. */
3911	uint32_t u2Dpl : 2;
3912	/** Flags selector present(=1) or not. */
3913	uint32_t u1Present : 1;
3914	/** Target code segment offset - High word.
3915	* Ignored if task-gate. */
3916	uint32_t u16OffsetHigh : 16;
3917	/** Target code segment offset - Top dword.
3918	* Ignored if task-gate. */
3919	uint32_t u32OffsetTop : 32;
3920	/** Reserved / ignored / must be zero.
3921	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3922	uint32_t u32Reserved : 32;
3923	} X86DESC64GATE;
3924	AssertCompileSize(X86DESC64GATE, 16);
3925	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3926	typedef X86DESC64GATE *PX86DESC64GATE;
3927	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3928	typedef const X86DESC64GATE *PCX86DESC64GATE;
3929
3930	#endif /* VBOX_FOR_DTRACE_LIB */
3931
3932	/**
3933	* Descriptor table entry.
3934	*/
3935	#pragma pack(1)
3936	typedef union X86DESC64
3937	{
3938	#ifndef VBOX_FOR_DTRACE_LIB
3939	/** Generic descriptor view. */
3940	X86DESC64GENERIC Gen;
3941	/** System descriptor view. */
3942	X86DESC64SYSTEM System;
3943	/** Gate descriptor view. */
3944	X86DESC64GATE Gate;
3945	#endif
3946
3947	/** 8 bit unsigned integer view. */
3948	uint8_t au8[16];
3949	/** 16 bit unsigned integer view. */
3950	uint16_t au16[8];
3951	/** 32 bit unsigned integer view. */
3952	uint32_t au32[4];
3953	/** 64 bit unsigned integer view. */
3954	uint64_t au64[2];
3955	} X86DESC64;
3956	#ifndef VBOX_FOR_DTRACE_LIB
3957	AssertCompileSize(X86DESC64, 16);
3958	#endif
3959	#pragma pack()
3960	/** Pointer to descriptor table entry. */
3961	typedef X86DESC64 *PX86DESC64;
3962	/** Pointer to const descriptor table entry. */
3963	typedef const X86DESC64 *PCX86DESC64;
3964
3965	/** @def X86DESC64_BASE
3966	* Return the base of a 64-bit descriptor.
3967	*/
3968	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
3969	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3970	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3971	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3972	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3973
3974
3975
3976	/** @name Host system descriptor table entry - Use with care!
3977	* @{ */
3978	/** Host system descriptor table entry. */
3979	#if HC_ARCH_BITS == 64
3980	typedef X86DESC64 X86DESCHC;
3981	#else
3982	typedef X86DESC X86DESCHC;
3983	#endif
3984	/** Pointer to a host system descriptor table entry. */
3985	#if HC_ARCH_BITS == 64
3986	typedef PX86DESC64 PX86DESCHC;
3987	#else
3988	typedef PX86DESC PX86DESCHC;
3989	#endif
3990	/** Pointer to a const host system descriptor table entry. */
3991	#if HC_ARCH_BITS == 64
3992	typedef PCX86DESC64 PCX86DESCHC;
3993	#else
3994	typedef PCX86DESC PCX86DESCHC;
3995	#endif
3996	/** @} */
3997
3998
3999	/** @name Selector Descriptor Types.
4000	* @{
4001	*/
4002
4003	/** @name Non-System Selector Types.
4004	* @{ */
4005	/** Code(=set)/Data(=clear) bit. */
4006	#define X86_SEL_TYPE_CODE 8
4007	/** Memory(=set)/System(=clear) bit. */
4008	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
4009	/** Accessed bit. */
4010	#define X86_SEL_TYPE_ACCESSED 1
4011	/** Expand down bit (for data selectors only). */
4012	#define X86_SEL_TYPE_DOWN 4
4013	/** Conforming bit (for code selectors only). */
4014	#define X86_SEL_TYPE_CONF 4
4015	/** Write bit (for data selectors only). */
4016	#define X86_SEL_TYPE_WRITE 2
4017	/** Read bit (for code selectors only). */
4018	#define X86_SEL_TYPE_READ 2
4019	/** The bit number of the code segment read bit (relative to u4Type). */
4020	#define X86_SEL_TYPE_READ_BIT 1
4021
4022	/** Read only selector type. */
4023	#define X86_SEL_TYPE_RO 0
4024	/** Accessed read only selector type. */
4025	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
4026	/** Read write selector type. */
4027	#define X86_SEL_TYPE_RW 2
4028	/** Accessed read write selector type. */
4029	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
4030	/** Expand down read only selector type. */
4031	#define X86_SEL_TYPE_RO_DOWN 4
4032	/** Accessed expand down read only selector type. */
4033	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
4034	/** Expand down read write selector type. */
4035	#define X86_SEL_TYPE_RW_DOWN 6
4036	/** Accessed expand down read write selector type. */
4037	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
4038	/** Execute only selector type. */
4039	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
4040	/** Accessed execute only selector type. */
4041	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4042	/** Execute and read selector type. */
4043	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
4044	/** Accessed execute and read selector type. */
4045	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4046	/** Conforming execute only selector type. */
4047	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
4048	/** Accessed Conforming execute only selector type. */
4049	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4050	/** Conforming execute and write selector type. */
4051	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
4052	/** Accessed Conforming execute and write selector type. */
4053	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4054	/** @} */
4055
4056
4057	/** @name System Selector Types.
4058	* @{ */
4059	/** The TSS busy bit mask. */
4060	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4061
4062	/** Undefined system selector type. */
4063	#define X86_SEL_TYPE_SYS_UNDEFINED 0
4064	/** 286 TSS selector. */
4065	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4066	/** LDT selector. */
4067	#define X86_SEL_TYPE_SYS_LDT 2
4068	/** 286 TSS selector - Busy. */
4069	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4070	/** 286 Callgate selector. */
4071	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4072	/** Taskgate selector. */
4073	#define X86_SEL_TYPE_SYS_TASK_GATE 5
4074	/** 286 Interrupt gate selector. */
4075	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4076	/** 286 Trapgate selector. */
4077	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4078	/** Undefined system selector. */
4079	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4080	/** 386 TSS selector. */
4081	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4082	/** Undefined system selector. */
4083	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4084	/** 386 TSS selector - Busy. */
4085	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4086	/** 386 Callgate selector. */
4087	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4088	/** Undefined system selector. */
4089	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4090	/** 386 Interruptgate selector. */
4091	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4092	/** 386 Trapgate selector. */
4093	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4094	/** @} */
4095
4096	/** @name AMD64 System Selector Types.
4097	* @{ */
4098	/** LDT selector. */
4099	#define AMD64_SEL_TYPE_SYS_LDT 2
4100	/** TSS selector - Busy. */
4101	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4102	/** TSS selector - Busy. */
4103	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4104	/** Callgate selector. */
4105	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4106	/** Interruptgate selector. */
4107	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4108	/** Trapgate selector. */
4109	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4110	/** @} */
4111
4112	/** @} */
4113
4114
4115	/** @name Descriptor Table Entry Flag Masks.
4116	* These are for the 2nd 32-bit word of a descriptor.
4117	* @{ */
4118	/** Bits 8-11 - TYPE - Descriptor type mask. */
4119	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
4120	/** Bit 12 - S - System (=0) or Code/Data (=1). */
4121	#define X86_DESC_S RT_BIT_32(12)
4122	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4123	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
4124	/** Bit 15 - P - Present. */
4125	#define X86_DESC_P RT_BIT_32(15)
4126	/** Bit 20 - AVL - Available for system software. */
4127	#define X86_DESC_AVL RT_BIT_32(20)
4128	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4129	#define X86_DESC_DB RT_BIT_32(22)
4130	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4131	* used, if clear byte. */
4132	#define X86_DESC_G RT_BIT_32(23)
4133	/** @} */
4134
4135	/** @} */
4136
4137
4138	/** @name Task Segments.
4139	* @{
4140	*/
4141
4142	/**
4143	* The minimum TSS descriptor limit for 286 tasks.
4144	*/
4145	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4146
4147	/**
4148	* The minimum TSS descriptor segment limit for 386 tasks.
4149	*/
4150	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4151
4152	/**
4153	* 16-bit Task Segment (TSS).
4154	*/
4155	#pragma pack(1)
4156	typedef struct X86TSS16
4157	{
4158	/** Back link to previous task. (static) */
4159	RTSEL selPrev;
4160	/** Ring-0 stack pointer. (static) */
4161	uint16_t sp0;
4162	/** Ring-0 stack segment. (static) */
4163	RTSEL ss0;
4164	/** Ring-1 stack pointer. (static) */
4165	uint16_t sp1;
4166	/** Ring-1 stack segment. (static) */
4167	RTSEL ss1;
4168	/** Ring-2 stack pointer. (static) */
4169	uint16_t sp2;
4170	/** Ring-2 stack segment. (static) */
4171	RTSEL ss2;
4172	/** IP before task switch. */
4173	uint16_t ip;
4174	/** FLAGS before task switch. */
4175	uint16_t flags;
4176	/** AX before task switch. */
4177	uint16_t ax;
4178	/** CX before task switch. */
4179	uint16_t cx;
4180	/** DX before task switch. */
4181	uint16_t dx;
4182	/** BX before task switch. */
4183	uint16_t bx;
4184	/** SP before task switch. */
4185	uint16_t sp;
4186	/** BP before task switch. */
4187	uint16_t bp;
4188	/** SI before task switch. */
4189	uint16_t si;
4190	/** DI before task switch. */
4191	uint16_t di;
4192	/** ES before task switch. */
4193	RTSEL es;
4194	/** CS before task switch. */
4195	RTSEL cs;
4196	/** SS before task switch. */
4197	RTSEL ss;
4198	/** DS before task switch. */
4199	RTSEL ds;
4200	/** LDTR before task switch. */
4201	RTSEL selLdt;
4202	} X86TSS16;
4203	#ifndef VBOX_FOR_DTRACE_LIB
4204	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4205	#endif
4206	#pragma pack()
4207	/** Pointer to a 16-bit task segment. */
4208	typedef X86TSS16 *PX86TSS16;
4209	/** Pointer to a const 16-bit task segment. */
4210	typedef const X86TSS16 *PCX86TSS16;
4211
4212
4213	/**
4214	* 32-bit Task Segment (TSS).
4215	*/
4216	#pragma pack(1)
4217	typedef struct X86TSS32
4218	{
4219	/** Back link to previous task. (static) */
4220	RTSEL selPrev;
4221	uint16_t padding1;
4222	/** Ring-0 stack pointer. (static) */
4223	uint32_t esp0;
4224	/** Ring-0 stack segment. (static) */
4225	RTSEL ss0;
4226	uint16_t padding_ss0;
4227	/** Ring-1 stack pointer. (static) */
4228	uint32_t esp1;
4229	/** Ring-1 stack segment. (static) */
4230	RTSEL ss1;
4231	uint16_t padding_ss1;
4232	/** Ring-2 stack pointer. (static) */
4233	uint32_t esp2;
4234	/** Ring-2 stack segment. (static) */
4235	RTSEL ss2;
4236	uint16_t padding_ss2;
4237	/** Page directory for the task. (static) */
4238	uint32_t cr3;
4239	/** EIP before task switch. */
4240	uint32_t eip;
4241	/** EFLAGS before task switch. */
4242	uint32_t eflags;
4243	/** EAX before task switch. */
4244	uint32_t eax;
4245	/** ECX before task switch. */
4246	uint32_t ecx;
4247	/** EDX before task switch. */
4248	uint32_t edx;
4249	/** EBX before task switch. */
4250	uint32_t ebx;
4251	/** ESP before task switch. */
4252	uint32_t esp;
4253	/** EBP before task switch. */
4254	uint32_t ebp;
4255	/** ESI before task switch. */
4256	uint32_t esi;
4257	/** EDI before task switch. */
4258	uint32_t edi;
4259	/** ES before task switch. */
4260	RTSEL es;
4261	uint16_t padding_es;
4262	/** CS before task switch. */
4263	RTSEL cs;
4264	uint16_t padding_cs;
4265	/** SS before task switch. */
4266	RTSEL ss;
4267	uint16_t padding_ss;
4268	/** DS before task switch. */
4269	RTSEL ds;
4270	uint16_t padding_ds;
4271	/** FS before task switch. */
4272	RTSEL fs;
4273	uint16_t padding_fs;
4274	/** GS before task switch. */
4275	RTSEL gs;
4276	uint16_t padding_gs;
4277	/** LDTR before task switch. */
4278	RTSEL selLdt;
4279	uint16_t padding_ldt;
4280	/** Debug trap flag */
4281	uint16_t fDebugTrap;
4282	/** Offset relative to the TSS of the start of the I/O Bitmap
4283	* and the end of the interrupt redirection bitmap. */
4284	uint16_t offIoBitmap;
4285	} X86TSS32;
4286	#pragma pack()
4287	/** Pointer to task segment. */
4288	typedef X86TSS32 *PX86TSS32;
4289	/** Pointer to const task segment. */
4290	typedef const X86TSS32 *PCX86TSS32;
4291	#ifndef VBOX_FOR_DTRACE_LIB
4292	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4293	AssertCompileMemberOffset(X86TSS32, cr3, 28);
4294	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4295	#endif
4296
4297	/**
4298	* 64-bit Task segment.
4299	*/
4300	#pragma pack(1)
4301	typedef struct X86TSS64
4302	{
4303	/** Reserved. */
4304	uint32_t u32Reserved;
4305	/** Ring-0 stack pointer. (static) */
4306	uint64_t rsp0;
4307	/** Ring-1 stack pointer. (static) */
4308	uint64_t rsp1;
4309	/** Ring-2 stack pointer. (static) */
4310	uint64_t rsp2;
4311	/** Reserved. */
4312	uint32_t u32Reserved2[2];
4313	/* IST */
4314	uint64_t ist1;
4315	uint64_t ist2;
4316	uint64_t ist3;
4317	uint64_t ist4;
4318	uint64_t ist5;
4319	uint64_t ist6;
4320	uint64_t ist7;
4321	/* Reserved. */
4322	uint16_t u16Reserved[5];
4323	/** Offset relative to the TSS of the start of the I/O Bitmap
4324	* and the end of the interrupt redirection bitmap. */
4325	uint16_t offIoBitmap;
4326	} X86TSS64;
4327	#pragma pack()
4328	/** Pointer to a 64-bit task segment. */
4329	typedef X86TSS64 *PX86TSS64;
4330	/** Pointer to a const 64-bit task segment. */
4331	typedef const X86TSS64 *PCX86TSS64;
4332	#ifndef VBOX_FOR_DTRACE_LIB
4333	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4334	#endif
4335
4336	/** @} */
4337
4338
4339	/** @name Selectors.
4340	* @{
4341	*/
4342
4343	/**
4344	* The shift used to convert a selector from and to index an index (C).
4345	*/
4346	#define X86_SEL_SHIFT 3
4347
4348	/**
4349	* The mask used to mask off the table indicator and RPL of an selector.
4350	*/
4351	#define X86_SEL_MASK 0xfff8U
4352
4353	/**
4354	* The mask used to mask off the RPL of an selector.
4355	* This is suitable for checking for NULL selectors.
4356	*/
4357	#define X86_SEL_MASK_OFF_RPL 0xfffcU
4358
4359	/**
4360	* The bit indicating that a selector is in the LDT and not in the GDT.
4361	*/
4362	#define X86_SEL_LDT 0x0004U
4363
4364	/**
4365	* The bit mask for getting the RPL of a selector.
4366	*/
4367	#define X86_SEL_RPL 0x0003U
4368
4369	/**
4370	* The mask covering both RPL and LDT.
4371	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4372	* checks.
4373	*/
4374	#define X86_SEL_RPL_LDT 0x0007U
4375
4376	/** @} */
4377
4378
4379	/**
4380	* x86 Exceptions/Faults/Traps.
4381	*/
4382	typedef enum X86XCPT
4383	{
4384	/** \#DE - Divide error. */
4385	X86_XCPT_DE = 0x00,
4386	/** \#DB - Debug event (single step, DRx, ..) */
4387	X86_XCPT_DB = 0x01,
4388	/** NMI - Non-Maskable Interrupt */
4389	X86_XCPT_NMI = 0x02,
4390	/** \#BP - Breakpoint (INT3). */
4391	X86_XCPT_BP = 0x03,
4392	/** \#OF - Overflow (INTO). */
4393	X86_XCPT_OF = 0x04,
4394	/** \#BR - Bound range exceeded (BOUND). */
4395	X86_XCPT_BR = 0x05,
4396	/** \#UD - Undefined opcode. */
4397	X86_XCPT_UD = 0x06,
4398	/** \#NM - Device not available (math coprocessor device). */
4399	X86_XCPT_NM = 0x07,
4400	/** \#DF - Double fault. */
4401	X86_XCPT_DF = 0x08,
4402	/** ??? - Coprocessor segment overrun (obsolete). */
4403	X86_XCPT_CO_SEG_OVERRUN = 0x09,
4404	/** \#TS - Taskswitch (TSS). */
4405	X86_XCPT_TS = 0x0a,
4406	/** \#NP - Segment no present. */
4407	X86_XCPT_NP = 0x0b,
4408	/** \#SS - Stack segment fault. */
4409	X86_XCPT_SS = 0x0c,
4410	/** \#GP - General protection fault. */
4411	X86_XCPT_GP = 0x0d,
4412	/** \#PF - Page fault. */
4413	X86_XCPT_PF = 0x0e,
4414	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4415	/** \#MF - Math fault (FPU). */
4416	X86_XCPT_MF = 0x10,
4417	/** \#AC - Alignment check. */
4418	X86_XCPT_AC = 0x11,
4419	/** \#MC - Machine check. */
4420	X86_XCPT_MC = 0x12,
4421	/** \#XF - SIMD Floating-Point Exception. */
4422	X86_XCPT_XF = 0x13,
4423	/** \#VE - Virtualization Exception (Intel only). */
4424	X86_XCPT_VE = 0x14,
4425	/** \#CP - Control Protection Exception (Intel only). */
4426	X86_XCPT_CP = 0x15,
4427	/** \#VC - VMM Communication Exception (AMD only). */
4428	X86_XCPT_VC = 0x1d,
4429	/** \#SX - Security Exception (AMD only). */
4430	X86_XCPT_SX = 0x1e
4431	} X86XCPT;
4432	/** Pointer to a x86 exception code. */
4433	typedef X86XCPT *PX86XCPT;
4434	/** Pointer to a const x86 exception code. */
4435	typedef const X86XCPT *PCX86XCPT;
4436	/** The last valid (currently reserved) exception value. */
4437	#define X86_XCPT_LAST 0x1f
4438
4439
4440	/** @name Trap Error Codes
4441	* @{
4442	*/
4443	/** External indicator. */
4444	#define X86_TRAP_ERR_EXTERNAL 1
4445	/** IDT indicator. */
4446	#define X86_TRAP_ERR_IDT 2
4447	/** Descriptor table indicator - If set LDT, if clear GDT. */
4448	#define X86_TRAP_ERR_TI 4
4449	/** Mask for getting the selector. */
4450	#define X86_TRAP_ERR_SEL_MASK 0xfff8
4451	/** Shift for getting the selector table index (C type index). */
4452	#define X86_TRAP_ERR_SEL_SHIFT 3
4453	/** @} */
4454
4455
4456	/** @name \#PF Trap Error Codes
4457	* @{
4458	*/
4459	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4460	#define X86_TRAP_PF_P RT_BIT_32(0)
4461	/** Bit 1 - R/W - Read (clear) or write (set) access. */
4462	#define X86_TRAP_PF_RW RT_BIT_32(1)
4463	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4464	#define X86_TRAP_PF_US RT_BIT_32(2)
4465	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4466	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4467	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4468	#define X86_TRAP_PF_ID RT_BIT_32(4)
4469	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4470	#define X86_TRAP_PF_PK RT_BIT_32(5)
4471	/** @} */
4472
4473	#pragma pack(1)
4474	/**
4475	* 16-bit IDTR.
4476	*/
4477	typedef struct X86IDTR16
4478	{
4479	/** Offset. */
4480	uint16_t offSel;
4481	/** Selector. */
4482	uint16_t uSel;
4483	} X86IDTR16, *PX86IDTR16;
4484	#pragma pack()
4485
4486	#pragma pack(1)
4487	/**
4488	* 32-bit IDTR/GDTR.
4489	*/
4490	typedef struct X86XDTR32
4491	{
4492	/** Size of the descriptor table. */
4493	uint16_t cb;
4494	/** Address of the descriptor table. */
4495	#ifndef VBOX_FOR_DTRACE_LIB
4496	uint32_t uAddr;
4497	#else
4498	uint16_t au16Addr[2];
4499	#endif
4500	} X86XDTR32, *PX86XDTR32;
4501	#pragma pack()
4502
4503	#pragma pack(1)
4504	/**
4505	* 64-bit IDTR/GDTR.
4506	*/
4507	typedef struct X86XDTR64
4508	{
4509	/** Size of the descriptor table. */
4510	uint16_t cb;
4511	/** Address of the descriptor table. */
4512	#ifndef VBOX_FOR_DTRACE_LIB
4513	uint64_t uAddr;
4514	#else
4515	uint16_t au16Addr[4];
4516	#endif
4517	} X86XDTR64, *PX86XDTR64;
4518	#pragma pack()
4519
4520
4521	/** @name ModR/M
4522	* @{ */
4523	#define X86_MODRM_RM_MASK UINT8_C(0x07)
4524	#define X86_MODRM_REG_MASK UINT8_C(0x38)
4525	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4526	#define X86_MODRM_REG_SHIFT 3
4527	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4528	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4529	#define X86_MODRM_MOD_SHIFT 6
4530	#ifndef VBOX_FOR_DTRACE_LIB
4531	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
4532	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4533	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4534	/** @def X86_MODRM_MAKE
4535	* @param a_Mod The mod value (0..3).
4536	* @param a_Reg The register value (0..7).
4537	* @param a_RegMem The register or memory value (0..7). */
4538	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
4539	#endif
4540	/** @} */
4541
4542	/** @name SIB
4543	* @{ */
4544	#define X86_SIB_BASE_MASK UINT8_C(0x07)
4545	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4546	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4547	#define X86_SIB_INDEX_SHIFT 3
4548	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4549	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4550	#define X86_SIB_SCALE_SHIFT 6
4551	#ifndef VBOX_FOR_DTRACE_LIB
4552	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
4553	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4554	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4555	#endif
4556	/** @} */
4557
4558	/** @name General register indexes.
4559	* @{ */
4560	#define X86_GREG_xAX 0
4561	#define X86_GREG_xCX 1
4562	#define X86_GREG_xDX 2
4563	#define X86_GREG_xBX 3
4564	#define X86_GREG_xSP 4
4565	#define X86_GREG_xBP 5
4566	#define X86_GREG_xSI 6
4567	#define X86_GREG_xDI 7
4568	#define X86_GREG_x8 8
4569	#define X86_GREG_x9 9
4570	#define X86_GREG_x10 10
4571	#define X86_GREG_x11 11
4572	#define X86_GREG_x12 12
4573	#define X86_GREG_x13 13
4574	#define X86_GREG_x14 14
4575	#define X86_GREG_x15 15
4576	/** @} */
4577	/** General register count. */
4578	#define X86_GREG_COUNT 16
4579
4580	/** @name X86_SREG_XXX - Segment register indexes.
4581	* @{ */
4582	#define X86_SREG_ES 0
4583	#define X86_SREG_CS 1
4584	#define X86_SREG_SS 2
4585	#define X86_SREG_DS 3
4586	#define X86_SREG_FS 4
4587	#define X86_SREG_GS 5
4588	/** @} */
4589	/** Segment register count. */
4590	#define X86_SREG_COUNT 6
4591
4592
4593	/** @name X86_OP_XXX - Prefixes
4594	* @{ */
4595	#define X86_OP_PRF_CS UINT8_C(0x2e)
4596	#define X86_OP_PRF_SS UINT8_C(0x36)
4597	#define X86_OP_PRF_DS UINT8_C(0x3e)
4598	#define X86_OP_PRF_ES UINT8_C(0x26)
4599	#define X86_OP_PRF_FS UINT8_C(0x64)
4600	#define X86_OP_PRF_GS UINT8_C(0x65)
4601	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4602	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4603	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4604	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4605	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4606	#define X86_OP_REX_B UINT8_C(0x41)
4607	#define X86_OP_REX_X UINT8_C(0x42)
4608	#define X86_OP_REX_R UINT8_C(0x44)
4609	#define X86_OP_REX_W UINT8_C(0x48)
4610	/** @} */
4611
4612
4613	/** @} */
4614
4615	#endif /* !IPRT_INCLUDED_x86_h */
4616

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/include/iprt/x86.h@ 85524

Download in other formats: