x86.h@ 90607

Last change on this file since 90607 was 89475, checked in by vboxsync, 4 years ago
Intel IOMMU: bugref:9967 x86.h: Macros for getting page base and offset masks (for upcoming changes and will replace similar macros in AMD IOMMU code as well).
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File size: 175.9 KB

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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2020 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef IPRT_INCLUDED_x86_h
29	#define IPRT_INCLUDED_x86_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef VBOX_FOR_DTRACE_LIB
35	# include <iprt/types.h>
36	# include <iprt/assert.h>
37	#else
38	# pragma D depends_on library vbox-types.d
39	#endif
40
41	/** Workaround for Solaris sys/regset.h defining CS, DS and sys/controlregs.h
42	* defining MSR_IA32_FLUSH_CMD */
43	#ifdef RT_OS_SOLARIS
44	# undef CS
45	# undef DS
46	# undef MSR_IA32_FLUSH_CMD
47	#endif
48
49	/** @defgroup grp_rt_x86 x86 Types and Definitions
50	* @ingroup grp_rt
51	* @{
52	*/
53
54	#ifndef VBOX_FOR_DTRACE_LIB
55	/**
56	* EFLAGS Bits.
57	*/
58	typedef struct X86EFLAGSBITS
59	{
60	/** Bit 0 - CF - Carry flag - Status flag. */
61	unsigned u1CF : 1;
62	/** Bit 1 - 1 - Reserved flag. */
63	unsigned u1Reserved0 : 1;
64	/** Bit 2 - PF - Parity flag - Status flag. */
65	unsigned u1PF : 1;
66	/** Bit 3 - 0 - Reserved flag. */
67	unsigned u1Reserved1 : 1;
68	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
69	unsigned u1AF : 1;
70	/** Bit 5 - 0 - Reserved flag. */
71	unsigned u1Reserved2 : 1;
72	/** Bit 6 - ZF - Zero flag - Status flag. */
73	unsigned u1ZF : 1;
74	/** Bit 7 - SF - Signed flag - Status flag. */
75	unsigned u1SF : 1;
76	/** Bit 8 - TF - Trap flag - System flag. */
77	unsigned u1TF : 1;
78	/** Bit 9 - IF - Interrupt flag - System flag. */
79	unsigned u1IF : 1;
80	/** Bit 10 - DF - Direction flag - Control flag. */
81	unsigned u1DF : 1;
82	/** Bit 11 - OF - Overflow flag - Status flag. */
83	unsigned u1OF : 1;
84	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
85	unsigned u2IOPL : 2;
86	/** Bit 14 - NT - Nested task flag - System flag. */
87	unsigned u1NT : 1;
88	/** Bit 15 - 0 - Reserved flag. */
89	unsigned u1Reserved3 : 1;
90	/** Bit 16 - RF - Resume flag - System flag. */
91	unsigned u1RF : 1;
92	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
93	unsigned u1VM : 1;
94	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
95	unsigned u1AC : 1;
96	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
97	unsigned u1VIF : 1;
98	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
99	unsigned u1VIP : 1;
100	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
101	unsigned u1ID : 1;
102	/** Bit 22-31 - 0 - Reserved flag. */
103	unsigned u10Reserved4 : 10;
104	} X86EFLAGSBITS;
105	/** Pointer to EFLAGS bits. */
106	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
107	/** Pointer to const EFLAGS bits. */
108	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
109	#endif /* !VBOX_FOR_DTRACE_LIB */
110
111	/**
112	* EFLAGS.
113	*/
114	typedef union X86EFLAGS
115	{
116	/** The plain unsigned view. */
117	uint32_t u;
118	#ifndef VBOX_FOR_DTRACE_LIB
119	/** The bitfield view. */
120	X86EFLAGSBITS Bits;
121	#endif
122	/** The 8-bit view. */
123	uint8_t au8[4];
124	/** The 16-bit view. */
125	uint16_t au16[2];
126	/** The 32-bit view. */
127	uint32_t au32[1];
128	/** The 32-bit view. */
129	uint32_t u32;
130	} X86EFLAGS;
131	/** Pointer to EFLAGS. */
132	typedef X86EFLAGS *PX86EFLAGS;
133	/** Pointer to const EFLAGS. */
134	typedef const X86EFLAGS *PCX86EFLAGS;
135
136	/**
137	* RFLAGS (32 upper bits are reserved).
138	*/
139	typedef union X86RFLAGS
140	{
141	/** The plain unsigned view. */
142	uint64_t u;
143	#ifndef VBOX_FOR_DTRACE_LIB
144	/** The bitfield view. */
145	X86EFLAGSBITS Bits;
146	#endif
147	/** The 8-bit view. */
148	uint8_t au8[8];
149	/** The 16-bit view. */
150	uint16_t au16[4];
151	/** The 32-bit view. */
152	uint32_t au32[2];
153	/** The 64-bit view. */
154	uint64_t au64[1];
155	/** The 64-bit view. */
156	uint64_t u64;
157	} X86RFLAGS;
158	/** Pointer to RFLAGS. */
159	typedef X86RFLAGS *PX86RFLAGS;
160	/** Pointer to const RFLAGS. */
161	typedef const X86RFLAGS *PCX86RFLAGS;
162
163
164	/** @name EFLAGS
165	* @{
166	*/
167	/** Bit 0 - CF - Carry flag - Status flag. */
168	#define X86_EFL_CF RT_BIT_32(0)
169	#define X86_EFL_CF_BIT 0
170	/** Bit 1 - Reserved, reads as 1. */
171	#define X86_EFL_1 RT_BIT_32(1)
172	/** Bit 2 - PF - Parity flag - Status flag. */
173	#define X86_EFL_PF RT_BIT_32(2)
174	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
175	#define X86_EFL_AF RT_BIT_32(4)
176	#define X86_EFL_AF_BIT 4
177	/** Bit 6 - ZF - Zero flag - Status flag. */
178	#define X86_EFL_ZF RT_BIT_32(6)
179	#define X86_EFL_ZF_BIT 6
180	/** Bit 7 - SF - Signed flag - Status flag. */
181	#define X86_EFL_SF RT_BIT_32(7)
182	#define X86_EFL_SF_BIT 7
183	/** Bit 8 - TF - Trap flag - System flag. */
184	#define X86_EFL_TF RT_BIT_32(8)
185	/** Bit 9 - IF - Interrupt flag - System flag. */
186	#define X86_EFL_IF RT_BIT_32(9)
187	/** Bit 10 - DF - Direction flag - Control flag. */
188	#define X86_EFL_DF RT_BIT_32(10)
189	/** Bit 11 - OF - Overflow flag - Status flag. */
190	#define X86_EFL_OF RT_BIT_32(11)
191	#define X86_EFL_OF_BIT 11
192	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
193	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
194	/** Bit 14 - NT - Nested task flag - System flag. */
195	#define X86_EFL_NT RT_BIT_32(14)
196	/** Bit 16 - RF - Resume flag - System flag. */
197	#define X86_EFL_RF RT_BIT_32(16)
198	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
199	#define X86_EFL_VM RT_BIT_32(17)
200	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
201	#define X86_EFL_AC RT_BIT_32(18)
202	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
203	#define X86_EFL_VIF RT_BIT_32(19)
204	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
205	#define X86_EFL_VIP RT_BIT_32(20)
206	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
207	#define X86_EFL_ID RT_BIT_32(21)
208	/** All live bits. */
209	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
210	/** Read as 1 bits. */
211	#define X86_EFL_RA1_MASK RT_BIT_32(1)
212	/** IOPL shift. */
213	#define X86_EFL_IOPL_SHIFT 12
214	/** The IOPL level from the flags. */
215	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
216	/** Bits restored by popf */
217	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
218	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
219	/** Bits restored by popf */
220	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
221	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
222	/** The status bits commonly updated by arithmetic instructions. */
223	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
224	/** @} */
225
226
227	/** CPUID Feature information - ECX.
228	* CPUID query with EAX=1.
229	*/
230	#ifndef VBOX_FOR_DTRACE_LIB
231	typedef struct X86CPUIDFEATECX
232	{
233	/** Bit 0 - SSE3 - Supports SSE3 or not. */
234	unsigned u1SSE3 : 1;
235	/** Bit 1 - PCLMULQDQ. */
236	unsigned u1PCLMULQDQ : 1;
237	/** Bit 2 - DS Area 64-bit layout. */
238	unsigned u1DTE64 : 1;
239	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
240	unsigned u1Monitor : 1;
241	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
242	unsigned u1CPLDS : 1;
243	/** Bit 5 - VMX - Virtual Machine Technology. */
244	unsigned u1VMX : 1;
245	/** Bit 6 - SMX: Safer Mode Extensions. */
246	unsigned u1SMX : 1;
247	/** Bit 7 - EST - Enh. SpeedStep Tech. */
248	unsigned u1EST : 1;
249	/** Bit 8 - TM2 - Terminal Monitor 2. */
250	unsigned u1TM2 : 1;
251	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
252	unsigned u1SSSE3 : 1;
253	/** Bit 10 - CNTX-ID - L1 Context ID. */
254	unsigned u1CNTXID : 1;
255	/** Bit 11 - Reserved. */
256	unsigned u1Reserved1 : 1;
257	/** Bit 12 - FMA. */
258	unsigned u1FMA : 1;
259	/** Bit 13 - CX16 - CMPXCHG16B. */
260	unsigned u1CX16 : 1;
261	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
262	unsigned u1TPRUpdate : 1;
263	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
264	unsigned u1PDCM : 1;
265	/** Bit 16 - Reserved. */
266	unsigned u1Reserved2 : 1;
267	/** Bit 17 - PCID - Process-context identifiers. */
268	unsigned u1PCID : 1;
269	/** Bit 18 - Direct Cache Access. */
270	unsigned u1DCA : 1;
271	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
272	unsigned u1SSE4_1 : 1;
273	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
274	unsigned u1SSE4_2 : 1;
275	/** Bit 21 - x2APIC. */
276	unsigned u1x2APIC : 1;
277	/** Bit 22 - MOVBE - Supports MOVBE. */
278	unsigned u1MOVBE : 1;
279	/** Bit 23 - POPCNT - Supports POPCNT. */
280	unsigned u1POPCNT : 1;
281	/** Bit 24 - TSC-Deadline. */
282	unsigned u1TSCDEADLINE : 1;
283	/** Bit 25 - AES. */
284	unsigned u1AES : 1;
285	/** Bit 26 - XSAVE - Supports XSAVE. */
286	unsigned u1XSAVE : 1;
287	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
288	unsigned u1OSXSAVE : 1;
289	/** Bit 28 - AVX - Supports AVX instruction extensions. */
290	unsigned u1AVX : 1;
291	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
292	unsigned u1F16C : 1;
293	/** Bit 30 - RDRAND - Supports RDRAND. */
294	unsigned u1RDRAND : 1;
295	/** Bit 31 - Hypervisor present (we're a guest). */
296	unsigned u1HVP : 1;
297	} X86CPUIDFEATECX;
298	#else /* VBOX_FOR_DTRACE_LIB */
299	typedef uint32_t X86CPUIDFEATECX;
300	#endif /* VBOX_FOR_DTRACE_LIB */
301	/** Pointer to CPUID Feature Information - ECX. */
302	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
303	/** Pointer to const CPUID Feature Information - ECX. */
304	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
305
306
307	/** CPUID Feature Information - EDX.
308	* CPUID query with EAX=1.
309	*/
310	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
311	typedef struct X86CPUIDFEATEDX
312	{
313	/** Bit 0 - FPU - x87 FPU on Chip. */
314	unsigned u1FPU : 1;
315	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
316	unsigned u1VME : 1;
317	/** Bit 2 - DE - Debugging extensions. */
318	unsigned u1DE : 1;
319	/** Bit 3 - PSE - Page Size Extension. */
320	unsigned u1PSE : 1;
321	/** Bit 4 - TSC - Time Stamp Counter. */
322	unsigned u1TSC : 1;
323	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
324	unsigned u1MSR : 1;
325	/** Bit 6 - PAE - Physical Address Extension. */
326	unsigned u1PAE : 1;
327	/** Bit 7 - MCE - Machine Check Exception. */
328	unsigned u1MCE : 1;
329	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
330	unsigned u1CX8 : 1;
331	/** Bit 9 - APIC - APIC On-Chip. */
332	unsigned u1APIC : 1;
333	/** Bit 10 - Reserved. */
334	unsigned u1Reserved1 : 1;
335	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
336	unsigned u1SEP : 1;
337	/** Bit 12 - MTRR - Memory Type Range Registers. */
338	unsigned u1MTRR : 1;
339	/** Bit 13 - PGE - PTE Global Bit. */
340	unsigned u1PGE : 1;
341	/** Bit 14 - MCA - Machine Check Architecture. */
342	unsigned u1MCA : 1;
343	/** Bit 15 - CMOV - Conditional Move Instructions. */
344	unsigned u1CMOV : 1;
345	/** Bit 16 - PAT - Page Attribute Table. */
346	unsigned u1PAT : 1;
347	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
348	unsigned u1PSE36 : 1;
349	/** Bit 18 - PSN - Processor Serial Number. */
350	unsigned u1PSN : 1;
351	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
352	unsigned u1CLFSH : 1;
353	/** Bit 20 - Reserved. */
354	unsigned u1Reserved2 : 1;
355	/** Bit 21 - DS - Debug Store. */
356	unsigned u1DS : 1;
357	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
358	unsigned u1ACPI : 1;
359	/** Bit 23 - MMX - Intel MMX 'Technology'. */
360	unsigned u1MMX : 1;
361	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
362	unsigned u1FXSR : 1;
363	/** Bit 25 - SSE - SSE Support. */
364	unsigned u1SSE : 1;
365	/** Bit 26 - SSE2 - SSE2 Support. */
366	unsigned u1SSE2 : 1;
367	/** Bit 27 - SS - Self Snoop. */
368	unsigned u1SS : 1;
369	/** Bit 28 - HTT - Hyper-Threading Technology. */
370	unsigned u1HTT : 1;
371	/** Bit 29 - TM - Thermal Monitor. */
372	unsigned u1TM : 1;
373	/** Bit 30 - Reserved - . */
374	unsigned u1Reserved3 : 1;
375	/** Bit 31 - PBE - Pending Break Enabled. */
376	unsigned u1PBE : 1;
377	} X86CPUIDFEATEDX;
378	#else /* VBOX_FOR_DTRACE_LIB */
379	typedef uint32_t X86CPUIDFEATEDX;
380	#endif /* VBOX_FOR_DTRACE_LIB */
381	/** Pointer to CPUID Feature Information - EDX. */
382	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
383	/** Pointer to const CPUID Feature Information - EDX. */
384	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
385
386	/** @name CPUID Vendor information.
387	* CPUID query with EAX=0.
388	* @{
389	*/
390	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
391	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
392	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
393
394	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
395	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
396	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
397
398	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
399	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
400	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
401
402	#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
403	#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
404	#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
405
406	#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
407	#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
408	#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
409	/** @} */
410
411
412	/** @name CPUID Feature information.
413	* CPUID query with EAX=1.
414	* @{
415	*/
416	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
417	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
418	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
419	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
420	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
421	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
422	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
423	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
424	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
425	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
426	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
427	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
428	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
429	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
430	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
431	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
432	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
433	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
434	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
435	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
436	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
437	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
438	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
439	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
440	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
441	/** ECX Bit 12 - FMA. */
442	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
443	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
444	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
445	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
446	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
447	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
448	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
449	/** ECX Bit 17 - PCID - Process-context identifiers. */
450	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
451	/** ECX Bit 18 - DCA - Direct Cache Access. */
452	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
453	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
454	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
455	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
456	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
457	/** ECX Bit 21 - x2APIC support. */
458	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
459	/** ECX Bit 22 - MOVBE instruction. */
460	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
461	/** ECX Bit 23 - POPCNT instruction. */
462	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
463	/** ECX Bir 24 - TSC-Deadline. */
464	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
465	/** ECX Bit 25 - AES instructions. */
466	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
467	/** ECX Bit 26 - XSAVE instruction. */
468	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
469	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
470	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
471	/** ECX Bit 28 - AVX. */
472	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
473	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
474	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
475	/** ECX Bit 30 - RDRAND instruction. */
476	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
477	/** ECX Bit 31 - Hypervisor Present (software only). */
478	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
479
480
481	/** Bit 0 - FPU - x87 FPU on Chip. */
482	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
483	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
484	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
485	/** Bit 2 - DE - Debugging extensions. */
486	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
487	/** Bit 3 - PSE - Page Size Extension. */
488	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
489	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
490	/** Bit 4 - TSC - Time Stamp Counter. */
491	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
492	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
493	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
494	/** Bit 6 - PAE - Physical Address Extension. */
495	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
496	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
497	/** Bit 7 - MCE - Machine Check Exception. */
498	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
499	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
500	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
501	/** Bit 9 - APIC - APIC On-Chip. */
502	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
503	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
504	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
505	/** Bit 12 - MTRR - Memory Type Range Registers. */
506	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
507	/** Bit 13 - PGE - PTE Global Bit. */
508	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
509	/** Bit 14 - MCA - Machine Check Architecture. */
510	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
511	/** Bit 15 - CMOV - Conditional Move Instructions. */
512	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
513	/** Bit 16 - PAT - Page Attribute Table. */
514	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
515	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
516	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
517	/** Bit 18 - PSN - Processor Serial Number. */
518	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
519	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
520	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
521	/** Bit 21 - DS - Debug Store. */
522	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
523	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
524	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
525	/** Bit 23 - MMX - Intel MMX Technology. */
526	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
527	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
528	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
529	/** Bit 25 - SSE - SSE Support. */
530	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
531	/** Bit 26 - SSE2 - SSE2 Support. */
532	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
533	/** Bit 27 - SS - Self Snoop. */
534	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
535	/** Bit 28 - HTT - Hyper-Threading Technology. */
536	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
537	/** Bit 29 - TM - Therm. Monitor. */
538	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
539	/** Bit 31 - PBE - Pending Break Enabled. */
540	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
541	/** @} */
542
543	/** @name CPUID mwait/monitor information.
544	* CPUID query with EAX=5.
545	* @{
546	*/
547	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
548	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
549	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
550	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
551	/** @} */
552
553
554	/** @name CPUID Structured Extended Feature information.
555	* CPUID query with EAX=7.
556	* @{
557	*/
558	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
559	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
560	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
561	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
562	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
563	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
564	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
565	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
566	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
567	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
568	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
569	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
570	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
571	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
572	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
573	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
574	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
575	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
576	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
577	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
578	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
579	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
580	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
581	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
582	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
583	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
584	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
585	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
586	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
587	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
588	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
589	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
590	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
591	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
592	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
593	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
594	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
595	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
596	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
597	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
598	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
599	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
600	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
601	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
602	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
603	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
604	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
605	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
606	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
607	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
608	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
609	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
610
611	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
612	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
613	/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
614	#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
615	/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
616	#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
617	/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
618	#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
619	/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
620	#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
621	/** ECX Bit 22 - RDPID - Support pread process ID. */
622	#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
623	/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
624	#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
625
626	/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
627	#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
628	/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
629	* IBPB command in IA32_PRED_CMD. */
630	#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
631	/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
632	#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
633	/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
634	#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
635	/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
636	#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
637	/** EDX Bit 31 - SSBD - Supports the SSBD flag in IA32_SPEC_CTRL. */
638	#define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
639
640	/** @} */
641
642
643	/** @name CPUID Extended Feature information.
644	* CPUID query with EAX=0x80000001.
645	* @{
646	*/
647	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
648	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
649
650	/** EDX Bit 11 - SYSCALL/SYSRET. */
651	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
652	/** EDX Bit 20 - No-Execute/Execute-Disable. */
653	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
654	/** EDX Bit 26 - 1 GB large page. */
655	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
656	/** EDX Bit 27 - RDTSCP. */
657	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
658	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
659	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
660	/** @}*/
661
662	/** @name CPUID AMD Feature information.
663	* CPUID query with EAX=0x80000001.
664	* @{
665	*/
666	/** Bit 0 - FPU - x87 FPU on Chip. */
667	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
668	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
669	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
670	/** Bit 2 - DE - Debugging extensions. */
671	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
672	/** Bit 3 - PSE - Page Size Extension. */
673	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
674	/** Bit 4 - TSC - Time Stamp Counter. */
675	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
676	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
677	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
678	/** Bit 6 - PAE - Physical Address Extension. */
679	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
680	/** Bit 7 - MCE - Machine Check Exception. */
681	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
682	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
683	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
684	/** Bit 9 - APIC - APIC On-Chip. */
685	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
686	/** Bit 12 - MTRR - Memory Type Range Registers. */
687	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
688	/** Bit 13 - PGE - PTE Global Bit. */
689	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
690	/** Bit 14 - MCA - Machine Check Architecture. */
691	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
692	/** Bit 15 - CMOV - Conditional Move Instructions. */
693	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
694	/** Bit 16 - PAT - Page Attribute Table. */
695	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
696	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
697	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
698	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
699	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
700	/** Bit 23 - MMX - Intel MMX Technology. */
701	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
702	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
703	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
704	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
705	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
706	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
707	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
708	/** Bit 31 - 3DNOW - AMD 3DNow. */
709	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
710
711	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
712	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
713	/** Bit 2 - SVM - AMD VM extensions. */
714	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
715	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
716	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
717	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
718	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
719	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
720	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
721	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
722	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
723	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
724	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
725	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
726	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
727	/** Bit 9 - OSVW - AMD OS visible workaround. */
728	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
729	/** Bit 10 - IBS - Instruct based sampling. */
730	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
731	/** Bit 11 - XOP - Extended operation support (see APM6). */
732	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
733	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
734	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
735	/** Bit 13 - WDT - AMD Watchdog timer support. */
736	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
737	/** Bit 15 - LWP - Lightweight profiling support. */
738	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
739	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
740	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
741	/** Bit 19 - NodeId - Indicates support for
742	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
743	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
744	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
745	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
746	/** Bit 22 - TopologyExtensions - . */
747	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
748	/** @} */
749
750
751	/** @name CPUID AMD Feature information.
752	* CPUID query with EAX=0x80000007.
753	* @{
754	*/
755	/** Bit 0 - TS - Temperature Sensor. */
756	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
757	/** Bit 1 - FID - Frequency ID Control. */
758	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
759	/** Bit 2 - VID - Voltage ID Control. */
760	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
761	/** Bit 3 - TTP - THERMTRIP. */
762	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
763	/** Bit 4 - TM - Hardware Thermal Control. */
764	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
765	/** Bit 5 - STC - Software Thermal Control. */
766	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
767	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
768	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
769	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
770	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
771	/** Bit 8 - TSCINVAR - TSC Invariant. */
772	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
773	/** Bit 9 - CPB - TSC Invariant. */
774	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
775	/** Bit 10 - EffFreqRO - MPERF/APERF. */
776	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
777	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
778	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
779	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
780	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
781	/** @} */
782
783
784	/** @name CPUID AMD extended feature extensions ID (EBX).
785	* CPUID query with EAX=0x80000008.
786	* @{
787	*/
788	/** Bit 0 - CLZERO - Clear zero instruction. */
789	#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
790	/** Bit 1 - IRPerf - Instructions retired count support. */
791	#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
792	/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
793	#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
794	/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
795	#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
796	/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
797	#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
798	/* AMD pipeline length: 9 feature bits ;-) */
799	/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
800	#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
801	/** Bit 14 - IBRS - Supports the IBRS bit in IA32_SPEC_CTRL. */
802	#define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
803	/** Bit 15 - STIBP - Supports the STIBP bit in IA32_SPEC_CTRL. */
804	#define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
805	/** Bit 16 - IBRS always on mode - IBRS should be set once during boot only. */
806	#define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
807	/** Bit 17 - STIBP always on mode - STIBP should be set once during boot only. */
808	#define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
809	/** Bit 18 - IBRS preferred - IBRS is preferred over software mitigations. */
810	#define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
811	/** Bit 24 - Speculative Store Bypass Disable supported in SPEC_CTL. */
812	#define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
813	/** Bit 25 - Speculative Store Bypass Disable supported in VIRT_SPEC_CTL. */
814	#define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
815	/** Bit 26 - Speculative Store Bypass Disable not required. */
816	#define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
817	/** @} */
818
819
820	/** @name CPUID AMD SVM Feature information.
821	* CPUID query with EAX=0x8000000a.
822	* @{
823	*/
824	/** Bit 0 - NP - Nested Paging supported. */
825	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
826	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
827	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
828	/** Bit 2 - SVML - SVM locking bit supported. */
829	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
830	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
831	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
832	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
833	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
834	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
835	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
836	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
837	* VMCB.TLB_Control is supported. */
838	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
839	/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
840	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
841	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
842	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
843	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
844	* intercept filter cycle count threshold. */
845	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
846	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
847	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
848	/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
849	#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
850	/** Bit 16 - VGIF - Supports virtualized GIF. */
851	#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
852	/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
853	#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
854
855	/** @} */
856
857
858	/** @name CR0
859	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
860	* reserved flags.
861	* @{ */
862	/** Bit 0 - PE - Protection Enabled */
863	#define X86_CR0_PE RT_BIT_32(0)
864	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
865	/** Bit 1 - MP - Monitor Coprocessor */
866	#define X86_CR0_MP RT_BIT_32(1)
867	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
868	/** Bit 2 - EM - Emulation. */
869	#define X86_CR0_EM RT_BIT_32(2)
870	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
871	/** Bit 3 - TS - Task Switch. */
872	#define X86_CR0_TS RT_BIT_32(3)
873	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
874	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
875	#define X86_CR0_ET RT_BIT_32(4)
876	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
877	/** Bit 5 - NE - Numeric error (486+). */
878	#define X86_CR0_NE RT_BIT_32(5)
879	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
880	/** Bit 16 - WP - Write Protect (486+). */
881	#define X86_CR0_WP RT_BIT_32(16)
882	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
883	/** Bit 18 - AM - Alignment Mask (486+). */
884	#define X86_CR0_AM RT_BIT_32(18)
885	#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
886	/** Bit 29 - NW - Not Write-though (486+). */
887	#define X86_CR0_NW RT_BIT_32(29)
888	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
889	/** Bit 30 - WP - Cache Disable (486+). */
890	#define X86_CR0_CD RT_BIT_32(30)
891	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
892	/** Bit 31 - PG - Paging. */
893	#define X86_CR0_PG RT_BIT_32(31)
894	#define X86_CR0_PAGING RT_BIT_32(31)
895	#define X86_CR0_BIT_PG 31 /*< Bit number of X86_CR0_PG /
896	/** @} */
897
898
899	/** @name CR3
900	* @{ */
901	/** Bit 3 - PWT - Page-level Writes Transparent. */
902	#define X86_CR3_PWT RT_BIT_32(3)
903	/** Bit 4 - PCD - Page-level Cache Disable. */
904	#define X86_CR3_PCD RT_BIT_32(4)
905	/** Bits 12-31 - - Page directory page number. */
906	#define X86_CR3_PAGE_MASK (0xfffff000)
907	/** Bits 5-31 - - PAE Page directory page number. */
908	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
909	/** Bits 12-51 - - AMD64 Page directory page number. */
910	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
911	/** @} */
912
913
914	/** @name CR4
915	* @{ */
916	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
917	#define X86_CR4_VME RT_BIT_32(0)
918	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
919	#define X86_CR4_PVI RT_BIT_32(1)
920	/** Bit 2 - TSD - Time Stamp Disable. */
921	#define X86_CR4_TSD RT_BIT_32(2)
922	/** Bit 3 - DE - Debugging Extensions. */
923	#define X86_CR4_DE RT_BIT_32(3)
924	/** Bit 4 - PSE - Page Size Extension. */
925	#define X86_CR4_PSE RT_BIT_32(4)
926	/** Bit 5 - PAE - Physical Address Extension. */
927	#define X86_CR4_PAE RT_BIT_32(5)
928	/** Bit 6 - MCE - Machine-Check Enable. */
929	#define X86_CR4_MCE RT_BIT_32(6)
930	/** Bit 7 - PGE - Page Global Enable. */
931	#define X86_CR4_PGE RT_BIT_32(7)
932	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
933	#define X86_CR4_PCE RT_BIT_32(8)
934	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
935	#define X86_CR4_OSFXSR RT_BIT_32(9)
936	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
937	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
938	/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
939	#define X86_CR4_UMIP RT_BIT_32(11)
940	/** Bit 13 - VMXE - VMX mode is enabled. */
941	#define X86_CR4_VMXE RT_BIT_32(13)
942	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
943	#define X86_CR4_SMXE RT_BIT_32(14)
944	/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
945	#define X86_CR4_FSGSBASE RT_BIT_32(16)
946	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
947	#define X86_CR4_PCIDE RT_BIT_32(17)
948	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
949	* extended states. */
950	#define X86_CR4_OSXSAVE RT_BIT_32(18)
951	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
952	#define X86_CR4_SMEP RT_BIT_32(20)
953	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
954	#define X86_CR4_SMAP RT_BIT_32(21)
955	/** Bit 22 - PKE - Protection Key Enable. */
956	#define X86_CR4_PKE RT_BIT_32(22)
957	/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
958	#define X86_CR4_CET RT_BIT_32(23)
959	/** @} */
960
961
962	/** @name DR6
963	* @{ */
964	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
965	#define X86_DR6_B0 RT_BIT_32(0)
966	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
967	#define X86_DR6_B1 RT_BIT_32(1)
968	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
969	#define X86_DR6_B2 RT_BIT_32(2)
970	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
971	#define X86_DR6_B3 RT_BIT_32(3)
972	/** Mask of all the Bx bits. */
973	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
974	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
975	#define X86_DR6_BD RT_BIT_32(13)
976	/** Bit 14 - BS - Single step */
977	#define X86_DR6_BS RT_BIT_32(14)
978	/** Bit 15 - BT - Task switch. (TSS T bit.) */
979	#define X86_DR6_BT RT_BIT_32(15)
980	/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
981	#define X86_DR6_RTM RT_BIT_32(16)
982	/** Value of DR6 after powerup/reset. */
983	#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
984	/** Bits which must be 1s in DR6. */
985	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
986	/** Bits which must be 1s in DR6, when RTM is supported. */
987	#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
988	/** Bits which must be 0s in DR6. */
989	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
990	/** Bits which must be 0s on writes to DR6. */
991	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
992	/** @} */
993
994	/** Get the DR6.Bx bit for a the given breakpoint. */
995	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
996
997
998	/** @name DR7
999	* @{ */
1000	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
1001	#define X86_DR7_L0 RT_BIT_32(0)
1002	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
1003	#define X86_DR7_G0 RT_BIT_32(1)
1004	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
1005	#define X86_DR7_L1 RT_BIT_32(2)
1006	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
1007	#define X86_DR7_G1 RT_BIT_32(3)
1008	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
1009	#define X86_DR7_L2 RT_BIT_32(4)
1010	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
1011	#define X86_DR7_G2 RT_BIT_32(5)
1012	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
1013	#define X86_DR7_L3 RT_BIT_32(6)
1014	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
1015	#define X86_DR7_G3 RT_BIT_32(7)
1016	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1017	#define X86_DR7_LE RT_BIT_32(8)
1018	/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1019	#define X86_DR7_GE RT_BIT_32(9)
1020
1021	/** L0, L1, L2, and L3. */
1022	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1023	/** L0, L1, L2, and L3. */
1024	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1025
1026	/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1027	* Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1028	#define X86_DR7_RTM RT_BIT_32(11)
1029	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1030	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1031	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1032	* instruction is executed.
1033	* @see http://www.rcollins.org/secrets/DR7.html */
1034	#define X86_DR7_ICE_IR RT_BIT_32(12)
1035	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1036	* any DR register is accessed. */
1037	#define X86_DR7_GD RT_BIT_32(13)
1038	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1039	* Pentium. */
1040	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1041	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1042	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1043	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
1044	#define X86_DR7_RW0_MASK (3 << 16)
1045	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
1046	#define X86_DR7_LEN0_MASK (3 << 18)
1047	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
1048	#define X86_DR7_RW1_MASK (3 << 20)
1049	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
1050	#define X86_DR7_LEN1_MASK (3 << 22)
1051	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
1052	#define X86_DR7_RW2_MASK (3 << 24)
1053	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
1054	#define X86_DR7_LEN2_MASK (3 << 26)
1055	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
1056	#define X86_DR7_RW3_MASK (3 << 28)
1057	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
1058	#define X86_DR7_LEN3_MASK (3 << 30)
1059
1060	/** Bits which reads as 1s. */
1061	#define X86_DR7_RA1_MASK RT_BIT_32(10)
1062	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1063	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1064	/** Bits which must be 0s when writing to DR7. */
1065	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1066
1067	/** Calcs the L bit of Nth breakpoint.
1068	* @param iBp The breakpoint number [0..3].
1069	*/
1070	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1071
1072	/** Calcs the G bit of Nth breakpoint.
1073	* @param iBp The breakpoint number [0..3].
1074	*/
1075	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1076
1077	/** Calcs the L and G bits of Nth breakpoint.
1078	* @param iBp The breakpoint number [0..3].
1079	*/
1080	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1081
1082	/** @name Read/Write values.
1083	* @{ */
1084	/** Break on instruction fetch only. */
1085	#define X86_DR7_RW_EO UINT32_C(0)
1086	/** Break on write only. */
1087	#define X86_DR7_RW_WO UINT32_C(1)
1088	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1089	#define X86_DR7_RW_IO UINT32_C(2)
1090	/** Break on read or write (but not instruction fetches). */
1091	#define X86_DR7_RW_RW UINT32_C(3)
1092	/** @} */
1093
1094	/** Shifts a X86_DR7_RW_* value to its right place.
1095	* @param iBp The breakpoint number [0..3].
1096	* @param fRw One of the X86_DR7_RW_* value.
1097	*/
1098	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1099
1100	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1101	* one of the X86_DR7_RW_XXX constants).
1102	*
1103	* @returns X86_DR7_RW_XXX
1104	* @param uDR7 DR7 value
1105	* @param iBp The breakpoint number [0..3].
1106	*/
1107	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1108
1109	/** R/W0, R/W1, R/W2, and R/W3. */
1110	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1111
1112	#ifndef VBOX_FOR_DTRACE_LIB
1113	/** Checks if there are any I/O breakpoint types configured in the RW
1114	* registers. Does NOT check if these are enabled, sorry. */
1115	# define X86_DR7_ANY_RW_IO(uDR7) \
1116	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1117	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1118	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1119	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1120	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1121	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1122	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1123	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1124	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1125	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1126	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1127	#endif /* !VBOX_FOR_DTRACE_LIB */
1128
1129	/** @name Length values.
1130	* @{ */
1131	#define X86_DR7_LEN_BYTE UINT32_C(0)
1132	#define X86_DR7_LEN_WORD UINT32_C(1)
1133	#define X86_DR7_LEN_QWORD UINT32_C(2) /*< AMD64 long mode only. /
1134	#define X86_DR7_LEN_DWORD UINT32_C(3)
1135	/** @} */
1136
1137	/** Shifts a X86_DR7_LEN_* value to its right place.
1138	* @param iBp The breakpoint number [0..3].
1139	* @param cb One of the X86_DR7_LEN_* values.
1140	*/
1141	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1142
1143	/** Fetch the breakpoint length bits from the DR7 value.
1144	* @param uDR7 DR7 value
1145	* @param iBp The breakpoint number [0..3].
1146	*/
1147	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1148
1149	/** Mask used to check if any breakpoints are enabled. */
1150	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1151
1152	/** LEN0, LEN1, LEN2, and LEN3. */
1153	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1154	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1155	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1156
1157	/** Value of DR7 after powerup/reset. */
1158	#define X86_DR7_INIT_VAL 0x400
1159	/** @} */
1160
1161
1162	/** @name Machine Specific Registers
1163	* @{
1164	*/
1165	/** Machine check address register (P5). */
1166	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1167	/** Machine check type register (P5). */
1168	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1169	/** Time Stamp Counter. */
1170	#define MSR_IA32_TSC 0x10
1171	#define MSR_IA32_CESR UINT32_C(0x00000011)
1172	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1173	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1174
1175	#define MSR_IA32_PLATFORM_ID 0x17
1176
1177	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1178	# define MSR_IA32_APICBASE 0x1b
1179	/** Local APIC enabled. */
1180	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1181	/** X2APIC enabled (requires the EN bit to be set). */
1182	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1183	/** The processor is the boot strap processor (BSP). */
1184	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1185	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1186	* width. */
1187	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1188	/** The default physical base address of the APIC. */
1189	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1190	/** Gets the physical base address from the MSR. */
1191	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1192	#endif
1193
1194	/** Undocumented intel MSR for reporting thread and core counts.
1195	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1196	* first 16 bits is the thread count. The next 16 bits the core count, except
1197	* on Westmere where it seems it's only the next 4 bits for some reason. */
1198	#define MSR_CORE_THREAD_COUNT 0x35
1199
1200	/** CPU Feature control. */
1201	#define MSR_IA32_FEATURE_CONTROL 0x3A
1202	/** Feature control - Lock MSR from writes (R/W0). */
1203	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1204	/** Feature control - Enable VMX inside SMX operation (R/WL). */
1205	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1206	/** Feature control - Enable VMX outside SMX operation (R/WL). */
1207	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1208	/** Feature control - SENTER local functions enable (R/WL). */
1209	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1210	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1211	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1212	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1213	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1214	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1215	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1216	/** Feature control - SENTER global enable (R/WL). */
1217	#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1218	/** Feature control - SGX launch control enable (R/WL). */
1219	#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1220	/** Feature control - SGX global enable (R/WL). */
1221	#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1222	/** Feature control - LMCE on (R/WL). */
1223	#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1224
1225	/** Per-processor TSC adjust MSR. */
1226	#define MSR_IA32_TSC_ADJUST 0x3B
1227
1228	/** Spectre control register.
1229	* Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1230	#define MSR_IA32_SPEC_CTRL 0x48
1231	/** IBRS - Indirect branch restricted speculation. */
1232	#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1233	/** STIBP - Single thread indirect branch predictors. */
1234	#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1235	/** SSBD - Speculative Store Bypass Disable. */
1236	#define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2)
1237
1238	/** Prediction command register.
1239	* Write only, logical processor scope, no state since write only. */
1240	#define MSR_IA32_PRED_CMD 0x49
1241	/** IBPB - Indirect branch prediction barrie when written as 1. */
1242	#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1243
1244	/** BIOS update trigger (microcode update). */
1245	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1246
1247	/** BIOS update signature (microcode). */
1248	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1249
1250	/** SMM monitor control. */
1251	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1252	/** SMM control - Valid. */
1253	#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1254	/** SMM control - VMXOFF unblocks SMI. */
1255	#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1256	/** SMM control - MSEG base physical address. */
1257	#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1258
1259	/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1260	#define MSR_IA32_SMBASE 0x9E
1261
1262	/** General performance counter no. 0. */
1263	#define MSR_IA32_PMC0 0xC1
1264	/** General performance counter no. 1. */
1265	#define MSR_IA32_PMC1 0xC2
1266	/** General performance counter no. 2. */
1267	#define MSR_IA32_PMC2 0xC3
1268	/** General performance counter no. 3. */
1269	#define MSR_IA32_PMC3 0xC4
1270	/** General performance counter no. 4. */
1271	#define MSR_IA32_PMC4 0xC5
1272	/** General performance counter no. 5. */
1273	#define MSR_IA32_PMC5 0xC6
1274	/** General performance counter no. 6. */
1275	#define MSR_IA32_PMC6 0xC7
1276	/** General performance counter no. 7. */
1277	#define MSR_IA32_PMC7 0xC8
1278
1279	/** Nehalem power control. */
1280	#define MSR_IA32_PLATFORM_INFO 0xCE
1281
1282	/** Get FSB clock status (Intel-specific). */
1283	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1284
1285	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1286	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1287
1288	/** C0 Maximum Frequency Clock Count */
1289	#define MSR_IA32_MPERF 0xE7
1290	/** C0 Actual Frequency Clock Count */
1291	#define MSR_IA32_APERF 0xE8
1292
1293	/** MTRR Capabilities. */
1294	#define MSR_IA32_MTRR_CAP 0xFE
1295
1296	/** Architecture capabilities (bugfixes). */
1297	#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1298	/** CPU is no subject to meltdown problems. */
1299	#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1300	/** CPU has better IBRS and you can leave it on all the time. */
1301	#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1302	/** CPU has return stack buffer (RSB) override. */
1303	#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1304	/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1305	* This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1306	#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1307	/** CPU does not suffer from MDS issues. */
1308	#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
1309
1310	/** Flush command register. */
1311	#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1312	/** Flush the level 1 data cache when this bit is written. */
1313	#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1314
1315	/** Cache control/info. */
1316	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1317
1318	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1319	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1320	* R0 SS == CS + 8
1321	* R3 CS == CS + 16
1322	* R3 SS == CS + 24
1323	*/
1324	#define MSR_IA32_SYSENTER_CS 0x174
1325	/** SYSENTER_ESP - the R0 ESP. */
1326	#define MSR_IA32_SYSENTER_ESP 0x175
1327	/** SYSENTER_EIP - the R0 EIP. */
1328	#define MSR_IA32_SYSENTER_EIP 0x176
1329	#endif
1330
1331	/** Machine Check Global Capabilities Register. */
1332	#define MSR_IA32_MCG_CAP 0x179
1333	/** Machine Check Global Status Register. */
1334	#define MSR_IA32_MCG_STATUS 0x17A
1335	/** Machine Check Global Control Register. */
1336	#define MSR_IA32_MCG_CTRL 0x17B
1337
1338	/** Page Attribute Table. */
1339	#define MSR_IA32_CR_PAT 0x277
1340	/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1341	* "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1342	#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1343
1344	/** Performance event select MSRs. (Intel only) */
1345	#define MSR_IA32_PERFEVTSEL0 0x186
1346	#define MSR_IA32_PERFEVTSEL1 0x187
1347	#define MSR_IA32_PERFEVTSEL2 0x188
1348	#define MSR_IA32_PERFEVTSEL3 0x189
1349
1350	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1351	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1352	* holds a ratio that Apple takes for TSC granularity.
1353	*
1354	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1355	#define MSR_FLEX_RATIO 0x194
1356	/** Performance state value and starting with Intel core more.
1357	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1358	#define MSR_IA32_PERF_STATUS 0x198
1359	#define MSR_IA32_PERF_CTL 0x199
1360	#define MSR_IA32_THERM_STATUS 0x19c
1361
1362	/** Offcore response event select registers. */
1363	#define MSR_OFFCORE_RSP_0 0x1a6
1364	#define MSR_OFFCORE_RSP_1 0x1a7
1365
1366	/** Enable misc. processor features (R/W). */
1367	#define MSR_IA32_MISC_ENABLE 0x1A0
1368	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1369	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1370	/** Automatic Thermal Control Circuit Enable (R/W). */
1371	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1372	/** Performance Monitoring Available (R). */
1373	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1374	/** Branch Trace Storage Unavailable (R/O). */
1375	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1376	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1377	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1378	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1379	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1380	/** If MONITOR/MWAIT is supported (R/W). */
1381	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1382	/** Limit CPUID Maxval to 3 leafs (R/W). */
1383	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1384	/** When set to 1, xTPR messages are disabled (R/W). */
1385	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1386	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1387	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1388
1389	/** Trace/Profile Resource Control (R/W) */
1390	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1391	/** Last branch record. */
1392	#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1393	/** Branch trace flag (single step on branches). */
1394	#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1395	/** Performance monitoring pin control (AMD only). */
1396	#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1397	#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1398	#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1399	#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1400	/** Trace message enable (Intel only). */
1401	#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1402	/** Branch trace store (Intel only). */
1403	#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1404	/** Branch trace interrupt (Intel only). */
1405	#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1406	/** Branch trace off in privileged code (Intel only). */
1407	#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1408	/** Branch trace off in user code (Intel only). */
1409	#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1410	/** Freeze LBR on PMI flag (Intel only). */
1411	#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1412	/** Freeze PERFMON on PMI flag (Intel only). */
1413	#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1414	/** Freeze while SMM enabled (Intel only). */
1415	#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1416	/** Advanced debugging of RTM regions (Intel only). */
1417	#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1418	/** Debug control MSR valid bits (Intel only). */
1419	#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR \| MSR_IA32_DEBUGCTL_BTF \| MSR_IA32_DEBUGCTL_TR \
1420	\| MSR_IA32_DEBUGCTL_BTS \| MSR_IA32_DEBUGCTL_BTINT \| MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1421	\| MSR_IA32_DEBUGCTL_BTS_OFF_USER \| MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1422	\| MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI \| MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1423	\| MSR_IA32_DEBUGCTL_RTM)
1424
1425	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1426	* @{ */
1427	#define MSR_P4_LASTBRANCH_0 0x1db
1428	#define MSR_P4_LASTBRANCH_1 0x1dc
1429	#define MSR_P4_LASTBRANCH_2 0x1dd
1430	#define MSR_P4_LASTBRANCH_3 0x1de
1431
1432	/** LBR Top-of-stack MSR (index to most recent record). */
1433	#define MSR_P4_LASTBRANCH_TOS 0x1da
1434	/** @} */
1435
1436	/** @name Last branch registers for Core 2 and related Xeons.
1437	* @{ */
1438	#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
1439	#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
1440	#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
1441	#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
1442
1443	#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
1444	#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
1445	#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
1446	#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
1447
1448	/** LBR Top-of-stack MSR (index to most recent record). */
1449	#define MSR_CORE2_LASTBRANCH_TOS 0x1c9
1450	/** @} */
1451
1452	/** @name Last branch registers.
1453	* @{ */
1454	#define MSR_LASTBRANCH_0_FROM_IP 0x680
1455	#define MSR_LASTBRANCH_1_FROM_IP 0x681
1456	#define MSR_LASTBRANCH_2_FROM_IP 0x682
1457	#define MSR_LASTBRANCH_3_FROM_IP 0x683
1458	#define MSR_LASTBRANCH_4_FROM_IP 0x684
1459	#define MSR_LASTBRANCH_5_FROM_IP 0x685
1460	#define MSR_LASTBRANCH_6_FROM_IP 0x686
1461	#define MSR_LASTBRANCH_7_FROM_IP 0x687
1462	#define MSR_LASTBRANCH_8_FROM_IP 0x688
1463	#define MSR_LASTBRANCH_9_FROM_IP 0x689
1464	#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1465	#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1466	#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1467	#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1468	#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1469	#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1470	#define MSR_LASTBRANCH_16_FROM_IP 0x690
1471	#define MSR_LASTBRANCH_17_FROM_IP 0x691
1472	#define MSR_LASTBRANCH_18_FROM_IP 0x692
1473	#define MSR_LASTBRANCH_19_FROM_IP 0x693
1474	#define MSR_LASTBRANCH_20_FROM_IP 0x694
1475	#define MSR_LASTBRANCH_21_FROM_IP 0x695
1476	#define MSR_LASTBRANCH_22_FROM_IP 0x696
1477	#define MSR_LASTBRANCH_23_FROM_IP 0x697
1478	#define MSR_LASTBRANCH_24_FROM_IP 0x698
1479	#define MSR_LASTBRANCH_25_FROM_IP 0x699
1480	#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1481	#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1482	#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1483	#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1484	#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1485	#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1486
1487	#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1488	#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1489	#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1490	#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1491	#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1492	#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1493	#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1494	#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1495	#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1496	#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1497	#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1498	#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1499	#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1500	#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1501	#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1502	#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1503	#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1504	#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1505	#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1506	#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1507	#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1508	#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1509	#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1510	#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1511	#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1512	#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1513	#define MSR_LASTBRANCH_26_TO_IP 0x6da
1514	#define MSR_LASTBRANCH_27_TO_IP 0x6db
1515	#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1516	#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1517	#define MSR_LASTBRANCH_30_TO_IP 0x6de
1518	#define MSR_LASTBRANCH_31_TO_IP 0x6df
1519
1520	/** LBR Top-of-stack MSR (index to most recent record). */
1521	#define MSR_LASTBRANCH_TOS 0x1c9
1522	/** @} */
1523
1524	/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
1525	#define MSR_IA32_TSX_CTRL 0x122
1526
1527	/** Variable range MTRRs.
1528	* @{ */
1529	#define MSR_IA32_MTRR_PHYSBASE0 0x200
1530	#define MSR_IA32_MTRR_PHYSMASK0 0x201
1531	#define MSR_IA32_MTRR_PHYSBASE1 0x202
1532	#define MSR_IA32_MTRR_PHYSMASK1 0x203
1533	#define MSR_IA32_MTRR_PHYSBASE2 0x204
1534	#define MSR_IA32_MTRR_PHYSMASK2 0x205
1535	#define MSR_IA32_MTRR_PHYSBASE3 0x206
1536	#define MSR_IA32_MTRR_PHYSMASK3 0x207
1537	#define MSR_IA32_MTRR_PHYSBASE4 0x208
1538	#define MSR_IA32_MTRR_PHYSMASK4 0x209
1539	#define MSR_IA32_MTRR_PHYSBASE5 0x20a
1540	#define MSR_IA32_MTRR_PHYSMASK5 0x20b
1541	#define MSR_IA32_MTRR_PHYSBASE6 0x20c
1542	#define MSR_IA32_MTRR_PHYSMASK6 0x20d
1543	#define MSR_IA32_MTRR_PHYSBASE7 0x20e
1544	#define MSR_IA32_MTRR_PHYSMASK7 0x20f
1545	#define MSR_IA32_MTRR_PHYSBASE8 0x210
1546	#define MSR_IA32_MTRR_PHYSMASK8 0x211
1547	#define MSR_IA32_MTRR_PHYSBASE9 0x212
1548	#define MSR_IA32_MTRR_PHYSMASK9 0x213
1549	/** @} */
1550
1551	/** Fixed range MTRRs.
1552	* @{ */
1553	#define MSR_IA32_MTRR_FIX64K_00000 0x250
1554	#define MSR_IA32_MTRR_FIX16K_80000 0x258
1555	#define MSR_IA32_MTRR_FIX16K_A0000 0x259
1556	#define MSR_IA32_MTRR_FIX4K_C0000 0x268
1557	#define MSR_IA32_MTRR_FIX4K_C8000 0x269
1558	#define MSR_IA32_MTRR_FIX4K_D0000 0x26a
1559	#define MSR_IA32_MTRR_FIX4K_D8000 0x26b
1560	#define MSR_IA32_MTRR_FIX4K_E0000 0x26c
1561	#define MSR_IA32_MTRR_FIX4K_E8000 0x26d
1562	#define MSR_IA32_MTRR_FIX4K_F0000 0x26e
1563	#define MSR_IA32_MTRR_FIX4K_F8000 0x26f
1564	/** @} */
1565
1566	/** MTRR Default Range. */
1567	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1568
1569	/** Global performance counter control facilities (Intel only). */
1570	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1571	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1572	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1573
1574	/** Precise Event Based sampling (Intel only). */
1575	#define MSR_IA32_PEBS_ENABLE 0x3F1
1576
1577	#define MSR_IA32_MC0_CTL 0x400
1578	#define MSR_IA32_MC0_STATUS 0x401
1579
1580	/** Basic VMX information. */
1581	#define MSR_IA32_VMX_BASIC 0x480
1582	/** Allowed settings for pin-based VM execution controls. */
1583	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1584	/** Allowed settings for proc-based VM execution controls. */
1585	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1586	/** Allowed settings for the VM-exit controls. */
1587	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1588	/** Allowed settings for the VM-entry controls. */
1589	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1590	/** Misc VMX info. */
1591	#define MSR_IA32_VMX_MISC 0x485
1592	/** Fixed cleared bits in CR0. */
1593	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1594	/** Fixed set bits in CR0. */
1595	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1596	/** Fixed cleared bits in CR4. */
1597	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1598	/** Fixed set bits in CR4. */
1599	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1600	/** Information for enumerating fields in the VMCS. */
1601	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1602	/** Allowed settings for secondary proc-based VM execution controls */
1603	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1604	/** EPT capabilities. */
1605	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1606	/** Allowed settings of all pin-based VM execution controls. */
1607	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1608	/** Allowed settings of all proc-based VM execution controls. */
1609	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1610	/** Allowed settings of all VMX exit controls. */
1611	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1612	/** Allowed settings of all VMX entry controls. */
1613	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1614	/** Allowed settings for the VM-function controls. */
1615	#define MSR_IA32_VMX_VMFUNC 0x491
1616
1617	/** Intel PT - Enable and control for trace packet generation. */
1618	#define MSR_IA32_RTIT_CTL 0x570
1619
1620	/** DS Save Area (R/W). */
1621	#define MSR_IA32_DS_AREA 0x600
1622	/** Running Average Power Limit (RAPL) power units. */
1623	#define MSR_RAPL_POWER_UNIT 0x606
1624	/** Package C3 Interrupt Response Limit. */
1625	#define MSR_PKGC3_IRTL 0x60a
1626	/** Package C6/C7S Interrupt Response Limit 1. */
1627	#define MSR_PKGC_IRTL1 0x60b
1628	/** Package C6/C7S Interrupt Response Limit 2. */
1629	#define MSR_PKGC_IRTL2 0x60c
1630	/** Package C2 Residency Counter. */
1631	#define MSR_PKG_C2_RESIDENCY 0x60d
1632	/** PKG RAPL Power Limit Control. */
1633	#define MSR_PKG_POWER_LIMIT 0x610
1634	/** PKG Energy Status. */
1635	#define MSR_PKG_ENERGY_STATUS 0x611
1636	/** PKG Perf Status. */
1637	#define MSR_PKG_PERF_STATUS 0x613
1638	/** PKG RAPL Parameters. */
1639	#define MSR_PKG_POWER_INFO 0x614
1640	/** DRAM RAPL Power Limit Control. */
1641	#define MSR_DRAM_POWER_LIMIT 0x618
1642	/** DRAM Energy Status. */
1643	#define MSR_DRAM_ENERGY_STATUS 0x619
1644	/** DRAM Performance Throttling Status. */
1645	#define MSR_DRAM_PERF_STATUS 0x61b
1646	/** DRAM RAPL Parameters. */
1647	#define MSR_DRAM_POWER_INFO 0x61c
1648	/** Package C10 Residency Counter. */
1649	#define MSR_PKG_C10_RESIDENCY 0x632
1650	/** PP0 Energy Status. */
1651	#define MSR_PP0_ENERGY_STATUS 0x639
1652	/** PP1 Energy Status. */
1653	#define MSR_PP1_ENERGY_STATUS 0x641
1654	/** Turbo Activation Ratio. */
1655	#define MSR_TURBO_ACTIVATION_RATIO 0x64c
1656	/** Core Performance Limit Reasons. */
1657	#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
1658
1659	/** X2APIC MSR range start. */
1660	#define MSR_IA32_X2APIC_START 0x800
1661	/** X2APIC MSR - APIC ID Register. */
1662	#define MSR_IA32_X2APIC_ID 0x802
1663	/** X2APIC MSR - APIC Version Register. */
1664	#define MSR_IA32_X2APIC_VERSION 0x803
1665	/** X2APIC MSR - Task Priority Register. */
1666	#define MSR_IA32_X2APIC_TPR 0x808
1667	/** X2APIC MSR - Processor Priority register. */
1668	#define MSR_IA32_X2APIC_PPR 0x80A
1669	/** X2APIC MSR - End Of Interrupt register. */
1670	#define MSR_IA32_X2APIC_EOI 0x80B
1671	/** X2APIC MSR - Logical Destination Register. */
1672	#define MSR_IA32_X2APIC_LDR 0x80D
1673	/** X2APIC MSR - Spurious Interrupt Vector Register. */
1674	#define MSR_IA32_X2APIC_SVR 0x80F
1675	/** X2APIC MSR - In-service Register (bits 31:0). */
1676	#define MSR_IA32_X2APIC_ISR0 0x810
1677	/** X2APIC MSR - In-service Register (bits 63:32). */
1678	#define MSR_IA32_X2APIC_ISR1 0x811
1679	/** X2APIC MSR - In-service Register (bits 95:64). */
1680	#define MSR_IA32_X2APIC_ISR2 0x812
1681	/** X2APIC MSR - In-service Register (bits 127:96). */
1682	#define MSR_IA32_X2APIC_ISR3 0x813
1683	/** X2APIC MSR - In-service Register (bits 159:128). */
1684	#define MSR_IA32_X2APIC_ISR4 0x814
1685	/** X2APIC MSR - In-service Register (bits 191:160). */
1686	#define MSR_IA32_X2APIC_ISR5 0x815
1687	/** X2APIC MSR - In-service Register (bits 223:192). */
1688	#define MSR_IA32_X2APIC_ISR6 0x816
1689	/** X2APIC MSR - In-service Register (bits 255:224). */
1690	#define MSR_IA32_X2APIC_ISR7 0x817
1691	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1692	#define MSR_IA32_X2APIC_TMR0 0x818
1693	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1694	#define MSR_IA32_X2APIC_TMR1 0x819
1695	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1696	#define MSR_IA32_X2APIC_TMR2 0x81A
1697	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1698	#define MSR_IA32_X2APIC_TMR3 0x81B
1699	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1700	#define MSR_IA32_X2APIC_TMR4 0x81C
1701	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1702	#define MSR_IA32_X2APIC_TMR5 0x81D
1703	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1704	#define MSR_IA32_X2APIC_TMR6 0x81E
1705	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1706	#define MSR_IA32_X2APIC_TMR7 0x81F
1707	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1708	#define MSR_IA32_X2APIC_IRR0 0x820
1709	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1710	#define MSR_IA32_X2APIC_IRR1 0x821
1711	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1712	#define MSR_IA32_X2APIC_IRR2 0x822
1713	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1714	#define MSR_IA32_X2APIC_IRR3 0x823
1715	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1716	#define MSR_IA32_X2APIC_IRR4 0x824
1717	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1718	#define MSR_IA32_X2APIC_IRR5 0x825
1719	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1720	#define MSR_IA32_X2APIC_IRR6 0x826
1721	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1722	#define MSR_IA32_X2APIC_IRR7 0x827
1723	/** X2APIC MSR - Error Status Register. */
1724	#define MSR_IA32_X2APIC_ESR 0x828
1725	/** X2APIC MSR - LVT CMCI Register. */
1726	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1727	/** X2APIC MSR - Interrupt Command Register. */
1728	#define MSR_IA32_X2APIC_ICR 0x830
1729	/** X2APIC MSR - LVT Timer Register. */
1730	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1731	/** X2APIC MSR - LVT Thermal Sensor Register. */
1732	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1733	/** X2APIC MSR - LVT Performance Counter Register. */
1734	#define MSR_IA32_X2APIC_LVT_PERF 0x834
1735	/** X2APIC MSR - LVT LINT0 Register. */
1736	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1737	/** X2APIC MSR - LVT LINT1 Register. */
1738	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1739	/** X2APIC MSR - LVT Error Register . */
1740	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1741	/** X2APIC MSR - Timer Initial Count Register. */
1742	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1743	/** X2APIC MSR - Timer Current Count Register. */
1744	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1745	/** X2APIC MSR - Timer Divide Configuration Register. */
1746	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1747	/** X2APIC MSR - Self IPI. */
1748	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1749	/** X2APIC MSR range end. */
1750	#define MSR_IA32_X2APIC_END 0x8FF
1751	/** X2APIC MSR - LVT start range. */
1752	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1753	/** X2APIC MSR - LVT end range (inclusive). */
1754	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1755
1756	/** K6 EFER - Extended Feature Enable Register. */
1757	#define MSR_K6_EFER UINT32_C(0xc0000080)
1758	/** @todo document EFER */
1759	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1760	#define MSR_K6_EFER_SCE RT_BIT_32(0)
1761	/** Bit 8 - LME - Long mode enabled. (R/W) */
1762	#define MSR_K6_EFER_LME RT_BIT_32(8)
1763	#define MSR_K6_EFER_BIT_LME 8 /*< Bit number of MSR_K6_EFER_LME /
1764	/** Bit 10 - LMA - Long mode active. (R) */
1765	#define MSR_K6_EFER_LMA RT_BIT_32(10)
1766	#define MSR_K6_EFER_BIT_LMA 10 /*< Bit number of MSR_K6_EFER_LMA /
1767	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1768	#define MSR_K6_EFER_NXE RT_BIT_32(11)
1769	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
1770	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1771	#define MSR_K6_EFER_SVME RT_BIT_32(12)
1772	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1773	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1774	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1775	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1776	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1777	#define MSR_K6_EFER_TCE RT_BIT_32(15)
1778	/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
1779	#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
1780
1781	/** K6 STAR - SYSCALL/RET targets. */
1782	#define MSR_K6_STAR UINT32_C(0xc0000081)
1783	/** Shift value for getting the SYSRET CS and SS value. */
1784	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1785	/** Shift value for getting the SYSCALL CS and SS value. */
1786	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1787	/** Selector mask for use after shifting. */
1788	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1789	/** The mask which give the SYSCALL EIP. */
1790	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1791	/** K6 WHCR - Write Handling Control Register. */
1792	#define MSR_K6_WHCR UINT32_C(0xc0000082)
1793	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1794	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1795	/** K6 PSOR - Processor State Observability Register. */
1796	#define MSR_K6_PSOR UINT32_C(0xc0000087)
1797	/** K6 PFIR - Page Flush/Invalidate Register. */
1798	#define MSR_K6_PFIR UINT32_C(0xc0000088)
1799
1800	/** Performance counter MSRs. (AMD only) */
1801	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1802	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1803	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1804	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1805	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1806	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1807	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1808	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1809
1810	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1811	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1812	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1813	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1814	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1815	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1816	/** K8 FS.base - The 64-bit base FS register. */
1817	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1818	/** K8 GS.base - The 64-bit base GS register. */
1819	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1820	/** K8 KernelGSbase - Used with SWAPGS. */
1821	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1822	/** K8 TSC_AUX - Used with RDTSCP. */
1823	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1824	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1825	#define MSR_K8_HWCR UINT32_C(0xc0010015)
1826	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1827	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1828	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1829	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1830	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1831	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1832
1833	/** SMM MSRs. */
1834	#define MSR_K7_SMBASE UINT32_C(0xc0010111)
1835	#define MSR_K7_SMM_ADDR UINT32_C(0xc0010112)
1836	#define MSR_K7_SMM_MASK UINT32_C(0xc0010113)
1837
1838	/** North bridge config? See BIOS & Kernel dev guides for
1839	* details. */
1840	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1841
1842	/** Hypertransport interrupt pending register.
1843	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1844	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1845
1846	/** SVM Control. */
1847	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1848	/** Disables HDT (Hardware Debug Tool) and certain internal debug
1849	* features. */
1850	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1851	/** If set, non-intercepted INIT signals are converted to \#SX
1852	* exceptions. */
1853	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1854	/** Disables A20 masking. */
1855	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1856	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1857	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1858	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1859	* clear, EFER.SVME can be written normally. */
1860	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1861
1862	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1863	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1864	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1865	* host state during world switch. */
1866	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1867
1868	/** Virtualized speculation control for AMD processors.
1869	*
1870	* Unified interface among different CPU generations.
1871	* The VMM will set any architectural MSRs based on the CPU.
1872	* See "White Paper: AMD64 Technology Speculative Store Bypass Disable 5.21.18"
1873	* (12441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf) */
1874	#define MSR_AMD_VIRT_SPEC_CTL UINT32_C(0xc001011f)
1875	/** Speculative Store Bypass Disable. */
1876	# define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
1877
1878	/** @} */
1879
1880
1881	/** @name Page Table / Directory / Directory Pointers / L4.
1882	* @{
1883	*/
1884
1885	/** Page table/directory entry as an unsigned integer. */
1886	typedef uint32_t X86PGUINT;
1887	/** Pointer to a page table/directory table entry as an unsigned integer. */
1888	typedef X86PGUINT *PX86PGUINT;
1889	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1890	typedef X86PGUINT const *PCX86PGUINT;
1891
1892	/** Number of entries in a 32-bit PT/PD. */
1893	#define X86_PG_ENTRIES 1024
1894
1895
1896	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1897	typedef uint64_t X86PGPAEUINT;
1898	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1899	typedef X86PGPAEUINT *PX86PGPAEUINT;
1900	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1901	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1902
1903	/** Number of entries in a PAE PT/PD. */
1904	#define X86_PG_PAE_ENTRIES 512
1905	/** Number of entries in a PAE PDPT. */
1906	#define X86_PG_PAE_PDPE_ENTRIES 4
1907
1908	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1909	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1910	/** Number of entries in an AMD64 PDPT.
1911	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1912	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1913
1914	/** The size of a default page. */
1915	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1916	/** The page shift of a default page. */
1917	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1918	/** The default page offset mask. */
1919	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1920	/** The default page base mask for virtual addresses. */
1921	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1922	/** The default page base mask for virtual addresses - 32bit version. */
1923	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1924
1925	/** The size of a 4KB page. */
1926	#define X86_PAGE_4K_SIZE _4K
1927	/** The page shift of a 4KB page. */
1928	#define X86_PAGE_4K_SHIFT 12
1929	/** The 4KB page offset mask. */
1930	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1931	/** The 4KB page base mask for virtual addresses. */
1932	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1933	/** The 4KB page base mask for virtual addresses - 32bit version. */
1934	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1935
1936	/** The size of a 2MB page. */
1937	#define X86_PAGE_2M_SIZE _2M
1938	/** The page shift of a 2MB page. */
1939	#define X86_PAGE_2M_SHIFT 21
1940	/** The 2MB page offset mask. */
1941	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
1942	/** The 2MB page base mask for virtual addresses. */
1943	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
1944	/** The 2MB page base mask for virtual addresses - 32bit version. */
1945	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
1946
1947	/** The size of a 4MB page. */
1948	#define X86_PAGE_4M_SIZE _4M
1949	/** The page shift of a 4MB page. */
1950	#define X86_PAGE_4M_SHIFT 22
1951	/** The 4MB page offset mask. */
1952	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
1953	/** The 4MB page base mask for virtual addresses. */
1954	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
1955	/** The 4MB page base mask for virtual addresses - 32bit version. */
1956	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
1957
1958	/** The size of a 1GB page. */
1959	#define X86_PAGE_1G_SIZE _1G
1960	/** The page shift of a 1GB page. */
1961	#define X86_PAGE_1G_SHIFT 30
1962	/** The 1GB page offset mask. */
1963	#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
1964	/** The 1GB page base mask for virtual addresses. */
1965	#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
1966
1967	/**
1968	* Check if the given address is canonical.
1969	*/
1970	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
1971
1972	/**
1973	* Gets the page base mask given the page shift.
1974	*/
1975	#define X86_GET_PAGE_BASE_MASK(a_cShift) (UINT64_C(0xffffffffffffffff) << (a_cShift))
1976
1977	/**
1978	* Gets the page offset mask given the page shift.
1979	*/
1980	#define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
1981
1982
1983	/** @name Page Table Entry
1984	* @{
1985	*/
1986	/** Bit 0 - P - Present bit. */
1987	#define X86_PTE_BIT_P 0
1988	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
1989	#define X86_PTE_BIT_RW 1
1990	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
1991	#define X86_PTE_BIT_US 2
1992	/** Bit 3 - PWT - Page level write thru bit. */
1993	#define X86_PTE_BIT_PWT 3
1994	/** Bit 4 - PCD - Page level cache disable bit. */
1995	#define X86_PTE_BIT_PCD 4
1996	/** Bit 5 - A - Access bit. */
1997	#define X86_PTE_BIT_A 5
1998	/** Bit 6 - D - Dirty bit. */
1999	#define X86_PTE_BIT_D 6
2000	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2001	#define X86_PTE_BIT_PAT 7
2002	/** Bit 8 - G - Global flag. */
2003	#define X86_PTE_BIT_G 8
2004	/** Bits 63 - NX - PAE/LM - No execution flag. */
2005	#define X86_PTE_PAE_BIT_NX 63
2006
2007	/** Bit 0 - P - Present bit mask. */
2008	#define X86_PTE_P RT_BIT_32(0)
2009	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
2010	#define X86_PTE_RW RT_BIT_32(1)
2011	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
2012	#define X86_PTE_US RT_BIT_32(2)
2013	/** Bit 3 - PWT - Page level write thru bit mask. */
2014	#define X86_PTE_PWT RT_BIT_32(3)
2015	/** Bit 4 - PCD - Page level cache disable bit mask. */
2016	#define X86_PTE_PCD RT_BIT_32(4)
2017	/** Bit 5 - A - Access bit mask. */
2018	#define X86_PTE_A RT_BIT_32(5)
2019	/** Bit 6 - D - Dirty bit mask. */
2020	#define X86_PTE_D RT_BIT_32(6)
2021	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
2022	#define X86_PTE_PAT RT_BIT_32(7)
2023	/** Bit 8 - G - Global bit mask. */
2024	#define X86_PTE_G RT_BIT_32(8)
2025
2026	/** Bits 9-11 - - Available for use to system software. */
2027	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2028	/** Bits 12-31 - - Physical Page number of the next level. */
2029	#define X86_PTE_PG_MASK ( 0xfffff000 )
2030
2031	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2032	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2033	/** Bits 63 - NX - PAE/LM - No execution flag. */
2034	#define X86_PTE_PAE_NX RT_BIT_64(63)
2035	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
2036	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
2037	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
2038	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
2039	/** No bits - - LM - MBZ bits when NX is active. */
2040	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
2041	/** Bits 63 - - LM - MBZ bits when no NX. */
2042	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
2043
2044	/**
2045	* Page table entry.
2046	*/
2047	typedef struct X86PTEBITS
2048	{
2049	/** Flags whether(=1) or not the page is present. */
2050	uint32_t u1Present : 1;
2051	/** Read(=0) / Write(=1) flag. */
2052	uint32_t u1Write : 1;
2053	/** User(=1) / Supervisor (=0) flag. */
2054	uint32_t u1User : 1;
2055	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2056	uint32_t u1WriteThru : 1;
2057	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2058	uint32_t u1CacheDisable : 1;
2059	/** Accessed flag.
2060	* Indicates that the page have been read or written to. */
2061	uint32_t u1Accessed : 1;
2062	/** Dirty flag.
2063	* Indicates that the page has been written to. */
2064	uint32_t u1Dirty : 1;
2065	/** Reserved / If PAT enabled, bit 2 of the index. */
2066	uint32_t u1PAT : 1;
2067	/** Global flag. (Ignored in all but final level.) */
2068	uint32_t u1Global : 1;
2069	/** Available for use to system software. */
2070	uint32_t u3Available : 3;
2071	/** Physical Page number of the next level. */
2072	uint32_t u20PageNo : 20;
2073	} X86PTEBITS;
2074	#ifndef VBOX_FOR_DTRACE_LIB
2075	AssertCompileSize(X86PTEBITS, 4);
2076	#endif
2077	/** Pointer to a page table entry. */
2078	typedef X86PTEBITS *PX86PTEBITS;
2079	/** Pointer to a const page table entry. */
2080	typedef const X86PTEBITS *PCX86PTEBITS;
2081
2082	/**
2083	* Page table entry.
2084	*/
2085	typedef union X86PTE
2086	{
2087	/** Unsigned integer view */
2088	X86PGUINT u;
2089	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2090	/** Bit field view. */
2091	X86PTEBITS n;
2092	#endif
2093	/** 32-bit view. */
2094	uint32_t au32[1];
2095	/** 16-bit view. */
2096	uint16_t au16[2];
2097	/** 8-bit view. */
2098	uint8_t au8[4];
2099	} X86PTE;
2100	#ifndef VBOX_FOR_DTRACE_LIB
2101	AssertCompileSize(X86PTE, 4);
2102	#endif
2103	/** Pointer to a page table entry. */
2104	typedef X86PTE *PX86PTE;
2105	/** Pointer to a const page table entry. */
2106	typedef const X86PTE *PCX86PTE;
2107
2108
2109	/**
2110	* PAE page table entry.
2111	*/
2112	typedef struct X86PTEPAEBITS
2113	{
2114	/** Flags whether(=1) or not the page is present. */
2115	uint32_t u1Present : 1;
2116	/** Read(=0) / Write(=1) flag. */
2117	uint32_t u1Write : 1;
2118	/** User(=1) / Supervisor(=0) flag. */
2119	uint32_t u1User : 1;
2120	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2121	uint32_t u1WriteThru : 1;
2122	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2123	uint32_t u1CacheDisable : 1;
2124	/** Accessed flag.
2125	* Indicates that the page have been read or written to. */
2126	uint32_t u1Accessed : 1;
2127	/** Dirty flag.
2128	* Indicates that the page has been written to. */
2129	uint32_t u1Dirty : 1;
2130	/** Reserved / If PAT enabled, bit 2 of the index. */
2131	uint32_t u1PAT : 1;
2132	/** Global flag. (Ignored in all but final level.) */
2133	uint32_t u1Global : 1;
2134	/** Available for use to system software. */
2135	uint32_t u3Available : 3;
2136	/** Physical Page number of the next level - Low Part. Don't use this. */
2137	uint32_t u20PageNoLow : 20;
2138	/** Physical Page number of the next level - High Part. Don't use this. */
2139	uint32_t u20PageNoHigh : 20;
2140	/** MBZ bits */
2141	uint32_t u11Reserved : 11;
2142	/** No Execute flag. */
2143	uint32_t u1NoExecute : 1;
2144	} X86PTEPAEBITS;
2145	#ifndef VBOX_FOR_DTRACE_LIB
2146	AssertCompileSize(X86PTEPAEBITS, 8);
2147	#endif
2148	/** Pointer to a page table entry. */
2149	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2150	/** Pointer to a page table entry. */
2151	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2152
2153	/**
2154	* PAE Page table entry.
2155	*/
2156	typedef union X86PTEPAE
2157	{
2158	/** Unsigned integer view */
2159	X86PGPAEUINT u;
2160	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2161	/** Bit field view. */
2162	X86PTEPAEBITS n;
2163	#endif
2164	/** 32-bit view. */
2165	uint32_t au32[2];
2166	/** 16-bit view. */
2167	uint16_t au16[4];
2168	/** 8-bit view. */
2169	uint8_t au8[8];
2170	} X86PTEPAE;
2171	#ifndef VBOX_FOR_DTRACE_LIB
2172	AssertCompileSize(X86PTEPAE, 8);
2173	#endif
2174	/** Pointer to a PAE page table entry. */
2175	typedef X86PTEPAE *PX86PTEPAE;
2176	/** Pointer to a const PAE page table entry. */
2177	typedef const X86PTEPAE *PCX86PTEPAE;
2178	/** @} */
2179
2180	/**
2181	* Page table.
2182	*/
2183	typedef struct X86PT
2184	{
2185	/** PTE Array. */
2186	X86PTE a[X86_PG_ENTRIES];
2187	} X86PT;
2188	#ifndef VBOX_FOR_DTRACE_LIB
2189	AssertCompileSize(X86PT, 4096);
2190	#endif
2191	/** Pointer to a page table. */
2192	typedef X86PT *PX86PT;
2193	/** Pointer to a const page table. */
2194	typedef const X86PT *PCX86PT;
2195
2196	/** The page shift to get the PT index. */
2197	#define X86_PT_SHIFT 12
2198	/** The PT index mask (apply to a shifted page address). */
2199	#define X86_PT_MASK 0x3ff
2200
2201
2202	/**
2203	* Page directory.
2204	*/
2205	typedef struct X86PTPAE
2206	{
2207	/** PTE Array. */
2208	X86PTEPAE a[X86_PG_PAE_ENTRIES];
2209	} X86PTPAE;
2210	#ifndef VBOX_FOR_DTRACE_LIB
2211	AssertCompileSize(X86PTPAE, 4096);
2212	#endif
2213	/** Pointer to a page table. */
2214	typedef X86PTPAE *PX86PTPAE;
2215	/** Pointer to a const page table. */
2216	typedef const X86PTPAE *PCX86PTPAE;
2217
2218	/** The page shift to get the PA PTE index. */
2219	#define X86_PT_PAE_SHIFT 12
2220	/** The PAE PT index mask (apply to a shifted page address). */
2221	#define X86_PT_PAE_MASK 0x1ff
2222
2223
2224	/** @name 4KB Page Directory Entry
2225	* @{
2226	*/
2227	/** Bit 0 - P - Present bit. */
2228	#define X86_PDE_P RT_BIT_32(0)
2229	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2230	#define X86_PDE_RW RT_BIT_32(1)
2231	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2232	#define X86_PDE_US RT_BIT_32(2)
2233	/** Bit 3 - PWT - Page level write thru bit. */
2234	#define X86_PDE_PWT RT_BIT_32(3)
2235	/** Bit 4 - PCD - Page level cache disable bit. */
2236	#define X86_PDE_PCD RT_BIT_32(4)
2237	/** Bit 5 - A - Access bit. */
2238	#define X86_PDE_A RT_BIT_32(5)
2239	/** Bit 7 - PS - Page size attribute.
2240	* Clear mean 4KB pages, set means large pages (2/4MB). */
2241	#define X86_PDE_PS RT_BIT_32(7)
2242	/** Bits 9-11 - - Available for use to system software. */
2243	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2244	/** Bits 12-31 - - Physical Page number of the next level. */
2245	#define X86_PDE_PG_MASK ( 0xfffff000 )
2246
2247	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2248	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2249	/** Bits 63 - NX - PAE/LM - No execution flag. */
2250	#define X86_PDE_PAE_NX RT_BIT_64(63)
2251	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2252	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2253	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2254	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2255	/** Bit 7 - - LM - MBZ bits when NX is active. */
2256	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2257	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2258	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2259
2260	/**
2261	* Page directory entry.
2262	*/
2263	typedef struct X86PDEBITS
2264	{
2265	/** Flags whether(=1) or not the page is present. */
2266	uint32_t u1Present : 1;
2267	/** Read(=0) / Write(=1) flag. */
2268	uint32_t u1Write : 1;
2269	/** User(=1) / Supervisor (=0) flag. */
2270	uint32_t u1User : 1;
2271	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2272	uint32_t u1WriteThru : 1;
2273	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2274	uint32_t u1CacheDisable : 1;
2275	/** Accessed flag.
2276	* Indicates that the page has been read or written to. */
2277	uint32_t u1Accessed : 1;
2278	/** Reserved / Ignored (dirty bit). */
2279	uint32_t u1Reserved0 : 1;
2280	/** Size bit if PSE is enabled - in any event it's 0. */
2281	uint32_t u1Size : 1;
2282	/** Reserved / Ignored (global bit). */
2283	uint32_t u1Reserved1 : 1;
2284	/** Available for use to system software. */
2285	uint32_t u3Available : 3;
2286	/** Physical Page number of the next level. */
2287	uint32_t u20PageNo : 20;
2288	} X86PDEBITS;
2289	#ifndef VBOX_FOR_DTRACE_LIB
2290	AssertCompileSize(X86PDEBITS, 4);
2291	#endif
2292	/** Pointer to a page directory entry. */
2293	typedef X86PDEBITS *PX86PDEBITS;
2294	/** Pointer to a const page directory entry. */
2295	typedef const X86PDEBITS *PCX86PDEBITS;
2296
2297
2298	/**
2299	* PAE page directory entry.
2300	*/
2301	typedef struct X86PDEPAEBITS
2302	{
2303	/** Flags whether(=1) or not the page is present. */
2304	uint32_t u1Present : 1;
2305	/** Read(=0) / Write(=1) flag. */
2306	uint32_t u1Write : 1;
2307	/** User(=1) / Supervisor (=0) flag. */
2308	uint32_t u1User : 1;
2309	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2310	uint32_t u1WriteThru : 1;
2311	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2312	uint32_t u1CacheDisable : 1;
2313	/** Accessed flag.
2314	* Indicates that the page has been read or written to. */
2315	uint32_t u1Accessed : 1;
2316	/** Reserved / Ignored (dirty bit). */
2317	uint32_t u1Reserved0 : 1;
2318	/** Size bit if PSE is enabled - in any event it's 0. */
2319	uint32_t u1Size : 1;
2320	/** Reserved / Ignored (global bit). / */
2321	uint32_t u1Reserved1 : 1;
2322	/** Available for use to system software. */
2323	uint32_t u3Available : 3;
2324	/** Physical Page number of the next level - Low Part. Don't use! */
2325	uint32_t u20PageNoLow : 20;
2326	/** Physical Page number of the next level - High Part. Don't use! */
2327	uint32_t u20PageNoHigh : 20;
2328	/** MBZ bits */
2329	uint32_t u11Reserved : 11;
2330	/** No Execute flag. */
2331	uint32_t u1NoExecute : 1;
2332	} X86PDEPAEBITS;
2333	#ifndef VBOX_FOR_DTRACE_LIB
2334	AssertCompileSize(X86PDEPAEBITS, 8);
2335	#endif
2336	/** Pointer to a page directory entry. */
2337	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2338	/** Pointer to a const page directory entry. */
2339	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2340
2341	/** @} */
2342
2343
2344	/** @name 2/4MB Page Directory Entry
2345	* @{
2346	*/
2347	/** Bit 0 - P - Present bit. */
2348	#define X86_PDE4M_P RT_BIT_32(0)
2349	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2350	#define X86_PDE4M_RW RT_BIT_32(1)
2351	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2352	#define X86_PDE4M_US RT_BIT_32(2)
2353	/** Bit 3 - PWT - Page level write thru bit. */
2354	#define X86_PDE4M_PWT RT_BIT_32(3)
2355	/** Bit 4 - PCD - Page level cache disable bit. */
2356	#define X86_PDE4M_PCD RT_BIT_32(4)
2357	/** Bit 5 - A - Access bit. */
2358	#define X86_PDE4M_A RT_BIT_32(5)
2359	/** Bit 6 - D - Dirty bit. */
2360	#define X86_PDE4M_D RT_BIT_32(6)
2361	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2362	#define X86_PDE4M_PS RT_BIT_32(7)
2363	/** Bit 8 - G - Global flag. */
2364	#define X86_PDE4M_G RT_BIT_32(8)
2365	/** Bits 9-11 - AVL - Available for use to system software. */
2366	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2367	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2368	#define X86_PDE4M_PAT RT_BIT_32(12)
2369	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2370	#define X86_PDE4M_PAT_SHIFT (12 - 7)
2371	/** Bits 22-31 - - Physical Page number. */
2372	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2373	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2374	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2375	/** The number of bits to the high part of the page number. */
2376	#define X86_PDE4M_PG_HIGH_SHIFT 19
2377	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2378	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2379
2380	/** Bits 21-51 - - PAE/LM - Physical Page number.
2381	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2382	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2383	/** Bits 63 - NX - PAE/LM - No execution flag. */
2384	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2385	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2386	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2387	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2388	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2389	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2390	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2391	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2392	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2393
2394	/**
2395	* 4MB page directory entry.
2396	*/
2397	typedef struct X86PDE4MBITS
2398	{
2399	/** Flags whether(=1) or not the page is present. */
2400	uint32_t u1Present : 1;
2401	/** Read(=0) / Write(=1) flag. */
2402	uint32_t u1Write : 1;
2403	/** User(=1) / Supervisor (=0) flag. */
2404	uint32_t u1User : 1;
2405	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2406	uint32_t u1WriteThru : 1;
2407	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2408	uint32_t u1CacheDisable : 1;
2409	/** Accessed flag.
2410	* Indicates that the page have been read or written to. */
2411	uint32_t u1Accessed : 1;
2412	/** Dirty flag.
2413	* Indicates that the page has been written to. */
2414	uint32_t u1Dirty : 1;
2415	/** Page size flag - always 1 for 4MB entries. */
2416	uint32_t u1Size : 1;
2417	/** Global flag. */
2418	uint32_t u1Global : 1;
2419	/** Available for use to system software. */
2420	uint32_t u3Available : 3;
2421	/** Reserved / If PAT enabled, bit 2 of the index. */
2422	uint32_t u1PAT : 1;
2423	/** Bits 32-39 of the page number on AMD64.
2424	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2425	uint32_t u8PageNoHigh : 8;
2426	/** Reserved. */
2427	uint32_t u1Reserved : 1;
2428	/** Physical Page number of the page. */
2429	uint32_t u10PageNo : 10;
2430	} X86PDE4MBITS;
2431	#ifndef VBOX_FOR_DTRACE_LIB
2432	AssertCompileSize(X86PDE4MBITS, 4);
2433	#endif
2434	/** Pointer to a page table entry. */
2435	typedef X86PDE4MBITS *PX86PDE4MBITS;
2436	/** Pointer to a const page table entry. */
2437	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2438
2439
2440	/**
2441	* 2MB PAE page directory entry.
2442	*/
2443	typedef struct X86PDE2MPAEBITS
2444	{
2445	/** Flags whether(=1) or not the page is present. */
2446	uint32_t u1Present : 1;
2447	/** Read(=0) / Write(=1) flag. */
2448	uint32_t u1Write : 1;
2449	/** User(=1) / Supervisor(=0) flag. */
2450	uint32_t u1User : 1;
2451	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2452	uint32_t u1WriteThru : 1;
2453	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2454	uint32_t u1CacheDisable : 1;
2455	/** Accessed flag.
2456	* Indicates that the page have been read or written to. */
2457	uint32_t u1Accessed : 1;
2458	/** Dirty flag.
2459	* Indicates that the page has been written to. */
2460	uint32_t u1Dirty : 1;
2461	/** Page size flag - always 1 for 2MB entries. */
2462	uint32_t u1Size : 1;
2463	/** Global flag. */
2464	uint32_t u1Global : 1;
2465	/** Available for use to system software. */
2466	uint32_t u3Available : 3;
2467	/** Reserved / If PAT enabled, bit 2 of the index. */
2468	uint32_t u1PAT : 1;
2469	/** Reserved. */
2470	uint32_t u9Reserved : 9;
2471	/** Physical Page number of the next level - Low part. Don't use! */
2472	uint32_t u10PageNoLow : 10;
2473	/** Physical Page number of the next level - High part. Don't use! */
2474	uint32_t u20PageNoHigh : 20;
2475	/** MBZ bits */
2476	uint32_t u11Reserved : 11;
2477	/** No Execute flag. */
2478	uint32_t u1NoExecute : 1;
2479	} X86PDE2MPAEBITS;
2480	#ifndef VBOX_FOR_DTRACE_LIB
2481	AssertCompileSize(X86PDE2MPAEBITS, 8);
2482	#endif
2483	/** Pointer to a 2MB PAE page table entry. */
2484	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2485	/** Pointer to a 2MB PAE page table entry. */
2486	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2487
2488	/** @} */
2489
2490	/**
2491	* Page directory entry.
2492	*/
2493	typedef union X86PDE
2494	{
2495	/** Unsigned integer view. */
2496	X86PGUINT u;
2497	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2498	/** Normal view. */
2499	X86PDEBITS n;
2500	/** 4MB view (big). */
2501	X86PDE4MBITS b;
2502	#endif
2503	/** 8 bit unsigned integer view. */
2504	uint8_t au8[4];
2505	/** 16 bit unsigned integer view. */
2506	uint16_t au16[2];
2507	/** 32 bit unsigned integer view. */
2508	uint32_t au32[1];
2509	} X86PDE;
2510	#ifndef VBOX_FOR_DTRACE_LIB
2511	AssertCompileSize(X86PDE, 4);
2512	#endif
2513	/** Pointer to a page directory entry. */
2514	typedef X86PDE *PX86PDE;
2515	/** Pointer to a const page directory entry. */
2516	typedef const X86PDE *PCX86PDE;
2517
2518	/**
2519	* PAE page directory entry.
2520	*/
2521	typedef union X86PDEPAE
2522	{
2523	/** Unsigned integer view. */
2524	X86PGPAEUINT u;
2525	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2526	/** Normal view. */
2527	X86PDEPAEBITS n;
2528	/** 2MB page view (big). */
2529	X86PDE2MPAEBITS b;
2530	#endif
2531	/** 8 bit unsigned integer view. */
2532	uint8_t au8[8];
2533	/** 16 bit unsigned integer view. */
2534	uint16_t au16[4];
2535	/** 32 bit unsigned integer view. */
2536	uint32_t au32[2];
2537	} X86PDEPAE;
2538	#ifndef VBOX_FOR_DTRACE_LIB
2539	AssertCompileSize(X86PDEPAE, 8);
2540	#endif
2541	/** Pointer to a page directory entry. */
2542	typedef X86PDEPAE *PX86PDEPAE;
2543	/** Pointer to a const page directory entry. */
2544	typedef const X86PDEPAE *PCX86PDEPAE;
2545
2546	/**
2547	* Page directory.
2548	*/
2549	typedef struct X86PD
2550	{
2551	/** PDE Array. */
2552	X86PDE a[X86_PG_ENTRIES];
2553	} X86PD;
2554	#ifndef VBOX_FOR_DTRACE_LIB
2555	AssertCompileSize(X86PD, 4096);
2556	#endif
2557	/** Pointer to a page directory. */
2558	typedef X86PD *PX86PD;
2559	/** Pointer to a const page directory. */
2560	typedef const X86PD *PCX86PD;
2561
2562	/** The page shift to get the PD index. */
2563	#define X86_PD_SHIFT 22
2564	/** The PD index mask (apply to a shifted page address). */
2565	#define X86_PD_MASK 0x3ff
2566
2567
2568	/**
2569	* PAE page directory.
2570	*/
2571	typedef struct X86PDPAE
2572	{
2573	/** PDE Array. */
2574	X86PDEPAE a[X86_PG_PAE_ENTRIES];
2575	} X86PDPAE;
2576	#ifndef VBOX_FOR_DTRACE_LIB
2577	AssertCompileSize(X86PDPAE, 4096);
2578	#endif
2579	/** Pointer to a PAE page directory. */
2580	typedef X86PDPAE *PX86PDPAE;
2581	/** Pointer to a const PAE page directory. */
2582	typedef const X86PDPAE *PCX86PDPAE;
2583
2584	/** The page shift to get the PAE PD index. */
2585	#define X86_PD_PAE_SHIFT 21
2586	/** The PAE PD index mask (apply to a shifted page address). */
2587	#define X86_PD_PAE_MASK 0x1ff
2588
2589
2590	/** @name Page Directory Pointer Table Entry (PAE)
2591	* @{
2592	*/
2593	/** Bit 0 - P - Present bit. */
2594	#define X86_PDPE_P RT_BIT_32(0)
2595	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2596	#define X86_PDPE_RW RT_BIT_32(1)
2597	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2598	#define X86_PDPE_US RT_BIT_32(2)
2599	/** Bit 3 - PWT - Page level write thru bit. */
2600	#define X86_PDPE_PWT RT_BIT_32(3)
2601	/** Bit 4 - PCD - Page level cache disable bit. */
2602	#define X86_PDPE_PCD RT_BIT_32(4)
2603	/** Bit 5 - A - Access bit. Long Mode only. */
2604	#define X86_PDPE_A RT_BIT_32(5)
2605	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2606	#define X86_PDPE_LM_PS RT_BIT_32(7)
2607	/** Bits 9-11 - - Available for use to system software. */
2608	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2609	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2610	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2611	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2612	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2613	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2614	#define X86_PDPE_LM_NX RT_BIT_64(63)
2615	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2616	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2617	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2618	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2619	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2620	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2621	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2622	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2623
2624
2625	/**
2626	* Page directory pointer table entry.
2627	*/
2628	typedef struct X86PDPEBITS
2629	{
2630	/** Flags whether(=1) or not the page is present. */
2631	uint32_t u1Present : 1;
2632	/** Chunk of reserved bits. */
2633	uint32_t u2Reserved : 2;
2634	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2635	uint32_t u1WriteThru : 1;
2636	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2637	uint32_t u1CacheDisable : 1;
2638	/** Chunk of reserved bits. */
2639	uint32_t u4Reserved : 4;
2640	/** Available for use to system software. */
2641	uint32_t u3Available : 3;
2642	/** Physical Page number of the next level - Low Part. Don't use! */
2643	uint32_t u20PageNoLow : 20;
2644	/** Physical Page number of the next level - High Part. Don't use! */
2645	uint32_t u20PageNoHigh : 20;
2646	/** MBZ bits */
2647	uint32_t u12Reserved : 12;
2648	} X86PDPEBITS;
2649	#ifndef VBOX_FOR_DTRACE_LIB
2650	AssertCompileSize(X86PDPEBITS, 8);
2651	#endif
2652	/** Pointer to a page directory pointer table entry. */
2653	typedef X86PDPEBITS *PX86PTPEBITS;
2654	/** Pointer to a const page directory pointer table entry. */
2655	typedef const X86PDPEBITS *PCX86PTPEBITS;
2656
2657	/**
2658	* Page directory pointer table entry. AMD64 version
2659	*/
2660	typedef struct X86PDPEAMD64BITS
2661	{
2662	/** Flags whether(=1) or not the page is present. */
2663	uint32_t u1Present : 1;
2664	/** Read(=0) / Write(=1) flag. */
2665	uint32_t u1Write : 1;
2666	/** User(=1) / Supervisor (=0) flag. */
2667	uint32_t u1User : 1;
2668	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2669	uint32_t u1WriteThru : 1;
2670	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2671	uint32_t u1CacheDisable : 1;
2672	/** Accessed flag.
2673	* Indicates that the page have been read or written to. */
2674	uint32_t u1Accessed : 1;
2675	/** Chunk of reserved bits. */
2676	uint32_t u3Reserved : 3;
2677	/** Available for use to system software. */
2678	uint32_t u3Available : 3;
2679	/** Physical Page number of the next level - Low Part. Don't use! */
2680	uint32_t u20PageNoLow : 20;
2681	/** Physical Page number of the next level - High Part. Don't use! */
2682	uint32_t u20PageNoHigh : 20;
2683	/** MBZ bits */
2684	uint32_t u11Reserved : 11;
2685	/** No Execute flag. */
2686	uint32_t u1NoExecute : 1;
2687	} X86PDPEAMD64BITS;
2688	#ifndef VBOX_FOR_DTRACE_LIB
2689	AssertCompileSize(X86PDPEAMD64BITS, 8);
2690	#endif
2691	/** Pointer to a page directory pointer table entry. */
2692	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2693	/** Pointer to a const page directory pointer table entry. */
2694	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2695
2696	/**
2697	* Page directory pointer table entry for 1GB page. (AMD64 only)
2698	*/
2699	typedef struct X86PDPE1GB
2700	{
2701	/** 0: Flags whether(=1) or not the page is present. */
2702	uint32_t u1Present : 1;
2703	/** 1: Read(=0) / Write(=1) flag. */
2704	uint32_t u1Write : 1;
2705	/** 2: User(=1) / Supervisor (=0) flag. */
2706	uint32_t u1User : 1;
2707	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2708	uint32_t u1WriteThru : 1;
2709	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2710	uint32_t u1CacheDisable : 1;
2711	/** 5: Accessed flag.
2712	* Indicates that the page have been read or written to. */
2713	uint32_t u1Accessed : 1;
2714	/** 6: Dirty flag for 1GB pages. */
2715	uint32_t u1Dirty : 1;
2716	/** 7: Indicates 1GB page if set. */
2717	uint32_t u1Size : 1;
2718	/** 8: Global 1GB page. */
2719	uint32_t u1Global: 1;
2720	/** 9-11: Available for use to system software. */
2721	uint32_t u3Available : 3;
2722	/** 12: PAT bit for 1GB page. */
2723	uint32_t u1PAT : 1;
2724	/** 13-29: MBZ bits. */
2725	uint32_t u17Reserved : 17;
2726	/** 30-31: Physical page number - Low Part. Don't use! */
2727	uint32_t u2PageNoLow : 2;
2728	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
2729	uint32_t u20PageNoHigh : 20;
2730	/** 52-62: MBZ bits */
2731	uint32_t u11Reserved : 11;
2732	/** 63: No Execute flag. */
2733	uint32_t u1NoExecute : 1;
2734	} X86PDPE1GB;
2735	#ifndef VBOX_FOR_DTRACE_LIB
2736	AssertCompileSize(X86PDPE1GB, 8);
2737	#endif
2738	/** Pointer to a page directory pointer table entry for a 1GB page. */
2739	typedef X86PDPE1GB *PX86PDPE1GB;
2740	/** Pointer to a const page directory pointer table entry for a 1GB page. */
2741	typedef const X86PDPE1GB *PCX86PDPE1GB;
2742
2743	/**
2744	* Page directory pointer table entry.
2745	*/
2746	typedef union X86PDPE
2747	{
2748	/** Unsigned integer view. */
2749	X86PGPAEUINT u;
2750	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2751	/** Normal view. */
2752	X86PDPEBITS n;
2753	/** AMD64 view. */
2754	X86PDPEAMD64BITS lm;
2755	/** AMD64 big view. */
2756	X86PDPE1GB b;
2757	#endif
2758	/** 8 bit unsigned integer view. */
2759	uint8_t au8[8];
2760	/** 16 bit unsigned integer view. */
2761	uint16_t au16[4];
2762	/** 32 bit unsigned integer view. */
2763	uint32_t au32[2];
2764	} X86PDPE;
2765	#ifndef VBOX_FOR_DTRACE_LIB
2766	AssertCompileSize(X86PDPE, 8);
2767	#endif
2768	/** Pointer to a page directory pointer table entry. */
2769	typedef X86PDPE *PX86PDPE;
2770	/** Pointer to a const page directory pointer table entry. */
2771	typedef const X86PDPE *PCX86PDPE;
2772
2773
2774	/**
2775	* Page directory pointer table.
2776	*/
2777	typedef struct X86PDPT
2778	{
2779	/** PDE Array. */
2780	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2781	} X86PDPT;
2782	#ifndef VBOX_FOR_DTRACE_LIB
2783	AssertCompileSize(X86PDPT, 4096);
2784	#endif
2785	/** Pointer to a page directory pointer table. */
2786	typedef X86PDPT *PX86PDPT;
2787	/** Pointer to a const page directory pointer table. */
2788	typedef const X86PDPT *PCX86PDPT;
2789
2790	/** The page shift to get the PDPT index. */
2791	#define X86_PDPT_SHIFT 30
2792	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2793	#define X86_PDPT_MASK_PAE 0x3
2794	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2795	#define X86_PDPT_MASK_AMD64 0x1ff
2796
2797	/** @} */
2798
2799
2800	/** @name Page Map Level-4 Entry (Long Mode PAE)
2801	* @{
2802	*/
2803	/** Bit 0 - P - Present bit. */
2804	#define X86_PML4E_P RT_BIT_32(0)
2805	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2806	#define X86_PML4E_RW RT_BIT_32(1)
2807	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2808	#define X86_PML4E_US RT_BIT_32(2)
2809	/** Bit 3 - PWT - Page level write thru bit. */
2810	#define X86_PML4E_PWT RT_BIT_32(3)
2811	/** Bit 4 - PCD - Page level cache disable bit. */
2812	#define X86_PML4E_PCD RT_BIT_32(4)
2813	/** Bit 5 - A - Access bit. */
2814	#define X86_PML4E_A RT_BIT_32(5)
2815	/** Bits 9-11 - - Available for use to system software. */
2816	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2817	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2818	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2819	/** Bits 8, 7 - - MBZ bits when NX is active. */
2820	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2821	/** Bits 63, 7 - - MBZ bits when no NX. */
2822	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2823	/** Bits 63 - NX - PAE - No execution flag. */
2824	#define X86_PML4E_NX RT_BIT_64(63)
2825
2826	/**
2827	* Page Map Level-4 Entry
2828	*/
2829	typedef struct X86PML4EBITS
2830	{
2831	/** Flags whether(=1) or not the page is present. */
2832	uint32_t u1Present : 1;
2833	/** Read(=0) / Write(=1) flag. */
2834	uint32_t u1Write : 1;
2835	/** User(=1) / Supervisor (=0) flag. */
2836	uint32_t u1User : 1;
2837	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2838	uint32_t u1WriteThru : 1;
2839	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2840	uint32_t u1CacheDisable : 1;
2841	/** Accessed flag.
2842	* Indicates that the page have been read or written to. */
2843	uint32_t u1Accessed : 1;
2844	/** Chunk of reserved bits. */
2845	uint32_t u3Reserved : 3;
2846	/** Available for use to system software. */
2847	uint32_t u3Available : 3;
2848	/** Physical Page number of the next level - Low Part. Don't use! */
2849	uint32_t u20PageNoLow : 20;
2850	/** Physical Page number of the next level - High Part. Don't use! */
2851	uint32_t u20PageNoHigh : 20;
2852	/** MBZ bits */
2853	uint32_t u11Reserved : 11;
2854	/** No Execute flag. */
2855	uint32_t u1NoExecute : 1;
2856	} X86PML4EBITS;
2857	#ifndef VBOX_FOR_DTRACE_LIB
2858	AssertCompileSize(X86PML4EBITS, 8);
2859	#endif
2860	/** Pointer to a page map level-4 entry. */
2861	typedef X86PML4EBITS *PX86PML4EBITS;
2862	/** Pointer to a const page map level-4 entry. */
2863	typedef const X86PML4EBITS *PCX86PML4EBITS;
2864
2865	/**
2866	* Page Map Level-4 Entry.
2867	*/
2868	typedef union X86PML4E
2869	{
2870	/** Unsigned integer view. */
2871	X86PGPAEUINT u;
2872	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2873	/** Normal view. */
2874	X86PML4EBITS n;
2875	#endif
2876	/** 8 bit unsigned integer view. */
2877	uint8_t au8[8];
2878	/** 16 bit unsigned integer view. */
2879	uint16_t au16[4];
2880	/** 32 bit unsigned integer view. */
2881	uint32_t au32[2];
2882	} X86PML4E;
2883	#ifndef VBOX_FOR_DTRACE_LIB
2884	AssertCompileSize(X86PML4E, 8);
2885	#endif
2886	/** Pointer to a page map level-4 entry. */
2887	typedef X86PML4E *PX86PML4E;
2888	/** Pointer to a const page map level-4 entry. */
2889	typedef const X86PML4E *PCX86PML4E;
2890
2891
2892	/**
2893	* Page Map Level-4.
2894	*/
2895	typedef struct X86PML4
2896	{
2897	/** PDE Array. */
2898	X86PML4E a[X86_PG_PAE_ENTRIES];
2899	} X86PML4;
2900	#ifndef VBOX_FOR_DTRACE_LIB
2901	AssertCompileSize(X86PML4, 4096);
2902	#endif
2903	/** Pointer to a page map level-4. */
2904	typedef X86PML4 *PX86PML4;
2905	/** Pointer to a const page map level-4. */
2906	typedef const X86PML4 *PCX86PML4;
2907
2908	/** The page shift to get the PML4 index. */
2909	#define X86_PML4_SHIFT 39
2910	/** The PML4 index mask (apply to a shifted page address). */
2911	#define X86_PML4_MASK 0x1ff
2912
2913	/** @} */
2914
2915	/** @} */
2916
2917	/**
2918	* Intel PCID invalidation types.
2919	*/
2920	/** Individual address invalidation. */
2921	#define X86_INVPCID_TYPE_INDV_ADDR 0
2922	/** Single-context invalidation. */
2923	#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
2924	/** All-context including globals invalidation. */
2925	#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
2926	/** All-context excluding globals invalidation. */
2927	#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
2928	/** The maximum valid invalidation type value. */
2929	#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
2930
2931	/**
2932	* 32-bit protected mode FSTENV image.
2933	*/
2934	typedef struct X86FSTENV32P
2935	{
2936	uint16_t FCW; /*< 0x00 /
2937	uint16_t padding1; /*< 0x02 /
2938	uint16_t FSW; /*< 0x04 /
2939	uint16_t padding2; /*< 0x06 /
2940	uint16_t FTW; /*< 0x08 /
2941	uint16_t padding3; /*< 0x0a /
2942	uint32_t FPUIP; /*< 0x0c /
2943	uint16_t FPUCS; /*< 0x10 /
2944	uint16_t FOP; /*< 0x12 /
2945	uint32_t FPUDP; /*< 0x14 /
2946	uint16_t FPUDS; /*< 0x18 /
2947	uint16_t padding4; /*< 0x1a /
2948	} X86FSTENV32P;
2949	#ifndef VBOX_FOR_DTRACE_LIB
2950	AssertCompileSize(X86FSTENV32P, 0x1c);
2951	#endif
2952	/** Pointer to a 32-bit protected mode FSTENV image. */
2953	typedef X86FSTENV32P *PX86FSTENV32P;
2954	/** Pointer to a const 32-bit protected mode FSTENV image. */
2955	typedef X86FSTENV32P const *PCX86FSTENV32P;
2956
2957
2958	/**
2959	* 80-bit MMX/FPU register type.
2960	*/
2961	typedef struct X86FPUMMX
2962	{
2963	uint8_t reg[10];
2964	} X86FPUMMX;
2965	#ifndef VBOX_FOR_DTRACE_LIB
2966	AssertCompileSize(X86FPUMMX, 10);
2967	#endif
2968	/** Pointer to a 80-bit MMX/FPU register type. */
2969	typedef X86FPUMMX *PX86FPUMMX;
2970	/** Pointer to a const 80-bit MMX/FPU register type. */
2971	typedef const X86FPUMMX *PCX86FPUMMX;
2972
2973	/** FPU (x87) register. */
2974	typedef union X86FPUREG
2975	{
2976	/** MMX view. */
2977	uint64_t mmx;
2978	/** FPU view - todo. */
2979	X86FPUMMX fpu;
2980	/** Extended precision floating point view. */
2981	RTFLOAT80U r80;
2982	/** Extended precision floating point view v2 */
2983	RTFLOAT80U2 r80Ex;
2984	/** 8-bit view. */
2985	uint8_t au8[16];
2986	/** 16-bit view. */
2987	uint16_t au16[8];
2988	/** 32-bit view. */
2989	uint32_t au32[4];
2990	/** 64-bit view. */
2991	uint64_t au64[2];
2992	/** 128-bit view. (yeah, very helpful) */
2993	uint128_t au128[1];
2994	} X86FPUREG;
2995	#ifndef VBOX_FOR_DTRACE_LIB
2996	AssertCompileSize(X86FPUREG, 16);
2997	#endif
2998	/** Pointer to a FPU register. */
2999	typedef X86FPUREG *PX86FPUREG;
3000	/** Pointer to a const FPU register. */
3001	typedef X86FPUREG const *PCX86FPUREG;
3002
3003	/**
3004	* XMM register union.
3005	*/
3006	typedef union X86XMMREG
3007	{
3008	/** XMM Register view. */
3009	uint128_t xmm;
3010	/** 8-bit view. */
3011	uint8_t au8[16];
3012	/** 16-bit view. */
3013	uint16_t au16[8];
3014	/** 32-bit view. */
3015	uint32_t au32[4];
3016	/** 64-bit view. */
3017	uint64_t au64[2];
3018	/** 128-bit view. (yeah, very helpful) */
3019	uint128_t au128[1];
3020	#ifndef VBOX_FOR_DTRACE_LIB
3021	/** Confusing nested 128-bit union view (this is what xmm should've been). */
3022	RTUINT128U uXmm;
3023	#endif
3024	} X86XMMREG;
3025	#ifndef VBOX_FOR_DTRACE_LIB
3026	AssertCompileSize(X86XMMREG, 16);
3027	#endif
3028	/** Pointer to an XMM register state. */
3029	typedef X86XMMREG *PX86XMMREG;
3030	/** Pointer to a const XMM register state. */
3031	typedef X86XMMREG const *PCX86XMMREG;
3032
3033	/**
3034	* YMM register union.
3035	*/
3036	typedef union X86YMMREG
3037	{
3038	/** 8-bit view. */
3039	uint8_t au8[32];
3040	/** 16-bit view. */
3041	uint16_t au16[16];
3042	/** 32-bit view. */
3043	uint32_t au32[8];
3044	/** 64-bit view. */
3045	uint64_t au64[4];
3046	/** 128-bit view. (yeah, very helpful) */
3047	uint128_t au128[2];
3048	/** XMM sub register view. */
3049	X86XMMREG aXmm[2];
3050	} X86YMMREG;
3051	#ifndef VBOX_FOR_DTRACE_LIB
3052	AssertCompileSize(X86YMMREG, 32);
3053	#endif
3054	/** Pointer to an YMM register state. */
3055	typedef X86YMMREG *PX86YMMREG;
3056	/** Pointer to a const YMM register state. */
3057	typedef X86YMMREG const *PCX86YMMREG;
3058
3059	/**
3060	* ZMM register union.
3061	*/
3062	typedef union X86ZMMREG
3063	{
3064	/** 8-bit view. */
3065	uint8_t au8[64];
3066	/** 16-bit view. */
3067	uint16_t au16[32];
3068	/** 32-bit view. */
3069	uint32_t au32[16];
3070	/** 64-bit view. */
3071	uint64_t au64[8];
3072	/** 128-bit view. (yeah, very helpful) */
3073	uint128_t au128[4];
3074	/** XMM sub register view. */
3075	X86XMMREG aXmm[4];
3076	/** YMM sub register view. */
3077	X86YMMREG aYmm[2];
3078	} X86ZMMREG;
3079	#ifndef VBOX_FOR_DTRACE_LIB
3080	AssertCompileSize(X86ZMMREG, 64);
3081	#endif
3082	/** Pointer to an ZMM register state. */
3083	typedef X86ZMMREG *PX86ZMMREG;
3084	/** Pointer to a const ZMM register state. */
3085	typedef X86ZMMREG const *PCX86ZMMREG;
3086
3087
3088	/**
3089	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3090	* @todo verify this...
3091	*/
3092	#pragma pack(1)
3093	typedef struct X86FPUSTATE
3094	{
3095	/** 0x00 - Control word. */
3096	uint16_t FCW;
3097	/** 0x02 - Alignment word */
3098	uint16_t Dummy1;
3099	/** 0x04 - Status word. */
3100	uint16_t FSW;
3101	/** 0x06 - Alignment word */
3102	uint16_t Dummy2;
3103	/** 0x08 - Tag word */
3104	uint16_t FTW;
3105	/** 0x0a - Alignment word */
3106	uint16_t Dummy3;
3107
3108	/** 0x0c - Instruction pointer. */
3109	uint32_t FPUIP;
3110	/** 0x10 - Code selector. */
3111	uint16_t CS;
3112	/** 0x12 - Opcode. */
3113	uint16_t FOP;
3114	/** 0x14 - FOO. */
3115	uint32_t FPUOO;
3116	/** 0x18 - FOS. */
3117	uint32_t FPUOS;
3118	/** 0x1c - FPU register. */
3119	X86FPUREG regs[8];
3120	} X86FPUSTATE;
3121	#pragma pack()
3122	/** Pointer to a FPU state. */
3123	typedef X86FPUSTATE *PX86FPUSTATE;
3124	/** Pointer to a const FPU state. */
3125	typedef const X86FPUSTATE *PCX86FPUSTATE;
3126
3127	/**
3128	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3129	*/
3130	#pragma pack(1)
3131	typedef struct X86FXSTATE
3132	{
3133	/** 0x00 - Control word. */
3134	uint16_t FCW;
3135	/** 0x02 - Status word. */
3136	uint16_t FSW;
3137	/** 0x04 - Tag word. (The upper byte is always zero.) */
3138	uint16_t FTW;
3139	/** 0x06 - Opcode. */
3140	uint16_t FOP;
3141	/** 0x08 - Instruction pointer. */
3142	uint32_t FPUIP;
3143	/** 0x0c - Code selector. */
3144	uint16_t CS;
3145	uint16_t Rsrvd1;
3146	/** 0x10 - Data pointer. */
3147	uint32_t FPUDP;
3148	/** 0x14 - Data segment */
3149	uint16_t DS;
3150	/** 0x16 */
3151	uint16_t Rsrvd2;
3152	/** 0x18 */
3153	uint32_t MXCSR;
3154	/** 0x1c */
3155	uint32_t MXCSR_MASK;
3156	/** 0x20 - FPU registers. */
3157	X86FPUREG aRegs[8];
3158	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3159	X86XMMREG aXMM[16];
3160	/* - offset 416 - */
3161	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3162	/* - offset 464 - Software usable reserved bits. */
3163	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3164	} X86FXSTATE;
3165	#pragma pack()
3166	/** Pointer to a FPU Extended state. */
3167	typedef X86FXSTATE *PX86FXSTATE;
3168	/** Pointer to a const FPU Extended state. */
3169	typedef const X86FXSTATE *PCX86FXSTATE;
3170
3171	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3172	* magic. Don't forget to update x86.mac if you change this! */
3173	#define X86_OFF_FXSTATE_RSVD 0x1d0
3174	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3175	* forget to update x86.mac if you change this!
3176	* @todo r=bird: This has nothing what-so-ever to do here.... */
3177	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3178	#ifndef VBOX_FOR_DTRACE_LIB
3179	AssertCompileSize(X86FXSTATE, 512);
3180	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3181	#endif
3182
3183	/** @name FPU status word flags.
3184	* @{ */
3185	/** Exception Flag: Invalid operation. */
3186	#define X86_FSW_IE RT_BIT_32(0)
3187	/** Exception Flag: Denormalized operand. */
3188	#define X86_FSW_DE RT_BIT_32(1)
3189	/** Exception Flag: Zero divide. */
3190	#define X86_FSW_ZE RT_BIT_32(2)
3191	/** Exception Flag: Overflow. */
3192	#define X86_FSW_OE RT_BIT_32(3)
3193	/** Exception Flag: Underflow. */
3194	#define X86_FSW_UE RT_BIT_32(4)
3195	/** Exception Flag: Precision. */
3196	#define X86_FSW_PE RT_BIT_32(5)
3197	/** Stack fault. */
3198	#define X86_FSW_SF RT_BIT_32(6)
3199	/** Error summary status. */
3200	#define X86_FSW_ES RT_BIT_32(7)
3201	/** Mask of exceptions flags, excluding the summary bit. */
3202	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3203	/** Mask of exceptions flags, including the summary bit. */
3204	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3205	/** Condition code 0. */
3206	#define X86_FSW_C0 RT_BIT_32(8)
3207	/** Condition code 1. */
3208	#define X86_FSW_C1 RT_BIT_32(9)
3209	/** Condition code 2. */
3210	#define X86_FSW_C2 RT_BIT_32(10)
3211	/** Top of the stack mask. */
3212	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3213	/** TOP shift value. */
3214	#define X86_FSW_TOP_SHIFT 11
3215	/** Mask for getting TOP value after shifting it right. */
3216	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3217	/** Get the TOP value. */
3218	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3219	/** Condition code 3. */
3220	#define X86_FSW_C3 RT_BIT_32(14)
3221	/** Mask of exceptions flags, including the summary bit. */
3222	#define X86_FSW_C_MASK UINT16_C(0x4700)
3223	/** FPU busy. */
3224	#define X86_FSW_B RT_BIT_32(15)
3225	/** @} */
3226
3227
3228	/** @name FPU control word flags.
3229	* @{ */
3230	/** Exception Mask: Invalid operation. */
3231	#define X86_FCW_IM RT_BIT_32(0)
3232	/** Exception Mask: Denormalized operand. */
3233	#define X86_FCW_DM RT_BIT_32(1)
3234	/** Exception Mask: Zero divide. */
3235	#define X86_FCW_ZM RT_BIT_32(2)
3236	/** Exception Mask: Overflow. */
3237	#define X86_FCW_OM RT_BIT_32(3)
3238	/** Exception Mask: Underflow. */
3239	#define X86_FCW_UM RT_BIT_32(4)
3240	/** Exception Mask: Precision. */
3241	#define X86_FCW_PM RT_BIT_32(5)
3242	/** Mask all exceptions, the value typically loaded (by for instance fninit).
3243	* @remarks This includes reserved bit 6. */
3244	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3245	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3246	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3247	/** Precision control mask. */
3248	#define X86_FCW_PC_MASK UINT16_C(0x0300)
3249	/** Precision control: 24-bit. */
3250	#define X86_FCW_PC_24 UINT16_C(0x0000)
3251	/** Precision control: Reserved. */
3252	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3253	/** Precision control: 53-bit. */
3254	#define X86_FCW_PC_53 UINT16_C(0x0200)
3255	/** Precision control: 64-bit. */
3256	#define X86_FCW_PC_64 UINT16_C(0x0300)
3257	/** Rounding control mask. */
3258	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3259	/** Rounding control: To nearest. */
3260	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3261	/** Rounding control: Down. */
3262	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3263	/** Rounding control: Up. */
3264	#define X86_FCW_RC_UP UINT16_C(0x0800)
3265	/** Rounding control: Towards zero. */
3266	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3267	/** Bits which should be zero, apparently. */
3268	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3269	/** @} */
3270
3271	/** @name SSE MXCSR
3272	* @{ */
3273	/** Exception Flag: Invalid operation. */
3274	#define X86_MXCSR_IE RT_BIT_32(0)
3275	/** Exception Flag: Denormalized operand. */
3276	#define X86_MXCSR_DE RT_BIT_32(1)
3277	/** Exception Flag: Zero divide. */
3278	#define X86_MXCSR_ZE RT_BIT_32(2)
3279	/** Exception Flag: Overflow. */
3280	#define X86_MXCSR_OE RT_BIT_32(3)
3281	/** Exception Flag: Underflow. */
3282	#define X86_MXCSR_UE RT_BIT_32(4)
3283	/** Exception Flag: Precision. */
3284	#define X86_MXCSR_PE RT_BIT_32(5)
3285
3286	/** Denormals are zero. */
3287	#define X86_MXCSR_DAZ RT_BIT_32(6)
3288
3289	/** Exception Mask: Invalid operation. */
3290	#define X86_MXCSR_IM RT_BIT_32(7)
3291	/** Exception Mask: Denormalized operand. */
3292	#define X86_MXCSR_DM RT_BIT_32(8)
3293	/** Exception Mask: Zero divide. */
3294	#define X86_MXCSR_ZM RT_BIT_32(9)
3295	/** Exception Mask: Overflow. */
3296	#define X86_MXCSR_OM RT_BIT_32(10)
3297	/** Exception Mask: Underflow. */
3298	#define X86_MXCSR_UM RT_BIT_32(11)
3299	/** Exception Mask: Precision. */
3300	#define X86_MXCSR_PM RT_BIT_32(12)
3301
3302	/** Rounding control mask. */
3303	#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
3304	/** Rounding control: To nearest. */
3305	#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
3306	/** Rounding control: Down. */
3307	#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
3308	/** Rounding control: Up. */
3309	#define X86_MXCSR_RC_UP UINT16_C(0x4000)
3310	/** Rounding control: Towards zero. */
3311	#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
3312
3313	/** Flush-to-zero for masked underflow. */
3314	#define X86_MXCSR_FZ RT_BIT_32(15)
3315
3316	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3317	#define X86_MXCSR_MM RT_BIT_32(17)
3318	/** @} */
3319
3320	/**
3321	* XSAVE header.
3322	*/
3323	typedef struct X86XSAVEHDR
3324	{
3325	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
3326	uint64_t bmXState;
3327	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3328	uint64_t bmXComp;
3329	/** Reserved for furture extensions, probably MBZ. */
3330	uint64_t au64Reserved[6];
3331	} X86XSAVEHDR;
3332	#ifndef VBOX_FOR_DTRACE_LIB
3333	AssertCompileSize(X86XSAVEHDR, 64);
3334	#endif
3335	/** Pointer to an XSAVE header. */
3336	typedef X86XSAVEHDR *PX86XSAVEHDR;
3337	/** Pointer to a const XSAVE header. */
3338	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3339
3340
3341	/**
3342	* The high 128-bit YMM register state (XSAVE_C_YMM).
3343	* (The lower 128-bits being in X86FXSTATE.)
3344	*/
3345	typedef struct X86XSAVEYMMHI
3346	{
3347	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3348	X86XMMREG aYmmHi[16];
3349	} X86XSAVEYMMHI;
3350	#ifndef VBOX_FOR_DTRACE_LIB
3351	AssertCompileSize(X86XSAVEYMMHI, 256);
3352	#endif
3353	/** Pointer to a high 128-bit YMM register state. */
3354	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3355	/** Pointer to a const high 128-bit YMM register state. */
3356	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3357
3358	/**
3359	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
3360	*/
3361	typedef struct X86XSAVEBNDREGS
3362	{
3363	/** Array of registers (BND0...BND3). */
3364	struct
3365	{
3366	/** Lower bound. */
3367	uint64_t uLowerBound;
3368	/** Upper bound. */
3369	uint64_t uUpperBound;
3370	} aRegs[4];
3371	} X86XSAVEBNDREGS;
3372	#ifndef VBOX_FOR_DTRACE_LIB
3373	AssertCompileSize(X86XSAVEBNDREGS, 64);
3374	#endif
3375	/** Pointer to a MPX bound register state. */
3376	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3377	/** Pointer to a const MPX bound register state. */
3378	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3379
3380	/**
3381	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3382	*/
3383	typedef struct X86XSAVEBNDCFG
3384	{
3385	uint64_t fConfig;
3386	uint64_t fStatus;
3387	} X86XSAVEBNDCFG;
3388	#ifndef VBOX_FOR_DTRACE_LIB
3389	AssertCompileSize(X86XSAVEBNDCFG, 16);
3390	#endif
3391	/** Pointer to a MPX bound config and status register state. */
3392	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3393	/** Pointer to a const MPX bound config and status register state. */
3394	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3395
3396	/**
3397	* AVX-512 opmask state (XSAVE_C_OPMASK).
3398	*/
3399	typedef struct X86XSAVEOPMASK
3400	{
3401	/** The K0..K7 values. */
3402	uint64_t aKRegs[8];
3403	} X86XSAVEOPMASK;
3404	#ifndef VBOX_FOR_DTRACE_LIB
3405	AssertCompileSize(X86XSAVEOPMASK, 64);
3406	#endif
3407	/** Pointer to a AVX-512 opmask state. */
3408	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3409	/** Pointer to a const AVX-512 opmask state. */
3410	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3411
3412	/**
3413	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3414	*/
3415	typedef struct X86XSAVEZMMHI256
3416	{
3417	/** Upper 256-bits of ZMM0-15. */
3418	X86YMMREG aHi256Regs[16];
3419	} X86XSAVEZMMHI256;
3420	#ifndef VBOX_FOR_DTRACE_LIB
3421	AssertCompileSize(X86XSAVEZMMHI256, 512);
3422	#endif
3423	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3424	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3425	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3426	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3427
3428	/**
3429	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3430	*/
3431	typedef struct X86XSAVEZMM16HI
3432	{
3433	/** ZMM16 thru ZMM31. */
3434	X86ZMMREG aRegs[16];
3435	} X86XSAVEZMM16HI;
3436	#ifndef VBOX_FOR_DTRACE_LIB
3437	AssertCompileSize(X86XSAVEZMM16HI, 1024);
3438	#endif
3439	/** Pointer to a state comprising ZMM16-32. */
3440	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3441	/** Pointer to a const state comprising ZMM16-32. */
3442	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3443
3444	/**
3445	* AMD Light weight profiling state (XSAVE_C_LWP).
3446	*
3447	* We probably won't play with this as AMD seems to be dropping from their "zen"
3448	* processor micro architecture.
3449	*/
3450	typedef struct X86XSAVELWP
3451	{
3452	/** Details when needed. */
3453	uint64_t auLater[128/8];
3454	} X86XSAVELWP;
3455	#ifndef VBOX_FOR_DTRACE_LIB
3456	AssertCompileSize(X86XSAVELWP, 128);
3457	#endif
3458
3459
3460	/**
3461	* x86 FPU/SSE/AVX/XXXX state.
3462	*
3463	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3464	* changes to this structure.
3465	*/
3466	typedef struct X86XSAVEAREA
3467	{
3468	/** The x87 and SSE region (or legacy region if you like). */
3469	X86FXSTATE x87;
3470	/** The XSAVE header. */
3471	X86XSAVEHDR Hdr;
3472	/** Beyond the header, there isn't really a fixed layout, but we can
3473	generally assume the YMM (AVX) register extensions are present and
3474	follows immediately. */
3475	union
3476	{
3477	/** The high 128-bit AVX registers for easy access by IEM.
3478	* @note This ASSUMES they will always be here... */
3479	X86XSAVEYMMHI YmmHi;
3480
3481	/** This is a typical layout on intel CPUs (good for debuggers). */
3482	struct
3483	{
3484	X86XSAVEYMMHI YmmHi;
3485	X86XSAVEBNDREGS BndRegs;
3486	X86XSAVEBNDCFG BndCfg;
3487	uint8_t abFudgeToMatchDocs[0xB0];
3488	X86XSAVEOPMASK Opmask;
3489	X86XSAVEZMMHI256 ZmmHi256;
3490	X86XSAVEZMM16HI Zmm16Hi;
3491	} Intel;
3492
3493	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3494	struct
3495	{
3496	X86XSAVEYMMHI YmmHi;
3497	X86XSAVELWP Lwp;
3498	} AmdBd;
3499
3500	/** To enbling static deployments that have a reasonable chance of working for
3501	* the next 3-6 CPU generations without running short on space, we allocate a
3502	* lot of extra space here, making the structure a round 8KB in size. This
3503	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3504	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3505	uint8_t ab[8192 - 512 - 64];
3506	} u;
3507	} X86XSAVEAREA;
3508	#ifndef VBOX_FOR_DTRACE_LIB
3509	AssertCompileSize(X86XSAVEAREA, 8192);
3510	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
3511	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3512	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3513	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3514	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3515	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3516	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3517	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3518	#endif
3519	/** Pointer to a XSAVE area. */
3520	typedef X86XSAVEAREA *PX86XSAVEAREA;
3521	/** Pointer to a const XSAVE area. */
3522	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3523
3524
3525	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3526	* @{ */
3527	/** Bit 0 - x87 - Legacy FPU state (bit number) */
3528	#define XSAVE_C_X87_BIT 0
3529	/** Bit 0 - x87 - Legacy FPU state. */
3530	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3531	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3532	#define XSAVE_C_SSE_BIT 1
3533	/** Bit 1 - SSE - 128-bit SSE state. */
3534	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3535	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3536	#define XSAVE_C_YMM_BIT 2
3537	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3538	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3539	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3540	#define XSAVE_C_BNDREGS_BIT 3
3541	/** Bit 3 - BNDREGS - MPX bound register state. */
3542	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3543	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3544	#define XSAVE_C_BNDCSR_BIT 4
3545	/** Bit 4 - BNDCSR - MPX bound config and status state. */
3546	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3547	/** Bit 5 - Opmask - opmask state (bit number). */
3548	#define XSAVE_C_OPMASK_BIT 5
3549	/** Bit 5 - Opmask - opmask state. */
3550	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3551	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3552	#define XSAVE_C_ZMM_HI256_BIT 6
3553	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3554	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3555	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3556	#define XSAVE_C_ZMM_16HI_BIT 7
3557	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3558	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3559	/** Bit 9 - PKRU - Protection-key state (bit number). */
3560	#define XSAVE_C_PKRU_BIT 9
3561	/** Bit 9 - PKRU - Protection-key state. */
3562	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3563	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3564	#define XSAVE_C_LWP_BIT 62
3565	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3566	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3567	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3568	#define XSAVE_C_X_BIT 63
3569	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3570	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3571	/** @} */
3572
3573
3574
3575	/** @name Selector Descriptor
3576	* @{
3577	*/
3578
3579	#ifndef VBOX_FOR_DTRACE_LIB
3580	/**
3581	* Descriptor attributes (as seen by VT-x).
3582	*/
3583	typedef struct X86DESCATTRBITS
3584	{
3585	/** 00 - Segment Type. */
3586	unsigned u4Type : 4;
3587	/** 04 - Descriptor Type. System(=0) or code/data selector */
3588	unsigned u1DescType : 1;
3589	/** 05 - Descriptor Privilege level. */
3590	unsigned u2Dpl : 2;
3591	/** 07 - Flags selector present(=1) or not. */
3592	unsigned u1Present : 1;
3593	/** 08 - Segment limit 16-19. */
3594	unsigned u4LimitHigh : 4;
3595	/** 0c - Available for system software. */
3596	unsigned u1Available : 1;
3597	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3598	unsigned u1Long : 1;
3599	/** 0e - This flags meaning depends on the segment type. Try make sense out
3600	* of the intel manual yourself. */
3601	unsigned u1DefBig : 1;
3602	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
3603	* clear byte. */
3604	unsigned u1Granularity : 1;
3605	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3606	unsigned u1Unusable : 1;
3607	} X86DESCATTRBITS;
3608	#endif /* !VBOX_FOR_DTRACE_LIB */
3609
3610	/** @name X86DESCATTR masks
3611	* @{ */
3612	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3613	#define X86DESCATTR_DT UINT32_C(0x00000010)
3614	#define X86DESCATTR_DPL UINT32_C(0x00000060)
3615	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
3616	#define X86DESCATTR_P UINT32_C(0x00000080)
3617	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3618	#define X86DESCATTR_AVL UINT32_C(0x00001000)
3619	#define X86DESCATTR_L UINT32_C(0x00002000)
3620	#define X86DESCATTR_D UINT32_C(0x00004000)
3621	#define X86DESCATTR_G UINT32_C(0x00008000)
3622	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3623	/** @} */
3624
3625	#pragma pack(1)
3626	typedef union X86DESCATTR
3627	{
3628	/** Unsigned integer view. */
3629	uint32_t u;
3630	#ifndef VBOX_FOR_DTRACE_LIB
3631	/** Normal view. */
3632	X86DESCATTRBITS n;
3633	#endif
3634	} X86DESCATTR;
3635	#pragma pack()
3636	/** Pointer to descriptor attributes. */
3637	typedef X86DESCATTR *PX86DESCATTR;
3638	/** Pointer to const descriptor attributes. */
3639	typedef const X86DESCATTR *PCX86DESCATTR;
3640
3641	#ifndef VBOX_FOR_DTRACE_LIB
3642
3643	/**
3644	* Generic descriptor table entry
3645	*/
3646	#pragma pack(1)
3647	typedef struct X86DESCGENERIC
3648	{
3649	/** 00 - Limit - Low word. */
3650	unsigned u16LimitLow : 16;
3651	/** 10 - Base address - low word.
3652	* Don't try set this to 24 because MSC is doing stupid things then. */
3653	unsigned u16BaseLow : 16;
3654	/** 20 - Base address - first 8 bits of high word. */
3655	unsigned u8BaseHigh1 : 8;
3656	/** 28 - Segment Type. */
3657	unsigned u4Type : 4;
3658	/** 2c - Descriptor Type. System(=0) or code/data selector */
3659	unsigned u1DescType : 1;
3660	/** 2d - Descriptor Privilege level. */
3661	unsigned u2Dpl : 2;
3662	/** 2f - Flags selector present(=1) or not. */
3663	unsigned u1Present : 1;
3664	/** 30 - Segment limit 16-19. */
3665	unsigned u4LimitHigh : 4;
3666	/** 34 - Available for system software. */
3667	unsigned u1Available : 1;
3668	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3669	unsigned u1Long : 1;
3670	/** 36 - This flags meaning depends on the segment type. Try make sense out
3671	* of the intel manual yourself. */
3672	unsigned u1DefBig : 1;
3673	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
3674	* clear byte. */
3675	unsigned u1Granularity : 1;
3676	/** 38 - Base address - highest 8 bits. */
3677	unsigned u8BaseHigh2 : 8;
3678	} X86DESCGENERIC;
3679	#pragma pack()
3680	/** Pointer to a generic descriptor entry. */
3681	typedef X86DESCGENERIC *PX86DESCGENERIC;
3682	/** Pointer to a const generic descriptor entry. */
3683	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3684
3685	/** @name Bit offsets of X86DESCGENERIC members.
3686	* @{*/
3687	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
3688	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
3689	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
3690	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
3691	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
3692	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
3693	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
3694	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
3695	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
3696	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
3697	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
3698	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
3699	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
3700	/** @} */
3701
3702
3703	/** @name LAR mask
3704	* @{ */
3705	#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3706	#define X86LAR_F_DT UINT16_C( 0x1000)
3707	#define X86LAR_F_DPL UINT16_C( 0x6000)
3708	#define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
3709	#define X86LAR_F_P UINT16_C( 0x8000)
3710	#define X86LAR_F_AVL UINT32_C(0x00100000)
3711	#define X86LAR_F_L UINT32_C(0x00200000)
3712	#define X86LAR_F_D UINT32_C(0x00400000)
3713	#define X86LAR_F_G UINT32_C(0x00800000)
3714	/** @} */
3715
3716
3717	/**
3718	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3719	*/
3720	typedef struct X86DESCGATE
3721	{
3722	/** 00 - Target code segment offset - Low word.
3723	* Ignored if task-gate. */
3724	unsigned u16OffsetLow : 16;
3725	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3726	* TSS selector if task-gate. */
3727	unsigned u16Sel : 16;
3728	/** 20 - Number of parameters for a call-gate.
3729	* Ignored if interrupt-, trap- or task-gate. */
3730	unsigned u5ParmCount : 5;
3731	/** 25 - Reserved / ignored. */
3732	unsigned u3Reserved : 3;
3733	/** 28 - Segment Type. */
3734	unsigned u4Type : 4;
3735	/** 2c - Descriptor Type (0 = system). */
3736	unsigned u1DescType : 1;
3737	/** 2d - Descriptor Privilege level. */
3738	unsigned u2Dpl : 2;
3739	/** 2f - Flags selector present(=1) or not. */
3740	unsigned u1Present : 1;
3741	/** 30 - Target code segment offset - High word.
3742	* Ignored if task-gate. */
3743	unsigned u16OffsetHigh : 16;
3744	} X86DESCGATE;
3745	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3746	typedef X86DESCGATE *PX86DESCGATE;
3747	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3748	typedef const X86DESCGATE *PCX86DESCGATE;
3749
3750	#endif /* VBOX_FOR_DTRACE_LIB */
3751
3752	/**
3753	* Descriptor table entry.
3754	*/
3755	#pragma pack(1)
3756	typedef union X86DESC
3757	{
3758	#ifndef VBOX_FOR_DTRACE_LIB
3759	/** Generic descriptor view. */
3760	X86DESCGENERIC Gen;
3761	/** Gate descriptor view. */
3762	X86DESCGATE Gate;
3763	#endif
3764
3765	/** 8 bit unsigned integer view. */
3766	uint8_t au8[8];
3767	/** 16 bit unsigned integer view. */
3768	uint16_t au16[4];
3769	/** 32 bit unsigned integer view. */
3770	uint32_t au32[2];
3771	/** 64 bit unsigned integer view. */
3772	uint64_t au64[1];
3773	/** Unsigned integer view. */
3774	uint64_t u;
3775	} X86DESC;
3776	#ifndef VBOX_FOR_DTRACE_LIB
3777	AssertCompileSize(X86DESC, 8);
3778	#endif
3779	#pragma pack()
3780	/** Pointer to descriptor table entry. */
3781	typedef X86DESC *PX86DESC;
3782	/** Pointer to const descriptor table entry. */
3783	typedef const X86DESC *PCX86DESC;
3784
3785	/** @def X86DESC_BASE
3786	* Return the base address of a descriptor.
3787	*/
3788	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
3789	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3790	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3791	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3792
3793	/** @def X86DESC_LIMIT
3794	* Return the limit of a descriptor.
3795	*/
3796	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
3797	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3798	\| ( (a_pDesc)->Gen.u16LimitLow ) )
3799
3800	/** @def X86DESC_LIMIT_G
3801	* Return the limit of a descriptor with the granularity bit taken into account.
3802	* @returns Selector limit (uint32_t).
3803	* @param a_pDesc Pointer to the descriptor.
3804	*/
3805	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
3806	( (a_pDesc)->Gen.u1Granularity \
3807	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
3808	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
3809	)
3810
3811	/** @def X86DESC_GET_HID_ATTR
3812	* Get the descriptor attributes for the hidden register.
3813	*/
3814	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
3815	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3816
3817	#ifndef VBOX_FOR_DTRACE_LIB
3818
3819	/**
3820	* 64 bits generic descriptor table entry
3821	* Note: most of these bits have no meaning in long mode.
3822	*/
3823	#pragma pack(1)
3824	typedef struct X86DESC64GENERIC
3825	{
3826	/** Limit - Low word - IGNORED. */
3827	uint32_t u16LimitLow : 16;
3828	/** Base address - low word. - IGNORED
3829	* Don't try set this to 24 because MSC is doing stupid things then. */
3830	uint32_t u16BaseLow : 16;
3831	/** Base address - first 8 bits of high word. - IGNORED */
3832	uint32_t u8BaseHigh1 : 8;
3833	/** Segment Type. */
3834	uint32_t u4Type : 4;
3835	/** Descriptor Type. System(=0) or code/data selector */
3836	uint32_t u1DescType : 1;
3837	/** Descriptor Privilege level. */
3838	uint32_t u2Dpl : 2;
3839	/** Flags selector present(=1) or not. */
3840	uint32_t u1Present : 1;
3841	/** Segment limit 16-19. - IGNORED */
3842	uint32_t u4LimitHigh : 4;
3843	/** Available for system software. - IGNORED */
3844	uint32_t u1Available : 1;
3845	/** Long mode flag. */
3846	uint32_t u1Long : 1;
3847	/** This flags meaning depends on the segment type. Try make sense out
3848	* of the intel manual yourself. */
3849	uint32_t u1DefBig : 1;
3850	/** Granularity of the limit. If set 4KB granularity is used, if
3851	* clear byte. - IGNORED */
3852	uint32_t u1Granularity : 1;
3853	/** Base address - highest 8 bits. - IGNORED */
3854	uint32_t u8BaseHigh2 : 8;
3855	/** Base address - bits 63-32. */
3856	uint32_t u32BaseHigh3 : 32;
3857	uint32_t u8Reserved : 8;
3858	uint32_t u5Zeros : 5;
3859	uint32_t u19Reserved : 19;
3860	} X86DESC64GENERIC;
3861	#pragma pack()
3862	/** Pointer to a generic descriptor entry. */
3863	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3864	/** Pointer to a const generic descriptor entry. */
3865	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3866
3867	/**
3868	* System descriptor table entry (64 bits)
3869	*
3870	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3871	*/
3872	#pragma pack(1)
3873	typedef struct X86DESC64SYSTEM
3874	{
3875	/** Limit - Low word. */
3876	uint32_t u16LimitLow : 16;
3877	/** Base address - low word.
3878	* Don't try set this to 24 because MSC is doing stupid things then. */
3879	uint32_t u16BaseLow : 16;
3880	/** Base address - first 8 bits of high word. */
3881	uint32_t u8BaseHigh1 : 8;
3882	/** Segment Type. */
3883	uint32_t u4Type : 4;
3884	/** Descriptor Type. System(=0) or code/data selector */
3885	uint32_t u1DescType : 1;
3886	/** Descriptor Privilege level. */
3887	uint32_t u2Dpl : 2;
3888	/** Flags selector present(=1) or not. */
3889	uint32_t u1Present : 1;
3890	/** Segment limit 16-19. */
3891	uint32_t u4LimitHigh : 4;
3892	/** Available for system software. */
3893	uint32_t u1Available : 1;
3894	/** Reserved - 0. */
3895	uint32_t u1Reserved : 1;
3896	/** This flags meaning depends on the segment type. Try make sense out
3897	* of the intel manual yourself. */
3898	uint32_t u1DefBig : 1;
3899	/** Granularity of the limit. If set 4KB granularity is used, if
3900	* clear byte. */
3901	uint32_t u1Granularity : 1;
3902	/** Base address - bits 31-24. */
3903	uint32_t u8BaseHigh2 : 8;
3904	/** Base address - bits 63-32. */
3905	uint32_t u32BaseHigh3 : 32;
3906	uint32_t u8Reserved : 8;
3907	uint32_t u5Zeros : 5;
3908	uint32_t u19Reserved : 19;
3909	} X86DESC64SYSTEM;
3910	#pragma pack()
3911	/** Pointer to a system descriptor entry. */
3912	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
3913	/** Pointer to a const system descriptor entry. */
3914	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
3915
3916	/**
3917	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
3918	*/
3919	typedef struct X86DESC64GATE
3920	{
3921	/** Target code segment offset - Low word. */
3922	uint32_t u16OffsetLow : 16;
3923	/** Target code segment selector. */
3924	uint32_t u16Sel : 16;
3925	/** Interrupt stack table for interrupt- and trap-gates.
3926	* Ignored by call-gates. */
3927	uint32_t u3IST : 3;
3928	/** Reserved / ignored. */
3929	uint32_t u5Reserved : 5;
3930	/** Segment Type. */
3931	uint32_t u4Type : 4;
3932	/** Descriptor Type (0 = system). */
3933	uint32_t u1DescType : 1;
3934	/** Descriptor Privilege level. */
3935	uint32_t u2Dpl : 2;
3936	/** Flags selector present(=1) or not. */
3937	uint32_t u1Present : 1;
3938	/** Target code segment offset - High word.
3939	* Ignored if task-gate. */
3940	uint32_t u16OffsetHigh : 16;
3941	/** Target code segment offset - Top dword.
3942	* Ignored if task-gate. */
3943	uint32_t u32OffsetTop : 32;
3944	/** Reserved / ignored / must be zero.
3945	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
3946	uint32_t u32Reserved : 32;
3947	} X86DESC64GATE;
3948	AssertCompileSize(X86DESC64GATE, 16);
3949	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3950	typedef X86DESC64GATE *PX86DESC64GATE;
3951	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3952	typedef const X86DESC64GATE *PCX86DESC64GATE;
3953
3954	#endif /* VBOX_FOR_DTRACE_LIB */
3955
3956	/**
3957	* Descriptor table entry.
3958	*/
3959	#pragma pack(1)
3960	typedef union X86DESC64
3961	{
3962	#ifndef VBOX_FOR_DTRACE_LIB
3963	/** Generic descriptor view. */
3964	X86DESC64GENERIC Gen;
3965	/** System descriptor view. */
3966	X86DESC64SYSTEM System;
3967	/** Gate descriptor view. */
3968	X86DESC64GATE Gate;
3969	#endif
3970
3971	/** 8 bit unsigned integer view. */
3972	uint8_t au8[16];
3973	/** 16 bit unsigned integer view. */
3974	uint16_t au16[8];
3975	/** 32 bit unsigned integer view. */
3976	uint32_t au32[4];
3977	/** 64 bit unsigned integer view. */
3978	uint64_t au64[2];
3979	} X86DESC64;
3980	#ifndef VBOX_FOR_DTRACE_LIB
3981	AssertCompileSize(X86DESC64, 16);
3982	#endif
3983	#pragma pack()
3984	/** Pointer to descriptor table entry. */
3985	typedef X86DESC64 *PX86DESC64;
3986	/** Pointer to const descriptor table entry. */
3987	typedef const X86DESC64 *PCX86DESC64;
3988
3989	/** @def X86DESC64_BASE
3990	* Return the base of a 64-bit descriptor.
3991	*/
3992	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
3993	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
3994	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3995	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3996	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3997
3998
3999
4000	/** @name Host system descriptor table entry - Use with care!
4001	* @{ */
4002	/** Host system descriptor table entry. */
4003	#if HC_ARCH_BITS == 64
4004	typedef X86DESC64 X86DESCHC;
4005	#else
4006	typedef X86DESC X86DESCHC;
4007	#endif
4008	/** Pointer to a host system descriptor table entry. */
4009	#if HC_ARCH_BITS == 64
4010	typedef PX86DESC64 PX86DESCHC;
4011	#else
4012	typedef PX86DESC PX86DESCHC;
4013	#endif
4014	/** Pointer to a const host system descriptor table entry. */
4015	#if HC_ARCH_BITS == 64
4016	typedef PCX86DESC64 PCX86DESCHC;
4017	#else
4018	typedef PCX86DESC PCX86DESCHC;
4019	#endif
4020	/** @} */
4021
4022
4023	/** @name Selector Descriptor Types.
4024	* @{
4025	*/
4026
4027	/** @name Non-System Selector Types.
4028	* @{ */
4029	/** Code(=set)/Data(=clear) bit. */
4030	#define X86_SEL_TYPE_CODE 8
4031	/** Memory(=set)/System(=clear) bit. */
4032	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
4033	/** Accessed bit. */
4034	#define X86_SEL_TYPE_ACCESSED 1
4035	/** Expand down bit (for data selectors only). */
4036	#define X86_SEL_TYPE_DOWN 4
4037	/** Conforming bit (for code selectors only). */
4038	#define X86_SEL_TYPE_CONF 4
4039	/** Write bit (for data selectors only). */
4040	#define X86_SEL_TYPE_WRITE 2
4041	/** Read bit (for code selectors only). */
4042	#define X86_SEL_TYPE_READ 2
4043	/** The bit number of the code segment read bit (relative to u4Type). */
4044	#define X86_SEL_TYPE_READ_BIT 1
4045
4046	/** Read only selector type. */
4047	#define X86_SEL_TYPE_RO 0
4048	/** Accessed read only selector type. */
4049	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
4050	/** Read write selector type. */
4051	#define X86_SEL_TYPE_RW 2
4052	/** Accessed read write selector type. */
4053	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
4054	/** Expand down read only selector type. */
4055	#define X86_SEL_TYPE_RO_DOWN 4
4056	/** Accessed expand down read only selector type. */
4057	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
4058	/** Expand down read write selector type. */
4059	#define X86_SEL_TYPE_RW_DOWN 6
4060	/** Accessed expand down read write selector type. */
4061	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
4062	/** Execute only selector type. */
4063	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
4064	/** Accessed execute only selector type. */
4065	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4066	/** Execute and read selector type. */
4067	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
4068	/** Accessed execute and read selector type. */
4069	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4070	/** Conforming execute only selector type. */
4071	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
4072	/** Accessed Conforming execute only selector type. */
4073	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4074	/** Conforming execute and write selector type. */
4075	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
4076	/** Accessed Conforming execute and write selector type. */
4077	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4078	/** @} */
4079
4080
4081	/** @name System Selector Types.
4082	* @{ */
4083	/** The TSS busy bit mask. */
4084	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4085
4086	/** Undefined system selector type. */
4087	#define X86_SEL_TYPE_SYS_UNDEFINED 0
4088	/** 286 TSS selector. */
4089	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4090	/** LDT selector. */
4091	#define X86_SEL_TYPE_SYS_LDT 2
4092	/** 286 TSS selector - Busy. */
4093	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4094	/** 286 Callgate selector. */
4095	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4096	/** Taskgate selector. */
4097	#define X86_SEL_TYPE_SYS_TASK_GATE 5
4098	/** 286 Interrupt gate selector. */
4099	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4100	/** 286 Trapgate selector. */
4101	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4102	/** Undefined system selector. */
4103	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4104	/** 386 TSS selector. */
4105	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4106	/** Undefined system selector. */
4107	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4108	/** 386 TSS selector - Busy. */
4109	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4110	/** 386 Callgate selector. */
4111	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4112	/** Undefined system selector. */
4113	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4114	/** 386 Interruptgate selector. */
4115	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4116	/** 386 Trapgate selector. */
4117	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4118	/** @} */
4119
4120	/** @name AMD64 System Selector Types.
4121	* @{ */
4122	/** LDT selector. */
4123	#define AMD64_SEL_TYPE_SYS_LDT 2
4124	/** TSS selector - Busy. */
4125	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4126	/** TSS selector - Busy. */
4127	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4128	/** Callgate selector. */
4129	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4130	/** Interruptgate selector. */
4131	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4132	/** Trapgate selector. */
4133	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4134	/** @} */
4135
4136	/** @} */
4137
4138
4139	/** @name Descriptor Table Entry Flag Masks.
4140	* These are for the 2nd 32-bit word of a descriptor.
4141	* @{ */
4142	/** Bits 8-11 - TYPE - Descriptor type mask. */
4143	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
4144	/** Bit 12 - S - System (=0) or Code/Data (=1). */
4145	#define X86_DESC_S RT_BIT_32(12)
4146	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4147	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
4148	/** Bit 15 - P - Present. */
4149	#define X86_DESC_P RT_BIT_32(15)
4150	/** Bit 20 - AVL - Available for system software. */
4151	#define X86_DESC_AVL RT_BIT_32(20)
4152	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4153	#define X86_DESC_DB RT_BIT_32(22)
4154	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4155	* used, if clear byte. */
4156	#define X86_DESC_G RT_BIT_32(23)
4157	/** @} */
4158
4159	/** @} */
4160
4161
4162	/** @name Task Segments.
4163	* @{
4164	*/
4165
4166	/**
4167	* The minimum TSS descriptor limit for 286 tasks.
4168	*/
4169	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4170
4171	/**
4172	* The minimum TSS descriptor segment limit for 386 tasks.
4173	*/
4174	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4175
4176	/**
4177	* 16-bit Task Segment (TSS).
4178	*/
4179	#pragma pack(1)
4180	typedef struct X86TSS16
4181	{
4182	/** Back link to previous task. (static) */
4183	RTSEL selPrev;
4184	/** Ring-0 stack pointer. (static) */
4185	uint16_t sp0;
4186	/** Ring-0 stack segment. (static) */
4187	RTSEL ss0;
4188	/** Ring-1 stack pointer. (static) */
4189	uint16_t sp1;
4190	/** Ring-1 stack segment. (static) */
4191	RTSEL ss1;
4192	/** Ring-2 stack pointer. (static) */
4193	uint16_t sp2;
4194	/** Ring-2 stack segment. (static) */
4195	RTSEL ss2;
4196	/** IP before task switch. */
4197	uint16_t ip;
4198	/** FLAGS before task switch. */
4199	uint16_t flags;
4200	/** AX before task switch. */
4201	uint16_t ax;
4202	/** CX before task switch. */
4203	uint16_t cx;
4204	/** DX before task switch. */
4205	uint16_t dx;
4206	/** BX before task switch. */
4207	uint16_t bx;
4208	/** SP before task switch. */
4209	uint16_t sp;
4210	/** BP before task switch. */
4211	uint16_t bp;
4212	/** SI before task switch. */
4213	uint16_t si;
4214	/** DI before task switch. */
4215	uint16_t di;
4216	/** ES before task switch. */
4217	RTSEL es;
4218	/** CS before task switch. */
4219	RTSEL cs;
4220	/** SS before task switch. */
4221	RTSEL ss;
4222	/** DS before task switch. */
4223	RTSEL ds;
4224	/** LDTR before task switch. */
4225	RTSEL selLdt;
4226	} X86TSS16;
4227	#ifndef VBOX_FOR_DTRACE_LIB
4228	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4229	#endif
4230	#pragma pack()
4231	/** Pointer to a 16-bit task segment. */
4232	typedef X86TSS16 *PX86TSS16;
4233	/** Pointer to a const 16-bit task segment. */
4234	typedef const X86TSS16 *PCX86TSS16;
4235
4236
4237	/**
4238	* 32-bit Task Segment (TSS).
4239	*/
4240	#pragma pack(1)
4241	typedef struct X86TSS32
4242	{
4243	/** Back link to previous task. (static) */
4244	RTSEL selPrev;
4245	uint16_t padding1;
4246	/** Ring-0 stack pointer. (static) */
4247	uint32_t esp0;
4248	/** Ring-0 stack segment. (static) */
4249	RTSEL ss0;
4250	uint16_t padding_ss0;
4251	/** Ring-1 stack pointer. (static) */
4252	uint32_t esp1;
4253	/** Ring-1 stack segment. (static) */
4254	RTSEL ss1;
4255	uint16_t padding_ss1;
4256	/** Ring-2 stack pointer. (static) */
4257	uint32_t esp2;
4258	/** Ring-2 stack segment. (static) */
4259	RTSEL ss2;
4260	uint16_t padding_ss2;
4261	/** Page directory for the task. (static) */
4262	uint32_t cr3;
4263	/** EIP before task switch. */
4264	uint32_t eip;
4265	/** EFLAGS before task switch. */
4266	uint32_t eflags;
4267	/** EAX before task switch. */
4268	uint32_t eax;
4269	/** ECX before task switch. */
4270	uint32_t ecx;
4271	/** EDX before task switch. */
4272	uint32_t edx;
4273	/** EBX before task switch. */
4274	uint32_t ebx;
4275	/** ESP before task switch. */
4276	uint32_t esp;
4277	/** EBP before task switch. */
4278	uint32_t ebp;
4279	/** ESI before task switch. */
4280	uint32_t esi;
4281	/** EDI before task switch. */
4282	uint32_t edi;
4283	/** ES before task switch. */
4284	RTSEL es;
4285	uint16_t padding_es;
4286	/** CS before task switch. */
4287	RTSEL cs;
4288	uint16_t padding_cs;
4289	/** SS before task switch. */
4290	RTSEL ss;
4291	uint16_t padding_ss;
4292	/** DS before task switch. */
4293	RTSEL ds;
4294	uint16_t padding_ds;
4295	/** FS before task switch. */
4296	RTSEL fs;
4297	uint16_t padding_fs;
4298	/** GS before task switch. */
4299	RTSEL gs;
4300	uint16_t padding_gs;
4301	/** LDTR before task switch. */
4302	RTSEL selLdt;
4303	uint16_t padding_ldt;
4304	/** Debug trap flag */
4305	uint16_t fDebugTrap;
4306	/** Offset relative to the TSS of the start of the I/O Bitmap
4307	* and the end of the interrupt redirection bitmap. */
4308	uint16_t offIoBitmap;
4309	} X86TSS32;
4310	#pragma pack()
4311	/** Pointer to task segment. */
4312	typedef X86TSS32 *PX86TSS32;
4313	/** Pointer to const task segment. */
4314	typedef const X86TSS32 *PCX86TSS32;
4315	#ifndef VBOX_FOR_DTRACE_LIB
4316	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4317	AssertCompileMemberOffset(X86TSS32, cr3, 28);
4318	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4319	#endif
4320
4321	/**
4322	* 64-bit Task segment.
4323	*/
4324	#pragma pack(1)
4325	typedef struct X86TSS64
4326	{
4327	/** Reserved. */
4328	uint32_t u32Reserved;
4329	/** Ring-0 stack pointer. (static) */
4330	uint64_t rsp0;
4331	/** Ring-1 stack pointer. (static) */
4332	uint64_t rsp1;
4333	/** Ring-2 stack pointer. (static) */
4334	uint64_t rsp2;
4335	/** Reserved. */
4336	uint32_t u32Reserved2[2];
4337	/* IST */
4338	uint64_t ist1;
4339	uint64_t ist2;
4340	uint64_t ist3;
4341	uint64_t ist4;
4342	uint64_t ist5;
4343	uint64_t ist6;
4344	uint64_t ist7;
4345	/* Reserved. */
4346	uint16_t u16Reserved[5];
4347	/** Offset relative to the TSS of the start of the I/O Bitmap
4348	* and the end of the interrupt redirection bitmap. */
4349	uint16_t offIoBitmap;
4350	} X86TSS64;
4351	#pragma pack()
4352	/** Pointer to a 64-bit task segment. */
4353	typedef X86TSS64 *PX86TSS64;
4354	/** Pointer to a const 64-bit task segment. */
4355	typedef const X86TSS64 *PCX86TSS64;
4356	#ifndef VBOX_FOR_DTRACE_LIB
4357	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4358	#endif
4359
4360	/** @} */
4361
4362
4363	/** @name Selectors.
4364	* @{
4365	*/
4366
4367	/**
4368	* The shift used to convert a selector from and to index an index (C).
4369	*/
4370	#define X86_SEL_SHIFT 3
4371
4372	/**
4373	* The mask used to mask off the table indicator and RPL of an selector.
4374	*/
4375	#define X86_SEL_MASK 0xfff8U
4376
4377	/**
4378	* The mask used to mask off the RPL of an selector.
4379	* This is suitable for checking for NULL selectors.
4380	*/
4381	#define X86_SEL_MASK_OFF_RPL 0xfffcU
4382
4383	/**
4384	* The bit indicating that a selector is in the LDT and not in the GDT.
4385	*/
4386	#define X86_SEL_LDT 0x0004U
4387
4388	/**
4389	* The bit mask for getting the RPL of a selector.
4390	*/
4391	#define X86_SEL_RPL 0x0003U
4392
4393	/**
4394	* The mask covering both RPL and LDT.
4395	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4396	* checks.
4397	*/
4398	#define X86_SEL_RPL_LDT 0x0007U
4399
4400	/** @} */
4401
4402
4403	/**
4404	* x86 Exceptions/Faults/Traps.
4405	*/
4406	typedef enum X86XCPT
4407	{
4408	/** \#DE - Divide error. */
4409	X86_XCPT_DE = 0x00,
4410	/** \#DB - Debug event (single step, DRx, ..) */
4411	X86_XCPT_DB = 0x01,
4412	/** NMI - Non-Maskable Interrupt */
4413	X86_XCPT_NMI = 0x02,
4414	/** \#BP - Breakpoint (INT3). */
4415	X86_XCPT_BP = 0x03,
4416	/** \#OF - Overflow (INTO). */
4417	X86_XCPT_OF = 0x04,
4418	/** \#BR - Bound range exceeded (BOUND). */
4419	X86_XCPT_BR = 0x05,
4420	/** \#UD - Undefined opcode. */
4421	X86_XCPT_UD = 0x06,
4422	/** \#NM - Device not available (math coprocessor device). */
4423	X86_XCPT_NM = 0x07,
4424	/** \#DF - Double fault. */
4425	X86_XCPT_DF = 0x08,
4426	/** ??? - Coprocessor segment overrun (obsolete). */
4427	X86_XCPT_CO_SEG_OVERRUN = 0x09,
4428	/** \#TS - Taskswitch (TSS). */
4429	X86_XCPT_TS = 0x0a,
4430	/** \#NP - Segment no present. */
4431	X86_XCPT_NP = 0x0b,
4432	/** \#SS - Stack segment fault. */
4433	X86_XCPT_SS = 0x0c,
4434	/** \#GP - General protection fault. */
4435	X86_XCPT_GP = 0x0d,
4436	/** \#PF - Page fault. */
4437	X86_XCPT_PF = 0x0e,
4438	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4439	/** \#MF - Math fault (FPU). */
4440	X86_XCPT_MF = 0x10,
4441	/** \#AC - Alignment check. */
4442	X86_XCPT_AC = 0x11,
4443	/** \#MC - Machine check. */
4444	X86_XCPT_MC = 0x12,
4445	/** \#XF - SIMD Floating-Point Exception. */
4446	X86_XCPT_XF = 0x13,
4447	/** \#VE - Virtualization Exception (Intel only). */
4448	X86_XCPT_VE = 0x14,
4449	/** \#CP - Control Protection Exception (Intel only). */
4450	X86_XCPT_CP = 0x15,
4451	/** \#VC - VMM Communication Exception (AMD only). */
4452	X86_XCPT_VC = 0x1d,
4453	/** \#SX - Security Exception (AMD only). */
4454	X86_XCPT_SX = 0x1e
4455	} X86XCPT;
4456	/** Pointer to a x86 exception code. */
4457	typedef X86XCPT *PX86XCPT;
4458	/** Pointer to a const x86 exception code. */
4459	typedef const X86XCPT *PCX86XCPT;
4460	/** The last valid (currently reserved) exception value. */
4461	#define X86_XCPT_LAST 0x1f
4462
4463
4464	/** @name Trap Error Codes
4465	* @{
4466	*/
4467	/** External indicator. */
4468	#define X86_TRAP_ERR_EXTERNAL 1
4469	/** IDT indicator. */
4470	#define X86_TRAP_ERR_IDT 2
4471	/** Descriptor table indicator - If set LDT, if clear GDT. */
4472	#define X86_TRAP_ERR_TI 4
4473	/** Mask for getting the selector. */
4474	#define X86_TRAP_ERR_SEL_MASK 0xfff8
4475	/** Shift for getting the selector table index (C type index). */
4476	#define X86_TRAP_ERR_SEL_SHIFT 3
4477	/** @} */
4478
4479
4480	/** @name \#PF Trap Error Codes
4481	* @{
4482	*/
4483	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4484	#define X86_TRAP_PF_P RT_BIT_32(0)
4485	/** Bit 1 - R/W - Read (clear) or write (set) access. */
4486	#define X86_TRAP_PF_RW RT_BIT_32(1)
4487	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4488	#define X86_TRAP_PF_US RT_BIT_32(2)
4489	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4490	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4491	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4492	#define X86_TRAP_PF_ID RT_BIT_32(4)
4493	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4494	#define X86_TRAP_PF_PK RT_BIT_32(5)
4495	/** @} */
4496
4497	#pragma pack(1)
4498	/**
4499	* 16-bit IDTR.
4500	*/
4501	typedef struct X86IDTR16
4502	{
4503	/** Offset. */
4504	uint16_t offSel;
4505	/** Selector. */
4506	uint16_t uSel;
4507	} X86IDTR16, *PX86IDTR16;
4508	#pragma pack()
4509
4510	#pragma pack(1)
4511	/**
4512	* 32-bit IDTR/GDTR.
4513	*/
4514	typedef struct X86XDTR32
4515	{
4516	/** Size of the descriptor table. */
4517	uint16_t cb;
4518	/** Address of the descriptor table. */
4519	#ifndef VBOX_FOR_DTRACE_LIB
4520	uint32_t uAddr;
4521	#else
4522	uint16_t au16Addr[2];
4523	#endif
4524	} X86XDTR32, *PX86XDTR32;
4525	#pragma pack()
4526
4527	#pragma pack(1)
4528	/**
4529	* 64-bit IDTR/GDTR.
4530	*/
4531	typedef struct X86XDTR64
4532	{
4533	/** Size of the descriptor table. */
4534	uint16_t cb;
4535	/** Address of the descriptor table. */
4536	#ifndef VBOX_FOR_DTRACE_LIB
4537	uint64_t uAddr;
4538	#else
4539	uint16_t au16Addr[4];
4540	#endif
4541	} X86XDTR64, *PX86XDTR64;
4542	#pragma pack()
4543
4544
4545	/** @name ModR/M
4546	* @{ */
4547	#define X86_MODRM_RM_MASK UINT8_C(0x07)
4548	#define X86_MODRM_REG_MASK UINT8_C(0x38)
4549	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4550	#define X86_MODRM_REG_SHIFT 3
4551	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4552	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4553	#define X86_MODRM_MOD_SHIFT 6
4554	#ifndef VBOX_FOR_DTRACE_LIB
4555	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
4556	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4557	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4558	/** @def X86_MODRM_MAKE
4559	* @param a_Mod The mod value (0..3).
4560	* @param a_Reg The register value (0..7).
4561	* @param a_RegMem The register or memory value (0..7). */
4562	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
4563	#endif
4564	/** @} */
4565
4566	/** @name SIB
4567	* @{ */
4568	#define X86_SIB_BASE_MASK UINT8_C(0x07)
4569	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4570	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4571	#define X86_SIB_INDEX_SHIFT 3
4572	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4573	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4574	#define X86_SIB_SCALE_SHIFT 6
4575	#ifndef VBOX_FOR_DTRACE_LIB
4576	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
4577	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4578	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4579	#endif
4580	/** @} */
4581
4582	/** @name General register indexes.
4583	* @{ */
4584	#define X86_GREG_xAX 0
4585	#define X86_GREG_xCX 1
4586	#define X86_GREG_xDX 2
4587	#define X86_GREG_xBX 3
4588	#define X86_GREG_xSP 4
4589	#define X86_GREG_xBP 5
4590	#define X86_GREG_xSI 6
4591	#define X86_GREG_xDI 7
4592	#define X86_GREG_x8 8
4593	#define X86_GREG_x9 9
4594	#define X86_GREG_x10 10
4595	#define X86_GREG_x11 11
4596	#define X86_GREG_x12 12
4597	#define X86_GREG_x13 13
4598	#define X86_GREG_x14 14
4599	#define X86_GREG_x15 15
4600	/** @} */
4601	/** General register count. */
4602	#define X86_GREG_COUNT 16
4603
4604	/** @name X86_SREG_XXX - Segment register indexes.
4605	* @{ */
4606	#define X86_SREG_ES 0
4607	#define X86_SREG_CS 1
4608	#define X86_SREG_SS 2
4609	#define X86_SREG_DS 3
4610	#define X86_SREG_FS 4
4611	#define X86_SREG_GS 5
4612	/** @} */
4613	/** Segment register count. */
4614	#define X86_SREG_COUNT 6
4615
4616
4617	/** @name X86_OP_XXX - Prefixes
4618	* @{ */
4619	#define X86_OP_PRF_CS UINT8_C(0x2e)
4620	#define X86_OP_PRF_SS UINT8_C(0x36)
4621	#define X86_OP_PRF_DS UINT8_C(0x3e)
4622	#define X86_OP_PRF_ES UINT8_C(0x26)
4623	#define X86_OP_PRF_FS UINT8_C(0x64)
4624	#define X86_OP_PRF_GS UINT8_C(0x65)
4625	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4626	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4627	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4628	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4629	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4630	#define X86_OP_REX_B UINT8_C(0x41)
4631	#define X86_OP_REX_X UINT8_C(0x42)
4632	#define X86_OP_REX_R UINT8_C(0x44)
4633	#define X86_OP_REX_W UINT8_C(0x48)
4634	/** @} */
4635
4636
4637	/** @} */
4638
4639	#endif /* !IPRT_INCLUDED_x86_h */
4640

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