VirtualBox

source: vbox/trunk/include/iprt/x86.h@ 95897

Last change on this file since 95897 was 94691, checked in by vboxsync, 3 years ago

iprt/x86.h: Added missing X86_EFL_*_BIT defines. bugref:9898
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1/** @file
2 * IPRT - X86 and AMD64 Structures and Definitions.
3 *
4 * @note x86.mac is generated from this file by running 'kmk incs' in the root.
5 */
6
7/*
8 * Copyright (C) 2006-2022 Oracle Corporation
9 *
10 * This file is part of VirtualBox Open Source Edition (OSE), as
11 * available from http://www.virtualbox.org. This file is free software;
12 * you can redistribute it and/or modify it under the terms of the GNU
13 * General Public License (GPL) as published by the Free Software
14 * Foundation, in version 2 as it comes in the "COPYING" file of the
15 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17 *
18 * The contents of this file may alternatively be used under the terms
19 * of the Common Development and Distribution License Version 1.0
20 * (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21 * VirtualBox OSE distribution, in which case the provisions of the
22 * CDDL are applicable instead of those of the GPL.
23 *
24 * You may elect to license modified versions of this file under the
25 * terms and conditions of either the GPL or the CDDL or both.
26 */
27
28#ifndef IPRT_INCLUDED_x86_h
29#define IPRT_INCLUDED_x86_h
30#ifndef RT_WITHOUT_PRAGMA_ONCE
31# pragma once
32#endif
33
34#ifndef VBOX_FOR_DTRACE_LIB
35# include <iprt/types.h>
36# include <iprt/assert.h>
37#else
38# pragma D depends_on library vbox-types.d
39#endif
40
41/** Workaround for Solaris sys/regset.h defining CS, DS and sys/controlregs.h
42 * defining MSR_IA32_FLUSH_CMD */
43#ifdef RT_OS_SOLARIS
44# undef CS
45# undef DS
46# undef MSR_IA32_FLUSH_CMD
47#endif
48
49/** @defgroup grp_rt_x86 x86 Types and Definitions
50 * @ingroup grp_rt
51 * @{
52 */
53
54#ifndef VBOX_FOR_DTRACE_LIB
55/**
56 * EFLAGS Bits.
57 */
58typedef struct X86EFLAGSBITS
59{
60 /** Bit 0 - CF - Carry flag - Status flag. */
61 unsigned u1CF : 1;
62 /** Bit 1 - 1 - Reserved flag. */
63 unsigned u1Reserved0 : 1;
64 /** Bit 2 - PF - Parity flag - Status flag. */
65 unsigned u1PF : 1;
66 /** Bit 3 - 0 - Reserved flag. */
67 unsigned u1Reserved1 : 1;
68 /** Bit 4 - AF - Auxiliary carry flag - Status flag. */
69 unsigned u1AF : 1;
70 /** Bit 5 - 0 - Reserved flag. */
71 unsigned u1Reserved2 : 1;
72 /** Bit 6 - ZF - Zero flag - Status flag. */
73 unsigned u1ZF : 1;
74 /** Bit 7 - SF - Signed flag - Status flag. */
75 unsigned u1SF : 1;
76 /** Bit 8 - TF - Trap flag - System flag. */
77 unsigned u1TF : 1;
78 /** Bit 9 - IF - Interrupt flag - System flag. */
79 unsigned u1IF : 1;
80 /** Bit 10 - DF - Direction flag - Control flag. */
81 unsigned u1DF : 1;
82 /** Bit 11 - OF - Overflow flag - Status flag. */
83 unsigned u1OF : 1;
84 /** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
85 unsigned u2IOPL : 2;
86 /** Bit 14 - NT - Nested task flag - System flag. */
87 unsigned u1NT : 1;
88 /** Bit 15 - 0 - Reserved flag. */
89 unsigned u1Reserved3 : 1;
90 /** Bit 16 - RF - Resume flag - System flag. */
91 unsigned u1RF : 1;
92 /** Bit 17 - VM - Virtual 8086 mode - System flag. */
93 unsigned u1VM : 1;
94 /** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
95 unsigned u1AC : 1;
96 /** Bit 19 - VIF - Virtual interrupt flag - System flag. */
97 unsigned u1VIF : 1;
98 /** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
99 unsigned u1VIP : 1;
100 /** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
101 unsigned u1ID : 1;
102 /** Bit 22-31 - 0 - Reserved flag. */
103 unsigned u10Reserved4 : 10;
104} X86EFLAGSBITS;
105/** Pointer to EFLAGS bits. */
106typedef X86EFLAGSBITS *PX86EFLAGSBITS;
107/** Pointer to const EFLAGS bits. */
108typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
109#endif /* !VBOX_FOR_DTRACE_LIB */
110
111/**
112 * EFLAGS.
113 */
114typedef union X86EFLAGS
115{
116 /** The plain unsigned view. */
117 uint32_t u;
118#ifndef VBOX_FOR_DTRACE_LIB
119 /** The bitfield view. */
120 X86EFLAGSBITS Bits;
121#endif
122 /** The 8-bit view. */
123 uint8_t au8[4];
124 /** The 16-bit view. */
125 uint16_t au16[2];
126 /** The 32-bit view. */
127 uint32_t au32[1];
128 /** The 32-bit view. */
129 uint32_t u32;
130} X86EFLAGS;
131/** Pointer to EFLAGS. */
132typedef X86EFLAGS *PX86EFLAGS;
133/** Pointer to const EFLAGS. */
134typedef const X86EFLAGS *PCX86EFLAGS;
135
136/**
137 * RFLAGS (32 upper bits are reserved).
138 */
139typedef union X86RFLAGS
140{
141 /** The plain unsigned view. */
142 uint64_t u;
143#ifndef VBOX_FOR_DTRACE_LIB
144 /** The bitfield view. */
145 X86EFLAGSBITS Bits;
146#endif
147 /** The 8-bit view. */
148 uint8_t au8[8];
149 /** The 16-bit view. */
150 uint16_t au16[4];
151 /** The 32-bit view. */
152 uint32_t au32[2];
153 /** The 64-bit view. */
154 uint64_t au64[1];
155 /** The 64-bit view. */
156 uint64_t u64;
157} X86RFLAGS;
158/** Pointer to RFLAGS. */
159typedef X86RFLAGS *PX86RFLAGS;
160/** Pointer to const RFLAGS. */
161typedef const X86RFLAGS *PCX86RFLAGS;
162
163
164/** @name EFLAGS
165 * @{
166 */
167/** Bit 0 - CF - Carry flag - Status flag. */
168#define X86_EFL_CF RT_BIT_32(0)
169#define X86_EFL_CF_BIT 0
170/** Bit 1 - Reserved, reads as 1. */
171#define X86_EFL_1 RT_BIT_32(1)
172/** Bit 2 - PF - Parity flag - Status flag. */
173#define X86_EFL_PF RT_BIT_32(2)
174#define X86_EFL_PF_BIT 2
175/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
176#define X86_EFL_AF RT_BIT_32(4)
177#define X86_EFL_AF_BIT 4
178/** Bit 6 - ZF - Zero flag - Status flag. */
179#define X86_EFL_ZF RT_BIT_32(6)
180#define X86_EFL_ZF_BIT 6
181/** Bit 7 - SF - Signed flag - Status flag. */
182#define X86_EFL_SF RT_BIT_32(7)
183#define X86_EFL_SF_BIT 7
184/** Bit 8 - TF - Trap flag - System flag. */
185#define X86_EFL_TF RT_BIT_32(8)
186#define X86_EFL_TF_BIT 8
187/** Bit 9 - IF - Interrupt flag - System flag. */
188#define X86_EFL_IF RT_BIT_32(9)
189#define X86_EFL_IF_BIT 9
190/** Bit 10 - DF - Direction flag - Control flag. */
191#define X86_EFL_DF RT_BIT_32(10)
192#define X86_EFL_DF_BIT 10
193/** Bit 11 - OF - Overflow flag - Status flag. */
194#define X86_EFL_OF RT_BIT_32(11)
195#define X86_EFL_OF_BIT 11
196/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
197#define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
198/** Bit 14 - NT - Nested task flag - System flag. */
199#define X86_EFL_NT RT_BIT_32(14)
200#define X86_EFL_NT_BIT 14
201/** Bit 16 - RF - Resume flag - System flag. */
202#define X86_EFL_RF RT_BIT_32(16)
203#define X86_EFL_RF_BIT 16
204/** Bit 17 - VM - Virtual 8086 mode - System flag. */
205#define X86_EFL_VM RT_BIT_32(17)
206#define X86_EFL_VM_BIT 17
207/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
208#define X86_EFL_AC RT_BIT_32(18)
209#define X86_EFL_AC_BIT 18
210/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
211#define X86_EFL_VIF RT_BIT_32(19)
212#define X86_EFL_VIF_BIT 19
213/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
214#define X86_EFL_VIP RT_BIT_32(20)
215#define X86_EFL_VIP_BIT 20
216/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
217#define X86_EFL_ID RT_BIT_32(21)
218#define X86_EFL_ID_BIT 21
219/** All live bits. */
220#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
221/** Read as 1 bits. */
222#define X86_EFL_RA1_MASK RT_BIT_32(1)
223/** IOPL shift. */
224#define X86_EFL_IOPL_SHIFT 12
225/** The IOPL level from the flags. */
226#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
227/** Bits restored by popf */
228#define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
229 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
230/** Bits restored by popf */
231#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
232 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
233/** The status bits commonly updated by arithmetic instructions. */
234#define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
235/** @} */
236
237
238/** CPUID Feature information - ECX.
239 * CPUID query with EAX=1.
240 */
241#ifndef VBOX_FOR_DTRACE_LIB
242typedef struct X86CPUIDFEATECX
243{
244 /** Bit 0 - SSE3 - Supports SSE3 or not. */
245 unsigned u1SSE3 : 1;
246 /** Bit 1 - PCLMULQDQ. */
247 unsigned u1PCLMULQDQ : 1;
248 /** Bit 2 - DS Area 64-bit layout. */
249 unsigned u1DTE64 : 1;
250 /** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
251 unsigned u1Monitor : 1;
252 /** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
253 unsigned u1CPLDS : 1;
254 /** Bit 5 - VMX - Virtual Machine Technology. */
255 unsigned u1VMX : 1;
256 /** Bit 6 - SMX: Safer Mode Extensions. */
257 unsigned u1SMX : 1;
258 /** Bit 7 - EST - Enh. SpeedStep Tech. */
259 unsigned u1EST : 1;
260 /** Bit 8 - TM2 - Terminal Monitor 2. */
261 unsigned u1TM2 : 1;
262 /** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
263 unsigned u1SSSE3 : 1;
264 /** Bit 10 - CNTX-ID - L1 Context ID. */
265 unsigned u1CNTXID : 1;
266 /** Bit 11 - Reserved. */
267 unsigned u1Reserved1 : 1;
268 /** Bit 12 - FMA. */
269 unsigned u1FMA : 1;
270 /** Bit 13 - CX16 - CMPXCHG16B. */
271 unsigned u1CX16 : 1;
272 /** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
273 unsigned u1TPRUpdate : 1;
274 /** Bit 15 - PDCM - Perf/Debug Capability MSR. */
275 unsigned u1PDCM : 1;
276 /** Bit 16 - Reserved. */
277 unsigned u1Reserved2 : 1;
278 /** Bit 17 - PCID - Process-context identifiers. */
279 unsigned u1PCID : 1;
280 /** Bit 18 - Direct Cache Access. */
281 unsigned u1DCA : 1;
282 /** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
283 unsigned u1SSE4_1 : 1;
284 /** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
285 unsigned u1SSE4_2 : 1;
286 /** Bit 21 - x2APIC. */
287 unsigned u1x2APIC : 1;
288 /** Bit 22 - MOVBE - Supports MOVBE. */
289 unsigned u1MOVBE : 1;
290 /** Bit 23 - POPCNT - Supports POPCNT. */
291 unsigned u1POPCNT : 1;
292 /** Bit 24 - TSC-Deadline. */
293 unsigned u1TSCDEADLINE : 1;
294 /** Bit 25 - AES. */
295 unsigned u1AES : 1;
296 /** Bit 26 - XSAVE - Supports XSAVE. */
297 unsigned u1XSAVE : 1;
298 /** Bit 27 - OSXSAVE - Supports OSXSAVE. */
299 unsigned u1OSXSAVE : 1;
300 /** Bit 28 - AVX - Supports AVX instruction extensions. */
301 unsigned u1AVX : 1;
302 /** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
303 unsigned u1F16C : 1;
304 /** Bit 30 - RDRAND - Supports RDRAND. */
305 unsigned u1RDRAND : 1;
306 /** Bit 31 - Hypervisor present (we're a guest). */
307 unsigned u1HVP : 1;
308} X86CPUIDFEATECX;
309#else /* VBOX_FOR_DTRACE_LIB */
310typedef uint32_t X86CPUIDFEATECX;
311#endif /* VBOX_FOR_DTRACE_LIB */
312/** Pointer to CPUID Feature Information - ECX. */
313typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
314/** Pointer to const CPUID Feature Information - ECX. */
315typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
316
317
318/** CPUID Feature Information - EDX.
319 * CPUID query with EAX=1.
320 */
321#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
322typedef struct X86CPUIDFEATEDX
323{
324 /** Bit 0 - FPU - x87 FPU on Chip. */
325 unsigned u1FPU : 1;
326 /** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
327 unsigned u1VME : 1;
328 /** Bit 2 - DE - Debugging extensions. */
329 unsigned u1DE : 1;
330 /** Bit 3 - PSE - Page Size Extension. */
331 unsigned u1PSE : 1;
332 /** Bit 4 - TSC - Time Stamp Counter. */
333 unsigned u1TSC : 1;
334 /** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
335 unsigned u1MSR : 1;
336 /** Bit 6 - PAE - Physical Address Extension. */
337 unsigned u1PAE : 1;
338 /** Bit 7 - MCE - Machine Check Exception. */
339 unsigned u1MCE : 1;
340 /** Bit 8 - CX8 - CMPXCHG8B instruction. */
341 unsigned u1CX8 : 1;
342 /** Bit 9 - APIC - APIC On-Chip. */
343 unsigned u1APIC : 1;
344 /** Bit 10 - Reserved. */
345 unsigned u1Reserved1 : 1;
346 /** Bit 11 - SEP - SYSENTER and SYSEXIT. */
347 unsigned u1SEP : 1;
348 /** Bit 12 - MTRR - Memory Type Range Registers. */
349 unsigned u1MTRR : 1;
350 /** Bit 13 - PGE - PTE Global Bit. */
351 unsigned u1PGE : 1;
352 /** Bit 14 - MCA - Machine Check Architecture. */
353 unsigned u1MCA : 1;
354 /** Bit 15 - CMOV - Conditional Move Instructions. */
355 unsigned u1CMOV : 1;
356 /** Bit 16 - PAT - Page Attribute Table. */
357 unsigned u1PAT : 1;
358 /** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
359 unsigned u1PSE36 : 1;
360 /** Bit 18 - PSN - Processor Serial Number. */
361 unsigned u1PSN : 1;
362 /** Bit 19 - CLFSH - CLFLUSH Instruction. */
363 unsigned u1CLFSH : 1;
364 /** Bit 20 - Reserved. */
365 unsigned u1Reserved2 : 1;
366 /** Bit 21 - DS - Debug Store. */
367 unsigned u1DS : 1;
368 /** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
369 unsigned u1ACPI : 1;
370 /** Bit 23 - MMX - Intel MMX 'Technology'. */
371 unsigned u1MMX : 1;
372 /** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
373 unsigned u1FXSR : 1;
374 /** Bit 25 - SSE - SSE Support. */
375 unsigned u1SSE : 1;
376 /** Bit 26 - SSE2 - SSE2 Support. */
377 unsigned u1SSE2 : 1;
378 /** Bit 27 - SS - Self Snoop. */
379 unsigned u1SS : 1;
380 /** Bit 28 - HTT - Hyper-Threading Technology. */
381 unsigned u1HTT : 1;
382 /** Bit 29 - TM - Thermal Monitor. */
383 unsigned u1TM : 1;
384 /** Bit 30 - Reserved - . */
385 unsigned u1Reserved3 : 1;
386 /** Bit 31 - PBE - Pending Break Enabled. */
387 unsigned u1PBE : 1;
388} X86CPUIDFEATEDX;
389#else /* VBOX_FOR_DTRACE_LIB */
390typedef uint32_t X86CPUIDFEATEDX;
391#endif /* VBOX_FOR_DTRACE_LIB */
392/** Pointer to CPUID Feature Information - EDX. */
393typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
394/** Pointer to const CPUID Feature Information - EDX. */
395typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
396
397/** @name CPUID Vendor information.
398 * CPUID query with EAX=0.
399 * @{
400 */
401#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
402#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
403#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
404
405#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
406#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
407#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
408
409#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
410#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
411#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
412
413#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
414#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
415#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
416
417#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
418#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
419#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
420/** @} */
421
422
423/** @name CPUID Feature information.
424 * CPUID query with EAX=1.
425 * @{
426 */
427/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
428#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
429/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
430#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
431/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
432#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
433/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
434#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
435/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
436#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
437/** ECX Bit 5 - VMX - Virtual Machine Technology. */
438#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
439/** ECX Bit 6 - SMX - Safer Mode Extensions. */
440#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
441/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
442#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
443/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
444#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
445/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
446#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
447/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
448#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
449/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
450 * See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
451#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
452/** ECX Bit 12 - FMA. */
453#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
454/** ECX Bit 13 - CX16 - CMPXCHG16B. */
455#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
456/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
457#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
458/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
459#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
460/** ECX Bit 17 - PCID - Process-context identifiers. */
461#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
462/** ECX Bit 18 - DCA - Direct Cache Access. */
463#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
464/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
465#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
466/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
467#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
468/** ECX Bit 21 - x2APIC support. */
469#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
470/** ECX Bit 22 - MOVBE instruction. */
471#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
472/** ECX Bit 23 - POPCNT instruction. */
473#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
474/** ECX Bir 24 - TSC-Deadline. */
475#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
476/** ECX Bit 25 - AES instructions. */
477#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
478/** ECX Bit 26 - XSAVE instruction. */
479#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
480/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
481#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
482/** ECX Bit 28 - AVX. */
483#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
484/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
485#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
486/** ECX Bit 30 - RDRAND instruction. */
487#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
488/** ECX Bit 31 - Hypervisor Present (software only). */
489#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
490
491
492/** Bit 0 - FPU - x87 FPU on Chip. */
493#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
494/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
495#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
496/** Bit 2 - DE - Debugging extensions. */
497#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
498/** Bit 3 - PSE - Page Size Extension. */
499#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
500#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /**< Bit number for X86_CPUID_FEATURE_EDX_PSE. */
501/** Bit 4 - TSC - Time Stamp Counter. */
502#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
503/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
504#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
505/** Bit 6 - PAE - Physical Address Extension. */
506#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
507#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /**< Bit number for X86_CPUID_FEATURE_EDX_PAE. */
508/** Bit 7 - MCE - Machine Check Exception. */
509#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
510/** Bit 8 - CX8 - CMPXCHG8B instruction. */
511#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
512/** Bit 9 - APIC - APIC On-Chip. */
513#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
514/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
515#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
516/** Bit 12 - MTRR - Memory Type Range Registers. */
517#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
518/** Bit 13 - PGE - PTE Global Bit. */
519#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
520/** Bit 14 - MCA - Machine Check Architecture. */
521#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
522/** Bit 15 - CMOV - Conditional Move Instructions. */
523#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
524/** Bit 16 - PAT - Page Attribute Table. */
525#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
526/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
527#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
528/** Bit 18 - PSN - Processor Serial Number. */
529#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
530/** Bit 19 - CLFSH - CLFLUSH Instruction. */
531#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
532/** Bit 21 - DS - Debug Store. */
533#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
534/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
535#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
536/** Bit 23 - MMX - Intel MMX Technology. */
537#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
538/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
539#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
540/** Bit 25 - SSE - SSE Support. */
541#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
542/** Bit 26 - SSE2 - SSE2 Support. */
543#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
544/** Bit 27 - SS - Self Snoop. */
545#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
546/** Bit 28 - HTT - Hyper-Threading Technology. */
547#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
548/** Bit 29 - TM - Therm. Monitor. */
549#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
550/** Bit 31 - PBE - Pending Break Enabled. */
551#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
552/** @} */
553
554/** @name CPUID mwait/monitor information.
555 * CPUID query with EAX=5.
556 * @{
557 */
558/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
559#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
560/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
561#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
562/** @} */
563
564
565/** @name CPUID Structured Extended Feature information.
566 * CPUID query with EAX=7.
567 * @{
568 */
569/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
570#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
571/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
572#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
573/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
574#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
575/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
576#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
577/** EBX Bit 4 - HLE - Hardware Lock Elision. */
578#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
579/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
580#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
581/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
582#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
583/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
584#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
585/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
586#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
587/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
588#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
589/** EBX Bit 10 - INVPCID - Supports INVPCID. */
590#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
591/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
592#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
593/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
594#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
595/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
596#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
597/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
598#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
599/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
600#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
601/** EBX Bit 16 - AVX512F - Supports AVX512F. */
602#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
603/** EBX Bit 18 - RDSEED - Supports RDSEED. */
604#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
605/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
606#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
607/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
608#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
609/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
610#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
611/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
612#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
613/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
614#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
615/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
616#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
617/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
618#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
619/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
620#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
621
622/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
623#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
624/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
625#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
626/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
627#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
628/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
629#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
630/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
631#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
632/** ECX Bit 22 - RDPID - Support pread process ID. */
633#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
634/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
635#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
636
637/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
638#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
639/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
640 * IBPB command in IA32_PRED_CMD. */
641#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
642/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
643#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
644/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
645#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
646/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
647#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
648/** EDX Bit 31 - SSBD - Supports the SSBD flag in IA32_SPEC_CTRL. */
649#define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
650
651/** @} */
652
653
654/** @name CPUID Extended Feature information.
655 * CPUID query with EAX=0x80000001.
656 * @{
657 */
658/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
659#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
660
661/** EDX Bit 11 - SYSCALL/SYSRET. */
662#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
663/** EDX Bit 20 - No-Execute/Execute-Disable. */
664#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
665/** EDX Bit 26 - 1 GB large page. */
666#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
667/** EDX Bit 27 - RDTSCP. */
668#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
669/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
670#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
671/** @}*/
672
673/** @name CPUID AMD Feature information.
674 * CPUID query with EAX=0x80000001.
675 * @{
676 */
677/** Bit 0 - FPU - x87 FPU on Chip. */
678#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
679/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
680#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
681/** Bit 2 - DE - Debugging extensions. */
682#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
683/** Bit 3 - PSE - Page Size Extension. */
684#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
685/** Bit 4 - TSC - Time Stamp Counter. */
686#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
687/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
688#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
689/** Bit 6 - PAE - Physical Address Extension. */
690#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
691/** Bit 7 - MCE - Machine Check Exception. */
692#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
693/** Bit 8 - CX8 - CMPXCHG8B instruction. */
694#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
695/** Bit 9 - APIC - APIC On-Chip. */
696#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
697/** Bit 12 - MTRR - Memory Type Range Registers. */
698#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
699/** Bit 13 - PGE - PTE Global Bit. */
700#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
701/** Bit 14 - MCA - Machine Check Architecture. */
702#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
703/** Bit 15 - CMOV - Conditional Move Instructions. */
704#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
705/** Bit 16 - PAT - Page Attribute Table. */
706#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
707/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
708#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
709/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
710#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
711/** Bit 23 - MMX - Intel MMX Technology. */
712#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
713/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
714#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
715/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
716#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
717/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
718#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
719/** Bit 31 - 3DNOW - AMD 3DNow. */
720#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
721
722/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
723#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
724/** Bit 2 - SVM - AMD VM extensions. */
725#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
726/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
727#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
728/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
729#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
730/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
731#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
732/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
733#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
734/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
735#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
736/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
737#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
738/** Bit 9 - OSVW - AMD OS visible workaround. */
739#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
740/** Bit 10 - IBS - Instruct based sampling. */
741#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
742/** Bit 11 - XOP - Extended operation support (see APM6). */
743#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
744/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
745#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
746/** Bit 13 - WDT - AMD Watchdog timer support. */
747#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
748/** Bit 15 - LWP - Lightweight profiling support. */
749#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
750/** Bit 16 - FMA4 - Four operand FMA instruction support. */
751#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
752/** Bit 19 - NodeId - Indicates support for
753 * MSR_C001_100C[NodeId,NodesPerProcessr]. */
754#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
755/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
756#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
757/** Bit 22 - TopologyExtensions - . */
758#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
759/** @} */
760
761
762/** @name CPUID AMD Feature information.
763 * CPUID query with EAX=0x80000007.
764 * @{
765 */
766/** Bit 0 - TS - Temperature Sensor. */
767#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
768/** Bit 1 - FID - Frequency ID Control. */
769#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
770/** Bit 2 - VID - Voltage ID Control. */
771#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
772/** Bit 3 - TTP - THERMTRIP. */
773#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
774/** Bit 4 - TM - Hardware Thermal Control. */
775#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
776/** Bit 5 - STC - Software Thermal Control. */
777#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
778/** Bit 6 - MC - 100 Mhz Multiplier Control. */
779#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
780/** Bit 7 - HWPSTATE - Hardware P-State Control. */
781#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
782/** Bit 8 - TSCINVAR - TSC Invariant. */
783#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
784/** Bit 9 - CPB - TSC Invariant. */
785#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
786/** Bit 10 - EffFreqRO - MPERF/APERF. */
787#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
788/** Bit 11 - PFI - Processor feedback interface (see EAX). */
789#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
790/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
791#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
792/** @} */
793
794
795/** @name CPUID AMD extended feature extensions ID (EBX).
796 * CPUID query with EAX=0x80000008.
797 * @{
798 */
799/** Bit 0 - CLZERO - Clear zero instruction. */
800#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
801/** Bit 1 - IRPerf - Instructions retired count support. */
802#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
803/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
804#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
805/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
806#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
807/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
808#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
809/* AMD pipeline length: 9 feature bits ;-) */
810/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
811#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
812/** Bit 14 - IBRS - Supports the IBRS bit in IA32_SPEC_CTRL. */
813#define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
814/** Bit 15 - STIBP - Supports the STIBP bit in IA32_SPEC_CTRL. */
815#define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
816/** Bit 16 - IBRS always on mode - IBRS should be set once during boot only. */
817#define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
818/** Bit 17 - STIBP always on mode - STIBP should be set once during boot only. */
819#define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
820/** Bit 18 - IBRS preferred - IBRS is preferred over software mitigations. */
821#define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
822/** Bit 24 - Speculative Store Bypass Disable supported in SPEC_CTL. */
823#define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
824/** Bit 25 - Speculative Store Bypass Disable supported in VIRT_SPEC_CTL. */
825#define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
826/** Bit 26 - Speculative Store Bypass Disable not required. */
827#define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
828/** @} */
829
830
831/** @name CPUID AMD SVM Feature information.
832 * CPUID query with EAX=0x8000000a.
833 * @{
834 */
835/** Bit 0 - NP - Nested Paging supported. */
836#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
837/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
838#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
839/** Bit 2 - SVML - SVM locking bit supported. */
840#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
841/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
842#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
843/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
844#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
845/** Bit 5 - VmcbClean - Support VMCB clean bits. */
846#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
847/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
848 * VMCB.TLB_Control is supported. */
849#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
850/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
851#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
852/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
853#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
854/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
855 * intercept filter cycle count threshold. */
856#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
857/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
858#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
859/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
860#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
861/** Bit 16 - VGIF - Supports virtualized GIF. */
862#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
863/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
864#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
865
866/** @} */
867
868
869/** @name CR0
870 * @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
871 * reserved flags.
872 * @{ */
873/** Bit 0 - PE - Protection Enabled */
874#define X86_CR0_PE RT_BIT_32(0)
875#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
876/** Bit 1 - MP - Monitor Coprocessor */
877#define X86_CR0_MP RT_BIT_32(1)
878#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
879/** Bit 2 - EM - Emulation. */
880#define X86_CR0_EM RT_BIT_32(2)
881#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
882/** Bit 3 - TS - Task Switch. */
883#define X86_CR0_TS RT_BIT_32(3)
884#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
885/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
886#define X86_CR0_ET RT_BIT_32(4)
887#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
888/** Bit 5 - NE - Numeric error (486+). */
889#define X86_CR0_NE RT_BIT_32(5)
890#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
891/** Bit 16 - WP - Write Protect (486+). */
892#define X86_CR0_WP RT_BIT_32(16)
893#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
894/** Bit 18 - AM - Alignment Mask (486+). */
895#define X86_CR0_AM RT_BIT_32(18)
896#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
897/** Bit 29 - NW - Not Write-though (486+). */
898#define X86_CR0_NW RT_BIT_32(29)
899#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
900/** Bit 30 - WP - Cache Disable (486+). */
901#define X86_CR0_CD RT_BIT_32(30)
902#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
903/** Bit 31 - PG - Paging. */
904#define X86_CR0_PG RT_BIT_32(31)
905#define X86_CR0_PAGING RT_BIT_32(31)
906#define X86_CR0_BIT_PG 31 /**< Bit number of X86_CR0_PG */
907/** @} */
908
909
910/** @name CR3
911 * @{ */
912/** Bit 3 - PWT - Page-level Writes Transparent. */
913#define X86_CR3_PWT RT_BIT_32(3)
914/** Bit 4 - PCD - Page-level Cache Disable. */
915#define X86_CR3_PCD RT_BIT_32(4)
916/** Bits 12-31 - - Page directory page number. */
917#define X86_CR3_PAGE_MASK (0xfffff000)
918/** Bits 5-31 - - PAE Page directory page number. */
919#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
920/** Bits 12-51 - - AMD64 Page directory page number. */
921#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
922/** Bits 12-47 - - Intel EPT Page directory page number. */
923#define X86_CR3_EPT_PAGE_MASK UINT64_C(0x0000fffffffff000)
924/** @} */
925
926
927/** @name CR4
928 * @{ */
929/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
930#define X86_CR4_VME RT_BIT_32(0)
931/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
932#define X86_CR4_PVI RT_BIT_32(1)
933/** Bit 2 - TSD - Time Stamp Disable. */
934#define X86_CR4_TSD RT_BIT_32(2)
935/** Bit 3 - DE - Debugging Extensions. */
936#define X86_CR4_DE RT_BIT_32(3)
937/** Bit 4 - PSE - Page Size Extension. */
938#define X86_CR4_PSE RT_BIT_32(4)
939/** Bit 5 - PAE - Physical Address Extension. */
940#define X86_CR4_PAE RT_BIT_32(5)
941/** Bit 6 - MCE - Machine-Check Enable. */
942#define X86_CR4_MCE RT_BIT_32(6)
943/** Bit 7 - PGE - Page Global Enable. */
944#define X86_CR4_PGE RT_BIT_32(7)
945/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
946#define X86_CR4_PCE RT_BIT_32(8)
947/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
948#define X86_CR4_OSFXSR RT_BIT_32(9)
949/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
950#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
951/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
952#define X86_CR4_UMIP RT_BIT_32(11)
953/** Bit 13 - VMXE - VMX mode is enabled. */
954#define X86_CR4_VMXE RT_BIT_32(13)
955/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
956#define X86_CR4_SMXE RT_BIT_32(14)
957/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
958#define X86_CR4_FSGSBASE RT_BIT_32(16)
959/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
960#define X86_CR4_PCIDE RT_BIT_32(17)
961/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
962 * extended states. */
963#define X86_CR4_OSXSAVE RT_BIT_32(18)
964/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
965#define X86_CR4_SMEP RT_BIT_32(20)
966/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
967#define X86_CR4_SMAP RT_BIT_32(21)
968/** Bit 22 - PKE - Protection Key Enable. */
969#define X86_CR4_PKE RT_BIT_32(22)
970/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
971#define X86_CR4_CET RT_BIT_32(23)
972/** @} */
973
974
975/** @name DR6
976 * @{ */
977/** Bit 0 - B0 - Breakpoint 0 condition detected. */
978#define X86_DR6_B0 RT_BIT_32(0)
979/** Bit 1 - B1 - Breakpoint 1 condition detected. */
980#define X86_DR6_B1 RT_BIT_32(1)
981/** Bit 2 - B2 - Breakpoint 2 condition detected. */
982#define X86_DR6_B2 RT_BIT_32(2)
983/** Bit 3 - B3 - Breakpoint 3 condition detected. */
984#define X86_DR6_B3 RT_BIT_32(3)
985/** Mask of all the Bx bits. */
986#define X86_DR6_B_MASK UINT64_C(0x0000000f)
987/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
988#define X86_DR6_BD RT_BIT_32(13)
989/** Bit 14 - BS - Single step */
990#define X86_DR6_BS RT_BIT_32(14)
991/** Bit 15 - BT - Task switch. (TSS T bit.) */
992#define X86_DR6_BT RT_BIT_32(15)
993/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
994#define X86_DR6_RTM RT_BIT_32(16)
995/** Value of DR6 after powerup/reset. */
996#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
997/** Bits which must be 1s in DR6. */
998#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
999/** Bits which must be 1s in DR6, when RTM is supported. */
1000#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
1001/** Bits which must be 0s in DR6. */
1002#define X86_DR6_RAZ_MASK RT_BIT_64(12)
1003/** Bits which must be 0s on writes to DR6. */
1004#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
1005/** @} */
1006
1007/** Get the DR6.Bx bit for a the given breakpoint. */
1008#define X86_DR6_B(iBp) RT_BIT_64(iBp)
1009
1010
1011/** @name DR7
1012 * @{ */
1013/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
1014#define X86_DR7_L0 RT_BIT_32(0)
1015/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
1016#define X86_DR7_G0 RT_BIT_32(1)
1017/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
1018#define X86_DR7_L1 RT_BIT_32(2)
1019/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
1020#define X86_DR7_G1 RT_BIT_32(3)
1021/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
1022#define X86_DR7_L2 RT_BIT_32(4)
1023/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
1024#define X86_DR7_G2 RT_BIT_32(5)
1025/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
1026#define X86_DR7_L3 RT_BIT_32(6)
1027/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
1028#define X86_DR7_G3 RT_BIT_32(7)
1029/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1030#define X86_DR7_LE RT_BIT_32(8)
1031/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1032#define X86_DR7_GE RT_BIT_32(9)
1033
1034/** L0, L1, L2, and L3. */
1035#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1036/** L0, L1, L2, and L3. */
1037#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1038
1039/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1040 * Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1041#define X86_DR7_RTM RT_BIT_32(11)
1042/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1043 * Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1044 * May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1045 * instruction is executed.
1046 * @see http://www.rcollins.org/secrets/DR7.html */
1047#define X86_DR7_ICE_IR RT_BIT_32(12)
1048/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1049 * any DR register is accessed. */
1050#define X86_DR7_GD RT_BIT_32(13)
1051/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1052 * Pentium. */
1053#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1054/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1055#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1056/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_*. */
1057#define X86_DR7_RW0_MASK (3 << 16)
1058/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_*. */
1059#define X86_DR7_LEN0_MASK (3 << 18)
1060/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_*. */
1061#define X86_DR7_RW1_MASK (3 << 20)
1062/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_*. */
1063#define X86_DR7_LEN1_MASK (3 << 22)
1064/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_*. */
1065#define X86_DR7_RW2_MASK (3 << 24)
1066/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_*. */
1067#define X86_DR7_LEN2_MASK (3 << 26)
1068/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_*. */
1069#define X86_DR7_RW3_MASK (3 << 28)
1070/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_*. */
1071#define X86_DR7_LEN3_MASK (3 << 30)
1072
1073/** Bits which reads as 1s. */
1074#define X86_DR7_RA1_MASK RT_BIT_32(10)
1075/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1076#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1077/** Bits which must be 0s when writing to DR7. */
1078#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1079
1080/** Calcs the L bit of Nth breakpoint.
1081 * @param iBp The breakpoint number [0..3].
1082 */
1083#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1084
1085/** Calcs the G bit of Nth breakpoint.
1086 * @param iBp The breakpoint number [0..3].
1087 */
1088#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1089
1090/** Calcs the L and G bits of Nth breakpoint.
1091 * @param iBp The breakpoint number [0..3].
1092 */
1093#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1094
1095/** @name Read/Write values.
1096 * @{ */
1097/** Break on instruction fetch only. */
1098#define X86_DR7_RW_EO UINT32_C(0)
1099/** Break on write only. */
1100#define X86_DR7_RW_WO UINT32_C(1)
1101/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1102#define X86_DR7_RW_IO UINT32_C(2)
1103/** Break on read or write (but not instruction fetches). */
1104#define X86_DR7_RW_RW UINT32_C(3)
1105/** @} */
1106
1107/** Shifts a X86_DR7_RW_* value to its right place.
1108 * @param iBp The breakpoint number [0..3].
1109 * @param fRw One of the X86_DR7_RW_* value.
1110 */
1111#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1112
1113/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1114 * one of the X86_DR7_RW_XXX constants).
1115 *
1116 * @returns X86_DR7_RW_XXX
1117 * @param uDR7 DR7 value
1118 * @param iBp The breakpoint number [0..3].
1119 */
1120#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1121
1122/** R/W0, R/W1, R/W2, and R/W3. */
1123#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1124
1125#ifndef VBOX_FOR_DTRACE_LIB
1126/** Checks if there are any I/O breakpoint types configured in the RW
1127 * registers. Does NOT check if these are enabled, sorry. */
1128# define X86_DR7_ANY_RW_IO(uDR7) \
1129 ( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1130 && ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1131AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1132AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1133AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1134AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1135AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1136AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1137AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1138AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1139AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1140#endif /* !VBOX_FOR_DTRACE_LIB */
1141
1142/** @name Length values.
1143 * @{ */
1144#define X86_DR7_LEN_BYTE UINT32_C(0)
1145#define X86_DR7_LEN_WORD UINT32_C(1)
1146#define X86_DR7_LEN_QWORD UINT32_C(2) /**< AMD64 long mode only. */
1147#define X86_DR7_LEN_DWORD UINT32_C(3)
1148/** @} */
1149
1150/** Shifts a X86_DR7_LEN_* value to its right place.
1151 * @param iBp The breakpoint number [0..3].
1152 * @param cb One of the X86_DR7_LEN_* values.
1153 */
1154#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1155
1156/** Fetch the breakpoint length bits from the DR7 value.
1157 * @param uDR7 DR7 value
1158 * @param iBp The breakpoint number [0..3].
1159 */
1160#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1161
1162/** Mask used to check if any breakpoints are enabled. */
1163#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1164
1165/** LEN0, LEN1, LEN2, and LEN3. */
1166#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1167/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1168#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1169
1170/** Value of DR7 after powerup/reset. */
1171#define X86_DR7_INIT_VAL 0x400
1172/** @} */
1173
1174
1175/** @name Machine Specific Registers
1176 * @{
1177 */
1178/** Machine check address register (P5). */
1179#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1180/** Machine check type register (P5). */
1181#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1182/** Time Stamp Counter. */
1183#define MSR_IA32_TSC 0x10
1184#define MSR_IA32_CESR UINT32_C(0x00000011)
1185#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1186#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1187
1188#define MSR_IA32_PLATFORM_ID 0x17
1189
1190#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1191# define MSR_IA32_APICBASE 0x1b
1192/** Local APIC enabled. */
1193# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1194/** X2APIC enabled (requires the EN bit to be set). */
1195# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1196/** The processor is the boot strap processor (BSP). */
1197# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1198/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1199 * width. */
1200# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1201/** The default physical base address of the APIC. */
1202# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1203/** Gets the physical base address from the MSR. */
1204# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1205#endif
1206
1207/** Undocumented intel MSR for reporting thread and core counts.
1208 * Judging from the XNU sources, it seems to be introduced in Nehalem. The
1209 * first 16 bits is the thread count. The next 16 bits the core count, except
1210 * on Westmere where it seems it's only the next 4 bits for some reason. */
1211#define MSR_CORE_THREAD_COUNT 0x35
1212
1213/** CPU Feature control. */
1214#define MSR_IA32_FEATURE_CONTROL 0x3A
1215/** Feature control - Lock MSR from writes (R/W0). */
1216#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1217/** Feature control - Enable VMX inside SMX operation (R/WL). */
1218#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1219/** Feature control - Enable VMX outside SMX operation (R/WL). */
1220#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1221/** Feature control - SENTER local functions enable (R/WL). */
1222#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1223#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1224#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1225#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1226#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1227#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1228#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1229/** Feature control - SENTER global enable (R/WL). */
1230#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1231/** Feature control - SGX launch control enable (R/WL). */
1232#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1233/** Feature control - SGX global enable (R/WL). */
1234#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1235/** Feature control - LMCE on (R/WL). */
1236#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1237
1238/** Per-processor TSC adjust MSR. */
1239#define MSR_IA32_TSC_ADJUST 0x3B
1240
1241/** Spectre control register.
1242 * Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1243#define MSR_IA32_SPEC_CTRL 0x48
1244/** IBRS - Indirect branch restricted speculation. */
1245#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1246/** STIBP - Single thread indirect branch predictors. */
1247#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1248/** SSBD - Speculative Store Bypass Disable. */
1249#define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2)
1250
1251/** Prediction command register.
1252 * Write only, logical processor scope, no state since write only. */
1253#define MSR_IA32_PRED_CMD 0x49
1254/** IBPB - Indirect branch prediction barrie when written as 1. */
1255#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1256
1257/** BIOS update trigger (microcode update). */
1258#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1259
1260/** BIOS update signature (microcode). */
1261#define MSR_IA32_BIOS_SIGN_ID 0x8B
1262
1263/** SMM monitor control. */
1264#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1265/** SMM control - Valid. */
1266#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1267/** SMM control - VMXOFF unblocks SMI. */
1268#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1269/** SMM control - MSEG base physical address. */
1270#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1271
1272/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1273#define MSR_IA32_SMBASE 0x9E
1274
1275/** General performance counter no. 0. */
1276#define MSR_IA32_PMC0 0xC1
1277/** General performance counter no. 1. */
1278#define MSR_IA32_PMC1 0xC2
1279/** General performance counter no. 2. */
1280#define MSR_IA32_PMC2 0xC3
1281/** General performance counter no. 3. */
1282#define MSR_IA32_PMC3 0xC4
1283/** General performance counter no. 4. */
1284#define MSR_IA32_PMC4 0xC5
1285/** General performance counter no. 5. */
1286#define MSR_IA32_PMC5 0xC6
1287/** General performance counter no. 6. */
1288#define MSR_IA32_PMC6 0xC7
1289/** General performance counter no. 7. */
1290#define MSR_IA32_PMC7 0xC8
1291
1292/** Nehalem power control. */
1293#define MSR_IA32_PLATFORM_INFO 0xCE
1294
1295/** Get FSB clock status (Intel-specific). */
1296#define MSR_IA32_FSB_CLOCK_STS 0xCD
1297
1298/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1299#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1300
1301/** C0 Maximum Frequency Clock Count */
1302#define MSR_IA32_MPERF 0xE7
1303/** C0 Actual Frequency Clock Count */
1304#define MSR_IA32_APERF 0xE8
1305
1306/** MTRR Capabilities. */
1307#define MSR_IA32_MTRR_CAP 0xFE
1308
1309/** Architecture capabilities (bugfixes). */
1310#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1311/** CPU is no subject to meltdown problems. */
1312#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1313/** CPU has better IBRS and you can leave it on all the time. */
1314#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1315/** CPU has return stack buffer (RSB) override. */
1316#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1317/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1318 * This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1319#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1320/** CPU does not suffer from MDS issues. */
1321#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
1322
1323/** Flush command register. */
1324#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1325/** Flush the level 1 data cache when this bit is written. */
1326#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1327
1328/** Cache control/info. */
1329#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1330
1331#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1332/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1333 * R0 SS == CS + 8
1334 * R3 CS == CS + 16
1335 * R3 SS == CS + 24
1336 */
1337#define MSR_IA32_SYSENTER_CS 0x174
1338/** SYSENTER_ESP - the R0 ESP. */
1339#define MSR_IA32_SYSENTER_ESP 0x175
1340/** SYSENTER_EIP - the R0 EIP. */
1341#define MSR_IA32_SYSENTER_EIP 0x176
1342#endif
1343
1344/** Machine Check Global Capabilities Register. */
1345#define MSR_IA32_MCG_CAP 0x179
1346/** Machine Check Global Status Register. */
1347#define MSR_IA32_MCG_STATUS 0x17A
1348/** Machine Check Global Control Register. */
1349#define MSR_IA32_MCG_CTRL 0x17B
1350
1351/** Page Attribute Table. */
1352#define MSR_IA32_CR_PAT 0x277
1353/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1354 * "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1355#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1356
1357/** Performance event select MSRs. (Intel only) */
1358#define MSR_IA32_PERFEVTSEL0 0x186
1359#define MSR_IA32_PERFEVTSEL1 0x187
1360#define MSR_IA32_PERFEVTSEL2 0x188
1361#define MSR_IA32_PERFEVTSEL3 0x189
1362
1363/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1364 * The 16th bit whether flex ratio is being used, in which case bits 15:8
1365 * holds a ratio that Apple takes for TSC granularity.
1366 *
1367 * @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1368#define MSR_FLEX_RATIO 0x194
1369/** Performance state value and starting with Intel core more.
1370 * Apple uses the >=core features to determine TSC granularity on older CPUs. */
1371#define MSR_IA32_PERF_STATUS 0x198
1372#define MSR_IA32_PERF_CTL 0x199
1373#define MSR_IA32_THERM_STATUS 0x19c
1374
1375/** Offcore response event select registers. */
1376#define MSR_OFFCORE_RSP_0 0x1a6
1377#define MSR_OFFCORE_RSP_1 0x1a7
1378
1379/** Enable misc. processor features (R/W). */
1380#define MSR_IA32_MISC_ENABLE 0x1A0
1381/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1382#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1383/** Automatic Thermal Control Circuit Enable (R/W). */
1384#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1385/** Performance Monitoring Available (R). */
1386#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1387/** Branch Trace Storage Unavailable (R/O). */
1388#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1389/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1390#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1391/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1392#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1393/** If MONITOR/MWAIT is supported (R/W). */
1394#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1395/** Limit CPUID Maxval to 3 leafs (R/W). */
1396#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1397/** When set to 1, xTPR messages are disabled (R/W). */
1398#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1399/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1400#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1401
1402/** Trace/Profile Resource Control (R/W) */
1403#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1404/** Last branch record. */
1405#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1406/** Branch trace flag (single step on branches). */
1407#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1408/** Performance monitoring pin control (AMD only). */
1409#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1410#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1411#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1412#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1413/** Trace message enable (Intel only). */
1414#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1415/** Branch trace store (Intel only). */
1416#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1417/** Branch trace interrupt (Intel only). */
1418#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1419/** Branch trace off in privileged code (Intel only). */
1420#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1421/** Branch trace off in user code (Intel only). */
1422#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1423/** Freeze LBR on PMI flag (Intel only). */
1424#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1425/** Freeze PERFMON on PMI flag (Intel only). */
1426#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1427/** Freeze while SMM enabled (Intel only). */
1428#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1429/** Advanced debugging of RTM regions (Intel only). */
1430#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1431/** Debug control MSR valid bits (Intel only). */
1432#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR | MSR_IA32_DEBUGCTL_BTF | MSR_IA32_DEBUGCTL_TR \
1433 | MSR_IA32_DEBUGCTL_BTS | MSR_IA32_DEBUGCTL_BTINT | MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1434 | MSR_IA32_DEBUGCTL_BTS_OFF_USER | MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1435 | MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI | MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1436 | MSR_IA32_DEBUGCTL_RTM)
1437
1438/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1439 * @{ */
1440#define MSR_P4_LASTBRANCH_0 0x1db
1441#define MSR_P4_LASTBRANCH_1 0x1dc
1442#define MSR_P4_LASTBRANCH_2 0x1dd
1443#define MSR_P4_LASTBRANCH_3 0x1de
1444
1445/** LBR Top-of-stack MSR (index to most recent record). */
1446#define MSR_P4_LASTBRANCH_TOS 0x1da
1447/** @} */
1448
1449/** @name Last branch registers for Core 2 and related Xeons.
1450 * @{ */
1451#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
1452#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
1453#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
1454#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
1455
1456#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
1457#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
1458#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
1459#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
1460
1461/** LBR Top-of-stack MSR (index to most recent record). */
1462#define MSR_CORE2_LASTBRANCH_TOS 0x1c9
1463/** @} */
1464
1465/** @name Last branch registers.
1466 * @{ */
1467#define MSR_LASTBRANCH_0_FROM_IP 0x680
1468#define MSR_LASTBRANCH_1_FROM_IP 0x681
1469#define MSR_LASTBRANCH_2_FROM_IP 0x682
1470#define MSR_LASTBRANCH_3_FROM_IP 0x683
1471#define MSR_LASTBRANCH_4_FROM_IP 0x684
1472#define MSR_LASTBRANCH_5_FROM_IP 0x685
1473#define MSR_LASTBRANCH_6_FROM_IP 0x686
1474#define MSR_LASTBRANCH_7_FROM_IP 0x687
1475#define MSR_LASTBRANCH_8_FROM_IP 0x688
1476#define MSR_LASTBRANCH_9_FROM_IP 0x689
1477#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1478#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1479#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1480#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1481#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1482#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1483#define MSR_LASTBRANCH_16_FROM_IP 0x690
1484#define MSR_LASTBRANCH_17_FROM_IP 0x691
1485#define MSR_LASTBRANCH_18_FROM_IP 0x692
1486#define MSR_LASTBRANCH_19_FROM_IP 0x693
1487#define MSR_LASTBRANCH_20_FROM_IP 0x694
1488#define MSR_LASTBRANCH_21_FROM_IP 0x695
1489#define MSR_LASTBRANCH_22_FROM_IP 0x696
1490#define MSR_LASTBRANCH_23_FROM_IP 0x697
1491#define MSR_LASTBRANCH_24_FROM_IP 0x698
1492#define MSR_LASTBRANCH_25_FROM_IP 0x699
1493#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1494#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1495#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1496#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1497#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1498#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1499
1500#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1501#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1502#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1503#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1504#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1505#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1506#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1507#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1508#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1509#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1510#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1511#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1512#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1513#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1514#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1515#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1516#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1517#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1518#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1519#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1520#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1521#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1522#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1523#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1524#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1525#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1526#define MSR_LASTBRANCH_26_TO_IP 0x6da
1527#define MSR_LASTBRANCH_27_TO_IP 0x6db
1528#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1529#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1530#define MSR_LASTBRANCH_30_TO_IP 0x6de
1531#define MSR_LASTBRANCH_31_TO_IP 0x6df
1532
1533#define MSR_LASTBRANCH_0_INFO 0xdc0
1534#define MSR_LASTBRANCH_1_INFO 0xdc1
1535#define MSR_LASTBRANCH_2_INFO 0xdc2
1536#define MSR_LASTBRANCH_3_INFO 0xdc3
1537#define MSR_LASTBRANCH_4_INFO 0xdc4
1538#define MSR_LASTBRANCH_5_INFO 0xdc5
1539#define MSR_LASTBRANCH_6_INFO 0xdc6
1540#define MSR_LASTBRANCH_7_INFO 0xdc7
1541#define MSR_LASTBRANCH_8_INFO 0xdc8
1542#define MSR_LASTBRANCH_9_INFO 0xdc9
1543#define MSR_LASTBRANCH_10_INFO 0xdca
1544#define MSR_LASTBRANCH_11_INFO 0xdcb
1545#define MSR_LASTBRANCH_12_INFO 0xdcc
1546#define MSR_LASTBRANCH_13_INFO 0xdcd
1547#define MSR_LASTBRANCH_14_INFO 0xdce
1548#define MSR_LASTBRANCH_15_INFO 0xdcf
1549#define MSR_LASTBRANCH_16_INFO 0xdd0
1550#define MSR_LASTBRANCH_17_INFO 0xdd1
1551#define MSR_LASTBRANCH_18_INFO 0xdd2
1552#define MSR_LASTBRANCH_19_INFO 0xdd3
1553#define MSR_LASTBRANCH_20_INFO 0xdd4
1554#define MSR_LASTBRANCH_21_INFO 0xdd5
1555#define MSR_LASTBRANCH_22_INFO 0xdd6
1556#define MSR_LASTBRANCH_23_INFO 0xdd7
1557#define MSR_LASTBRANCH_24_INFO 0xdd8
1558#define MSR_LASTBRANCH_25_INFO 0xdd9
1559#define MSR_LASTBRANCH_26_INFO 0xdda
1560#define MSR_LASTBRANCH_27_INFO 0xddb
1561#define MSR_LASTBRANCH_28_INFO 0xddc
1562#define MSR_LASTBRANCH_29_INFO 0xddd
1563#define MSR_LASTBRANCH_30_INFO 0xdde
1564#define MSR_LASTBRANCH_31_INFO 0xddf
1565
1566/** LBR branch tracking selection MSR. */
1567#define MSR_LASTBRANCH_SELECT 0x1c8
1568/** LBR Top-of-stack MSR (index to most recent record). */
1569#define MSR_LASTBRANCH_TOS 0x1c9
1570/** @} */
1571
1572/** @name Last event record registers.
1573 * @{ */
1574/** Last event record source IP register. */
1575#define MSR_LER_FROM_IP 0x1dd
1576/** Last event record destination IP register. */
1577#define MSR_LER_TO_IP 0x1de
1578/** @} */
1579
1580/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
1581#define MSR_IA32_TSX_CTRL 0x122
1582
1583/** Variable range MTRRs.
1584 * @{ */
1585#define MSR_IA32_MTRR_PHYSBASE0 0x200
1586#define MSR_IA32_MTRR_PHYSMASK0 0x201
1587#define MSR_IA32_MTRR_PHYSBASE1 0x202
1588#define MSR_IA32_MTRR_PHYSMASK1 0x203
1589#define MSR_IA32_MTRR_PHYSBASE2 0x204
1590#define MSR_IA32_MTRR_PHYSMASK2 0x205
1591#define MSR_IA32_MTRR_PHYSBASE3 0x206
1592#define MSR_IA32_MTRR_PHYSMASK3 0x207
1593#define MSR_IA32_MTRR_PHYSBASE4 0x208
1594#define MSR_IA32_MTRR_PHYSMASK4 0x209
1595#define MSR_IA32_MTRR_PHYSBASE5 0x20a
1596#define MSR_IA32_MTRR_PHYSMASK5 0x20b
1597#define MSR_IA32_MTRR_PHYSBASE6 0x20c
1598#define MSR_IA32_MTRR_PHYSMASK6 0x20d
1599#define MSR_IA32_MTRR_PHYSBASE7 0x20e
1600#define MSR_IA32_MTRR_PHYSMASK7 0x20f
1601#define MSR_IA32_MTRR_PHYSBASE8 0x210
1602#define MSR_IA32_MTRR_PHYSMASK8 0x211
1603#define MSR_IA32_MTRR_PHYSBASE9 0x212
1604#define MSR_IA32_MTRR_PHYSMASK9 0x213
1605/** @} */
1606
1607/** Fixed range MTRRs.
1608 * @{ */
1609#define MSR_IA32_MTRR_FIX64K_00000 0x250
1610#define MSR_IA32_MTRR_FIX16K_80000 0x258
1611#define MSR_IA32_MTRR_FIX16K_A0000 0x259
1612#define MSR_IA32_MTRR_FIX4K_C0000 0x268
1613#define MSR_IA32_MTRR_FIX4K_C8000 0x269
1614#define MSR_IA32_MTRR_FIX4K_D0000 0x26a
1615#define MSR_IA32_MTRR_FIX4K_D8000 0x26b
1616#define MSR_IA32_MTRR_FIX4K_E0000 0x26c
1617#define MSR_IA32_MTRR_FIX4K_E8000 0x26d
1618#define MSR_IA32_MTRR_FIX4K_F0000 0x26e
1619#define MSR_IA32_MTRR_FIX4K_F8000 0x26f
1620/** @} */
1621
1622/** MTRR Default Range. */
1623#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1624
1625/** Global performance counter control facilities (Intel only). */
1626#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1627#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1628#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1629
1630/** Precise Event Based sampling (Intel only). */
1631#define MSR_IA32_PEBS_ENABLE 0x3F1
1632
1633#define MSR_IA32_MC0_CTL 0x400
1634#define MSR_IA32_MC0_STATUS 0x401
1635
1636/** Basic VMX information. */
1637#define MSR_IA32_VMX_BASIC 0x480
1638/** Allowed settings for pin-based VM execution controls. */
1639#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1640/** Allowed settings for proc-based VM execution controls. */
1641#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1642/** Allowed settings for the VM-exit controls. */
1643#define MSR_IA32_VMX_EXIT_CTLS 0x483
1644/** Allowed settings for the VM-entry controls. */
1645#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1646/** Misc VMX info. */
1647#define MSR_IA32_VMX_MISC 0x485
1648/** Fixed cleared bits in CR0. */
1649#define MSR_IA32_VMX_CR0_FIXED0 0x486
1650/** Fixed set bits in CR0. */
1651#define MSR_IA32_VMX_CR0_FIXED1 0x487
1652/** Fixed cleared bits in CR4. */
1653#define MSR_IA32_VMX_CR4_FIXED0 0x488
1654/** Fixed set bits in CR4. */
1655#define MSR_IA32_VMX_CR4_FIXED1 0x489
1656/** Information for enumerating fields in the VMCS. */
1657#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1658/** Allowed settings for secondary processor-based VM-execution controls. */
1659#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1660/** EPT capabilities. */
1661#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1662/** Allowed settings of all pin-based VM execution controls. */
1663#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1664/** Allowed settings of all proc-based VM execution controls. */
1665#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1666/** Allowed settings of all VMX exit controls. */
1667#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1668/** Allowed settings of all VMX entry controls. */
1669#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1670/** Allowed settings for the VM-function controls. */
1671#define MSR_IA32_VMX_VMFUNC 0x491
1672/** Tertiary processor-based VM execution controls. */
1673#define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
1674
1675/** Intel PT - Enable and control for trace packet generation. */
1676#define MSR_IA32_RTIT_CTL 0x570
1677
1678/** DS Save Area (R/W). */
1679#define MSR_IA32_DS_AREA 0x600
1680/** Running Average Power Limit (RAPL) power units. */
1681#define MSR_RAPL_POWER_UNIT 0x606
1682/** Package C3 Interrupt Response Limit. */
1683#define MSR_PKGC3_IRTL 0x60a
1684/** Package C6/C7S Interrupt Response Limit 1. */
1685#define MSR_PKGC_IRTL1 0x60b
1686/** Package C6/C7S Interrupt Response Limit 2. */
1687#define MSR_PKGC_IRTL2 0x60c
1688/** Package C2 Residency Counter. */
1689#define MSR_PKG_C2_RESIDENCY 0x60d
1690/** PKG RAPL Power Limit Control. */
1691#define MSR_PKG_POWER_LIMIT 0x610
1692/** PKG Energy Status. */
1693#define MSR_PKG_ENERGY_STATUS 0x611
1694/** PKG Perf Status. */
1695#define MSR_PKG_PERF_STATUS 0x613
1696/** PKG RAPL Parameters. */
1697#define MSR_PKG_POWER_INFO 0x614
1698/** DRAM RAPL Power Limit Control. */
1699#define MSR_DRAM_POWER_LIMIT 0x618
1700/** DRAM Energy Status. */
1701#define MSR_DRAM_ENERGY_STATUS 0x619
1702/** DRAM Performance Throttling Status. */
1703#define MSR_DRAM_PERF_STATUS 0x61b
1704/** DRAM RAPL Parameters. */
1705#define MSR_DRAM_POWER_INFO 0x61c
1706/** Package C10 Residency Counter. */
1707#define MSR_PKG_C10_RESIDENCY 0x632
1708/** PP0 Energy Status. */
1709#define MSR_PP0_ENERGY_STATUS 0x639
1710/** PP1 Energy Status. */
1711#define MSR_PP1_ENERGY_STATUS 0x641
1712/** Turbo Activation Ratio. */
1713#define MSR_TURBO_ACTIVATION_RATIO 0x64c
1714/** Core Performance Limit Reasons. */
1715#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
1716
1717/** X2APIC MSR range start. */
1718#define MSR_IA32_X2APIC_START 0x800
1719/** X2APIC MSR - APIC ID Register. */
1720#define MSR_IA32_X2APIC_ID 0x802
1721/** X2APIC MSR - APIC Version Register. */
1722#define MSR_IA32_X2APIC_VERSION 0x803
1723/** X2APIC MSR - Task Priority Register. */
1724#define MSR_IA32_X2APIC_TPR 0x808
1725/** X2APIC MSR - Processor Priority register. */
1726#define MSR_IA32_X2APIC_PPR 0x80A
1727/** X2APIC MSR - End Of Interrupt register. */
1728#define MSR_IA32_X2APIC_EOI 0x80B
1729/** X2APIC MSR - Logical Destination Register. */
1730#define MSR_IA32_X2APIC_LDR 0x80D
1731/** X2APIC MSR - Spurious Interrupt Vector Register. */
1732#define MSR_IA32_X2APIC_SVR 0x80F
1733/** X2APIC MSR - In-service Register (bits 31:0). */
1734#define MSR_IA32_X2APIC_ISR0 0x810
1735/** X2APIC MSR - In-service Register (bits 63:32). */
1736#define MSR_IA32_X2APIC_ISR1 0x811
1737/** X2APIC MSR - In-service Register (bits 95:64). */
1738#define MSR_IA32_X2APIC_ISR2 0x812
1739/** X2APIC MSR - In-service Register (bits 127:96). */
1740#define MSR_IA32_X2APIC_ISR3 0x813
1741/** X2APIC MSR - In-service Register (bits 159:128). */
1742#define MSR_IA32_X2APIC_ISR4 0x814
1743/** X2APIC MSR - In-service Register (bits 191:160). */
1744#define MSR_IA32_X2APIC_ISR5 0x815
1745/** X2APIC MSR - In-service Register (bits 223:192). */
1746#define MSR_IA32_X2APIC_ISR6 0x816
1747/** X2APIC MSR - In-service Register (bits 255:224). */
1748#define MSR_IA32_X2APIC_ISR7 0x817
1749/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1750#define MSR_IA32_X2APIC_TMR0 0x818
1751/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1752#define MSR_IA32_X2APIC_TMR1 0x819
1753/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1754#define MSR_IA32_X2APIC_TMR2 0x81A
1755/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1756#define MSR_IA32_X2APIC_TMR3 0x81B
1757/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1758#define MSR_IA32_X2APIC_TMR4 0x81C
1759/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1760#define MSR_IA32_X2APIC_TMR5 0x81D
1761/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1762#define MSR_IA32_X2APIC_TMR6 0x81E
1763/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1764#define MSR_IA32_X2APIC_TMR7 0x81F
1765/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1766#define MSR_IA32_X2APIC_IRR0 0x820
1767/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1768#define MSR_IA32_X2APIC_IRR1 0x821
1769/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1770#define MSR_IA32_X2APIC_IRR2 0x822
1771/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1772#define MSR_IA32_X2APIC_IRR3 0x823
1773/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1774#define MSR_IA32_X2APIC_IRR4 0x824
1775/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1776#define MSR_IA32_X2APIC_IRR5 0x825
1777/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1778#define MSR_IA32_X2APIC_IRR6 0x826
1779/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1780#define MSR_IA32_X2APIC_IRR7 0x827
1781/** X2APIC MSR - Error Status Register. */
1782#define MSR_IA32_X2APIC_ESR 0x828
1783/** X2APIC MSR - LVT CMCI Register. */
1784#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1785/** X2APIC MSR - Interrupt Command Register. */
1786#define MSR_IA32_X2APIC_ICR 0x830
1787/** X2APIC MSR - LVT Timer Register. */
1788#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1789/** X2APIC MSR - LVT Thermal Sensor Register. */
1790#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1791/** X2APIC MSR - LVT Performance Counter Register. */
1792#define MSR_IA32_X2APIC_LVT_PERF 0x834
1793/** X2APIC MSR - LVT LINT0 Register. */
1794#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1795/** X2APIC MSR - LVT LINT1 Register. */
1796#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1797/** X2APIC MSR - LVT Error Register . */
1798#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1799/** X2APIC MSR - Timer Initial Count Register. */
1800#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1801/** X2APIC MSR - Timer Current Count Register. */
1802#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1803/** X2APIC MSR - Timer Divide Configuration Register. */
1804#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1805/** X2APIC MSR - Self IPI. */
1806#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1807/** X2APIC MSR range end. */
1808#define MSR_IA32_X2APIC_END 0x8FF
1809/** X2APIC MSR - LVT start range. */
1810#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1811/** X2APIC MSR - LVT end range (inclusive). */
1812#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1813
1814/** K6 EFER - Extended Feature Enable Register. */
1815#define MSR_K6_EFER UINT32_C(0xc0000080)
1816/** @todo document EFER */
1817/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1818#define MSR_K6_EFER_SCE RT_BIT_32(0)
1819/** Bit 8 - LME - Long mode enabled. (R/W) */
1820#define MSR_K6_EFER_LME RT_BIT_32(8)
1821#define MSR_K6_EFER_BIT_LME 8 /**< Bit number of MSR_K6_EFER_LME */
1822/** Bit 10 - LMA - Long mode active. (R) */
1823#define MSR_K6_EFER_LMA RT_BIT_32(10)
1824#define MSR_K6_EFER_BIT_LMA 10 /**< Bit number of MSR_K6_EFER_LMA */
1825/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1826#define MSR_K6_EFER_NXE RT_BIT_32(11)
1827#define MSR_K6_EFER_BIT_NXE 11 /**< Bit number of MSR_K6_EFER_NXE */
1828/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1829#define MSR_K6_EFER_SVME RT_BIT_32(12)
1830/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1831#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1832/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM*). (R/W) */
1833#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1834/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1835#define MSR_K6_EFER_TCE RT_BIT_32(15)
1836/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
1837#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
1838
1839/** K6 STAR - SYSCALL/RET targets. */
1840#define MSR_K6_STAR UINT32_C(0xc0000081)
1841/** Shift value for getting the SYSRET CS and SS value. */
1842#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1843/** Shift value for getting the SYSCALL CS and SS value. */
1844#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1845/** Selector mask for use after shifting. */
1846#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1847/** The mask which give the SYSCALL EIP. */
1848#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1849/** K6 WHCR - Write Handling Control Register. */
1850#define MSR_K6_WHCR UINT32_C(0xc0000082)
1851/** K6 UWCCR - UC/WC Cacheability Control Register. */
1852#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1853/** K6 PSOR - Processor State Observability Register. */
1854#define MSR_K6_PSOR UINT32_C(0xc0000087)
1855/** K6 PFIR - Page Flush/Invalidate Register. */
1856#define MSR_K6_PFIR UINT32_C(0xc0000088)
1857
1858/** Performance counter MSRs. (AMD only) */
1859#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1860#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1861#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1862#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1863#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1864#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1865#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1866#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1867
1868/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1869#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1870/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1871#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1872/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1873#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1874/** K8 FS.base - The 64-bit base FS register. */
1875#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1876/** K8 GS.base - The 64-bit base GS register. */
1877#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1878/** K8 KernelGSbase - Used with SWAPGS. */
1879#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1880/** K8 TSC_AUX - Used with RDTSCP. */
1881#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1882#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1883#define MSR_K8_HWCR UINT32_C(0xc0010015)
1884#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1885#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1886#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1887#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1888#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1889#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1890
1891/** SMM MSRs. */
1892#define MSR_K7_SMBASE UINT32_C(0xc0010111)
1893#define MSR_K7_SMM_ADDR UINT32_C(0xc0010112)
1894#define MSR_K7_SMM_MASK UINT32_C(0xc0010113)
1895
1896/** North bridge config? See BIOS & Kernel dev guides for
1897 * details. */
1898#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1899
1900/** Hypertransport interrupt pending register.
1901 * "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1902#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1903
1904/** SVM Control. */
1905#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1906/** Disables HDT (Hardware Debug Tool) and certain internal debug
1907 * features. */
1908#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1909/** If set, non-intercepted INIT signals are converted to \#SX
1910 * exceptions. */
1911#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1912/** Disables A20 masking. */
1913#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1914/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1915#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1916/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1917 * clear, EFER.SVME can be written normally. */
1918#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1919
1920#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1921#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1922/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1923 * host state during world switch. */
1924#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1925
1926/** Virtualized speculation control for AMD processors.
1927 *
1928 * Unified interface among different CPU generations.
1929 * The VMM will set any architectural MSRs based on the CPU.
1930 * See "White Paper: AMD64 Technology Speculative Store Bypass Disable 5.21.18"
1931 * (12441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf) */
1932#define MSR_AMD_VIRT_SPEC_CTL UINT32_C(0xc001011f)
1933/** Speculative Store Bypass Disable. */
1934# define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
1935
1936/** @} */
1937
1938
1939/** @name Page Table / Directory / Directory Pointers / L4.
1940 * @{
1941 */
1942
1943/** Page table/directory entry as an unsigned integer. */
1944typedef uint32_t X86PGUINT;
1945/** Pointer to a page table/directory table entry as an unsigned integer. */
1946typedef X86PGUINT *PX86PGUINT;
1947/** Pointer to an const page table/directory table entry as an unsigned integer. */
1948typedef X86PGUINT const *PCX86PGUINT;
1949
1950/** Number of entries in a 32-bit PT/PD. */
1951#define X86_PG_ENTRIES 1024
1952
1953
1954/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1955typedef uint64_t X86PGPAEUINT;
1956/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1957typedef X86PGPAEUINT *PX86PGPAEUINT;
1958/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1959typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1960
1961/** Number of entries in a PAE PT/PD. */
1962#define X86_PG_PAE_ENTRIES 512
1963/** Number of entries in a PAE PDPT. */
1964#define X86_PG_PAE_PDPE_ENTRIES 4
1965
1966/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1967#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1968/** Number of entries in an AMD64 PDPT.
1969 * Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1970#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1971
1972/** The size of a default page. */
1973#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1974/** The page shift of a default page. */
1975#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1976/** The default page offset mask. */
1977#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1978/** The default page base mask for virtual addresses. */
1979#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1980/** The default page base mask for virtual addresses - 32bit version. */
1981#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1982
1983/** The size of a 4KB page. */
1984#define X86_PAGE_4K_SIZE _4K
1985/** The page shift of a 4KB page. */
1986#define X86_PAGE_4K_SHIFT 12
1987/** The 4KB page offset mask. */
1988#define X86_PAGE_4K_OFFSET_MASK 0xfff
1989/** The 4KB page base mask for virtual addresses. */
1990#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1991/** The 4KB page base mask for virtual addresses - 32bit version. */
1992#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
1993
1994/** The size of a 2MB page. */
1995#define X86_PAGE_2M_SIZE _2M
1996/** The page shift of a 2MB page. */
1997#define X86_PAGE_2M_SHIFT 21
1998/** The 2MB page offset mask. */
1999#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
2000/** The 2MB page base mask for virtual addresses. */
2001#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
2002/** The 2MB page base mask for virtual addresses - 32bit version. */
2003#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
2004
2005/** The size of a 4MB page. */
2006#define X86_PAGE_4M_SIZE _4M
2007/** The page shift of a 4MB page. */
2008#define X86_PAGE_4M_SHIFT 22
2009/** The 4MB page offset mask. */
2010#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
2011/** The 4MB page base mask for virtual addresses. */
2012#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
2013/** The 4MB page base mask for virtual addresses - 32bit version. */
2014#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
2015
2016/** The size of a 1GB page. */
2017#define X86_PAGE_1G_SIZE _1G
2018/** The page shift of a 1GB page. */
2019#define X86_PAGE_1G_SHIFT 30
2020/** The 1GB page offset mask. */
2021#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
2022/** The 1GB page base mask for virtual addresses. */
2023#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
2024
2025/**
2026 * Check if the given address is canonical.
2027 */
2028#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
2029
2030/**
2031 * Gets the page base mask given the page shift.
2032 */
2033#define X86_GET_PAGE_BASE_MASK(a_cShift) (UINT64_C(0xffffffffffffffff) << (a_cShift))
2034
2035/**
2036 * Gets the page offset mask given the page shift.
2037 */
2038#define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
2039
2040
2041/** @name Page Table Entry
2042 * @{
2043 */
2044/** Bit 0 - P - Present bit. */
2045#define X86_PTE_BIT_P 0
2046/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2047#define X86_PTE_BIT_RW 1
2048/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2049#define X86_PTE_BIT_US 2
2050/** Bit 3 - PWT - Page level write thru bit. */
2051#define X86_PTE_BIT_PWT 3
2052/** Bit 4 - PCD - Page level cache disable bit. */
2053#define X86_PTE_BIT_PCD 4
2054/** Bit 5 - A - Access bit. */
2055#define X86_PTE_BIT_A 5
2056/** Bit 6 - D - Dirty bit. */
2057#define X86_PTE_BIT_D 6
2058/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2059#define X86_PTE_BIT_PAT 7
2060/** Bit 8 - G - Global flag. */
2061#define X86_PTE_BIT_G 8
2062/** Bits 63 - NX - PAE/LM - No execution flag. */
2063#define X86_PTE_PAE_BIT_NX 63
2064
2065/** Bit 0 - P - Present bit mask. */
2066#define X86_PTE_P RT_BIT_32(0)
2067/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
2068#define X86_PTE_RW RT_BIT_32(1)
2069/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
2070#define X86_PTE_US RT_BIT_32(2)
2071/** Bit 3 - PWT - Page level write thru bit mask. */
2072#define X86_PTE_PWT RT_BIT_32(3)
2073/** Bit 4 - PCD - Page level cache disable bit mask. */
2074#define X86_PTE_PCD RT_BIT_32(4)
2075/** Bit 5 - A - Access bit mask. */
2076#define X86_PTE_A RT_BIT_32(5)
2077/** Bit 6 - D - Dirty bit mask. */
2078#define X86_PTE_D RT_BIT_32(6)
2079/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
2080#define X86_PTE_PAT RT_BIT_32(7)
2081/** Bit 8 - G - Global bit mask. */
2082#define X86_PTE_G RT_BIT_32(8)
2083
2084/** Bits 9-11 - - Available for use to system software. */
2085#define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2086/** Bits 12-31 - - Physical Page number of the next level. */
2087#define X86_PTE_PG_MASK ( 0xfffff000 )
2088
2089/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2090#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2091/** Bits 63 - NX - PAE/LM - No execution flag. */
2092#define X86_PTE_PAE_NX RT_BIT_64(63)
2093/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
2094#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
2095/** Bits 63-52 - - PAE - MBZ bits when no NX. */
2096#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
2097/** No bits - - LM - MBZ bits when NX is active. */
2098#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
2099/** Bits 63 - - LM - MBZ bits when no NX. */
2100#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
2101
2102/**
2103 * Page table entry.
2104 */
2105typedef struct X86PTEBITS
2106{
2107 /** Flags whether(=1) or not the page is present. */
2108 uint32_t u1Present : 1;
2109 /** Read(=0) / Write(=1) flag. */
2110 uint32_t u1Write : 1;
2111 /** User(=1) / Supervisor (=0) flag. */
2112 uint32_t u1User : 1;
2113 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2114 uint32_t u1WriteThru : 1;
2115 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2116 uint32_t u1CacheDisable : 1;
2117 /** Accessed flag.
2118 * Indicates that the page have been read or written to. */
2119 uint32_t u1Accessed : 1;
2120 /** Dirty flag.
2121 * Indicates that the page has been written to. */
2122 uint32_t u1Dirty : 1;
2123 /** Reserved / If PAT enabled, bit 2 of the index. */
2124 uint32_t u1PAT : 1;
2125 /** Global flag. (Ignored in all but final level.) */
2126 uint32_t u1Global : 1;
2127 /** Available for use to system software. */
2128 uint32_t u3Available : 3;
2129 /** Physical Page number of the next level. */
2130 uint32_t u20PageNo : 20;
2131} X86PTEBITS;
2132#ifndef VBOX_FOR_DTRACE_LIB
2133AssertCompileSize(X86PTEBITS, 4);
2134#endif
2135/** Pointer to a page table entry. */
2136typedef X86PTEBITS *PX86PTEBITS;
2137/** Pointer to a const page table entry. */
2138typedef const X86PTEBITS *PCX86PTEBITS;
2139
2140/**
2141 * Page table entry.
2142 */
2143typedef union X86PTE
2144{
2145 /** Unsigned integer view */
2146 X86PGUINT u;
2147#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2148 /** Bit field view. */
2149 X86PTEBITS n;
2150#endif
2151 /** 32-bit view. */
2152 uint32_t au32[1];
2153 /** 16-bit view. */
2154 uint16_t au16[2];
2155 /** 8-bit view. */
2156 uint8_t au8[4];
2157} X86PTE;
2158#ifndef VBOX_FOR_DTRACE_LIB
2159AssertCompileSize(X86PTE, 4);
2160#endif
2161/** Pointer to a page table entry. */
2162typedef X86PTE *PX86PTE;
2163/** Pointer to a const page table entry. */
2164typedef const X86PTE *PCX86PTE;
2165
2166
2167/**
2168 * PAE page table entry.
2169 */
2170typedef struct X86PTEPAEBITS
2171{
2172 /** Flags whether(=1) or not the page is present. */
2173 uint32_t u1Present : 1;
2174 /** Read(=0) / Write(=1) flag. */
2175 uint32_t u1Write : 1;
2176 /** User(=1) / Supervisor(=0) flag. */
2177 uint32_t u1User : 1;
2178 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2179 uint32_t u1WriteThru : 1;
2180 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2181 uint32_t u1CacheDisable : 1;
2182 /** Accessed flag.
2183 * Indicates that the page have been read or written to. */
2184 uint32_t u1Accessed : 1;
2185 /** Dirty flag.
2186 * Indicates that the page has been written to. */
2187 uint32_t u1Dirty : 1;
2188 /** Reserved / If PAT enabled, bit 2 of the index. */
2189 uint32_t u1PAT : 1;
2190 /** Global flag. (Ignored in all but final level.) */
2191 uint32_t u1Global : 1;
2192 /** Available for use to system software. */
2193 uint32_t u3Available : 3;
2194 /** Physical Page number of the next level - Low Part. Don't use this. */
2195 uint32_t u20PageNoLow : 20;
2196 /** Physical Page number of the next level - High Part. Don't use this. */
2197 uint32_t u20PageNoHigh : 20;
2198 /** MBZ bits */
2199 uint32_t u11Reserved : 11;
2200 /** No Execute flag. */
2201 uint32_t u1NoExecute : 1;
2202} X86PTEPAEBITS;
2203#ifndef VBOX_FOR_DTRACE_LIB
2204AssertCompileSize(X86PTEPAEBITS, 8);
2205#endif
2206/** Pointer to a page table entry. */
2207typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2208/** Pointer to a page table entry. */
2209typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2210
2211/**
2212 * PAE Page table entry.
2213 */
2214typedef union X86PTEPAE
2215{
2216 /** Unsigned integer view */
2217 X86PGPAEUINT u;
2218#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2219 /** Bit field view. */
2220 X86PTEPAEBITS n;
2221#endif
2222 /** 32-bit view. */
2223 uint32_t au32[2];
2224 /** 16-bit view. */
2225 uint16_t au16[4];
2226 /** 8-bit view. */
2227 uint8_t au8[8];
2228} X86PTEPAE;
2229#ifndef VBOX_FOR_DTRACE_LIB
2230AssertCompileSize(X86PTEPAE, 8);
2231#endif
2232/** Pointer to a PAE page table entry. */
2233typedef X86PTEPAE *PX86PTEPAE;
2234/** Pointer to a const PAE page table entry. */
2235typedef const X86PTEPAE *PCX86PTEPAE;
2236/** @} */
2237
2238/**
2239 * Page table.
2240 */
2241typedef struct X86PT
2242{
2243 /** PTE Array. */
2244 X86PTE a[X86_PG_ENTRIES];
2245} X86PT;
2246#ifndef VBOX_FOR_DTRACE_LIB
2247AssertCompileSize(X86PT, 4096);
2248#endif
2249/** Pointer to a page table. */
2250typedef X86PT *PX86PT;
2251/** Pointer to a const page table. */
2252typedef const X86PT *PCX86PT;
2253
2254/** The page shift to get the PT index. */
2255#define X86_PT_SHIFT 12
2256/** The PT index mask (apply to a shifted page address). */
2257#define X86_PT_MASK 0x3ff
2258
2259
2260/**
2261 * Page directory.
2262 */
2263typedef struct X86PTPAE
2264{
2265 /** PTE Array. */
2266 X86PTEPAE a[X86_PG_PAE_ENTRIES];
2267} X86PTPAE;
2268#ifndef VBOX_FOR_DTRACE_LIB
2269AssertCompileSize(X86PTPAE, 4096);
2270#endif
2271/** Pointer to a page table. */
2272typedef X86PTPAE *PX86PTPAE;
2273/** Pointer to a const page table. */
2274typedef const X86PTPAE *PCX86PTPAE;
2275
2276/** The page shift to get the PA PTE index. */
2277#define X86_PT_PAE_SHIFT 12
2278/** The PAE PT index mask (apply to a shifted page address). */
2279#define X86_PT_PAE_MASK 0x1ff
2280
2281
2282/** @name 4KB Page Directory Entry
2283 * @{
2284 */
2285/** Bit 0 - P - Present bit. */
2286#define X86_PDE_P RT_BIT_32(0)
2287/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2288#define X86_PDE_RW RT_BIT_32(1)
2289/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2290#define X86_PDE_US RT_BIT_32(2)
2291/** Bit 3 - PWT - Page level write thru bit. */
2292#define X86_PDE_PWT RT_BIT_32(3)
2293/** Bit 4 - PCD - Page level cache disable bit. */
2294#define X86_PDE_PCD RT_BIT_32(4)
2295/** Bit 5 - A - Access bit. */
2296#define X86_PDE_A RT_BIT_32(5)
2297/** Bit 7 - PS - Page size attribute.
2298 * Clear mean 4KB pages, set means large pages (2/4MB). */
2299#define X86_PDE_PS RT_BIT_32(7)
2300/** Bits 9-11 - - Available for use to system software. */
2301#define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2302/** Bits 12-31 - - Physical Page number of the next level. */
2303#define X86_PDE_PG_MASK ( 0xfffff000 )
2304
2305/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2306#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2307/** Bits 63 - NX - PAE/LM - No execution flag. */
2308#define X86_PDE_PAE_NX RT_BIT_64(63)
2309/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2310#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2311/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2312#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2313/** Bit 7 - - LM - MBZ bits when NX is active. */
2314#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2315/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2316#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2317
2318/**
2319 * Page directory entry.
2320 */
2321typedef struct X86PDEBITS
2322{
2323 /** Flags whether(=1) or not the page is present. */
2324 uint32_t u1Present : 1;
2325 /** Read(=0) / Write(=1) flag. */
2326 uint32_t u1Write : 1;
2327 /** User(=1) / Supervisor (=0) flag. */
2328 uint32_t u1User : 1;
2329 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2330 uint32_t u1WriteThru : 1;
2331 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2332 uint32_t u1CacheDisable : 1;
2333 /** Accessed flag.
2334 * Indicates that the page has been read or written to. */
2335 uint32_t u1Accessed : 1;
2336 /** Reserved / Ignored (dirty bit). */
2337 uint32_t u1Reserved0 : 1;
2338 /** Size bit if PSE is enabled - in any event it's 0. */
2339 uint32_t u1Size : 1;
2340 /** Reserved / Ignored (global bit). */
2341 uint32_t u1Reserved1 : 1;
2342 /** Available for use to system software. */
2343 uint32_t u3Available : 3;
2344 /** Physical Page number of the next level. */
2345 uint32_t u20PageNo : 20;
2346} X86PDEBITS;
2347#ifndef VBOX_FOR_DTRACE_LIB
2348AssertCompileSize(X86PDEBITS, 4);
2349#endif
2350/** Pointer to a page directory entry. */
2351typedef X86PDEBITS *PX86PDEBITS;
2352/** Pointer to a const page directory entry. */
2353typedef const X86PDEBITS *PCX86PDEBITS;
2354
2355
2356/**
2357 * PAE page directory entry.
2358 */
2359typedef struct X86PDEPAEBITS
2360{
2361 /** Flags whether(=1) or not the page is present. */
2362 uint32_t u1Present : 1;
2363 /** Read(=0) / Write(=1) flag. */
2364 uint32_t u1Write : 1;
2365 /** User(=1) / Supervisor (=0) flag. */
2366 uint32_t u1User : 1;
2367 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2368 uint32_t u1WriteThru : 1;
2369 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2370 uint32_t u1CacheDisable : 1;
2371 /** Accessed flag.
2372 * Indicates that the page has been read or written to. */
2373 uint32_t u1Accessed : 1;
2374 /** Reserved / Ignored (dirty bit). */
2375 uint32_t u1Reserved0 : 1;
2376 /** Size bit if PSE is enabled - in any event it's 0. */
2377 uint32_t u1Size : 1;
2378 /** Reserved / Ignored (global bit). / */
2379 uint32_t u1Reserved1 : 1;
2380 /** Available for use to system software. */
2381 uint32_t u3Available : 3;
2382 /** Physical Page number of the next level - Low Part. Don't use! */
2383 uint32_t u20PageNoLow : 20;
2384 /** Physical Page number of the next level - High Part. Don't use! */
2385 uint32_t u20PageNoHigh : 20;
2386 /** MBZ bits */
2387 uint32_t u11Reserved : 11;
2388 /** No Execute flag. */
2389 uint32_t u1NoExecute : 1;
2390} X86PDEPAEBITS;
2391#ifndef VBOX_FOR_DTRACE_LIB
2392AssertCompileSize(X86PDEPAEBITS, 8);
2393#endif
2394/** Pointer to a page directory entry. */
2395typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2396/** Pointer to a const page directory entry. */
2397typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2398
2399/** @} */
2400
2401
2402/** @name 2/4MB Page Directory Entry
2403 * @{
2404 */
2405/** Bit 0 - P - Present bit. */
2406#define X86_PDE4M_P RT_BIT_32(0)
2407/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2408#define X86_PDE4M_RW RT_BIT_32(1)
2409/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2410#define X86_PDE4M_US RT_BIT_32(2)
2411/** Bit 3 - PWT - Page level write thru bit. */
2412#define X86_PDE4M_PWT RT_BIT_32(3)
2413/** Bit 4 - PCD - Page level cache disable bit. */
2414#define X86_PDE4M_PCD RT_BIT_32(4)
2415/** Bit 5 - A - Access bit. */
2416#define X86_PDE4M_A RT_BIT_32(5)
2417/** Bit 6 - D - Dirty bit. */
2418#define X86_PDE4M_D RT_BIT_32(6)
2419/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2420#define X86_PDE4M_PS RT_BIT_32(7)
2421/** Bit 8 - G - Global flag. */
2422#define X86_PDE4M_G RT_BIT_32(8)
2423/** Bits 9-11 - AVL - Available for use to system software. */
2424#define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2425/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2426#define X86_PDE4M_PAT RT_BIT_32(12)
2427/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2428#define X86_PDE4M_PAT_SHIFT (12 - 7)
2429/** Bits 22-31 - - Physical Page number. */
2430#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2431/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2432#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2433/** The number of bits to the high part of the page number. */
2434#define X86_PDE4M_PG_HIGH_SHIFT 19
2435/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2436#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2437
2438/** Bits 21-51 - - PAE/LM - Physical Page number.
2439 * (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2440#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2441/** Bits 63 - NX - PAE/LM - No execution flag. */
2442#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2443/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2444#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2445/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2446#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2447/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2448#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2449/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2450#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2451
2452/**
2453 * 4MB page directory entry.
2454 */
2455typedef struct X86PDE4MBITS
2456{
2457 /** Flags whether(=1) or not the page is present. */
2458 uint32_t u1Present : 1;
2459 /** Read(=0) / Write(=1) flag. */
2460 uint32_t u1Write : 1;
2461 /** User(=1) / Supervisor (=0) flag. */
2462 uint32_t u1User : 1;
2463 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2464 uint32_t u1WriteThru : 1;
2465 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2466 uint32_t u1CacheDisable : 1;
2467 /** Accessed flag.
2468 * Indicates that the page have been read or written to. */
2469 uint32_t u1Accessed : 1;
2470 /** Dirty flag.
2471 * Indicates that the page has been written to. */
2472 uint32_t u1Dirty : 1;
2473 /** Page size flag - always 1 for 4MB entries. */
2474 uint32_t u1Size : 1;
2475 /** Global flag. */
2476 uint32_t u1Global : 1;
2477 /** Available for use to system software. */
2478 uint32_t u3Available : 3;
2479 /** Reserved / If PAT enabled, bit 2 of the index. */
2480 uint32_t u1PAT : 1;
2481 /** Bits 32-39 of the page number on AMD64.
2482 * This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2483 uint32_t u8PageNoHigh : 8;
2484 /** Reserved. */
2485 uint32_t u1Reserved : 1;
2486 /** Physical Page number of the page. */
2487 uint32_t u10PageNo : 10;
2488} X86PDE4MBITS;
2489#ifndef VBOX_FOR_DTRACE_LIB
2490AssertCompileSize(X86PDE4MBITS, 4);
2491#endif
2492/** Pointer to a page table entry. */
2493typedef X86PDE4MBITS *PX86PDE4MBITS;
2494/** Pointer to a const page table entry. */
2495typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2496
2497
2498/**
2499 * 2MB PAE page directory entry.
2500 */
2501typedef struct X86PDE2MPAEBITS
2502{
2503 /** Flags whether(=1) or not the page is present. */
2504 uint32_t u1Present : 1;
2505 /** Read(=0) / Write(=1) flag. */
2506 uint32_t u1Write : 1;
2507 /** User(=1) / Supervisor(=0) flag. */
2508 uint32_t u1User : 1;
2509 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2510 uint32_t u1WriteThru : 1;
2511 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2512 uint32_t u1CacheDisable : 1;
2513 /** Accessed flag.
2514 * Indicates that the page have been read or written to. */
2515 uint32_t u1Accessed : 1;
2516 /** Dirty flag.
2517 * Indicates that the page has been written to. */
2518 uint32_t u1Dirty : 1;
2519 /** Page size flag - always 1 for 2MB entries. */
2520 uint32_t u1Size : 1;
2521 /** Global flag. */
2522 uint32_t u1Global : 1;
2523 /** Available for use to system software. */
2524 uint32_t u3Available : 3;
2525 /** Reserved / If PAT enabled, bit 2 of the index. */
2526 uint32_t u1PAT : 1;
2527 /** Reserved. */
2528 uint32_t u9Reserved : 9;
2529 /** Physical Page number of the next level - Low part. Don't use! */
2530 uint32_t u10PageNoLow : 10;
2531 /** Physical Page number of the next level - High part. Don't use! */
2532 uint32_t u20PageNoHigh : 20;
2533 /** MBZ bits */
2534 uint32_t u11Reserved : 11;
2535 /** No Execute flag. */
2536 uint32_t u1NoExecute : 1;
2537} X86PDE2MPAEBITS;
2538#ifndef VBOX_FOR_DTRACE_LIB
2539AssertCompileSize(X86PDE2MPAEBITS, 8);
2540#endif
2541/** Pointer to a 2MB PAE page table entry. */
2542typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2543/** Pointer to a 2MB PAE page table entry. */
2544typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2545
2546/** @} */
2547
2548/**
2549 * Page directory entry.
2550 */
2551typedef union X86PDE
2552{
2553 /** Unsigned integer view. */
2554 X86PGUINT u;
2555#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2556 /** Normal view. */
2557 X86PDEBITS n;
2558 /** 4MB view (big). */
2559 X86PDE4MBITS b;
2560#endif
2561 /** 8 bit unsigned integer view. */
2562 uint8_t au8[4];
2563 /** 16 bit unsigned integer view. */
2564 uint16_t au16[2];
2565 /** 32 bit unsigned integer view. */
2566 uint32_t au32[1];
2567} X86PDE;
2568#ifndef VBOX_FOR_DTRACE_LIB
2569AssertCompileSize(X86PDE, 4);
2570#endif
2571/** Pointer to a page directory entry. */
2572typedef X86PDE *PX86PDE;
2573/** Pointer to a const page directory entry. */
2574typedef const X86PDE *PCX86PDE;
2575
2576/**
2577 * PAE page directory entry.
2578 */
2579typedef union X86PDEPAE
2580{
2581 /** Unsigned integer view. */
2582 X86PGPAEUINT u;
2583#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2584 /** Normal view. */
2585 X86PDEPAEBITS n;
2586 /** 2MB page view (big). */
2587 X86PDE2MPAEBITS b;
2588#endif
2589 /** 8 bit unsigned integer view. */
2590 uint8_t au8[8];
2591 /** 16 bit unsigned integer view. */
2592 uint16_t au16[4];
2593 /** 32 bit unsigned integer view. */
2594 uint32_t au32[2];
2595} X86PDEPAE;
2596#ifndef VBOX_FOR_DTRACE_LIB
2597AssertCompileSize(X86PDEPAE, 8);
2598#endif
2599/** Pointer to a page directory entry. */
2600typedef X86PDEPAE *PX86PDEPAE;
2601/** Pointer to a const page directory entry. */
2602typedef const X86PDEPAE *PCX86PDEPAE;
2603
2604/**
2605 * Page directory.
2606 */
2607typedef struct X86PD
2608{
2609 /** PDE Array. */
2610 X86PDE a[X86_PG_ENTRIES];
2611} X86PD;
2612#ifndef VBOX_FOR_DTRACE_LIB
2613AssertCompileSize(X86PD, 4096);
2614#endif
2615/** Pointer to a page directory. */
2616typedef X86PD *PX86PD;
2617/** Pointer to a const page directory. */
2618typedef const X86PD *PCX86PD;
2619
2620/** The page shift to get the PD index. */
2621#define X86_PD_SHIFT 22
2622/** The PD index mask (apply to a shifted page address). */
2623#define X86_PD_MASK 0x3ff
2624
2625
2626/**
2627 * PAE page directory.
2628 */
2629typedef struct X86PDPAE
2630{
2631 /** PDE Array. */
2632 X86PDEPAE a[X86_PG_PAE_ENTRIES];
2633} X86PDPAE;
2634#ifndef VBOX_FOR_DTRACE_LIB
2635AssertCompileSize(X86PDPAE, 4096);
2636#endif
2637/** Pointer to a PAE page directory. */
2638typedef X86PDPAE *PX86PDPAE;
2639/** Pointer to a const PAE page directory. */
2640typedef const X86PDPAE *PCX86PDPAE;
2641
2642/** The page shift to get the PAE PD index. */
2643#define X86_PD_PAE_SHIFT 21
2644/** The PAE PD index mask (apply to a shifted page address). */
2645#define X86_PD_PAE_MASK 0x1ff
2646
2647
2648/** @name Page Directory Pointer Table Entry (PAE)
2649 * @{
2650 */
2651/** Bit 0 - P - Present bit. */
2652#define X86_PDPE_P RT_BIT_32(0)
2653/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2654#define X86_PDPE_RW RT_BIT_32(1)
2655/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2656#define X86_PDPE_US RT_BIT_32(2)
2657/** Bit 3 - PWT - Page level write thru bit. */
2658#define X86_PDPE_PWT RT_BIT_32(3)
2659/** Bit 4 - PCD - Page level cache disable bit. */
2660#define X86_PDPE_PCD RT_BIT_32(4)
2661/** Bit 5 - A - Access bit. Long Mode only. */
2662#define X86_PDPE_A RT_BIT_32(5)
2663/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2664#define X86_PDPE_LM_PS RT_BIT_32(7)
2665/** Bits 9-11 - - Available for use to system software. */
2666#define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2667/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2668#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2669/** Bits 30-51 - - PG - Physical address of the 1GB page referenced by this entry. */
2670#define X86_PDPE1G_PG_MASK UINT64_C(0x000fffffc0000000)
2671/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2672#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2673/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2674#define X86_PDPE_LM_NX RT_BIT_64(63)
2675/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2676#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2677/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2678#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2679/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2680#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2681/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2682#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2683
2684
2685/**
2686 * Page directory pointer table entry.
2687 */
2688typedef struct X86PDPEBITS
2689{
2690 /** Flags whether(=1) or not the page is present. */
2691 uint32_t u1Present : 1;
2692 /** Chunk of reserved bits. */
2693 uint32_t u2Reserved : 2;
2694 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2695 uint32_t u1WriteThru : 1;
2696 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2697 uint32_t u1CacheDisable : 1;
2698 /** Chunk of reserved bits. */
2699 uint32_t u4Reserved : 4;
2700 /** Available for use to system software. */
2701 uint32_t u3Available : 3;
2702 /** Physical Page number of the next level - Low Part. Don't use! */
2703 uint32_t u20PageNoLow : 20;
2704 /** Physical Page number of the next level - High Part. Don't use! */
2705 uint32_t u20PageNoHigh : 20;
2706 /** MBZ bits */
2707 uint32_t u12Reserved : 12;
2708} X86PDPEBITS;
2709#ifndef VBOX_FOR_DTRACE_LIB
2710AssertCompileSize(X86PDPEBITS, 8);
2711#endif
2712/** Pointer to a page directory pointer table entry. */
2713typedef X86PDPEBITS *PX86PTPEBITS;
2714/** Pointer to a const page directory pointer table entry. */
2715typedef const X86PDPEBITS *PCX86PTPEBITS;
2716
2717/**
2718 * Page directory pointer table entry. AMD64 version
2719 */
2720typedef struct X86PDPEAMD64BITS
2721{
2722 /** Flags whether(=1) or not the page is present. */
2723 uint32_t u1Present : 1;
2724 /** Read(=0) / Write(=1) flag. */
2725 uint32_t u1Write : 1;
2726 /** User(=1) / Supervisor (=0) flag. */
2727 uint32_t u1User : 1;
2728 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2729 uint32_t u1WriteThru : 1;
2730 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2731 uint32_t u1CacheDisable : 1;
2732 /** Accessed flag.
2733 * Indicates that the page have been read or written to. */
2734 uint32_t u1Accessed : 1;
2735 /** Chunk of reserved bits. */
2736 uint32_t u3Reserved : 3;
2737 /** Available for use to system software. */
2738 uint32_t u3Available : 3;
2739 /** Physical Page number of the next level - Low Part. Don't use! */
2740 uint32_t u20PageNoLow : 20;
2741 /** Physical Page number of the next level - High Part. Don't use! */
2742 uint32_t u20PageNoHigh : 20;
2743 /** MBZ bits */
2744 uint32_t u11Reserved : 11;
2745 /** No Execute flag. */
2746 uint32_t u1NoExecute : 1;
2747} X86PDPEAMD64BITS;
2748#ifndef VBOX_FOR_DTRACE_LIB
2749AssertCompileSize(X86PDPEAMD64BITS, 8);
2750#endif
2751/** Pointer to a page directory pointer table entry. */
2752typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2753/** Pointer to a const page directory pointer table entry. */
2754typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2755
2756/**
2757 * Page directory pointer table entry for 1GB page. (AMD64 only)
2758 */
2759typedef struct X86PDPE1GB
2760{
2761 /** 0: Flags whether(=1) or not the page is present. */
2762 uint32_t u1Present : 1;
2763 /** 1: Read(=0) / Write(=1) flag. */
2764 uint32_t u1Write : 1;
2765 /** 2: User(=1) / Supervisor (=0) flag. */
2766 uint32_t u1User : 1;
2767 /** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2768 uint32_t u1WriteThru : 1;
2769 /** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2770 uint32_t u1CacheDisable : 1;
2771 /** 5: Accessed flag.
2772 * Indicates that the page have been read or written to. */
2773 uint32_t u1Accessed : 1;
2774 /** 6: Dirty flag for 1GB pages. */
2775 uint32_t u1Dirty : 1;
2776 /** 7: Indicates 1GB page if set. */
2777 uint32_t u1Size : 1;
2778 /** 8: Global 1GB page. */
2779 uint32_t u1Global: 1;
2780 /** 9-11: Available for use to system software. */
2781 uint32_t u3Available : 3;
2782 /** 12: PAT bit for 1GB page. */
2783 uint32_t u1PAT : 1;
2784 /** 13-29: MBZ bits. */
2785 uint32_t u17Reserved : 17;
2786 /** 30-31: Physical page number - Low Part. Don't use! */
2787 uint32_t u2PageNoLow : 2;
2788 /** 32-51: Physical Page number of the next level - High Part. Don't use! */
2789 uint32_t u20PageNoHigh : 20;
2790 /** 52-62: MBZ bits */
2791 uint32_t u11Reserved : 11;
2792 /** 63: No Execute flag. */
2793 uint32_t u1NoExecute : 1;
2794} X86PDPE1GB;
2795#ifndef VBOX_FOR_DTRACE_LIB
2796AssertCompileSize(X86PDPE1GB, 8);
2797#endif
2798/** Pointer to a page directory pointer table entry for a 1GB page. */
2799typedef X86PDPE1GB *PX86PDPE1GB;
2800/** Pointer to a const page directory pointer table entry for a 1GB page. */
2801typedef const X86PDPE1GB *PCX86PDPE1GB;
2802
2803/**
2804 * Page directory pointer table entry.
2805 */
2806typedef union X86PDPE
2807{
2808 /** Unsigned integer view. */
2809 X86PGPAEUINT u;
2810#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2811 /** Normal view. */
2812 X86PDPEBITS n;
2813 /** AMD64 view. */
2814 X86PDPEAMD64BITS lm;
2815 /** AMD64 big view. */
2816 X86PDPE1GB b;
2817#endif
2818 /** 8 bit unsigned integer view. */
2819 uint8_t au8[8];
2820 /** 16 bit unsigned integer view. */
2821 uint16_t au16[4];
2822 /** 32 bit unsigned integer view. */
2823 uint32_t au32[2];
2824} X86PDPE;
2825#ifndef VBOX_FOR_DTRACE_LIB
2826AssertCompileSize(X86PDPE, 8);
2827#endif
2828/** Pointer to a page directory pointer table entry. */
2829typedef X86PDPE *PX86PDPE;
2830/** Pointer to a const page directory pointer table entry. */
2831typedef const X86PDPE *PCX86PDPE;
2832
2833
2834/**
2835 * Page directory pointer table.
2836 */
2837typedef struct X86PDPT
2838{
2839 /** PDE Array. */
2840 X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2841} X86PDPT;
2842#ifndef VBOX_FOR_DTRACE_LIB
2843AssertCompileSize(X86PDPT, 4096);
2844#endif
2845/** Pointer to a page directory pointer table. */
2846typedef X86PDPT *PX86PDPT;
2847/** Pointer to a const page directory pointer table. */
2848typedef const X86PDPT *PCX86PDPT;
2849
2850/** The page shift to get the PDPT index. */
2851#define X86_PDPT_SHIFT 30
2852/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2853#define X86_PDPT_MASK_PAE 0x3
2854/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2855#define X86_PDPT_MASK_AMD64 0x1ff
2856
2857/** @} */
2858
2859
2860/** @name Page Map Level-4 Entry (Long Mode PAE)
2861 * @{
2862 */
2863/** Bit 0 - P - Present bit. */
2864#define X86_PML4E_P RT_BIT_32(0)
2865/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2866#define X86_PML4E_RW RT_BIT_32(1)
2867/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2868#define X86_PML4E_US RT_BIT_32(2)
2869/** Bit 3 - PWT - Page level write thru bit. */
2870#define X86_PML4E_PWT RT_BIT_32(3)
2871/** Bit 4 - PCD - Page level cache disable bit. */
2872#define X86_PML4E_PCD RT_BIT_32(4)
2873/** Bit 5 - A - Access bit. */
2874#define X86_PML4E_A RT_BIT_32(5)
2875/** Bits 9-11 - - Available for use to system software. */
2876#define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
2877/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2878#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2879/** Bits 8, 7 - - MBZ bits when NX is active. */
2880#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2881/** Bits 63, 7 - - MBZ bits when no NX. */
2882#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2883/** Bits 63 - NX - PAE - No execution flag. */
2884#define X86_PML4E_NX RT_BIT_64(63)
2885
2886/**
2887 * Page Map Level-4 Entry
2888 */
2889typedef struct X86PML4EBITS
2890{
2891 /** Flags whether(=1) or not the page is present. */
2892 uint32_t u1Present : 1;
2893 /** Read(=0) / Write(=1) flag. */
2894 uint32_t u1Write : 1;
2895 /** User(=1) / Supervisor (=0) flag. */
2896 uint32_t u1User : 1;
2897 /** Write Thru flag. If PAT enabled, bit 0 of the index. */
2898 uint32_t u1WriteThru : 1;
2899 /** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2900 uint32_t u1CacheDisable : 1;
2901 /** Accessed flag.
2902 * Indicates that the page have been read or written to. */
2903 uint32_t u1Accessed : 1;
2904 /** Chunk of reserved bits. */
2905 uint32_t u3Reserved : 3;
2906 /** Available for use to system software. */
2907 uint32_t u3Available : 3;
2908 /** Physical Page number of the next level - Low Part. Don't use! */
2909 uint32_t u20PageNoLow : 20;
2910 /** Physical Page number of the next level - High Part. Don't use! */
2911 uint32_t u20PageNoHigh : 20;
2912 /** MBZ bits */
2913 uint32_t u11Reserved : 11;
2914 /** No Execute flag. */
2915 uint32_t u1NoExecute : 1;
2916} X86PML4EBITS;
2917#ifndef VBOX_FOR_DTRACE_LIB
2918AssertCompileSize(X86PML4EBITS, 8);
2919#endif
2920/** Pointer to a page map level-4 entry. */
2921typedef X86PML4EBITS *PX86PML4EBITS;
2922/** Pointer to a const page map level-4 entry. */
2923typedef const X86PML4EBITS *PCX86PML4EBITS;
2924
2925/**
2926 * Page Map Level-4 Entry.
2927 */
2928typedef union X86PML4E
2929{
2930 /** Unsigned integer view. */
2931 X86PGPAEUINT u;
2932#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2933 /** Normal view. */
2934 X86PML4EBITS n;
2935#endif
2936 /** 8 bit unsigned integer view. */
2937 uint8_t au8[8];
2938 /** 16 bit unsigned integer view. */
2939 uint16_t au16[4];
2940 /** 32 bit unsigned integer view. */
2941 uint32_t au32[2];
2942} X86PML4E;
2943#ifndef VBOX_FOR_DTRACE_LIB
2944AssertCompileSize(X86PML4E, 8);
2945#endif
2946/** Pointer to a page map level-4 entry. */
2947typedef X86PML4E *PX86PML4E;
2948/** Pointer to a const page map level-4 entry. */
2949typedef const X86PML4E *PCX86PML4E;
2950
2951
2952/**
2953 * Page Map Level-4.
2954 */
2955typedef struct X86PML4
2956{
2957 /** PDE Array. */
2958 X86PML4E a[X86_PG_PAE_ENTRIES];
2959} X86PML4;
2960#ifndef VBOX_FOR_DTRACE_LIB
2961AssertCompileSize(X86PML4, 4096);
2962#endif
2963/** Pointer to a page map level-4. */
2964typedef X86PML4 *PX86PML4;
2965/** Pointer to a const page map level-4. */
2966typedef const X86PML4 *PCX86PML4;
2967
2968/** The page shift to get the PML4 index. */
2969#define X86_PML4_SHIFT 39
2970/** The PML4 index mask (apply to a shifted page address). */
2971#define X86_PML4_MASK 0x1ff
2972
2973/** @} */
2974
2975/** @} */
2976
2977/**
2978 * Intel PCID invalidation types.
2979 */
2980/** Individual address invalidation. */
2981#define X86_INVPCID_TYPE_INDV_ADDR 0
2982/** Single-context invalidation. */
2983#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
2984/** All-context including globals invalidation. */
2985#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
2986/** All-context excluding globals invalidation. */
2987#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
2988/** The maximum valid invalidation type value. */
2989#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
2990
2991
2992/** @name Special FPU integer values.
2993 * @{ */
2994#define X86_FPU_INT64_INDEFINITE INT64_MIN
2995#define X86_FPU_INT32_INDEFINITE INT32_MIN
2996#define X86_FPU_INT16_INDEFINITE INT16_MIN
2997/** @} */
2998
2999/**
3000 * 32-bit protected mode FSTENV image.
3001 */
3002typedef struct X86FSTENV32P
3003{
3004 uint16_t FCW; /**< 0x00 */
3005 uint16_t padding1; /**< 0x02 */
3006 uint16_t FSW; /**< 0x04 */
3007 uint16_t padding2; /**< 0x06 */
3008 uint16_t FTW; /**< 0x08 */
3009 uint16_t padding3; /**< 0x0a */
3010 uint32_t FPUIP; /**< 0x0c */
3011 uint16_t FPUCS; /**< 0x10 */
3012 uint16_t FOP; /**< 0x12 */
3013 uint32_t FPUDP; /**< 0x14 */
3014 uint16_t FPUDS; /**< 0x18 */
3015 uint16_t padding4; /**< 0x1a */
3016} X86FSTENV32P;
3017#ifndef VBOX_FOR_DTRACE_LIB
3018AssertCompileSize(X86FSTENV32P, 0x1c);
3019#endif
3020/** Pointer to a 32-bit protected mode FSTENV image. */
3021typedef X86FSTENV32P *PX86FSTENV32P;
3022/** Pointer to a const 32-bit protected mode FSTENV image. */
3023typedef X86FSTENV32P const *PCX86FSTENV32P;
3024
3025
3026/**
3027 * 80-bit MMX/FPU register type.
3028 */
3029typedef struct X86FPUMMX
3030{
3031 uint8_t reg[10];
3032} X86FPUMMX;
3033#ifndef VBOX_FOR_DTRACE_LIB
3034AssertCompileSize(X86FPUMMX, 10);
3035#endif
3036/** Pointer to a 80-bit MMX/FPU register type. */
3037typedef X86FPUMMX *PX86FPUMMX;
3038/** Pointer to a const 80-bit MMX/FPU register type. */
3039typedef const X86FPUMMX *PCX86FPUMMX;
3040
3041/** FPU (x87) register. */
3042typedef union X86FPUREG
3043{
3044 /** MMX view. */
3045 uint64_t mmx;
3046 /** FPU view - todo. */
3047 X86FPUMMX fpu;
3048 /** Extended precision floating point view. */
3049 RTFLOAT80U r80;
3050 /** Extended precision floating point view v2 */
3051 RTFLOAT80U2 r80Ex;
3052 /** 8-bit view. */
3053 uint8_t au8[16];
3054 /** 16-bit view. */
3055 uint16_t au16[8];
3056 /** 32-bit view. */
3057 uint32_t au32[4];
3058 /** 64-bit view. */
3059 uint64_t au64[2];
3060 /** 128-bit view. (yeah, very helpful) */
3061 uint128_t au128[1];
3062} X86FPUREG;
3063#ifndef VBOX_FOR_DTRACE_LIB
3064AssertCompileSize(X86FPUREG, 16);
3065#endif
3066/** Pointer to a FPU register. */
3067typedef X86FPUREG *PX86FPUREG;
3068/** Pointer to a const FPU register. */
3069typedef X86FPUREG const *PCX86FPUREG;
3070
3071/**
3072 * XMM register union.
3073 */
3074typedef union X86XMMREG
3075{
3076 /** XMM Register view. */
3077 uint128_t xmm;
3078 /** 8-bit view. */
3079 uint8_t au8[16];
3080 /** 16-bit view. */
3081 uint16_t au16[8];
3082 /** 32-bit view. */
3083 uint32_t au32[4];
3084 /** 64-bit view. */
3085 uint64_t au64[2];
3086 /** 128-bit view. (yeah, very helpful) */
3087 uint128_t au128[1];
3088#ifndef VBOX_FOR_DTRACE_LIB
3089 /** Confusing nested 128-bit union view (this is what xmm should've been). */
3090 RTUINT128U uXmm;
3091#endif
3092} X86XMMREG;
3093#ifndef VBOX_FOR_DTRACE_LIB
3094AssertCompileSize(X86XMMREG, 16);
3095#endif
3096/** Pointer to an XMM register state. */
3097typedef X86XMMREG *PX86XMMREG;
3098/** Pointer to a const XMM register state. */
3099typedef X86XMMREG const *PCX86XMMREG;
3100
3101/**
3102 * YMM register union.
3103 */
3104typedef union X86YMMREG
3105{
3106 /** 8-bit view. */
3107 uint8_t au8[32];
3108 /** 16-bit view. */
3109 uint16_t au16[16];
3110 /** 32-bit view. */
3111 uint32_t au32[8];
3112 /** 64-bit view. */
3113 uint64_t au64[4];
3114 /** 128-bit view. (yeah, very helpful) */
3115 uint128_t au128[2];
3116 /** XMM sub register view. */
3117 X86XMMREG aXmm[2];
3118} X86YMMREG;
3119#ifndef VBOX_FOR_DTRACE_LIB
3120AssertCompileSize(X86YMMREG, 32);
3121#endif
3122/** Pointer to an YMM register state. */
3123typedef X86YMMREG *PX86YMMREG;
3124/** Pointer to a const YMM register state. */
3125typedef X86YMMREG const *PCX86YMMREG;
3126
3127/**
3128 * ZMM register union.
3129 */
3130typedef union X86ZMMREG
3131{
3132 /** 8-bit view. */
3133 uint8_t au8[64];
3134 /** 16-bit view. */
3135 uint16_t au16[32];
3136 /** 32-bit view. */
3137 uint32_t au32[16];
3138 /** 64-bit view. */
3139 uint64_t au64[8];
3140 /** 128-bit view. (yeah, very helpful) */
3141 uint128_t au128[4];
3142 /** XMM sub register view. */
3143 X86XMMREG aXmm[4];
3144 /** YMM sub register view. */
3145 X86YMMREG aYmm[2];
3146} X86ZMMREG;
3147#ifndef VBOX_FOR_DTRACE_LIB
3148AssertCompileSize(X86ZMMREG, 64);
3149#endif
3150/** Pointer to an ZMM register state. */
3151typedef X86ZMMREG *PX86ZMMREG;
3152/** Pointer to a const ZMM register state. */
3153typedef X86ZMMREG const *PCX86ZMMREG;
3154
3155
3156/**
3157 * 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3158 * @todo verify this...
3159 */
3160#pragma pack(1)
3161typedef struct X86FPUSTATE
3162{
3163 /** 0x00 - Control word. */
3164 uint16_t FCW;
3165 /** 0x02 - Alignment word */
3166 uint16_t Dummy1;
3167 /** 0x04 - Status word. */
3168 uint16_t FSW;
3169 /** 0x06 - Alignment word */
3170 uint16_t Dummy2;
3171 /** 0x08 - Tag word */
3172 uint16_t FTW;
3173 /** 0x0a - Alignment word */
3174 uint16_t Dummy3;
3175
3176 /** 0x0c - Instruction pointer. */
3177 uint32_t FPUIP;
3178 /** 0x10 - Code selector. */
3179 uint16_t CS;
3180 /** 0x12 - Opcode. */
3181 uint16_t FOP;
3182 /** 0x14 - FOO. */
3183 uint32_t FPUOO;
3184 /** 0x18 - FOS. */
3185 uint32_t FPUOS;
3186 /** 0x1c - FPU register. */
3187 X86FPUREG regs[8];
3188} X86FPUSTATE;
3189#pragma pack()
3190/** Pointer to a FPU state. */
3191typedef X86FPUSTATE *PX86FPUSTATE;
3192/** Pointer to a const FPU state. */
3193typedef const X86FPUSTATE *PCX86FPUSTATE;
3194
3195/**
3196 * FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3197 */
3198#pragma pack(1)
3199typedef struct X86FXSTATE
3200{
3201 /** 0x00 - Control word. */
3202 uint16_t FCW;
3203 /** 0x02 - Status word. */
3204 uint16_t FSW;
3205 /** 0x04 - Tag word. (The upper byte is always zero.) */
3206 uint16_t FTW;
3207 /** 0x06 - Opcode. */
3208 uint16_t FOP;
3209 /** 0x08 - Instruction pointer. */
3210 uint32_t FPUIP;
3211 /** 0x0c - Code selector. */
3212 uint16_t CS;
3213 uint16_t Rsrvd1;
3214 /** 0x10 - Data pointer. */
3215 uint32_t FPUDP;
3216 /** 0x14 - Data segment */
3217 uint16_t DS;
3218 /** 0x16 */
3219 uint16_t Rsrvd2;
3220 /** 0x18 */
3221 uint32_t MXCSR;
3222 /** 0x1c */
3223 uint32_t MXCSR_MASK;
3224 /** 0x20 - FPU registers. */
3225 X86FPUREG aRegs[8];
3226 /** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3227 X86XMMREG aXMM[16];
3228 /* - offset 416 - */
3229 uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3230 /* - offset 464 - Software usable reserved bits. */
3231 uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3232} X86FXSTATE;
3233#pragma pack()
3234/** Pointer to a FPU Extended state. */
3235typedef X86FXSTATE *PX86FXSTATE;
3236/** Pointer to a const FPU Extended state. */
3237typedef const X86FXSTATE *PCX86FXSTATE;
3238
3239/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3240 * magic. Don't forget to update x86.mac if you change this! */
3241#define X86_OFF_FXSTATE_RSVD 0x1d0
3242/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3243 * forget to update x86.mac if you change this!
3244 * @todo r=bird: This has nothing what-so-ever to do here.... */
3245#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3246#ifndef VBOX_FOR_DTRACE_LIB
3247AssertCompileSize(X86FXSTATE, 512);
3248AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3249#endif
3250
3251/** @name FPU status word flags.
3252 * @{ */
3253/** Exception Flag: Invalid operation. */
3254#define X86_FSW_IE RT_BIT_32(0)
3255/** Exception Flag: Denormalized operand. */
3256#define X86_FSW_DE RT_BIT_32(1)
3257/** Exception Flag: Zero divide. */
3258#define X86_FSW_ZE RT_BIT_32(2)
3259/** Exception Flag: Overflow. */
3260#define X86_FSW_OE RT_BIT_32(3)
3261/** Exception Flag: Underflow. */
3262#define X86_FSW_UE RT_BIT_32(4)
3263/** Exception Flag: Precision. */
3264#define X86_FSW_PE RT_BIT_32(5)
3265/** Stack fault. */
3266#define X86_FSW_SF RT_BIT_32(6)
3267/** Error summary status. */
3268#define X86_FSW_ES RT_BIT_32(7)
3269/** Mask of exceptions flags, excluding the summary bit. */
3270#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3271/** Mask of exceptions flags, including the summary bit. */
3272#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3273/** Condition code 0. */
3274#define X86_FSW_C0 RT_BIT_32(X86_FSW_C0_BIT)
3275#define X86_FSW_C0_BIT 8
3276/** Condition code 1. */
3277#define X86_FSW_C1 RT_BIT_32(X86_FSW_C1_BIT)
3278#define X86_FSW_C1_BIT 9
3279/** Condition code 2. */
3280#define X86_FSW_C2 RT_BIT_32(X86_FSW_C2_BIT)
3281#define X86_FSW_C2_BIT 10
3282/** Top of the stack mask. */
3283#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3284/** TOP shift value. */
3285#define X86_FSW_TOP_SHIFT 11
3286/** Mask for getting TOP value after shifting it right. */
3287#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3288/** Get the TOP value. */
3289#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3290/** Get the TOP value offsetted by a_iSt (0-7). */
3291#define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK)
3292/** Condition code 3. */
3293#define X86_FSW_C3 RT_BIT_32(X86_FSW_C3_BIT)
3294#define X86_FSW_C3_BIT 14
3295/** Mask of exceptions flags, including the summary bit. */
3296#define X86_FSW_C_MASK UINT16_C(0x4700)
3297/** FPU busy. */
3298#define X86_FSW_B RT_BIT_32(15)
3299/** For use with FPREM and FPREM1. */
3300#define X86_FSW_CX_TO_QUOTIENT(a_fFsw) \
3301 ( (((a_fFsw) & X86_FSW_C1) >> (X86_FSW_C1_BIT - 0)) \
3302 | (((a_fFsw) & X86_FSW_C3) >> (X86_FSW_C3_BIT - 1)) \
3303 | (((a_fFsw) & X86_FSW_C0) >> (X86_FSW_C0_BIT - 2)) )
3304/** For use with FPREM and FPREM1. */
3305#define X86_FSW_CX_FROM_QUOTIENT(a_uQuotient) \
3306 ( ((uint16_t)((a_uQuotient) & 1) << (X86_FSW_C1_BIT - 0)) \
3307 | ((uint16_t)((a_uQuotient) & 2) << (X86_FSW_C3_BIT - 1)) \
3308 | ((uint16_t)((a_uQuotient) & 4) << (X86_FSW_C0_BIT - 2)) )
3309/** @} */
3310
3311
3312/** @name FPU control word flags.
3313 * @{ */
3314/** Exception Mask: Invalid operation. */
3315#define X86_FCW_IM RT_BIT_32(0)
3316#define X86_FCW_IM_BIT 0
3317/** Exception Mask: Denormalized operand. */
3318#define X86_FCW_DM RT_BIT_32(1)
3319#define X86_FCW_DM_BIT 1
3320/** Exception Mask: Zero divide. */
3321#define X86_FCW_ZM RT_BIT_32(2)
3322#define X86_FCW_ZM_BIT 2
3323/** Exception Mask: Overflow. */
3324#define X86_FCW_OM RT_BIT_32(3)
3325#define X86_FCW_OM_BIT 3
3326/** Exception Mask: Underflow. */
3327#define X86_FCW_UM RT_BIT_32(4)
3328#define X86_FCW_UM_BIT 4
3329/** Exception Mask: Precision. */
3330#define X86_FCW_PM RT_BIT_32(5)
3331#define X86_FCW_PM_BIT 5
3332/** Mask all exceptions, the value typically loaded (by for instance fninit).
3333 * @remarks This includes reserved bit 6. */
3334#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3335/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3336#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3337/** Precision control mask. */
3338#define X86_FCW_PC_MASK UINT16_C(0x0300)
3339/** Precision control shift. */
3340#define X86_FCW_PC_SHIFT 8
3341/** Precision control: 24-bit. */
3342#define X86_FCW_PC_24 UINT16_C(0x0000)
3343/** Precision control: Reserved. */
3344#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3345/** Precision control: 53-bit. */
3346#define X86_FCW_PC_53 UINT16_C(0x0200)
3347/** Precision control: 64-bit. */
3348#define X86_FCW_PC_64 UINT16_C(0x0300)
3349/** Rounding control mask. */
3350#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3351/** Rounding control shift. */
3352#define X86_FCW_RC_SHIFT 10
3353/** Rounding control: To nearest. */
3354#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3355/** Rounding control: Down. */
3356#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3357/** Rounding control: Up. */
3358#define X86_FCW_RC_UP UINT16_C(0x0800)
3359/** Rounding control: Towards zero. */
3360#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3361/** Infinity control mask - obsolete, 8087 & 287 only. */
3362#define X86_FCW_IC_MASK UINT16_C(0x1000)
3363/** Infinity control: Affine - positive infinity is distictly different from
3364 * negative infinity.
3365 * @note 8087, 287 only */
3366#define X86_FCW_IC_AFFINE UINT16_C(0x1000)
3367/** Infinity control: Projective - positive and negative infinity are the
3368 * same (sign ignored).
3369 * @note 8087, 287 only */
3370#define X86_FCW_IC_PROJECTIVE UINT16_C(0x0000)
3371/** Bits which should be zero, apparently. */
3372#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3373/** @} */
3374
3375/** @name SSE MXCSR
3376 * @{ */
3377/** Exception Flag: Invalid operation. */
3378#define X86_MXCSR_IE RT_BIT_32(0)
3379/** Exception Flag: Denormalized operand. */
3380#define X86_MXCSR_DE RT_BIT_32(1)
3381/** Exception Flag: Zero divide. */
3382#define X86_MXCSR_ZE RT_BIT_32(2)
3383/** Exception Flag: Overflow. */
3384#define X86_MXCSR_OE RT_BIT_32(3)
3385/** Exception Flag: Underflow. */
3386#define X86_MXCSR_UE RT_BIT_32(4)
3387/** Exception Flag: Precision. */
3388#define X86_MXCSR_PE RT_BIT_32(5)
3389
3390/** Denormals are zero. */
3391#define X86_MXCSR_DAZ RT_BIT_32(6)
3392
3393/** Exception Mask: Invalid operation. */
3394#define X86_MXCSR_IM RT_BIT_32(7)
3395/** Exception Mask: Denormalized operand. */
3396#define X86_MXCSR_DM RT_BIT_32(8)
3397/** Exception Mask: Zero divide. */
3398#define X86_MXCSR_ZM RT_BIT_32(9)
3399/** Exception Mask: Overflow. */
3400#define X86_MXCSR_OM RT_BIT_32(10)
3401/** Exception Mask: Underflow. */
3402#define X86_MXCSR_UM RT_BIT_32(11)
3403/** Exception Mask: Precision. */
3404#define X86_MXCSR_PM RT_BIT_32(12)
3405
3406/** Rounding control mask. */
3407#define X86_MXCSR_RC_MASK UINT16_C(0x6000)
3408/** Rounding control: To nearest. */
3409#define X86_MXCSR_RC_NEAREST UINT16_C(0x0000)
3410/** Rounding control: Down. */
3411#define X86_MXCSR_RC_DOWN UINT16_C(0x2000)
3412/** Rounding control: Up. */
3413#define X86_MXCSR_RC_UP UINT16_C(0x4000)
3414/** Rounding control: Towards zero. */
3415#define X86_MXCSR_RC_ZERO UINT16_C(0x6000)
3416
3417/** Flush-to-zero for masked underflow. */
3418#define X86_MXCSR_FZ RT_BIT_32(15)
3419
3420/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3421#define X86_MXCSR_MM RT_BIT_32(17)
3422/** @} */
3423
3424/**
3425 * XSAVE header.
3426 */
3427typedef struct X86XSAVEHDR
3428{
3429 /** XTATE_BV - Bitmap indicating whether a component is in the state. */
3430 uint64_t bmXState;
3431 /** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3432 uint64_t bmXComp;
3433 /** Reserved for furture extensions, probably MBZ. */
3434 uint64_t au64Reserved[6];
3435} X86XSAVEHDR;
3436#ifndef VBOX_FOR_DTRACE_LIB
3437AssertCompileSize(X86XSAVEHDR, 64);
3438#endif
3439/** Pointer to an XSAVE header. */
3440typedef X86XSAVEHDR *PX86XSAVEHDR;
3441/** Pointer to a const XSAVE header. */
3442typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3443
3444
3445/**
3446 * The high 128-bit YMM register state (XSAVE_C_YMM).
3447 * (The lower 128-bits being in X86FXSTATE.)
3448 */
3449typedef struct X86XSAVEYMMHI
3450{
3451 /** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3452 X86XMMREG aYmmHi[16];
3453} X86XSAVEYMMHI;
3454#ifndef VBOX_FOR_DTRACE_LIB
3455AssertCompileSize(X86XSAVEYMMHI, 256);
3456#endif
3457/** Pointer to a high 128-bit YMM register state. */
3458typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3459/** Pointer to a const high 128-bit YMM register state. */
3460typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3461
3462/**
3463 * Intel MPX bound registers state (XSAVE_C_BNDREGS).
3464 */
3465typedef struct X86XSAVEBNDREGS
3466{
3467 /** Array of registers (BND0...BND3). */
3468 struct
3469 {
3470 /** Lower bound. */
3471 uint64_t uLowerBound;
3472 /** Upper bound. */
3473 uint64_t uUpperBound;
3474 } aRegs[4];
3475} X86XSAVEBNDREGS;
3476#ifndef VBOX_FOR_DTRACE_LIB
3477AssertCompileSize(X86XSAVEBNDREGS, 64);
3478#endif
3479/** Pointer to a MPX bound register state. */
3480typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3481/** Pointer to a const MPX bound register state. */
3482typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3483
3484/**
3485 * Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3486 */
3487typedef struct X86XSAVEBNDCFG
3488{
3489 uint64_t fConfig;
3490 uint64_t fStatus;
3491} X86XSAVEBNDCFG;
3492#ifndef VBOX_FOR_DTRACE_LIB
3493AssertCompileSize(X86XSAVEBNDCFG, 16);
3494#endif
3495/** Pointer to a MPX bound config and status register state. */
3496typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3497/** Pointer to a const MPX bound config and status register state. */
3498typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3499
3500/**
3501 * AVX-512 opmask state (XSAVE_C_OPMASK).
3502 */
3503typedef struct X86XSAVEOPMASK
3504{
3505 /** The K0..K7 values. */
3506 uint64_t aKRegs[8];
3507} X86XSAVEOPMASK;
3508#ifndef VBOX_FOR_DTRACE_LIB
3509AssertCompileSize(X86XSAVEOPMASK, 64);
3510#endif
3511/** Pointer to a AVX-512 opmask state. */
3512typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3513/** Pointer to a const AVX-512 opmask state. */
3514typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3515
3516/**
3517 * ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3518 */
3519typedef struct X86XSAVEZMMHI256
3520{
3521 /** Upper 256-bits of ZMM0-15. */
3522 X86YMMREG aHi256Regs[16];
3523} X86XSAVEZMMHI256;
3524#ifndef VBOX_FOR_DTRACE_LIB
3525AssertCompileSize(X86XSAVEZMMHI256, 512);
3526#endif
3527/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3528typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3529/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3530typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3531
3532/**
3533 * ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3534 */
3535typedef struct X86XSAVEZMM16HI
3536{
3537 /** ZMM16 thru ZMM31. */
3538 X86ZMMREG aRegs[16];
3539} X86XSAVEZMM16HI;
3540#ifndef VBOX_FOR_DTRACE_LIB
3541AssertCompileSize(X86XSAVEZMM16HI, 1024);
3542#endif
3543/** Pointer to a state comprising ZMM16-32. */
3544typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3545/** Pointer to a const state comprising ZMM16-32. */
3546typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3547
3548/**
3549 * AMD Light weight profiling state (XSAVE_C_LWP).
3550 *
3551 * We probably won't play with this as AMD seems to be dropping from their "zen"
3552 * processor micro architecture.
3553 */
3554typedef struct X86XSAVELWP
3555{
3556 /** Details when needed. */
3557 uint64_t auLater[128/8];
3558} X86XSAVELWP;
3559#ifndef VBOX_FOR_DTRACE_LIB
3560AssertCompileSize(X86XSAVELWP, 128);
3561#endif
3562
3563
3564/**
3565 * x86 FPU/SSE/AVX/XXXX state.
3566 *
3567 * Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3568 * changes to this structure.
3569 */
3570typedef struct X86XSAVEAREA
3571{
3572 /** The x87 and SSE region (or legacy region if you like). */
3573 X86FXSTATE x87;
3574 /** The XSAVE header. */
3575 X86XSAVEHDR Hdr;
3576 /** Beyond the header, there isn't really a fixed layout, but we can
3577 generally assume the YMM (AVX) register extensions are present and
3578 follows immediately. */
3579 union
3580 {
3581 /** The high 128-bit AVX registers for easy access by IEM.
3582 * @note This ASSUMES they will always be here... */
3583 X86XSAVEYMMHI YmmHi;
3584
3585 /** This is a typical layout on intel CPUs (good for debuggers). */
3586 struct
3587 {
3588 X86XSAVEYMMHI YmmHi;
3589 X86XSAVEBNDREGS BndRegs;
3590 X86XSAVEBNDCFG BndCfg;
3591 uint8_t abFudgeToMatchDocs[0xB0];
3592 X86XSAVEOPMASK Opmask;
3593 X86XSAVEZMMHI256 ZmmHi256;
3594 X86XSAVEZMM16HI Zmm16Hi;
3595 } Intel;
3596
3597 /** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3598 struct
3599 {
3600 X86XSAVEYMMHI YmmHi;
3601 X86XSAVELWP Lwp;
3602 } AmdBd;
3603
3604 /** To enbling static deployments that have a reasonable chance of working for
3605 * the next 3-6 CPU generations without running short on space, we allocate a
3606 * lot of extra space here, making the structure a round 8KB in size. This
3607 * leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3608 * 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3609 uint8_t ab[8192 - 512 - 64];
3610 } u;
3611} X86XSAVEAREA;
3612#ifndef VBOX_FOR_DTRACE_LIB
3613AssertCompileSize(X86XSAVEAREA, 8192);
3614AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /*2112 => total 0xa80 (2688) */);
3615AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3616AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3617AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3618AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3619AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3620AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3621AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3622#endif
3623/** Pointer to a XSAVE area. */
3624typedef X86XSAVEAREA *PX86XSAVEAREA;
3625/** Pointer to a const XSAVE area. */
3626typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3627
3628
3629/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3630 * @{ */
3631/** Bit 0 - x87 - Legacy FPU state (bit number) */
3632#define XSAVE_C_X87_BIT 0
3633/** Bit 0 - x87 - Legacy FPU state. */
3634#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3635/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3636#define XSAVE_C_SSE_BIT 1
3637/** Bit 1 - SSE - 128-bit SSE state. */
3638#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3639/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3640#define XSAVE_C_YMM_BIT 2
3641/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3642#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3643/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3644#define XSAVE_C_BNDREGS_BIT 3
3645/** Bit 3 - BNDREGS - MPX bound register state. */
3646#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3647/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3648#define XSAVE_C_BNDCSR_BIT 4
3649/** Bit 4 - BNDCSR - MPX bound config and status state. */
3650#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3651/** Bit 5 - Opmask - opmask state (bit number). */
3652#define XSAVE_C_OPMASK_BIT 5
3653/** Bit 5 - Opmask - opmask state. */
3654#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3655/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3656#define XSAVE_C_ZMM_HI256_BIT 6
3657/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3658#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3659/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3660#define XSAVE_C_ZMM_16HI_BIT 7
3661/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3662#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3663/** Bit 9 - PKRU - Protection-key state (bit number). */
3664#define XSAVE_C_PKRU_BIT 9
3665/** Bit 9 - PKRU - Protection-key state. */
3666#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3667/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3668#define XSAVE_C_LWP_BIT 62
3669/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3670#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3671/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3672#define XSAVE_C_X_BIT 63
3673/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3674#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3675/** @} */
3676
3677
3678
3679/** @name Selector Descriptor
3680 * @{
3681 */
3682
3683#ifndef VBOX_FOR_DTRACE_LIB
3684/**
3685 * Descriptor attributes (as seen by VT-x).
3686 */
3687typedef struct X86DESCATTRBITS
3688{
3689 /** 00 - Segment Type. */
3690 unsigned u4Type : 4;
3691 /** 04 - Descriptor Type. System(=0) or code/data selector */
3692 unsigned u1DescType : 1;
3693 /** 05 - Descriptor Privilege level. */
3694 unsigned u2Dpl : 2;
3695 /** 07 - Flags selector present(=1) or not. */
3696 unsigned u1Present : 1;
3697 /** 08 - Segment limit 16-19. */
3698 unsigned u4LimitHigh : 4;
3699 /** 0c - Available for system software. */
3700 unsigned u1Available : 1;
3701 /** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3702 unsigned u1Long : 1;
3703 /** 0e - This flags meaning depends on the segment type. Try make sense out
3704 * of the intel manual yourself. */
3705 unsigned u1DefBig : 1;
3706 /** 0f - Granularity of the limit. If set 4KB granularity is used, if
3707 * clear byte. */
3708 unsigned u1Granularity : 1;
3709 /** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3710 unsigned u1Unusable : 1;
3711} X86DESCATTRBITS;
3712#endif /* !VBOX_FOR_DTRACE_LIB */
3713
3714/** @name X86DESCATTR masks
3715 * @{ */
3716#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3717#define X86DESCATTR_DT UINT32_C(0x00000010)
3718#define X86DESCATTR_DPL UINT32_C(0x00000060)
3719#define X86DESCATTR_DPL_SHIFT 5 /**< Shift count for the DPL value. */
3720#define X86DESCATTR_P UINT32_C(0x00000080)
3721#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3722#define X86DESCATTR_AVL UINT32_C(0x00001000)
3723#define X86DESCATTR_L UINT32_C(0x00002000)
3724#define X86DESCATTR_D UINT32_C(0x00004000)
3725#define X86DESCATTR_G UINT32_C(0x00008000)
3726#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3727/** @} */
3728
3729#pragma pack(1)
3730typedef union X86DESCATTR
3731{
3732 /** Unsigned integer view. */
3733 uint32_t u;
3734#ifndef VBOX_FOR_DTRACE_LIB
3735 /** Normal view. */
3736 X86DESCATTRBITS n;
3737#endif
3738} X86DESCATTR;
3739#pragma pack()
3740/** Pointer to descriptor attributes. */
3741typedef X86DESCATTR *PX86DESCATTR;
3742/** Pointer to const descriptor attributes. */
3743typedef const X86DESCATTR *PCX86DESCATTR;
3744
3745#ifndef VBOX_FOR_DTRACE_LIB
3746
3747/**
3748 * Generic descriptor table entry
3749 */
3750#pragma pack(1)
3751typedef struct X86DESCGENERIC
3752{
3753 /** 00 - Limit - Low word. */
3754 unsigned u16LimitLow : 16;
3755 /** 10 - Base address - low word.
3756 * Don't try set this to 24 because MSC is doing stupid things then. */
3757 unsigned u16BaseLow : 16;
3758 /** 20 - Base address - first 8 bits of high word. */
3759 unsigned u8BaseHigh1 : 8;
3760 /** 28 - Segment Type. */
3761 unsigned u4Type : 4;
3762 /** 2c - Descriptor Type. System(=0) or code/data selector */
3763 unsigned u1DescType : 1;
3764 /** 2d - Descriptor Privilege level. */
3765 unsigned u2Dpl : 2;
3766 /** 2f - Flags selector present(=1) or not. */
3767 unsigned u1Present : 1;
3768 /** 30 - Segment limit 16-19. */
3769 unsigned u4LimitHigh : 4;
3770 /** 34 - Available for system software. */
3771 unsigned u1Available : 1;
3772 /** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3773 unsigned u1Long : 1;
3774 /** 36 - This flags meaning depends on the segment type. Try make sense out
3775 * of the intel manual yourself. */
3776 unsigned u1DefBig : 1;
3777 /** 37 - Granularity of the limit. If set 4KB granularity is used, if
3778 * clear byte. */
3779 unsigned u1Granularity : 1;
3780 /** 38 - Base address - highest 8 bits. */
3781 unsigned u8BaseHigh2 : 8;
3782} X86DESCGENERIC;
3783#pragma pack()
3784/** Pointer to a generic descriptor entry. */
3785typedef X86DESCGENERIC *PX86DESCGENERIC;
3786/** Pointer to a const generic descriptor entry. */
3787typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3788
3789/** @name Bit offsets of X86DESCGENERIC members.
3790 * @{*/
3791#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /**< Bit offset of X86DESCGENERIC::u16LimitLow. */
3792#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /**< Bit offset of X86DESCGENERIC::u16BaseLow. */
3793#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /**< Bit offset of X86DESCGENERIC::u8BaseHigh1. */
3794#define X86DESCGENERIC_BIT_OFF_TYPE (40) /**< Bit offset of X86DESCGENERIC::u4Type. */
3795#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /**< Bit offset of X86DESCGENERIC::u1DescType. */
3796#define X86DESCGENERIC_BIT_OFF_DPL (45) /**< Bit offset of X86DESCGENERIC::u2Dpl. */
3797#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /**< Bit offset of X86DESCGENERIC::uu1Present. */
3798#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /**< Bit offset of X86DESCGENERIC::u4LimitHigh. */
3799#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /**< Bit offset of X86DESCGENERIC::u1Available. */
3800#define X86DESCGENERIC_BIT_OFF_LONG (53) /**< Bit offset of X86DESCGENERIC::u1Long. */
3801#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /**< Bit offset of X86DESCGENERIC::u1DefBig. */
3802#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /**< Bit offset of X86DESCGENERIC::u1Granularity. */
3803#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /**< Bit offset of X86DESCGENERIC::u8BaseHigh2. */
3804/** @} */
3805
3806
3807/** @name LAR mask
3808 * @{ */
3809#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3810#define X86LAR_F_DT UINT16_C( 0x1000)
3811#define X86LAR_F_DPL UINT16_C( 0x6000)
3812#define X86LAR_F_DPL_SHIFT 13 /**< Shift count for the DPL value. */
3813#define X86LAR_F_P UINT16_C( 0x8000)
3814#define X86LAR_F_AVL UINT32_C(0x00100000)
3815#define X86LAR_F_L UINT32_C(0x00200000)
3816#define X86LAR_F_D UINT32_C(0x00400000)
3817#define X86LAR_F_G UINT32_C(0x00800000)
3818/** @} */
3819
3820
3821/**
3822 * Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3823 */
3824typedef struct X86DESCGATE
3825{
3826 /** 00 - Target code segment offset - Low word.
3827 * Ignored if task-gate. */
3828 unsigned u16OffsetLow : 16;
3829 /** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3830 * TSS selector if task-gate. */
3831 unsigned u16Sel : 16;
3832 /** 20 - Number of parameters for a call-gate.
3833 * Ignored if interrupt-, trap- or task-gate. */
3834 unsigned u5ParmCount : 5;
3835 /** 25 - Reserved / ignored. */
3836 unsigned u3Reserved : 3;
3837 /** 28 - Segment Type. */
3838 unsigned u4Type : 4;
3839 /** 2c - Descriptor Type (0 = system). */
3840 unsigned u1DescType : 1;
3841 /** 2d - Descriptor Privilege level. */
3842 unsigned u2Dpl : 2;
3843 /** 2f - Flags selector present(=1) or not. */
3844 unsigned u1Present : 1;
3845 /** 30 - Target code segment offset - High word.
3846 * Ignored if task-gate. */
3847 unsigned u16OffsetHigh : 16;
3848} X86DESCGATE;
3849/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3850typedef X86DESCGATE *PX86DESCGATE;
3851/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3852typedef const X86DESCGATE *PCX86DESCGATE;
3853
3854#endif /* VBOX_FOR_DTRACE_LIB */
3855
3856/**
3857 * Descriptor table entry.
3858 */
3859#pragma pack(1)
3860typedef union X86DESC
3861{
3862#ifndef VBOX_FOR_DTRACE_LIB
3863 /** Generic descriptor view. */
3864 X86DESCGENERIC Gen;
3865 /** Gate descriptor view. */
3866 X86DESCGATE Gate;
3867#endif
3868
3869 /** 8 bit unsigned integer view. */
3870 uint8_t au8[8];
3871 /** 16 bit unsigned integer view. */
3872 uint16_t au16[4];
3873 /** 32 bit unsigned integer view. */
3874 uint32_t au32[2];
3875 /** 64 bit unsigned integer view. */
3876 uint64_t au64[1];
3877 /** Unsigned integer view. */
3878 uint64_t u;
3879} X86DESC;
3880#ifndef VBOX_FOR_DTRACE_LIB
3881AssertCompileSize(X86DESC, 8);
3882#endif
3883#pragma pack()
3884/** Pointer to descriptor table entry. */
3885typedef X86DESC *PX86DESC;
3886/** Pointer to const descriptor table entry. */
3887typedef const X86DESC *PCX86DESC;
3888
3889/** @def X86DESC_BASE
3890 * Return the base address of a descriptor.
3891 */
3892#define X86DESC_BASE(a_pDesc) /*ASM-NOINC*/ \
3893 ( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3894 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3895 | ( (a_pDesc)->Gen.u16BaseLow ) )
3896
3897/** @def X86DESC_LIMIT
3898 * Return the limit of a descriptor.
3899 */
3900#define X86DESC_LIMIT(a_pDesc) /*ASM-NOINC*/ \
3901 ( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3902 | ( (a_pDesc)->Gen.u16LimitLow ) )
3903
3904/** @def X86DESC_LIMIT_G
3905 * Return the limit of a descriptor with the granularity bit taken into account.
3906 * @returns Selector limit (uint32_t).
3907 * @param a_pDesc Pointer to the descriptor.
3908 */
3909#define X86DESC_LIMIT_G(a_pDesc) /*ASM-NOINC*/ \
3910 ( (a_pDesc)->Gen.u1Granularity \
3911 ? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow ) << 12 ) | UINT32_C(0xfff) \
3912 : ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) | (a_pDesc)->Gen.u16LimitLow \
3913 )
3914
3915/** @def X86DESC_GET_HID_ATTR
3916 * Get the descriptor attributes for the hidden register.
3917 */
3918#define X86DESC_GET_HID_ATTR(a_pDesc) /*ASM-NOINC*/ \
3919 ( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3920
3921#ifndef VBOX_FOR_DTRACE_LIB
3922
3923/**
3924 * 64 bits generic descriptor table entry
3925 * Note: most of these bits have no meaning in long mode.
3926 */
3927#pragma pack(1)
3928typedef struct X86DESC64GENERIC
3929{
3930 /** Limit - Low word - *IGNORED*. */
3931 uint32_t u16LimitLow : 16;
3932 /** Base address - low word. - *IGNORED*
3933 * Don't try set this to 24 because MSC is doing stupid things then. */
3934 uint32_t u16BaseLow : 16;
3935 /** Base address - first 8 bits of high word. - *IGNORED* */
3936 uint32_t u8BaseHigh1 : 8;
3937 /** Segment Type. */
3938 uint32_t u4Type : 4;
3939 /** Descriptor Type. System(=0) or code/data selector */
3940 uint32_t u1DescType : 1;
3941 /** Descriptor Privilege level. */
3942 uint32_t u2Dpl : 2;
3943 /** Flags selector present(=1) or not. */
3944 uint32_t u1Present : 1;
3945 /** Segment limit 16-19. - *IGNORED* */
3946 uint32_t u4LimitHigh : 4;
3947 /** Available for system software. - *IGNORED* */
3948 uint32_t u1Available : 1;
3949 /** Long mode flag. */
3950 uint32_t u1Long : 1;
3951 /** This flags meaning depends on the segment type. Try make sense out
3952 * of the intel manual yourself. */
3953 uint32_t u1DefBig : 1;
3954 /** Granularity of the limit. If set 4KB granularity is used, if
3955 * clear byte. - *IGNORED* */
3956 uint32_t u1Granularity : 1;
3957 /** Base address - highest 8 bits. - *IGNORED* */
3958 uint32_t u8BaseHigh2 : 8;
3959 /** Base address - bits 63-32. */
3960 uint32_t u32BaseHigh3 : 32;
3961 uint32_t u8Reserved : 8;
3962 uint32_t u5Zeros : 5;
3963 uint32_t u19Reserved : 19;
3964} X86DESC64GENERIC;
3965#pragma pack()
3966/** Pointer to a generic descriptor entry. */
3967typedef X86DESC64GENERIC *PX86DESC64GENERIC;
3968/** Pointer to a const generic descriptor entry. */
3969typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
3970
3971/**
3972 * System descriptor table entry (64 bits)
3973 *
3974 * @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
3975 */
3976#pragma pack(1)
3977typedef struct X86DESC64SYSTEM
3978{
3979 /** Limit - Low word. */
3980 uint32_t u16LimitLow : 16;
3981 /** Base address - low word.
3982 * Don't try set this to 24 because MSC is doing stupid things then. */
3983 uint32_t u16BaseLow : 16;
3984 /** Base address - first 8 bits of high word. */
3985 uint32_t u8BaseHigh1 : 8;
3986 /** Segment Type. */
3987 uint32_t u4Type : 4;
3988 /** Descriptor Type. System(=0) or code/data selector */
3989 uint32_t u1DescType : 1;
3990 /** Descriptor Privilege level. */
3991 uint32_t u2Dpl : 2;
3992 /** Flags selector present(=1) or not. */
3993 uint32_t u1Present : 1;
3994 /** Segment limit 16-19. */
3995 uint32_t u4LimitHigh : 4;
3996 /** Available for system software. */
3997 uint32_t u1Available : 1;
3998 /** Reserved - 0. */
3999 uint32_t u1Reserved : 1;
4000 /** This flags meaning depends on the segment type. Try make sense out
4001 * of the intel manual yourself. */
4002 uint32_t u1DefBig : 1;
4003 /** Granularity of the limit. If set 4KB granularity is used, if
4004 * clear byte. */
4005 uint32_t u1Granularity : 1;
4006 /** Base address - bits 31-24. */
4007 uint32_t u8BaseHigh2 : 8;
4008 /** Base address - bits 63-32. */
4009 uint32_t u32BaseHigh3 : 32;
4010 uint32_t u8Reserved : 8;
4011 uint32_t u5Zeros : 5;
4012 uint32_t u19Reserved : 19;
4013} X86DESC64SYSTEM;
4014#pragma pack()
4015/** Pointer to a system descriptor entry. */
4016typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
4017/** Pointer to a const system descriptor entry. */
4018typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
4019
4020/**
4021 * Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
4022 */
4023typedef struct X86DESC64GATE
4024{
4025 /** Target code segment offset - Low word. */
4026 uint32_t u16OffsetLow : 16;
4027 /** Target code segment selector. */
4028 uint32_t u16Sel : 16;
4029 /** Interrupt stack table for interrupt- and trap-gates.
4030 * Ignored by call-gates. */
4031 uint32_t u3IST : 3;
4032 /** Reserved / ignored. */
4033 uint32_t u5Reserved : 5;
4034 /** Segment Type. */
4035 uint32_t u4Type : 4;
4036 /** Descriptor Type (0 = system). */
4037 uint32_t u1DescType : 1;
4038 /** Descriptor Privilege level. */
4039 uint32_t u2Dpl : 2;
4040 /** Flags selector present(=1) or not. */
4041 uint32_t u1Present : 1;
4042 /** Target code segment offset - High word.
4043 * Ignored if task-gate. */
4044 uint32_t u16OffsetHigh : 16;
4045 /** Target code segment offset - Top dword.
4046 * Ignored if task-gate. */
4047 uint32_t u32OffsetTop : 32;
4048 /** Reserved / ignored / must be zero.
4049 * For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
4050 uint32_t u32Reserved : 32;
4051} X86DESC64GATE;
4052AssertCompileSize(X86DESC64GATE, 16);
4053/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4054typedef X86DESC64GATE *PX86DESC64GATE;
4055/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4056typedef const X86DESC64GATE *PCX86DESC64GATE;
4057
4058#endif /* VBOX_FOR_DTRACE_LIB */
4059
4060/**
4061 * Descriptor table entry.
4062 */
4063#pragma pack(1)
4064typedef union X86DESC64
4065{
4066#ifndef VBOX_FOR_DTRACE_LIB
4067 /** Generic descriptor view. */
4068 X86DESC64GENERIC Gen;
4069 /** System descriptor view. */
4070 X86DESC64SYSTEM System;
4071 /** Gate descriptor view. */
4072 X86DESC64GATE Gate;
4073#endif
4074
4075 /** 8 bit unsigned integer view. */
4076 uint8_t au8[16];
4077 /** 16 bit unsigned integer view. */
4078 uint16_t au16[8];
4079 /** 32 bit unsigned integer view. */
4080 uint32_t au32[4];
4081 /** 64 bit unsigned integer view. */
4082 uint64_t au64[2];
4083} X86DESC64;
4084#ifndef VBOX_FOR_DTRACE_LIB
4085AssertCompileSize(X86DESC64, 16);
4086#endif
4087#pragma pack()
4088/** Pointer to descriptor table entry. */
4089typedef X86DESC64 *PX86DESC64;
4090/** Pointer to const descriptor table entry. */
4091typedef const X86DESC64 *PCX86DESC64;
4092
4093/** @def X86DESC64_BASE
4094 * Return the base of a 64-bit descriptor.
4095 */
4096#define X86DESC64_BASE(a_pDesc) /*ASM-NOINC*/ \
4097 ( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
4098 | ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4099 | ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4100 | ( (a_pDesc)->Gen.u16BaseLow ) )
4101
4102
4103
4104/** @name Host system descriptor table entry - Use with care!
4105 * @{ */
4106/** Host system descriptor table entry. */
4107#if HC_ARCH_BITS == 64
4108typedef X86DESC64 X86DESCHC;
4109#else
4110typedef X86DESC X86DESCHC;
4111#endif
4112/** Pointer to a host system descriptor table entry. */
4113#if HC_ARCH_BITS == 64
4114typedef PX86DESC64 PX86DESCHC;
4115#else
4116typedef PX86DESC PX86DESCHC;
4117#endif
4118/** Pointer to a const host system descriptor table entry. */
4119#if HC_ARCH_BITS == 64
4120typedef PCX86DESC64 PCX86DESCHC;
4121#else
4122typedef PCX86DESC PCX86DESCHC;
4123#endif
4124/** @} */
4125
4126
4127/** @name Selector Descriptor Types.
4128 * @{
4129 */
4130
4131/** @name Non-System Selector Types.
4132 * @{ */
4133/** Code(=set)/Data(=clear) bit. */
4134#define X86_SEL_TYPE_CODE 8
4135/** Memory(=set)/System(=clear) bit. */
4136#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
4137/** Accessed bit. */
4138#define X86_SEL_TYPE_ACCESSED 1
4139/** Expand down bit (for data selectors only). */
4140#define X86_SEL_TYPE_DOWN 4
4141/** Conforming bit (for code selectors only). */
4142#define X86_SEL_TYPE_CONF 4
4143/** Write bit (for data selectors only). */
4144#define X86_SEL_TYPE_WRITE 2
4145/** Read bit (for code selectors only). */
4146#define X86_SEL_TYPE_READ 2
4147/** The bit number of the code segment read bit (relative to u4Type). */
4148#define X86_SEL_TYPE_READ_BIT 1
4149
4150/** Read only selector type. */
4151#define X86_SEL_TYPE_RO 0
4152/** Accessed read only selector type. */
4153#define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
4154/** Read write selector type. */
4155#define X86_SEL_TYPE_RW 2
4156/** Accessed read write selector type. */
4157#define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
4158/** Expand down read only selector type. */
4159#define X86_SEL_TYPE_RO_DOWN 4
4160/** Accessed expand down read only selector type. */
4161#define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
4162/** Expand down read write selector type. */
4163#define X86_SEL_TYPE_RW_DOWN 6
4164/** Accessed expand down read write selector type. */
4165#define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
4166/** Execute only selector type. */
4167#define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
4168/** Accessed execute only selector type. */
4169#define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4170/** Execute and read selector type. */
4171#define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
4172/** Accessed execute and read selector type. */
4173#define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4174/** Conforming execute only selector type. */
4175#define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
4176/** Accessed Conforming execute only selector type. */
4177#define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4178/** Conforming execute and write selector type. */
4179#define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
4180/** Accessed Conforming execute and write selector type. */
4181#define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
4182/** @} */
4183
4184
4185/** @name System Selector Types.
4186 * @{ */
4187/** The TSS busy bit mask. */
4188#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4189
4190/** Undefined system selector type. */
4191#define X86_SEL_TYPE_SYS_UNDEFINED 0
4192/** 286 TSS selector. */
4193#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4194/** LDT selector. */
4195#define X86_SEL_TYPE_SYS_LDT 2
4196/** 286 TSS selector - Busy. */
4197#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4198/** 286 Callgate selector. */
4199#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4200/** Taskgate selector. */
4201#define X86_SEL_TYPE_SYS_TASK_GATE 5
4202/** 286 Interrupt gate selector. */
4203#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4204/** 286 Trapgate selector. */
4205#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4206/** Undefined system selector. */
4207#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4208/** 386 TSS selector. */
4209#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4210/** Undefined system selector. */
4211#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4212/** 386 TSS selector - Busy. */
4213#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4214/** 386 Callgate selector. */
4215#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4216/** Undefined system selector. */
4217#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4218/** 386 Interruptgate selector. */
4219#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4220/** 386 Trapgate selector. */
4221#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4222/** @} */
4223
4224/** @name AMD64 System Selector Types.
4225 * @{ */
4226/** LDT selector. */
4227#define AMD64_SEL_TYPE_SYS_LDT 2
4228/** TSS selector - Busy. */
4229#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4230/** TSS selector - Busy. */
4231#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4232/** Callgate selector. */
4233#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4234/** Interruptgate selector. */
4235#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4236/** Trapgate selector. */
4237#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4238/** @} */
4239
4240/** @} */
4241
4242
4243/** @name Descriptor Table Entry Flag Masks.
4244 * These are for the 2nd 32-bit word of a descriptor.
4245 * @{ */
4246/** Bits 8-11 - TYPE - Descriptor type mask. */
4247#define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
4248/** Bit 12 - S - System (=0) or Code/Data (=1). */
4249#define X86_DESC_S RT_BIT_32(12)
4250/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4251#define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
4252/** Bit 15 - P - Present. */
4253#define X86_DESC_P RT_BIT_32(15)
4254/** Bit 20 - AVL - Available for system software. */
4255#define X86_DESC_AVL RT_BIT_32(20)
4256/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4257#define X86_DESC_DB RT_BIT_32(22)
4258/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4259 * used, if clear byte. */
4260#define X86_DESC_G RT_BIT_32(23)
4261/** @} */
4262
4263/** @} */
4264
4265
4266/** @name Task Segments.
4267 * @{
4268 */
4269
4270/**
4271 * The minimum TSS descriptor limit for 286 tasks.
4272 */
4273#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4274
4275/**
4276 * The minimum TSS descriptor segment limit for 386 tasks.
4277 */
4278#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4279
4280/**
4281 * 16-bit Task Segment (TSS).
4282 */
4283#pragma pack(1)
4284typedef struct X86TSS16
4285{
4286 /** Back link to previous task. (static) */
4287 RTSEL selPrev;
4288 /** Ring-0 stack pointer. (static) */
4289 uint16_t sp0;
4290 /** Ring-0 stack segment. (static) */
4291 RTSEL ss0;
4292 /** Ring-1 stack pointer. (static) */
4293 uint16_t sp1;
4294 /** Ring-1 stack segment. (static) */
4295 RTSEL ss1;
4296 /** Ring-2 stack pointer. (static) */
4297 uint16_t sp2;
4298 /** Ring-2 stack segment. (static) */
4299 RTSEL ss2;
4300 /** IP before task switch. */
4301 uint16_t ip;
4302 /** FLAGS before task switch. */
4303 uint16_t flags;
4304 /** AX before task switch. */
4305 uint16_t ax;
4306 /** CX before task switch. */
4307 uint16_t cx;
4308 /** DX before task switch. */
4309 uint16_t dx;
4310 /** BX before task switch. */
4311 uint16_t bx;
4312 /** SP before task switch. */
4313 uint16_t sp;
4314 /** BP before task switch. */
4315 uint16_t bp;
4316 /** SI before task switch. */
4317 uint16_t si;
4318 /** DI before task switch. */
4319 uint16_t di;
4320 /** ES before task switch. */
4321 RTSEL es;
4322 /** CS before task switch. */
4323 RTSEL cs;
4324 /** SS before task switch. */
4325 RTSEL ss;
4326 /** DS before task switch. */
4327 RTSEL ds;
4328 /** LDTR before task switch. */
4329 RTSEL selLdt;
4330} X86TSS16;
4331#ifndef VBOX_FOR_DTRACE_LIB
4332AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4333#endif
4334#pragma pack()
4335/** Pointer to a 16-bit task segment. */
4336typedef X86TSS16 *PX86TSS16;
4337/** Pointer to a const 16-bit task segment. */
4338typedef const X86TSS16 *PCX86TSS16;
4339
4340
4341/**
4342 * 32-bit Task Segment (TSS).
4343 */
4344#pragma pack(1)
4345typedef struct X86TSS32
4346{
4347 /** Back link to previous task. (static) */
4348 RTSEL selPrev;
4349 uint16_t padding1;
4350 /** Ring-0 stack pointer. (static) */
4351 uint32_t esp0;
4352 /** Ring-0 stack segment. (static) */
4353 RTSEL ss0;
4354 uint16_t padding_ss0;
4355 /** Ring-1 stack pointer. (static) */
4356 uint32_t esp1;
4357 /** Ring-1 stack segment. (static) */
4358 RTSEL ss1;
4359 uint16_t padding_ss1;
4360 /** Ring-2 stack pointer. (static) */
4361 uint32_t esp2;
4362 /** Ring-2 stack segment. (static) */
4363 RTSEL ss2;
4364 uint16_t padding_ss2;
4365 /** Page directory for the task. (static) */
4366 uint32_t cr3;
4367 /** EIP before task switch. */
4368 uint32_t eip;
4369 /** EFLAGS before task switch. */
4370 uint32_t eflags;
4371 /** EAX before task switch. */
4372 uint32_t eax;
4373 /** ECX before task switch. */
4374 uint32_t ecx;
4375 /** EDX before task switch. */
4376 uint32_t edx;
4377 /** EBX before task switch. */
4378 uint32_t ebx;
4379 /** ESP before task switch. */
4380 uint32_t esp;
4381 /** EBP before task switch. */
4382 uint32_t ebp;
4383 /** ESI before task switch. */
4384 uint32_t esi;
4385 /** EDI before task switch. */
4386 uint32_t edi;
4387 /** ES before task switch. */
4388 RTSEL es;
4389 uint16_t padding_es;
4390 /** CS before task switch. */
4391 RTSEL cs;
4392 uint16_t padding_cs;
4393 /** SS before task switch. */
4394 RTSEL ss;
4395 uint16_t padding_ss;
4396 /** DS before task switch. */
4397 RTSEL ds;
4398 uint16_t padding_ds;
4399 /** FS before task switch. */
4400 RTSEL fs;
4401 uint16_t padding_fs;
4402 /** GS before task switch. */
4403 RTSEL gs;
4404 uint16_t padding_gs;
4405 /** LDTR before task switch. */
4406 RTSEL selLdt;
4407 uint16_t padding_ldt;
4408 /** Debug trap flag */
4409 uint16_t fDebugTrap;
4410 /** Offset relative to the TSS of the start of the I/O Bitmap
4411 * and the end of the interrupt redirection bitmap. */
4412 uint16_t offIoBitmap;
4413} X86TSS32;
4414#pragma pack()
4415/** Pointer to task segment. */
4416typedef X86TSS32 *PX86TSS32;
4417/** Pointer to const task segment. */
4418typedef const X86TSS32 *PCX86TSS32;
4419#ifndef VBOX_FOR_DTRACE_LIB
4420AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4421AssertCompileMemberOffset(X86TSS32, cr3, 28);
4422AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4423#endif
4424
4425/**
4426 * 64-bit Task segment.
4427 */
4428#pragma pack(1)
4429typedef struct X86TSS64
4430{
4431 /** Reserved. */
4432 uint32_t u32Reserved;
4433 /** Ring-0 stack pointer. (static) */
4434 uint64_t rsp0;
4435 /** Ring-1 stack pointer. (static) */
4436 uint64_t rsp1;
4437 /** Ring-2 stack pointer. (static) */
4438 uint64_t rsp2;
4439 /** Reserved. */
4440 uint32_t u32Reserved2[2];
4441 /* IST */
4442 uint64_t ist1;
4443 uint64_t ist2;
4444 uint64_t ist3;
4445 uint64_t ist4;
4446 uint64_t ist5;
4447 uint64_t ist6;
4448 uint64_t ist7;
4449 /* Reserved. */
4450 uint16_t u16Reserved[5];
4451 /** Offset relative to the TSS of the start of the I/O Bitmap
4452 * and the end of the interrupt redirection bitmap. */
4453 uint16_t offIoBitmap;
4454} X86TSS64;
4455#pragma pack()
4456/** Pointer to a 64-bit task segment. */
4457typedef X86TSS64 *PX86TSS64;
4458/** Pointer to a const 64-bit task segment. */
4459typedef const X86TSS64 *PCX86TSS64;
4460#ifndef VBOX_FOR_DTRACE_LIB
4461AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4462#endif
4463
4464/** @} */
4465
4466
4467/** @name Selectors.
4468 * @{
4469 */
4470
4471/**
4472 * The shift used to convert a selector from and to index an index (C).
4473 */
4474#define X86_SEL_SHIFT 3
4475
4476/**
4477 * The mask used to mask off the table indicator and RPL of an selector.
4478 */
4479#define X86_SEL_MASK 0xfff8U
4480
4481/**
4482 * The mask used to mask off the RPL of an selector.
4483 * This is suitable for checking for NULL selectors.
4484 */
4485#define X86_SEL_MASK_OFF_RPL 0xfffcU
4486
4487/**
4488 * The bit indicating that a selector is in the LDT and not in the GDT.
4489 */
4490#define X86_SEL_LDT 0x0004U
4491
4492/**
4493 * The bit mask for getting the RPL of a selector.
4494 */
4495#define X86_SEL_RPL 0x0003U
4496
4497/**
4498 * The mask covering both RPL and LDT.
4499 * This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4500 * checks.
4501 */
4502#define X86_SEL_RPL_LDT 0x0007U
4503
4504/** @} */
4505
4506
4507/**
4508 * x86 Exceptions/Faults/Traps.
4509 */
4510typedef enum X86XCPT
4511{
4512 /** \#DE - Divide error. */
4513 X86_XCPT_DE = 0x00,
4514 /** \#DB - Debug event (single step, DRx, ..) */
4515 X86_XCPT_DB = 0x01,
4516 /** NMI - Non-Maskable Interrupt */
4517 X86_XCPT_NMI = 0x02,
4518 /** \#BP - Breakpoint (INT3). */
4519 X86_XCPT_BP = 0x03,
4520 /** \#OF - Overflow (INTO). */
4521 X86_XCPT_OF = 0x04,
4522 /** \#BR - Bound range exceeded (BOUND). */
4523 X86_XCPT_BR = 0x05,
4524 /** \#UD - Undefined opcode. */
4525 X86_XCPT_UD = 0x06,
4526 /** \#NM - Device not available (math coprocessor device). */
4527 X86_XCPT_NM = 0x07,
4528 /** \#DF - Double fault. */
4529 X86_XCPT_DF = 0x08,
4530 /** ??? - Coprocessor segment overrun (obsolete). */
4531 X86_XCPT_CO_SEG_OVERRUN = 0x09,
4532 /** \#TS - Taskswitch (TSS). */
4533 X86_XCPT_TS = 0x0a,
4534 /** \#NP - Segment no present. */
4535 X86_XCPT_NP = 0x0b,
4536 /** \#SS - Stack segment fault. */
4537 X86_XCPT_SS = 0x0c,
4538 /** \#GP - General protection fault. */
4539 X86_XCPT_GP = 0x0d,
4540 /** \#PF - Page fault. */
4541 X86_XCPT_PF = 0x0e,
4542 /* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4543 /** \#MF - Math fault (FPU). */
4544 X86_XCPT_MF = 0x10,
4545 /** \#AC - Alignment check. */
4546 X86_XCPT_AC = 0x11,
4547 /** \#MC - Machine check. */
4548 X86_XCPT_MC = 0x12,
4549 /** \#XF - SIMD Floating-Point Exception. */
4550 X86_XCPT_XF = 0x13,
4551 /** \#VE - Virtualization Exception (Intel only). */
4552 X86_XCPT_VE = 0x14,
4553 /** \#CP - Control Protection Exception (Intel only). */
4554 X86_XCPT_CP = 0x15,
4555 /** \#VC - VMM Communication Exception (AMD only). */
4556 X86_XCPT_VC = 0x1d,
4557 /** \#SX - Security Exception (AMD only). */
4558 X86_XCPT_SX = 0x1e
4559} X86XCPT;
4560/** Pointer to a x86 exception code. */
4561typedef X86XCPT *PX86XCPT;
4562/** Pointer to a const x86 exception code. */
4563typedef const X86XCPT *PCX86XCPT;
4564/** The last valid (currently reserved) exception value. */
4565#define X86_XCPT_LAST 0x1f
4566
4567
4568/** @name Trap Error Codes
4569 * @{
4570 */
4571/** External indicator. */
4572#define X86_TRAP_ERR_EXTERNAL 1
4573/** IDT indicator. */
4574#define X86_TRAP_ERR_IDT 2
4575/** Descriptor table indicator - If set LDT, if clear GDT. */
4576#define X86_TRAP_ERR_TI 4
4577/** Mask for getting the selector. */
4578#define X86_TRAP_ERR_SEL_MASK 0xfff8
4579/** Shift for getting the selector table index (C type index). */
4580#define X86_TRAP_ERR_SEL_SHIFT 3
4581/** @} */
4582
4583
4584/** @name \#PF Trap Error Codes
4585 * @{
4586 */
4587/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4588#define X86_TRAP_PF_P RT_BIT_32(0)
4589/** Bit 1 - R/W - Read (clear) or write (set) access. */
4590#define X86_TRAP_PF_RW RT_BIT_32(1)
4591/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4592#define X86_TRAP_PF_US RT_BIT_32(2)
4593/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4594#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4595/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4596#define X86_TRAP_PF_ID RT_BIT_32(4)
4597/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4598#define X86_TRAP_PF_PK RT_BIT_32(5)
4599/** @} */
4600
4601#pragma pack(1)
4602/**
4603 * 16-bit IDTR.
4604 */
4605typedef struct X86IDTR16
4606{
4607 /** Offset. */
4608 uint16_t offSel;
4609 /** Selector. */
4610 uint16_t uSel;
4611} X86IDTR16, *PX86IDTR16;
4612#pragma pack()
4613
4614#pragma pack(1)
4615/**
4616 * 32-bit IDTR/GDTR.
4617 */
4618typedef struct X86XDTR32
4619{
4620 /** Size of the descriptor table. */
4621 uint16_t cb;
4622 /** Address of the descriptor table. */
4623#ifndef VBOX_FOR_DTRACE_LIB
4624 uint32_t uAddr;
4625#else
4626 uint16_t au16Addr[2];
4627#endif
4628} X86XDTR32, *PX86XDTR32;
4629#pragma pack()
4630
4631#pragma pack(1)
4632/**
4633 * 64-bit IDTR/GDTR.
4634 */
4635typedef struct X86XDTR64
4636{
4637 /** Size of the descriptor table. */
4638 uint16_t cb;
4639 /** Address of the descriptor table. */
4640#ifndef VBOX_FOR_DTRACE_LIB
4641 uint64_t uAddr;
4642#else
4643 uint16_t au16Addr[4];
4644#endif
4645} X86XDTR64, *PX86XDTR64;
4646#pragma pack()
4647
4648
4649/** @name ModR/M
4650 * @{ */
4651#define X86_MODRM_RM_MASK UINT8_C(0x07)
4652#define X86_MODRM_REG_MASK UINT8_C(0x38)
4653#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4654#define X86_MODRM_REG_SHIFT 3
4655#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4656#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4657#define X86_MODRM_MOD_SHIFT 6
4658#ifndef VBOX_FOR_DTRACE_LIB
4659AssertCompile((X86_MODRM_RM_MASK | X86_MODRM_REG_MASK | X86_MODRM_MOD_MASK) == 0xff);
4660AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4661AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4662/** @def X86_MODRM_MAKE
4663 * @param a_Mod The mod value (0..3).
4664 * @param a_Reg The register value (0..7).
4665 * @param a_RegMem The register or memory value (0..7). */
4666# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
4667#endif
4668/** @} */
4669
4670/** @name SIB
4671 * @{ */
4672#define X86_SIB_BASE_MASK UINT8_C(0x07)
4673#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4674#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4675#define X86_SIB_INDEX_SHIFT 3
4676#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4677#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4678#define X86_SIB_SCALE_SHIFT 6
4679#ifndef VBOX_FOR_DTRACE_LIB
4680AssertCompile((X86_SIB_BASE_MASK | X86_SIB_INDEX_MASK | X86_SIB_SCALE_MASK) == 0xff);
4681AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4682AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4683#endif
4684/** @} */
4685
4686/** @name General register indexes.
4687 * @{ */
4688#define X86_GREG_xAX 0
4689#define X86_GREG_xCX 1
4690#define X86_GREG_xDX 2
4691#define X86_GREG_xBX 3
4692#define X86_GREG_xSP 4
4693#define X86_GREG_xBP 5
4694#define X86_GREG_xSI 6
4695#define X86_GREG_xDI 7
4696#define X86_GREG_x8 8
4697#define X86_GREG_x9 9
4698#define X86_GREG_x10 10
4699#define X86_GREG_x11 11
4700#define X86_GREG_x12 12
4701#define X86_GREG_x13 13
4702#define X86_GREG_x14 14
4703#define X86_GREG_x15 15
4704/** @} */
4705/** General register count. */
4706#define X86_GREG_COUNT 16
4707
4708/** @name X86_SREG_XXX - Segment register indexes.
4709 * @{ */
4710#define X86_SREG_ES 0
4711#define X86_SREG_CS 1
4712#define X86_SREG_SS 2
4713#define X86_SREG_DS 3
4714#define X86_SREG_FS 4
4715#define X86_SREG_GS 5
4716/** @} */
4717/** Segment register count. */
4718#define X86_SREG_COUNT 6
4719
4720
4721/** @name X86_OP_XXX - Prefixes
4722 * @{ */
4723#define X86_OP_PRF_CS UINT8_C(0x2e)
4724#define X86_OP_PRF_SS UINT8_C(0x36)
4725#define X86_OP_PRF_DS UINT8_C(0x3e)
4726#define X86_OP_PRF_ES UINT8_C(0x26)
4727#define X86_OP_PRF_FS UINT8_C(0x64)
4728#define X86_OP_PRF_GS UINT8_C(0x65)
4729#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4730#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4731#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4732#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4733#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4734#define X86_OP_REX_B UINT8_C(0x41)
4735#define X86_OP_REX_X UINT8_C(0x42)
4736#define X86_OP_REX_R UINT8_C(0x44)
4737#define X86_OP_REX_W UINT8_C(0x48)
4738/** @} */
4739
4740
4741/** @} */
4742
4743#endif /* !IPRT_INCLUDED_x86_h */
4744
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