x86.h@ 96251

Last change on this file since 96251 was 96251, checked in by vboxsync, 2 years ago
VMM/IEM: Start implementing floating point SSE instructions using addps, added some new infrastructure bits (mostly untested), bugref:9898 [missing file]
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 182.0 KB

Line
1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2022 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*
18	* The contents of this file may alternatively be used under the terms
19	* of the Common Development and Distribution License Version 1.0
20	* (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	* VirtualBox OSE distribution, in which case the provisions of the
22	* CDDL are applicable instead of those of the GPL.
23	*
24	* You may elect to license modified versions of this file under the
25	* terms and conditions of either the GPL or the CDDL or both.
26	*/
27
28	#ifndef IPRT_INCLUDED_x86_h
29	#define IPRT_INCLUDED_x86_h
30	#ifndef RT_WITHOUT_PRAGMA_ONCE
31	# pragma once
32	#endif
33
34	#ifndef VBOX_FOR_DTRACE_LIB
35	# include <iprt/types.h>
36	# include <iprt/assert.h>
37	#else
38	# pragma D depends_on library vbox-types.d
39	#endif
40
41	/** Workaround for Solaris sys/regset.h defining CS, DS and sys/controlregs.h
42	* defining MSR_IA32_FLUSH_CMD */
43	#ifdef RT_OS_SOLARIS
44	# undef CS
45	# undef DS
46	# undef MSR_IA32_FLUSH_CMD
47	#endif
48
49	/** @defgroup grp_rt_x86 x86 Types and Definitions
50	* @ingroup grp_rt
51	* @{
52	*/
53
54	#ifndef VBOX_FOR_DTRACE_LIB
55	/**
56	* EFLAGS Bits.
57	*/
58	typedef struct X86EFLAGSBITS
59	{
60	/** Bit 0 - CF - Carry flag - Status flag. */
61	unsigned u1CF : 1;
62	/** Bit 1 - 1 - Reserved flag. */
63	unsigned u1Reserved0 : 1;
64	/** Bit 2 - PF - Parity flag - Status flag. */
65	unsigned u1PF : 1;
66	/** Bit 3 - 0 - Reserved flag. */
67	unsigned u1Reserved1 : 1;
68	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
69	unsigned u1AF : 1;
70	/** Bit 5 - 0 - Reserved flag. */
71	unsigned u1Reserved2 : 1;
72	/** Bit 6 - ZF - Zero flag - Status flag. */
73	unsigned u1ZF : 1;
74	/** Bit 7 - SF - Signed flag - Status flag. */
75	unsigned u1SF : 1;
76	/** Bit 8 - TF - Trap flag - System flag. */
77	unsigned u1TF : 1;
78	/** Bit 9 - IF - Interrupt flag - System flag. */
79	unsigned u1IF : 1;
80	/** Bit 10 - DF - Direction flag - Control flag. */
81	unsigned u1DF : 1;
82	/** Bit 11 - OF - Overflow flag - Status flag. */
83	unsigned u1OF : 1;
84	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
85	unsigned u2IOPL : 2;
86	/** Bit 14 - NT - Nested task flag - System flag. */
87	unsigned u1NT : 1;
88	/** Bit 15 - 0 - Reserved flag. */
89	unsigned u1Reserved3 : 1;
90	/** Bit 16 - RF - Resume flag - System flag. */
91	unsigned u1RF : 1;
92	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
93	unsigned u1VM : 1;
94	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
95	unsigned u1AC : 1;
96	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
97	unsigned u1VIF : 1;
98	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
99	unsigned u1VIP : 1;
100	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
101	unsigned u1ID : 1;
102	/** Bit 22-31 - 0 - Reserved flag. */
103	unsigned u10Reserved4 : 10;
104	} X86EFLAGSBITS;
105	/** Pointer to EFLAGS bits. */
106	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
107	/** Pointer to const EFLAGS bits. */
108	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
109	#endif /* !VBOX_FOR_DTRACE_LIB */
110
111	/**
112	* EFLAGS.
113	*/
114	typedef union X86EFLAGS
115	{
116	/** The plain unsigned view. */
117	uint32_t u;
118	#ifndef VBOX_FOR_DTRACE_LIB
119	/** The bitfield view. */
120	X86EFLAGSBITS Bits;
121	#endif
122	/** The 8-bit view. */
123	uint8_t au8[4];
124	/** The 16-bit view. */
125	uint16_t au16[2];
126	/** The 32-bit view. */
127	uint32_t au32[1];
128	/** The 32-bit view. */
129	uint32_t u32;
130	} X86EFLAGS;
131	/** Pointer to EFLAGS. */
132	typedef X86EFLAGS *PX86EFLAGS;
133	/** Pointer to const EFLAGS. */
134	typedef const X86EFLAGS *PCX86EFLAGS;
135
136	/**
137	* RFLAGS (32 upper bits are reserved).
138	*/
139	typedef union X86RFLAGS
140	{
141	/** The plain unsigned view. */
142	uint64_t u;
143	#ifndef VBOX_FOR_DTRACE_LIB
144	/** The bitfield view. */
145	X86EFLAGSBITS Bits;
146	#endif
147	/** The 8-bit view. */
148	uint8_t au8[8];
149	/** The 16-bit view. */
150	uint16_t au16[4];
151	/** The 32-bit view. */
152	uint32_t au32[2];
153	/** The 64-bit view. */
154	uint64_t au64[1];
155	/** The 64-bit view. */
156	uint64_t u64;
157	} X86RFLAGS;
158	/** Pointer to RFLAGS. */
159	typedef X86RFLAGS *PX86RFLAGS;
160	/** Pointer to const RFLAGS. */
161	typedef const X86RFLAGS *PCX86RFLAGS;
162
163
164	/** @name EFLAGS
165	* @{
166	*/
167	/** Bit 0 - CF - Carry flag - Status flag. */
168	#define X86_EFL_CF RT_BIT_32(0)
169	#define X86_EFL_CF_BIT 0
170	/** Bit 1 - Reserved, reads as 1. */
171	#define X86_EFL_1 RT_BIT_32(1)
172	/** Bit 2 - PF - Parity flag - Status flag. */
173	#define X86_EFL_PF RT_BIT_32(2)
174	#define X86_EFL_PF_BIT 2
175	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
176	#define X86_EFL_AF RT_BIT_32(4)
177	#define X86_EFL_AF_BIT 4
178	/** Bit 6 - ZF - Zero flag - Status flag. */
179	#define X86_EFL_ZF RT_BIT_32(6)
180	#define X86_EFL_ZF_BIT 6
181	/** Bit 7 - SF - Signed flag - Status flag. */
182	#define X86_EFL_SF RT_BIT_32(7)
183	#define X86_EFL_SF_BIT 7
184	/** Bit 8 - TF - Trap flag - System flag. */
185	#define X86_EFL_TF RT_BIT_32(8)
186	#define X86_EFL_TF_BIT 8
187	/** Bit 9 - IF - Interrupt flag - System flag. */
188	#define X86_EFL_IF RT_BIT_32(9)
189	#define X86_EFL_IF_BIT 9
190	/** Bit 10 - DF - Direction flag - Control flag. */
191	#define X86_EFL_DF RT_BIT_32(10)
192	#define X86_EFL_DF_BIT 10
193	/** Bit 11 - OF - Overflow flag - Status flag. */
194	#define X86_EFL_OF RT_BIT_32(11)
195	#define X86_EFL_OF_BIT 11
196	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
197	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
198	/** Bit 14 - NT - Nested task flag - System flag. */
199	#define X86_EFL_NT RT_BIT_32(14)
200	#define X86_EFL_NT_BIT 14
201	/** Bit 16 - RF - Resume flag - System flag. */
202	#define X86_EFL_RF RT_BIT_32(16)
203	#define X86_EFL_RF_BIT 16
204	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
205	#define X86_EFL_VM RT_BIT_32(17)
206	#define X86_EFL_VM_BIT 17
207	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
208	#define X86_EFL_AC RT_BIT_32(18)
209	#define X86_EFL_AC_BIT 18
210	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
211	#define X86_EFL_VIF RT_BIT_32(19)
212	#define X86_EFL_VIF_BIT 19
213	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
214	#define X86_EFL_VIP RT_BIT_32(20)
215	#define X86_EFL_VIP_BIT 20
216	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
217	#define X86_EFL_ID RT_BIT_32(21)
218	#define X86_EFL_ID_BIT 21
219	/** All live bits. */
220	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
221	/** Read as 1 bits. */
222	#define X86_EFL_RA1_MASK RT_BIT_32(1)
223	/** IOPL shift. */
224	#define X86_EFL_IOPL_SHIFT 12
225	/** The IOPL level from the flags. */
226	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
227	/** Bits restored by popf */
228	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
229	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
230	/** Bits restored by popf */
231	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
232	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
233	/** The status bits commonly updated by arithmetic instructions. */
234	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
235	/** @} */
236
237
238	/** CPUID Feature information - ECX.
239	* CPUID query with EAX=1.
240	*/
241	#ifndef VBOX_FOR_DTRACE_LIB
242	typedef struct X86CPUIDFEATECX
243	{
244	/** Bit 0 - SSE3 - Supports SSE3 or not. */
245	unsigned u1SSE3 : 1;
246	/** Bit 1 - PCLMULQDQ. */
247	unsigned u1PCLMULQDQ : 1;
248	/** Bit 2 - DS Area 64-bit layout. */
249	unsigned u1DTE64 : 1;
250	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
251	unsigned u1Monitor : 1;
252	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
253	unsigned u1CPLDS : 1;
254	/** Bit 5 - VMX - Virtual Machine Technology. */
255	unsigned u1VMX : 1;
256	/** Bit 6 - SMX: Safer Mode Extensions. */
257	unsigned u1SMX : 1;
258	/** Bit 7 - EST - Enh. SpeedStep Tech. */
259	unsigned u1EST : 1;
260	/** Bit 8 - TM2 - Terminal Monitor 2. */
261	unsigned u1TM2 : 1;
262	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
263	unsigned u1SSSE3 : 1;
264	/** Bit 10 - CNTX-ID - L1 Context ID. */
265	unsigned u1CNTXID : 1;
266	/** Bit 11 - Reserved. */
267	unsigned u1Reserved1 : 1;
268	/** Bit 12 - FMA. */
269	unsigned u1FMA : 1;
270	/** Bit 13 - CX16 - CMPXCHG16B. */
271	unsigned u1CX16 : 1;
272	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
273	unsigned u1TPRUpdate : 1;
274	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
275	unsigned u1PDCM : 1;
276	/** Bit 16 - Reserved. */
277	unsigned u1Reserved2 : 1;
278	/** Bit 17 - PCID - Process-context identifiers. */
279	unsigned u1PCID : 1;
280	/** Bit 18 - Direct Cache Access. */
281	unsigned u1DCA : 1;
282	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
283	unsigned u1SSE4_1 : 1;
284	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
285	unsigned u1SSE4_2 : 1;
286	/** Bit 21 - x2APIC. */
287	unsigned u1x2APIC : 1;
288	/** Bit 22 - MOVBE - Supports MOVBE. */
289	unsigned u1MOVBE : 1;
290	/** Bit 23 - POPCNT - Supports POPCNT. */
291	unsigned u1POPCNT : 1;
292	/** Bit 24 - TSC-Deadline. */
293	unsigned u1TSCDEADLINE : 1;
294	/** Bit 25 - AES. */
295	unsigned u1AES : 1;
296	/** Bit 26 - XSAVE - Supports XSAVE. */
297	unsigned u1XSAVE : 1;
298	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
299	unsigned u1OSXSAVE : 1;
300	/** Bit 28 - AVX - Supports AVX instruction extensions. */
301	unsigned u1AVX : 1;
302	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
303	unsigned u1F16C : 1;
304	/** Bit 30 - RDRAND - Supports RDRAND. */
305	unsigned u1RDRAND : 1;
306	/** Bit 31 - Hypervisor present (we're a guest). */
307	unsigned u1HVP : 1;
308	} X86CPUIDFEATECX;
309	#else /* VBOX_FOR_DTRACE_LIB */
310	typedef uint32_t X86CPUIDFEATECX;
311	#endif /* VBOX_FOR_DTRACE_LIB */
312	/** Pointer to CPUID Feature Information - ECX. */
313	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
314	/** Pointer to const CPUID Feature Information - ECX. */
315	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
316
317
318	/** CPUID Feature Information - EDX.
319	* CPUID query with EAX=1.
320	*/
321	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
322	typedef struct X86CPUIDFEATEDX
323	{
324	/** Bit 0 - FPU - x87 FPU on Chip. */
325	unsigned u1FPU : 1;
326	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
327	unsigned u1VME : 1;
328	/** Bit 2 - DE - Debugging extensions. */
329	unsigned u1DE : 1;
330	/** Bit 3 - PSE - Page Size Extension. */
331	unsigned u1PSE : 1;
332	/** Bit 4 - TSC - Time Stamp Counter. */
333	unsigned u1TSC : 1;
334	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
335	unsigned u1MSR : 1;
336	/** Bit 6 - PAE - Physical Address Extension. */
337	unsigned u1PAE : 1;
338	/** Bit 7 - MCE - Machine Check Exception. */
339	unsigned u1MCE : 1;
340	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
341	unsigned u1CX8 : 1;
342	/** Bit 9 - APIC - APIC On-Chip. */
343	unsigned u1APIC : 1;
344	/** Bit 10 - Reserved. */
345	unsigned u1Reserved1 : 1;
346	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
347	unsigned u1SEP : 1;
348	/** Bit 12 - MTRR - Memory Type Range Registers. */
349	unsigned u1MTRR : 1;
350	/** Bit 13 - PGE - PTE Global Bit. */
351	unsigned u1PGE : 1;
352	/** Bit 14 - MCA - Machine Check Architecture. */
353	unsigned u1MCA : 1;
354	/** Bit 15 - CMOV - Conditional Move Instructions. */
355	unsigned u1CMOV : 1;
356	/** Bit 16 - PAT - Page Attribute Table. */
357	unsigned u1PAT : 1;
358	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
359	unsigned u1PSE36 : 1;
360	/** Bit 18 - PSN - Processor Serial Number. */
361	unsigned u1PSN : 1;
362	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
363	unsigned u1CLFSH : 1;
364	/** Bit 20 - Reserved. */
365	unsigned u1Reserved2 : 1;
366	/** Bit 21 - DS - Debug Store. */
367	unsigned u1DS : 1;
368	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
369	unsigned u1ACPI : 1;
370	/** Bit 23 - MMX - Intel MMX 'Technology'. */
371	unsigned u1MMX : 1;
372	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
373	unsigned u1FXSR : 1;
374	/** Bit 25 - SSE - SSE Support. */
375	unsigned u1SSE : 1;
376	/** Bit 26 - SSE2 - SSE2 Support. */
377	unsigned u1SSE2 : 1;
378	/** Bit 27 - SS - Self Snoop. */
379	unsigned u1SS : 1;
380	/** Bit 28 - HTT - Hyper-Threading Technology. */
381	unsigned u1HTT : 1;
382	/** Bit 29 - TM - Thermal Monitor. */
383	unsigned u1TM : 1;
384	/** Bit 30 - Reserved - . */
385	unsigned u1Reserved3 : 1;
386	/** Bit 31 - PBE - Pending Break Enabled. */
387	unsigned u1PBE : 1;
388	} X86CPUIDFEATEDX;
389	#else /* VBOX_FOR_DTRACE_LIB */
390	typedef uint32_t X86CPUIDFEATEDX;
391	#endif /* VBOX_FOR_DTRACE_LIB */
392	/** Pointer to CPUID Feature Information - EDX. */
393	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
394	/** Pointer to const CPUID Feature Information - EDX. */
395	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
396
397	/** @name CPUID Vendor information.
398	* CPUID query with EAX=0.
399	* @{
400	*/
401	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
402	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
403	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
404
405	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
406	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
407	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
408
409	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
410	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
411	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
412
413	#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
414	#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
415	#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
416
417	#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
418	#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
419	#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
420	/** @} */
421
422
423	/** @name CPUID Feature information.
424	* CPUID query with EAX=1.
425	* @{
426	*/
427	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
428	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
429	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
430	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
431	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
432	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
433	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
434	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
435	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
436	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
437	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
438	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
439	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
440	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
441	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
442	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
443	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
444	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
445	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
446	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
447	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
448	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
449	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
450	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
451	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
452	/** ECX Bit 12 - FMA. */
453	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
454	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
455	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
456	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
457	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
458	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
459	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
460	/** ECX Bit 17 - PCID - Process-context identifiers. */
461	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
462	/** ECX Bit 18 - DCA - Direct Cache Access. */
463	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
464	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
465	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
466	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
467	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
468	/** ECX Bit 21 - x2APIC support. */
469	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
470	/** ECX Bit 22 - MOVBE instruction. */
471	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
472	/** ECX Bit 23 - POPCNT instruction. */
473	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
474	/** ECX Bir 24 - TSC-Deadline. */
475	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
476	/** ECX Bit 25 - AES instructions. */
477	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
478	/** ECX Bit 26 - XSAVE instruction. */
479	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
480	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
481	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
482	/** ECX Bit 28 - AVX. */
483	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
484	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
485	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
486	/** ECX Bit 30 - RDRAND instruction. */
487	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
488	/** ECX Bit 31 - Hypervisor Present (software only). */
489	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
490
491
492	/** Bit 0 - FPU - x87 FPU on Chip. */
493	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
494	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
495	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
496	/** Bit 2 - DE - Debugging extensions. */
497	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
498	/** Bit 3 - PSE - Page Size Extension. */
499	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
500	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
501	/** Bit 4 - TSC - Time Stamp Counter. */
502	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
503	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
504	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
505	/** Bit 6 - PAE - Physical Address Extension. */
506	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
507	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
508	/** Bit 7 - MCE - Machine Check Exception. */
509	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
510	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
511	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
512	/** Bit 9 - APIC - APIC On-Chip. */
513	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
514	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
515	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
516	/** Bit 12 - MTRR - Memory Type Range Registers. */
517	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
518	/** Bit 13 - PGE - PTE Global Bit. */
519	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
520	/** Bit 14 - MCA - Machine Check Architecture. */
521	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
522	/** Bit 15 - CMOV - Conditional Move Instructions. */
523	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
524	/** Bit 16 - PAT - Page Attribute Table. */
525	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
526	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
527	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
528	/** Bit 18 - PSN - Processor Serial Number. */
529	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
530	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
531	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
532	/** Bit 21 - DS - Debug Store. */
533	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
534	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
535	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
536	/** Bit 23 - MMX - Intel MMX Technology. */
537	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
538	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
539	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
540	/** Bit 25 - SSE - SSE Support. */
541	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
542	/** Bit 26 - SSE2 - SSE2 Support. */
543	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
544	/** Bit 27 - SS - Self Snoop. */
545	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
546	/** Bit 28 - HTT - Hyper-Threading Technology. */
547	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
548	/** Bit 29 - TM - Therm. Monitor. */
549	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
550	/** Bit 31 - PBE - Pending Break Enabled. */
551	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
552	/** @} */
553
554	/** @name CPUID mwait/monitor information.
555	* CPUID query with EAX=5.
556	* @{
557	*/
558	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
559	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
560	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
561	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
562	/** @} */
563
564
565	/** @name CPUID Structured Extended Feature information.
566	* CPUID query with EAX=7.
567	* @{
568	*/
569	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
570	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
571	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
572	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
573	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
574	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
575	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
576	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
577	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
578	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
579	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
580	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
581	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
582	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
583	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
584	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
585	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
586	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
587	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
588	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
589	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
590	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
591	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
592	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
593	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
594	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
595	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
596	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
597	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
598	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
599	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
600	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
601	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
602	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
603	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
604	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
605	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
606	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
607	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
608	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
609	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
610	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
611	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
612	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
613	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
614	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
615	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
616	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
617	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
618	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
619	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
620	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
621
622	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
623	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
624	/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
625	#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
626	/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
627	#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
628	/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
629	#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
630	/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
631	#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
632	/** ECX Bit 22 - RDPID - Support pread process ID. */
633	#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
634	/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
635	#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
636
637	/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
638	#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
639	/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
640	* IBPB command in IA32_PRED_CMD. */
641	#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
642	/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
643	#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
644	/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
645	#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
646	/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
647	#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
648	/** EDX Bit 31 - SSBD - Supports the SSBD flag in IA32_SPEC_CTRL. */
649	#define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
650
651	/** @} */
652
653
654	/** @name CPUID Extended Feature information.
655	* CPUID query with EAX=0x80000001.
656	* @{
657	*/
658	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
659	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
660
661	/** EDX Bit 11 - SYSCALL/SYSRET. */
662	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
663	/** EDX Bit 20 - No-Execute/Execute-Disable. */
664	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
665	/** EDX Bit 26 - 1 GB large page. */
666	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
667	/** EDX Bit 27 - RDTSCP. */
668	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
669	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
670	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
671	/** @}*/
672
673	/** @name CPUID AMD Feature information.
674	* CPUID query with EAX=0x80000001.
675	* @{
676	*/
677	/** Bit 0 - FPU - x87 FPU on Chip. */
678	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
679	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
680	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
681	/** Bit 2 - DE - Debugging extensions. */
682	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
683	/** Bit 3 - PSE - Page Size Extension. */
684	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
685	/** Bit 4 - TSC - Time Stamp Counter. */
686	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
687	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
688	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
689	/** Bit 6 - PAE - Physical Address Extension. */
690	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
691	/** Bit 7 - MCE - Machine Check Exception. */
692	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
693	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
694	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
695	/** Bit 9 - APIC - APIC On-Chip. */
696	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
697	/** Bit 12 - MTRR - Memory Type Range Registers. */
698	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
699	/** Bit 13 - PGE - PTE Global Bit. */
700	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
701	/** Bit 14 - MCA - Machine Check Architecture. */
702	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
703	/** Bit 15 - CMOV - Conditional Move Instructions. */
704	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
705	/** Bit 16 - PAT - Page Attribute Table. */
706	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
707	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
708	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
709	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
710	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
711	/** Bit 23 - MMX - Intel MMX Technology. */
712	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
713	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
714	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
715	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
716	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
717	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
718	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
719	/** Bit 31 - 3DNOW - AMD 3DNow. */
720	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
721
722	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
723	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
724	/** Bit 2 - SVM - AMD VM extensions. */
725	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
726	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
727	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
728	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
729	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
730	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
731	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
732	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
733	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
734	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
735	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
736	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
737	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
738	/** Bit 9 - OSVW - AMD OS visible workaround. */
739	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
740	/** Bit 10 - IBS - Instruct based sampling. */
741	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
742	/** Bit 11 - XOP - Extended operation support (see APM6). */
743	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
744	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
745	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
746	/** Bit 13 - WDT - AMD Watchdog timer support. */
747	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
748	/** Bit 15 - LWP - Lightweight profiling support. */
749	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
750	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
751	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
752	/** Bit 19 - NodeId - Indicates support for
753	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
754	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
755	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
756	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
757	/** Bit 22 - TopologyExtensions - . */
758	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
759	/** @} */
760
761
762	/** @name CPUID AMD Feature information.
763	* CPUID query with EAX=0x80000007.
764	* @{
765	*/
766	/** Bit 0 - TS - Temperature Sensor. */
767	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
768	/** Bit 1 - FID - Frequency ID Control. */
769	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
770	/** Bit 2 - VID - Voltage ID Control. */
771	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
772	/** Bit 3 - TTP - THERMTRIP. */
773	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
774	/** Bit 4 - TM - Hardware Thermal Control. */
775	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
776	/** Bit 5 - STC - Software Thermal Control. */
777	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
778	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
779	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
780	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
781	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
782	/** Bit 8 - TSCINVAR - TSC Invariant. */
783	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
784	/** Bit 9 - CPB - TSC Invariant. */
785	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
786	/** Bit 10 - EffFreqRO - MPERF/APERF. */
787	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
788	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
789	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
790	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
791	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
792	/** @} */
793
794
795	/** @name CPUID AMD extended feature extensions ID (EBX).
796	* CPUID query with EAX=0x80000008.
797	* @{
798	*/
799	/** Bit 0 - CLZERO - Clear zero instruction. */
800	#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
801	/** Bit 1 - IRPerf - Instructions retired count support. */
802	#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
803	/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
804	#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
805	/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
806	#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
807	/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
808	#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
809	/* AMD pipeline length: 9 feature bits ;-) */
810	/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
811	#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
812	/** Bit 14 - IBRS - Supports the IBRS bit in IA32_SPEC_CTRL. */
813	#define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
814	/** Bit 15 - STIBP - Supports the STIBP bit in IA32_SPEC_CTRL. */
815	#define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
816	/** Bit 16 - IBRS always on mode - IBRS should be set once during boot only. */
817	#define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
818	/** Bit 17 - STIBP always on mode - STIBP should be set once during boot only. */
819	#define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
820	/** Bit 18 - IBRS preferred - IBRS is preferred over software mitigations. */
821	#define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
822	/** Bit 24 - Speculative Store Bypass Disable supported in SPEC_CTL. */
823	#define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
824	/** Bit 25 - Speculative Store Bypass Disable supported in VIRT_SPEC_CTL. */
825	#define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
826	/** Bit 26 - Speculative Store Bypass Disable not required. */
827	#define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
828	/** @} */
829
830
831	/** @name CPUID AMD SVM Feature information.
832	* CPUID query with EAX=0x8000000a.
833	* @{
834	*/
835	/** Bit 0 - NP - Nested Paging supported. */
836	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
837	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
838	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
839	/** Bit 2 - SVML - SVM locking bit supported. */
840	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
841	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
842	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
843	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
844	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
845	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
846	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
847	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
848	* VMCB.TLB_Control is supported. */
849	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
850	/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
851	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
852	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
853	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
854	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
855	* intercept filter cycle count threshold. */
856	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
857	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
858	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
859	/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
860	#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
861	/** Bit 16 - VGIF - Supports virtualized GIF. */
862	#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
863	/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
864	#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
865	/** Bit 19 - SSSCheck - SVM supervisor shadow stack restrictions. */
866	#define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK RT_BIT(19)
867	/** Bit 20 - SpecCtrl - Supports SPEC_CTRL Virtualization. */
868	#define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL RT_BIT(20)
869	/** Bit 23 - HOST_MCE_OVERRIDE - Supports host \#MC exception override. */
870	#define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE RT_BIT(23)
871	/** Bit 24 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
872	#define X86_CPUID_SVM_FEATURE_EDX_TLBICTL RT_BIT(24)
873	/** @} */
874
875
876	/** @name CR0
877	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
878	* reserved flags.
879	* @{ */
880	/** Bit 0 - PE - Protection Enabled */
881	#define X86_CR0_PE RT_BIT_32(0)
882	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
883	/** Bit 1 - MP - Monitor Coprocessor */
884	#define X86_CR0_MP RT_BIT_32(1)
885	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
886	/** Bit 2 - EM - Emulation. */
887	#define X86_CR0_EM RT_BIT_32(2)
888	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
889	/** Bit 3 - TS - Task Switch. */
890	#define X86_CR0_TS RT_BIT_32(3)
891	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
892	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
893	#define X86_CR0_ET RT_BIT_32(4)
894	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
895	/** Bit 5 - NE - Numeric error (486+). */
896	#define X86_CR0_NE RT_BIT_32(5)
897	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
898	/** Bit 16 - WP - Write Protect (486+). */
899	#define X86_CR0_WP RT_BIT_32(16)
900	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
901	/** Bit 18 - AM - Alignment Mask (486+). */
902	#define X86_CR0_AM RT_BIT_32(18)
903	#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
904	/** Bit 29 - NW - Not Write-though (486+). */
905	#define X86_CR0_NW RT_BIT_32(29)
906	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
907	/** Bit 30 - WP - Cache Disable (486+). */
908	#define X86_CR0_CD RT_BIT_32(30)
909	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
910	/** Bit 31 - PG - Paging. */
911	#define X86_CR0_PG RT_BIT_32(31)
912	#define X86_CR0_PAGING RT_BIT_32(31)
913	#define X86_CR0_BIT_PG 31 /*< Bit number of X86_CR0_PG /
914	/** @} */
915
916
917	/** @name CR3
918	* @{ */
919	/** Bit 3 - PWT - Page-level Writes Transparent. */
920	#define X86_CR3_PWT RT_BIT_32(3)
921	/** Bit 4 - PCD - Page-level Cache Disable. */
922	#define X86_CR3_PCD RT_BIT_32(4)
923	/** Bits 12-31 - - Page directory page number. */
924	#define X86_CR3_PAGE_MASK (0xfffff000)
925	/** Bits 5-31 - - PAE Page directory page number. */
926	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
927	/** Bits 12-51 - - AMD64 Page directory page number. */
928	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
929	/** Bits 12-47 - - Intel EPT Page directory page number. */
930	#define X86_CR3_EPT_PAGE_MASK UINT64_C(0x0000fffffffff000)
931	/** @} */
932
933
934	/** @name CR4
935	* @{ */
936	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
937	#define X86_CR4_VME RT_BIT_32(0)
938	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
939	#define X86_CR4_PVI RT_BIT_32(1)
940	/** Bit 2 - TSD - Time Stamp Disable. */
941	#define X86_CR4_TSD RT_BIT_32(2)
942	/** Bit 3 - DE - Debugging Extensions. */
943	#define X86_CR4_DE RT_BIT_32(3)
944	/** Bit 4 - PSE - Page Size Extension. */
945	#define X86_CR4_PSE RT_BIT_32(4)
946	/** Bit 5 - PAE - Physical Address Extension. */
947	#define X86_CR4_PAE RT_BIT_32(5)
948	/** Bit 6 - MCE - Machine-Check Enable. */
949	#define X86_CR4_MCE RT_BIT_32(6)
950	/** Bit 7 - PGE - Page Global Enable. */
951	#define X86_CR4_PGE RT_BIT_32(7)
952	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
953	#define X86_CR4_PCE RT_BIT_32(8)
954	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
955	#define X86_CR4_OSFXSR RT_BIT_32(9)
956	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
957	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
958	/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
959	#define X86_CR4_UMIP RT_BIT_32(11)
960	/** Bit 13 - VMXE - VMX mode is enabled. */
961	#define X86_CR4_VMXE RT_BIT_32(13)
962	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
963	#define X86_CR4_SMXE RT_BIT_32(14)
964	/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
965	#define X86_CR4_FSGSBASE RT_BIT_32(16)
966	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
967	#define X86_CR4_PCIDE RT_BIT_32(17)
968	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
969	* extended states. */
970	#define X86_CR4_OSXSAVE RT_BIT_32(18)
971	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
972	#define X86_CR4_SMEP RT_BIT_32(20)
973	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
974	#define X86_CR4_SMAP RT_BIT_32(21)
975	/** Bit 22 - PKE - Protection Key Enable. */
976	#define X86_CR4_PKE RT_BIT_32(22)
977	/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
978	#define X86_CR4_CET RT_BIT_32(23)
979	/** @} */
980
981
982	/** @name DR6
983	* @{ */
984	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
985	#define X86_DR6_B0 RT_BIT_32(0)
986	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
987	#define X86_DR6_B1 RT_BIT_32(1)
988	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
989	#define X86_DR6_B2 RT_BIT_32(2)
990	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
991	#define X86_DR6_B3 RT_BIT_32(3)
992	/** Mask of all the Bx bits. */
993	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
994	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
995	#define X86_DR6_BD RT_BIT_32(13)
996	/** Bit 14 - BS - Single step */
997	#define X86_DR6_BS RT_BIT_32(14)
998	/** Bit 15 - BT - Task switch. (TSS T bit.) */
999	#define X86_DR6_BT RT_BIT_32(15)
1000	/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
1001	#define X86_DR6_RTM RT_BIT_32(16)
1002	/** Value of DR6 after powerup/reset. */
1003	#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
1004	/** Bits which must be 1s in DR6. */
1005	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
1006	/** Bits which must be 1s in DR6, when RTM is supported. */
1007	#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
1008	/** Bits which must be 0s in DR6. */
1009	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
1010	/** Bits which must be 0s on writes to DR6. */
1011	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
1012	/** @} */
1013
1014	/** Get the DR6.Bx bit for a the given breakpoint. */
1015	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
1016
1017
1018	/** @name DR7
1019	* @{ */
1020	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
1021	#define X86_DR7_L0 RT_BIT_32(0)
1022	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
1023	#define X86_DR7_G0 RT_BIT_32(1)
1024	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
1025	#define X86_DR7_L1 RT_BIT_32(2)
1026	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
1027	#define X86_DR7_G1 RT_BIT_32(3)
1028	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
1029	#define X86_DR7_L2 RT_BIT_32(4)
1030	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
1031	#define X86_DR7_G2 RT_BIT_32(5)
1032	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
1033	#define X86_DR7_L3 RT_BIT_32(6)
1034	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
1035	#define X86_DR7_G3 RT_BIT_32(7)
1036	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1037	#define X86_DR7_LE RT_BIT_32(8)
1038	/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1039	#define X86_DR7_GE RT_BIT_32(9)
1040
1041	/** L0, L1, L2, and L3. */
1042	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1043	/** L0, L1, L2, and L3. */
1044	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1045
1046	/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1047	* Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1048	#define X86_DR7_RTM RT_BIT_32(11)
1049	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1050	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1051	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1052	* instruction is executed.
1053	* @see http://www.rcollins.org/secrets/DR7.html */
1054	#define X86_DR7_ICE_IR RT_BIT_32(12)
1055	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1056	* any DR register is accessed. */
1057	#define X86_DR7_GD RT_BIT_32(13)
1058	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1059	* Pentium. */
1060	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1061	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1062	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1063	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
1064	#define X86_DR7_RW0_MASK (3 << 16)
1065	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
1066	#define X86_DR7_LEN0_MASK (3 << 18)
1067	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
1068	#define X86_DR7_RW1_MASK (3 << 20)
1069	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
1070	#define X86_DR7_LEN1_MASK (3 << 22)
1071	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
1072	#define X86_DR7_RW2_MASK (3 << 24)
1073	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
1074	#define X86_DR7_LEN2_MASK (3 << 26)
1075	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
1076	#define X86_DR7_RW3_MASK (3 << 28)
1077	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
1078	#define X86_DR7_LEN3_MASK (3 << 30)
1079
1080	/** Bits which reads as 1s. */
1081	#define X86_DR7_RA1_MASK RT_BIT_32(10)
1082	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1083	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1084	/** Bits which must be 0s when writing to DR7. */
1085	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1086
1087	/** Calcs the L bit of Nth breakpoint.
1088	* @param iBp The breakpoint number [0..3].
1089	*/
1090	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1091
1092	/** Calcs the G bit of Nth breakpoint.
1093	* @param iBp The breakpoint number [0..3].
1094	*/
1095	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1096
1097	/** Calcs the L and G bits of Nth breakpoint.
1098	* @param iBp The breakpoint number [0..3].
1099	*/
1100	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1101
1102	/** @name Read/Write values.
1103	* @{ */
1104	/** Break on instruction fetch only. */
1105	#define X86_DR7_RW_EO UINT32_C(0)
1106	/** Break on write only. */
1107	#define X86_DR7_RW_WO UINT32_C(1)
1108	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1109	#define X86_DR7_RW_IO UINT32_C(2)
1110	/** Break on read or write (but not instruction fetches). */
1111	#define X86_DR7_RW_RW UINT32_C(3)
1112	/** @} */
1113
1114	/** Shifts a X86_DR7_RW_* value to its right place.
1115	* @param iBp The breakpoint number [0..3].
1116	* @param fRw One of the X86_DR7_RW_* value.
1117	*/
1118	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1119
1120	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1121	* one of the X86_DR7_RW_XXX constants).
1122	*
1123	* @returns X86_DR7_RW_XXX
1124	* @param uDR7 DR7 value
1125	* @param iBp The breakpoint number [0..3].
1126	*/
1127	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1128
1129	/** R/W0, R/W1, R/W2, and R/W3. */
1130	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1131
1132	#ifndef VBOX_FOR_DTRACE_LIB
1133	/** Checks if there are any I/O breakpoint types configured in the RW
1134	* registers. Does NOT check if these are enabled, sorry. */
1135	# define X86_DR7_ANY_RW_IO(uDR7) \
1136	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1137	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1138	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1139	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1140	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1141	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1142	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1143	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1144	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1145	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1146	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1147	#endif /* !VBOX_FOR_DTRACE_LIB */
1148
1149	/** @name Length values.
1150	* @{ */
1151	#define X86_DR7_LEN_BYTE UINT32_C(0)
1152	#define X86_DR7_LEN_WORD UINT32_C(1)
1153	#define X86_DR7_LEN_QWORD UINT32_C(2) /*< AMD64 long mode only. /
1154	#define X86_DR7_LEN_DWORD UINT32_C(3)
1155	/** @} */
1156
1157	/** Shifts a X86_DR7_LEN_* value to its right place.
1158	* @param iBp The breakpoint number [0..3].
1159	* @param cb One of the X86_DR7_LEN_* values.
1160	*/
1161	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1162
1163	/** Fetch the breakpoint length bits from the DR7 value.
1164	* @param uDR7 DR7 value
1165	* @param iBp The breakpoint number [0..3].
1166	*/
1167	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1168
1169	/** Mask used to check if any breakpoints are enabled. */
1170	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1171
1172	/** LEN0, LEN1, LEN2, and LEN3. */
1173	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1174	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1175	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1176
1177	/** Value of DR7 after powerup/reset. */
1178	#define X86_DR7_INIT_VAL 0x400
1179	/** @} */
1180
1181
1182	/** @name Machine Specific Registers
1183	* @{
1184	*/
1185	/** Machine check address register (P5). */
1186	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1187	/** Machine check type register (P5). */
1188	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1189	/** Time Stamp Counter. */
1190	#define MSR_IA32_TSC 0x10
1191	#define MSR_IA32_CESR UINT32_C(0x00000011)
1192	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1193	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1194
1195	#define MSR_IA32_PLATFORM_ID 0x17
1196
1197	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1198	# define MSR_IA32_APICBASE 0x1b
1199	/** Local APIC enabled. */
1200	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1201	/** X2APIC enabled (requires the EN bit to be set). */
1202	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1203	/** The processor is the boot strap processor (BSP). */
1204	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1205	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1206	* width. */
1207	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1208	/** The default physical base address of the APIC. */
1209	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1210	/** Gets the physical base address from the MSR. */
1211	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1212	#endif
1213
1214	/** Undocumented intel MSR for reporting thread and core counts.
1215	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1216	* first 16 bits is the thread count. The next 16 bits the core count, except
1217	* on Westmere where it seems it's only the next 4 bits for some reason. */
1218	#define MSR_CORE_THREAD_COUNT 0x35
1219
1220	/** CPU Feature control. */
1221	#define MSR_IA32_FEATURE_CONTROL 0x3A
1222	/** Feature control - Lock MSR from writes (R/W0). */
1223	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1224	/** Feature control - Enable VMX inside SMX operation (R/WL). */
1225	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1226	/** Feature control - Enable VMX outside SMX operation (R/WL). */
1227	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1228	/** Feature control - SENTER local functions enable (R/WL). */
1229	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1230	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1231	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1232	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1233	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1234	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1235	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1236	/** Feature control - SENTER global enable (R/WL). */
1237	#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1238	/** Feature control - SGX launch control enable (R/WL). */
1239	#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1240	/** Feature control - SGX global enable (R/WL). */
1241	#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1242	/** Feature control - LMCE on (R/WL). */
1243	#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1244
1245	/** Per-processor TSC adjust MSR. */
1246	#define MSR_IA32_TSC_ADJUST 0x3B
1247
1248	/** Spectre control register.
1249	* Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1250	#define MSR_IA32_SPEC_CTRL 0x48
1251	/** IBRS - Indirect branch restricted speculation. */
1252	#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1253	/** STIBP - Single thread indirect branch predictors. */
1254	#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1255	/** SSBD - Speculative Store Bypass Disable. */
1256	#define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2)
1257
1258	/** Prediction command register.
1259	* Write only, logical processor scope, no state since write only. */
1260	#define MSR_IA32_PRED_CMD 0x49
1261	/** IBPB - Indirect branch prediction barrie when written as 1. */
1262	#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1263
1264	/** BIOS update trigger (microcode update). */
1265	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1266
1267	/** BIOS update signature (microcode). */
1268	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1269
1270	/** SMM monitor control. */
1271	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1272	/** SMM control - Valid. */
1273	#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1274	/** SMM control - VMXOFF unblocks SMI. */
1275	#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1276	/** SMM control - MSEG base physical address. */
1277	#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1278
1279	/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1280	#define MSR_IA32_SMBASE 0x9E
1281
1282	/** General performance counter no. 0. */
1283	#define MSR_IA32_PMC0 0xC1
1284	/** General performance counter no. 1. */
1285	#define MSR_IA32_PMC1 0xC2
1286	/** General performance counter no. 2. */
1287	#define MSR_IA32_PMC2 0xC3
1288	/** General performance counter no. 3. */
1289	#define MSR_IA32_PMC3 0xC4
1290	/** General performance counter no. 4. */
1291	#define MSR_IA32_PMC4 0xC5
1292	/** General performance counter no. 5. */
1293	#define MSR_IA32_PMC5 0xC6
1294	/** General performance counter no. 6. */
1295	#define MSR_IA32_PMC6 0xC7
1296	/** General performance counter no. 7. */
1297	#define MSR_IA32_PMC7 0xC8
1298
1299	/** Nehalem power control. */
1300	#define MSR_IA32_PLATFORM_INFO 0xCE
1301
1302	/** Get FSB clock status (Intel-specific). */
1303	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1304
1305	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1306	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1307
1308	/** C0 Maximum Frequency Clock Count */
1309	#define MSR_IA32_MPERF 0xE7
1310	/** C0 Actual Frequency Clock Count */
1311	#define MSR_IA32_APERF 0xE8
1312
1313	/** MTRR Capabilities. */
1314	#define MSR_IA32_MTRR_CAP 0xFE
1315
1316	/** Architecture capabilities (bugfixes). */
1317	#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1318	/** CPU is no subject to meltdown problems. */
1319	#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1320	/** CPU has better IBRS and you can leave it on all the time. */
1321	#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1322	/** CPU has return stack buffer (RSB) override. */
1323	#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1324	/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1325	* This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1326	#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1327	/** CPU does not suffer from MDS issues. */
1328	#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
1329
1330	/** Flush command register. */
1331	#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1332	/** Flush the level 1 data cache when this bit is written. */
1333	#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1334
1335	/** Cache control/info. */
1336	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1337
1338	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1339	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1340	* R0 SS == CS + 8
1341	* R3 CS == CS + 16
1342	* R3 SS == CS + 24
1343	*/
1344	#define MSR_IA32_SYSENTER_CS 0x174
1345	/** SYSENTER_ESP - the R0 ESP. */
1346	#define MSR_IA32_SYSENTER_ESP 0x175
1347	/** SYSENTER_EIP - the R0 EIP. */
1348	#define MSR_IA32_SYSENTER_EIP 0x176
1349	#endif
1350
1351	/** Machine Check Global Capabilities Register. */
1352	#define MSR_IA32_MCG_CAP 0x179
1353	/** Machine Check Global Status Register. */
1354	#define MSR_IA32_MCG_STATUS 0x17A
1355	/** Machine Check Global Control Register. */
1356	#define MSR_IA32_MCG_CTRL 0x17B
1357
1358	/** Page Attribute Table. */
1359	#define MSR_IA32_CR_PAT 0x277
1360	/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1361	* "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1362	#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1363
1364	/** Performance event select MSRs. (Intel only) */
1365	#define MSR_IA32_PERFEVTSEL0 0x186
1366	#define MSR_IA32_PERFEVTSEL1 0x187
1367	#define MSR_IA32_PERFEVTSEL2 0x188
1368	#define MSR_IA32_PERFEVTSEL3 0x189
1369
1370	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1371	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1372	* holds a ratio that Apple takes for TSC granularity.
1373	*
1374	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1375	#define MSR_FLEX_RATIO 0x194
1376	/** Performance state value and starting with Intel core more.
1377	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1378	#define MSR_IA32_PERF_STATUS 0x198
1379	#define MSR_IA32_PERF_CTL 0x199
1380	#define MSR_IA32_THERM_STATUS 0x19c
1381
1382	/** Offcore response event select registers. */
1383	#define MSR_OFFCORE_RSP_0 0x1a6
1384	#define MSR_OFFCORE_RSP_1 0x1a7
1385
1386	/** Enable misc. processor features (R/W). */
1387	#define MSR_IA32_MISC_ENABLE 0x1A0
1388	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1389	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1390	/** Automatic Thermal Control Circuit Enable (R/W). */
1391	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1392	/** Performance Monitoring Available (R). */
1393	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1394	/** Branch Trace Storage Unavailable (R/O). */
1395	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1396	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1397	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1398	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1399	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1400	/** If MONITOR/MWAIT is supported (R/W). */
1401	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1402	/** Limit CPUID Maxval to 3 leafs (R/W). */
1403	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1404	/** When set to 1, xTPR messages are disabled (R/W). */
1405	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1406	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1407	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1408
1409	/** Trace/Profile Resource Control (R/W) */
1410	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1411	/** Last branch record. */
1412	#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1413	/** Branch trace flag (single step on branches). */
1414	#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1415	/** Performance monitoring pin control (AMD only). */
1416	#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1417	#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1418	#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1419	#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1420	/** Trace message enable (Intel only). */
1421	#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1422	/** Branch trace store (Intel only). */
1423	#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1424	/** Branch trace interrupt (Intel only). */
1425	#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1426	/** Branch trace off in privileged code (Intel only). */
1427	#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1428	/** Branch trace off in user code (Intel only). */
1429	#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1430	/** Freeze LBR on PMI flag (Intel only). */
1431	#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1432	/** Freeze PERFMON on PMI flag (Intel only). */
1433	#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1434	/** Freeze while SMM enabled (Intel only). */
1435	#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1436	/** Advanced debugging of RTM regions (Intel only). */
1437	#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1438	/** Debug control MSR valid bits (Intel only). */
1439	#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR \| MSR_IA32_DEBUGCTL_BTF \| MSR_IA32_DEBUGCTL_TR \
1440	\| MSR_IA32_DEBUGCTL_BTS \| MSR_IA32_DEBUGCTL_BTINT \| MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1441	\| MSR_IA32_DEBUGCTL_BTS_OFF_USER \| MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1442	\| MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI \| MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1443	\| MSR_IA32_DEBUGCTL_RTM)
1444
1445	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1446	* @{ */
1447	#define MSR_P4_LASTBRANCH_0 0x1db
1448	#define MSR_P4_LASTBRANCH_1 0x1dc
1449	#define MSR_P4_LASTBRANCH_2 0x1dd
1450	#define MSR_P4_LASTBRANCH_3 0x1de
1451
1452	/** LBR Top-of-stack MSR (index to most recent record). */
1453	#define MSR_P4_LASTBRANCH_TOS 0x1da
1454	/** @} */
1455
1456	/** @name Last branch registers for Core 2 and related Xeons.
1457	* @{ */
1458	#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
1459	#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
1460	#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
1461	#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
1462
1463	#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
1464	#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
1465	#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
1466	#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
1467
1468	/** LBR Top-of-stack MSR (index to most recent record). */
1469	#define MSR_CORE2_LASTBRANCH_TOS 0x1c9
1470	/** @} */
1471
1472	/** @name Last branch registers.
1473	* @{ */
1474	#define MSR_LASTBRANCH_0_FROM_IP 0x680
1475	#define MSR_LASTBRANCH_1_FROM_IP 0x681
1476	#define MSR_LASTBRANCH_2_FROM_IP 0x682
1477	#define MSR_LASTBRANCH_3_FROM_IP 0x683
1478	#define MSR_LASTBRANCH_4_FROM_IP 0x684
1479	#define MSR_LASTBRANCH_5_FROM_IP 0x685
1480	#define MSR_LASTBRANCH_6_FROM_IP 0x686
1481	#define MSR_LASTBRANCH_7_FROM_IP 0x687
1482	#define MSR_LASTBRANCH_8_FROM_IP 0x688
1483	#define MSR_LASTBRANCH_9_FROM_IP 0x689
1484	#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1485	#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1486	#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1487	#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1488	#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1489	#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1490	#define MSR_LASTBRANCH_16_FROM_IP 0x690
1491	#define MSR_LASTBRANCH_17_FROM_IP 0x691
1492	#define MSR_LASTBRANCH_18_FROM_IP 0x692
1493	#define MSR_LASTBRANCH_19_FROM_IP 0x693
1494	#define MSR_LASTBRANCH_20_FROM_IP 0x694
1495	#define MSR_LASTBRANCH_21_FROM_IP 0x695
1496	#define MSR_LASTBRANCH_22_FROM_IP 0x696
1497	#define MSR_LASTBRANCH_23_FROM_IP 0x697
1498	#define MSR_LASTBRANCH_24_FROM_IP 0x698
1499	#define MSR_LASTBRANCH_25_FROM_IP 0x699
1500	#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1501	#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1502	#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1503	#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1504	#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1505	#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1506
1507	#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1508	#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1509	#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1510	#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1511	#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1512	#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1513	#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1514	#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1515	#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1516	#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1517	#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1518	#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1519	#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1520	#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1521	#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1522	#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1523	#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1524	#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1525	#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1526	#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1527	#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1528	#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1529	#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1530	#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1531	#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1532	#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1533	#define MSR_LASTBRANCH_26_TO_IP 0x6da
1534	#define MSR_LASTBRANCH_27_TO_IP 0x6db
1535	#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1536	#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1537	#define MSR_LASTBRANCH_30_TO_IP 0x6de
1538	#define MSR_LASTBRANCH_31_TO_IP 0x6df
1539
1540	#define MSR_LASTBRANCH_0_INFO 0xdc0
1541	#define MSR_LASTBRANCH_1_INFO 0xdc1
1542	#define MSR_LASTBRANCH_2_INFO 0xdc2
1543	#define MSR_LASTBRANCH_3_INFO 0xdc3
1544	#define MSR_LASTBRANCH_4_INFO 0xdc4
1545	#define MSR_LASTBRANCH_5_INFO 0xdc5
1546	#define MSR_LASTBRANCH_6_INFO 0xdc6
1547	#define MSR_LASTBRANCH_7_INFO 0xdc7
1548	#define MSR_LASTBRANCH_8_INFO 0xdc8
1549	#define MSR_LASTBRANCH_9_INFO 0xdc9
1550	#define MSR_LASTBRANCH_10_INFO 0xdca
1551	#define MSR_LASTBRANCH_11_INFO 0xdcb
1552	#define MSR_LASTBRANCH_12_INFO 0xdcc
1553	#define MSR_LASTBRANCH_13_INFO 0xdcd
1554	#define MSR_LASTBRANCH_14_INFO 0xdce
1555	#define MSR_LASTBRANCH_15_INFO 0xdcf
1556	#define MSR_LASTBRANCH_16_INFO 0xdd0
1557	#define MSR_LASTBRANCH_17_INFO 0xdd1
1558	#define MSR_LASTBRANCH_18_INFO 0xdd2
1559	#define MSR_LASTBRANCH_19_INFO 0xdd3
1560	#define MSR_LASTBRANCH_20_INFO 0xdd4
1561	#define MSR_LASTBRANCH_21_INFO 0xdd5
1562	#define MSR_LASTBRANCH_22_INFO 0xdd6
1563	#define MSR_LASTBRANCH_23_INFO 0xdd7
1564	#define MSR_LASTBRANCH_24_INFO 0xdd8
1565	#define MSR_LASTBRANCH_25_INFO 0xdd9
1566	#define MSR_LASTBRANCH_26_INFO 0xdda
1567	#define MSR_LASTBRANCH_27_INFO 0xddb
1568	#define MSR_LASTBRANCH_28_INFO 0xddc
1569	#define MSR_LASTBRANCH_29_INFO 0xddd
1570	#define MSR_LASTBRANCH_30_INFO 0xdde
1571	#define MSR_LASTBRANCH_31_INFO 0xddf
1572
1573	/** LBR branch tracking selection MSR. */
1574	#define MSR_LASTBRANCH_SELECT 0x1c8
1575	/** LBR Top-of-stack MSR (index to most recent record). */
1576	#define MSR_LASTBRANCH_TOS 0x1c9
1577	/** @} */
1578
1579	/** @name Last event record registers.
1580	* @{ */
1581	/** Last event record source IP register. */
1582	#define MSR_LER_FROM_IP 0x1dd
1583	/** Last event record destination IP register. */
1584	#define MSR_LER_TO_IP 0x1de
1585	/** @} */
1586
1587	/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
1588	#define MSR_IA32_TSX_CTRL 0x122
1589
1590	/** Variable range MTRRs.
1591	* @{ */
1592	#define MSR_IA32_MTRR_PHYSBASE0 0x200
1593	#define MSR_IA32_MTRR_PHYSMASK0 0x201
1594	#define MSR_IA32_MTRR_PHYSBASE1 0x202
1595	#define MSR_IA32_MTRR_PHYSMASK1 0x203
1596	#define MSR_IA32_MTRR_PHYSBASE2 0x204
1597	#define MSR_IA32_MTRR_PHYSMASK2 0x205
1598	#define MSR_IA32_MTRR_PHYSBASE3 0x206
1599	#define MSR_IA32_MTRR_PHYSMASK3 0x207
1600	#define MSR_IA32_MTRR_PHYSBASE4 0x208
1601	#define MSR_IA32_MTRR_PHYSMASK4 0x209
1602	#define MSR_IA32_MTRR_PHYSBASE5 0x20a
1603	#define MSR_IA32_MTRR_PHYSMASK5 0x20b
1604	#define MSR_IA32_MTRR_PHYSBASE6 0x20c
1605	#define MSR_IA32_MTRR_PHYSMASK6 0x20d
1606	#define MSR_IA32_MTRR_PHYSBASE7 0x20e
1607	#define MSR_IA32_MTRR_PHYSMASK7 0x20f
1608	#define MSR_IA32_MTRR_PHYSBASE8 0x210
1609	#define MSR_IA32_MTRR_PHYSMASK8 0x211
1610	#define MSR_IA32_MTRR_PHYSBASE9 0x212
1611	#define MSR_IA32_MTRR_PHYSMASK9 0x213
1612	/** @} */
1613
1614	/** Fixed range MTRRs.
1615	* @{ */
1616	#define MSR_IA32_MTRR_FIX64K_00000 0x250
1617	#define MSR_IA32_MTRR_FIX16K_80000 0x258
1618	#define MSR_IA32_MTRR_FIX16K_A0000 0x259
1619	#define MSR_IA32_MTRR_FIX4K_C0000 0x268
1620	#define MSR_IA32_MTRR_FIX4K_C8000 0x269
1621	#define MSR_IA32_MTRR_FIX4K_D0000 0x26a
1622	#define MSR_IA32_MTRR_FIX4K_D8000 0x26b
1623	#define MSR_IA32_MTRR_FIX4K_E0000 0x26c
1624	#define MSR_IA32_MTRR_FIX4K_E8000 0x26d
1625	#define MSR_IA32_MTRR_FIX4K_F0000 0x26e
1626	#define MSR_IA32_MTRR_FIX4K_F8000 0x26f
1627	/** @} */
1628
1629	/** MTRR Default Range. */
1630	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1631
1632	/** Global performance counter control facilities (Intel only). */
1633	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1634	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1635	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1636
1637	/** Precise Event Based sampling (Intel only). */
1638	#define MSR_IA32_PEBS_ENABLE 0x3F1
1639
1640	#define MSR_IA32_MC0_CTL 0x400
1641	#define MSR_IA32_MC0_STATUS 0x401
1642
1643	/** Basic VMX information. */
1644	#define MSR_IA32_VMX_BASIC 0x480
1645	/** Allowed settings for pin-based VM execution controls. */
1646	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1647	/** Allowed settings for proc-based VM execution controls. */
1648	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1649	/** Allowed settings for the VM-exit controls. */
1650	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1651	/** Allowed settings for the VM-entry controls. */
1652	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1653	/** Misc VMX info. */
1654	#define MSR_IA32_VMX_MISC 0x485
1655	/** Fixed cleared bits in CR0. */
1656	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1657	/** Fixed set bits in CR0. */
1658	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1659	/** Fixed cleared bits in CR4. */
1660	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1661	/** Fixed set bits in CR4. */
1662	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1663	/** Information for enumerating fields in the VMCS. */
1664	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1665	/** Allowed settings for secondary processor-based VM-execution controls. */
1666	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1667	/** EPT capabilities. */
1668	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1669	/** Allowed settings of all pin-based VM execution controls. */
1670	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1671	/** Allowed settings of all proc-based VM execution controls. */
1672	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1673	/** Allowed settings of all VMX exit controls. */
1674	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1675	/** Allowed settings of all VMX entry controls. */
1676	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1677	/** Allowed settings for the VM-function controls. */
1678	#define MSR_IA32_VMX_VMFUNC 0x491
1679	/** Tertiary processor-based VM execution controls. */
1680	#define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
1681
1682	/** Intel PT - Enable and control for trace packet generation. */
1683	#define MSR_IA32_RTIT_CTL 0x570
1684
1685	/** DS Save Area (R/W). */
1686	#define MSR_IA32_DS_AREA 0x600
1687	/** Running Average Power Limit (RAPL) power units. */
1688	#define MSR_RAPL_POWER_UNIT 0x606
1689	/** Package C3 Interrupt Response Limit. */
1690	#define MSR_PKGC3_IRTL 0x60a
1691	/** Package C6/C7S Interrupt Response Limit 1. */
1692	#define MSR_PKGC_IRTL1 0x60b
1693	/** Package C6/C7S Interrupt Response Limit 2. */
1694	#define MSR_PKGC_IRTL2 0x60c
1695	/** Package C2 Residency Counter. */
1696	#define MSR_PKG_C2_RESIDENCY 0x60d
1697	/** PKG RAPL Power Limit Control. */
1698	#define MSR_PKG_POWER_LIMIT 0x610
1699	/** PKG Energy Status. */
1700	#define MSR_PKG_ENERGY_STATUS 0x611
1701	/** PKG Perf Status. */
1702	#define MSR_PKG_PERF_STATUS 0x613
1703	/** PKG RAPL Parameters. */
1704	#define MSR_PKG_POWER_INFO 0x614
1705	/** DRAM RAPL Power Limit Control. */
1706	#define MSR_DRAM_POWER_LIMIT 0x618
1707	/** DRAM Energy Status. */
1708	#define MSR_DRAM_ENERGY_STATUS 0x619
1709	/** DRAM Performance Throttling Status. */
1710	#define MSR_DRAM_PERF_STATUS 0x61b
1711	/** DRAM RAPL Parameters. */
1712	#define MSR_DRAM_POWER_INFO 0x61c
1713	/** Package C10 Residency Counter. */
1714	#define MSR_PKG_C10_RESIDENCY 0x632
1715	/** PP0 Energy Status. */
1716	#define MSR_PP0_ENERGY_STATUS 0x639
1717	/** PP1 Energy Status. */
1718	#define MSR_PP1_ENERGY_STATUS 0x641
1719	/** Turbo Activation Ratio. */
1720	#define MSR_TURBO_ACTIVATION_RATIO 0x64c
1721	/** Core Performance Limit Reasons. */
1722	#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
1723
1724	/** X2APIC MSR range start. */
1725	#define MSR_IA32_X2APIC_START 0x800
1726	/** X2APIC MSR - APIC ID Register. */
1727	#define MSR_IA32_X2APIC_ID 0x802
1728	/** X2APIC MSR - APIC Version Register. */
1729	#define MSR_IA32_X2APIC_VERSION 0x803
1730	/** X2APIC MSR - Task Priority Register. */
1731	#define MSR_IA32_X2APIC_TPR 0x808
1732	/** X2APIC MSR - Processor Priority register. */
1733	#define MSR_IA32_X2APIC_PPR 0x80A
1734	/** X2APIC MSR - End Of Interrupt register. */
1735	#define MSR_IA32_X2APIC_EOI 0x80B
1736	/** X2APIC MSR - Logical Destination Register. */
1737	#define MSR_IA32_X2APIC_LDR 0x80D
1738	/** X2APIC MSR - Spurious Interrupt Vector Register. */
1739	#define MSR_IA32_X2APIC_SVR 0x80F
1740	/** X2APIC MSR - In-service Register (bits 31:0). */
1741	#define MSR_IA32_X2APIC_ISR0 0x810
1742	/** X2APIC MSR - In-service Register (bits 63:32). */
1743	#define MSR_IA32_X2APIC_ISR1 0x811
1744	/** X2APIC MSR - In-service Register (bits 95:64). */
1745	#define MSR_IA32_X2APIC_ISR2 0x812
1746	/** X2APIC MSR - In-service Register (bits 127:96). */
1747	#define MSR_IA32_X2APIC_ISR3 0x813
1748	/** X2APIC MSR - In-service Register (bits 159:128). */
1749	#define MSR_IA32_X2APIC_ISR4 0x814
1750	/** X2APIC MSR - In-service Register (bits 191:160). */
1751	#define MSR_IA32_X2APIC_ISR5 0x815
1752	/** X2APIC MSR - In-service Register (bits 223:192). */
1753	#define MSR_IA32_X2APIC_ISR6 0x816
1754	/** X2APIC MSR - In-service Register (bits 255:224). */
1755	#define MSR_IA32_X2APIC_ISR7 0x817
1756	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1757	#define MSR_IA32_X2APIC_TMR0 0x818
1758	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1759	#define MSR_IA32_X2APIC_TMR1 0x819
1760	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1761	#define MSR_IA32_X2APIC_TMR2 0x81A
1762	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1763	#define MSR_IA32_X2APIC_TMR3 0x81B
1764	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1765	#define MSR_IA32_X2APIC_TMR4 0x81C
1766	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1767	#define MSR_IA32_X2APIC_TMR5 0x81D
1768	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1769	#define MSR_IA32_X2APIC_TMR6 0x81E
1770	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1771	#define MSR_IA32_X2APIC_TMR7 0x81F
1772	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1773	#define MSR_IA32_X2APIC_IRR0 0x820
1774	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1775	#define MSR_IA32_X2APIC_IRR1 0x821
1776	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1777	#define MSR_IA32_X2APIC_IRR2 0x822
1778	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1779	#define MSR_IA32_X2APIC_IRR3 0x823
1780	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1781	#define MSR_IA32_X2APIC_IRR4 0x824
1782	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1783	#define MSR_IA32_X2APIC_IRR5 0x825
1784	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1785	#define MSR_IA32_X2APIC_IRR6 0x826
1786	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1787	#define MSR_IA32_X2APIC_IRR7 0x827
1788	/** X2APIC MSR - Error Status Register. */
1789	#define MSR_IA32_X2APIC_ESR 0x828
1790	/** X2APIC MSR - LVT CMCI Register. */
1791	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1792	/** X2APIC MSR - Interrupt Command Register. */
1793	#define MSR_IA32_X2APIC_ICR 0x830
1794	/** X2APIC MSR - LVT Timer Register. */
1795	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1796	/** X2APIC MSR - LVT Thermal Sensor Register. */
1797	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1798	/** X2APIC MSR - LVT Performance Counter Register. */
1799	#define MSR_IA32_X2APIC_LVT_PERF 0x834
1800	/** X2APIC MSR - LVT LINT0 Register. */
1801	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1802	/** X2APIC MSR - LVT LINT1 Register. */
1803	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1804	/** X2APIC MSR - LVT Error Register . */
1805	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1806	/** X2APIC MSR - Timer Initial Count Register. */
1807	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1808	/** X2APIC MSR - Timer Current Count Register. */
1809	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1810	/** X2APIC MSR - Timer Divide Configuration Register. */
1811	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1812	/** X2APIC MSR - Self IPI. */
1813	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1814	/** X2APIC MSR range end. */
1815	#define MSR_IA32_X2APIC_END 0x8FF
1816	/** X2APIC MSR - LVT start range. */
1817	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1818	/** X2APIC MSR - LVT end range (inclusive). */
1819	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1820
1821	/** K6 EFER - Extended Feature Enable Register. */
1822	#define MSR_K6_EFER UINT32_C(0xc0000080)
1823	/** @todo document EFER */
1824	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1825	#define MSR_K6_EFER_SCE RT_BIT_32(0)
1826	/** Bit 8 - LME - Long mode enabled. (R/W) */
1827	#define MSR_K6_EFER_LME RT_BIT_32(8)
1828	#define MSR_K6_EFER_BIT_LME 8 /*< Bit number of MSR_K6_EFER_LME /
1829	/** Bit 10 - LMA - Long mode active. (R) */
1830	#define MSR_K6_EFER_LMA RT_BIT_32(10)
1831	#define MSR_K6_EFER_BIT_LMA 10 /*< Bit number of MSR_K6_EFER_LMA /
1832	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1833	#define MSR_K6_EFER_NXE RT_BIT_32(11)
1834	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
1835	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1836	#define MSR_K6_EFER_SVME RT_BIT_32(12)
1837	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1838	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1839	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1840	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1841	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1842	#define MSR_K6_EFER_TCE RT_BIT_32(15)
1843	/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
1844	#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
1845
1846	/** K6 STAR - SYSCALL/RET targets. */
1847	#define MSR_K6_STAR UINT32_C(0xc0000081)
1848	/** Shift value for getting the SYSRET CS and SS value. */
1849	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1850	/** Shift value for getting the SYSCALL CS and SS value. */
1851	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1852	/** Selector mask for use after shifting. */
1853	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1854	/** The mask which give the SYSCALL EIP. */
1855	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1856	/** K6 WHCR - Write Handling Control Register. */
1857	#define MSR_K6_WHCR UINT32_C(0xc0000082)
1858	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1859	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1860	/** K6 PSOR - Processor State Observability Register. */
1861	#define MSR_K6_PSOR UINT32_C(0xc0000087)
1862	/** K6 PFIR - Page Flush/Invalidate Register. */
1863	#define MSR_K6_PFIR UINT32_C(0xc0000088)
1864
1865	/** Performance counter MSRs. (AMD only) */
1866	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1867	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1868	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1869	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1870	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1871	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1872	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1873	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1874
1875	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1876	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1877	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1878	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1879	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1880	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1881	/** K8 FS.base - The 64-bit base FS register. */
1882	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1883	/** K8 GS.base - The 64-bit base GS register. */
1884	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1885	/** K8 KernelGSbase - Used with SWAPGS. */
1886	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1887	/** K8 TSC_AUX - Used with RDTSCP. */
1888	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1889	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1890	#define MSR_K8_HWCR UINT32_C(0xc0010015)
1891	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1892	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1893	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1894	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1895	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1896	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1897
1898	/** SMM MSRs. */
1899	#define MSR_K7_SMBASE UINT32_C(0xc0010111)
1900	#define MSR_K7_SMM_ADDR UINT32_C(0xc0010112)
1901	#define MSR_K7_SMM_MASK UINT32_C(0xc0010113)
1902
1903	/** North bridge config? See BIOS & Kernel dev guides for
1904	* details. */
1905	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1906
1907	/** Hypertransport interrupt pending register.
1908	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1909	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1910
1911	/** SVM Control. */
1912	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1913	/** Disables HDT (Hardware Debug Tool) and certain internal debug
1914	* features. */
1915	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1916	/** If set, non-intercepted INIT signals are converted to \#SX
1917	* exceptions. */
1918	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1919	/** Disables A20 masking. */
1920	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1921	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1922	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1923	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1924	* clear, EFER.SVME can be written normally. */
1925	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1926
1927	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1928	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1929	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1930	* host state during world switch. */
1931	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1932
1933	/** Virtualized speculation control for AMD processors.
1934	*
1935	* Unified interface among different CPU generations.
1936	* The VMM will set any architectural MSRs based on the CPU.
1937	* See "White Paper: AMD64 Technology Speculative Store Bypass Disable 5.21.18"
1938	* (12441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf) */
1939	#define MSR_AMD_VIRT_SPEC_CTL UINT32_C(0xc001011f)
1940	/** Speculative Store Bypass Disable. */
1941	# define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
1942
1943	/** @} */
1944
1945
1946	/** @name Page Table / Directory / Directory Pointers / L4.
1947	* @{
1948	*/
1949
1950	/** Page table/directory entry as an unsigned integer. */
1951	typedef uint32_t X86PGUINT;
1952	/** Pointer to a page table/directory table entry as an unsigned integer. */
1953	typedef X86PGUINT *PX86PGUINT;
1954	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1955	typedef X86PGUINT const *PCX86PGUINT;
1956
1957	/** Number of entries in a 32-bit PT/PD. */
1958	#define X86_PG_ENTRIES 1024
1959
1960
1961	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1962	typedef uint64_t X86PGPAEUINT;
1963	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1964	typedef X86PGPAEUINT *PX86PGPAEUINT;
1965	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
1966	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
1967
1968	/** Number of entries in a PAE PT/PD. */
1969	#define X86_PG_PAE_ENTRIES 512
1970	/** Number of entries in a PAE PDPT. */
1971	#define X86_PG_PAE_PDPE_ENTRIES 4
1972
1973	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
1974	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
1975	/** Number of entries in an AMD64 PDPT.
1976	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
1977	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
1978
1979	/** The size of a default page. */
1980	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
1981	/** The page shift of a default page. */
1982	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
1983	/** The default page offset mask. */
1984	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
1985	/** The default page base mask for virtual addresses. */
1986	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
1987	/** The default page base mask for virtual addresses - 32bit version. */
1988	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
1989
1990	/** The size of a 4KB page. */
1991	#define X86_PAGE_4K_SIZE _4K
1992	/** The page shift of a 4KB page. */
1993	#define X86_PAGE_4K_SHIFT 12
1994	/** The 4KB page offset mask. */
1995	#define X86_PAGE_4K_OFFSET_MASK 0xfff
1996	/** The 4KB page base mask for virtual addresses. */
1997	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
1998	/** The 4KB page base mask for virtual addresses - 32bit version. */
1999	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
2000
2001	/** The size of a 2MB page. */
2002	#define X86_PAGE_2M_SIZE _2M
2003	/** The page shift of a 2MB page. */
2004	#define X86_PAGE_2M_SHIFT 21
2005	/** The 2MB page offset mask. */
2006	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
2007	/** The 2MB page base mask for virtual addresses. */
2008	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
2009	/** The 2MB page base mask for virtual addresses - 32bit version. */
2010	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
2011
2012	/** The size of a 4MB page. */
2013	#define X86_PAGE_4M_SIZE _4M
2014	/** The page shift of a 4MB page. */
2015	#define X86_PAGE_4M_SHIFT 22
2016	/** The 4MB page offset mask. */
2017	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
2018	/** The 4MB page base mask for virtual addresses. */
2019	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
2020	/** The 4MB page base mask for virtual addresses - 32bit version. */
2021	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
2022
2023	/** The size of a 1GB page. */
2024	#define X86_PAGE_1G_SIZE _1G
2025	/** The page shift of a 1GB page. */
2026	#define X86_PAGE_1G_SHIFT 30
2027	/** The 1GB page offset mask. */
2028	#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
2029	/** The 1GB page base mask for virtual addresses. */
2030	#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
2031
2032	/**
2033	* Check if the given address is canonical.
2034	*/
2035	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
2036
2037	/**
2038	* Gets the page base mask given the page shift.
2039	*/
2040	#define X86_GET_PAGE_BASE_MASK(a_cShift) (UINT64_C(0xffffffffffffffff) << (a_cShift))
2041
2042	/**
2043	* Gets the page offset mask given the page shift.
2044	*/
2045	#define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
2046
2047
2048	/** @name Page Table Entry
2049	* @{
2050	*/
2051	/** Bit 0 - P - Present bit. */
2052	#define X86_PTE_BIT_P 0
2053	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2054	#define X86_PTE_BIT_RW 1
2055	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2056	#define X86_PTE_BIT_US 2
2057	/** Bit 3 - PWT - Page level write thru bit. */
2058	#define X86_PTE_BIT_PWT 3
2059	/** Bit 4 - PCD - Page level cache disable bit. */
2060	#define X86_PTE_BIT_PCD 4
2061	/** Bit 5 - A - Access bit. */
2062	#define X86_PTE_BIT_A 5
2063	/** Bit 6 - D - Dirty bit. */
2064	#define X86_PTE_BIT_D 6
2065	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2066	#define X86_PTE_BIT_PAT 7
2067	/** Bit 8 - G - Global flag. */
2068	#define X86_PTE_BIT_G 8
2069	/** Bits 63 - NX - PAE/LM - No execution flag. */
2070	#define X86_PTE_PAE_BIT_NX 63
2071
2072	/** Bit 0 - P - Present bit mask. */
2073	#define X86_PTE_P RT_BIT_32(0)
2074	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
2075	#define X86_PTE_RW RT_BIT_32(1)
2076	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
2077	#define X86_PTE_US RT_BIT_32(2)
2078	/** Bit 3 - PWT - Page level write thru bit mask. */
2079	#define X86_PTE_PWT RT_BIT_32(3)
2080	/** Bit 4 - PCD - Page level cache disable bit mask. */
2081	#define X86_PTE_PCD RT_BIT_32(4)
2082	/** Bit 5 - A - Access bit mask. */
2083	#define X86_PTE_A RT_BIT_32(5)
2084	/** Bit 6 - D - Dirty bit mask. */
2085	#define X86_PTE_D RT_BIT_32(6)
2086	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
2087	#define X86_PTE_PAT RT_BIT_32(7)
2088	/** Bit 8 - G - Global bit mask. */
2089	#define X86_PTE_G RT_BIT_32(8)
2090
2091	/** Bits 9-11 - - Available for use to system software. */
2092	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2093	/** Bits 12-31 - - Physical Page number of the next level. */
2094	#define X86_PTE_PG_MASK ( 0xfffff000 )
2095
2096	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2097	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2098	/** Bits 63 - NX - PAE/LM - No execution flag. */
2099	#define X86_PTE_PAE_NX RT_BIT_64(63)
2100	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
2101	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
2102	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
2103	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
2104	/** No bits - - LM - MBZ bits when NX is active. */
2105	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
2106	/** Bits 63 - - LM - MBZ bits when no NX. */
2107	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
2108
2109	/**
2110	* Page table entry.
2111	*/
2112	typedef struct X86PTEBITS
2113	{
2114	/** Flags whether(=1) or not the page is present. */
2115	uint32_t u1Present : 1;
2116	/** Read(=0) / Write(=1) flag. */
2117	uint32_t u1Write : 1;
2118	/** User(=1) / Supervisor (=0) flag. */
2119	uint32_t u1User : 1;
2120	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2121	uint32_t u1WriteThru : 1;
2122	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2123	uint32_t u1CacheDisable : 1;
2124	/** Accessed flag.
2125	* Indicates that the page have been read or written to. */
2126	uint32_t u1Accessed : 1;
2127	/** Dirty flag.
2128	* Indicates that the page has been written to. */
2129	uint32_t u1Dirty : 1;
2130	/** Reserved / If PAT enabled, bit 2 of the index. */
2131	uint32_t u1PAT : 1;
2132	/** Global flag. (Ignored in all but final level.) */
2133	uint32_t u1Global : 1;
2134	/** Available for use to system software. */
2135	uint32_t u3Available : 3;
2136	/** Physical Page number of the next level. */
2137	uint32_t u20PageNo : 20;
2138	} X86PTEBITS;
2139	#ifndef VBOX_FOR_DTRACE_LIB
2140	AssertCompileSize(X86PTEBITS, 4);
2141	#endif
2142	/** Pointer to a page table entry. */
2143	typedef X86PTEBITS *PX86PTEBITS;
2144	/** Pointer to a const page table entry. */
2145	typedef const X86PTEBITS *PCX86PTEBITS;
2146
2147	/**
2148	* Page table entry.
2149	*/
2150	typedef union X86PTE
2151	{
2152	/** Unsigned integer view */
2153	X86PGUINT u;
2154	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2155	/** Bit field view. */
2156	X86PTEBITS n;
2157	#endif
2158	/** 32-bit view. */
2159	uint32_t au32[1];
2160	/** 16-bit view. */
2161	uint16_t au16[2];
2162	/** 8-bit view. */
2163	uint8_t au8[4];
2164	} X86PTE;
2165	#ifndef VBOX_FOR_DTRACE_LIB
2166	AssertCompileSize(X86PTE, 4);
2167	#endif
2168	/** Pointer to a page table entry. */
2169	typedef X86PTE *PX86PTE;
2170	/** Pointer to a const page table entry. */
2171	typedef const X86PTE *PCX86PTE;
2172
2173
2174	/**
2175	* PAE page table entry.
2176	*/
2177	typedef struct X86PTEPAEBITS
2178	{
2179	/** Flags whether(=1) or not the page is present. */
2180	uint32_t u1Present : 1;
2181	/** Read(=0) / Write(=1) flag. */
2182	uint32_t u1Write : 1;
2183	/** User(=1) / Supervisor(=0) flag. */
2184	uint32_t u1User : 1;
2185	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2186	uint32_t u1WriteThru : 1;
2187	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2188	uint32_t u1CacheDisable : 1;
2189	/** Accessed flag.
2190	* Indicates that the page have been read or written to. */
2191	uint32_t u1Accessed : 1;
2192	/** Dirty flag.
2193	* Indicates that the page has been written to. */
2194	uint32_t u1Dirty : 1;
2195	/** Reserved / If PAT enabled, bit 2 of the index. */
2196	uint32_t u1PAT : 1;
2197	/** Global flag. (Ignored in all but final level.) */
2198	uint32_t u1Global : 1;
2199	/** Available for use to system software. */
2200	uint32_t u3Available : 3;
2201	/** Physical Page number of the next level - Low Part. Don't use this. */
2202	uint32_t u20PageNoLow : 20;
2203	/** Physical Page number of the next level - High Part. Don't use this. */
2204	uint32_t u20PageNoHigh : 20;
2205	/** MBZ bits */
2206	uint32_t u11Reserved : 11;
2207	/** No Execute flag. */
2208	uint32_t u1NoExecute : 1;
2209	} X86PTEPAEBITS;
2210	#ifndef VBOX_FOR_DTRACE_LIB
2211	AssertCompileSize(X86PTEPAEBITS, 8);
2212	#endif
2213	/** Pointer to a page table entry. */
2214	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2215	/** Pointer to a page table entry. */
2216	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2217
2218	/**
2219	* PAE Page table entry.
2220	*/
2221	typedef union X86PTEPAE
2222	{
2223	/** Unsigned integer view */
2224	X86PGPAEUINT u;
2225	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2226	/** Bit field view. */
2227	X86PTEPAEBITS n;
2228	#endif
2229	/** 32-bit view. */
2230	uint32_t au32[2];
2231	/** 16-bit view. */
2232	uint16_t au16[4];
2233	/** 8-bit view. */
2234	uint8_t au8[8];
2235	} X86PTEPAE;
2236	#ifndef VBOX_FOR_DTRACE_LIB
2237	AssertCompileSize(X86PTEPAE, 8);
2238	#endif
2239	/** Pointer to a PAE page table entry. */
2240	typedef X86PTEPAE *PX86PTEPAE;
2241	/** Pointer to a const PAE page table entry. */
2242	typedef const X86PTEPAE *PCX86PTEPAE;
2243	/** @} */
2244
2245	/**
2246	* Page table.
2247	*/
2248	typedef struct X86PT
2249	{
2250	/** PTE Array. */
2251	X86PTE a[X86_PG_ENTRIES];
2252	} X86PT;
2253	#ifndef VBOX_FOR_DTRACE_LIB
2254	AssertCompileSize(X86PT, 4096);
2255	#endif
2256	/** Pointer to a page table. */
2257	typedef X86PT *PX86PT;
2258	/** Pointer to a const page table. */
2259	typedef const X86PT *PCX86PT;
2260
2261	/** The page shift to get the PT index. */
2262	#define X86_PT_SHIFT 12
2263	/** The PT index mask (apply to a shifted page address). */
2264	#define X86_PT_MASK 0x3ff
2265
2266
2267	/**
2268	* Page directory.
2269	*/
2270	typedef struct X86PTPAE
2271	{
2272	/** PTE Array. */
2273	X86PTEPAE a[X86_PG_PAE_ENTRIES];
2274	} X86PTPAE;
2275	#ifndef VBOX_FOR_DTRACE_LIB
2276	AssertCompileSize(X86PTPAE, 4096);
2277	#endif
2278	/** Pointer to a page table. */
2279	typedef X86PTPAE *PX86PTPAE;
2280	/** Pointer to a const page table. */
2281	typedef const X86PTPAE *PCX86PTPAE;
2282
2283	/** The page shift to get the PA PTE index. */
2284	#define X86_PT_PAE_SHIFT 12
2285	/** The PAE PT index mask (apply to a shifted page address). */
2286	#define X86_PT_PAE_MASK 0x1ff
2287
2288
2289	/** @name 4KB Page Directory Entry
2290	* @{
2291	*/
2292	/** Bit 0 - P - Present bit. */
2293	#define X86_PDE_P RT_BIT_32(0)
2294	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2295	#define X86_PDE_RW RT_BIT_32(1)
2296	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2297	#define X86_PDE_US RT_BIT_32(2)
2298	/** Bit 3 - PWT - Page level write thru bit. */
2299	#define X86_PDE_PWT RT_BIT_32(3)
2300	/** Bit 4 - PCD - Page level cache disable bit. */
2301	#define X86_PDE_PCD RT_BIT_32(4)
2302	/** Bit 5 - A - Access bit. */
2303	#define X86_PDE_A RT_BIT_32(5)
2304	/** Bit 7 - PS - Page size attribute.
2305	* Clear mean 4KB pages, set means large pages (2/4MB). */
2306	#define X86_PDE_PS RT_BIT_32(7)
2307	/** Bits 9-11 - - Available for use to system software. */
2308	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2309	/** Bits 12-31 - - Physical Page number of the next level. */
2310	#define X86_PDE_PG_MASK ( 0xfffff000 )
2311
2312	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2313	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2314	/** Bits 63 - NX - PAE/LM - No execution flag. */
2315	#define X86_PDE_PAE_NX RT_BIT_64(63)
2316	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2317	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2318	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2319	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2320	/** Bit 7 - - LM - MBZ bits when NX is active. */
2321	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2322	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2323	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2324
2325	/**
2326	* Page directory entry.
2327	*/
2328	typedef struct X86PDEBITS
2329	{
2330	/** Flags whether(=1) or not the page is present. */
2331	uint32_t u1Present : 1;
2332	/** Read(=0) / Write(=1) flag. */
2333	uint32_t u1Write : 1;
2334	/** User(=1) / Supervisor (=0) flag. */
2335	uint32_t u1User : 1;
2336	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2337	uint32_t u1WriteThru : 1;
2338	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2339	uint32_t u1CacheDisable : 1;
2340	/** Accessed flag.
2341	* Indicates that the page has been read or written to. */
2342	uint32_t u1Accessed : 1;
2343	/** Reserved / Ignored (dirty bit). */
2344	uint32_t u1Reserved0 : 1;
2345	/** Size bit if PSE is enabled - in any event it's 0. */
2346	uint32_t u1Size : 1;
2347	/** Reserved / Ignored (global bit). */
2348	uint32_t u1Reserved1 : 1;
2349	/** Available for use to system software. */
2350	uint32_t u3Available : 3;
2351	/** Physical Page number of the next level. */
2352	uint32_t u20PageNo : 20;
2353	} X86PDEBITS;
2354	#ifndef VBOX_FOR_DTRACE_LIB
2355	AssertCompileSize(X86PDEBITS, 4);
2356	#endif
2357	/** Pointer to a page directory entry. */
2358	typedef X86PDEBITS *PX86PDEBITS;
2359	/** Pointer to a const page directory entry. */
2360	typedef const X86PDEBITS *PCX86PDEBITS;
2361
2362
2363	/**
2364	* PAE page directory entry.
2365	*/
2366	typedef struct X86PDEPAEBITS
2367	{
2368	/** Flags whether(=1) or not the page is present. */
2369	uint32_t u1Present : 1;
2370	/** Read(=0) / Write(=1) flag. */
2371	uint32_t u1Write : 1;
2372	/** User(=1) / Supervisor (=0) flag. */
2373	uint32_t u1User : 1;
2374	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2375	uint32_t u1WriteThru : 1;
2376	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2377	uint32_t u1CacheDisable : 1;
2378	/** Accessed flag.
2379	* Indicates that the page has been read or written to. */
2380	uint32_t u1Accessed : 1;
2381	/** Reserved / Ignored (dirty bit). */
2382	uint32_t u1Reserved0 : 1;
2383	/** Size bit if PSE is enabled - in any event it's 0. */
2384	uint32_t u1Size : 1;
2385	/** Reserved / Ignored (global bit). / */
2386	uint32_t u1Reserved1 : 1;
2387	/** Available for use to system software. */
2388	uint32_t u3Available : 3;
2389	/** Physical Page number of the next level - Low Part. Don't use! */
2390	uint32_t u20PageNoLow : 20;
2391	/** Physical Page number of the next level - High Part. Don't use! */
2392	uint32_t u20PageNoHigh : 20;
2393	/** MBZ bits */
2394	uint32_t u11Reserved : 11;
2395	/** No Execute flag. */
2396	uint32_t u1NoExecute : 1;
2397	} X86PDEPAEBITS;
2398	#ifndef VBOX_FOR_DTRACE_LIB
2399	AssertCompileSize(X86PDEPAEBITS, 8);
2400	#endif
2401	/** Pointer to a page directory entry. */
2402	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2403	/** Pointer to a const page directory entry. */
2404	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2405
2406	/** @} */
2407
2408
2409	/** @name 2/4MB Page Directory Entry
2410	* @{
2411	*/
2412	/** Bit 0 - P - Present bit. */
2413	#define X86_PDE4M_P RT_BIT_32(0)
2414	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2415	#define X86_PDE4M_RW RT_BIT_32(1)
2416	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2417	#define X86_PDE4M_US RT_BIT_32(2)
2418	/** Bit 3 - PWT - Page level write thru bit. */
2419	#define X86_PDE4M_PWT RT_BIT_32(3)
2420	/** Bit 4 - PCD - Page level cache disable bit. */
2421	#define X86_PDE4M_PCD RT_BIT_32(4)
2422	/** Bit 5 - A - Access bit. */
2423	#define X86_PDE4M_A RT_BIT_32(5)
2424	/** Bit 6 - D - Dirty bit. */
2425	#define X86_PDE4M_D RT_BIT_32(6)
2426	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2427	#define X86_PDE4M_PS RT_BIT_32(7)
2428	/** Bit 8 - G - Global flag. */
2429	#define X86_PDE4M_G RT_BIT_32(8)
2430	/** Bits 9-11 - AVL - Available for use to system software. */
2431	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2432	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2433	#define X86_PDE4M_PAT RT_BIT_32(12)
2434	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2435	#define X86_PDE4M_PAT_SHIFT (12 - 7)
2436	/** Bits 22-31 - - Physical Page number. */
2437	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2438	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2439	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2440	/** The number of bits to the high part of the page number. */
2441	#define X86_PDE4M_PG_HIGH_SHIFT 19
2442	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2443	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2444
2445	/** Bits 21-51 - - PAE/LM - Physical Page number.
2446	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2447	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2448	/** Bits 63 - NX - PAE/LM - No execution flag. */
2449	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2450	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2451	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2452	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2453	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2454	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2455	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2456	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2457	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2458
2459	/**
2460	* 4MB page directory entry.
2461	*/
2462	typedef struct X86PDE4MBITS
2463	{
2464	/** Flags whether(=1) or not the page is present. */
2465	uint32_t u1Present : 1;
2466	/** Read(=0) / Write(=1) flag. */
2467	uint32_t u1Write : 1;
2468	/** User(=1) / Supervisor (=0) flag. */
2469	uint32_t u1User : 1;
2470	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2471	uint32_t u1WriteThru : 1;
2472	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2473	uint32_t u1CacheDisable : 1;
2474	/** Accessed flag.
2475	* Indicates that the page have been read or written to. */
2476	uint32_t u1Accessed : 1;
2477	/** Dirty flag.
2478	* Indicates that the page has been written to. */
2479	uint32_t u1Dirty : 1;
2480	/** Page size flag - always 1 for 4MB entries. */
2481	uint32_t u1Size : 1;
2482	/** Global flag. */
2483	uint32_t u1Global : 1;
2484	/** Available for use to system software. */
2485	uint32_t u3Available : 3;
2486	/** Reserved / If PAT enabled, bit 2 of the index. */
2487	uint32_t u1PAT : 1;
2488	/** Bits 32-39 of the page number on AMD64.
2489	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2490	uint32_t u8PageNoHigh : 8;
2491	/** Reserved. */
2492	uint32_t u1Reserved : 1;
2493	/** Physical Page number of the page. */
2494	uint32_t u10PageNo : 10;
2495	} X86PDE4MBITS;
2496	#ifndef VBOX_FOR_DTRACE_LIB
2497	AssertCompileSize(X86PDE4MBITS, 4);
2498	#endif
2499	/** Pointer to a page table entry. */
2500	typedef X86PDE4MBITS *PX86PDE4MBITS;
2501	/** Pointer to a const page table entry. */
2502	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2503
2504
2505	/**
2506	* 2MB PAE page directory entry.
2507	*/
2508	typedef struct X86PDE2MPAEBITS
2509	{
2510	/** Flags whether(=1) or not the page is present. */
2511	uint32_t u1Present : 1;
2512	/** Read(=0) / Write(=1) flag. */
2513	uint32_t u1Write : 1;
2514	/** User(=1) / Supervisor(=0) flag. */
2515	uint32_t u1User : 1;
2516	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2517	uint32_t u1WriteThru : 1;
2518	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2519	uint32_t u1CacheDisable : 1;
2520	/** Accessed flag.
2521	* Indicates that the page have been read or written to. */
2522	uint32_t u1Accessed : 1;
2523	/** Dirty flag.
2524	* Indicates that the page has been written to. */
2525	uint32_t u1Dirty : 1;
2526	/** Page size flag - always 1 for 2MB entries. */
2527	uint32_t u1Size : 1;
2528	/** Global flag. */
2529	uint32_t u1Global : 1;
2530	/** Available for use to system software. */
2531	uint32_t u3Available : 3;
2532	/** Reserved / If PAT enabled, bit 2 of the index. */
2533	uint32_t u1PAT : 1;
2534	/** Reserved. */
2535	uint32_t u9Reserved : 9;
2536	/** Physical Page number of the next level - Low part. Don't use! */
2537	uint32_t u10PageNoLow : 10;
2538	/** Physical Page number of the next level - High part. Don't use! */
2539	uint32_t u20PageNoHigh : 20;
2540	/** MBZ bits */
2541	uint32_t u11Reserved : 11;
2542	/** No Execute flag. */
2543	uint32_t u1NoExecute : 1;
2544	} X86PDE2MPAEBITS;
2545	#ifndef VBOX_FOR_DTRACE_LIB
2546	AssertCompileSize(X86PDE2MPAEBITS, 8);
2547	#endif
2548	/** Pointer to a 2MB PAE page table entry. */
2549	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2550	/** Pointer to a 2MB PAE page table entry. */
2551	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2552
2553	/** @} */
2554
2555	/**
2556	* Page directory entry.
2557	*/
2558	typedef union X86PDE
2559	{
2560	/** Unsigned integer view. */
2561	X86PGUINT u;
2562	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2563	/** Normal view. */
2564	X86PDEBITS n;
2565	/** 4MB view (big). */
2566	X86PDE4MBITS b;
2567	#endif
2568	/** 8 bit unsigned integer view. */
2569	uint8_t au8[4];
2570	/** 16 bit unsigned integer view. */
2571	uint16_t au16[2];
2572	/** 32 bit unsigned integer view. */
2573	uint32_t au32[1];
2574	} X86PDE;
2575	#ifndef VBOX_FOR_DTRACE_LIB
2576	AssertCompileSize(X86PDE, 4);
2577	#endif
2578	/** Pointer to a page directory entry. */
2579	typedef X86PDE *PX86PDE;
2580	/** Pointer to a const page directory entry. */
2581	typedef const X86PDE *PCX86PDE;
2582
2583	/**
2584	* PAE page directory entry.
2585	*/
2586	typedef union X86PDEPAE
2587	{
2588	/** Unsigned integer view. */
2589	X86PGPAEUINT u;
2590	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2591	/** Normal view. */
2592	X86PDEPAEBITS n;
2593	/** 2MB page view (big). */
2594	X86PDE2MPAEBITS b;
2595	#endif
2596	/** 8 bit unsigned integer view. */
2597	uint8_t au8[8];
2598	/** 16 bit unsigned integer view. */
2599	uint16_t au16[4];
2600	/** 32 bit unsigned integer view. */
2601	uint32_t au32[2];
2602	} X86PDEPAE;
2603	#ifndef VBOX_FOR_DTRACE_LIB
2604	AssertCompileSize(X86PDEPAE, 8);
2605	#endif
2606	/** Pointer to a page directory entry. */
2607	typedef X86PDEPAE *PX86PDEPAE;
2608	/** Pointer to a const page directory entry. */
2609	typedef const X86PDEPAE *PCX86PDEPAE;
2610
2611	/**
2612	* Page directory.
2613	*/
2614	typedef struct X86PD
2615	{
2616	/** PDE Array. */
2617	X86PDE a[X86_PG_ENTRIES];
2618	} X86PD;
2619	#ifndef VBOX_FOR_DTRACE_LIB
2620	AssertCompileSize(X86PD, 4096);
2621	#endif
2622	/** Pointer to a page directory. */
2623	typedef X86PD *PX86PD;
2624	/** Pointer to a const page directory. */
2625	typedef const X86PD *PCX86PD;
2626
2627	/** The page shift to get the PD index. */
2628	#define X86_PD_SHIFT 22
2629	/** The PD index mask (apply to a shifted page address). */
2630	#define X86_PD_MASK 0x3ff
2631
2632
2633	/**
2634	* PAE page directory.
2635	*/
2636	typedef struct X86PDPAE
2637	{
2638	/** PDE Array. */
2639	X86PDEPAE a[X86_PG_PAE_ENTRIES];
2640	} X86PDPAE;
2641	#ifndef VBOX_FOR_DTRACE_LIB
2642	AssertCompileSize(X86PDPAE, 4096);
2643	#endif
2644	/** Pointer to a PAE page directory. */
2645	typedef X86PDPAE *PX86PDPAE;
2646	/** Pointer to a const PAE page directory. */
2647	typedef const X86PDPAE *PCX86PDPAE;
2648
2649	/** The page shift to get the PAE PD index. */
2650	#define X86_PD_PAE_SHIFT 21
2651	/** The PAE PD index mask (apply to a shifted page address). */
2652	#define X86_PD_PAE_MASK 0x1ff
2653
2654
2655	/** @name Page Directory Pointer Table Entry (PAE)
2656	* @{
2657	*/
2658	/** Bit 0 - P - Present bit. */
2659	#define X86_PDPE_P RT_BIT_32(0)
2660	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2661	#define X86_PDPE_RW RT_BIT_32(1)
2662	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2663	#define X86_PDPE_US RT_BIT_32(2)
2664	/** Bit 3 - PWT - Page level write thru bit. */
2665	#define X86_PDPE_PWT RT_BIT_32(3)
2666	/** Bit 4 - PCD - Page level cache disable bit. */
2667	#define X86_PDPE_PCD RT_BIT_32(4)
2668	/** Bit 5 - A - Access bit. Long Mode only. */
2669	#define X86_PDPE_A RT_BIT_32(5)
2670	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2671	#define X86_PDPE_LM_PS RT_BIT_32(7)
2672	/** Bits 9-11 - - Available for use to system software. */
2673	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2674	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2675	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2676	/** Bits 30-51 - - PG - Physical address of the 1GB page referenced by this entry. */
2677	#define X86_PDPE1G_PG_MASK UINT64_C(0x000fffffc0000000)
2678	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2679	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2680	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2681	#define X86_PDPE_LM_NX RT_BIT_64(63)
2682	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2683	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2684	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2685	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2686	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2687	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2688	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2689	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2690
2691
2692	/**
2693	* Page directory pointer table entry.
2694	*/
2695	typedef struct X86PDPEBITS
2696	{
2697	/** Flags whether(=1) or not the page is present. */
2698	uint32_t u1Present : 1;
2699	/** Chunk of reserved bits. */
2700	uint32_t u2Reserved : 2;
2701	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2702	uint32_t u1WriteThru : 1;
2703	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2704	uint32_t u1CacheDisable : 1;
2705	/** Chunk of reserved bits. */
2706	uint32_t u4Reserved : 4;
2707	/** Available for use to system software. */
2708	uint32_t u3Available : 3;
2709	/** Physical Page number of the next level - Low Part. Don't use! */
2710	uint32_t u20PageNoLow : 20;
2711	/** Physical Page number of the next level - High Part. Don't use! */
2712	uint32_t u20PageNoHigh : 20;
2713	/** MBZ bits */
2714	uint32_t u12Reserved : 12;
2715	} X86PDPEBITS;
2716	#ifndef VBOX_FOR_DTRACE_LIB
2717	AssertCompileSize(X86PDPEBITS, 8);
2718	#endif
2719	/** Pointer to a page directory pointer table entry. */
2720	typedef X86PDPEBITS *PX86PTPEBITS;
2721	/** Pointer to a const page directory pointer table entry. */
2722	typedef const X86PDPEBITS *PCX86PTPEBITS;
2723
2724	/**
2725	* Page directory pointer table entry. AMD64 version
2726	*/
2727	typedef struct X86PDPEAMD64BITS
2728	{
2729	/** Flags whether(=1) or not the page is present. */
2730	uint32_t u1Present : 1;
2731	/** Read(=0) / Write(=1) flag. */
2732	uint32_t u1Write : 1;
2733	/** User(=1) / Supervisor (=0) flag. */
2734	uint32_t u1User : 1;
2735	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2736	uint32_t u1WriteThru : 1;
2737	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2738	uint32_t u1CacheDisable : 1;
2739	/** Accessed flag.
2740	* Indicates that the page have been read or written to. */
2741	uint32_t u1Accessed : 1;
2742	/** Chunk of reserved bits. */
2743	uint32_t u3Reserved : 3;
2744	/** Available for use to system software. */
2745	uint32_t u3Available : 3;
2746	/** Physical Page number of the next level - Low Part. Don't use! */
2747	uint32_t u20PageNoLow : 20;
2748	/** Physical Page number of the next level - High Part. Don't use! */
2749	uint32_t u20PageNoHigh : 20;
2750	/** MBZ bits */
2751	uint32_t u11Reserved : 11;
2752	/** No Execute flag. */
2753	uint32_t u1NoExecute : 1;
2754	} X86PDPEAMD64BITS;
2755	#ifndef VBOX_FOR_DTRACE_LIB
2756	AssertCompileSize(X86PDPEAMD64BITS, 8);
2757	#endif
2758	/** Pointer to a page directory pointer table entry. */
2759	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2760	/** Pointer to a const page directory pointer table entry. */
2761	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2762
2763	/**
2764	* Page directory pointer table entry for 1GB page. (AMD64 only)
2765	*/
2766	typedef struct X86PDPE1GB
2767	{
2768	/** 0: Flags whether(=1) or not the page is present. */
2769	uint32_t u1Present : 1;
2770	/** 1: Read(=0) / Write(=1) flag. */
2771	uint32_t u1Write : 1;
2772	/** 2: User(=1) / Supervisor (=0) flag. */
2773	uint32_t u1User : 1;
2774	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2775	uint32_t u1WriteThru : 1;
2776	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2777	uint32_t u1CacheDisable : 1;
2778	/** 5: Accessed flag.
2779	* Indicates that the page have been read or written to. */
2780	uint32_t u1Accessed : 1;
2781	/** 6: Dirty flag for 1GB pages. */
2782	uint32_t u1Dirty : 1;
2783	/** 7: Indicates 1GB page if set. */
2784	uint32_t u1Size : 1;
2785	/** 8: Global 1GB page. */
2786	uint32_t u1Global: 1;
2787	/** 9-11: Available for use to system software. */
2788	uint32_t u3Available : 3;
2789	/** 12: PAT bit for 1GB page. */
2790	uint32_t u1PAT : 1;
2791	/** 13-29: MBZ bits. */
2792	uint32_t u17Reserved : 17;
2793	/** 30-31: Physical page number - Low Part. Don't use! */
2794	uint32_t u2PageNoLow : 2;
2795	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
2796	uint32_t u20PageNoHigh : 20;
2797	/** 52-62: MBZ bits */
2798	uint32_t u11Reserved : 11;
2799	/** 63: No Execute flag. */
2800	uint32_t u1NoExecute : 1;
2801	} X86PDPE1GB;
2802	#ifndef VBOX_FOR_DTRACE_LIB
2803	AssertCompileSize(X86PDPE1GB, 8);
2804	#endif
2805	/** Pointer to a page directory pointer table entry for a 1GB page. */
2806	typedef X86PDPE1GB *PX86PDPE1GB;
2807	/** Pointer to a const page directory pointer table entry for a 1GB page. */
2808	typedef const X86PDPE1GB *PCX86PDPE1GB;
2809
2810	/**
2811	* Page directory pointer table entry.
2812	*/
2813	typedef union X86PDPE
2814	{
2815	/** Unsigned integer view. */
2816	X86PGPAEUINT u;
2817	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2818	/** Normal view. */
2819	X86PDPEBITS n;
2820	/** AMD64 view. */
2821	X86PDPEAMD64BITS lm;
2822	/** AMD64 big view. */
2823	X86PDPE1GB b;
2824	#endif
2825	/** 8 bit unsigned integer view. */
2826	uint8_t au8[8];
2827	/** 16 bit unsigned integer view. */
2828	uint16_t au16[4];
2829	/** 32 bit unsigned integer view. */
2830	uint32_t au32[2];
2831	} X86PDPE;
2832	#ifndef VBOX_FOR_DTRACE_LIB
2833	AssertCompileSize(X86PDPE, 8);
2834	#endif
2835	/** Pointer to a page directory pointer table entry. */
2836	typedef X86PDPE *PX86PDPE;
2837	/** Pointer to a const page directory pointer table entry. */
2838	typedef const X86PDPE *PCX86PDPE;
2839
2840
2841	/**
2842	* Page directory pointer table.
2843	*/
2844	typedef struct X86PDPT
2845	{
2846	/** PDE Array. */
2847	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2848	} X86PDPT;
2849	#ifndef VBOX_FOR_DTRACE_LIB
2850	AssertCompileSize(X86PDPT, 4096);
2851	#endif
2852	/** Pointer to a page directory pointer table. */
2853	typedef X86PDPT *PX86PDPT;
2854	/** Pointer to a const page directory pointer table. */
2855	typedef const X86PDPT *PCX86PDPT;
2856
2857	/** The page shift to get the PDPT index. */
2858	#define X86_PDPT_SHIFT 30
2859	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2860	#define X86_PDPT_MASK_PAE 0x3
2861	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2862	#define X86_PDPT_MASK_AMD64 0x1ff
2863
2864	/** @} */
2865
2866
2867	/** @name Page Map Level-4 Entry (Long Mode PAE)
2868	* @{
2869	*/
2870	/** Bit 0 - P - Present bit. */
2871	#define X86_PML4E_P RT_BIT_32(0)
2872	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2873	#define X86_PML4E_RW RT_BIT_32(1)
2874	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2875	#define X86_PML4E_US RT_BIT_32(2)
2876	/** Bit 3 - PWT - Page level write thru bit. */
2877	#define X86_PML4E_PWT RT_BIT_32(3)
2878	/** Bit 4 - PCD - Page level cache disable bit. */
2879	#define X86_PML4E_PCD RT_BIT_32(4)
2880	/** Bit 5 - A - Access bit. */
2881	#define X86_PML4E_A RT_BIT_32(5)
2882	/** Bits 9-11 - - Available for use to system software. */
2883	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2884	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2885	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2886	/** Bits 8, 7 - - MBZ bits when NX is active. */
2887	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2888	/** Bits 63, 7 - - MBZ bits when no NX. */
2889	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2890	/** Bits 63 - NX - PAE - No execution flag. */
2891	#define X86_PML4E_NX RT_BIT_64(63)
2892
2893	/**
2894	* Page Map Level-4 Entry
2895	*/
2896	typedef struct X86PML4EBITS
2897	{
2898	/** Flags whether(=1) or not the page is present. */
2899	uint32_t u1Present : 1;
2900	/** Read(=0) / Write(=1) flag. */
2901	uint32_t u1Write : 1;
2902	/** User(=1) / Supervisor (=0) flag. */
2903	uint32_t u1User : 1;
2904	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2905	uint32_t u1WriteThru : 1;
2906	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2907	uint32_t u1CacheDisable : 1;
2908	/** Accessed flag.
2909	* Indicates that the page have been read or written to. */
2910	uint32_t u1Accessed : 1;
2911	/** Chunk of reserved bits. */
2912	uint32_t u3Reserved : 3;
2913	/** Available for use to system software. */
2914	uint32_t u3Available : 3;
2915	/** Physical Page number of the next level - Low Part. Don't use! */
2916	uint32_t u20PageNoLow : 20;
2917	/** Physical Page number of the next level - High Part. Don't use! */
2918	uint32_t u20PageNoHigh : 20;
2919	/** MBZ bits */
2920	uint32_t u11Reserved : 11;
2921	/** No Execute flag. */
2922	uint32_t u1NoExecute : 1;
2923	} X86PML4EBITS;
2924	#ifndef VBOX_FOR_DTRACE_LIB
2925	AssertCompileSize(X86PML4EBITS, 8);
2926	#endif
2927	/** Pointer to a page map level-4 entry. */
2928	typedef X86PML4EBITS *PX86PML4EBITS;
2929	/** Pointer to a const page map level-4 entry. */
2930	typedef const X86PML4EBITS *PCX86PML4EBITS;
2931
2932	/**
2933	* Page Map Level-4 Entry.
2934	*/
2935	typedef union X86PML4E
2936	{
2937	/** Unsigned integer view. */
2938	X86PGPAEUINT u;
2939	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2940	/** Normal view. */
2941	X86PML4EBITS n;
2942	#endif
2943	/** 8 bit unsigned integer view. */
2944	uint8_t au8[8];
2945	/** 16 bit unsigned integer view. */
2946	uint16_t au16[4];
2947	/** 32 bit unsigned integer view. */
2948	uint32_t au32[2];
2949	} X86PML4E;
2950	#ifndef VBOX_FOR_DTRACE_LIB
2951	AssertCompileSize(X86PML4E, 8);
2952	#endif
2953	/** Pointer to a page map level-4 entry. */
2954	typedef X86PML4E *PX86PML4E;
2955	/** Pointer to a const page map level-4 entry. */
2956	typedef const X86PML4E *PCX86PML4E;
2957
2958
2959	/**
2960	* Page Map Level-4.
2961	*/
2962	typedef struct X86PML4
2963	{
2964	/** PDE Array. */
2965	X86PML4E a[X86_PG_PAE_ENTRIES];
2966	} X86PML4;
2967	#ifndef VBOX_FOR_DTRACE_LIB
2968	AssertCompileSize(X86PML4, 4096);
2969	#endif
2970	/** Pointer to a page map level-4. */
2971	typedef X86PML4 *PX86PML4;
2972	/** Pointer to a const page map level-4. */
2973	typedef const X86PML4 *PCX86PML4;
2974
2975	/** The page shift to get the PML4 index. */
2976	#define X86_PML4_SHIFT 39
2977	/** The PML4 index mask (apply to a shifted page address). */
2978	#define X86_PML4_MASK 0x1ff
2979
2980	/** @} */
2981
2982	/** @} */
2983
2984	/**
2985	* Intel PCID invalidation types.
2986	*/
2987	/** Individual address invalidation. */
2988	#define X86_INVPCID_TYPE_INDV_ADDR 0
2989	/** Single-context invalidation. */
2990	#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
2991	/** All-context including globals invalidation. */
2992	#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
2993	/** All-context excluding globals invalidation. */
2994	#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
2995	/** The maximum valid invalidation type value. */
2996	#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
2997
2998
2999	/** @name Special FPU integer values.
3000	* @{ */
3001	#define X86_FPU_INT64_INDEFINITE INT64_MIN
3002	#define X86_FPU_INT32_INDEFINITE INT32_MIN
3003	#define X86_FPU_INT16_INDEFINITE INT16_MIN
3004	/** @} */
3005
3006	/**
3007	* 32-bit protected mode FSTENV image.
3008	*/
3009	typedef struct X86FSTENV32P
3010	{
3011	uint16_t FCW; /*< 0x00 /
3012	uint16_t padding1; /*< 0x02 /
3013	uint16_t FSW; /*< 0x04 /
3014	uint16_t padding2; /*< 0x06 /
3015	uint16_t FTW; /*< 0x08 /
3016	uint16_t padding3; /*< 0x0a /
3017	uint32_t FPUIP; /*< 0x0c /
3018	uint16_t FPUCS; /*< 0x10 /
3019	uint16_t FOP; /*< 0x12 /
3020	uint32_t FPUDP; /*< 0x14 /
3021	uint16_t FPUDS; /*< 0x18 /
3022	uint16_t padding4; /*< 0x1a /
3023	} X86FSTENV32P;
3024	#ifndef VBOX_FOR_DTRACE_LIB
3025	AssertCompileSize(X86FSTENV32P, 0x1c);
3026	#endif
3027	/** Pointer to a 32-bit protected mode FSTENV image. */
3028	typedef X86FSTENV32P *PX86FSTENV32P;
3029	/** Pointer to a const 32-bit protected mode FSTENV image. */
3030	typedef X86FSTENV32P const *PCX86FSTENV32P;
3031
3032
3033	/**
3034	* 80-bit MMX/FPU register type.
3035	*/
3036	typedef struct X86FPUMMX
3037	{
3038	uint8_t reg[10];
3039	} X86FPUMMX;
3040	#ifndef VBOX_FOR_DTRACE_LIB
3041	AssertCompileSize(X86FPUMMX, 10);
3042	#endif
3043	/** Pointer to a 80-bit MMX/FPU register type. */
3044	typedef X86FPUMMX *PX86FPUMMX;
3045	/** Pointer to a const 80-bit MMX/FPU register type. */
3046	typedef const X86FPUMMX *PCX86FPUMMX;
3047
3048	/** FPU (x87) register. */
3049	typedef union X86FPUREG
3050	{
3051	/** MMX view. */
3052	uint64_t mmx;
3053	/** FPU view - todo. */
3054	X86FPUMMX fpu;
3055	/** Extended precision floating point view. */
3056	RTFLOAT80U r80;
3057	/** Extended precision floating point view v2 */
3058	RTFLOAT80U2 r80Ex;
3059	/** 8-bit view. */
3060	uint8_t au8[16];
3061	/** 16-bit view. */
3062	uint16_t au16[8];
3063	/** 32-bit view. */
3064	uint32_t au32[4];
3065	/** 64-bit view. */
3066	uint64_t au64[2];
3067	/** 128-bit view. (yeah, very helpful) */
3068	uint128_t au128[1];
3069	} X86FPUREG;
3070	#ifndef VBOX_FOR_DTRACE_LIB
3071	AssertCompileSize(X86FPUREG, 16);
3072	#endif
3073	/** Pointer to a FPU register. */
3074	typedef X86FPUREG *PX86FPUREG;
3075	/** Pointer to a const FPU register. */
3076	typedef X86FPUREG const *PCX86FPUREG;
3077
3078	/**
3079	* XMM register union.
3080	*/
3081	typedef union X86XMMREG
3082	{
3083	/** XMM Register view. */
3084	uint128_t xmm;
3085	/** 8-bit view. */
3086	uint8_t au8[16];
3087	/** 16-bit view. */
3088	uint16_t au16[8];
3089	/** 32-bit view. */
3090	uint32_t au32[4];
3091	/** 64-bit view. */
3092	uint64_t au64[2];
3093	/** 128-bit view. (yeah, very helpful) */
3094	uint128_t au128[1];
3095	/** Single precision floating point view. */
3096	RTFLOAT32U ar32[4];
3097	/** Double precision floating point view. */
3098	RTFLOAT64U ar64[2];
3099	#ifndef VBOX_FOR_DTRACE_LIB
3100	/** Confusing nested 128-bit union view (this is what xmm should've been). */
3101	RTUINT128U uXmm;
3102	#endif
3103	} X86XMMREG;
3104	#ifndef VBOX_FOR_DTRACE_LIB
3105	AssertCompileSize(X86XMMREG, 16);
3106	#endif
3107	/** Pointer to an XMM register state. */
3108	typedef X86XMMREG *PX86XMMREG;
3109	/** Pointer to a const XMM register state. */
3110	typedef X86XMMREG const *PCX86XMMREG;
3111
3112	/**
3113	* YMM register union.
3114	*/
3115	typedef union X86YMMREG
3116	{
3117	/** YMM register view. */
3118	RTUINT256U ymm;
3119	/** 8-bit view. */
3120	uint8_t au8[32];
3121	/** 16-bit view. */
3122	uint16_t au16[16];
3123	/** 32-bit view. */
3124	uint32_t au32[8];
3125	/** 64-bit view. */
3126	uint64_t au64[4];
3127	/** 128-bit view. (yeah, very helpful) */
3128	uint128_t au128[2];
3129	/** Single precision floating point view. */
3130	RTFLOAT32U ar32[8];
3131	/** Double precision floating point view. */
3132	RTFLOAT64U ar64[4];
3133	/** XMM sub register view. */
3134	X86XMMREG aXmm[2];
3135	} X86YMMREG;
3136	#ifndef VBOX_FOR_DTRACE_LIB
3137	AssertCompileSize(X86YMMREG, 32);
3138	#endif
3139	/** Pointer to an YMM register state. */
3140	typedef X86YMMREG *PX86YMMREG;
3141	/** Pointer to a const YMM register state. */
3142	typedef X86YMMREG const *PCX86YMMREG;
3143
3144	/**
3145	* ZMM register union.
3146	*/
3147	typedef union X86ZMMREG
3148	{
3149	/** 8-bit view. */
3150	uint8_t au8[64];
3151	/** 16-bit view. */
3152	uint16_t au16[32];
3153	/** 32-bit view. */
3154	uint32_t au32[16];
3155	/** 64-bit view. */
3156	uint64_t au64[8];
3157	/** 128-bit view. (yeah, very helpful) */
3158	uint128_t au128[4];
3159	/** Single precision floating point view. */
3160	RTFLOAT32U ar32[16];
3161	/** Double precision floating point view. */
3162	RTFLOAT64U ar64[8];
3163	/** XMM sub register view. */
3164	X86XMMREG aXmm[4];
3165	/** YMM sub register view. */
3166	X86YMMREG aYmm[2];
3167	} X86ZMMREG;
3168	#ifndef VBOX_FOR_DTRACE_LIB
3169	AssertCompileSize(X86ZMMREG, 64);
3170	#endif
3171	/** Pointer to an ZMM register state. */
3172	typedef X86ZMMREG *PX86ZMMREG;
3173	/** Pointer to a const ZMM register state. */
3174	typedef X86ZMMREG const *PCX86ZMMREG;
3175
3176
3177	/**
3178	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3179	* @todo verify this...
3180	*/
3181	#pragma pack(1)
3182	typedef struct X86FPUSTATE
3183	{
3184	/** 0x00 - Control word. */
3185	uint16_t FCW;
3186	/** 0x02 - Alignment word */
3187	uint16_t Dummy1;
3188	/** 0x04 - Status word. */
3189	uint16_t FSW;
3190	/** 0x06 - Alignment word */
3191	uint16_t Dummy2;
3192	/** 0x08 - Tag word */
3193	uint16_t FTW;
3194	/** 0x0a - Alignment word */
3195	uint16_t Dummy3;
3196
3197	/** 0x0c - Instruction pointer. */
3198	uint32_t FPUIP;
3199	/** 0x10 - Code selector. */
3200	uint16_t CS;
3201	/** 0x12 - Opcode. */
3202	uint16_t FOP;
3203	/** 0x14 - FOO. */
3204	uint32_t FPUOO;
3205	/** 0x18 - FOS. */
3206	uint32_t FPUOS;
3207	/** 0x1c - FPU register. */
3208	X86FPUREG regs[8];
3209	} X86FPUSTATE;
3210	#pragma pack()
3211	/** Pointer to a FPU state. */
3212	typedef X86FPUSTATE *PX86FPUSTATE;
3213	/** Pointer to a const FPU state. */
3214	typedef const X86FPUSTATE *PCX86FPUSTATE;
3215
3216	/**
3217	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3218	*/
3219	#pragma pack(1)
3220	typedef struct X86FXSTATE
3221	{
3222	/** 0x00 - Control word. */
3223	uint16_t FCW;
3224	/** 0x02 - Status word. */
3225	uint16_t FSW;
3226	/** 0x04 - Tag word. (The upper byte is always zero.) */
3227	uint16_t FTW;
3228	/** 0x06 - Opcode. */
3229	uint16_t FOP;
3230	/** 0x08 - Instruction pointer. */
3231	uint32_t FPUIP;
3232	/** 0x0c - Code selector. */
3233	uint16_t CS;
3234	uint16_t Rsrvd1;
3235	/** 0x10 - Data pointer. */
3236	uint32_t FPUDP;
3237	/** 0x14 - Data segment */
3238	uint16_t DS;
3239	/** 0x16 */
3240	uint16_t Rsrvd2;
3241	/** 0x18 */
3242	uint32_t MXCSR;
3243	/** 0x1c */
3244	uint32_t MXCSR_MASK;
3245	/** 0x20 - FPU registers. */
3246	X86FPUREG aRegs[8];
3247	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3248	X86XMMREG aXMM[16];
3249	/* - offset 416 - */
3250	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3251	/* - offset 464 - Software usable reserved bits. */
3252	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3253	} X86FXSTATE;
3254	#pragma pack()
3255	/** Pointer to a FPU Extended state. */
3256	typedef X86FXSTATE *PX86FXSTATE;
3257	/** Pointer to a const FPU Extended state. */
3258	typedef const X86FXSTATE *PCX86FXSTATE;
3259
3260	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3261	* magic. Don't forget to update x86.mac if you change this! */
3262	#define X86_OFF_FXSTATE_RSVD 0x1d0
3263	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3264	* forget to update x86.mac if you change this!
3265	* @todo r=bird: This has nothing what-so-ever to do here.... */
3266	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3267	#ifndef VBOX_FOR_DTRACE_LIB
3268	AssertCompileSize(X86FXSTATE, 512);
3269	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3270	#endif
3271
3272	/** @name FPU status word flags.
3273	* @{ */
3274	/** Exception Flag: Invalid operation. */
3275	#define X86_FSW_IE RT_BIT_32(0)
3276	#define X86_FSW_IE_BIT 0
3277	/** Exception Flag: Denormalized operand. */
3278	#define X86_FSW_DE RT_BIT_32(1)
3279	#define X86_FSW_DE_BIT 1
3280	/** Exception Flag: Zero divide. */
3281	#define X86_FSW_ZE RT_BIT_32(2)
3282	#define X86_FSW_ZE_BIT 2
3283	/** Exception Flag: Overflow. */
3284	#define X86_FSW_OE RT_BIT_32(3)
3285	#define X86_FSW_OE_BIT 3
3286	/** Exception Flag: Underflow. */
3287	#define X86_FSW_UE RT_BIT_32(4)
3288	#define X86_FSW_UE_BIT 4
3289	/** Exception Flag: Precision. */
3290	#define X86_FSW_PE RT_BIT_32(5)
3291	#define X86_FSW_PE_BIT 5
3292	/** Stack fault. */
3293	#define X86_FSW_SF RT_BIT_32(6)
3294	#define X86_FSW_SF_BIT 6
3295	/** Error summary status. */
3296	#define X86_FSW_ES RT_BIT_32(7)
3297	#define X86_FSW_ES_BIT 7
3298	/** Mask of exceptions flags, excluding the summary bit. */
3299	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3300	/** Mask of exceptions flags, including the summary bit. */
3301	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3302	/** Condition code 0. */
3303	#define X86_FSW_C0 RT_BIT_32(X86_FSW_C0_BIT)
3304	#define X86_FSW_C0_BIT 8
3305	/** Condition code 1. */
3306	#define X86_FSW_C1 RT_BIT_32(X86_FSW_C1_BIT)
3307	#define X86_FSW_C1_BIT 9
3308	/** Condition code 2. */
3309	#define X86_FSW_C2 RT_BIT_32(X86_FSW_C2_BIT)
3310	#define X86_FSW_C2_BIT 10
3311	/** Top of the stack mask. */
3312	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3313	/** TOP shift value. */
3314	#define X86_FSW_TOP_SHIFT 11
3315	/** Mask for getting TOP value after shifting it right. */
3316	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3317	/** Get the TOP value. */
3318	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3319	/** Get the TOP value offsetted by a_iSt (0-7). */
3320	#define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK)
3321	/** Condition code 3. */
3322	#define X86_FSW_C3 RT_BIT_32(X86_FSW_C3_BIT)
3323	#define X86_FSW_C3_BIT 14
3324	/** Mask of exceptions flags, including the summary bit. */
3325	#define X86_FSW_C_MASK UINT16_C(0x4700)
3326	/** FPU busy. */
3327	#define X86_FSW_B RT_BIT_32(15)
3328	/** For use with FPREM and FPREM1. */
3329	#define X86_FSW_CX_TO_QUOTIENT(a_fFsw) \
3330	( (((a_fFsw) & X86_FSW_C1) >> (X86_FSW_C1_BIT - 0)) \
3331	\| (((a_fFsw) & X86_FSW_C3) >> (X86_FSW_C3_BIT - 1)) \
3332	\| (((a_fFsw) & X86_FSW_C0) >> (X86_FSW_C0_BIT - 2)) )
3333	/** For use with FPREM and FPREM1. */
3334	#define X86_FSW_CX_FROM_QUOTIENT(a_uQuotient) \
3335	( ((uint16_t)((a_uQuotient) & 1) << (X86_FSW_C1_BIT - 0)) \
3336	\| ((uint16_t)((a_uQuotient) & 2) << (X86_FSW_C3_BIT - 1)) \
3337	\| ((uint16_t)((a_uQuotient) & 4) << (X86_FSW_C0_BIT - 2)) )
3338	/** @} */
3339
3340
3341	/** @name FPU control word flags.
3342	* @{ */
3343	/** Exception Mask: Invalid operation. */
3344	#define X86_FCW_IM RT_BIT_32(0)
3345	#define X86_FCW_IM_BIT 0
3346	/** Exception Mask: Denormalized operand. */
3347	#define X86_FCW_DM RT_BIT_32(1)
3348	#define X86_FCW_DM_BIT 1
3349	/** Exception Mask: Zero divide. */
3350	#define X86_FCW_ZM RT_BIT_32(2)
3351	#define X86_FCW_ZM_BIT 2
3352	/** Exception Mask: Overflow. */
3353	#define X86_FCW_OM RT_BIT_32(3)
3354	#define X86_FCW_OM_BIT 3
3355	/** Exception Mask: Underflow. */
3356	#define X86_FCW_UM RT_BIT_32(4)
3357	#define X86_FCW_UM_BIT 4
3358	/** Exception Mask: Precision. */
3359	#define X86_FCW_PM RT_BIT_32(5)
3360	#define X86_FCW_PM_BIT 5
3361	/** Mask all exceptions, the value typically loaded (by for instance fninit).
3362	* @remarks This includes reserved bit 6. */
3363	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3364	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3365	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3366	/** Precision control mask. */
3367	#define X86_FCW_PC_MASK UINT16_C(0x0300)
3368	/** Precision control shift. */
3369	#define X86_FCW_PC_SHIFT 8
3370	/** Precision control: 24-bit. */
3371	#define X86_FCW_PC_24 UINT16_C(0x0000)
3372	/** Precision control: Reserved. */
3373	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3374	/** Precision control: 53-bit. */
3375	#define X86_FCW_PC_53 UINT16_C(0x0200)
3376	/** Precision control: 64-bit. */
3377	#define X86_FCW_PC_64 UINT16_C(0x0300)
3378	/** Rounding control mask. */
3379	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3380	/** Rounding control shift. */
3381	#define X86_FCW_RC_SHIFT 10
3382	/** Rounding control: To nearest. */
3383	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3384	/** Rounding control: Down. */
3385	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3386	/** Rounding control: Up. */
3387	#define X86_FCW_RC_UP UINT16_C(0x0800)
3388	/** Rounding control: Towards zero. */
3389	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3390	/** Infinity control mask - obsolete, 8087 & 287 only. */
3391	#define X86_FCW_IC_MASK UINT16_C(0x1000)
3392	/** Infinity control: Affine - positive infinity is distictly different from
3393	* negative infinity.
3394	* @note 8087, 287 only */
3395	#define X86_FCW_IC_AFFINE UINT16_C(0x1000)
3396	/** Infinity control: Projective - positive and negative infinity are the
3397	* same (sign ignored).
3398	* @note 8087, 287 only */
3399	#define X86_FCW_IC_PROJECTIVE UINT16_C(0x0000)
3400	/** Bits which should be zero, apparently. */
3401	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3402	/** @} */
3403
3404	/** @name SSE MXCSR
3405	* @{ */
3406	/** Exception Flag: Invalid operation. */
3407	#define X86_MXCSR_IE RT_BIT_32(0)
3408	/** Exception Flag: Denormalized operand. */
3409	#define X86_MXCSR_DE RT_BIT_32(1)
3410	/** Exception Flag: Zero divide. */
3411	#define X86_MXCSR_ZE RT_BIT_32(2)
3412	/** Exception Flag: Overflow. */
3413	#define X86_MXCSR_OE RT_BIT_32(3)
3414	/** Exception Flag: Underflow. */
3415	#define X86_MXCSR_UE RT_BIT_32(4)
3416	/** Exception Flag: Precision. */
3417	#define X86_MXCSR_PE RT_BIT_32(5)
3418	/** Exception Flags: mask */
3419	#define X86_MXCSR_XCPT_FLAGS UINT32_C(0x003f)
3420
3421	/** Denormals are zero. */
3422	#define X86_MXCSR_DAZ RT_BIT_32(6)
3423
3424	/** Exception Mask: Invalid operation. */
3425	#define X86_MXCSR_IM RT_BIT_32(7)
3426	/** Exception Mask: Denormalized operand. */
3427	#define X86_MXCSR_DM RT_BIT_32(8)
3428	/** Exception Mask: Zero divide. */
3429	#define X86_MXCSR_ZM RT_BIT_32(9)
3430	/** Exception Mask: Overflow. */
3431	#define X86_MXCSR_OM RT_BIT_32(10)
3432	/** Exception Mask: Underflow. */
3433	#define X86_MXCSR_UM RT_BIT_32(11)
3434	/** Exception Mask: Precision. */
3435	#define X86_MXCSR_PM RT_BIT_32(12)
3436	/** Exception Mask: mask. */
3437	#define X86_MXCSR_XCPT_MASK UINT32_C(0x1f80)
3438	/** Exception Mask: shift. */
3439	#define X86_MXCSR_XCPT_MASK_SHIFT 7
3440
3441	/** Rounding control mask. */
3442	#define X86_MXCSR_RC_MASK UINT32_C(0x6000)
3443	/** Rounding control shift. */
3444	#define X86_MXCSR_RC_SHIFT 13
3445	/** Rounding control: To nearest. */
3446	#define X86_MXCSR_RC_NEAREST UINT32_C(0x0000)
3447	/** Rounding control: Down. */
3448	#define X86_MXCSR_RC_DOWN UINT32_C(0x2000)
3449	/** Rounding control: Up. */
3450	#define X86_MXCSR_RC_UP UINT32_C(0x4000)
3451	/** Rounding control: Towards zero. */
3452	#define X86_MXCSR_RC_ZERO UINT32_C(0x6000)
3453
3454	/** Flush-to-zero for masked underflow. */
3455	#define X86_MXCSR_FZ RT_BIT_32(15)
3456
3457	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3458	#define X86_MXCSR_MM RT_BIT_32(17)
3459	/** Bits which should be zero, apparently. */
3460	#define X86_MXCSR_ZERO_MASK UINT32_C(0xfffd0000)
3461	/** @} */
3462
3463	/**
3464	* XSAVE header.
3465	*/
3466	typedef struct X86XSAVEHDR
3467	{
3468	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
3469	uint64_t bmXState;
3470	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3471	uint64_t bmXComp;
3472	/** Reserved for furture extensions, probably MBZ. */
3473	uint64_t au64Reserved[6];
3474	} X86XSAVEHDR;
3475	#ifndef VBOX_FOR_DTRACE_LIB
3476	AssertCompileSize(X86XSAVEHDR, 64);
3477	#endif
3478	/** Pointer to an XSAVE header. */
3479	typedef X86XSAVEHDR *PX86XSAVEHDR;
3480	/** Pointer to a const XSAVE header. */
3481	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3482
3483
3484	/**
3485	* The high 128-bit YMM register state (XSAVE_C_YMM).
3486	* (The lower 128-bits being in X86FXSTATE.)
3487	*/
3488	typedef struct X86XSAVEYMMHI
3489	{
3490	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3491	X86XMMREG aYmmHi[16];
3492	} X86XSAVEYMMHI;
3493	#ifndef VBOX_FOR_DTRACE_LIB
3494	AssertCompileSize(X86XSAVEYMMHI, 256);
3495	#endif
3496	/** Pointer to a high 128-bit YMM register state. */
3497	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3498	/** Pointer to a const high 128-bit YMM register state. */
3499	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3500
3501	/**
3502	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
3503	*/
3504	typedef struct X86XSAVEBNDREGS
3505	{
3506	/** Array of registers (BND0...BND3). */
3507	struct
3508	{
3509	/** Lower bound. */
3510	uint64_t uLowerBound;
3511	/** Upper bound. */
3512	uint64_t uUpperBound;
3513	} aRegs[4];
3514	} X86XSAVEBNDREGS;
3515	#ifndef VBOX_FOR_DTRACE_LIB
3516	AssertCompileSize(X86XSAVEBNDREGS, 64);
3517	#endif
3518	/** Pointer to a MPX bound register state. */
3519	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3520	/** Pointer to a const MPX bound register state. */
3521	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3522
3523	/**
3524	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3525	*/
3526	typedef struct X86XSAVEBNDCFG
3527	{
3528	uint64_t fConfig;
3529	uint64_t fStatus;
3530	} X86XSAVEBNDCFG;
3531	#ifndef VBOX_FOR_DTRACE_LIB
3532	AssertCompileSize(X86XSAVEBNDCFG, 16);
3533	#endif
3534	/** Pointer to a MPX bound config and status register state. */
3535	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3536	/** Pointer to a const MPX bound config and status register state. */
3537	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3538
3539	/**
3540	* AVX-512 opmask state (XSAVE_C_OPMASK).
3541	*/
3542	typedef struct X86XSAVEOPMASK
3543	{
3544	/** The K0..K7 values. */
3545	uint64_t aKRegs[8];
3546	} X86XSAVEOPMASK;
3547	#ifndef VBOX_FOR_DTRACE_LIB
3548	AssertCompileSize(X86XSAVEOPMASK, 64);
3549	#endif
3550	/** Pointer to a AVX-512 opmask state. */
3551	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3552	/** Pointer to a const AVX-512 opmask state. */
3553	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3554
3555	/**
3556	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3557	*/
3558	typedef struct X86XSAVEZMMHI256
3559	{
3560	/** Upper 256-bits of ZMM0-15. */
3561	X86YMMREG aHi256Regs[16];
3562	} X86XSAVEZMMHI256;
3563	#ifndef VBOX_FOR_DTRACE_LIB
3564	AssertCompileSize(X86XSAVEZMMHI256, 512);
3565	#endif
3566	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3567	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3568	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3569	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3570
3571	/**
3572	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3573	*/
3574	typedef struct X86XSAVEZMM16HI
3575	{
3576	/** ZMM16 thru ZMM31. */
3577	X86ZMMREG aRegs[16];
3578	} X86XSAVEZMM16HI;
3579	#ifndef VBOX_FOR_DTRACE_LIB
3580	AssertCompileSize(X86XSAVEZMM16HI, 1024);
3581	#endif
3582	/** Pointer to a state comprising ZMM16-32. */
3583	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3584	/** Pointer to a const state comprising ZMM16-32. */
3585	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3586
3587	/**
3588	* AMD Light weight profiling state (XSAVE_C_LWP).
3589	*
3590	* We probably won't play with this as AMD seems to be dropping from their "zen"
3591	* processor micro architecture.
3592	*/
3593	typedef struct X86XSAVELWP
3594	{
3595	/** Details when needed. */
3596	uint64_t auLater[128/8];
3597	} X86XSAVELWP;
3598	#ifndef VBOX_FOR_DTRACE_LIB
3599	AssertCompileSize(X86XSAVELWP, 128);
3600	#endif
3601
3602
3603	/**
3604	* x86 FPU/SSE/AVX/XXXX state.
3605	*
3606	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3607	* changes to this structure.
3608	*/
3609	typedef struct X86XSAVEAREA
3610	{
3611	/** The x87 and SSE region (or legacy region if you like). */
3612	X86FXSTATE x87;
3613	/** The XSAVE header. */
3614	X86XSAVEHDR Hdr;
3615	/** Beyond the header, there isn't really a fixed layout, but we can
3616	generally assume the YMM (AVX) register extensions are present and
3617	follows immediately. */
3618	union
3619	{
3620	/** The high 128-bit AVX registers for easy access by IEM.
3621	* @note This ASSUMES they will always be here... */
3622	X86XSAVEYMMHI YmmHi;
3623
3624	/** This is a typical layout on intel CPUs (good for debuggers). */
3625	struct
3626	{
3627	X86XSAVEYMMHI YmmHi;
3628	X86XSAVEBNDREGS BndRegs;
3629	X86XSAVEBNDCFG BndCfg;
3630	uint8_t abFudgeToMatchDocs[0xB0];
3631	X86XSAVEOPMASK Opmask;
3632	X86XSAVEZMMHI256 ZmmHi256;
3633	X86XSAVEZMM16HI Zmm16Hi;
3634	} Intel;
3635
3636	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3637	struct
3638	{
3639	X86XSAVEYMMHI YmmHi;
3640	X86XSAVELWP Lwp;
3641	} AmdBd;
3642
3643	/** To enbling static deployments that have a reasonable chance of working for
3644	* the next 3-6 CPU generations without running short on space, we allocate a
3645	* lot of extra space here, making the structure a round 8KB in size. This
3646	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3647	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3648	uint8_t ab[8192 - 512 - 64];
3649	} u;
3650	} X86XSAVEAREA;
3651	#ifndef VBOX_FOR_DTRACE_LIB
3652	AssertCompileSize(X86XSAVEAREA, 8192);
3653	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
3654	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3655	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3656	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3657	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3658	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3659	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3660	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3661	#endif
3662	/** Pointer to a XSAVE area. */
3663	typedef X86XSAVEAREA *PX86XSAVEAREA;
3664	/** Pointer to a const XSAVE area. */
3665	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3666
3667
3668	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3669	* @{ */
3670	/** Bit 0 - x87 - Legacy FPU state (bit number) */
3671	#define XSAVE_C_X87_BIT 0
3672	/** Bit 0 - x87 - Legacy FPU state. */
3673	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3674	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3675	#define XSAVE_C_SSE_BIT 1
3676	/** Bit 1 - SSE - 128-bit SSE state. */
3677	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3678	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3679	#define XSAVE_C_YMM_BIT 2
3680	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3681	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3682	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3683	#define XSAVE_C_BNDREGS_BIT 3
3684	/** Bit 3 - BNDREGS - MPX bound register state. */
3685	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3686	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3687	#define XSAVE_C_BNDCSR_BIT 4
3688	/** Bit 4 - BNDCSR - MPX bound config and status state. */
3689	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3690	/** Bit 5 - Opmask - opmask state (bit number). */
3691	#define XSAVE_C_OPMASK_BIT 5
3692	/** Bit 5 - Opmask - opmask state. */
3693	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3694	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3695	#define XSAVE_C_ZMM_HI256_BIT 6
3696	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3697	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3698	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3699	#define XSAVE_C_ZMM_16HI_BIT 7
3700	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3701	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3702	/** Bit 9 - PKRU - Protection-key state (bit number). */
3703	#define XSAVE_C_PKRU_BIT 9
3704	/** Bit 9 - PKRU - Protection-key state. */
3705	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3706	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3707	#define XSAVE_C_LWP_BIT 62
3708	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3709	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3710	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3711	#define XSAVE_C_X_BIT 63
3712	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3713	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3714	/** @} */
3715
3716
3717
3718	/** @name Selector Descriptor
3719	* @{
3720	*/
3721
3722	#ifndef VBOX_FOR_DTRACE_LIB
3723	/**
3724	* Descriptor attributes (as seen by VT-x).
3725	*/
3726	typedef struct X86DESCATTRBITS
3727	{
3728	/** 00 - Segment Type. */
3729	unsigned u4Type : 4;
3730	/** 04 - Descriptor Type. System(=0) or code/data selector */
3731	unsigned u1DescType : 1;
3732	/** 05 - Descriptor Privilege level. */
3733	unsigned u2Dpl : 2;
3734	/** 07 - Flags selector present(=1) or not. */
3735	unsigned u1Present : 1;
3736	/** 08 - Segment limit 16-19. */
3737	unsigned u4LimitHigh : 4;
3738	/** 0c - Available for system software. */
3739	unsigned u1Available : 1;
3740	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3741	unsigned u1Long : 1;
3742	/** 0e - This flags meaning depends on the segment type. Try make sense out
3743	* of the intel manual yourself. */
3744	unsigned u1DefBig : 1;
3745	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
3746	* clear byte. */
3747	unsigned u1Granularity : 1;
3748	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3749	unsigned u1Unusable : 1;
3750	} X86DESCATTRBITS;
3751	#endif /* !VBOX_FOR_DTRACE_LIB */
3752
3753	/** @name X86DESCATTR masks
3754	* @{ */
3755	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3756	#define X86DESCATTR_DT UINT32_C(0x00000010)
3757	#define X86DESCATTR_DPL UINT32_C(0x00000060)
3758	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
3759	#define X86DESCATTR_P UINT32_C(0x00000080)
3760	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3761	#define X86DESCATTR_AVL UINT32_C(0x00001000)
3762	#define X86DESCATTR_L UINT32_C(0x00002000)
3763	#define X86DESCATTR_D UINT32_C(0x00004000)
3764	#define X86DESCATTR_G UINT32_C(0x00008000)
3765	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3766	/** @} */
3767
3768	#pragma pack(1)
3769	typedef union X86DESCATTR
3770	{
3771	/** Unsigned integer view. */
3772	uint32_t u;
3773	#ifndef VBOX_FOR_DTRACE_LIB
3774	/** Normal view. */
3775	X86DESCATTRBITS n;
3776	#endif
3777	} X86DESCATTR;
3778	#pragma pack()
3779	/** Pointer to descriptor attributes. */
3780	typedef X86DESCATTR *PX86DESCATTR;
3781	/** Pointer to const descriptor attributes. */
3782	typedef const X86DESCATTR *PCX86DESCATTR;
3783
3784	#ifndef VBOX_FOR_DTRACE_LIB
3785
3786	/**
3787	* Generic descriptor table entry
3788	*/
3789	#pragma pack(1)
3790	typedef struct X86DESCGENERIC
3791	{
3792	/** 00 - Limit - Low word. */
3793	unsigned u16LimitLow : 16;
3794	/** 10 - Base address - low word.
3795	* Don't try set this to 24 because MSC is doing stupid things then. */
3796	unsigned u16BaseLow : 16;
3797	/** 20 - Base address - first 8 bits of high word. */
3798	unsigned u8BaseHigh1 : 8;
3799	/** 28 - Segment Type. */
3800	unsigned u4Type : 4;
3801	/** 2c - Descriptor Type. System(=0) or code/data selector */
3802	unsigned u1DescType : 1;
3803	/** 2d - Descriptor Privilege level. */
3804	unsigned u2Dpl : 2;
3805	/** 2f - Flags selector present(=1) or not. */
3806	unsigned u1Present : 1;
3807	/** 30 - Segment limit 16-19. */
3808	unsigned u4LimitHigh : 4;
3809	/** 34 - Available for system software. */
3810	unsigned u1Available : 1;
3811	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3812	unsigned u1Long : 1;
3813	/** 36 - This flags meaning depends on the segment type. Try make sense out
3814	* of the intel manual yourself. */
3815	unsigned u1DefBig : 1;
3816	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
3817	* clear byte. */
3818	unsigned u1Granularity : 1;
3819	/** 38 - Base address - highest 8 bits. */
3820	unsigned u8BaseHigh2 : 8;
3821	} X86DESCGENERIC;
3822	#pragma pack()
3823	/** Pointer to a generic descriptor entry. */
3824	typedef X86DESCGENERIC *PX86DESCGENERIC;
3825	/** Pointer to a const generic descriptor entry. */
3826	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3827
3828	/** @name Bit offsets of X86DESCGENERIC members.
3829	* @{*/
3830	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
3831	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
3832	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
3833	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
3834	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
3835	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
3836	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
3837	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
3838	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
3839	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
3840	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
3841	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
3842	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
3843	/** @} */
3844
3845
3846	/** @name LAR mask
3847	* @{ */
3848	#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3849	#define X86LAR_F_DT UINT16_C( 0x1000)
3850	#define X86LAR_F_DPL UINT16_C( 0x6000)
3851	#define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
3852	#define X86LAR_F_P UINT16_C( 0x8000)
3853	#define X86LAR_F_AVL UINT32_C(0x00100000)
3854	#define X86LAR_F_L UINT32_C(0x00200000)
3855	#define X86LAR_F_D UINT32_C(0x00400000)
3856	#define X86LAR_F_G UINT32_C(0x00800000)
3857	/** @} */
3858
3859
3860	/**
3861	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3862	*/
3863	typedef struct X86DESCGATE
3864	{
3865	/** 00 - Target code segment offset - Low word.
3866	* Ignored if task-gate. */
3867	unsigned u16OffsetLow : 16;
3868	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3869	* TSS selector if task-gate. */
3870	unsigned u16Sel : 16;
3871	/** 20 - Number of parameters for a call-gate.
3872	* Ignored if interrupt-, trap- or task-gate. */
3873	unsigned u5ParmCount : 5;
3874	/** 25 - Reserved / ignored. */
3875	unsigned u3Reserved : 3;
3876	/** 28 - Segment Type. */
3877	unsigned u4Type : 4;
3878	/** 2c - Descriptor Type (0 = system). */
3879	unsigned u1DescType : 1;
3880	/** 2d - Descriptor Privilege level. */
3881	unsigned u2Dpl : 2;
3882	/** 2f - Flags selector present(=1) or not. */
3883	unsigned u1Present : 1;
3884	/** 30 - Target code segment offset - High word.
3885	* Ignored if task-gate. */
3886	unsigned u16OffsetHigh : 16;
3887	} X86DESCGATE;
3888	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3889	typedef X86DESCGATE *PX86DESCGATE;
3890	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3891	typedef const X86DESCGATE *PCX86DESCGATE;
3892
3893	#endif /* VBOX_FOR_DTRACE_LIB */
3894
3895	/**
3896	* Descriptor table entry.
3897	*/
3898	#pragma pack(1)
3899	typedef union X86DESC
3900	{
3901	#ifndef VBOX_FOR_DTRACE_LIB
3902	/** Generic descriptor view. */
3903	X86DESCGENERIC Gen;
3904	/** Gate descriptor view. */
3905	X86DESCGATE Gate;
3906	#endif
3907
3908	/** 8 bit unsigned integer view. */
3909	uint8_t au8[8];
3910	/** 16 bit unsigned integer view. */
3911	uint16_t au16[4];
3912	/** 32 bit unsigned integer view. */
3913	uint32_t au32[2];
3914	/** 64 bit unsigned integer view. */
3915	uint64_t au64[1];
3916	/** Unsigned integer view. */
3917	uint64_t u;
3918	} X86DESC;
3919	#ifndef VBOX_FOR_DTRACE_LIB
3920	AssertCompileSize(X86DESC, 8);
3921	#endif
3922	#pragma pack()
3923	/** Pointer to descriptor table entry. */
3924	typedef X86DESC *PX86DESC;
3925	/** Pointer to const descriptor table entry. */
3926	typedef const X86DESC *PCX86DESC;
3927
3928	/** @def X86DESC_BASE
3929	* Return the base address of a descriptor.
3930	*/
3931	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
3932	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
3933	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
3934	\| ( (a_pDesc)->Gen.u16BaseLow ) )
3935
3936	/** @def X86DESC_LIMIT
3937	* Return the limit of a descriptor.
3938	*/
3939	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
3940	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
3941	\| ( (a_pDesc)->Gen.u16LimitLow ) )
3942
3943	/** @def X86DESC_LIMIT_G
3944	* Return the limit of a descriptor with the granularity bit taken into account.
3945	* @returns Selector limit (uint32_t).
3946	* @param a_pDesc Pointer to the descriptor.
3947	*/
3948	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
3949	( (a_pDesc)->Gen.u1Granularity \
3950	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
3951	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
3952	)
3953
3954	/** @def X86DESC_GET_HID_ATTR
3955	* Get the descriptor attributes for the hidden register.
3956	*/
3957	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
3958	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
3959
3960	#ifndef VBOX_FOR_DTRACE_LIB
3961
3962	/**
3963	* 64 bits generic descriptor table entry
3964	* Note: most of these bits have no meaning in long mode.
3965	*/
3966	#pragma pack(1)
3967	typedef struct X86DESC64GENERIC
3968	{
3969	/** Limit - Low word - IGNORED. */
3970	uint32_t u16LimitLow : 16;
3971	/** Base address - low word. - IGNORED
3972	* Don't try set this to 24 because MSC is doing stupid things then. */
3973	uint32_t u16BaseLow : 16;
3974	/** Base address - first 8 bits of high word. - IGNORED */
3975	uint32_t u8BaseHigh1 : 8;
3976	/** Segment Type. */
3977	uint32_t u4Type : 4;
3978	/** Descriptor Type. System(=0) or code/data selector */
3979	uint32_t u1DescType : 1;
3980	/** Descriptor Privilege level. */
3981	uint32_t u2Dpl : 2;
3982	/** Flags selector present(=1) or not. */
3983	uint32_t u1Present : 1;
3984	/** Segment limit 16-19. - IGNORED */
3985	uint32_t u4LimitHigh : 4;
3986	/** Available for system software. - IGNORED */
3987	uint32_t u1Available : 1;
3988	/** Long mode flag. */
3989	uint32_t u1Long : 1;
3990	/** This flags meaning depends on the segment type. Try make sense out
3991	* of the intel manual yourself. */
3992	uint32_t u1DefBig : 1;
3993	/** Granularity of the limit. If set 4KB granularity is used, if
3994	* clear byte. - IGNORED */
3995	uint32_t u1Granularity : 1;
3996	/** Base address - highest 8 bits. - IGNORED */
3997	uint32_t u8BaseHigh2 : 8;
3998	/** Base address - bits 63-32. */
3999	uint32_t u32BaseHigh3 : 32;
4000	uint32_t u8Reserved : 8;
4001	uint32_t u5Zeros : 5;
4002	uint32_t u19Reserved : 19;
4003	} X86DESC64GENERIC;
4004	#pragma pack()
4005	/** Pointer to a generic descriptor entry. */
4006	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
4007	/** Pointer to a const generic descriptor entry. */
4008	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
4009
4010	/**
4011	* System descriptor table entry (64 bits)
4012	*
4013	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
4014	*/
4015	#pragma pack(1)
4016	typedef struct X86DESC64SYSTEM
4017	{
4018	/** Limit - Low word. */
4019	uint32_t u16LimitLow : 16;
4020	/** Base address - low word.
4021	* Don't try set this to 24 because MSC is doing stupid things then. */
4022	uint32_t u16BaseLow : 16;
4023	/** Base address - first 8 bits of high word. */
4024	uint32_t u8BaseHigh1 : 8;
4025	/** Segment Type. */
4026	uint32_t u4Type : 4;
4027	/** Descriptor Type. System(=0) or code/data selector */
4028	uint32_t u1DescType : 1;
4029	/** Descriptor Privilege level. */
4030	uint32_t u2Dpl : 2;
4031	/** Flags selector present(=1) or not. */
4032	uint32_t u1Present : 1;
4033	/** Segment limit 16-19. */
4034	uint32_t u4LimitHigh : 4;
4035	/** Available for system software. */
4036	uint32_t u1Available : 1;
4037	/** Reserved - 0. */
4038	uint32_t u1Reserved : 1;
4039	/** This flags meaning depends on the segment type. Try make sense out
4040	* of the intel manual yourself. */
4041	uint32_t u1DefBig : 1;
4042	/** Granularity of the limit. If set 4KB granularity is used, if
4043	* clear byte. */
4044	uint32_t u1Granularity : 1;
4045	/** Base address - bits 31-24. */
4046	uint32_t u8BaseHigh2 : 8;
4047	/** Base address - bits 63-32. */
4048	uint32_t u32BaseHigh3 : 32;
4049	uint32_t u8Reserved : 8;
4050	uint32_t u5Zeros : 5;
4051	uint32_t u19Reserved : 19;
4052	} X86DESC64SYSTEM;
4053	#pragma pack()
4054	/** Pointer to a system descriptor entry. */
4055	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
4056	/** Pointer to a const system descriptor entry. */
4057	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
4058
4059	/**
4060	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
4061	*/
4062	typedef struct X86DESC64GATE
4063	{
4064	/** Target code segment offset - Low word. */
4065	uint32_t u16OffsetLow : 16;
4066	/** Target code segment selector. */
4067	uint32_t u16Sel : 16;
4068	/** Interrupt stack table for interrupt- and trap-gates.
4069	* Ignored by call-gates. */
4070	uint32_t u3IST : 3;
4071	/** Reserved / ignored. */
4072	uint32_t u5Reserved : 5;
4073	/** Segment Type. */
4074	uint32_t u4Type : 4;
4075	/** Descriptor Type (0 = system). */
4076	uint32_t u1DescType : 1;
4077	/** Descriptor Privilege level. */
4078	uint32_t u2Dpl : 2;
4079	/** Flags selector present(=1) or not. */
4080	uint32_t u1Present : 1;
4081	/** Target code segment offset - High word.
4082	* Ignored if task-gate. */
4083	uint32_t u16OffsetHigh : 16;
4084	/** Target code segment offset - Top dword.
4085	* Ignored if task-gate. */
4086	uint32_t u32OffsetTop : 32;
4087	/** Reserved / ignored / must be zero.
4088	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
4089	uint32_t u32Reserved : 32;
4090	} X86DESC64GATE;
4091	AssertCompileSize(X86DESC64GATE, 16);
4092	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4093	typedef X86DESC64GATE *PX86DESC64GATE;
4094	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4095	typedef const X86DESC64GATE *PCX86DESC64GATE;
4096
4097	#endif /* VBOX_FOR_DTRACE_LIB */
4098
4099	/**
4100	* Descriptor table entry.
4101	*/
4102	#pragma pack(1)
4103	typedef union X86DESC64
4104	{
4105	#ifndef VBOX_FOR_DTRACE_LIB
4106	/** Generic descriptor view. */
4107	X86DESC64GENERIC Gen;
4108	/** System descriptor view. */
4109	X86DESC64SYSTEM System;
4110	/** Gate descriptor view. */
4111	X86DESC64GATE Gate;
4112	#endif
4113
4114	/** 8 bit unsigned integer view. */
4115	uint8_t au8[16];
4116	/** 16 bit unsigned integer view. */
4117	uint16_t au16[8];
4118	/** 32 bit unsigned integer view. */
4119	uint32_t au32[4];
4120	/** 64 bit unsigned integer view. */
4121	uint64_t au64[2];
4122	} X86DESC64;
4123	#ifndef VBOX_FOR_DTRACE_LIB
4124	AssertCompileSize(X86DESC64, 16);
4125	#endif
4126	#pragma pack()
4127	/** Pointer to descriptor table entry. */
4128	typedef X86DESC64 *PX86DESC64;
4129	/** Pointer to const descriptor table entry. */
4130	typedef const X86DESC64 *PCX86DESC64;
4131
4132	/** @def X86DESC64_BASE
4133	* Return the base of a 64-bit descriptor.
4134	*/
4135	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
4136	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
4137	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4138	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4139	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4140
4141
4142
4143	/** @name Host system descriptor table entry - Use with care!
4144	* @{ */
4145	/** Host system descriptor table entry. */
4146	#if HC_ARCH_BITS == 64
4147	typedef X86DESC64 X86DESCHC;
4148	#else
4149	typedef X86DESC X86DESCHC;
4150	#endif
4151	/** Pointer to a host system descriptor table entry. */
4152	#if HC_ARCH_BITS == 64
4153	typedef PX86DESC64 PX86DESCHC;
4154	#else
4155	typedef PX86DESC PX86DESCHC;
4156	#endif
4157	/** Pointer to a const host system descriptor table entry. */
4158	#if HC_ARCH_BITS == 64
4159	typedef PCX86DESC64 PCX86DESCHC;
4160	#else
4161	typedef PCX86DESC PCX86DESCHC;
4162	#endif
4163	/** @} */
4164
4165
4166	/** @name Selector Descriptor Types.
4167	* @{
4168	*/
4169
4170	/** @name Non-System Selector Types.
4171	* @{ */
4172	/** Code(=set)/Data(=clear) bit. */
4173	#define X86_SEL_TYPE_CODE 8
4174	/** Memory(=set)/System(=clear) bit. */
4175	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
4176	/** Accessed bit. */
4177	#define X86_SEL_TYPE_ACCESSED 1
4178	/** Expand down bit (for data selectors only). */
4179	#define X86_SEL_TYPE_DOWN 4
4180	/** Conforming bit (for code selectors only). */
4181	#define X86_SEL_TYPE_CONF 4
4182	/** Write bit (for data selectors only). */
4183	#define X86_SEL_TYPE_WRITE 2
4184	/** Read bit (for code selectors only). */
4185	#define X86_SEL_TYPE_READ 2
4186	/** The bit number of the code segment read bit (relative to u4Type). */
4187	#define X86_SEL_TYPE_READ_BIT 1
4188
4189	/** Read only selector type. */
4190	#define X86_SEL_TYPE_RO 0
4191	/** Accessed read only selector type. */
4192	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
4193	/** Read write selector type. */
4194	#define X86_SEL_TYPE_RW 2
4195	/** Accessed read write selector type. */
4196	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
4197	/** Expand down read only selector type. */
4198	#define X86_SEL_TYPE_RO_DOWN 4
4199	/** Accessed expand down read only selector type. */
4200	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
4201	/** Expand down read write selector type. */
4202	#define X86_SEL_TYPE_RW_DOWN 6
4203	/** Accessed expand down read write selector type. */
4204	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
4205	/** Execute only selector type. */
4206	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
4207	/** Accessed execute only selector type. */
4208	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4209	/** Execute and read selector type. */
4210	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
4211	/** Accessed execute and read selector type. */
4212	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4213	/** Conforming execute only selector type. */
4214	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
4215	/** Accessed Conforming execute only selector type. */
4216	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4217	/** Conforming execute and write selector type. */
4218	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
4219	/** Accessed Conforming execute and write selector type. */
4220	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4221	/** @} */
4222
4223
4224	/** @name System Selector Types.
4225	* @{ */
4226	/** The TSS busy bit mask. */
4227	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4228
4229	/** Undefined system selector type. */
4230	#define X86_SEL_TYPE_SYS_UNDEFINED 0
4231	/** 286 TSS selector. */
4232	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4233	/** LDT selector. */
4234	#define X86_SEL_TYPE_SYS_LDT 2
4235	/** 286 TSS selector - Busy. */
4236	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4237	/** 286 Callgate selector. */
4238	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4239	/** Taskgate selector. */
4240	#define X86_SEL_TYPE_SYS_TASK_GATE 5
4241	/** 286 Interrupt gate selector. */
4242	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4243	/** 286 Trapgate selector. */
4244	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4245	/** Undefined system selector. */
4246	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4247	/** 386 TSS selector. */
4248	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4249	/** Undefined system selector. */
4250	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4251	/** 386 TSS selector - Busy. */
4252	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4253	/** 386 Callgate selector. */
4254	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4255	/** Undefined system selector. */
4256	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4257	/** 386 Interruptgate selector. */
4258	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4259	/** 386 Trapgate selector. */
4260	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4261	/** @} */
4262
4263	/** @name AMD64 System Selector Types.
4264	* @{ */
4265	/** LDT selector. */
4266	#define AMD64_SEL_TYPE_SYS_LDT 2
4267	/** TSS selector - Busy. */
4268	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4269	/** TSS selector - Busy. */
4270	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4271	/** Callgate selector. */
4272	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4273	/** Interruptgate selector. */
4274	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4275	/** Trapgate selector. */
4276	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4277	/** @} */
4278
4279	/** @} */
4280
4281
4282	/** @name Descriptor Table Entry Flag Masks.
4283	* These are for the 2nd 32-bit word of a descriptor.
4284	* @{ */
4285	/** Bits 8-11 - TYPE - Descriptor type mask. */
4286	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
4287	/** Bit 12 - S - System (=0) or Code/Data (=1). */
4288	#define X86_DESC_S RT_BIT_32(12)
4289	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4290	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
4291	/** Bit 15 - P - Present. */
4292	#define X86_DESC_P RT_BIT_32(15)
4293	/** Bit 20 - AVL - Available for system software. */
4294	#define X86_DESC_AVL RT_BIT_32(20)
4295	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4296	#define X86_DESC_DB RT_BIT_32(22)
4297	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4298	* used, if clear byte. */
4299	#define X86_DESC_G RT_BIT_32(23)
4300	/** @} */
4301
4302	/** @} */
4303
4304
4305	/** @name Task Segments.
4306	* @{
4307	*/
4308
4309	/**
4310	* The minimum TSS descriptor limit for 286 tasks.
4311	*/
4312	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4313
4314	/**
4315	* The minimum TSS descriptor segment limit for 386 tasks.
4316	*/
4317	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4318
4319	/**
4320	* 16-bit Task Segment (TSS).
4321	*/
4322	#pragma pack(1)
4323	typedef struct X86TSS16
4324	{
4325	/** Back link to previous task. (static) */
4326	RTSEL selPrev;
4327	/** Ring-0 stack pointer. (static) */
4328	uint16_t sp0;
4329	/** Ring-0 stack segment. (static) */
4330	RTSEL ss0;
4331	/** Ring-1 stack pointer. (static) */
4332	uint16_t sp1;
4333	/** Ring-1 stack segment. (static) */
4334	RTSEL ss1;
4335	/** Ring-2 stack pointer. (static) */
4336	uint16_t sp2;
4337	/** Ring-2 stack segment. (static) */
4338	RTSEL ss2;
4339	/** IP before task switch. */
4340	uint16_t ip;
4341	/** FLAGS before task switch. */
4342	uint16_t flags;
4343	/** AX before task switch. */
4344	uint16_t ax;
4345	/** CX before task switch. */
4346	uint16_t cx;
4347	/** DX before task switch. */
4348	uint16_t dx;
4349	/** BX before task switch. */
4350	uint16_t bx;
4351	/** SP before task switch. */
4352	uint16_t sp;
4353	/** BP before task switch. */
4354	uint16_t bp;
4355	/** SI before task switch. */
4356	uint16_t si;
4357	/** DI before task switch. */
4358	uint16_t di;
4359	/** ES before task switch. */
4360	RTSEL es;
4361	/** CS before task switch. */
4362	RTSEL cs;
4363	/** SS before task switch. */
4364	RTSEL ss;
4365	/** DS before task switch. */
4366	RTSEL ds;
4367	/** LDTR before task switch. */
4368	RTSEL selLdt;
4369	} X86TSS16;
4370	#ifndef VBOX_FOR_DTRACE_LIB
4371	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4372	#endif
4373	#pragma pack()
4374	/** Pointer to a 16-bit task segment. */
4375	typedef X86TSS16 *PX86TSS16;
4376	/** Pointer to a const 16-bit task segment. */
4377	typedef const X86TSS16 *PCX86TSS16;
4378
4379
4380	/**
4381	* 32-bit Task Segment (TSS).
4382	*/
4383	#pragma pack(1)
4384	typedef struct X86TSS32
4385	{
4386	/** Back link to previous task. (static) */
4387	RTSEL selPrev;
4388	uint16_t padding1;
4389	/** Ring-0 stack pointer. (static) */
4390	uint32_t esp0;
4391	/** Ring-0 stack segment. (static) */
4392	RTSEL ss0;
4393	uint16_t padding_ss0;
4394	/** Ring-1 stack pointer. (static) */
4395	uint32_t esp1;
4396	/** Ring-1 stack segment. (static) */
4397	RTSEL ss1;
4398	uint16_t padding_ss1;
4399	/** Ring-2 stack pointer. (static) */
4400	uint32_t esp2;
4401	/** Ring-2 stack segment. (static) */
4402	RTSEL ss2;
4403	uint16_t padding_ss2;
4404	/** Page directory for the task. (static) */
4405	uint32_t cr3;
4406	/** EIP before task switch. */
4407	uint32_t eip;
4408	/** EFLAGS before task switch. */
4409	uint32_t eflags;
4410	/** EAX before task switch. */
4411	uint32_t eax;
4412	/** ECX before task switch. */
4413	uint32_t ecx;
4414	/** EDX before task switch. */
4415	uint32_t edx;
4416	/** EBX before task switch. */
4417	uint32_t ebx;
4418	/** ESP before task switch. */
4419	uint32_t esp;
4420	/** EBP before task switch. */
4421	uint32_t ebp;
4422	/** ESI before task switch. */
4423	uint32_t esi;
4424	/** EDI before task switch. */
4425	uint32_t edi;
4426	/** ES before task switch. */
4427	RTSEL es;
4428	uint16_t padding_es;
4429	/** CS before task switch. */
4430	RTSEL cs;
4431	uint16_t padding_cs;
4432	/** SS before task switch. */
4433	RTSEL ss;
4434	uint16_t padding_ss;
4435	/** DS before task switch. */
4436	RTSEL ds;
4437	uint16_t padding_ds;
4438	/** FS before task switch. */
4439	RTSEL fs;
4440	uint16_t padding_fs;
4441	/** GS before task switch. */
4442	RTSEL gs;
4443	uint16_t padding_gs;
4444	/** LDTR before task switch. */
4445	RTSEL selLdt;
4446	uint16_t padding_ldt;
4447	/** Debug trap flag */
4448	uint16_t fDebugTrap;
4449	/** Offset relative to the TSS of the start of the I/O Bitmap
4450	* and the end of the interrupt redirection bitmap. */
4451	uint16_t offIoBitmap;
4452	} X86TSS32;
4453	#pragma pack()
4454	/** Pointer to task segment. */
4455	typedef X86TSS32 *PX86TSS32;
4456	/** Pointer to const task segment. */
4457	typedef const X86TSS32 *PCX86TSS32;
4458	#ifndef VBOX_FOR_DTRACE_LIB
4459	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4460	AssertCompileMemberOffset(X86TSS32, cr3, 28);
4461	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4462	#endif
4463
4464	/**
4465	* 64-bit Task segment.
4466	*/
4467	#pragma pack(1)
4468	typedef struct X86TSS64
4469	{
4470	/** Reserved. */
4471	uint32_t u32Reserved;
4472	/** Ring-0 stack pointer. (static) */
4473	uint64_t rsp0;
4474	/** Ring-1 stack pointer. (static) */
4475	uint64_t rsp1;
4476	/** Ring-2 stack pointer. (static) */
4477	uint64_t rsp2;
4478	/** Reserved. */
4479	uint32_t u32Reserved2[2];
4480	/* IST */
4481	uint64_t ist1;
4482	uint64_t ist2;
4483	uint64_t ist3;
4484	uint64_t ist4;
4485	uint64_t ist5;
4486	uint64_t ist6;
4487	uint64_t ist7;
4488	/* Reserved. */
4489	uint16_t u16Reserved[5];
4490	/** Offset relative to the TSS of the start of the I/O Bitmap
4491	* and the end of the interrupt redirection bitmap. */
4492	uint16_t offIoBitmap;
4493	} X86TSS64;
4494	#pragma pack()
4495	/** Pointer to a 64-bit task segment. */
4496	typedef X86TSS64 *PX86TSS64;
4497	/** Pointer to a const 64-bit task segment. */
4498	typedef const X86TSS64 *PCX86TSS64;
4499	#ifndef VBOX_FOR_DTRACE_LIB
4500	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4501	#endif
4502
4503	/** @} */
4504
4505
4506	/** @name Selectors.
4507	* @{
4508	*/
4509
4510	/**
4511	* The shift used to convert a selector from and to index an index (C).
4512	*/
4513	#define X86_SEL_SHIFT 3
4514
4515	/**
4516	* The mask used to mask off the table indicator and RPL of an selector.
4517	*/
4518	#define X86_SEL_MASK 0xfff8U
4519
4520	/**
4521	* The mask used to mask off the RPL of an selector.
4522	* This is suitable for checking for NULL selectors.
4523	*/
4524	#define X86_SEL_MASK_OFF_RPL 0xfffcU
4525
4526	/**
4527	* The bit indicating that a selector is in the LDT and not in the GDT.
4528	*/
4529	#define X86_SEL_LDT 0x0004U
4530
4531	/**
4532	* The bit mask for getting the RPL of a selector.
4533	*/
4534	#define X86_SEL_RPL 0x0003U
4535
4536	/**
4537	* The mask covering both RPL and LDT.
4538	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4539	* checks.
4540	*/
4541	#define X86_SEL_RPL_LDT 0x0007U
4542
4543	/** @} */
4544
4545
4546	/**
4547	* x86 Exceptions/Faults/Traps.
4548	*/
4549	typedef enum X86XCPT
4550	{
4551	/** \#DE - Divide error. */
4552	X86_XCPT_DE = 0x00,
4553	/** \#DB - Debug event (single step, DRx, ..) */
4554	X86_XCPT_DB = 0x01,
4555	/** NMI - Non-Maskable Interrupt */
4556	X86_XCPT_NMI = 0x02,
4557	/** \#BP - Breakpoint (INT3). */
4558	X86_XCPT_BP = 0x03,
4559	/** \#OF - Overflow (INTO). */
4560	X86_XCPT_OF = 0x04,
4561	/** \#BR - Bound range exceeded (BOUND). */
4562	X86_XCPT_BR = 0x05,
4563	/** \#UD - Undefined opcode. */
4564	X86_XCPT_UD = 0x06,
4565	/** \#NM - Device not available (math coprocessor device). */
4566	X86_XCPT_NM = 0x07,
4567	/** \#DF - Double fault. */
4568	X86_XCPT_DF = 0x08,
4569	/** ??? - Coprocessor segment overrun (obsolete). */
4570	X86_XCPT_CO_SEG_OVERRUN = 0x09,
4571	/** \#TS - Taskswitch (TSS). */
4572	X86_XCPT_TS = 0x0a,
4573	/** \#NP - Segment no present. */
4574	X86_XCPT_NP = 0x0b,
4575	/** \#SS - Stack segment fault. */
4576	X86_XCPT_SS = 0x0c,
4577	/** \#GP - General protection fault. */
4578	X86_XCPT_GP = 0x0d,
4579	/** \#PF - Page fault. */
4580	X86_XCPT_PF = 0x0e,
4581	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4582	/** \#MF - Math fault (FPU). */
4583	X86_XCPT_MF = 0x10,
4584	/** \#AC - Alignment check. */
4585	X86_XCPT_AC = 0x11,
4586	/** \#MC - Machine check. */
4587	X86_XCPT_MC = 0x12,
4588	/** \#XF - SIMD Floating-Point Exception. */
4589	X86_XCPT_XF = 0x13,
4590	/** \#VE - Virtualization Exception (Intel only). */
4591	X86_XCPT_VE = 0x14,
4592	/** \#CP - Control Protection Exception (Intel only). */
4593	X86_XCPT_CP = 0x15,
4594	/** \#VC - VMM Communication Exception (AMD only). */
4595	X86_XCPT_VC = 0x1d,
4596	/** \#SX - Security Exception (AMD only). */
4597	X86_XCPT_SX = 0x1e
4598	} X86XCPT;
4599	/** Pointer to a x86 exception code. */
4600	typedef X86XCPT *PX86XCPT;
4601	/** Pointer to a const x86 exception code. */
4602	typedef const X86XCPT *PCX86XCPT;
4603	/** The last valid (currently reserved) exception value. */
4604	#define X86_XCPT_LAST 0x1f
4605
4606
4607	/** @name Trap Error Codes
4608	* @{
4609	*/
4610	/** External indicator. */
4611	#define X86_TRAP_ERR_EXTERNAL 1
4612	/** IDT indicator. */
4613	#define X86_TRAP_ERR_IDT 2
4614	/** Descriptor table indicator - If set LDT, if clear GDT. */
4615	#define X86_TRAP_ERR_TI 4
4616	/** Mask for getting the selector. */
4617	#define X86_TRAP_ERR_SEL_MASK 0xfff8
4618	/** Shift for getting the selector table index (C type index). */
4619	#define X86_TRAP_ERR_SEL_SHIFT 3
4620	/** @} */
4621
4622
4623	/** @name \#PF Trap Error Codes
4624	* @{
4625	*/
4626	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4627	#define X86_TRAP_PF_P RT_BIT_32(0)
4628	/** Bit 1 - R/W - Read (clear) or write (set) access. */
4629	#define X86_TRAP_PF_RW RT_BIT_32(1)
4630	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4631	#define X86_TRAP_PF_US RT_BIT_32(2)
4632	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4633	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4634	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4635	#define X86_TRAP_PF_ID RT_BIT_32(4)
4636	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4637	#define X86_TRAP_PF_PK RT_BIT_32(5)
4638	/** @} */
4639
4640	#pragma pack(1)
4641	/**
4642	* 16-bit IDTR.
4643	*/
4644	typedef struct X86IDTR16
4645	{
4646	/** Offset. */
4647	uint16_t offSel;
4648	/** Selector. */
4649	uint16_t uSel;
4650	} X86IDTR16, *PX86IDTR16;
4651	#pragma pack()
4652
4653	#pragma pack(1)
4654	/**
4655	* 32-bit IDTR/GDTR.
4656	*/
4657	typedef struct X86XDTR32
4658	{
4659	/** Size of the descriptor table. */
4660	uint16_t cb;
4661	/** Address of the descriptor table. */
4662	#ifndef VBOX_FOR_DTRACE_LIB
4663	uint32_t uAddr;
4664	#else
4665	uint16_t au16Addr[2];
4666	#endif
4667	} X86XDTR32, *PX86XDTR32;
4668	#pragma pack()
4669
4670	#pragma pack(1)
4671	/**
4672	* 64-bit IDTR/GDTR.
4673	*/
4674	typedef struct X86XDTR64
4675	{
4676	/** Size of the descriptor table. */
4677	uint16_t cb;
4678	/** Address of the descriptor table. */
4679	#ifndef VBOX_FOR_DTRACE_LIB
4680	uint64_t uAddr;
4681	#else
4682	uint16_t au16Addr[4];
4683	#endif
4684	} X86XDTR64, *PX86XDTR64;
4685	#pragma pack()
4686
4687
4688	/** @name ModR/M
4689	* @{ */
4690	#define X86_MODRM_RM_MASK UINT8_C(0x07)
4691	#define X86_MODRM_REG_MASK UINT8_C(0x38)
4692	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4693	#define X86_MODRM_REG_SHIFT 3
4694	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4695	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4696	#define X86_MODRM_MOD_SHIFT 6
4697	#ifndef VBOX_FOR_DTRACE_LIB
4698	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
4699	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4700	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4701	/** @def X86_MODRM_MAKE
4702	* @param a_Mod The mod value (0..3).
4703	* @param a_Reg The register value (0..7).
4704	* @param a_RegMem The register or memory value (0..7). */
4705	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
4706	#endif
4707	/** @} */
4708
4709	/** @name SIB
4710	* @{ */
4711	#define X86_SIB_BASE_MASK UINT8_C(0x07)
4712	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4713	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4714	#define X86_SIB_INDEX_SHIFT 3
4715	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4716	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4717	#define X86_SIB_SCALE_SHIFT 6
4718	#ifndef VBOX_FOR_DTRACE_LIB
4719	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
4720	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4721	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4722	#endif
4723	/** @} */
4724
4725	/** @name General register indexes.
4726	* @{ */
4727	#define X86_GREG_xAX 0
4728	#define X86_GREG_xCX 1
4729	#define X86_GREG_xDX 2
4730	#define X86_GREG_xBX 3
4731	#define X86_GREG_xSP 4
4732	#define X86_GREG_xBP 5
4733	#define X86_GREG_xSI 6
4734	#define X86_GREG_xDI 7
4735	#define X86_GREG_x8 8
4736	#define X86_GREG_x9 9
4737	#define X86_GREG_x10 10
4738	#define X86_GREG_x11 11
4739	#define X86_GREG_x12 12
4740	#define X86_GREG_x13 13
4741	#define X86_GREG_x14 14
4742	#define X86_GREG_x15 15
4743	/** @} */
4744	/** General register count. */
4745	#define X86_GREG_COUNT 16
4746
4747	/** @name X86_SREG_XXX - Segment register indexes.
4748	* @{ */
4749	#define X86_SREG_ES 0
4750	#define X86_SREG_CS 1
4751	#define X86_SREG_SS 2
4752	#define X86_SREG_DS 3
4753	#define X86_SREG_FS 4
4754	#define X86_SREG_GS 5
4755	/** @} */
4756	/** Segment register count. */
4757	#define X86_SREG_COUNT 6
4758
4759
4760	/** @name X86_OP_XXX - Prefixes
4761	* @{ */
4762	#define X86_OP_PRF_CS UINT8_C(0x2e)
4763	#define X86_OP_PRF_SS UINT8_C(0x36)
4764	#define X86_OP_PRF_DS UINT8_C(0x3e)
4765	#define X86_OP_PRF_ES UINT8_C(0x26)
4766	#define X86_OP_PRF_FS UINT8_C(0x64)
4767	#define X86_OP_PRF_GS UINT8_C(0x65)
4768	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4769	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4770	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4771	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4772	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4773	#define X86_OP_REX_B UINT8_C(0x41)
4774	#define X86_OP_REX_X UINT8_C(0x42)
4775	#define X86_OP_REX_R UINT8_C(0x44)
4776	#define X86_OP_REX_W UINT8_C(0x48)
4777	/** @} */
4778
4779
4780	/** @} */
4781
4782	#endif /* !IPRT_INCLUDED_x86_h */
4783

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source: vbox/trunk/include/iprt/x86.h@ 96251

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