x86.h@ 99026

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1	/** @file
2	* IPRT - X86 and AMD64 Structures and Definitions.
3	*
4	* @note x86.mac is generated from this file by running 'kmk incs' in the root.
5	*/
6
7	/*
8	* Copyright (C) 2006-2023 Oracle and/or its affiliates.
9	*
10	* This file is part of VirtualBox base platform packages, as
11	* available from https://www.virtualbox.org.
12	*
13	* This program is free software; you can redistribute it and/or
14	* modify it under the terms of the GNU General Public License
15	* as published by the Free Software Foundation, in version 3 of the
16	* License.
17	*
18	* This program is distributed in the hope that it will be useful, but
19	* WITHOUT ANY WARRANTY; without even the implied warranty of
20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
21	* General Public License for more details.
22	*
23	* You should have received a copy of the GNU General Public License
24	* along with this program; if not, see <https://www.gnu.org/licenses>.
25	*
26	* The contents of this file may alternatively be used under the terms
27	* of the Common Development and Distribution License Version 1.0
28	* (CDDL), a copy of it is provided in the "COPYING.CDDL" file included
29	* in the VirtualBox distribution, in which case the provisions of the
30	* CDDL are applicable instead of those of the GPL.
31	*
32	* You may elect to license modified versions of this file under the
33	* terms and conditions of either the GPL or the CDDL or both.
34	*
35	* SPDX-License-Identifier: GPL-3.0-only OR CDDL-1.0
36	*/
37
38	#ifndef IPRT_INCLUDED_x86_h
39	#define IPRT_INCLUDED_x86_h
40	#ifndef RT_WITHOUT_PRAGMA_ONCE
41	# pragma once
42	#endif
43
44	#ifndef VBOX_FOR_DTRACE_LIB
45	# include <iprt/types.h>
46	# include <iprt/assert.h>
47	#else
48	# pragma D depends_on library vbox-types.d
49	#endif
50
51	/** Workaround for Solaris sys/regset.h defining CS, DS and sys/controlregs.h
52	* defining MSR_IA32_FLUSH_CMD */
53	#ifdef RT_OS_SOLARIS
54	# undef CS
55	# undef DS
56	# undef MSR_IA32_FLUSH_CMD
57	#endif
58
59	/** @defgroup grp_rt_x86 x86 Types and Definitions
60	* @ingroup grp_rt
61	* @{
62	*/
63
64	#ifndef VBOX_FOR_DTRACE_LIB
65	/**
66	* EFLAGS Bits.
67	*/
68	typedef struct X86EFLAGSBITS
69	{
70	/** Bit 0 - CF - Carry flag - Status flag. */
71	unsigned u1CF : 1;
72	/** Bit 1 - 1 - Reserved flag. */
73	unsigned u1Reserved0 : 1;
74	/** Bit 2 - PF - Parity flag - Status flag. */
75	unsigned u1PF : 1;
76	/** Bit 3 - 0 - Reserved flag. */
77	unsigned u1Reserved1 : 1;
78	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
79	unsigned u1AF : 1;
80	/** Bit 5 - 0 - Reserved flag. */
81	unsigned u1Reserved2 : 1;
82	/** Bit 6 - ZF - Zero flag - Status flag. */
83	unsigned u1ZF : 1;
84	/** Bit 7 - SF - Signed flag - Status flag. */
85	unsigned u1SF : 1;
86	/** Bit 8 - TF - Trap flag - System flag. */
87	unsigned u1TF : 1;
88	/** Bit 9 - IF - Interrupt flag - System flag. */
89	unsigned u1IF : 1;
90	/** Bit 10 - DF - Direction flag - Control flag. */
91	unsigned u1DF : 1;
92	/** Bit 11 - OF - Overflow flag - Status flag. */
93	unsigned u1OF : 1;
94	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
95	unsigned u2IOPL : 2;
96	/** Bit 14 - NT - Nested task flag - System flag. */
97	unsigned u1NT : 1;
98	/** Bit 15 - 0 - Reserved flag. */
99	unsigned u1Reserved3 : 1;
100	/** Bit 16 - RF - Resume flag - System flag. */
101	unsigned u1RF : 1;
102	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
103	unsigned u1VM : 1;
104	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
105	unsigned u1AC : 1;
106	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
107	unsigned u1VIF : 1;
108	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
109	unsigned u1VIP : 1;
110	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
111	unsigned u1ID : 1;
112	/** Bit 22-31 - 0 - Reserved flag. */
113	unsigned u10Reserved4 : 10;
114	} X86EFLAGSBITS;
115	/** Pointer to EFLAGS bits. */
116	typedef X86EFLAGSBITS *PX86EFLAGSBITS;
117	/** Pointer to const EFLAGS bits. */
118	typedef const X86EFLAGSBITS *PCX86EFLAGSBITS;
119	#endif /* !VBOX_FOR_DTRACE_LIB */
120
121	/**
122	* EFLAGS.
123	*/
124	typedef union X86EFLAGS
125	{
126	/** The plain unsigned view. */
127	uint32_t u;
128	#ifndef VBOX_FOR_DTRACE_LIB
129	/** The bitfield view. */
130	X86EFLAGSBITS Bits;
131	#endif
132	/** The 8-bit view. */
133	uint8_t au8[4];
134	/** The 16-bit view. */
135	uint16_t au16[2];
136	/** The 32-bit view. */
137	uint32_t au32[1];
138	/** The 32-bit view. */
139	uint32_t u32;
140	} X86EFLAGS;
141	/** Pointer to EFLAGS. */
142	typedef X86EFLAGS *PX86EFLAGS;
143	/** Pointer to const EFLAGS. */
144	typedef const X86EFLAGS *PCX86EFLAGS;
145
146	/**
147	* RFLAGS (32 upper bits are reserved).
148	*/
149	typedef union X86RFLAGS
150	{
151	/** The plain unsigned view. */
152	uint64_t u;
153	#ifndef VBOX_FOR_DTRACE_LIB
154	/** The bitfield view. */
155	X86EFLAGSBITS Bits;
156	#endif
157	/** The 8-bit view. */
158	uint8_t au8[8];
159	/** The 16-bit view. */
160	uint16_t au16[4];
161	/** The 32-bit view. */
162	uint32_t au32[2];
163	/** The 64-bit view. */
164	uint64_t au64[1];
165	/** The 64-bit view. */
166	uint64_t u64;
167	} X86RFLAGS;
168	/** Pointer to RFLAGS. */
169	typedef X86RFLAGS *PX86RFLAGS;
170	/** Pointer to const RFLAGS. */
171	typedef const X86RFLAGS *PCX86RFLAGS;
172
173
174	/** @name EFLAGS
175	* @{
176	*/
177	/** Bit 0 - CF - Carry flag - Status flag. */
178	#define X86_EFL_CF RT_BIT_32(0)
179	#define X86_EFL_CF_BIT 0
180	/** Bit 1 - Reserved, reads as 1. */
181	#define X86_EFL_1 RT_BIT_32(1)
182	/** Bit 2 - PF - Parity flag - Status flag. */
183	#define X86_EFL_PF RT_BIT_32(2)
184	#define X86_EFL_PF_BIT 2
185	/** Bit 4 - AF - Auxiliary carry flag - Status flag. */
186	#define X86_EFL_AF RT_BIT_32(4)
187	#define X86_EFL_AF_BIT 4
188	/** Bit 6 - ZF - Zero flag - Status flag. */
189	#define X86_EFL_ZF RT_BIT_32(6)
190	#define X86_EFL_ZF_BIT 6
191	/** Bit 7 - SF - Signed flag - Status flag. */
192	#define X86_EFL_SF RT_BIT_32(7)
193	#define X86_EFL_SF_BIT 7
194	/** Bit 8 - TF - Trap flag - System flag. */
195	#define X86_EFL_TF RT_BIT_32(8)
196	#define X86_EFL_TF_BIT 8
197	/** Bit 9 - IF - Interrupt flag - System flag. */
198	#define X86_EFL_IF RT_BIT_32(9)
199	#define X86_EFL_IF_BIT 9
200	/** Bit 10 - DF - Direction flag - Control flag. */
201	#define X86_EFL_DF RT_BIT_32(10)
202	#define X86_EFL_DF_BIT 10
203	/** Bit 11 - OF - Overflow flag - Status flag. */
204	#define X86_EFL_OF RT_BIT_32(11)
205	#define X86_EFL_OF_BIT 11
206	/** Bit 12-13 - IOPL - I/O privilege level flag - System flag. */
207	#define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
208	/** Bit 14 - NT - Nested task flag - System flag. */
209	#define X86_EFL_NT RT_BIT_32(14)
210	#define X86_EFL_NT_BIT 14
211	/** Bit 16 - RF - Resume flag - System flag. */
212	#define X86_EFL_RF RT_BIT_32(16)
213	#define X86_EFL_RF_BIT 16
214	/** Bit 17 - VM - Virtual 8086 mode - System flag. */
215	#define X86_EFL_VM RT_BIT_32(17)
216	#define X86_EFL_VM_BIT 17
217	/** Bit 18 - AC - Alignment check flag - System flag. Works with CR0.AM. */
218	#define X86_EFL_AC RT_BIT_32(18)
219	#define X86_EFL_AC_BIT 18
220	/** Bit 19 - VIF - Virtual interrupt flag - System flag. */
221	#define X86_EFL_VIF RT_BIT_32(19)
222	#define X86_EFL_VIF_BIT 19
223	/** Bit 20 - VIP - Virtual interrupt pending flag - System flag. */
224	#define X86_EFL_VIP RT_BIT_32(20)
225	#define X86_EFL_VIP_BIT 20
226	/** Bit 21 - ID - CPUID flag - System flag. If this responds to flipping CPUID is supported. */
227	#define X86_EFL_ID RT_BIT_32(21)
228	#define X86_EFL_ID_BIT 21
229	/** All live bits. */
230	#define X86_EFL_LIVE_MASK UINT32_C(0x003f7fd5)
231	/** Read as 1 bits. */
232	#define X86_EFL_RA1_MASK RT_BIT_32(1)
233	/** Read as 0 bits, excluding bits 31:22.
234	* Bits 3, 5, 15, and 22 thru 31. */
235	#define X86_EFL_RAZ_MASK UINT32_C(0xffc08028)
236	/** Read as 0 bits, excluding bits 31:22.
237	* Bits 3, 5 and 15. */
238	#define X86_EFL_RAZ_LO_MASK UINT32_C(0x00008028)
239	/** IOPL shift. */
240	#define X86_EFL_IOPL_SHIFT 12
241	/** The IOPL level from the flags. */
242	#define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
243	/** Bits restored by popf */
244	#define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
245	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
246	/** Bits restored by popf */
247	#define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
248	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
249	/** The status bits commonly updated by arithmetic instructions. */
250	#define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
251	/** @} */
252
253
254	/** CPUID Feature information - ECX.
255	* CPUID query with EAX=1.
256	*/
257	#ifndef VBOX_FOR_DTRACE_LIB
258	typedef struct X86CPUIDFEATECX
259	{
260	/** Bit 0 - SSE3 - Supports SSE3 or not. */
261	unsigned u1SSE3 : 1;
262	/** Bit 1 - PCLMULQDQ. */
263	unsigned u1PCLMULQDQ : 1;
264	/** Bit 2 - DS Area 64-bit layout. */
265	unsigned u1DTE64 : 1;
266	/** Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
267	unsigned u1Monitor : 1;
268	/** Bit 4 - CPL-DS - CPL Qualified Debug Store. */
269	unsigned u1CPLDS : 1;
270	/** Bit 5 - VMX - Virtual Machine Technology. */
271	unsigned u1VMX : 1;
272	/** Bit 6 - SMX: Safer Mode Extensions. */
273	unsigned u1SMX : 1;
274	/** Bit 7 - EST - Enh. SpeedStep Tech. */
275	unsigned u1EST : 1;
276	/** Bit 8 - TM2 - Terminal Monitor 2. */
277	unsigned u1TM2 : 1;
278	/** Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
279	unsigned u1SSSE3 : 1;
280	/** Bit 10 - CNTX-ID - L1 Context ID. */
281	unsigned u1CNTXID : 1;
282	/** Bit 11 - Reserved. */
283	unsigned u1Reserved1 : 1;
284	/** Bit 12 - FMA. */
285	unsigned u1FMA : 1;
286	/** Bit 13 - CX16 - CMPXCHG16B. */
287	unsigned u1CX16 : 1;
288	/** Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
289	unsigned u1TPRUpdate : 1;
290	/** Bit 15 - PDCM - Perf/Debug Capability MSR. */
291	unsigned u1PDCM : 1;
292	/** Bit 16 - Reserved. */
293	unsigned u1Reserved2 : 1;
294	/** Bit 17 - PCID - Process-context identifiers. */
295	unsigned u1PCID : 1;
296	/** Bit 18 - Direct Cache Access. */
297	unsigned u1DCA : 1;
298	/** Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
299	unsigned u1SSE4_1 : 1;
300	/** Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
301	unsigned u1SSE4_2 : 1;
302	/** Bit 21 - x2APIC. */
303	unsigned u1x2APIC : 1;
304	/** Bit 22 - MOVBE - Supports MOVBE. */
305	unsigned u1MOVBE : 1;
306	/** Bit 23 - POPCNT - Supports POPCNT. */
307	unsigned u1POPCNT : 1;
308	/** Bit 24 - TSC-Deadline. */
309	unsigned u1TSCDEADLINE : 1;
310	/** Bit 25 - AES. */
311	unsigned u1AES : 1;
312	/** Bit 26 - XSAVE - Supports XSAVE. */
313	unsigned u1XSAVE : 1;
314	/** Bit 27 - OSXSAVE - Supports OSXSAVE. */
315	unsigned u1OSXSAVE : 1;
316	/** Bit 28 - AVX - Supports AVX instruction extensions. */
317	unsigned u1AVX : 1;
318	/** Bit 29 - F16C - Supports 16-bit floating point conversion instructions. */
319	unsigned u1F16C : 1;
320	/** Bit 30 - RDRAND - Supports RDRAND. */
321	unsigned u1RDRAND : 1;
322	/** Bit 31 - Hypervisor present (we're a guest). */
323	unsigned u1HVP : 1;
324	} X86CPUIDFEATECX;
325	#else /* VBOX_FOR_DTRACE_LIB */
326	typedef uint32_t X86CPUIDFEATECX;
327	#endif /* VBOX_FOR_DTRACE_LIB */
328	/** Pointer to CPUID Feature Information - ECX. */
329	typedef X86CPUIDFEATECX *PX86CPUIDFEATECX;
330	/** Pointer to const CPUID Feature Information - ECX. */
331	typedef const X86CPUIDFEATECX *PCX86CPUIDFEATECX;
332
333
334	/** CPUID Feature Information - EDX.
335	* CPUID query with EAX=1.
336	*/
337	#ifndef VBOX_FOR_DTRACE_LIB /* DTrace different (brain-dead from a C pov) bitfield implementation */
338	typedef struct X86CPUIDFEATEDX
339	{
340	/** Bit 0 - FPU - x87 FPU on Chip. */
341	unsigned u1FPU : 1;
342	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
343	unsigned u1VME : 1;
344	/** Bit 2 - DE - Debugging extensions. */
345	unsigned u1DE : 1;
346	/** Bit 3 - PSE - Page Size Extension. */
347	unsigned u1PSE : 1;
348	/** Bit 4 - TSC - Time Stamp Counter. */
349	unsigned u1TSC : 1;
350	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
351	unsigned u1MSR : 1;
352	/** Bit 6 - PAE - Physical Address Extension. */
353	unsigned u1PAE : 1;
354	/** Bit 7 - MCE - Machine Check Exception. */
355	unsigned u1MCE : 1;
356	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
357	unsigned u1CX8 : 1;
358	/** Bit 9 - APIC - APIC On-Chip. */
359	unsigned u1APIC : 1;
360	/** Bit 10 - Reserved. */
361	unsigned u1Reserved1 : 1;
362	/** Bit 11 - SEP - SYSENTER and SYSEXIT. */
363	unsigned u1SEP : 1;
364	/** Bit 12 - MTRR - Memory Type Range Registers. */
365	unsigned u1MTRR : 1;
366	/** Bit 13 - PGE - PTE Global Bit. */
367	unsigned u1PGE : 1;
368	/** Bit 14 - MCA - Machine Check Architecture. */
369	unsigned u1MCA : 1;
370	/** Bit 15 - CMOV - Conditional Move Instructions. */
371	unsigned u1CMOV : 1;
372	/** Bit 16 - PAT - Page Attribute Table. */
373	unsigned u1PAT : 1;
374	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
375	unsigned u1PSE36 : 1;
376	/** Bit 18 - PSN - Processor Serial Number. */
377	unsigned u1PSN : 1;
378	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
379	unsigned u1CLFSH : 1;
380	/** Bit 20 - Reserved. */
381	unsigned u1Reserved2 : 1;
382	/** Bit 21 - DS - Debug Store. */
383	unsigned u1DS : 1;
384	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
385	unsigned u1ACPI : 1;
386	/** Bit 23 - MMX - Intel MMX 'Technology'. */
387	unsigned u1MMX : 1;
388	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
389	unsigned u1FXSR : 1;
390	/** Bit 25 - SSE - SSE Support. */
391	unsigned u1SSE : 1;
392	/** Bit 26 - SSE2 - SSE2 Support. */
393	unsigned u1SSE2 : 1;
394	/** Bit 27 - SS - Self Snoop. */
395	unsigned u1SS : 1;
396	/** Bit 28 - HTT - Hyper-Threading Technology. */
397	unsigned u1HTT : 1;
398	/** Bit 29 - TM - Thermal Monitor. */
399	unsigned u1TM : 1;
400	/** Bit 30 - Reserved - . */
401	unsigned u1Reserved3 : 1;
402	/** Bit 31 - PBE - Pending Break Enabled. */
403	unsigned u1PBE : 1;
404	} X86CPUIDFEATEDX;
405	#else /* VBOX_FOR_DTRACE_LIB */
406	typedef uint32_t X86CPUIDFEATEDX;
407	#endif /* VBOX_FOR_DTRACE_LIB */
408	/** Pointer to CPUID Feature Information - EDX. */
409	typedef X86CPUIDFEATEDX *PX86CPUIDFEATEDX;
410	/** Pointer to const CPUID Feature Information - EDX. */
411	typedef const X86CPUIDFEATEDX *PCX86CPUIDFEATEDX;
412
413	/** @name CPUID Vendor information.
414	* CPUID query with EAX=0.
415	* @{
416	*/
417	#define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547 /* Genu */
418	#define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e /* ntel */
419	#define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69 /* ineI */
420
421	#define X86_CPUID_VENDOR_AMD_EBX 0x68747541 /* Auth */
422	#define X86_CPUID_VENDOR_AMD_ECX 0x444d4163 /* cAMD */
423	#define X86_CPUID_VENDOR_AMD_EDX 0x69746e65 /* enti */
424
425	#define X86_CPUID_VENDOR_VIA_EBX 0x746e6543 /* Cent */
426	#define X86_CPUID_VENDOR_VIA_ECX 0x736c7561 /* auls */
427	#define X86_CPUID_VENDOR_VIA_EDX 0x48727561 /* aurH */
428
429	#define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020 /* Sh */
430	#define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961 /* ai */
431	#define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61 /* angh */
432
433	#define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948 /* Hygo */
434	#define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975 /* uine */
435	#define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e /* nGen */
436	/** @} */
437
438
439	/** @name CPUID Feature information.
440	* CPUID query with EAX=1.
441	* @{
442	*/
443	/** ECX Bit 0 - SSE3 - Supports SSE3 or not. */
444	#define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
445	/** ECX Bit 1 - PCLMUL - PCLMULQDQ support (for AES-GCM). */
446	#define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
447	/** ECX Bit 2 - DTES64 - DS Area 64-bit Layout. */
448	#define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
449	/** ECX Bit 3 - MONITOR - Supports MONITOR/MWAIT. */
450	#define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
451	/** ECX Bit 4 - CPL-DS - CPL Qualified Debug Store. */
452	#define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
453	/** ECX Bit 5 - VMX - Virtual Machine Technology. */
454	#define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
455	/** ECX Bit 6 - SMX - Safer Mode Extensions. */
456	#define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
457	/** ECX Bit 7 - EST - Enh. SpeedStep Tech. */
458	#define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
459	/** ECX Bit 8 - TM2 - Terminal Monitor 2. */
460	#define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
461	/** ECX Bit 9 - SSSE3 - Supplemental Streaming SIMD Extensions 3. */
462	#define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
463	/** ECX Bit 10 - CNTX-ID - L1 Context ID. */
464	#define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
465	/** ECX Bit 11 - SDBG - Sillicon debug interface (IA32_DEBUG_INTERFACE MSR).
466	* See figure 3-6 and table 3-10, in intel Vol. 2A. from 2015-01-01. */
467	#define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
468	/** ECX Bit 12 - FMA. */
469	#define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
470	/** ECX Bit 13 - CX16 - CMPXCHG16B. */
471	#define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
472	/** ECX Bit 14 - xTPR Update Control. Processor supports changing IA32_MISC_ENABLES[bit 23]. */
473	#define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
474	/** ECX Bit 15 - PDCM - Perf/Debug Capability MSR. */
475	#define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
476	/** ECX Bit 17 - PCID - Process-context identifiers. */
477	#define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
478	/** ECX Bit 18 - DCA - Direct Cache Access. */
479	#define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
480	/** ECX Bit 19 - SSE4_1 - Supports SSE4_1 or not. */
481	#define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
482	/** ECX Bit 20 - SSE4_2 - Supports SSE4_2 or not. */
483	#define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
484	/** ECX Bit 21 - x2APIC support. */
485	#define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
486	/** ECX Bit 22 - MOVBE instruction. */
487	#define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
488	/** ECX Bit 23 - POPCNT instruction. */
489	#define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
490	/** ECX Bir 24 - TSC-Deadline. */
491	#define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
492	/** ECX Bit 25 - AES instructions. */
493	#define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
494	/** ECX Bit 26 - XSAVE instruction. */
495	#define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
496	/** ECX Bit 27 - Copy of CR4.OSXSAVE. */
497	#define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
498	/** ECX Bit 28 - AVX. */
499	#define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
500	/** ECX Bit 29 - F16C - Half-precision convert instruction support. */
501	#define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
502	/** ECX Bit 30 - RDRAND instruction. */
503	#define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
504	/** ECX Bit 31 - Hypervisor Present (software only). */
505	#define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
506
507
508	/** Bit 0 - FPU - x87 FPU on Chip. */
509	#define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
510	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
511	#define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
512	/** Bit 2 - DE - Debugging extensions. */
513	#define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
514	/** Bit 3 - PSE - Page Size Extension. */
515	#define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
516	#define X86_CPUID_FEATURE_EDX_PSE_BIT 3 /*< Bit number for X86_CPUID_FEATURE_EDX_PSE. /
517	/** Bit 4 - TSC - Time Stamp Counter. */
518	#define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
519	/** Bit 5 - MSR - Model Specific Registers RDMSR and WRMSR Instructions. */
520	#define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
521	/** Bit 6 - PAE - Physical Address Extension. */
522	#define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
523	#define X86_CPUID_FEATURE_EDX_PAE_BIT 6 /*< Bit number for X86_CPUID_FEATURE_EDX_PAE. /
524	/** Bit 7 - MCE - Machine Check Exception. */
525	#define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
526	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
527	#define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
528	/** Bit 9 - APIC - APIC On-Chip. */
529	#define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
530	/** Bit 11 - SEP - SYSENTER and SYSEXIT Present. */
531	#define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
532	/** Bit 12 - MTRR - Memory Type Range Registers. */
533	#define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
534	/** Bit 13 - PGE - PTE Global Bit. */
535	#define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
536	/** Bit 14 - MCA - Machine Check Architecture. */
537	#define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
538	/** Bit 15 - CMOV - Conditional Move Instructions. */
539	#define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
540	/** Bit 16 - PAT - Page Attribute Table. */
541	#define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
542	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
543	#define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
544	/** Bit 18 - PSN - Processor Serial Number. */
545	#define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
546	/** Bit 19 - CLFSH - CLFLUSH Instruction. */
547	#define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
548	/** Bit 21 - DS - Debug Store. */
549	#define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
550	/** Bit 22 - ACPI - Thermal Monitor and Software Controlled Clock Facilities. */
551	#define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
552	/** Bit 23 - MMX - Intel MMX Technology. */
553	#define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
554	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
555	#define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
556	/** Bit 25 - SSE - SSE Support. */
557	#define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
558	/** Bit 26 - SSE2 - SSE2 Support. */
559	#define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
560	/** Bit 27 - SS - Self Snoop. */
561	#define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
562	/** Bit 28 - HTT - Hyper-Threading Technology. */
563	#define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
564	/** Bit 29 - TM - Therm. Monitor. */
565	#define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
566	/** Bit 31 - PBE - Pending Break Enabled. */
567	#define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
568	/** @} */
569
570	/** @name CPUID mwait/monitor information.
571	* CPUID query with EAX=5.
572	* @{
573	*/
574	/** ECX Bit 0 - MWAITEXT - Supports mwait/monitor extensions or not. */
575	#define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
576	/** ECX Bit 1 - MWAITBREAK - Break mwait for external interrupt even if EFLAGS.IF=0. */
577	#define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
578	/** @} */
579
580
581	/** @name CPUID Structured Extended Feature information.
582	* CPUID query with EAX=7.
583	* @{
584	*/
585	/** EBX Bit 0 - FSGSBASE - Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE. */
586	#define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
587	/** EBX Bit 1 - TSCADJUST - Supports MSR_IA32_TSC_ADJUST. */
588	#define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
589	/** EBX Bit 2 - SGX - Supports Software Guard Extensions . */
590	#define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
591	/** EBX Bit 3 - BMI1 - Advanced Bit Manipulation extension 1. */
592	#define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
593	/** EBX Bit 4 - HLE - Hardware Lock Elision. */
594	#define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
595	/** EBX Bit 5 - AVX2 - Advanced Vector Extensions 2. */
596	#define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
597	/** EBX Bit 6 - FDP_EXCPTN_ONLY - FPU data pointer only updated on exceptions if set. */
598	#define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
599	/** EBX Bit 7 - SMEP - Supervisor Mode Execution Prevention. */
600	#define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
601	/** EBX Bit 8 - BMI2 - Advanced Bit Manipulation extension 2. */
602	#define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
603	/** EBX Bit 9 - ERMS - Supports Enhanced REP MOVSB/STOSB. */
604	#define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
605	/** EBX Bit 10 - INVPCID - Supports INVPCID. */
606	#define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
607	/** EBX Bit 11 - RTM - Supports Restricted Transactional Memory. */
608	#define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
609	/** EBX Bit 12 - PQM - Supports Platform Quality of Service Monitoring. */
610	#define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
611	/** EBX Bit 13 - DEPFPU_CS_DS - Deprecates FPU CS, FPU DS values if set. */
612	#define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
613	/** EBX Bit 14 - MPE - Supports Intel Memory Protection Extensions. */
614	#define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
615	/** EBX Bit 15 - PQE - Supports Platform Quality of Service Enforcement. */
616	#define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
617	/** EBX Bit 16 - AVX512F - Supports AVX512F. */
618	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
619	/** EBX Bit 18 - RDSEED - Supports RDSEED. */
620	#define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
621	/** EBX Bit 19 - ADX - Supports ADCX/ADOX. */
622	#define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
623	/** EBX Bit 20 - SMAP - Supports Supervisor Mode Access Prevention. */
624	#define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
625	/** EBX Bit 23 - CLFLUSHOPT - Supports CLFLUSHOPT (Cache Line Flush). */
626	#define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
627	/** EBX Bit 25 - INTEL_PT - Supports Intel Processor Trace. */
628	#define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
629	/** EBX Bit 26 - AVX512PF - Supports AVX512PF. */
630	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
631	/** EBX Bit 27 - AVX512ER - Supports AVX512ER. */
632	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
633	/** EBX Bit 28 - AVX512CD - Supports AVX512CD. */
634	#define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
635	/** EBX Bit 29 - SHA - Supports Secure Hash Algorithm extensions. */
636	#define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
637
638	/** ECX Bit 0 - PREFETCHWT1 - Supports the PREFETCHWT1 instruction. */
639	#define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
640	/** ECX Bit 2 - UIMP - Supports user mode instruction prevention. */
641	#define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
642	/** ECX Bit 3 - PKU - Supports protection keys for user-mode pages. */
643	#define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
644	/** ECX Bit 4 - OSPKE - Protection keys for user mode pages enabled. */
645	#define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
646	/** ECX Bits 17-21 - MAWAU - Value used by BNDLDX and BNDSTX. */
647	#define X86_CPUID_STEXT_FEATURE_ECX_MAWAU UINT32_C(0x003e0000)
648	/** ECX Bit 22 - RDPID - Support pread process ID. */
649	#define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
650	/** ECX Bit 30 - SGX_LC - Supports SGX launch configuration. */
651	#define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
652
653	/** EDX Bit 10 - MD_CLEAR - Supports flushing MDS related buffers. */
654	#define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
655	/** EDX Bit 26 - IBRS & IBPB - Supports the IBRS flag in IA32_SPEC_CTRL and
656	* IBPB command in IA32_PRED_CMD. */
657	#define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
658	/** EDX Bit 27 - IBRS & IBPB - Supports the STIBP flag in IA32_SPEC_CTRL. */
659	#define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
660	/** EDX Bit 28 - FLUSH_CMD - Supports IA32_FLUSH_CMD MSR. */
661	#define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
662	/** EDX Bit 29 - ARCHCAP - Supports the IA32_ARCH_CAPABILITIES MSR. */
663	#define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
664	/** EDX Bit 31 - SSBD - Supports the SSBD flag in IA32_SPEC_CTRL. */
665	#define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
666
667	/** @} */
668
669
670	/** @name CPUID Extended Feature information.
671	* CPUID query with EAX=0x80000001.
672	* @{
673	*/
674	/** ECX Bit 0 - LAHF/SAHF support in 64-bit mode. */
675	#define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
676
677	/** EDX Bit 11 - SYSCALL/SYSRET. */
678	#define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
679	/** EDX Bit 20 - No-Execute/Execute-Disable. */
680	#define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
681	/** EDX Bit 26 - 1 GB large page. */
682	#define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
683	/** EDX Bit 27 - RDTSCP. */
684	#define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
685	/** EDX Bit 29 - AMD Long Mode/Intel-64 Instructions. */
686	#define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
687	/** @}*/
688
689	/** @name CPUID AMD Feature information.
690	* CPUID query with EAX=0x80000001.
691	* @{
692	*/
693	/** Bit 0 - FPU - x87 FPU on Chip. */
694	#define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
695	/** Bit 1 - VME - Virtual 8086 Mode Enhancements. */
696	#define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
697	/** Bit 2 - DE - Debugging extensions. */
698	#define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
699	/** Bit 3 - PSE - Page Size Extension. */
700	#define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
701	/** Bit 4 - TSC - Time Stamp Counter. */
702	#define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
703	/** Bit 5 - MSR - K86 Model Specific Registers RDMSR and WRMSR Instructions. */
704	#define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
705	/** Bit 6 - PAE - Physical Address Extension. */
706	#define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
707	/** Bit 7 - MCE - Machine Check Exception. */
708	#define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
709	/** Bit 8 - CX8 - CMPXCHG8B instruction. */
710	#define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
711	/** Bit 9 - APIC - APIC On-Chip. */
712	#define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
713	/** Bit 12 - MTRR - Memory Type Range Registers. */
714	#define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
715	/** Bit 13 - PGE - PTE Global Bit. */
716	#define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
717	/** Bit 14 - MCA - Machine Check Architecture. */
718	#define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
719	/** Bit 15 - CMOV - Conditional Move Instructions. */
720	#define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
721	/** Bit 16 - PAT - Page Attribute Table. */
722	#define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
723	/** Bit 17 - PSE-36 - 36-bit Page Size Extension. */
724	#define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
725	/** Bit 22 - AXMMX - AMD Extensions to MMX Instructions. */
726	#define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
727	/** Bit 23 - MMX - Intel MMX Technology. */
728	#define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
729	/** Bit 24 - FXSR - FXSAVE and FXRSTOR Instructions. */
730	#define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
731	/** Bit 25 - FFXSR - AMD fast FXSAVE and FXRSTOR Instructions. */
732	#define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
733	/** Bit 30 - 3DNOWEXT - AMD Extensions to 3DNow. */
734	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
735	/** Bit 31 - 3DNOW - AMD 3DNow. */
736	#define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
737
738	/** Bit 1 - CmpLegacy - Core multi-processing legacy mode. */
739	#define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
740	/** Bit 2 - SVM - AMD VM extensions. */
741	#define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
742	/** Bit 3 - EXTAPIC - AMD extended APIC registers starting at 0x400. */
743	#define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
744	/** Bit 4 - CR8L - AMD LOCK MOV CR0 means MOV CR8. */
745	#define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
746	/** Bit 5 - ABM - AMD Advanced bit manipulation. LZCNT instruction support. */
747	#define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
748	/** Bit 6 - SSE4A - AMD EXTRQ, INSERTQ, MOVNTSS, and MOVNTSD instruction support. */
749	#define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
750	/** Bit 7 - MISALIGNSSE - AMD Misaligned SSE mode. */
751	#define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
752	/** Bit 8 - 3DNOWPRF - AMD PREFETCH and PREFETCHW instruction support. */
753	#define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
754	/** Bit 9 - OSVW - AMD OS visible workaround. */
755	#define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
756	/** Bit 10 - IBS - Instruct based sampling. */
757	#define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
758	/** Bit 11 - XOP - Extended operation support (see APM6). */
759	#define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
760	/** Bit 12 - SKINIT - AMD SKINIT: SKINIT, STGI, and DEV support. */
761	#define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
762	/** Bit 13 - WDT - AMD Watchdog timer support. */
763	#define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
764	/** Bit 15 - LWP - Lightweight profiling support. */
765	#define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
766	/** Bit 16 - FMA4 - Four operand FMA instruction support. */
767	#define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
768	/** Bit 19 - NodeId - Indicates support for
769	* MSR_C001_100C[NodeId,NodesPerProcessr]. */
770	#define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
771	/** Bit 21 - TBM - Trailing bit manipulation instruction support. */
772	#define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
773	/** Bit 22 - TopologyExtensions - . */
774	#define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
775	/** @} */
776
777
778	/** @name CPUID AMD Feature information.
779	* CPUID query with EAX=0x80000007.
780	* @{
781	*/
782	/** Bit 0 - TS - Temperature Sensor. */
783	#define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
784	/** Bit 1 - FID - Frequency ID Control. */
785	#define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
786	/** Bit 2 - VID - Voltage ID Control. */
787	#define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
788	/** Bit 3 - TTP - THERMTRIP. */
789	#define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
790	/** Bit 4 - TM - Hardware Thermal Control. */
791	#define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
792	/** Bit 5 - STC - Software Thermal Control. */
793	#define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
794	/** Bit 6 - MC - 100 Mhz Multiplier Control. */
795	#define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
796	/** Bit 7 - HWPSTATE - Hardware P-State Control. */
797	#define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
798	/** Bit 8 - TSCINVAR - TSC Invariant. */
799	#define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
800	/** Bit 9 - CPB - TSC Invariant. */
801	#define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
802	/** Bit 10 - EffFreqRO - MPERF/APERF. */
803	#define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
804	/** Bit 11 - PFI - Processor feedback interface (see EAX). */
805	#define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
806	/** Bit 12 - PA - Processor accumulator (MSR c001_007a). */
807	#define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
808	/** @} */
809
810
811	/** @name CPUID AMD extended feature extensions ID (EBX).
812	* CPUID query with EAX=0x80000008.
813	* @{
814	*/
815	/** Bit 0 - CLZERO - Clear zero instruction. */
816	#define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
817	/** Bit 1 - IRPerf - Instructions retired count support. */
818	#define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
819	/** Bit 2 - XSaveErPtr - Always XSAVE* and XRSTR* error pointers. */
820	#define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
821	/** Bit 4 - RDPRU - Supports the RDPRU instruction. */
822	#define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
823	/** Bit 8 - MCOMMIT - Supports the MCOMMIT instruction. */
824	#define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
825	/* AMD pipeline length: 9 feature bits ;-) */
826	/** Bit 12 - IBPB - Supports the IBPB command in IA32_PRED_CMD. */
827	#define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
828	/** Bit 14 - IBRS - Supports the IBRS bit in IA32_SPEC_CTRL. */
829	#define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
830	/** Bit 15 - STIBP - Supports the STIBP bit in IA32_SPEC_CTRL. */
831	#define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
832	/** Bit 16 - IBRS always on mode - IBRS should be set once during boot only. */
833	#define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
834	/** Bit 17 - STIBP always on mode - STIBP should be set once during boot only. */
835	#define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
836	/** Bit 18 - IBRS preferred - IBRS is preferred over software mitigations. */
837	#define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
838	/** Bit 24 - Speculative Store Bypass Disable supported in SPEC_CTL. */
839	#define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
840	/** Bit 25 - Speculative Store Bypass Disable supported in VIRT_SPEC_CTL. */
841	#define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
842	/** Bit 26 - Speculative Store Bypass Disable not required. */
843	#define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
844	/** @} */
845
846
847	/** @name CPUID AMD SVM Feature information.
848	* CPUID query with EAX=0x8000000a.
849	* @{
850	*/
851	/** Bit 0 - NP - Nested Paging supported. */
852	#define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
853	/** Bit 1 - LbrVirt - Support for saving five debug MSRs. */
854	#define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
855	/** Bit 2 - SVML - SVM locking bit supported. */
856	#define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
857	/** Bit 3 - NRIPS - Saving the next instruction pointer is supported. */
858	#define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
859	/** Bit 4 - TscRateMsr - Support for MSR TSC ratio. */
860	#define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
861	/** Bit 5 - VmcbClean - Support VMCB clean bits. */
862	#define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
863	/** Bit 6 - FlushByAsid - Indicate TLB flushing for current ASID only, and that
864	* VMCB.TLB_Control is supported. */
865	#define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
866	/** Bit 7 - DecodeAssists - Indicate decode assists is supported. */
867	#define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
868	/** Bit 10 - PauseFilter - Indicates support for the PAUSE intercept filter. */
869	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
870	/** Bit 12 - PauseFilterThreshold - Indicates support for the PAUSE
871	* intercept filter cycle count threshold. */
872	#define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
873	/** Bit 13 - AVIC - Advanced Virtual Interrupt Controller. */
874	#define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
875	/** Bit 15 - VMSAVEvirt - Supports virtualized VMSAVE/VMLOAD. */
876	#define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
877	/** Bit 16 - VGIF - Supports virtualized GIF. */
878	#define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
879	/** Bit 17 - GMET - Supports Guest Mode Execute Trap Extensions. */
880	#define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
881	/** Bit 19 - SSSCheck - SVM supervisor shadow stack restrictions. */
882	#define X86_CPUID_SVM_FEATURE_EDX_SSSCHECK RT_BIT(19)
883	/** Bit 20 - SpecCtrl - Supports SPEC_CTRL Virtualization. */
884	#define X86_CPUID_SVM_FEATURE_EDX_SPEC_CTRL RT_BIT(20)
885	/** Bit 23 - HOST_MCE_OVERRIDE - Supports host \#MC exception override. */
886	#define X86_CPUID_SVM_FEATURE_EDX_HOST_MCE_OVERRIDE RT_BIT(23)
887	/** Bit 24 - TlbiCtl - Supports INVLPGB/TLBSYNC in VMCB and TLBSYNC intercept. */
888	#define X86_CPUID_SVM_FEATURE_EDX_TLBICTL RT_BIT(24)
889	/** @} */
890
891
892	/** @name CR0
893	* @remarks The 286 (MSW), 386 and 486 ignores attempts at setting
894	* reserved flags.
895	* @{ */
896	/** Bit 0 - PE - Protection Enabled */
897	#define X86_CR0_PE RT_BIT_32(0)
898	#define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
899	/** Bit 1 - MP - Monitor Coprocessor */
900	#define X86_CR0_MP RT_BIT_32(1)
901	#define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
902	/** Bit 2 - EM - Emulation. */
903	#define X86_CR0_EM RT_BIT_32(2)
904	#define X86_CR0_EMULATE_FPU RT_BIT_32(2)
905	/** Bit 3 - TS - Task Switch. */
906	#define X86_CR0_TS RT_BIT_32(3)
907	#define X86_CR0_TASK_SWITCH RT_BIT_32(3)
908	/** Bit 4 - ET - Extension flag. (386, 'hardcoded' to 1 on 486+) */
909	#define X86_CR0_ET RT_BIT_32(4)
910	#define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
911	/** Bit 5 - NE - Numeric error (486+). */
912	#define X86_CR0_NE RT_BIT_32(5)
913	#define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
914	/** Bit 16 - WP - Write Protect (486+). */
915	#define X86_CR0_WP RT_BIT_32(16)
916	#define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
917	/** Bit 18 - AM - Alignment Mask (486+). */
918	#define X86_CR0_AM RT_BIT_32(18)
919	#define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
920	/** Bit 29 - NW - Not Write-though (486+). */
921	#define X86_CR0_NW RT_BIT_32(29)
922	#define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
923	/** Bit 30 - WP - Cache Disable (486+). */
924	#define X86_CR0_CD RT_BIT_32(30)
925	#define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
926	/** Bit 31 - PG - Paging. */
927	#define X86_CR0_PG RT_BIT_32(31)
928	#define X86_CR0_PAGING RT_BIT_32(31)
929	#define X86_CR0_BIT_PG 31 /*< Bit number of X86_CR0_PG /
930	/** @} */
931
932
933	/** @name CR3
934	* @{ */
935	/** Bit 3 - PWT - Page-level Writes Transparent. */
936	#define X86_CR3_PWT RT_BIT_32(3)
937	/** Bit 4 - PCD - Page-level Cache Disable. */
938	#define X86_CR3_PCD RT_BIT_32(4)
939	/** Bits 12-31 - - Page directory page number. */
940	#define X86_CR3_PAGE_MASK (0xfffff000)
941	/** Bits 5-31 - - PAE Page directory page number. */
942	#define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
943	/** Bits 12-51 - - AMD64 PML4 page number.
944	* @note This is a maxed out mask, the actual acceptable CR3 value can
945	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
946	#define X86_CR3_AMD64_PAGE_MASK UINT64_C(0x000ffffffffff000)
947	/** Bits 12-51 - - Intel EPT PML4 page number (EPTP).
948	* @note This is a maxed out mask, the actual acceptable CR3/EPTP value can
949	* be lower depending on the PhysAddrSize from CPUID Fn8000_0008. */
950	#define X86_CR3_EPT_PAGE_MASK UINT64_C(0x000ffffffffff000)
951	/** @} */
952
953
954	/** @name CR4
955	* @{ */
956	/** Bit 0 - VME - Virtual-8086 Mode Extensions. */
957	#define X86_CR4_VME RT_BIT_32(0)
958	/** Bit 1 - PVI - Protected-Mode Virtual Interrupts. */
959	#define X86_CR4_PVI RT_BIT_32(1)
960	/** Bit 2 - TSD - Time Stamp Disable. */
961	#define X86_CR4_TSD RT_BIT_32(2)
962	/** Bit 3 - DE - Debugging Extensions. */
963	#define X86_CR4_DE RT_BIT_32(3)
964	/** Bit 4 - PSE - Page Size Extension. */
965	#define X86_CR4_PSE RT_BIT_32(4)
966	/** Bit 5 - PAE - Physical Address Extension. */
967	#define X86_CR4_PAE RT_BIT_32(5)
968	/** Bit 6 - MCE - Machine-Check Enable. */
969	#define X86_CR4_MCE RT_BIT_32(6)
970	/** Bit 7 - PGE - Page Global Enable. */
971	#define X86_CR4_PGE RT_BIT_32(7)
972	/** Bit 8 - PCE - Performance-Monitoring Counter Enable. */
973	#define X86_CR4_PCE RT_BIT_32(8)
974	/** Bit 9 - OSFXSR - Operating System Support for FXSAVE and FXRSTORE instructions. */
975	#define X86_CR4_OSFXSR RT_BIT_32(9)
976	/** Bit 10 - OSXMMEEXCPT - Operating System Support for Unmasked SIMD Floating-Point Exceptions. */
977	#define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
978	/** Bit 11 - UMIP - User-Mode Instruction Prevention. */
979	#define X86_CR4_UMIP RT_BIT_32(11)
980	/** Bit 13 - VMXE - VMX mode is enabled. */
981	#define X86_CR4_VMXE RT_BIT_32(13)
982	/** Bit 14 - SMXE - Safer Mode Extensions Enabled. */
983	#define X86_CR4_SMXE RT_BIT_32(14)
984	/** Bit 16 - FSGSBASE - Read/write FSGSBASE instructions Enable. */
985	#define X86_CR4_FSGSBASE RT_BIT_32(16)
986	/** Bit 17 - PCIDE - Process-Context Identifiers Enabled. */
987	#define X86_CR4_PCIDE RT_BIT_32(17)
988	/** Bit 18 - OSXSAVE - Operating System Support for XSAVE and processor
989	* extended states. */
990	#define X86_CR4_OSXSAVE RT_BIT_32(18)
991	/** Bit 20 - SMEP - Supervisor-mode Execution Prevention enabled. */
992	#define X86_CR4_SMEP RT_BIT_32(20)
993	/** Bit 21 - SMAP - Supervisor-mode Access Prevention enabled. */
994	#define X86_CR4_SMAP RT_BIT_32(21)
995	/** Bit 22 - PKE - Protection Key Enable. */
996	#define X86_CR4_PKE RT_BIT_32(22)
997	/** Bit 23 - CET - Control-flow Enhancement Technology enabled. */
998	#define X86_CR4_CET RT_BIT_32(23)
999	/** @} */
1000
1001
1002	/** @name DR6
1003	* @{ */
1004	/** Bit 0 - B0 - Breakpoint 0 condition detected. */
1005	#define X86_DR6_B0 RT_BIT_32(0)
1006	/** Bit 1 - B1 - Breakpoint 1 condition detected. */
1007	#define X86_DR6_B1 RT_BIT_32(1)
1008	/** Bit 2 - B2 - Breakpoint 2 condition detected. */
1009	#define X86_DR6_B2 RT_BIT_32(2)
1010	/** Bit 3 - B3 - Breakpoint 3 condition detected. */
1011	#define X86_DR6_B3 RT_BIT_32(3)
1012	/** Mask of all the Bx bits. */
1013	#define X86_DR6_B_MASK UINT64_C(0x0000000f)
1014	/** Bit 13 - BD - Debug register access detected. Corresponds to the X86_DR7_GD bit. */
1015	#define X86_DR6_BD RT_BIT_32(13)
1016	/** Bit 14 - BS - Single step */
1017	#define X86_DR6_BS RT_BIT_32(14)
1018	/** Bit 15 - BT - Task switch. (TSS T bit.) */
1019	#define X86_DR6_BT RT_BIT_32(15)
1020	/** Bit 16 - RTM - Cleared if debug exception inside RTM (@sa X86_DR7_RTM). */
1021	#define X86_DR6_RTM RT_BIT_32(16)
1022	/** Value of DR6 after powerup/reset. */
1023	#define X86_DR6_INIT_VAL UINT64_C(0xffff0ff0)
1024	/** Bits which must be 1s in DR6. */
1025	#define X86_DR6_RA1_MASK UINT64_C(0xffff0ff0)
1026	/** Bits which must be 1s in DR6, when RTM is supported. */
1027	#define X86_DR6_RA1_MASK_RTM UINT64_C(0xfffe0ff0)
1028	/** Bits which must be 0s in DR6. */
1029	#define X86_DR6_RAZ_MASK RT_BIT_64(12)
1030	/** Bits which must be 0s on writes to DR6. */
1031	#define X86_DR6_MBZ_MASK UINT64_C(0xffffffff00000000)
1032	/** @} */
1033
1034	/** Get the DR6.Bx bit for a the given breakpoint. */
1035	#define X86_DR6_B(iBp) RT_BIT_64(iBp)
1036
1037
1038	/** @name DR7
1039	* @{ */
1040	/** Bit 0 - L0 - Local breakpoint enable. Cleared on task switch. */
1041	#define X86_DR7_L0 RT_BIT_32(0)
1042	/** Bit 1 - G0 - Global breakpoint enable. Not cleared on task switch. */
1043	#define X86_DR7_G0 RT_BIT_32(1)
1044	/** Bit 2 - L1 - Local breakpoint enable. Cleared on task switch. */
1045	#define X86_DR7_L1 RT_BIT_32(2)
1046	/** Bit 3 - G1 - Global breakpoint enable. Not cleared on task switch. */
1047	#define X86_DR7_G1 RT_BIT_32(3)
1048	/** Bit 4 - L2 - Local breakpoint enable. Cleared on task switch. */
1049	#define X86_DR7_L2 RT_BIT_32(4)
1050	/** Bit 5 - G2 - Global breakpoint enable. Not cleared on task switch. */
1051	#define X86_DR7_G2 RT_BIT_32(5)
1052	/** Bit 6 - L3 - Local breakpoint enable. Cleared on task switch. */
1053	#define X86_DR7_L3 RT_BIT_32(6)
1054	/** Bit 7 - G3 - Global breakpoint enable. Not cleared on task switch. */
1055	#define X86_DR7_G3 RT_BIT_32(7)
1056	/** Bit 8 - LE - Local breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1057	#define X86_DR7_LE RT_BIT_32(8)
1058	/** Bit 9 - GE - Global breakpoint exact. (Not supported (read ignored) by P6 and later.) */
1059	#define X86_DR7_GE RT_BIT_32(9)
1060
1061	/** L0, L1, L2, and L3. */
1062	#define X86_DR7_LE_ALL UINT64_C(0x0000000000000055)
1063	/** L0, L1, L2, and L3. */
1064	#define X86_DR7_GE_ALL UINT64_C(0x00000000000000aa)
1065
1066	/** Bit 11 - RTM - Enable advanced debugging of RTM transactions.
1067	* Requires IA32_DEBUGCTL.RTM=1 too, and RTM HW support of course. */
1068	#define X86_DR7_RTM RT_BIT_32(11)
1069	/** Bit 12 - IR (ICE) - Interrupt redirection on Pentium. When set, the in
1070	* Circuit Emulator (ICE) will break emulation on breakpoints and stuff.
1071	* May cause CPU hang if enabled without ICE attached when the ICEBP/INT1
1072	* instruction is executed.
1073	* @see http://www.rcollins.org/secrets/DR7.html */
1074	#define X86_DR7_ICE_IR RT_BIT_32(12)
1075	/** Bit 13 - GD - General detect enable. Enables emulators to get exceptions when
1076	* any DR register is accessed. */
1077	#define X86_DR7_GD RT_BIT_32(13)
1078	/** Bit 14 - TR1 (ICE) - Code discontinuity trace for use with ICE on
1079	* Pentium. */
1080	#define X86_DR7_ICE_TR1 RT_BIT_32(14)
1081	/** Bit 15 - TR2 (ICE) - Controls unknown ICE trace feature of the pentium. */
1082	#define X86_DR7_ICE_TR2 RT_BIT_32(15)
1083	/** Bit 16 & 17 - R/W0 - Read write field 0. Values X86_DR7_RW_. /
1084	#define X86_DR7_RW0_MASK (3 << 16)
1085	/** Bit 18 & 19 - LEN0 - Length field 0. Values X86_DR7_LEN_. /
1086	#define X86_DR7_LEN0_MASK (3 << 18)
1087	/** Bit 20 & 21 - R/W1 - Read write field 0. Values X86_DR7_RW_. /
1088	#define X86_DR7_RW1_MASK (3 << 20)
1089	/** Bit 22 & 23 - LEN1 - Length field 0. Values X86_DR7_LEN_. /
1090	#define X86_DR7_LEN1_MASK (3 << 22)
1091	/** Bit 24 & 25 - R/W2 - Read write field 0. Values X86_DR7_RW_. /
1092	#define X86_DR7_RW2_MASK (3 << 24)
1093	/** Bit 26 & 27 - LEN2 - Length field 0. Values X86_DR7_LEN_. /
1094	#define X86_DR7_LEN2_MASK (3 << 26)
1095	/** Bit 28 & 29 - R/W3 - Read write field 0. Values X86_DR7_RW_. /
1096	#define X86_DR7_RW3_MASK (3 << 28)
1097	/** Bit 30 & 31 - LEN3 - Length field 0. Values X86_DR7_LEN_. /
1098	#define X86_DR7_LEN3_MASK (3 << 30)
1099
1100	/** Bits which reads as 1s. */
1101	#define X86_DR7_RA1_MASK RT_BIT_32(10)
1102	/** Bits which reads as zeros. These are related to ICE (bits 12, 14, 15). */
1103	#define X86_DR7_RAZ_MASK UINT64_C(0x0000d800)
1104	/** Bits which must be 0s when writing to DR7. */
1105	#define X86_DR7_MBZ_MASK UINT64_C(0xffffffff00000000)
1106
1107	/** Calcs the L bit of Nth breakpoint.
1108	* @param iBp The breakpoint number [0..3].
1109	*/
1110	#define X86_DR7_L(iBp) ( UINT32_C(1) << (iBp * 2) )
1111
1112	/** Calcs the G bit of Nth breakpoint.
1113	* @param iBp The breakpoint number [0..3].
1114	*/
1115	#define X86_DR7_G(iBp) ( UINT32_C(1) << (iBp * 2 + 1) )
1116
1117	/** Calcs the L and G bits of Nth breakpoint.
1118	* @param iBp The breakpoint number [0..3].
1119	*/
1120	#define X86_DR7_L_G(iBp) ( UINT32_C(3) << (iBp * 2) )
1121
1122	/** @name Read/Write values.
1123	* @{ */
1124	/** Break on instruction fetch only. */
1125	#define X86_DR7_RW_EO UINT32_C(0)
1126	/** Break on write only. */
1127	#define X86_DR7_RW_WO UINT32_C(1)
1128	/** Break on I/O read/write. This is only defined if CR4.DE is set. */
1129	#define X86_DR7_RW_IO UINT32_C(2)
1130	/** Break on read or write (but not instruction fetches). */
1131	#define X86_DR7_RW_RW UINT32_C(3)
1132	/** @} */
1133
1134	/** Shifts a X86_DR7_RW_* value to its right place.
1135	* @param iBp The breakpoint number [0..3].
1136	* @param fRw One of the X86_DR7_RW_* value.
1137	*/
1138	#define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
1139
1140	/** Fetch the R/Wx bits for a given breakpoint (so it can be compared with
1141	* one of the X86_DR7_RW_XXX constants).
1142	*
1143	* @returns X86_DR7_RW_XXX
1144	* @param uDR7 DR7 value
1145	* @param iBp The breakpoint number [0..3].
1146	*/
1147	#define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & UINT32_C(3) )
1148
1149	/** R/W0, R/W1, R/W2, and R/W3. */
1150	#define X86_DR7_RW_ALL_MASKS UINT32_C(0x33330000)
1151
1152	#ifndef VBOX_FOR_DTRACE_LIB
1153	/** Checks the RW and LEN fields are set up for an instruction breakpoint.
1154	* @note This does not check if it's enabled. */
1155	# define X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) ( ((a_uDR7) & (UINT32_C(0x000f0000) << ((a_iBp) * 4))) == 0 )
1156	/** Checks if an instruction breakpoint is enabled and configured correctly.
1157	* @sa X86_DR7_IS_EO_CFG, X86_DR7_ANY_EO_ENABLED */
1158	# define X86_DR7_IS_EO_ENABLED(a_uDR7, a_iBp) \
1159	( ((a_uDR7) & (UINT32_C(0x03) << ((a_iBp) * 2))) != 0 && X86_DR7_IS_EO_CFG(a_uDR7, a_iBp) )
1160	/** Checks if there are any instruction fetch breakpoint types configured in the
1161	* RW and LEN registers.
1162	* @sa X86_DR7_IS_EO_CFG, X86_DR7_IS_EO_ENABLED */
1163	# define X86_DR7_ANY_EO_ENABLED(a_uDR7) \
1164	( (((a_uDR7) & UINT32_C(0x03)) != 0 && ((a_uDR7) & UINT32_C(0x000f0000)) == 0) \
1165	\|\| (((a_uDR7) & UINT32_C(0x0c)) != 0 && ((a_uDR7) & UINT32_C(0x00f00000)) == 0) \
1166	\|\| (((a_uDR7) & UINT32_C(0x30)) != 0 && ((a_uDR7) & UINT32_C(0x0f000000)) == 0) \
1167	\|\| (((a_uDR7) & UINT32_C(0xc0)) != 0 && ((a_uDR7) & UINT32_C(0xf0000000)) == 0) )
1168
1169	/** Checks if there are any I/O breakpoint types configured in the RW
1170	* registers. Does NOT check if these are enabled, sorry. */
1171	# define X86_DR7_ANY_RW_IO(uDR7) \
1172	( ( UINT32_C(0x22220000) & (uDR7) ) /* any candidates? */ \
1173	&& ( ( (UINT32_C(0x22220000) & (uDR7) ) >> 1 ) & ~(uDR7) ) )
1174	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x33330000)) == 0);
1175	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x22220000)) == 1);
1176	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x32320000)) == 1);
1177	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x23230000)) == 1);
1178	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00000000)) == 0);
1179	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00010000)) == 0);
1180	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00020000)) == 1);
1181	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00030000)) == 0);
1182	AssertCompile(X86_DR7_ANY_RW_IO(UINT32_C(0x00040000)) == 0);
1183
1184	#endif /* !VBOX_FOR_DTRACE_LIB */
1185
1186	/** @name Length values.
1187	* @{ */
1188	#define X86_DR7_LEN_BYTE UINT32_C(0)
1189	#define X86_DR7_LEN_WORD UINT32_C(1)
1190	#define X86_DR7_LEN_QWORD UINT32_C(2) /*< AMD64 long mode only. /
1191	#define X86_DR7_LEN_DWORD UINT32_C(3)
1192	/** @} */
1193
1194	/** Shifts a X86_DR7_LEN_* value to its right place.
1195	* @param iBp The breakpoint number [0..3].
1196	* @param cb One of the X86_DR7_LEN_* values.
1197	*/
1198	#define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
1199
1200	/** Fetch the breakpoint length bits from the DR7 value.
1201	* @param uDR7 DR7 value
1202	* @param iBp The breakpoint number [0..3].
1203	*/
1204	#define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & UINT32_C(0x3) )
1205
1206	/** Mask used to check if any breakpoints are enabled. */
1207	#define X86_DR7_ENABLED_MASK UINT32_C(0x000000ff)
1208
1209	/** LEN0, LEN1, LEN2, and LEN3. */
1210	#define X86_DR7_LEN_ALL_MASKS UINT32_C(0xcccc0000)
1211	/** R/W0, R/W1, R/W2, R/W3,LEN0, LEN1, LEN2, and LEN3. */
1212	#define X86_DR7_RW_LEN_ALL_MASKS UINT32_C(0xffff0000)
1213
1214	/** Value of DR7 after powerup/reset. */
1215	#define X86_DR7_INIT_VAL 0x400
1216	/** @} */
1217
1218
1219	/** @name Machine Specific Registers
1220	* @{
1221	*/
1222	/** Machine check address register (P5). */
1223	#define MSR_P5_MC_ADDR UINT32_C(0x00000000)
1224	/** Machine check type register (P5). */
1225	#define MSR_P5_MC_TYPE UINT32_C(0x00000001)
1226	/** Time Stamp Counter. */
1227	#define MSR_IA32_TSC 0x10
1228	#define MSR_IA32_CESR UINT32_C(0x00000011)
1229	#define MSR_IA32_CTR0 UINT32_C(0x00000012)
1230	#define MSR_IA32_CTR1 UINT32_C(0x00000013)
1231
1232	#define MSR_IA32_PLATFORM_ID 0x17
1233
1234	#ifndef MSR_IA32_APICBASE /* qemu cpu.h kludge */
1235	# define MSR_IA32_APICBASE 0x1b
1236	/** Local APIC enabled. */
1237	# define MSR_IA32_APICBASE_EN RT_BIT_64(11)
1238	/** X2APIC enabled (requires the EN bit to be set). */
1239	# define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
1240	/** The processor is the boot strap processor (BSP). */
1241	# define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
1242	/** Minimum base address mask, consult CPUID leaf 0x80000008 for the actual
1243	* width. */
1244	# define MSR_IA32_APICBASE_BASE_MIN UINT64_C(0x0000000ffffff000)
1245	/** The default physical base address of the APIC. */
1246	# define MSR_IA32_APICBASE_ADDR UINT64_C(0x00000000fee00000)
1247	/** Gets the physical base address from the MSR. */
1248	# define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
1249	#endif
1250
1251	/** Undocumented intel MSR for reporting thread and core counts.
1252	* Judging from the XNU sources, it seems to be introduced in Nehalem. The
1253	* first 16 bits is the thread count. The next 16 bits the core count, except
1254	* on Westmere where it seems it's only the next 4 bits for some reason. */
1255	#define MSR_CORE_THREAD_COUNT 0x35
1256
1257	/** CPU Feature control. */
1258	#define MSR_IA32_FEATURE_CONTROL 0x3A
1259	/** Feature control - Lock MSR from writes (R/W0). */
1260	#define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
1261	/** Feature control - Enable VMX inside SMX operation (R/WL). */
1262	#define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
1263	/** Feature control - Enable VMX outside SMX operation (R/WL). */
1264	#define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
1265	/** Feature control - SENTER local functions enable (R/WL). */
1266	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
1267	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
1268	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
1269	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
1270	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
1271	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
1272	#define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
1273	/** Feature control - SENTER global enable (R/WL). */
1274	#define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
1275	/** Feature control - SGX launch control enable (R/WL). */
1276	#define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
1277	/** Feature control - SGX global enable (R/WL). */
1278	#define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
1279	/** Feature control - LMCE on (R/WL). */
1280	#define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
1281
1282	/** Per-processor TSC adjust MSR. */
1283	#define MSR_IA32_TSC_ADJUST 0x3B
1284
1285	/** Spectre control register.
1286	* Logical processor scope. Reset value 0, unaffected by SIPI & INIT. */
1287	#define MSR_IA32_SPEC_CTRL 0x48
1288	/** IBRS - Indirect branch restricted speculation. */
1289	#define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
1290	/** STIBP - Single thread indirect branch predictors. */
1291	#define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
1292	/** SSBD - Speculative Store Bypass Disable. */
1293	#define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2)
1294
1295	/** Prediction command register.
1296	* Write only, logical processor scope, no state since write only. */
1297	#define MSR_IA32_PRED_CMD 0x49
1298	/** IBPB - Indirect branch prediction barrie when written as 1. */
1299	#define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
1300
1301	/** BIOS update trigger (microcode update). */
1302	#define MSR_IA32_BIOS_UPDT_TRIG 0x79
1303
1304	/** BIOS update signature (microcode). */
1305	#define MSR_IA32_BIOS_SIGN_ID 0x8B
1306
1307	/** SMM monitor control. */
1308	#define MSR_IA32_SMM_MONITOR_CTL 0x9B
1309	/** SMM control - Valid. */
1310	#define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
1311	/** SMM control - VMXOFF unblocks SMI. */
1312	#define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
1313	/** SMM control - MSEG base physical address. */
1314	#define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & UINT64_C(0xfffff))
1315
1316	/** SMBASE - Base address of SMRANGE image (Read-only, SMM only). */
1317	#define MSR_IA32_SMBASE 0x9E
1318
1319	/** General performance counter no. 0. */
1320	#define MSR_IA32_PMC0 0xC1
1321	/** General performance counter no. 1. */
1322	#define MSR_IA32_PMC1 0xC2
1323	/** General performance counter no. 2. */
1324	#define MSR_IA32_PMC2 0xC3
1325	/** General performance counter no. 3. */
1326	#define MSR_IA32_PMC3 0xC4
1327	/** General performance counter no. 4. */
1328	#define MSR_IA32_PMC4 0xC5
1329	/** General performance counter no. 5. */
1330	#define MSR_IA32_PMC5 0xC6
1331	/** General performance counter no. 6. */
1332	#define MSR_IA32_PMC6 0xC7
1333	/** General performance counter no. 7. */
1334	#define MSR_IA32_PMC7 0xC8
1335
1336	/** Nehalem power control. */
1337	#define MSR_IA32_PLATFORM_INFO 0xCE
1338
1339	/** Get FSB clock status (Intel-specific). */
1340	#define MSR_IA32_FSB_CLOCK_STS 0xCD
1341
1342	/** C-State configuration control. Intel specific: Nehalem, Sandy Bridge. */
1343	#define MSR_PKG_CST_CONFIG_CONTROL UINT32_C(0x000000e2)
1344
1345	/** C0 Maximum Frequency Clock Count */
1346	#define MSR_IA32_MPERF 0xE7
1347	/** C0 Actual Frequency Clock Count */
1348	#define MSR_IA32_APERF 0xE8
1349
1350	/** MTRR Capabilities. */
1351	#define MSR_IA32_MTRR_CAP 0xFE
1352
1353	/** Architecture capabilities (bugfixes). */
1354	#define MSR_IA32_ARCH_CAPABILITIES UINT32_C(0x10a)
1355	/** CPU is no subject to meltdown problems. */
1356	#define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
1357	/** CPU has better IBRS and you can leave it on all the time. */
1358	#define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
1359	/** CPU has return stack buffer (RSB) override. */
1360	#define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
1361	/** Virtual machine monitors need not flush the level 1 data cache on VM entry.
1362	* This is also the case when MSR_IA32_ARCH_CAP_F_RDCL_NO is set. */
1363	#define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
1364	/** CPU does not suffer from MDS issues. */
1365	#define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
1366
1367	/** Flush command register. */
1368	#define MSR_IA32_FLUSH_CMD UINT32_C(0x10b)
1369	/** Flush the level 1 data cache when this bit is written. */
1370	#define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
1371
1372	/** Cache control/info. */
1373	#define MSR_BBL_CR_CTL3 UINT32_C(0x11e)
1374
1375	#ifndef MSR_IA32_SYSENTER_CS /* qemu cpu.h kludge */
1376	/** SYSENTER_CS - the R0 CS, indirectly giving R0 SS, R3 CS and R3 DS.
1377	* R0 SS == CS + 8
1378	* R3 CS == CS + 16
1379	* R3 SS == CS + 24
1380	*/
1381	#define MSR_IA32_SYSENTER_CS 0x174
1382	/** SYSENTER_ESP - the R0 ESP. */
1383	#define MSR_IA32_SYSENTER_ESP 0x175
1384	/** SYSENTER_EIP - the R0 EIP. */
1385	#define MSR_IA32_SYSENTER_EIP 0x176
1386	#endif
1387
1388	/** Machine Check Global Capabilities Register. */
1389	#define MSR_IA32_MCG_CAP 0x179
1390	/** Machine Check Global Status Register. */
1391	#define MSR_IA32_MCG_STATUS 0x17A
1392	/** Machine Check Global Control Register. */
1393	#define MSR_IA32_MCG_CTRL 0x17B
1394
1395	/** Page Attribute Table. */
1396	#define MSR_IA32_CR_PAT 0x277
1397	/** Default PAT MSR value on processor powerup / reset (see Intel spec. 11.12.4
1398	* "Programming the PAT", AMD spec. 7.8.2 "PAT Indexing") */
1399	#define MSR_IA32_CR_PAT_INIT_VAL UINT64_C(0x0007040600070406)
1400
1401	/** Performance event select MSRs. (Intel only) */
1402	#define MSR_IA32_PERFEVTSEL0 0x186
1403	#define MSR_IA32_PERFEVTSEL1 0x187
1404	#define MSR_IA32_PERFEVTSEL2 0x188
1405	#define MSR_IA32_PERFEVTSEL3 0x189
1406
1407	/** Flexible ratio, seems to be undocumented, used by XNU (tsc.c).
1408	* The 16th bit whether flex ratio is being used, in which case bits 15:8
1409	* holds a ratio that Apple takes for TSC granularity.
1410	*
1411	* @note This MSR conflicts the P4 MSR_MCG_R12 register. */
1412	#define MSR_FLEX_RATIO 0x194
1413	/** Performance state value and starting with Intel core more.
1414	* Apple uses the >=core features to determine TSC granularity on older CPUs. */
1415	#define MSR_IA32_PERF_STATUS 0x198
1416	#define MSR_IA32_PERF_CTL 0x199
1417	#define MSR_IA32_THERM_STATUS 0x19c
1418
1419	/** Offcore response event select registers. */
1420	#define MSR_OFFCORE_RSP_0 0x1a6
1421	#define MSR_OFFCORE_RSP_1 0x1a7
1422
1423	/** Enable misc. processor features (R/W). */
1424	#define MSR_IA32_MISC_ENABLE 0x1A0
1425	/** Enable fast-strings feature (for REP MOVS and REP STORS). */
1426	#define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
1427	/** Automatic Thermal Control Circuit Enable (R/W). */
1428	#define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
1429	/** Performance Monitoring Available (R). */
1430	#define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
1431	/** Branch Trace Storage Unavailable (R/O). */
1432	#define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
1433	/** Precise Event Based Sampling (PEBS) Unavailable (R/O). */
1434	#define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
1435	/** Enhanced Intel SpeedStep Technology Enable (R/W). */
1436	#define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
1437	/** If MONITOR/MWAIT is supported (R/W). */
1438	#define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
1439	/** Limit CPUID Maxval to 3 leafs (R/W). */
1440	#define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
1441	/** When set to 1, xTPR messages are disabled (R/W). */
1442	#define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
1443	/** When set to 1, the Execute Disable Bit feature (XD Bit) is disabled (R/W). */
1444	#define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
1445
1446	/** Trace/Profile Resource Control (R/W) */
1447	#define MSR_IA32_DEBUGCTL UINT32_C(0x000001d9)
1448	/** Last branch record. */
1449	#define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
1450	/** Branch trace flag (single step on branches). */
1451	#define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
1452	/** Performance monitoring pin control (AMD only). */
1453	#define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
1454	#define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
1455	#define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
1456	#define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
1457	/** Trace message enable (Intel only). */
1458	#define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
1459	/** Branch trace store (Intel only). */
1460	#define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
1461	/** Branch trace interrupt (Intel only). */
1462	#define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
1463	/** Branch trace off in privileged code (Intel only). */
1464	#define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
1465	/** Branch trace off in user code (Intel only). */
1466	#define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
1467	/** Freeze LBR on PMI flag (Intel only). */
1468	#define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
1469	/** Freeze PERFMON on PMI flag (Intel only). */
1470	#define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
1471	/** Freeze while SMM enabled (Intel only). */
1472	#define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
1473	/** Advanced debugging of RTM regions (Intel only). */
1474	#define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
1475	/** Debug control MSR valid bits (Intel only). */
1476	#define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR \| MSR_IA32_DEBUGCTL_BTF \| MSR_IA32_DEBUGCTL_TR \
1477	\| MSR_IA32_DEBUGCTL_BTS \| MSR_IA32_DEBUGCTL_BTINT \| MSR_IA32_DEBUGCTL_BTS_OFF_OS \
1478	\| MSR_IA32_DEBUGCTL_BTS_OFF_USER \| MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
1479	\| MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI \| MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
1480	\| MSR_IA32_DEBUGCTL_RTM)
1481
1482	/** @name Last branch registers for P4 and Xeon, models 0 thru 2.
1483	* @{ */
1484	#define MSR_P4_LASTBRANCH_0 0x1db
1485	#define MSR_P4_LASTBRANCH_1 0x1dc
1486	#define MSR_P4_LASTBRANCH_2 0x1dd
1487	#define MSR_P4_LASTBRANCH_3 0x1de
1488
1489	/** LBR Top-of-stack MSR (index to most recent record). */
1490	#define MSR_P4_LASTBRANCH_TOS 0x1da
1491	/** @} */
1492
1493	/** @name Last branch registers for Core 2 and related Xeons.
1494	* @{ */
1495	#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
1496	#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
1497	#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
1498	#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
1499
1500	#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
1501	#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
1502	#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
1503	#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
1504
1505	/** LBR Top-of-stack MSR (index to most recent record). */
1506	#define MSR_CORE2_LASTBRANCH_TOS 0x1c9
1507	/** @} */
1508
1509	/** @name Last branch registers.
1510	* @{ */
1511	#define MSR_LASTBRANCH_0_FROM_IP 0x680
1512	#define MSR_LASTBRANCH_1_FROM_IP 0x681
1513	#define MSR_LASTBRANCH_2_FROM_IP 0x682
1514	#define MSR_LASTBRANCH_3_FROM_IP 0x683
1515	#define MSR_LASTBRANCH_4_FROM_IP 0x684
1516	#define MSR_LASTBRANCH_5_FROM_IP 0x685
1517	#define MSR_LASTBRANCH_6_FROM_IP 0x686
1518	#define MSR_LASTBRANCH_7_FROM_IP 0x687
1519	#define MSR_LASTBRANCH_8_FROM_IP 0x688
1520	#define MSR_LASTBRANCH_9_FROM_IP 0x689
1521	#define MSR_LASTBRANCH_10_FROM_IP 0x68a
1522	#define MSR_LASTBRANCH_11_FROM_IP 0x68b
1523	#define MSR_LASTBRANCH_12_FROM_IP 0x68c
1524	#define MSR_LASTBRANCH_13_FROM_IP 0x68d
1525	#define MSR_LASTBRANCH_14_FROM_IP 0x68e
1526	#define MSR_LASTBRANCH_15_FROM_IP 0x68f
1527	#define MSR_LASTBRANCH_16_FROM_IP 0x690
1528	#define MSR_LASTBRANCH_17_FROM_IP 0x691
1529	#define MSR_LASTBRANCH_18_FROM_IP 0x692
1530	#define MSR_LASTBRANCH_19_FROM_IP 0x693
1531	#define MSR_LASTBRANCH_20_FROM_IP 0x694
1532	#define MSR_LASTBRANCH_21_FROM_IP 0x695
1533	#define MSR_LASTBRANCH_22_FROM_IP 0x696
1534	#define MSR_LASTBRANCH_23_FROM_IP 0x697
1535	#define MSR_LASTBRANCH_24_FROM_IP 0x698
1536	#define MSR_LASTBRANCH_25_FROM_IP 0x699
1537	#define MSR_LASTBRANCH_26_FROM_IP 0x69a
1538	#define MSR_LASTBRANCH_27_FROM_IP 0x69b
1539	#define MSR_LASTBRANCH_28_FROM_IP 0x69c
1540	#define MSR_LASTBRANCH_29_FROM_IP 0x69d
1541	#define MSR_LASTBRANCH_30_FROM_IP 0x69e
1542	#define MSR_LASTBRANCH_31_FROM_IP 0x69f
1543
1544	#define MSR_LASTBRANCH_0_TO_IP 0x6c0
1545	#define MSR_LASTBRANCH_1_TO_IP 0x6c1
1546	#define MSR_LASTBRANCH_2_TO_IP 0x6c2
1547	#define MSR_LASTBRANCH_3_TO_IP 0x6c3
1548	#define MSR_LASTBRANCH_4_TO_IP 0x6c4
1549	#define MSR_LASTBRANCH_5_TO_IP 0x6c5
1550	#define MSR_LASTBRANCH_6_TO_IP 0x6c6
1551	#define MSR_LASTBRANCH_7_TO_IP 0x6c7
1552	#define MSR_LASTBRANCH_8_TO_IP 0x6c8
1553	#define MSR_LASTBRANCH_9_TO_IP 0x6c9
1554	#define MSR_LASTBRANCH_10_TO_IP 0x6ca
1555	#define MSR_LASTBRANCH_11_TO_IP 0x6cb
1556	#define MSR_LASTBRANCH_12_TO_IP 0x6cc
1557	#define MSR_LASTBRANCH_13_TO_IP 0x6cd
1558	#define MSR_LASTBRANCH_14_TO_IP 0x6ce
1559	#define MSR_LASTBRANCH_15_TO_IP 0x6cf
1560	#define MSR_LASTBRANCH_16_TO_IP 0x6d0
1561	#define MSR_LASTBRANCH_17_TO_IP 0x6d1
1562	#define MSR_LASTBRANCH_18_TO_IP 0x6d2
1563	#define MSR_LASTBRANCH_19_TO_IP 0x6d3
1564	#define MSR_LASTBRANCH_20_TO_IP 0x6d4
1565	#define MSR_LASTBRANCH_21_TO_IP 0x6d5
1566	#define MSR_LASTBRANCH_22_TO_IP 0x6d6
1567	#define MSR_LASTBRANCH_23_TO_IP 0x6d7
1568	#define MSR_LASTBRANCH_24_TO_IP 0x6d8
1569	#define MSR_LASTBRANCH_25_TO_IP 0x6d9
1570	#define MSR_LASTBRANCH_26_TO_IP 0x6da
1571	#define MSR_LASTBRANCH_27_TO_IP 0x6db
1572	#define MSR_LASTBRANCH_28_TO_IP 0x6dc
1573	#define MSR_LASTBRANCH_29_TO_IP 0x6dd
1574	#define MSR_LASTBRANCH_30_TO_IP 0x6de
1575	#define MSR_LASTBRANCH_31_TO_IP 0x6df
1576
1577	#define MSR_LASTBRANCH_0_INFO 0xdc0
1578	#define MSR_LASTBRANCH_1_INFO 0xdc1
1579	#define MSR_LASTBRANCH_2_INFO 0xdc2
1580	#define MSR_LASTBRANCH_3_INFO 0xdc3
1581	#define MSR_LASTBRANCH_4_INFO 0xdc4
1582	#define MSR_LASTBRANCH_5_INFO 0xdc5
1583	#define MSR_LASTBRANCH_6_INFO 0xdc6
1584	#define MSR_LASTBRANCH_7_INFO 0xdc7
1585	#define MSR_LASTBRANCH_8_INFO 0xdc8
1586	#define MSR_LASTBRANCH_9_INFO 0xdc9
1587	#define MSR_LASTBRANCH_10_INFO 0xdca
1588	#define MSR_LASTBRANCH_11_INFO 0xdcb
1589	#define MSR_LASTBRANCH_12_INFO 0xdcc
1590	#define MSR_LASTBRANCH_13_INFO 0xdcd
1591	#define MSR_LASTBRANCH_14_INFO 0xdce
1592	#define MSR_LASTBRANCH_15_INFO 0xdcf
1593	#define MSR_LASTBRANCH_16_INFO 0xdd0
1594	#define MSR_LASTBRANCH_17_INFO 0xdd1
1595	#define MSR_LASTBRANCH_18_INFO 0xdd2
1596	#define MSR_LASTBRANCH_19_INFO 0xdd3
1597	#define MSR_LASTBRANCH_20_INFO 0xdd4
1598	#define MSR_LASTBRANCH_21_INFO 0xdd5
1599	#define MSR_LASTBRANCH_22_INFO 0xdd6
1600	#define MSR_LASTBRANCH_23_INFO 0xdd7
1601	#define MSR_LASTBRANCH_24_INFO 0xdd8
1602	#define MSR_LASTBRANCH_25_INFO 0xdd9
1603	#define MSR_LASTBRANCH_26_INFO 0xdda
1604	#define MSR_LASTBRANCH_27_INFO 0xddb
1605	#define MSR_LASTBRANCH_28_INFO 0xddc
1606	#define MSR_LASTBRANCH_29_INFO 0xddd
1607	#define MSR_LASTBRANCH_30_INFO 0xdde
1608	#define MSR_LASTBRANCH_31_INFO 0xddf
1609
1610	/** LBR branch tracking selection MSR. */
1611	#define MSR_LASTBRANCH_SELECT 0x1c8
1612	/** LBR Top-of-stack MSR (index to most recent record). */
1613	#define MSR_LASTBRANCH_TOS 0x1c9
1614	/** @} */
1615
1616	/** @name Last event record registers.
1617	* @{ */
1618	/** Last event record source IP register. */
1619	#define MSR_LER_FROM_IP 0x1dd
1620	/** Last event record destination IP register. */
1621	#define MSR_LER_TO_IP 0x1de
1622	/** @} */
1623
1624	/** Intel TSX (Transactional Synchronization Extensions) control MSR. */
1625	#define MSR_IA32_TSX_CTRL 0x122
1626
1627	/** Variable range MTRRs.
1628	* @{ */
1629	#define MSR_IA32_MTRR_PHYSBASE0 0x200
1630	#define MSR_IA32_MTRR_PHYSMASK0 0x201
1631	#define MSR_IA32_MTRR_PHYSBASE1 0x202
1632	#define MSR_IA32_MTRR_PHYSMASK1 0x203
1633	#define MSR_IA32_MTRR_PHYSBASE2 0x204
1634	#define MSR_IA32_MTRR_PHYSMASK2 0x205
1635	#define MSR_IA32_MTRR_PHYSBASE3 0x206
1636	#define MSR_IA32_MTRR_PHYSMASK3 0x207
1637	#define MSR_IA32_MTRR_PHYSBASE4 0x208
1638	#define MSR_IA32_MTRR_PHYSMASK4 0x209
1639	#define MSR_IA32_MTRR_PHYSBASE5 0x20a
1640	#define MSR_IA32_MTRR_PHYSMASK5 0x20b
1641	#define MSR_IA32_MTRR_PHYSBASE6 0x20c
1642	#define MSR_IA32_MTRR_PHYSMASK6 0x20d
1643	#define MSR_IA32_MTRR_PHYSBASE7 0x20e
1644	#define MSR_IA32_MTRR_PHYSMASK7 0x20f
1645	#define MSR_IA32_MTRR_PHYSBASE8 0x210
1646	#define MSR_IA32_MTRR_PHYSMASK8 0x211
1647	#define MSR_IA32_MTRR_PHYSBASE9 0x212
1648	#define MSR_IA32_MTRR_PHYSMASK9 0x213
1649	/** @} */
1650
1651	/** Fixed range MTRRs.
1652	* @{ */
1653	#define MSR_IA32_MTRR_FIX64K_00000 0x250
1654	#define MSR_IA32_MTRR_FIX16K_80000 0x258
1655	#define MSR_IA32_MTRR_FIX16K_A0000 0x259
1656	#define MSR_IA32_MTRR_FIX4K_C0000 0x268
1657	#define MSR_IA32_MTRR_FIX4K_C8000 0x269
1658	#define MSR_IA32_MTRR_FIX4K_D0000 0x26a
1659	#define MSR_IA32_MTRR_FIX4K_D8000 0x26b
1660	#define MSR_IA32_MTRR_FIX4K_E0000 0x26c
1661	#define MSR_IA32_MTRR_FIX4K_E8000 0x26d
1662	#define MSR_IA32_MTRR_FIX4K_F0000 0x26e
1663	#define MSR_IA32_MTRR_FIX4K_F8000 0x26f
1664	/** @} */
1665
1666	/** MTRR Default Range. */
1667	#define MSR_IA32_MTRR_DEF_TYPE 0x2FF
1668
1669	/** Global performance counter control facilities (Intel only). */
1670	#define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
1671	#define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
1672	#define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
1673
1674	/** Precise Event Based sampling (Intel only). */
1675	#define MSR_IA32_PEBS_ENABLE 0x3F1
1676
1677	#define MSR_IA32_MC0_CTL 0x400
1678	#define MSR_IA32_MC0_STATUS 0x401
1679
1680	/** Basic VMX information. */
1681	#define MSR_IA32_VMX_BASIC 0x480
1682	/** Allowed settings for pin-based VM execution controls. */
1683	#define MSR_IA32_VMX_PINBASED_CTLS 0x481
1684	/** Allowed settings for proc-based VM execution controls. */
1685	#define MSR_IA32_VMX_PROCBASED_CTLS 0x482
1686	/** Allowed settings for the VM-exit controls. */
1687	#define MSR_IA32_VMX_EXIT_CTLS 0x483
1688	/** Allowed settings for the VM-entry controls. */
1689	#define MSR_IA32_VMX_ENTRY_CTLS 0x484
1690	/** Misc VMX info. */
1691	#define MSR_IA32_VMX_MISC 0x485
1692	/** Fixed cleared bits in CR0. */
1693	#define MSR_IA32_VMX_CR0_FIXED0 0x486
1694	/** Fixed set bits in CR0. */
1695	#define MSR_IA32_VMX_CR0_FIXED1 0x487
1696	/** Fixed cleared bits in CR4. */
1697	#define MSR_IA32_VMX_CR4_FIXED0 0x488
1698	/** Fixed set bits in CR4. */
1699	#define MSR_IA32_VMX_CR4_FIXED1 0x489
1700	/** Information for enumerating fields in the VMCS. */
1701	#define MSR_IA32_VMX_VMCS_ENUM 0x48A
1702	/** Allowed settings for secondary processor-based VM-execution controls. */
1703	#define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
1704	/** EPT capabilities. */
1705	#define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
1706	/** Allowed settings of all pin-based VM execution controls. */
1707	#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
1708	/** Allowed settings of all proc-based VM execution controls. */
1709	#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
1710	/** Allowed settings of all VMX exit controls. */
1711	#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
1712	/** Allowed settings of all VMX entry controls. */
1713	#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
1714	/** Allowed settings for the VM-function controls. */
1715	#define MSR_IA32_VMX_VMFUNC 0x491
1716	/** Tertiary processor-based VM execution controls. */
1717	#define MSR_IA32_VMX_PROCBASED_CTLS3 0x492
1718	/** Secondary VM-exit controls. */
1719	#define MSR_IA32_VMX_EXIT_CTLS2 0x493
1720
1721	/** Intel PT - Enable and control for trace packet generation. */
1722	#define MSR_IA32_RTIT_CTL 0x570
1723
1724	/** DS Save Area (R/W). */
1725	#define MSR_IA32_DS_AREA 0x600
1726	/** Running Average Power Limit (RAPL) power units. */
1727	#define MSR_RAPL_POWER_UNIT 0x606
1728	/** Package C3 Interrupt Response Limit. */
1729	#define MSR_PKGC3_IRTL 0x60a
1730	/** Package C6/C7S Interrupt Response Limit 1. */
1731	#define MSR_PKGC_IRTL1 0x60b
1732	/** Package C6/C7S Interrupt Response Limit 2. */
1733	#define MSR_PKGC_IRTL2 0x60c
1734	/** Package C2 Residency Counter. */
1735	#define MSR_PKG_C2_RESIDENCY 0x60d
1736	/** PKG RAPL Power Limit Control. */
1737	#define MSR_PKG_POWER_LIMIT 0x610
1738	/** PKG Energy Status. */
1739	#define MSR_PKG_ENERGY_STATUS 0x611
1740	/** PKG Perf Status. */
1741	#define MSR_PKG_PERF_STATUS 0x613
1742	/** PKG RAPL Parameters. */
1743	#define MSR_PKG_POWER_INFO 0x614
1744	/** DRAM RAPL Power Limit Control. */
1745	#define MSR_DRAM_POWER_LIMIT 0x618
1746	/** DRAM Energy Status. */
1747	#define MSR_DRAM_ENERGY_STATUS 0x619
1748	/** DRAM Performance Throttling Status. */
1749	#define MSR_DRAM_PERF_STATUS 0x61b
1750	/** DRAM RAPL Parameters. */
1751	#define MSR_DRAM_POWER_INFO 0x61c
1752	/** Package C10 Residency Counter. */
1753	#define MSR_PKG_C10_RESIDENCY 0x632
1754	/** PP0 Energy Status. */
1755	#define MSR_PP0_ENERGY_STATUS 0x639
1756	/** PP1 Energy Status. */
1757	#define MSR_PP1_ENERGY_STATUS 0x641
1758	/** Turbo Activation Ratio. */
1759	#define MSR_TURBO_ACTIVATION_RATIO 0x64c
1760	/** Core Performance Limit Reasons. */
1761	#define MSR_CORE_PERF_LIMIT_REASONS 0x64f
1762
1763	/** X2APIC MSR range start. */
1764	#define MSR_IA32_X2APIC_START 0x800
1765	/** X2APIC MSR - APIC ID Register. */
1766	#define MSR_IA32_X2APIC_ID 0x802
1767	/** X2APIC MSR - APIC Version Register. */
1768	#define MSR_IA32_X2APIC_VERSION 0x803
1769	/** X2APIC MSR - Task Priority Register. */
1770	#define MSR_IA32_X2APIC_TPR 0x808
1771	/** X2APIC MSR - Processor Priority register. */
1772	#define MSR_IA32_X2APIC_PPR 0x80A
1773	/** X2APIC MSR - End Of Interrupt register. */
1774	#define MSR_IA32_X2APIC_EOI 0x80B
1775	/** X2APIC MSR - Logical Destination Register. */
1776	#define MSR_IA32_X2APIC_LDR 0x80D
1777	/** X2APIC MSR - Spurious Interrupt Vector Register. */
1778	#define MSR_IA32_X2APIC_SVR 0x80F
1779	/** X2APIC MSR - In-service Register (bits 31:0). */
1780	#define MSR_IA32_X2APIC_ISR0 0x810
1781	/** X2APIC MSR - In-service Register (bits 63:32). */
1782	#define MSR_IA32_X2APIC_ISR1 0x811
1783	/** X2APIC MSR - In-service Register (bits 95:64). */
1784	#define MSR_IA32_X2APIC_ISR2 0x812
1785	/** X2APIC MSR - In-service Register (bits 127:96). */
1786	#define MSR_IA32_X2APIC_ISR3 0x813
1787	/** X2APIC MSR - In-service Register (bits 159:128). */
1788	#define MSR_IA32_X2APIC_ISR4 0x814
1789	/** X2APIC MSR - In-service Register (bits 191:160). */
1790	#define MSR_IA32_X2APIC_ISR5 0x815
1791	/** X2APIC MSR - In-service Register (bits 223:192). */
1792	#define MSR_IA32_X2APIC_ISR6 0x816
1793	/** X2APIC MSR - In-service Register (bits 255:224). */
1794	#define MSR_IA32_X2APIC_ISR7 0x817
1795	/** X2APIC MSR - Trigger Mode Register (bits 31:0). */
1796	#define MSR_IA32_X2APIC_TMR0 0x818
1797	/** X2APIC MSR - Trigger Mode Register (bits 63:32). */
1798	#define MSR_IA32_X2APIC_TMR1 0x819
1799	/** X2APIC MSR - Trigger Mode Register (bits 95:64). */
1800	#define MSR_IA32_X2APIC_TMR2 0x81A
1801	/** X2APIC MSR - Trigger Mode Register (bits 127:96). */
1802	#define MSR_IA32_X2APIC_TMR3 0x81B
1803	/** X2APIC MSR - Trigger Mode Register (bits 159:128). */
1804	#define MSR_IA32_X2APIC_TMR4 0x81C
1805	/** X2APIC MSR - Trigger Mode Register (bits 191:160). */
1806	#define MSR_IA32_X2APIC_TMR5 0x81D
1807	/** X2APIC MSR - Trigger Mode Register (bits 223:192). */
1808	#define MSR_IA32_X2APIC_TMR6 0x81E
1809	/** X2APIC MSR - Trigger Mode Register (bits 255:224). */
1810	#define MSR_IA32_X2APIC_TMR7 0x81F
1811	/** X2APIC MSR - Interrupt Request Register (bits 31:0). */
1812	#define MSR_IA32_X2APIC_IRR0 0x820
1813	/** X2APIC MSR - Interrupt Request Register (bits 63:32). */
1814	#define MSR_IA32_X2APIC_IRR1 0x821
1815	/** X2APIC MSR - Interrupt Request Register (bits 95:64). */
1816	#define MSR_IA32_X2APIC_IRR2 0x822
1817	/** X2APIC MSR - Interrupt Request Register (bits 127:96). */
1818	#define MSR_IA32_X2APIC_IRR3 0x823
1819	/** X2APIC MSR - Interrupt Request Register (bits 159:128). */
1820	#define MSR_IA32_X2APIC_IRR4 0x824
1821	/** X2APIC MSR - Interrupt Request Register (bits 191:160). */
1822	#define MSR_IA32_X2APIC_IRR5 0x825
1823	/** X2APIC MSR - Interrupt Request Register (bits 223:192). */
1824	#define MSR_IA32_X2APIC_IRR6 0x826
1825	/** X2APIC MSR - Interrupt Request Register (bits 255:224). */
1826	#define MSR_IA32_X2APIC_IRR7 0x827
1827	/** X2APIC MSR - Error Status Register. */
1828	#define MSR_IA32_X2APIC_ESR 0x828
1829	/** X2APIC MSR - LVT CMCI Register. */
1830	#define MSR_IA32_X2APIC_LVT_CMCI 0x82F
1831	/** X2APIC MSR - Interrupt Command Register. */
1832	#define MSR_IA32_X2APIC_ICR 0x830
1833	/** X2APIC MSR - LVT Timer Register. */
1834	#define MSR_IA32_X2APIC_LVT_TIMER 0x832
1835	/** X2APIC MSR - LVT Thermal Sensor Register. */
1836	#define MSR_IA32_X2APIC_LVT_THERMAL 0x833
1837	/** X2APIC MSR - LVT Performance Counter Register. */
1838	#define MSR_IA32_X2APIC_LVT_PERF 0x834
1839	/** X2APIC MSR - LVT LINT0 Register. */
1840	#define MSR_IA32_X2APIC_LVT_LINT0 0x835
1841	/** X2APIC MSR - LVT LINT1 Register. */
1842	#define MSR_IA32_X2APIC_LVT_LINT1 0x836
1843	/** X2APIC MSR - LVT Error Register . */
1844	#define MSR_IA32_X2APIC_LVT_ERROR 0x837
1845	/** X2APIC MSR - Timer Initial Count Register. */
1846	#define MSR_IA32_X2APIC_TIMER_ICR 0x838
1847	/** X2APIC MSR - Timer Current Count Register. */
1848	#define MSR_IA32_X2APIC_TIMER_CCR 0x839
1849	/** X2APIC MSR - Timer Divide Configuration Register. */
1850	#define MSR_IA32_X2APIC_TIMER_DCR 0x83E
1851	/** X2APIC MSR - Self IPI. */
1852	#define MSR_IA32_X2APIC_SELF_IPI 0x83F
1853	/** X2APIC MSR range end. */
1854	#define MSR_IA32_X2APIC_END 0x8FF
1855	/** X2APIC MSR - LVT start range. */
1856	#define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
1857	/** X2APIC MSR - LVT end range (inclusive). */
1858	#define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
1859
1860	/** K6 EFER - Extended Feature Enable Register. */
1861	#define MSR_K6_EFER UINT32_C(0xc0000080)
1862	/** @todo document EFER */
1863	/** Bit 0 - SCE - System call extensions (SYSCALL / SYSRET). (R/W) */
1864	#define MSR_K6_EFER_SCE RT_BIT_32(0)
1865	/** Bit 8 - LME - Long mode enabled. (R/W) */
1866	#define MSR_K6_EFER_LME RT_BIT_32(8)
1867	#define MSR_K6_EFER_BIT_LME 8 /*< Bit number of MSR_K6_EFER_LME /
1868	/** Bit 10 - LMA - Long mode active. (R) */
1869	#define MSR_K6_EFER_LMA RT_BIT_32(10)
1870	#define MSR_K6_EFER_BIT_LMA 10 /*< Bit number of MSR_K6_EFER_LMA /
1871	/** Bit 11 - NXE - No-Execute Page Protection Enabled. (R/W) */
1872	#define MSR_K6_EFER_NXE RT_BIT_32(11)
1873	#define MSR_K6_EFER_BIT_NXE 11 /*< Bit number of MSR_K6_EFER_NXE /
1874	/** Bit 12 - SVME - Secure VM Extension Enabled. (R/W) */
1875	#define MSR_K6_EFER_SVME RT_BIT_32(12)
1876	/** Bit 13 - LMSLE - Long Mode Segment Limit Enable. (R/W?) */
1877	#define MSR_K6_EFER_LMSLE RT_BIT_32(13)
1878	/** Bit 14 - FFXSR - Fast FXSAVE / FXRSTOR (skip XMM). (R/W) /
1879	#define MSR_K6_EFER_FFXSR RT_BIT_32(14)
1880	/** Bit 15 - TCE - Translation Cache Extension. (R/W) */
1881	#define MSR_K6_EFER_TCE RT_BIT_32(15)
1882	/** Bit 17 - MCOMMIT - Commit Stores to memory. (R/W) */
1883	#define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
1884
1885	/** K6 STAR - SYSCALL/RET targets. */
1886	#define MSR_K6_STAR UINT32_C(0xc0000081)
1887	/** Shift value for getting the SYSRET CS and SS value. */
1888	#define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
1889	/** Shift value for getting the SYSCALL CS and SS value. */
1890	#define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
1891	/** Selector mask for use after shifting. */
1892	#define MSR_K6_STAR_SEL_MASK UINT32_C(0xffff)
1893	/** The mask which give the SYSCALL EIP. */
1894	#define MSR_K6_STAR_SYSCALL_EIP_MASK UINT32_C(0xffffffff)
1895	/** K6 WHCR - Write Handling Control Register. */
1896	#define MSR_K6_WHCR UINT32_C(0xc0000082)
1897	/** K6 UWCCR - UC/WC Cacheability Control Register. */
1898	#define MSR_K6_UWCCR UINT32_C(0xc0000085)
1899	/** K6 PSOR - Processor State Observability Register. */
1900	#define MSR_K6_PSOR UINT32_C(0xc0000087)
1901	/** K6 PFIR - Page Flush/Invalidate Register. */
1902	#define MSR_K6_PFIR UINT32_C(0xc0000088)
1903
1904	/** Performance counter MSRs. (AMD only) */
1905	#define MSR_K7_EVNTSEL0 UINT32_C(0xc0010000)
1906	#define MSR_K7_EVNTSEL1 UINT32_C(0xc0010001)
1907	#define MSR_K7_EVNTSEL2 UINT32_C(0xc0010002)
1908	#define MSR_K7_EVNTSEL3 UINT32_C(0xc0010003)
1909	#define MSR_K7_PERFCTR0 UINT32_C(0xc0010004)
1910	#define MSR_K7_PERFCTR1 UINT32_C(0xc0010005)
1911	#define MSR_K7_PERFCTR2 UINT32_C(0xc0010006)
1912	#define MSR_K7_PERFCTR3 UINT32_C(0xc0010007)
1913
1914	/** K8 LSTAR - Long mode SYSCALL target (RIP). */
1915	#define MSR_K8_LSTAR UINT32_C(0xc0000082)
1916	/** K8 CSTAR - Compatibility mode SYSCALL target (RIP). */
1917	#define MSR_K8_CSTAR UINT32_C(0xc0000083)
1918	/** K8 SF_MASK - SYSCALL flag mask. (aka SFMASK) */
1919	#define MSR_K8_SF_MASK UINT32_C(0xc0000084)
1920	/** K8 FS.base - The 64-bit base FS register. */
1921	#define MSR_K8_FS_BASE UINT32_C(0xc0000100)
1922	/** K8 GS.base - The 64-bit base GS register. */
1923	#define MSR_K8_GS_BASE UINT32_C(0xc0000101)
1924	/** K8 KernelGSbase - Used with SWAPGS. */
1925	#define MSR_K8_KERNEL_GS_BASE UINT32_C(0xc0000102)
1926	/** K8 TSC_AUX - Used with RDTSCP. */
1927	#define MSR_K8_TSC_AUX UINT32_C(0xc0000103)
1928	#define MSR_K8_SYSCFG UINT32_C(0xc0010010)
1929	#define MSR_K8_HWCR UINT32_C(0xc0010015)
1930	#define MSR_K8_IORRBASE0 UINT32_C(0xc0010016)
1931	#define MSR_K8_IORRMASK0 UINT32_C(0xc0010017)
1932	#define MSR_K8_IORRBASE1 UINT32_C(0xc0010018)
1933	#define MSR_K8_IORRMASK1 UINT32_C(0xc0010019)
1934	#define MSR_K8_TOP_MEM1 UINT32_C(0xc001001a)
1935	#define MSR_K8_TOP_MEM2 UINT32_C(0xc001001d)
1936
1937	/** SMM MSRs. */
1938	#define MSR_K7_SMBASE UINT32_C(0xc0010111)
1939	#define MSR_K7_SMM_ADDR UINT32_C(0xc0010112)
1940	#define MSR_K7_SMM_MASK UINT32_C(0xc0010113)
1941
1942	/** North bridge config? See BIOS & Kernel dev guides for
1943	* details. */
1944	#define MSR_K8_NB_CFG UINT32_C(0xc001001f)
1945
1946	/** Hypertransport interrupt pending register.
1947	* "BIOS and Kernel Developer's Guide for AMD NPT Family 0Fh Processors" */
1948	#define MSR_K8_INT_PENDING UINT32_C(0xc0010055)
1949
1950	/** SVM Control. */
1951	#define MSR_K8_VM_CR UINT32_C(0xc0010114)
1952	/** Disables HDT (Hardware Debug Tool) and certain internal debug
1953	* features. */
1954	#define MSR_K8_VM_CR_DPD RT_BIT_32(0)
1955	/** If set, non-intercepted INIT signals are converted to \#SX
1956	* exceptions. */
1957	#define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
1958	/** Disables A20 masking. */
1959	#define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
1960	/** Lock bit for this MSR controlling bits 3 (LOCK) and 4 (SVMDIS). */
1961	#define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
1962	/** SVM disable. When set, writes to EFER.SVME are treated as MBZ. When
1963	* clear, EFER.SVME can be written normally. */
1964	#define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
1965
1966	#define MSR_K8_IGNNE UINT32_C(0xc0010115)
1967	#define MSR_K8_SMM_CTL UINT32_C(0xc0010116)
1968	/** SVM - VM_HSAVE_PA - Physical address for saving and restoring
1969	* host state during world switch. */
1970	#define MSR_K8_VM_HSAVE_PA UINT32_C(0xc0010117)
1971
1972	/** Virtualized speculation control for AMD processors.
1973	*
1974	* Unified interface among different CPU generations.
1975	* The VMM will set any architectural MSRs based on the CPU.
1976	* See "White Paper: AMD64 Technology Speculative Store Bypass Disable 5.21.18"
1977	* (12441_AMD64_SpeculativeStoreBypassDisable_Whitepaper_final.pdf) */
1978	#define MSR_AMD_VIRT_SPEC_CTL UINT32_C(0xc001011f)
1979	/** Speculative Store Bypass Disable. */
1980	# define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
1981
1982	/** @} */
1983
1984
1985	/** @name Page Table / Directory / Directory Pointers / L4.
1986	* @{
1987	*/
1988
1989	/** Page table/directory entry as an unsigned integer. */
1990	typedef uint32_t X86PGUINT;
1991	/** Pointer to a page table/directory table entry as an unsigned integer. */
1992	typedef X86PGUINT *PX86PGUINT;
1993	/** Pointer to an const page table/directory table entry as an unsigned integer. */
1994	typedef X86PGUINT const *PCX86PGUINT;
1995
1996	/** Number of entries in a 32-bit PT/PD. */
1997	#define X86_PG_ENTRIES 1024
1998
1999
2000	/** PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2001	typedef uint64_t X86PGPAEUINT;
2002	/** Pointer to a PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2003	typedef X86PGPAEUINT *PX86PGPAEUINT;
2004	/** Pointer to an const PAE page table/page directory/pdpt/l4/l5 entry as an unsigned integer. */
2005	typedef X86PGPAEUINT const *PCX86PGPAEUINT;
2006
2007	/** Number of entries in a PAE PT/PD. */
2008	#define X86_PG_PAE_ENTRIES 512
2009	/** Number of entries in a PAE PDPT. */
2010	#define X86_PG_PAE_PDPE_ENTRIES 4
2011
2012	/** Number of entries in an AMD64 PT/PD/PDPT/L4/L5. */
2013	#define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
2014	/** Number of entries in an AMD64 PDPT.
2015	* Just for complementing X86_PG_PAE_PDPE_ENTRIES, using X86_PG_AMD64_ENTRIES for this is fine too. */
2016	#define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
2017
2018	/** The size of a default page. */
2019	#define X86_PAGE_SIZE X86_PAGE_4K_SIZE
2020	/** The page shift of a default page. */
2021	#define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
2022	/** The default page offset mask. */
2023	#define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
2024	/** The default page base mask for virtual addresses. */
2025	#define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
2026	/** The default page base mask for virtual addresses - 32bit version. */
2027	#define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
2028
2029	/** The size of a 4KB page. */
2030	#define X86_PAGE_4K_SIZE _4K
2031	/** The page shift of a 4KB page. */
2032	#define X86_PAGE_4K_SHIFT 12
2033	/** The 4KB page offset mask. */
2034	#define X86_PAGE_4K_OFFSET_MASK 0xfff
2035	/** The 4KB page base mask for virtual addresses. */
2036	#define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000ULL
2037	/** The 4KB page base mask for virtual addresses - 32bit version. */
2038	#define X86_PAGE_4K_BASE_MASK_32 0xfffff000U
2039
2040	/** The size of a 2MB page. */
2041	#define X86_PAGE_2M_SIZE _2M
2042	/** The page shift of a 2MB page. */
2043	#define X86_PAGE_2M_SHIFT 21
2044	/** The 2MB page offset mask. */
2045	#define X86_PAGE_2M_OFFSET_MASK 0x001fffff
2046	/** The 2MB page base mask for virtual addresses. */
2047	#define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000ULL
2048	/** The 2MB page base mask for virtual addresses - 32bit version. */
2049	#define X86_PAGE_2M_BASE_MASK_32 0xffe00000U
2050
2051	/** The size of a 4MB page. */
2052	#define X86_PAGE_4M_SIZE _4M
2053	/** The page shift of a 4MB page. */
2054	#define X86_PAGE_4M_SHIFT 22
2055	/** The 4MB page offset mask. */
2056	#define X86_PAGE_4M_OFFSET_MASK 0x003fffff
2057	/** The 4MB page base mask for virtual addresses. */
2058	#define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000ULL
2059	/** The 4MB page base mask for virtual addresses - 32bit version. */
2060	#define X86_PAGE_4M_BASE_MASK_32 0xffc00000U
2061
2062	/** The size of a 1GB page. */
2063	#define X86_PAGE_1G_SIZE _1G
2064	/** The page shift of a 1GB page. */
2065	#define X86_PAGE_1G_SHIFT 30
2066	/** The 1GB page offset mask. */
2067	#define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
2068	/** The 1GB page base mask for virtual addresses. */
2069	#define X86_PAGE_1G_BASE_MASK UINT64_C(0xffffffffc0000000)
2070
2071	/**
2072	* Check if the given address is canonical.
2073	*/
2074	#define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + UINT64_C(0x800000000000) < UINT64_C(0x1000000000000))
2075
2076	/**
2077	* Gets the page base mask given the page shift.
2078	*/
2079	#define X86_GET_PAGE_BASE_MASK(a_cShift) (UINT64_C(0xffffffffffffffff) << (a_cShift))
2080
2081	/**
2082	* Gets the page offset mask given the page shift.
2083	*/
2084	#define X86_GET_PAGE_OFFSET_MASK(a_cShift) (~X86_GET_PAGE_BASE_MASK(a_cShift))
2085
2086
2087	/** @name Page Table Entry
2088	* @{
2089	*/
2090	/** Bit 0 - P - Present bit. */
2091	#define X86_PTE_BIT_P 0
2092	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2093	#define X86_PTE_BIT_RW 1
2094	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2095	#define X86_PTE_BIT_US 2
2096	/** Bit 3 - PWT - Page level write thru bit. */
2097	#define X86_PTE_BIT_PWT 3
2098	/** Bit 4 - PCD - Page level cache disable bit. */
2099	#define X86_PTE_BIT_PCD 4
2100	/** Bit 5 - A - Access bit. */
2101	#define X86_PTE_BIT_A 5
2102	/** Bit 6 - D - Dirty bit. */
2103	#define X86_PTE_BIT_D 6
2104	/** Bit 7 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2105	#define X86_PTE_BIT_PAT 7
2106	/** Bit 8 - G - Global flag. */
2107	#define X86_PTE_BIT_G 8
2108	/** Bits 63 - NX - PAE/LM - No execution flag. */
2109	#define X86_PTE_PAE_BIT_NX 63
2110
2111	/** Bit 0 - P - Present bit mask. */
2112	#define X86_PTE_P RT_BIT_32(0)
2113	/** Bit 1 - R/W - Read (clear) / Write (set) bit mask. */
2114	#define X86_PTE_RW RT_BIT_32(1)
2115	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit mask. */
2116	#define X86_PTE_US RT_BIT_32(2)
2117	/** Bit 3 - PWT - Page level write thru bit mask. */
2118	#define X86_PTE_PWT RT_BIT_32(3)
2119	/** Bit 4 - PCD - Page level cache disable bit mask. */
2120	#define X86_PTE_PCD RT_BIT_32(4)
2121	/** Bit 5 - A - Access bit mask. */
2122	#define X86_PTE_A RT_BIT_32(5)
2123	/** Bit 6 - D - Dirty bit mask. */
2124	#define X86_PTE_D RT_BIT_32(6)
2125	/** Bit 7 - PAT - Page Attribute Table index bit mask. Reserved and 0 if not supported. */
2126	#define X86_PTE_PAT RT_BIT_32(7)
2127	/** Bit 8 - G - Global bit mask. */
2128	#define X86_PTE_G RT_BIT_32(8)
2129
2130	/** Bits 9-11 - - Available for use to system software. */
2131	#define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2132	/** Bits 12-31 - - Physical Page number of the next level. */
2133	#define X86_PTE_PG_MASK ( 0xfffff000 )
2134
2135	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2136	#define X86_PTE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2137	/** Bits 63 - NX - PAE/LM - No execution flag. */
2138	#define X86_PTE_PAE_NX RT_BIT_64(63)
2139	/** Bits 62-52 - - PAE - MBZ bits when NX is active. */
2140	#define X86_PTE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000000)
2141	/** Bits 63-52 - - PAE - MBZ bits when no NX. */
2142	#define X86_PTE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000000)
2143	/** No bits - - LM - MBZ bits when NX is active. */
2144	#define X86_PTE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000000)
2145	/** Bits 63 - - LM - MBZ bits when no NX. */
2146	#define X86_PTE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000000)
2147
2148	/**
2149	* Page table entry.
2150	*/
2151	typedef struct X86PTEBITS
2152	{
2153	/** Flags whether(=1) or not the page is present. */
2154	uint32_t u1Present : 1;
2155	/** Read(=0) / Write(=1) flag. */
2156	uint32_t u1Write : 1;
2157	/** User(=1) / Supervisor (=0) flag. */
2158	uint32_t u1User : 1;
2159	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2160	uint32_t u1WriteThru : 1;
2161	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2162	uint32_t u1CacheDisable : 1;
2163	/** Accessed flag.
2164	* Indicates that the page have been read or written to. */
2165	uint32_t u1Accessed : 1;
2166	/** Dirty flag.
2167	* Indicates that the page has been written to. */
2168	uint32_t u1Dirty : 1;
2169	/** Reserved / If PAT enabled, bit 2 of the index. */
2170	uint32_t u1PAT : 1;
2171	/** Global flag. (Ignored in all but final level.) */
2172	uint32_t u1Global : 1;
2173	/** Available for use to system software. */
2174	uint32_t u3Available : 3;
2175	/** Physical Page number of the next level. */
2176	uint32_t u20PageNo : 20;
2177	} X86PTEBITS;
2178	#ifndef VBOX_FOR_DTRACE_LIB
2179	AssertCompileSize(X86PTEBITS, 4);
2180	#endif
2181	/** Pointer to a page table entry. */
2182	typedef X86PTEBITS *PX86PTEBITS;
2183	/** Pointer to a const page table entry. */
2184	typedef const X86PTEBITS *PCX86PTEBITS;
2185
2186	/**
2187	* Page table entry.
2188	*/
2189	typedef union X86PTE
2190	{
2191	/** Unsigned integer view */
2192	X86PGUINT u;
2193	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2194	/** Bit field view. */
2195	X86PTEBITS n;
2196	#endif
2197	/** 32-bit view. */
2198	uint32_t au32[1];
2199	/** 16-bit view. */
2200	uint16_t au16[2];
2201	/** 8-bit view. */
2202	uint8_t au8[4];
2203	} X86PTE;
2204	#ifndef VBOX_FOR_DTRACE_LIB
2205	AssertCompileSize(X86PTE, 4);
2206	#endif
2207	/** Pointer to a page table entry. */
2208	typedef X86PTE *PX86PTE;
2209	/** Pointer to a const page table entry. */
2210	typedef const X86PTE *PCX86PTE;
2211
2212
2213	/**
2214	* PAE page table entry.
2215	*/
2216	typedef struct X86PTEPAEBITS
2217	{
2218	/** Flags whether(=1) or not the page is present. */
2219	uint32_t u1Present : 1;
2220	/** Read(=0) / Write(=1) flag. */
2221	uint32_t u1Write : 1;
2222	/** User(=1) / Supervisor(=0) flag. */
2223	uint32_t u1User : 1;
2224	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2225	uint32_t u1WriteThru : 1;
2226	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2227	uint32_t u1CacheDisable : 1;
2228	/** Accessed flag.
2229	* Indicates that the page have been read or written to. */
2230	uint32_t u1Accessed : 1;
2231	/** Dirty flag.
2232	* Indicates that the page has been written to. */
2233	uint32_t u1Dirty : 1;
2234	/** Reserved / If PAT enabled, bit 2 of the index. */
2235	uint32_t u1PAT : 1;
2236	/** Global flag. (Ignored in all but final level.) */
2237	uint32_t u1Global : 1;
2238	/** Available for use to system software. */
2239	uint32_t u3Available : 3;
2240	/** Physical Page number of the next level - Low Part. Don't use this. */
2241	uint32_t u20PageNoLow : 20;
2242	/** Physical Page number of the next level - High Part. Don't use this. */
2243	uint32_t u20PageNoHigh : 20;
2244	/** MBZ bits */
2245	uint32_t u11Reserved : 11;
2246	/** No Execute flag. */
2247	uint32_t u1NoExecute : 1;
2248	} X86PTEPAEBITS;
2249	#ifndef VBOX_FOR_DTRACE_LIB
2250	AssertCompileSize(X86PTEPAEBITS, 8);
2251	#endif
2252	/** Pointer to a page table entry. */
2253	typedef X86PTEPAEBITS *PX86PTEPAEBITS;
2254	/** Pointer to a page table entry. */
2255	typedef const X86PTEPAEBITS *PCX86PTEPAEBITS;
2256
2257	/**
2258	* PAE Page table entry.
2259	*/
2260	typedef union X86PTEPAE
2261	{
2262	/** Unsigned integer view */
2263	X86PGPAEUINT u;
2264	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2265	/** Bit field view. */
2266	X86PTEPAEBITS n;
2267	#endif
2268	/** 32-bit view. */
2269	uint32_t au32[2];
2270	/** 16-bit view. */
2271	uint16_t au16[4];
2272	/** 8-bit view. */
2273	uint8_t au8[8];
2274	} X86PTEPAE;
2275	#ifndef VBOX_FOR_DTRACE_LIB
2276	AssertCompileSize(X86PTEPAE, 8);
2277	#endif
2278	/** Pointer to a PAE page table entry. */
2279	typedef X86PTEPAE *PX86PTEPAE;
2280	/** Pointer to a const PAE page table entry. */
2281	typedef const X86PTEPAE *PCX86PTEPAE;
2282	/** @} */
2283
2284	/**
2285	* Page table.
2286	*/
2287	typedef struct X86PT
2288	{
2289	/** PTE Array. */
2290	X86PTE a[X86_PG_ENTRIES];
2291	} X86PT;
2292	#ifndef VBOX_FOR_DTRACE_LIB
2293	AssertCompileSize(X86PT, 4096);
2294	#endif
2295	/** Pointer to a page table. */
2296	typedef X86PT *PX86PT;
2297	/** Pointer to a const page table. */
2298	typedef const X86PT *PCX86PT;
2299
2300	/** The page shift to get the PT index. */
2301	#define X86_PT_SHIFT 12
2302	/** The PT index mask (apply to a shifted page address). */
2303	#define X86_PT_MASK 0x3ff
2304
2305
2306	/**
2307	* Page directory.
2308	*/
2309	typedef struct X86PTPAE
2310	{
2311	/** PTE Array. */
2312	X86PTEPAE a[X86_PG_PAE_ENTRIES];
2313	} X86PTPAE;
2314	#ifndef VBOX_FOR_DTRACE_LIB
2315	AssertCompileSize(X86PTPAE, 4096);
2316	#endif
2317	/** Pointer to a page table. */
2318	typedef X86PTPAE *PX86PTPAE;
2319	/** Pointer to a const page table. */
2320	typedef const X86PTPAE *PCX86PTPAE;
2321
2322	/** The page shift to get the PA PTE index. */
2323	#define X86_PT_PAE_SHIFT 12
2324	/** The PAE PT index mask (apply to a shifted page address). */
2325	#define X86_PT_PAE_MASK 0x1ff
2326
2327
2328	/** @name 4KB Page Directory Entry
2329	* @{
2330	*/
2331	/** Bit 0 - P - Present bit. */
2332	#define X86_PDE_P RT_BIT_32(0)
2333	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2334	#define X86_PDE_RW RT_BIT_32(1)
2335	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2336	#define X86_PDE_US RT_BIT_32(2)
2337	/** Bit 3 - PWT - Page level write thru bit. */
2338	#define X86_PDE_PWT RT_BIT_32(3)
2339	/** Bit 4 - PCD - Page level cache disable bit. */
2340	#define X86_PDE_PCD RT_BIT_32(4)
2341	/** Bit 5 - A - Access bit. */
2342	#define X86_PDE_A RT_BIT_32(5)
2343	/** Bit 7 - PS - Page size attribute.
2344	* Clear mean 4KB pages, set means large pages (2/4MB). */
2345	#define X86_PDE_PS RT_BIT_32(7)
2346	/** Bits 9-11 - - Available for use to system software. */
2347	#define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2348	/** Bits 12-31 - - Physical Page number of the next level. */
2349	#define X86_PDE_PG_MASK ( 0xfffff000 )
2350
2351	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2352	#define X86_PDE_PAE_PG_MASK UINT64_C(0x000ffffffffff000)
2353	/** Bits 63 - NX - PAE/LM - No execution flag. */
2354	#define X86_PDE_PAE_NX RT_BIT_64(63)
2355	/** Bits 62-52, 7 - - PAE - MBZ bits when NX is active. */
2356	#define X86_PDE_PAE_MBZ_MASK_NX UINT64_C(0x7ff0000000000080)
2357	/** Bits 63-52, 7 - - PAE - MBZ bits when no NX. */
2358	#define X86_PDE_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff0000000000080)
2359	/** Bit 7 - - LM - MBZ bits when NX is active. */
2360	#define X86_PDE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2361	/** Bits 63, 7 - - LM - MBZ bits when no NX. */
2362	#define X86_PDE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2363
2364	/**
2365	* Page directory entry.
2366	*/
2367	typedef struct X86PDEBITS
2368	{
2369	/** Flags whether(=1) or not the page is present. */
2370	uint32_t u1Present : 1;
2371	/** Read(=0) / Write(=1) flag. */
2372	uint32_t u1Write : 1;
2373	/** User(=1) / Supervisor (=0) flag. */
2374	uint32_t u1User : 1;
2375	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2376	uint32_t u1WriteThru : 1;
2377	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2378	uint32_t u1CacheDisable : 1;
2379	/** Accessed flag.
2380	* Indicates that the page has been read or written to. */
2381	uint32_t u1Accessed : 1;
2382	/** Reserved / Ignored (dirty bit). */
2383	uint32_t u1Reserved0 : 1;
2384	/** Size bit if PSE is enabled - in any event it's 0. */
2385	uint32_t u1Size : 1;
2386	/** Reserved / Ignored (global bit). */
2387	uint32_t u1Reserved1 : 1;
2388	/** Available for use to system software. */
2389	uint32_t u3Available : 3;
2390	/** Physical Page number of the next level. */
2391	uint32_t u20PageNo : 20;
2392	} X86PDEBITS;
2393	#ifndef VBOX_FOR_DTRACE_LIB
2394	AssertCompileSize(X86PDEBITS, 4);
2395	#endif
2396	/** Pointer to a page directory entry. */
2397	typedef X86PDEBITS *PX86PDEBITS;
2398	/** Pointer to a const page directory entry. */
2399	typedef const X86PDEBITS *PCX86PDEBITS;
2400
2401
2402	/**
2403	* PAE page directory entry.
2404	*/
2405	typedef struct X86PDEPAEBITS
2406	{
2407	/** Flags whether(=1) or not the page is present. */
2408	uint32_t u1Present : 1;
2409	/** Read(=0) / Write(=1) flag. */
2410	uint32_t u1Write : 1;
2411	/** User(=1) / Supervisor (=0) flag. */
2412	uint32_t u1User : 1;
2413	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2414	uint32_t u1WriteThru : 1;
2415	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2416	uint32_t u1CacheDisable : 1;
2417	/** Accessed flag.
2418	* Indicates that the page has been read or written to. */
2419	uint32_t u1Accessed : 1;
2420	/** Reserved / Ignored (dirty bit). */
2421	uint32_t u1Reserved0 : 1;
2422	/** Size bit if PSE is enabled - in any event it's 0. */
2423	uint32_t u1Size : 1;
2424	/** Reserved / Ignored (global bit). / */
2425	uint32_t u1Reserved1 : 1;
2426	/** Available for use to system software. */
2427	uint32_t u3Available : 3;
2428	/** Physical Page number of the next level - Low Part. Don't use! */
2429	uint32_t u20PageNoLow : 20;
2430	/** Physical Page number of the next level - High Part. Don't use! */
2431	uint32_t u20PageNoHigh : 20;
2432	/** MBZ bits */
2433	uint32_t u11Reserved : 11;
2434	/** No Execute flag. */
2435	uint32_t u1NoExecute : 1;
2436	} X86PDEPAEBITS;
2437	#ifndef VBOX_FOR_DTRACE_LIB
2438	AssertCompileSize(X86PDEPAEBITS, 8);
2439	#endif
2440	/** Pointer to a page directory entry. */
2441	typedef X86PDEPAEBITS *PX86PDEPAEBITS;
2442	/** Pointer to a const page directory entry. */
2443	typedef const X86PDEPAEBITS *PCX86PDEPAEBITS;
2444
2445	/** @} */
2446
2447
2448	/** @name 2/4MB Page Directory Entry
2449	* @{
2450	*/
2451	/** Bit 0 - P - Present bit. */
2452	#define X86_PDE4M_P RT_BIT_32(0)
2453	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2454	#define X86_PDE4M_RW RT_BIT_32(1)
2455	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2456	#define X86_PDE4M_US RT_BIT_32(2)
2457	/** Bit 3 - PWT - Page level write thru bit. */
2458	#define X86_PDE4M_PWT RT_BIT_32(3)
2459	/** Bit 4 - PCD - Page level cache disable bit. */
2460	#define X86_PDE4M_PCD RT_BIT_32(4)
2461	/** Bit 5 - A - Access bit. */
2462	#define X86_PDE4M_A RT_BIT_32(5)
2463	/** Bit 6 - D - Dirty bit. */
2464	#define X86_PDE4M_D RT_BIT_32(6)
2465	/** Bit 7 - PS - Page size attribute. Clear mean 4KB pages, set means large pages (2/4MB). */
2466	#define X86_PDE4M_PS RT_BIT_32(7)
2467	/** Bit 8 - G - Global flag. */
2468	#define X86_PDE4M_G RT_BIT_32(8)
2469	/** Bits 9-11 - AVL - Available for use to system software. */
2470	#define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2471	/** Bit 12 - PAT - Page Attribute Table index bit. Reserved and 0 if not supported. */
2472	#define X86_PDE4M_PAT RT_BIT_32(12)
2473	/** Shift to get from X86_PTE_PAT to X86_PDE4M_PAT. */
2474	#define X86_PDE4M_PAT_SHIFT (12 - 7)
2475	/** Bits 22-31 - - Physical Page number. */
2476	#define X86_PDE4M_PG_MASK ( 0xffc00000 )
2477	/** Bits 20-13 - - Physical Page number high part (32-39 bits). AMD64 hack. */
2478	#define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
2479	/** The number of bits to the high part of the page number. */
2480	#define X86_PDE4M_PG_HIGH_SHIFT 19
2481	/** Bit 21 - - MBZ bits for AMD CPUs, no PSE36. */
2482	#define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
2483
2484	/** Bits 21-51 - - PAE/LM - Physical Page number.
2485	* (Bits 40-51 (long mode) & bits 36-51 (pae legacy) are reserved according to the Intel docs; AMD allows for more.) */
2486	#define X86_PDE2M_PAE_PG_MASK UINT64_C(0x000fffffffe00000)
2487	/** Bits 63 - NX - PAE/LM - No execution flag. */
2488	#define X86_PDE2M_PAE_NX RT_BIT_64(63)
2489	/** Bits 62-52, 20-13 - - PAE - MBZ bits when NX is active. */
2490	#define X86_PDE2M_PAE_MBZ_MASK_NX UINT64_C(0x7ff00000001fe000)
2491	/** Bits 63-52, 20-13 - - PAE - MBZ bits when no NX. */
2492	#define X86_PDE2M_PAE_MBZ_MASK_NO_NX UINT64_C(0xfff00000001fe000)
2493	/** Bits 20-13 - - LM - MBZ bits when NX is active. */
2494	#define X86_PDE2M_LM_MBZ_MASK_NX UINT64_C(0x00000000001fe000)
2495	/** Bits 63, 20-13 - - LM - MBZ bits when no NX. */
2496	#define X86_PDE2M_LM_MBZ_MASK_NO_NX UINT64_C(0x80000000001fe000)
2497
2498	/**
2499	* 4MB page directory entry.
2500	*/
2501	typedef struct X86PDE4MBITS
2502	{
2503	/** Flags whether(=1) or not the page is present. */
2504	uint32_t u1Present : 1;
2505	/** Read(=0) / Write(=1) flag. */
2506	uint32_t u1Write : 1;
2507	/** User(=1) / Supervisor (=0) flag. */
2508	uint32_t u1User : 1;
2509	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2510	uint32_t u1WriteThru : 1;
2511	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2512	uint32_t u1CacheDisable : 1;
2513	/** Accessed flag.
2514	* Indicates that the page have been read or written to. */
2515	uint32_t u1Accessed : 1;
2516	/** Dirty flag.
2517	* Indicates that the page has been written to. */
2518	uint32_t u1Dirty : 1;
2519	/** Page size flag - always 1 for 4MB entries. */
2520	uint32_t u1Size : 1;
2521	/** Global flag. */
2522	uint32_t u1Global : 1;
2523	/** Available for use to system software. */
2524	uint32_t u3Available : 3;
2525	/** Reserved / If PAT enabled, bit 2 of the index. */
2526	uint32_t u1PAT : 1;
2527	/** Bits 32-39 of the page number on AMD64.
2528	* This AMD64 hack allows accessing 40bits of physical memory without PAE. */
2529	uint32_t u8PageNoHigh : 8;
2530	/** Reserved. */
2531	uint32_t u1Reserved : 1;
2532	/** Physical Page number of the page. */
2533	uint32_t u10PageNo : 10;
2534	} X86PDE4MBITS;
2535	#ifndef VBOX_FOR_DTRACE_LIB
2536	AssertCompileSize(X86PDE4MBITS, 4);
2537	#endif
2538	/** Pointer to a page table entry. */
2539	typedef X86PDE4MBITS *PX86PDE4MBITS;
2540	/** Pointer to a const page table entry. */
2541	typedef const X86PDE4MBITS *PCX86PDE4MBITS;
2542
2543
2544	/**
2545	* 2MB PAE page directory entry.
2546	*/
2547	typedef struct X86PDE2MPAEBITS
2548	{
2549	/** Flags whether(=1) or not the page is present. */
2550	uint32_t u1Present : 1;
2551	/** Read(=0) / Write(=1) flag. */
2552	uint32_t u1Write : 1;
2553	/** User(=1) / Supervisor(=0) flag. */
2554	uint32_t u1User : 1;
2555	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2556	uint32_t u1WriteThru : 1;
2557	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2558	uint32_t u1CacheDisable : 1;
2559	/** Accessed flag.
2560	* Indicates that the page have been read or written to. */
2561	uint32_t u1Accessed : 1;
2562	/** Dirty flag.
2563	* Indicates that the page has been written to. */
2564	uint32_t u1Dirty : 1;
2565	/** Page size flag - always 1 for 2MB entries. */
2566	uint32_t u1Size : 1;
2567	/** Global flag. */
2568	uint32_t u1Global : 1;
2569	/** Available for use to system software. */
2570	uint32_t u3Available : 3;
2571	/** Reserved / If PAT enabled, bit 2 of the index. */
2572	uint32_t u1PAT : 1;
2573	/** Reserved. */
2574	uint32_t u9Reserved : 9;
2575	/** Physical Page number of the next level - Low part. Don't use! */
2576	uint32_t u10PageNoLow : 10;
2577	/** Physical Page number of the next level - High part. Don't use! */
2578	uint32_t u20PageNoHigh : 20;
2579	/** MBZ bits */
2580	uint32_t u11Reserved : 11;
2581	/** No Execute flag. */
2582	uint32_t u1NoExecute : 1;
2583	} X86PDE2MPAEBITS;
2584	#ifndef VBOX_FOR_DTRACE_LIB
2585	AssertCompileSize(X86PDE2MPAEBITS, 8);
2586	#endif
2587	/** Pointer to a 2MB PAE page table entry. */
2588	typedef X86PDE2MPAEBITS *PX86PDE2MPAEBITS;
2589	/** Pointer to a 2MB PAE page table entry. */
2590	typedef const X86PDE2MPAEBITS *PCX86PDE2MPAEBITS;
2591
2592	/** @} */
2593
2594	/**
2595	* Page directory entry.
2596	*/
2597	typedef union X86PDE
2598	{
2599	/** Unsigned integer view. */
2600	X86PGUINT u;
2601	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2602	/** Normal view. */
2603	X86PDEBITS n;
2604	/** 4MB view (big). */
2605	X86PDE4MBITS b;
2606	#endif
2607	/** 8 bit unsigned integer view. */
2608	uint8_t au8[4];
2609	/** 16 bit unsigned integer view. */
2610	uint16_t au16[2];
2611	/** 32 bit unsigned integer view. */
2612	uint32_t au32[1];
2613	} X86PDE;
2614	#ifndef VBOX_FOR_DTRACE_LIB
2615	AssertCompileSize(X86PDE, 4);
2616	#endif
2617	/** Pointer to a page directory entry. */
2618	typedef X86PDE *PX86PDE;
2619	/** Pointer to a const page directory entry. */
2620	typedef const X86PDE *PCX86PDE;
2621
2622	/**
2623	* PAE page directory entry.
2624	*/
2625	typedef union X86PDEPAE
2626	{
2627	/** Unsigned integer view. */
2628	X86PGPAEUINT u;
2629	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2630	/** Normal view. */
2631	X86PDEPAEBITS n;
2632	/** 2MB page view (big). */
2633	X86PDE2MPAEBITS b;
2634	#endif
2635	/** 8 bit unsigned integer view. */
2636	uint8_t au8[8];
2637	/** 16 bit unsigned integer view. */
2638	uint16_t au16[4];
2639	/** 32 bit unsigned integer view. */
2640	uint32_t au32[2];
2641	} X86PDEPAE;
2642	#ifndef VBOX_FOR_DTRACE_LIB
2643	AssertCompileSize(X86PDEPAE, 8);
2644	#endif
2645	/** Pointer to a page directory entry. */
2646	typedef X86PDEPAE *PX86PDEPAE;
2647	/** Pointer to a const page directory entry. */
2648	typedef const X86PDEPAE *PCX86PDEPAE;
2649
2650	/**
2651	* Page directory.
2652	*/
2653	typedef struct X86PD
2654	{
2655	/** PDE Array. */
2656	X86PDE a[X86_PG_ENTRIES];
2657	} X86PD;
2658	#ifndef VBOX_FOR_DTRACE_LIB
2659	AssertCompileSize(X86PD, 4096);
2660	#endif
2661	/** Pointer to a page directory. */
2662	typedef X86PD *PX86PD;
2663	/** Pointer to a const page directory. */
2664	typedef const X86PD *PCX86PD;
2665
2666	/** The page shift to get the PD index. */
2667	#define X86_PD_SHIFT 22
2668	/** The PD index mask (apply to a shifted page address). */
2669	#define X86_PD_MASK 0x3ff
2670
2671
2672	/**
2673	* PAE page directory.
2674	*/
2675	typedef struct X86PDPAE
2676	{
2677	/** PDE Array. */
2678	X86PDEPAE a[X86_PG_PAE_ENTRIES];
2679	} X86PDPAE;
2680	#ifndef VBOX_FOR_DTRACE_LIB
2681	AssertCompileSize(X86PDPAE, 4096);
2682	#endif
2683	/** Pointer to a PAE page directory. */
2684	typedef X86PDPAE *PX86PDPAE;
2685	/** Pointer to a const PAE page directory. */
2686	typedef const X86PDPAE *PCX86PDPAE;
2687
2688	/** The page shift to get the PAE PD index. */
2689	#define X86_PD_PAE_SHIFT 21
2690	/** The PAE PD index mask (apply to a shifted page address). */
2691	#define X86_PD_PAE_MASK 0x1ff
2692
2693
2694	/** @name Page Directory Pointer Table Entry (PAE)
2695	* @{
2696	*/
2697	/** Bit 0 - P - Present bit. */
2698	#define X86_PDPE_P RT_BIT_32(0)
2699	/** Bit 1 - R/W - Read (clear) / Write (set) bit. Long Mode only. */
2700	#define X86_PDPE_RW RT_BIT_32(1)
2701	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. Long Mode only. */
2702	#define X86_PDPE_US RT_BIT_32(2)
2703	/** Bit 3 - PWT - Page level write thru bit. */
2704	#define X86_PDPE_PWT RT_BIT_32(3)
2705	/** Bit 4 - PCD - Page level cache disable bit. */
2706	#define X86_PDPE_PCD RT_BIT_32(4)
2707	/** Bit 5 - A - Access bit. Long Mode only. */
2708	#define X86_PDPE_A RT_BIT_32(5)
2709	/** Bit 7 - PS - Page size (1GB). Long Mode only. */
2710	#define X86_PDPE_LM_PS RT_BIT_32(7)
2711	/** Bits 9-11 - - Available for use to system software. */
2712	#define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2713	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2714	#define X86_PDPE_PG_MASK UINT64_C(0x000ffffffffff000)
2715	/** Bits 30-51 - - PG - Physical address of the 1GB page referenced by this entry. */
2716	#define X86_PDPE1G_PG_MASK UINT64_C(0x000fffffc0000000)
2717	/** Bits 63-52, 8-5, 2-1 - - PAE - MBZ bits (NX is long mode only). */
2718	#define X86_PDPE_PAE_MBZ_MASK UINT64_C(0xfff00000000001e6)
2719	/** Bits 63 - NX - LM - No execution flag. Long Mode only. */
2720	#define X86_PDPE_LM_NX RT_BIT_64(63)
2721	/** Bits 8, 7 - - LM - MBZ bits when NX is active. */
2722	#define X86_PDPE_LM_MBZ_MASK_NX UINT64_C(0x0000000000000180)
2723	/** Bits 63, 8, 7 - - LM - MBZ bits when no NX. */
2724	#define X86_PDPE_LM_MBZ_MASK_NO_NX UINT64_C(0x8000000000000180)
2725	/** Bits 29-13 - - LM - MBZ bits for 1GB page entry when NX is active. */
2726	#define X86_PDPE1G_LM_MBZ_MASK_NX UINT64_C(0x000000003fffe000)
2727	/** Bits 63, 29-13 - - LM - MBZ bits for 1GB page entry when no NX. */
2728	#define X86_PDPE1G_LM_MBZ_MASK_NO_NX UINT64_C(0x800000003fffe000)
2729
2730
2731	/**
2732	* Page directory pointer table entry.
2733	*/
2734	typedef struct X86PDPEBITS
2735	{
2736	/** Flags whether(=1) or not the page is present. */
2737	uint32_t u1Present : 1;
2738	/** Chunk of reserved bits. */
2739	uint32_t u2Reserved : 2;
2740	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2741	uint32_t u1WriteThru : 1;
2742	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2743	uint32_t u1CacheDisable : 1;
2744	/** Chunk of reserved bits. */
2745	uint32_t u4Reserved : 4;
2746	/** Available for use to system software. */
2747	uint32_t u3Available : 3;
2748	/** Physical Page number of the next level - Low Part. Don't use! */
2749	uint32_t u20PageNoLow : 20;
2750	/** Physical Page number of the next level - High Part. Don't use! */
2751	uint32_t u20PageNoHigh : 20;
2752	/** MBZ bits */
2753	uint32_t u12Reserved : 12;
2754	} X86PDPEBITS;
2755	#ifndef VBOX_FOR_DTRACE_LIB
2756	AssertCompileSize(X86PDPEBITS, 8);
2757	#endif
2758	/** Pointer to a page directory pointer table entry. */
2759	typedef X86PDPEBITS *PX86PTPEBITS;
2760	/** Pointer to a const page directory pointer table entry. */
2761	typedef const X86PDPEBITS *PCX86PTPEBITS;
2762
2763	/**
2764	* Page directory pointer table entry. AMD64 version
2765	*/
2766	typedef struct X86PDPEAMD64BITS
2767	{
2768	/** Flags whether(=1) or not the page is present. */
2769	uint32_t u1Present : 1;
2770	/** Read(=0) / Write(=1) flag. */
2771	uint32_t u1Write : 1;
2772	/** User(=1) / Supervisor (=0) flag. */
2773	uint32_t u1User : 1;
2774	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2775	uint32_t u1WriteThru : 1;
2776	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2777	uint32_t u1CacheDisable : 1;
2778	/** Accessed flag.
2779	* Indicates that the page have been read or written to. */
2780	uint32_t u1Accessed : 1;
2781	/** Chunk of reserved bits. */
2782	uint32_t u3Reserved : 3;
2783	/** Available for use to system software. */
2784	uint32_t u3Available : 3;
2785	/** Physical Page number of the next level - Low Part. Don't use! */
2786	uint32_t u20PageNoLow : 20;
2787	/** Physical Page number of the next level - High Part. Don't use! */
2788	uint32_t u20PageNoHigh : 20;
2789	/** MBZ bits */
2790	uint32_t u11Reserved : 11;
2791	/** No Execute flag. */
2792	uint32_t u1NoExecute : 1;
2793	} X86PDPEAMD64BITS;
2794	#ifndef VBOX_FOR_DTRACE_LIB
2795	AssertCompileSize(X86PDPEAMD64BITS, 8);
2796	#endif
2797	/** Pointer to a page directory pointer table entry. */
2798	typedef X86PDPEAMD64BITS *PX86PDPEAMD64BITS;
2799	/** Pointer to a const page directory pointer table entry. */
2800	typedef const X86PDPEAMD64BITS *PCX86PDPEAMD64BITS;
2801
2802	/**
2803	* Page directory pointer table entry for 1GB page. (AMD64 only)
2804	*/
2805	typedef struct X86PDPE1GB
2806	{
2807	/** 0: Flags whether(=1) or not the page is present. */
2808	uint32_t u1Present : 1;
2809	/** 1: Read(=0) / Write(=1) flag. */
2810	uint32_t u1Write : 1;
2811	/** 2: User(=1) / Supervisor (=0) flag. */
2812	uint32_t u1User : 1;
2813	/** 3: Write Thru flag. If PAT enabled, bit 0 of the index. */
2814	uint32_t u1WriteThru : 1;
2815	/** 4: Cache disabled flag. If PAT enabled, bit 1 of the index. */
2816	uint32_t u1CacheDisable : 1;
2817	/** 5: Accessed flag.
2818	* Indicates that the page have been read or written to. */
2819	uint32_t u1Accessed : 1;
2820	/** 6: Dirty flag for 1GB pages. */
2821	uint32_t u1Dirty : 1;
2822	/** 7: Indicates 1GB page if set. */
2823	uint32_t u1Size : 1;
2824	/** 8: Global 1GB page. */
2825	uint32_t u1Global: 1;
2826	/** 9-11: Available for use to system software. */
2827	uint32_t u3Available : 3;
2828	/** 12: PAT bit for 1GB page. */
2829	uint32_t u1PAT : 1;
2830	/** 13-29: MBZ bits. */
2831	uint32_t u17Reserved : 17;
2832	/** 30-31: Physical page number - Low Part. Don't use! */
2833	uint32_t u2PageNoLow : 2;
2834	/** 32-51: Physical Page number of the next level - High Part. Don't use! */
2835	uint32_t u20PageNoHigh : 20;
2836	/** 52-62: MBZ bits */
2837	uint32_t u11Reserved : 11;
2838	/** 63: No Execute flag. */
2839	uint32_t u1NoExecute : 1;
2840	} X86PDPE1GB;
2841	#ifndef VBOX_FOR_DTRACE_LIB
2842	AssertCompileSize(X86PDPE1GB, 8);
2843	#endif
2844	/** Pointer to a page directory pointer table entry for a 1GB page. */
2845	typedef X86PDPE1GB *PX86PDPE1GB;
2846	/** Pointer to a const page directory pointer table entry for a 1GB page. */
2847	typedef const X86PDPE1GB *PCX86PDPE1GB;
2848
2849	/**
2850	* Page directory pointer table entry.
2851	*/
2852	typedef union X86PDPE
2853	{
2854	/** Unsigned integer view. */
2855	X86PGPAEUINT u;
2856	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2857	/** Normal view. */
2858	X86PDPEBITS n;
2859	/** AMD64 view. */
2860	X86PDPEAMD64BITS lm;
2861	/** AMD64 big view. */
2862	X86PDPE1GB b;
2863	#endif
2864	/** 8 bit unsigned integer view. */
2865	uint8_t au8[8];
2866	/** 16 bit unsigned integer view. */
2867	uint16_t au16[4];
2868	/** 32 bit unsigned integer view. */
2869	uint32_t au32[2];
2870	} X86PDPE;
2871	#ifndef VBOX_FOR_DTRACE_LIB
2872	AssertCompileSize(X86PDPE, 8);
2873	#endif
2874	/** Pointer to a page directory pointer table entry. */
2875	typedef X86PDPE *PX86PDPE;
2876	/** Pointer to a const page directory pointer table entry. */
2877	typedef const X86PDPE *PCX86PDPE;
2878
2879
2880	/**
2881	* Page directory pointer table.
2882	*/
2883	typedef struct X86PDPT
2884	{
2885	/** PDE Array. */
2886	X86PDPE a[X86_PG_AMD64_PDPE_ENTRIES];
2887	} X86PDPT;
2888	#ifndef VBOX_FOR_DTRACE_LIB
2889	AssertCompileSize(X86PDPT, 4096);
2890	#endif
2891	/** Pointer to a page directory pointer table. */
2892	typedef X86PDPT *PX86PDPT;
2893	/** Pointer to a const page directory pointer table. */
2894	typedef const X86PDPT *PCX86PDPT;
2895
2896	/** The page shift to get the PDPT index. */
2897	#define X86_PDPT_SHIFT 30
2898	/** The PDPT index mask (apply to a shifted page address). (32 bits PAE) */
2899	#define X86_PDPT_MASK_PAE 0x3
2900	/** The PDPT index mask (apply to a shifted page address). (64 bits PAE)*/
2901	#define X86_PDPT_MASK_AMD64 0x1ff
2902
2903	/** @} */
2904
2905
2906	/** @name Page Map Level-4 Entry (Long Mode PAE)
2907	* @{
2908	*/
2909	/** Bit 0 - P - Present bit. */
2910	#define X86_PML4E_P RT_BIT_32(0)
2911	/** Bit 1 - R/W - Read (clear) / Write (set) bit. */
2912	#define X86_PML4E_RW RT_BIT_32(1)
2913	/** Bit 2 - U/S - User (set) / Supervisor (clear) bit. */
2914	#define X86_PML4E_US RT_BIT_32(2)
2915	/** Bit 3 - PWT - Page level write thru bit. */
2916	#define X86_PML4E_PWT RT_BIT_32(3)
2917	/** Bit 4 - PCD - Page level cache disable bit. */
2918	#define X86_PML4E_PCD RT_BIT_32(4)
2919	/** Bit 5 - A - Access bit. */
2920	#define X86_PML4E_A RT_BIT_32(5)
2921	/** Bits 9-11 - - Available for use to system software. */
2922	#define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
2923	/** Bits 12-51 - - PAE - Physical Page number of the next level. */
2924	#define X86_PML4E_PG_MASK UINT64_C(0x000ffffffffff000)
2925	/** Bits 8, 7 - - MBZ bits when NX is active. */
2926	#define X86_PML4E_MBZ_MASK_NX UINT64_C(0x0000000000000080)
2927	/** Bits 63, 7 - - MBZ bits when no NX. */
2928	#define X86_PML4E_MBZ_MASK_NO_NX UINT64_C(0x8000000000000080)
2929	/** Bits 63 - NX - PAE - No execution flag. */
2930	#define X86_PML4E_NX RT_BIT_64(63)
2931
2932	/**
2933	* Page Map Level-4 Entry
2934	*/
2935	typedef struct X86PML4EBITS
2936	{
2937	/** Flags whether(=1) or not the page is present. */
2938	uint32_t u1Present : 1;
2939	/** Read(=0) / Write(=1) flag. */
2940	uint32_t u1Write : 1;
2941	/** User(=1) / Supervisor (=0) flag. */
2942	uint32_t u1User : 1;
2943	/** Write Thru flag. If PAT enabled, bit 0 of the index. */
2944	uint32_t u1WriteThru : 1;
2945	/** Cache disabled flag. If PAT enabled, bit 1 of the index. */
2946	uint32_t u1CacheDisable : 1;
2947	/** Accessed flag.
2948	* Indicates that the page have been read or written to. */
2949	uint32_t u1Accessed : 1;
2950	/** Chunk of reserved bits. */
2951	uint32_t u3Reserved : 3;
2952	/** Available for use to system software. */
2953	uint32_t u3Available : 3;
2954	/** Physical Page number of the next level - Low Part. Don't use! */
2955	uint32_t u20PageNoLow : 20;
2956	/** Physical Page number of the next level - High Part. Don't use! */
2957	uint32_t u20PageNoHigh : 20;
2958	/** MBZ bits */
2959	uint32_t u11Reserved : 11;
2960	/** No Execute flag. */
2961	uint32_t u1NoExecute : 1;
2962	} X86PML4EBITS;
2963	#ifndef VBOX_FOR_DTRACE_LIB
2964	AssertCompileSize(X86PML4EBITS, 8);
2965	#endif
2966	/** Pointer to a page map level-4 entry. */
2967	typedef X86PML4EBITS *PX86PML4EBITS;
2968	/** Pointer to a const page map level-4 entry. */
2969	typedef const X86PML4EBITS *PCX86PML4EBITS;
2970
2971	/**
2972	* Page Map Level-4 Entry.
2973	*/
2974	typedef union X86PML4E
2975	{
2976	/** Unsigned integer view. */
2977	X86PGPAEUINT u;
2978	#ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
2979	/** Normal view. */
2980	X86PML4EBITS n;
2981	#endif
2982	/** 8 bit unsigned integer view. */
2983	uint8_t au8[8];
2984	/** 16 bit unsigned integer view. */
2985	uint16_t au16[4];
2986	/** 32 bit unsigned integer view. */
2987	uint32_t au32[2];
2988	} X86PML4E;
2989	#ifndef VBOX_FOR_DTRACE_LIB
2990	AssertCompileSize(X86PML4E, 8);
2991	#endif
2992	/** Pointer to a page map level-4 entry. */
2993	typedef X86PML4E *PX86PML4E;
2994	/** Pointer to a const page map level-4 entry. */
2995	typedef const X86PML4E *PCX86PML4E;
2996
2997
2998	/**
2999	* Page Map Level-4.
3000	*/
3001	typedef struct X86PML4
3002	{
3003	/** PDE Array. */
3004	X86PML4E a[X86_PG_PAE_ENTRIES];
3005	} X86PML4;
3006	#ifndef VBOX_FOR_DTRACE_LIB
3007	AssertCompileSize(X86PML4, 4096);
3008	#endif
3009	/** Pointer to a page map level-4. */
3010	typedef X86PML4 *PX86PML4;
3011	/** Pointer to a const page map level-4. */
3012	typedef const X86PML4 *PCX86PML4;
3013
3014	/** The page shift to get the PML4 index. */
3015	#define X86_PML4_SHIFT 39
3016	/** The PML4 index mask (apply to a shifted page address). */
3017	#define X86_PML4_MASK 0x1ff
3018
3019	/** @} */
3020
3021	/** @} */
3022
3023	/**
3024	* Intel PCID invalidation types.
3025	*/
3026	/** Individual address invalidation. */
3027	#define X86_INVPCID_TYPE_INDV_ADDR 0
3028	/** Single-context invalidation. */
3029	#define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
3030	/** All-context including globals invalidation. */
3031	#define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
3032	/** All-context excluding globals invalidation. */
3033	#define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
3034	/** The maximum valid invalidation type value. */
3035	#define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
3036
3037
3038	/** @name Special FPU integer values.
3039	* @{ */
3040	#define X86_FPU_INT64_INDEFINITE INT64_MIN
3041	#define X86_FPU_INT32_INDEFINITE INT32_MIN
3042	#define X86_FPU_INT16_INDEFINITE INT16_MIN
3043	/** @} */
3044
3045	/**
3046	* 32-bit protected mode FSTENV image.
3047	*/
3048	typedef struct X86FSTENV32P
3049	{
3050	uint16_t FCW; /*< 0x00 /
3051	uint16_t padding1; /*< 0x02 /
3052	uint16_t FSW; /*< 0x04 /
3053	uint16_t padding2; /*< 0x06 /
3054	uint16_t FTW; /*< 0x08 /
3055	uint16_t padding3; /*< 0x0a /
3056	uint32_t FPUIP; /*< 0x0c /
3057	uint16_t FPUCS; /*< 0x10 /
3058	uint16_t FOP; /*< 0x12 /
3059	uint32_t FPUDP; /*< 0x14 /
3060	uint16_t FPUDS; /*< 0x18 /
3061	uint16_t padding4; /*< 0x1a /
3062	} X86FSTENV32P;
3063	#ifndef VBOX_FOR_DTRACE_LIB
3064	AssertCompileSize(X86FSTENV32P, 0x1c);
3065	#endif
3066	/** Pointer to a 32-bit protected mode FSTENV image. */
3067	typedef X86FSTENV32P *PX86FSTENV32P;
3068	/** Pointer to a const 32-bit protected mode FSTENV image. */
3069	typedef X86FSTENV32P const *PCX86FSTENV32P;
3070
3071
3072	/**
3073	* 80-bit MMX/FPU register type.
3074	*/
3075	typedef struct X86FPUMMX
3076	{
3077	uint8_t reg[10];
3078	} X86FPUMMX;
3079	#ifndef VBOX_FOR_DTRACE_LIB
3080	AssertCompileSize(X86FPUMMX, 10);
3081	#endif
3082	/** Pointer to a 80-bit MMX/FPU register type. */
3083	typedef X86FPUMMX *PX86FPUMMX;
3084	/** Pointer to a const 80-bit MMX/FPU register type. */
3085	typedef const X86FPUMMX *PCX86FPUMMX;
3086
3087	/** FPU (x87) register. */
3088	typedef union X86FPUREG
3089	{
3090	/** MMX view. */
3091	uint64_t mmx;
3092	/** FPU view - todo. */
3093	X86FPUMMX fpu;
3094	/** Extended precision floating point view. */
3095	RTFLOAT80U r80;
3096	/** Extended precision floating point view v2 */
3097	RTFLOAT80U2 r80Ex;
3098	/** 8-bit view. */
3099	uint8_t au8[16];
3100	/** 16-bit view. */
3101	uint16_t au16[8];
3102	/** 32-bit view. */
3103	uint32_t au32[4];
3104	/** 64-bit view. */
3105	uint64_t au64[2];
3106	/** 128-bit view. (yeah, very helpful) */
3107	uint128_t au128[1];
3108	} X86FPUREG;
3109	#ifndef VBOX_FOR_DTRACE_LIB
3110	AssertCompileSize(X86FPUREG, 16);
3111	#endif
3112	/** Pointer to a FPU register. */
3113	typedef X86FPUREG *PX86FPUREG;
3114	/** Pointer to a const FPU register. */
3115	typedef X86FPUREG const *PCX86FPUREG;
3116
3117	/** FPU (x87) register - v2 with correct size. */
3118	#pragma pack(1)
3119	typedef union X86FPUREG2
3120	{
3121	/** MMX view. */
3122	uint64_t mmx;
3123	/** FPU view - todo. */
3124	X86FPUMMX fpu;
3125	/** Extended precision floating point view. */
3126	RTFLOAT80U r80;
3127	/** 8-bit view. */
3128	uint8_t au8[10];
3129	/** 16-bit view. */
3130	uint16_t au16[5];
3131	/** 32-bit view. */
3132	uint32_t au32[2];
3133	/** 64-bit view. */
3134	uint64_t au64[1];
3135	} X86FPUREG2;
3136	#pragma pack()
3137	#ifndef VBOX_FOR_DTRACE_LIB
3138	AssertCompileSize(X86FPUREG2, 10);
3139	#endif
3140	/** Pointer to a FPU register - v2. */
3141	typedef X86FPUREG2 *PX86FPUREG2;
3142	/** Pointer to a const FPU register - v2. */
3143	typedef X86FPUREG2 const *PCX86FPUREG2;
3144
3145	/**
3146	* XMM register union.
3147	*/
3148	typedef union X86XMMREG
3149	{
3150	/** XMM Register view. */
3151	uint128_t xmm;
3152	/** 8-bit view. */
3153	uint8_t au8[16];
3154	/** 16-bit view. */
3155	uint16_t au16[8];
3156	/** 32-bit view. */
3157	uint32_t au32[4];
3158	/** 64-bit view. */
3159	uint64_t au64[2];
3160	/** Signed 8-bit view. */
3161	int8_t ai8[16];
3162	/** Signed 16-bit view. */
3163	int16_t ai16[8];
3164	/** Signed 32-bit view. */
3165	int32_t ai32[4];
3166	/** Signed 64-bit view. */
3167	int64_t ai64[2];
3168	/** 128-bit view. (yeah, very helpful) */
3169	uint128_t au128[1];
3170	/** Single precision floating point view. */
3171	RTFLOAT32U ar32[4];
3172	/** Double precision floating point view. */
3173	RTFLOAT64U ar64[2];
3174	#ifndef VBOX_FOR_DTRACE_LIB
3175	/** Confusing nested 128-bit union view (this is what xmm should've been). */
3176	RTUINT128U uXmm;
3177	#endif
3178	} X86XMMREG;
3179	#ifndef VBOX_FOR_DTRACE_LIB
3180	AssertCompileSize(X86XMMREG, 16);
3181	#endif
3182	/** Pointer to an XMM register state. */
3183	typedef X86XMMREG *PX86XMMREG;
3184	/** Pointer to a const XMM register state. */
3185	typedef X86XMMREG const *PCX86XMMREG;
3186
3187	/**
3188	* YMM register union.
3189	*/
3190	typedef union X86YMMREG
3191	{
3192	/** YMM register view. */
3193	RTUINT256U ymm;
3194	/** 8-bit view. */
3195	uint8_t au8[32];
3196	/** 16-bit view. */
3197	uint16_t au16[16];
3198	/** 32-bit view. */
3199	uint32_t au32[8];
3200	/** 64-bit view. */
3201	uint64_t au64[4];
3202	/** 128-bit view. (yeah, very helpful) */
3203	uint128_t au128[2];
3204	/** Single precision floating point view. */
3205	RTFLOAT32U ar32[8];
3206	/** Double precision floating point view. */
3207	RTFLOAT64U ar64[4];
3208	/** XMM sub register view. */
3209	X86XMMREG aXmm[2];
3210	} X86YMMREG;
3211	#ifndef VBOX_FOR_DTRACE_LIB
3212	AssertCompileSize(X86YMMREG, 32);
3213	#endif
3214	/** Pointer to an YMM register state. */
3215	typedef X86YMMREG *PX86YMMREG;
3216	/** Pointer to a const YMM register state. */
3217	typedef X86YMMREG const *PCX86YMMREG;
3218
3219	/**
3220	* ZMM register union.
3221	*/
3222	typedef union X86ZMMREG
3223	{
3224	/** 8-bit view. */
3225	uint8_t au8[64];
3226	/** 16-bit view. */
3227	uint16_t au16[32];
3228	/** 32-bit view. */
3229	uint32_t au32[16];
3230	/** 64-bit view. */
3231	uint64_t au64[8];
3232	/** 128-bit view. (yeah, very helpful) */
3233	uint128_t au128[4];
3234	/** Single precision floating point view. */
3235	RTFLOAT32U ar32[16];
3236	/** Double precision floating point view. */
3237	RTFLOAT64U ar64[8];
3238	/** XMM sub register view. */
3239	X86XMMREG aXmm[4];
3240	/** YMM sub register view. */
3241	X86YMMREG aYmm[2];
3242	} X86ZMMREG;
3243	#ifndef VBOX_FOR_DTRACE_LIB
3244	AssertCompileSize(X86ZMMREG, 64);
3245	#endif
3246	/** Pointer to an ZMM register state. */
3247	typedef X86ZMMREG *PX86ZMMREG;
3248	/** Pointer to a const ZMM register state. */
3249	typedef X86ZMMREG const *PCX86ZMMREG;
3250
3251
3252	/**
3253	* 32-bit FPU state (aka FSAVE/FRSTOR Memory Region).
3254	*/
3255	#pragma pack(1)
3256	typedef struct X86FPUSTATE
3257	{
3258	/** 0x00 - Control word. */
3259	uint16_t FCW;
3260	/** 0x02 - Alignment word */
3261	uint16_t Dummy1;
3262	/** 0x04 - Status word. */
3263	uint16_t FSW;
3264	/** 0x06 - Alignment word */
3265	uint16_t Dummy2;
3266	/** 0x08 - Tag word */
3267	uint16_t FTW;
3268	/** 0x0a - Alignment word */
3269	uint16_t Dummy3;
3270
3271	/** 0x0c - Instruction pointer. */
3272	uint32_t FPUIP;
3273	/** 0x10 - Code selector. */
3274	uint16_t CS;
3275	/** 0x12 - Opcode. */
3276	uint16_t FOP;
3277	/** 0x14 - Data pointer. */
3278	uint32_t FPUOO;
3279	/** 0x18 - FOS. */
3280	uint16_t FPUOS;
3281	/** 0x0a - Alignment word */
3282	uint16_t Dummy4;
3283	/** 0x1c - FPU register. */
3284	X86FPUREG2 regs[8];
3285	} X86FPUSTATE;
3286	#pragma pack()
3287	AssertCompileSize(X86FPUSTATE, 108);
3288	/** Pointer to a FPU state. */
3289	typedef X86FPUSTATE *PX86FPUSTATE;
3290	/** Pointer to a const FPU state. */
3291	typedef const X86FPUSTATE *PCX86FPUSTATE;
3292
3293	/**
3294	* FPU Extended state (aka FXSAVE/FXRSTORE Memory Region).
3295	*/
3296	#pragma pack(1)
3297	typedef struct X86FXSTATE
3298	{
3299	/** 0x00 - Control word. */
3300	uint16_t FCW;
3301	/** 0x02 - Status word. */
3302	uint16_t FSW;
3303	/** 0x04 - Tag word. (The upper byte is always zero.) */
3304	uint16_t FTW;
3305	/** 0x06 - Opcode. */
3306	uint16_t FOP;
3307	/** 0x08 - Instruction pointer. */
3308	uint32_t FPUIP;
3309	/** 0x0c - Code selector. */
3310	uint16_t CS;
3311	uint16_t Rsrvd1;
3312	/** 0x10 - Data pointer. */
3313	uint32_t FPUDP;
3314	/** 0x14 - Data segment */
3315	uint16_t DS;
3316	/** 0x16 */
3317	uint16_t Rsrvd2;
3318	/** 0x18 */
3319	uint32_t MXCSR;
3320	/** 0x1c */
3321	uint32_t MXCSR_MASK;
3322	/** 0x20 - FPU registers. */
3323	X86FPUREG aRegs[8];
3324	/** 0xA0 - XMM registers - 8 registers in 32 bits mode, 16 in long mode. */
3325	X86XMMREG aXMM[16];
3326	/* - offset 416 - */
3327	uint32_t au32RsrvdRest[(464 - 416) / sizeof(uint32_t)];
3328	/* - offset 464 - Software usable reserved bits. */
3329	uint32_t au32RsrvdForSoftware[(512 - 464) / sizeof(uint32_t)];
3330	} X86FXSTATE;
3331	#pragma pack()
3332	/** Pointer to a FPU Extended state. */
3333	typedef X86FXSTATE *PX86FXSTATE;
3334	/** Pointer to a const FPU Extended state. */
3335	typedef const X86FXSTATE *PCX86FXSTATE;
3336
3337	/** Offset for software usable reserved bits (464:511) where we store a 32-bit
3338	* magic. Don't forget to update x86.mac if you change this! */
3339	#define X86_OFF_FXSTATE_RSVD 0x1d0
3340	/** The 32-bit magic used to recognize if this a 32-bit FPU state. Don't
3341	* forget to update x86.mac if you change this!
3342	* @todo r=bird: This has nothing what-so-ever to do here.... */
3343	#define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
3344	#ifndef VBOX_FOR_DTRACE_LIB
3345	AssertCompileSize(X86FXSTATE, 512);
3346	AssertCompileMemberOffset(X86FXSTATE, au32RsrvdForSoftware, X86_OFF_FXSTATE_RSVD);
3347	#endif
3348
3349	/** @name FPU status word flags.
3350	* @{ */
3351	/** Exception Flag: Invalid operation. */
3352	#define X86_FSW_IE RT_BIT_32(0)
3353	#define X86_FSW_IE_BIT 0
3354	/** Exception Flag: Denormalized operand. */
3355	#define X86_FSW_DE RT_BIT_32(1)
3356	#define X86_FSW_DE_BIT 1
3357	/** Exception Flag: Zero divide. */
3358	#define X86_FSW_ZE RT_BIT_32(2)
3359	#define X86_FSW_ZE_BIT 2
3360	/** Exception Flag: Overflow. */
3361	#define X86_FSW_OE RT_BIT_32(3)
3362	#define X86_FSW_OE_BIT 3
3363	/** Exception Flag: Underflow. */
3364	#define X86_FSW_UE RT_BIT_32(4)
3365	#define X86_FSW_UE_BIT 4
3366	/** Exception Flag: Precision. */
3367	#define X86_FSW_PE RT_BIT_32(5)
3368	#define X86_FSW_PE_BIT 5
3369	/** Stack fault. */
3370	#define X86_FSW_SF RT_BIT_32(6)
3371	#define X86_FSW_SF_BIT 6
3372	/** Error summary status. */
3373	#define X86_FSW_ES RT_BIT_32(7)
3374	#define X86_FSW_ES_BIT 7
3375	/** Mask of exceptions flags, excluding the summary bit. */
3376	#define X86_FSW_XCPT_MASK UINT16_C(0x007f)
3377	/** Mask of exceptions flags, including the summary bit. */
3378	#define X86_FSW_XCPT_ES_MASK UINT16_C(0x00ff)
3379	/** Condition code 0. */
3380	#define X86_FSW_C0 RT_BIT_32(X86_FSW_C0_BIT)
3381	#define X86_FSW_C0_BIT 8
3382	/** Condition code 1. */
3383	#define X86_FSW_C1 RT_BIT_32(X86_FSW_C1_BIT)
3384	#define X86_FSW_C1_BIT 9
3385	/** Condition code 2. */
3386	#define X86_FSW_C2 RT_BIT_32(X86_FSW_C2_BIT)
3387	#define X86_FSW_C2_BIT 10
3388	/** Top of the stack mask. */
3389	#define X86_FSW_TOP_MASK UINT16_C(0x3800)
3390	/** TOP shift value. */
3391	#define X86_FSW_TOP_SHIFT 11
3392	/** Mask for getting TOP value after shifting it right. */
3393	#define X86_FSW_TOP_SMASK UINT16_C(0x0007)
3394	/** Get the TOP value. */
3395	#define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
3396	/** Get the TOP value offsetted by a_iSt (0-7). */
3397	#define X86_FSW_TOP_GET_ST(a_uFsw, a_iSt) ((((a_uFsw) >> X86_FSW_TOP_SHIFT) + (a_iSt)) & X86_FSW_TOP_SMASK)
3398	/** Condition code 3. */
3399	#define X86_FSW_C3 RT_BIT_32(X86_FSW_C3_BIT)
3400	#define X86_FSW_C3_BIT 14
3401	/** Mask of exceptions flags, including the summary bit. */
3402	#define X86_FSW_C_MASK UINT16_C(0x4700)
3403	/** FPU busy. */
3404	#define X86_FSW_B RT_BIT_32(15)
3405	/** For use with FPREM and FPREM1. */
3406	#define X86_FSW_CX_TO_QUOTIENT(a_fFsw) \
3407	( (((a_fFsw) & X86_FSW_C1) >> (X86_FSW_C1_BIT - 0)) \
3408	\| (((a_fFsw) & X86_FSW_C3) >> (X86_FSW_C3_BIT - 1)) \
3409	\| (((a_fFsw) & X86_FSW_C0) >> (X86_FSW_C0_BIT - 2)) )
3410	/** For use with FPREM and FPREM1. */
3411	#define X86_FSW_CX_FROM_QUOTIENT(a_uQuotient) \
3412	( ((uint16_t)((a_uQuotient) & 1) << (X86_FSW_C1_BIT - 0)) \
3413	\| ((uint16_t)((a_uQuotient) & 2) << (X86_FSW_C3_BIT - 1)) \
3414	\| ((uint16_t)((a_uQuotient) & 4) << (X86_FSW_C0_BIT - 2)) )
3415	/** @} */
3416
3417
3418	/** @name FPU control word flags.
3419	* @{ */
3420	/** Exception Mask: Invalid operation. */
3421	#define X86_FCW_IM RT_BIT_32(0)
3422	#define X86_FCW_IM_BIT 0
3423	/** Exception Mask: Denormalized operand. */
3424	#define X86_FCW_DM RT_BIT_32(1)
3425	#define X86_FCW_DM_BIT 1
3426	/** Exception Mask: Zero divide. */
3427	#define X86_FCW_ZM RT_BIT_32(2)
3428	#define X86_FCW_ZM_BIT 2
3429	/** Exception Mask: Overflow. */
3430	#define X86_FCW_OM RT_BIT_32(3)
3431	#define X86_FCW_OM_BIT 3
3432	/** Exception Mask: Underflow. */
3433	#define X86_FCW_UM RT_BIT_32(4)
3434	#define X86_FCW_UM_BIT 4
3435	/** Exception Mask: Precision. */
3436	#define X86_FCW_PM RT_BIT_32(5)
3437	#define X86_FCW_PM_BIT 5
3438	/** Mask all exceptions, the value typically loaded (by for instance fninit).
3439	* @remarks This includes reserved bit 6. */
3440	#define X86_FCW_MASK_ALL UINT16_C(0x007f)
3441	/** Mask all exceptions. Same as X86_FSW_XCPT_MASK. */
3442	#define X86_FCW_XCPT_MASK UINT16_C(0x003f)
3443	/** Precision control mask. */
3444	#define X86_FCW_PC_MASK UINT16_C(0x0300)
3445	/** Precision control shift. */
3446	#define X86_FCW_PC_SHIFT 8
3447	/** Precision control: 24-bit. */
3448	#define X86_FCW_PC_24 UINT16_C(0x0000)
3449	/** Precision control: Reserved. */
3450	#define X86_FCW_PC_RSVD UINT16_C(0x0100)
3451	/** Precision control: 53-bit. */
3452	#define X86_FCW_PC_53 UINT16_C(0x0200)
3453	/** Precision control: 64-bit. */
3454	#define X86_FCW_PC_64 UINT16_C(0x0300)
3455	/** Rounding control mask. */
3456	#define X86_FCW_RC_MASK UINT16_C(0x0c00)
3457	/** Rounding control shift. */
3458	#define X86_FCW_RC_SHIFT 10
3459	/** Rounding control: To nearest. */
3460	#define X86_FCW_RC_NEAREST UINT16_C(0x0000)
3461	/** Rounding control: Down. */
3462	#define X86_FCW_RC_DOWN UINT16_C(0x0400)
3463	/** Rounding control: Up. */
3464	#define X86_FCW_RC_UP UINT16_C(0x0800)
3465	/** Rounding control: Towards zero. */
3466	#define X86_FCW_RC_ZERO UINT16_C(0x0c00)
3467	/** Infinity control mask - obsolete, 8087 & 287 only. */
3468	#define X86_FCW_IC_MASK UINT16_C(0x1000)
3469	/** Infinity control: Affine - positive infinity is distictly different from
3470	* negative infinity.
3471	* @note 8087, 287 only */
3472	#define X86_FCW_IC_AFFINE UINT16_C(0x1000)
3473	/** Infinity control: Projective - positive and negative infinity are the
3474	* same (sign ignored).
3475	* @note 8087, 287 only */
3476	#define X86_FCW_IC_PROJECTIVE UINT16_C(0x0000)
3477	/** Bits which should be zero, apparently. */
3478	#define X86_FCW_ZERO_MASK UINT16_C(0xf080)
3479	/** @} */
3480
3481	/** @name SSE MXCSR
3482	* @{ */
3483	/** Exception Flag: Invalid operation. */
3484	#define X86_MXCSR_IE RT_BIT_32(0)
3485	/** Exception Flag: Denormalized operand. */
3486	#define X86_MXCSR_DE RT_BIT_32(1)
3487	/** Exception Flag: Zero divide. */
3488	#define X86_MXCSR_ZE RT_BIT_32(2)
3489	/** Exception Flag: Overflow. */
3490	#define X86_MXCSR_OE RT_BIT_32(3)
3491	/** Exception Flag: Underflow. */
3492	#define X86_MXCSR_UE RT_BIT_32(4)
3493	/** Exception Flag: Precision. */
3494	#define X86_MXCSR_PE RT_BIT_32(5)
3495	/** Exception Flags: mask */
3496	#define X86_MXCSR_XCPT_FLAGS UINT32_C(0x003f)
3497
3498	/** Denormals are zero. */
3499	#define X86_MXCSR_DAZ RT_BIT_32(6)
3500
3501	/** Exception Mask: Invalid operation. */
3502	#define X86_MXCSR_IM RT_BIT_32(7)
3503	/** Exception Mask: Denormalized operand. */
3504	#define X86_MXCSR_DM RT_BIT_32(8)
3505	/** Exception Mask: Zero divide. */
3506	#define X86_MXCSR_ZM RT_BIT_32(9)
3507	/** Exception Mask: Overflow. */
3508	#define X86_MXCSR_OM RT_BIT_32(10)
3509	/** Exception Mask: Underflow. */
3510	#define X86_MXCSR_UM RT_BIT_32(11)
3511	/** Exception Mask: Precision. */
3512	#define X86_MXCSR_PM RT_BIT_32(12)
3513	/** Exception Mask: mask. */
3514	#define X86_MXCSR_XCPT_MASK UINT32_C(0x1f80)
3515	/** Exception Mask: shift. */
3516	#define X86_MXCSR_XCPT_MASK_SHIFT 7
3517
3518	/** Rounding control mask. */
3519	#define X86_MXCSR_RC_MASK UINT32_C(0x6000)
3520	/** Rounding control shift. */
3521	#define X86_MXCSR_RC_SHIFT 13
3522	/** Rounding control: To nearest. */
3523	#define X86_MXCSR_RC_NEAREST UINT32_C(0x0000)
3524	/** Rounding control: Down. */
3525	#define X86_MXCSR_RC_DOWN UINT32_C(0x2000)
3526	/** Rounding control: Up. */
3527	#define X86_MXCSR_RC_UP UINT32_C(0x4000)
3528	/** Rounding control: Towards zero. */
3529	#define X86_MXCSR_RC_ZERO UINT32_C(0x6000)
3530
3531	/** Flush-to-zero for masked underflow. */
3532	#define X86_MXCSR_FZ RT_BIT_32(15)
3533
3534	/** Misaligned Exception Mask (AMD MISALIGNSSE). */
3535	#define X86_MXCSR_MM RT_BIT_32(17)
3536	/** Bits which should be zero, apparently. */
3537	#define X86_MXCSR_ZERO_MASK UINT32_C(0xfffd0000)
3538	/** @} */
3539
3540	/**
3541	* XSAVE header.
3542	*/
3543	typedef struct X86XSAVEHDR
3544	{
3545	/** XTATE_BV - Bitmap indicating whether a component is in the state. */
3546	uint64_t bmXState;
3547	/** XCOMP_BC - Bitmap used by instructions applying structure compaction. */
3548	uint64_t bmXComp;
3549	/** Reserved for furture extensions, probably MBZ. */
3550	uint64_t au64Reserved[6];
3551	} X86XSAVEHDR;
3552	#ifndef VBOX_FOR_DTRACE_LIB
3553	AssertCompileSize(X86XSAVEHDR, 64);
3554	#endif
3555	/** Pointer to an XSAVE header. */
3556	typedef X86XSAVEHDR *PX86XSAVEHDR;
3557	/** Pointer to a const XSAVE header. */
3558	typedef X86XSAVEHDR const *PCX86XSAVEHDR;
3559
3560
3561	/**
3562	* The high 128-bit YMM register state (XSAVE_C_YMM).
3563	* (The lower 128-bits being in X86FXSTATE.)
3564	*/
3565	typedef struct X86XSAVEYMMHI
3566	{
3567	/** 16 registers in 64-bit mode, 8 in 32-bit mode. */
3568	X86XMMREG aYmmHi[16];
3569	} X86XSAVEYMMHI;
3570	#ifndef VBOX_FOR_DTRACE_LIB
3571	AssertCompileSize(X86XSAVEYMMHI, 256);
3572	#endif
3573	/** Pointer to a high 128-bit YMM register state. */
3574	typedef X86XSAVEYMMHI *PX86XSAVEYMMHI;
3575	/** Pointer to a const high 128-bit YMM register state. */
3576	typedef X86XSAVEYMMHI const *PCX86XSAVEYMMHI;
3577
3578	/**
3579	* Intel MPX bound registers state (XSAVE_C_BNDREGS).
3580	*/
3581	typedef struct X86XSAVEBNDREGS
3582	{
3583	/** Array of registers (BND0...BND3). */
3584	struct
3585	{
3586	/** Lower bound. */
3587	uint64_t uLowerBound;
3588	/** Upper bound. */
3589	uint64_t uUpperBound;
3590	} aRegs[4];
3591	} X86XSAVEBNDREGS;
3592	#ifndef VBOX_FOR_DTRACE_LIB
3593	AssertCompileSize(X86XSAVEBNDREGS, 64);
3594	#endif
3595	/** Pointer to a MPX bound register state. */
3596	typedef X86XSAVEBNDREGS *PX86XSAVEBNDREGS;
3597	/** Pointer to a const MPX bound register state. */
3598	typedef X86XSAVEBNDREGS const *PCX86XSAVEBNDREGS;
3599
3600	/**
3601	* Intel MPX bound config and status register state (XSAVE_C_BNDCSR).
3602	*/
3603	typedef struct X86XSAVEBNDCFG
3604	{
3605	uint64_t fConfig;
3606	uint64_t fStatus;
3607	} X86XSAVEBNDCFG;
3608	#ifndef VBOX_FOR_DTRACE_LIB
3609	AssertCompileSize(X86XSAVEBNDCFG, 16);
3610	#endif
3611	/** Pointer to a MPX bound config and status register state. */
3612	typedef X86XSAVEBNDCFG *PX86XSAVEBNDCFG;
3613	/** Pointer to a const MPX bound config and status register state. */
3614	typedef X86XSAVEBNDCFG *PCX86XSAVEBNDCFG;
3615
3616	/**
3617	* AVX-512 opmask state (XSAVE_C_OPMASK).
3618	*/
3619	typedef struct X86XSAVEOPMASK
3620	{
3621	/** The K0..K7 values. */
3622	uint64_t aKRegs[8];
3623	} X86XSAVEOPMASK;
3624	#ifndef VBOX_FOR_DTRACE_LIB
3625	AssertCompileSize(X86XSAVEOPMASK, 64);
3626	#endif
3627	/** Pointer to a AVX-512 opmask state. */
3628	typedef X86XSAVEOPMASK *PX86XSAVEOPMASK;
3629	/** Pointer to a const AVX-512 opmask state. */
3630	typedef X86XSAVEOPMASK const *PCX86XSAVEOPMASK;
3631
3632	/**
3633	* ZMM0-15 upper 256 bits introduced in AVX-512 (XSAVE_C_ZMM_HI256).
3634	*/
3635	typedef struct X86XSAVEZMMHI256
3636	{
3637	/** Upper 256-bits of ZMM0-15. */
3638	X86YMMREG aHi256Regs[16];
3639	} X86XSAVEZMMHI256;
3640	#ifndef VBOX_FOR_DTRACE_LIB
3641	AssertCompileSize(X86XSAVEZMMHI256, 512);
3642	#endif
3643	/** Pointer to a state comprising the upper 256-bits of ZMM0-15. */
3644	typedef X86XSAVEZMMHI256 *PX86XSAVEZMMHI256;
3645	/** Pointer to a const state comprising the upper 256-bits of ZMM0-15. */
3646	typedef X86XSAVEZMMHI256 const *PCX86XSAVEZMMHI256;
3647
3648	/**
3649	* ZMM16-31 register state introduced in AVX-512 (XSAVE_C_ZMM_16HI).
3650	*/
3651	typedef struct X86XSAVEZMM16HI
3652	{
3653	/** ZMM16 thru ZMM31. */
3654	X86ZMMREG aRegs[16];
3655	} X86XSAVEZMM16HI;
3656	#ifndef VBOX_FOR_DTRACE_LIB
3657	AssertCompileSize(X86XSAVEZMM16HI, 1024);
3658	#endif
3659	/** Pointer to a state comprising ZMM16-32. */
3660	typedef X86XSAVEZMM16HI *PX86XSAVEZMM16HI;
3661	/** Pointer to a const state comprising ZMM16-32. */
3662	typedef X86XSAVEZMM16HI const *PCX86XSAVEZMM16HI;
3663
3664	/**
3665	* AMD Light weight profiling state (XSAVE_C_LWP).
3666	*
3667	* We probably won't play with this as AMD seems to be dropping from their "zen"
3668	* processor micro architecture.
3669	*/
3670	typedef struct X86XSAVELWP
3671	{
3672	/** Details when needed. */
3673	uint64_t auLater[128/8];
3674	} X86XSAVELWP;
3675	#ifndef VBOX_FOR_DTRACE_LIB
3676	AssertCompileSize(X86XSAVELWP, 128);
3677	#endif
3678
3679
3680	/**
3681	* x86 FPU/SSE/AVX/XXXX state.
3682	*
3683	* Please bump DBGFCORE_FMT_VERSION by 1 in dbgfcorefmt.h if you make any
3684	* changes to this structure.
3685	*/
3686	typedef struct X86XSAVEAREA
3687	{
3688	/** The x87 and SSE region (or legacy region if you like). */
3689	X86FXSTATE x87;
3690	/** The XSAVE header. */
3691	X86XSAVEHDR Hdr;
3692	/** Beyond the header, there isn't really a fixed layout, but we can
3693	generally assume the YMM (AVX) register extensions are present and
3694	follows immediately. */
3695	union
3696	{
3697	/** The high 128-bit AVX registers for easy access by IEM.
3698	* @note This ASSUMES they will always be here... */
3699	X86XSAVEYMMHI YmmHi;
3700
3701	/** This is a typical layout on intel CPUs (good for debuggers). */
3702	struct
3703	{
3704	X86XSAVEYMMHI YmmHi;
3705	X86XSAVEBNDREGS BndRegs;
3706	X86XSAVEBNDCFG BndCfg;
3707	uint8_t abFudgeToMatchDocs[0xB0];
3708	X86XSAVEOPMASK Opmask;
3709	X86XSAVEZMMHI256 ZmmHi256;
3710	X86XSAVEZMM16HI Zmm16Hi;
3711	} Intel;
3712
3713	/** This is a typical layout on AMD Bulldozer type CPUs (good for debuggers). */
3714	struct
3715	{
3716	X86XSAVEYMMHI YmmHi;
3717	X86XSAVELWP Lwp;
3718	} AmdBd;
3719
3720	/** To enbling static deployments that have a reasonable chance of working for
3721	* the next 3-6 CPU generations without running short on space, we allocate a
3722	* lot of extra space here, making the structure a round 8KB in size. This
3723	* leaves us 7616 bytes for extended state. The skylake xeons are likely to use
3724	* 2112 of these, leaving us with 5504 bytes for future Intel generations. */
3725	uint8_t ab[8192 - 512 - 64];
3726	} u;
3727	} X86XSAVEAREA;
3728	#ifndef VBOX_FOR_DTRACE_LIB
3729	AssertCompileSize(X86XSAVEAREA, 8192);
3730	AssertCompileMemberSize(X86XSAVEAREA, u.Intel, 0x840 /2112 => total 0xa80 (2688) /);
3731	AssertCompileMemberOffset(X86XSAVEAREA, Hdr, 0x200);
3732	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.YmmHi, 0x240);
3733	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndRegs, 0x340);
3734	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.BndCfg, 0x380);
3735	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Opmask, 0x440 /* 1088 */);
3736	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.ZmmHi256, 0x480 /* 1152 */);
3737	AssertCompileMemberOffset(X86XSAVEAREA, u.Intel.Zmm16Hi, 0x680 /* 1664 */);
3738	#endif
3739	/** Pointer to a XSAVE area. */
3740	typedef X86XSAVEAREA *PX86XSAVEAREA;
3741	/** Pointer to a const XSAVE area. */
3742	typedef X86XSAVEAREA const *PCX86XSAVEAREA;
3743
3744
3745	/** @name XSAVE_C_XXX - XSAVE State Components Bits (XCR0).
3746	* @{ */
3747	/** Bit 0 - x87 - Legacy FPU state (bit number) */
3748	#define XSAVE_C_X87_BIT 0
3749	/** Bit 0 - x87 - Legacy FPU state. */
3750	#define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
3751	/** Bit 1 - SSE - 128-bit SSE state (bit number). */
3752	#define XSAVE_C_SSE_BIT 1
3753	/** Bit 1 - SSE - 128-bit SSE state. */
3754	#define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
3755	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX) (bit number). */
3756	#define XSAVE_C_YMM_BIT 2
3757	/** Bit 2 - YMM_Hi128 - Upper 128 bits of YMM0-15 (AVX). */
3758	#define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
3759	/** Bit 3 - BNDREGS - MPX bound register state (bit number). */
3760	#define XSAVE_C_BNDREGS_BIT 3
3761	/** Bit 3 - BNDREGS - MPX bound register state. */
3762	#define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
3763	/** Bit 4 - BNDCSR - MPX bound config and status state (bit number). */
3764	#define XSAVE_C_BNDCSR_BIT 4
3765	/** Bit 4 - BNDCSR - MPX bound config and status state. */
3766	#define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
3767	/** Bit 5 - Opmask - opmask state (bit number). */
3768	#define XSAVE_C_OPMASK_BIT 5
3769	/** Bit 5 - Opmask - opmask state. */
3770	#define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
3771	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512) (bit number). */
3772	#define XSAVE_C_ZMM_HI256_BIT 6
3773	/** Bit 6 - ZMM_Hi256 - Upper 256 bits of ZMM0-15 (AVX-512). */
3774	#define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
3775	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512) (bit number). */
3776	#define XSAVE_C_ZMM_16HI_BIT 7
3777	/** Bit 7 - Hi16_ZMM - 512-bits ZMM16-31 state (AVX-512). */
3778	#define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
3779	/** Bit 9 - PKRU - Protection-key state (bit number). */
3780	#define XSAVE_C_PKRU_BIT 9
3781	/** Bit 9 - PKRU - Protection-key state. */
3782	#define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
3783	/** Bit 62 - LWP - Lightweight Profiling (AMD) (bit number). */
3784	#define XSAVE_C_LWP_BIT 62
3785	/** Bit 62 - LWP - Lightweight Profiling (AMD). */
3786	#define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
3787	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (bit number). */
3788	#define XSAVE_C_X_BIT 63
3789	/** Bit 63 - X - Reserved (MBZ) for extending XCR0 (AMD). */
3790	#define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
3791	/** @} */
3792
3793
3794
3795	/** @name Selector Descriptor
3796	* @{
3797	*/
3798
3799	#ifndef VBOX_FOR_DTRACE_LIB
3800	/**
3801	* Descriptor attributes (as seen by VT-x).
3802	*/
3803	typedef struct X86DESCATTRBITS
3804	{
3805	/** 00 - Segment Type. */
3806	unsigned u4Type : 4;
3807	/** 04 - Descriptor Type. System(=0) or code/data selector */
3808	unsigned u1DescType : 1;
3809	/** 05 - Descriptor Privilege level. */
3810	unsigned u2Dpl : 2;
3811	/** 07 - Flags selector present(=1) or not. */
3812	unsigned u1Present : 1;
3813	/** 08 - Segment limit 16-19. */
3814	unsigned u4LimitHigh : 4;
3815	/** 0c - Available for system software. */
3816	unsigned u1Available : 1;
3817	/** 0d - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3818	unsigned u1Long : 1;
3819	/** 0e - This flags meaning depends on the segment type. Try make sense out
3820	* of the intel manual yourself. */
3821	unsigned u1DefBig : 1;
3822	/** 0f - Granularity of the limit. If set 4KB granularity is used, if
3823	* clear byte. */
3824	unsigned u1Granularity : 1;
3825	/** 10 - "Unusable" selector, special Intel (VT-x only?) bit. */
3826	unsigned u1Unusable : 1;
3827	} X86DESCATTRBITS;
3828	#endif /* !VBOX_FOR_DTRACE_LIB */
3829
3830	/** @name X86DESCATTR masks
3831	* @{ */
3832	#define X86DESCATTR_TYPE UINT32_C(0x0000000f)
3833	#define X86DESCATTR_DT UINT32_C(0x00000010)
3834	#define X86DESCATTR_DPL UINT32_C(0x00000060)
3835	#define X86DESCATTR_DPL_SHIFT 5 /*< Shift count for the DPL value. /
3836	#define X86DESCATTR_P UINT32_C(0x00000080)
3837	#define X86DESCATTR_LIMIT_HIGH UINT32_C(0x00000f00)
3838	#define X86DESCATTR_AVL UINT32_C(0x00001000)
3839	#define X86DESCATTR_L UINT32_C(0x00002000)
3840	#define X86DESCATTR_D UINT32_C(0x00004000)
3841	#define X86DESCATTR_G UINT32_C(0x00008000)
3842	#define X86DESCATTR_UNUSABLE UINT32_C(0x00010000)
3843	/** @} */
3844
3845	#pragma pack(1)
3846	typedef union X86DESCATTR
3847	{
3848	/** Unsigned integer view. */
3849	uint32_t u;
3850	#ifndef VBOX_FOR_DTRACE_LIB
3851	/** Normal view. */
3852	X86DESCATTRBITS n;
3853	#endif
3854	} X86DESCATTR;
3855	#pragma pack()
3856	/** Pointer to descriptor attributes. */
3857	typedef X86DESCATTR *PX86DESCATTR;
3858	/** Pointer to const descriptor attributes. */
3859	typedef const X86DESCATTR *PCX86DESCATTR;
3860
3861	#ifndef VBOX_FOR_DTRACE_LIB
3862
3863	/**
3864	* Generic descriptor table entry
3865	*/
3866	#pragma pack(1)
3867	typedef struct X86DESCGENERIC
3868	{
3869	/** 00 - Limit - Low word. */
3870	unsigned u16LimitLow : 16;
3871	/** 10 - Base address - low word.
3872	* Don't try set this to 24 because MSC is doing stupid things then. */
3873	unsigned u16BaseLow : 16;
3874	/** 20 - Base address - first 8 bits of high word. */
3875	unsigned u8BaseHigh1 : 8;
3876	/** 28 - Segment Type. */
3877	unsigned u4Type : 4;
3878	/** 2c - Descriptor Type. System(=0) or code/data selector */
3879	unsigned u1DescType : 1;
3880	/** 2d - Descriptor Privilege level. */
3881	unsigned u2Dpl : 2;
3882	/** 2f - Flags selector present(=1) or not. */
3883	unsigned u1Present : 1;
3884	/** 30 - Segment limit 16-19. */
3885	unsigned u4LimitHigh : 4;
3886	/** 34 - Available for system software. */
3887	unsigned u1Available : 1;
3888	/** 35 - 32 bits mode: Reserved - 0, long mode: Long Attribute Bit. */
3889	unsigned u1Long : 1;
3890	/** 36 - This flags meaning depends on the segment type. Try make sense out
3891	* of the intel manual yourself. */
3892	unsigned u1DefBig : 1;
3893	/** 37 - Granularity of the limit. If set 4KB granularity is used, if
3894	* clear byte. */
3895	unsigned u1Granularity : 1;
3896	/** 38 - Base address - highest 8 bits. */
3897	unsigned u8BaseHigh2 : 8;
3898	} X86DESCGENERIC;
3899	#pragma pack()
3900	/** Pointer to a generic descriptor entry. */
3901	typedef X86DESCGENERIC *PX86DESCGENERIC;
3902	/** Pointer to a const generic descriptor entry. */
3903	typedef const X86DESCGENERIC *PCX86DESCGENERIC;
3904
3905	/** @name Bit offsets of X86DESCGENERIC members.
3906	* @{*/
3907	#define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0) /*< Bit offset of X86DESCGENERIC::u16LimitLow. /
3908	#define X86DESCGENERIC_BIT_OFF_BASE_LOW (16) /*< Bit offset of X86DESCGENERIC::u16BaseLow. /
3909	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32) /*< Bit offset of X86DESCGENERIC::u8BaseHigh1. /
3910	#define X86DESCGENERIC_BIT_OFF_TYPE (40) /*< Bit offset of X86DESCGENERIC::u4Type. /
3911	#define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44) /*< Bit offset of X86DESCGENERIC::u1DescType. /
3912	#define X86DESCGENERIC_BIT_OFF_DPL (45) /*< Bit offset of X86DESCGENERIC::u2Dpl. /
3913	#define X86DESCGENERIC_BIT_OFF_PRESENT (47) /*< Bit offset of X86DESCGENERIC::uu1Present. /
3914	#define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48) /*< Bit offset of X86DESCGENERIC::u4LimitHigh. /
3915	#define X86DESCGENERIC_BIT_OFF_AVAILABLE (52) /*< Bit offset of X86DESCGENERIC::u1Available. /
3916	#define X86DESCGENERIC_BIT_OFF_LONG (53) /*< Bit offset of X86DESCGENERIC::u1Long. /
3917	#define X86DESCGENERIC_BIT_OFF_DEF_BIG (54) /*< Bit offset of X86DESCGENERIC::u1DefBig. /
3918	#define X86DESCGENERIC_BIT_OFF_GRANULARITY (55) /*< Bit offset of X86DESCGENERIC::u1Granularity. /
3919	#define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56) /*< Bit offset of X86DESCGENERIC::u8BaseHigh2. /
3920	/** @} */
3921
3922
3923	/** @name LAR mask
3924	* @{ */
3925	#define X86LAR_F_TYPE UINT16_C( 0x0f00)
3926	#define X86LAR_F_DT UINT16_C( 0x1000)
3927	#define X86LAR_F_DPL UINT16_C( 0x6000)
3928	#define X86LAR_F_DPL_SHIFT 13 /*< Shift count for the DPL value. /
3929	#define X86LAR_F_P UINT16_C( 0x8000)
3930	#define X86LAR_F_AVL UINT32_C(0x00100000)
3931	#define X86LAR_F_L UINT32_C(0x00200000)
3932	#define X86LAR_F_D UINT32_C(0x00400000)
3933	#define X86LAR_F_G UINT32_C(0x00800000)
3934	/** @} */
3935
3936
3937	/**
3938	* Call-, Interrupt-, Trap- or Task-gate descriptor (legacy).
3939	*/
3940	typedef struct X86DESCGATE
3941	{
3942	/** 00 - Target code segment offset - Low word.
3943	* Ignored if task-gate. */
3944	unsigned u16OffsetLow : 16;
3945	/** 10 - Target code segment selector for call-, interrupt- and trap-gates,
3946	* TSS selector if task-gate. */
3947	unsigned u16Sel : 16;
3948	/** 20 - Number of parameters for a call-gate.
3949	* Ignored if interrupt-, trap- or task-gate. */
3950	unsigned u5ParmCount : 5;
3951	/** 25 - Reserved / ignored. */
3952	unsigned u3Reserved : 3;
3953	/** 28 - Segment Type. */
3954	unsigned u4Type : 4;
3955	/** 2c - Descriptor Type (0 = system). */
3956	unsigned u1DescType : 1;
3957	/** 2d - Descriptor Privilege level. */
3958	unsigned u2Dpl : 2;
3959	/** 2f - Flags selector present(=1) or not. */
3960	unsigned u1Present : 1;
3961	/** 30 - Target code segment offset - High word.
3962	* Ignored if task-gate. */
3963	unsigned u16OffsetHigh : 16;
3964	} X86DESCGATE;
3965	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3966	typedef X86DESCGATE *PX86DESCGATE;
3967	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
3968	typedef const X86DESCGATE *PCX86DESCGATE;
3969
3970	#endif /* VBOX_FOR_DTRACE_LIB */
3971
3972	/**
3973	* Descriptor table entry.
3974	*/
3975	#pragma pack(1)
3976	typedef union X86DESC
3977	{
3978	#ifndef VBOX_FOR_DTRACE_LIB
3979	/** Generic descriptor view. */
3980	X86DESCGENERIC Gen;
3981	/** Gate descriptor view. */
3982	X86DESCGATE Gate;
3983	#endif
3984
3985	/** 8 bit unsigned integer view. */
3986	uint8_t au8[8];
3987	/** 16 bit unsigned integer view. */
3988	uint16_t au16[4];
3989	/** 32 bit unsigned integer view. */
3990	uint32_t au32[2];
3991	/** 64 bit unsigned integer view. */
3992	uint64_t au64[1];
3993	/** Unsigned integer view. */
3994	uint64_t u;
3995	} X86DESC;
3996	#ifndef VBOX_FOR_DTRACE_LIB
3997	AssertCompileSize(X86DESC, 8);
3998	#endif
3999	#pragma pack()
4000	/** Pointer to descriptor table entry. */
4001	typedef X86DESC *PX86DESC;
4002	/** Pointer to const descriptor table entry. */
4003	typedef const X86DESC *PCX86DESC;
4004
4005	/** @def X86DESC_BASE
4006	* Return the base address of a descriptor.
4007	*/
4008	#define X86DESC_BASE(a_pDesc) /ASM-NOINC/ \
4009	( ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4010	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4011	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4012
4013	/** @def X86DESC_LIMIT
4014	* Return the limit of a descriptor.
4015	*/
4016	#define X86DESC_LIMIT(a_pDesc) /ASM-NOINC/ \
4017	( ((uint32_t)((a_pDesc)->Gen.u4LimitHigh) << 16) \
4018	\| ( (a_pDesc)->Gen.u16LimitLow ) )
4019
4020	/** @def X86DESC_LIMIT_G
4021	* Return the limit of a descriptor with the granularity bit taken into account.
4022	* @returns Selector limit (uint32_t).
4023	* @param a_pDesc Pointer to the descriptor.
4024	*/
4025	#define X86DESC_LIMIT_G(a_pDesc) /ASM-NOINC/ \
4026	( (a_pDesc)->Gen.u1Granularity \
4027	? ( ( ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow ) << 12 ) \| UINT32_C(0xfff) \
4028	: ((uint32_t)(a_pDesc)->Gen.u4LimitHigh << 16) \| (a_pDesc)->Gen.u16LimitLow \
4029	)
4030
4031	/** @def X86DESC_GET_HID_ATTR
4032	* Get the descriptor attributes for the hidden register.
4033	*/
4034	#define X86DESC_GET_HID_ATTR(a_pDesc) /ASM-NOINC/ \
4035	( ((a_pDesc)->u >> (16+16+8)) & UINT32_C(0xf0ff) ) /** @todo do we have a define for 0xf0ff? */
4036
4037	#ifndef VBOX_FOR_DTRACE_LIB
4038
4039	/**
4040	* 64 bits generic descriptor table entry
4041	* Note: most of these bits have no meaning in long mode.
4042	*/
4043	#pragma pack(1)
4044	typedef struct X86DESC64GENERIC
4045	{
4046	/** Limit - Low word - IGNORED. */
4047	uint32_t u16LimitLow : 16;
4048	/** Base address - low word. - IGNORED
4049	* Don't try set this to 24 because MSC is doing stupid things then. */
4050	uint32_t u16BaseLow : 16;
4051	/** Base address - first 8 bits of high word. - IGNORED */
4052	uint32_t u8BaseHigh1 : 8;
4053	/** Segment Type. */
4054	uint32_t u4Type : 4;
4055	/** Descriptor Type. System(=0) or code/data selector */
4056	uint32_t u1DescType : 1;
4057	/** Descriptor Privilege level. */
4058	uint32_t u2Dpl : 2;
4059	/** Flags selector present(=1) or not. */
4060	uint32_t u1Present : 1;
4061	/** Segment limit 16-19. - IGNORED */
4062	uint32_t u4LimitHigh : 4;
4063	/** Available for system software. - IGNORED */
4064	uint32_t u1Available : 1;
4065	/** Long mode flag. */
4066	uint32_t u1Long : 1;
4067	/** This flags meaning depends on the segment type. Try make sense out
4068	* of the intel manual yourself. */
4069	uint32_t u1DefBig : 1;
4070	/** Granularity of the limit. If set 4KB granularity is used, if
4071	* clear byte. - IGNORED */
4072	uint32_t u1Granularity : 1;
4073	/** Base address - highest 8 bits. - IGNORED */
4074	uint32_t u8BaseHigh2 : 8;
4075	/** Base address - bits 63-32. */
4076	uint32_t u32BaseHigh3 : 32;
4077	uint32_t u8Reserved : 8;
4078	uint32_t u5Zeros : 5;
4079	uint32_t u19Reserved : 19;
4080	} X86DESC64GENERIC;
4081	#pragma pack()
4082	/** Pointer to a generic descriptor entry. */
4083	typedef X86DESC64GENERIC *PX86DESC64GENERIC;
4084	/** Pointer to a const generic descriptor entry. */
4085	typedef const X86DESC64GENERIC *PCX86DESC64GENERIC;
4086
4087	/**
4088	* System descriptor table entry (64 bits)
4089	*
4090	* @remarks This is, save a couple of comments, identical to X86DESC64GENERIC...
4091	*/
4092	#pragma pack(1)
4093	typedef struct X86DESC64SYSTEM
4094	{
4095	/** Limit - Low word. */
4096	uint32_t u16LimitLow : 16;
4097	/** Base address - low word.
4098	* Don't try set this to 24 because MSC is doing stupid things then. */
4099	uint32_t u16BaseLow : 16;
4100	/** Base address - first 8 bits of high word. */
4101	uint32_t u8BaseHigh1 : 8;
4102	/** Segment Type. */
4103	uint32_t u4Type : 4;
4104	/** Descriptor Type. System(=0) or code/data selector */
4105	uint32_t u1DescType : 1;
4106	/** Descriptor Privilege level. */
4107	uint32_t u2Dpl : 2;
4108	/** Flags selector present(=1) or not. */
4109	uint32_t u1Present : 1;
4110	/** Segment limit 16-19. */
4111	uint32_t u4LimitHigh : 4;
4112	/** Available for system software. */
4113	uint32_t u1Available : 1;
4114	/** Reserved - 0. */
4115	uint32_t u1Reserved : 1;
4116	/** This flags meaning depends on the segment type. Try make sense out
4117	* of the intel manual yourself. */
4118	uint32_t u1DefBig : 1;
4119	/** Granularity of the limit. If set 4KB granularity is used, if
4120	* clear byte. */
4121	uint32_t u1Granularity : 1;
4122	/** Base address - bits 31-24. */
4123	uint32_t u8BaseHigh2 : 8;
4124	/** Base address - bits 63-32. */
4125	uint32_t u32BaseHigh3 : 32;
4126	uint32_t u8Reserved : 8;
4127	uint32_t u5Zeros : 5;
4128	uint32_t u19Reserved : 19;
4129	} X86DESC64SYSTEM;
4130	#pragma pack()
4131	/** Pointer to a system descriptor entry. */
4132	typedef X86DESC64SYSTEM *PX86DESC64SYSTEM;
4133	/** Pointer to a const system descriptor entry. */
4134	typedef const X86DESC64SYSTEM *PCX86DESC64SYSTEM;
4135
4136	/**
4137	* Call-, Interrupt-, Trap- or Task-gate descriptor (64-bit).
4138	*/
4139	typedef struct X86DESC64GATE
4140	{
4141	/** Target code segment offset - Low word. */
4142	uint32_t u16OffsetLow : 16;
4143	/** Target code segment selector. */
4144	uint32_t u16Sel : 16;
4145	/** Interrupt stack table for interrupt- and trap-gates.
4146	* Ignored by call-gates. */
4147	uint32_t u3IST : 3;
4148	/** Reserved / ignored. */
4149	uint32_t u5Reserved : 5;
4150	/** Segment Type. */
4151	uint32_t u4Type : 4;
4152	/** Descriptor Type (0 = system). */
4153	uint32_t u1DescType : 1;
4154	/** Descriptor Privilege level. */
4155	uint32_t u2Dpl : 2;
4156	/** Flags selector present(=1) or not. */
4157	uint32_t u1Present : 1;
4158	/** Target code segment offset - High word.
4159	* Ignored if task-gate. */
4160	uint32_t u16OffsetHigh : 16;
4161	/** Target code segment offset - Top dword.
4162	* Ignored if task-gate. */
4163	uint32_t u32OffsetTop : 32;
4164	/** Reserved / ignored / must be zero.
4165	* For call-gates bits 8 thru 12 must be zero, the other gates ignores this. */
4166	uint32_t u32Reserved : 32;
4167	} X86DESC64GATE;
4168	AssertCompileSize(X86DESC64GATE, 16);
4169	/** Pointer to a Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4170	typedef X86DESC64GATE *PX86DESC64GATE;
4171	/** Pointer to a const Call-, Interrupt-, Trap- or Task-gate descriptor entry. */
4172	typedef const X86DESC64GATE *PCX86DESC64GATE;
4173
4174	#endif /* VBOX_FOR_DTRACE_LIB */
4175
4176	/**
4177	* Descriptor table entry.
4178	*/
4179	#pragma pack(1)
4180	typedef union X86DESC64
4181	{
4182	#ifndef VBOX_FOR_DTRACE_LIB
4183	/** Generic descriptor view. */
4184	X86DESC64GENERIC Gen;
4185	/** System descriptor view. */
4186	X86DESC64SYSTEM System;
4187	/** Gate descriptor view. */
4188	X86DESC64GATE Gate;
4189	#endif
4190
4191	/** 8 bit unsigned integer view. */
4192	uint8_t au8[16];
4193	/** 16 bit unsigned integer view. */
4194	uint16_t au16[8];
4195	/** 32 bit unsigned integer view. */
4196	uint32_t au32[4];
4197	/** 64 bit unsigned integer view. */
4198	uint64_t au64[2];
4199	} X86DESC64;
4200	#ifndef VBOX_FOR_DTRACE_LIB
4201	AssertCompileSize(X86DESC64, 16);
4202	#endif
4203	#pragma pack()
4204	/** Pointer to descriptor table entry. */
4205	typedef X86DESC64 *PX86DESC64;
4206	/** Pointer to const descriptor table entry. */
4207	typedef const X86DESC64 *PCX86DESC64;
4208
4209	/** @def X86DESC64_BASE
4210	* Return the base of a 64-bit descriptor.
4211	*/
4212	#define X86DESC64_BASE(a_pDesc) /ASM-NOINC/ \
4213	( ((uint64_t)((a_pDesc)->Gen.u32BaseHigh3) << 32) \
4214	\| ((uint32_t)((a_pDesc)->Gen.u8BaseHigh2) << 24) \
4215	\| ( (a_pDesc)->Gen.u8BaseHigh1 << 16) \
4216	\| ( (a_pDesc)->Gen.u16BaseLow ) )
4217
4218
4219
4220	/** @name Host system descriptor table entry - Use with care!
4221	* @{ */
4222	/** Host system descriptor table entry. */
4223	#if HC_ARCH_BITS == 64
4224	typedef X86DESC64 X86DESCHC;
4225	#else
4226	typedef X86DESC X86DESCHC;
4227	#endif
4228	/** Pointer to a host system descriptor table entry. */
4229	#if HC_ARCH_BITS == 64
4230	typedef PX86DESC64 PX86DESCHC;
4231	#else
4232	typedef PX86DESC PX86DESCHC;
4233	#endif
4234	/** Pointer to a const host system descriptor table entry. */
4235	#if HC_ARCH_BITS == 64
4236	typedef PCX86DESC64 PCX86DESCHC;
4237	#else
4238	typedef PCX86DESC PCX86DESCHC;
4239	#endif
4240	/** @} */
4241
4242
4243	/** @name Selector Descriptor Types.
4244	* @{
4245	*/
4246
4247	/** @name Non-System Selector Types.
4248	* @{ */
4249	/** Code(=set)/Data(=clear) bit. */
4250	#define X86_SEL_TYPE_CODE 8
4251	/** Memory(=set)/System(=clear) bit. */
4252	#define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
4253	/** Accessed bit. */
4254	#define X86_SEL_TYPE_ACCESSED 1
4255	/** Expand down bit (for data selectors only). */
4256	#define X86_SEL_TYPE_DOWN 4
4257	/** Conforming bit (for code selectors only). */
4258	#define X86_SEL_TYPE_CONF 4
4259	/** Write bit (for data selectors only). */
4260	#define X86_SEL_TYPE_WRITE 2
4261	/** Read bit (for code selectors only). */
4262	#define X86_SEL_TYPE_READ 2
4263	/** The bit number of the code segment read bit (relative to u4Type). */
4264	#define X86_SEL_TYPE_READ_BIT 1
4265
4266	/** Read only selector type. */
4267	#define X86_SEL_TYPE_RO 0
4268	/** Accessed read only selector type. */
4269	#define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
4270	/** Read write selector type. */
4271	#define X86_SEL_TYPE_RW 2
4272	/** Accessed read write selector type. */
4273	#define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
4274	/** Expand down read only selector type. */
4275	#define X86_SEL_TYPE_RO_DOWN 4
4276	/** Accessed expand down read only selector type. */
4277	#define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
4278	/** Expand down read write selector type. */
4279	#define X86_SEL_TYPE_RW_DOWN 6
4280	/** Accessed expand down read write selector type. */
4281	#define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
4282	/** Execute only selector type. */
4283	#define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
4284	/** Accessed execute only selector type. */
4285	#define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4286	/** Execute and read selector type. */
4287	#define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
4288	/** Accessed execute and read selector type. */
4289	#define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4290	/** Conforming execute only selector type. */
4291	#define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
4292	/** Accessed Conforming execute only selector type. */
4293	#define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4294	/** Conforming execute and write selector type. */
4295	#define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
4296	/** Accessed Conforming execute and write selector type. */
4297	#define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
4298	/** @} */
4299
4300
4301	/** @name System Selector Types.
4302	* @{ */
4303	/** The TSS busy bit mask. */
4304	#define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
4305
4306	/** Undefined system selector type. */
4307	#define X86_SEL_TYPE_SYS_UNDEFINED 0
4308	/** 286 TSS selector. */
4309	#define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
4310	/** LDT selector. */
4311	#define X86_SEL_TYPE_SYS_LDT 2
4312	/** 286 TSS selector - Busy. */
4313	#define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
4314	/** 286 Callgate selector. */
4315	#define X86_SEL_TYPE_SYS_286_CALL_GATE 4
4316	/** Taskgate selector. */
4317	#define X86_SEL_TYPE_SYS_TASK_GATE 5
4318	/** 286 Interrupt gate selector. */
4319	#define X86_SEL_TYPE_SYS_286_INT_GATE 6
4320	/** 286 Trapgate selector. */
4321	#define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
4322	/** Undefined system selector. */
4323	#define X86_SEL_TYPE_SYS_UNDEFINED2 8
4324	/** 386 TSS selector. */
4325	#define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
4326	/** Undefined system selector. */
4327	#define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
4328	/** 386 TSS selector - Busy. */
4329	#define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
4330	/** 386 Callgate selector. */
4331	#define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
4332	/** Undefined system selector. */
4333	#define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
4334	/** 386 Interruptgate selector. */
4335	#define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
4336	/** 386 Trapgate selector. */
4337	#define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
4338	/** @} */
4339
4340	/** @name AMD64 System Selector Types.
4341	* @{ */
4342	/** LDT selector. */
4343	#define AMD64_SEL_TYPE_SYS_LDT 2
4344	/** TSS selector - Busy. */
4345	#define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
4346	/** TSS selector - Busy. */
4347	#define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
4348	/** Callgate selector. */
4349	#define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
4350	/** Interruptgate selector. */
4351	#define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
4352	/** Trapgate selector. */
4353	#define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
4354	/** @} */
4355
4356	/** @} */
4357
4358
4359	/** @name Descriptor Table Entry Flag Masks.
4360	* These are for the 2nd 32-bit word of a descriptor.
4361	* @{ */
4362	/** Bits 8-11 - TYPE - Descriptor type mask. */
4363	#define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
4364	/** Bit 12 - S - System (=0) or Code/Data (=1). */
4365	#define X86_DESC_S RT_BIT_32(12)
4366	/** Bits 13-14 - DPL - Descriptor Privilege Level. */
4367	#define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
4368	/** Bit 15 - P - Present. */
4369	#define X86_DESC_P RT_BIT_32(15)
4370	/** Bit 20 - AVL - Available for system software. */
4371	#define X86_DESC_AVL RT_BIT_32(20)
4372	/** Bit 22 - DB - Default operation size. 0 = 16 bit, 1 = 32 bit. */
4373	#define X86_DESC_DB RT_BIT_32(22)
4374	/** Bit 23 - G - Granularity of the limit. If set 4KB granularity is
4375	* used, if clear byte. */
4376	#define X86_DESC_G RT_BIT_32(23)
4377	/** @} */
4378
4379	/** @} */
4380
4381
4382	/** @name Task Segments.
4383	* @{
4384	*/
4385
4386	/**
4387	* The minimum TSS descriptor limit for 286 tasks.
4388	*/
4389	#define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
4390
4391	/**
4392	* The minimum TSS descriptor segment limit for 386 tasks.
4393	*/
4394	#define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
4395
4396	/**
4397	* 16-bit Task Segment (TSS).
4398	*/
4399	#pragma pack(1)
4400	typedef struct X86TSS16
4401	{
4402	/** Back link to previous task. (static) */
4403	RTSEL selPrev;
4404	/** Ring-0 stack pointer. (static) */
4405	uint16_t sp0;
4406	/** Ring-0 stack segment. (static) */
4407	RTSEL ss0;
4408	/** Ring-1 stack pointer. (static) */
4409	uint16_t sp1;
4410	/** Ring-1 stack segment. (static) */
4411	RTSEL ss1;
4412	/** Ring-2 stack pointer. (static) */
4413	uint16_t sp2;
4414	/** Ring-2 stack segment. (static) */
4415	RTSEL ss2;
4416	/** IP before task switch. */
4417	uint16_t ip;
4418	/** FLAGS before task switch. */
4419	uint16_t flags;
4420	/** AX before task switch. */
4421	uint16_t ax;
4422	/** CX before task switch. */
4423	uint16_t cx;
4424	/** DX before task switch. */
4425	uint16_t dx;
4426	/** BX before task switch. */
4427	uint16_t bx;
4428	/** SP before task switch. */
4429	uint16_t sp;
4430	/** BP before task switch. */
4431	uint16_t bp;
4432	/** SI before task switch. */
4433	uint16_t si;
4434	/** DI before task switch. */
4435	uint16_t di;
4436	/** ES before task switch. */
4437	RTSEL es;
4438	/** CS before task switch. */
4439	RTSEL cs;
4440	/** SS before task switch. */
4441	RTSEL ss;
4442	/** DS before task switch. */
4443	RTSEL ds;
4444	/** LDTR before task switch. */
4445	RTSEL selLdt;
4446	} X86TSS16;
4447	#ifndef VBOX_FOR_DTRACE_LIB
4448	AssertCompileSize(X86TSS16, X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN + 1);
4449	#endif
4450	#pragma pack()
4451	/** Pointer to a 16-bit task segment. */
4452	typedef X86TSS16 *PX86TSS16;
4453	/** Pointer to a const 16-bit task segment. */
4454	typedef const X86TSS16 *PCX86TSS16;
4455
4456
4457	/**
4458	* 32-bit Task Segment (TSS).
4459	*/
4460	#pragma pack(1)
4461	typedef struct X86TSS32
4462	{
4463	/** Back link to previous task. (static) */
4464	RTSEL selPrev;
4465	uint16_t padding1;
4466	/** Ring-0 stack pointer. (static) */
4467	uint32_t esp0;
4468	/** Ring-0 stack segment. (static) */
4469	RTSEL ss0;
4470	uint16_t padding_ss0;
4471	/** Ring-1 stack pointer. (static) */
4472	uint32_t esp1;
4473	/** Ring-1 stack segment. (static) */
4474	RTSEL ss1;
4475	uint16_t padding_ss1;
4476	/** Ring-2 stack pointer. (static) */
4477	uint32_t esp2;
4478	/** Ring-2 stack segment. (static) */
4479	RTSEL ss2;
4480	uint16_t padding_ss2;
4481	/** Page directory for the task. (static) */
4482	uint32_t cr3;
4483	/** EIP before task switch. */
4484	uint32_t eip;
4485	/** EFLAGS before task switch. */
4486	uint32_t eflags;
4487	/** EAX before task switch. */
4488	uint32_t eax;
4489	/** ECX before task switch. */
4490	uint32_t ecx;
4491	/** EDX before task switch. */
4492	uint32_t edx;
4493	/** EBX before task switch. */
4494	uint32_t ebx;
4495	/** ESP before task switch. */
4496	uint32_t esp;
4497	/** EBP before task switch. */
4498	uint32_t ebp;
4499	/** ESI before task switch. */
4500	uint32_t esi;
4501	/** EDI before task switch. */
4502	uint32_t edi;
4503	/** ES before task switch. */
4504	RTSEL es;
4505	uint16_t padding_es;
4506	/** CS before task switch. */
4507	RTSEL cs;
4508	uint16_t padding_cs;
4509	/** SS before task switch. */
4510	RTSEL ss;
4511	uint16_t padding_ss;
4512	/** DS before task switch. */
4513	RTSEL ds;
4514	uint16_t padding_ds;
4515	/** FS before task switch. */
4516	RTSEL fs;
4517	uint16_t padding_fs;
4518	/** GS before task switch. */
4519	RTSEL gs;
4520	uint16_t padding_gs;
4521	/** LDTR before task switch. */
4522	RTSEL selLdt;
4523	uint16_t padding_ldt;
4524	/** Debug trap flag */
4525	uint16_t fDebugTrap;
4526	/** Offset relative to the TSS of the start of the I/O Bitmap
4527	* and the end of the interrupt redirection bitmap. */
4528	uint16_t offIoBitmap;
4529	} X86TSS32;
4530	#pragma pack()
4531	/** Pointer to task segment. */
4532	typedef X86TSS32 *PX86TSS32;
4533	/** Pointer to const task segment. */
4534	typedef const X86TSS32 *PCX86TSS32;
4535	#ifndef VBOX_FOR_DTRACE_LIB
4536	AssertCompileSize(X86TSS32, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4537	AssertCompileMemberOffset(X86TSS32, cr3, 28);
4538	AssertCompileMemberOffset(X86TSS32, offIoBitmap, 102);
4539	#endif
4540
4541	/**
4542	* 64-bit Task segment.
4543	*/
4544	#pragma pack(1)
4545	typedef struct X86TSS64
4546	{
4547	/** Reserved. */
4548	uint32_t u32Reserved;
4549	/** Ring-0 stack pointer. (static) */
4550	uint64_t rsp0;
4551	/** Ring-1 stack pointer. (static) */
4552	uint64_t rsp1;
4553	/** Ring-2 stack pointer. (static) */
4554	uint64_t rsp2;
4555	/** Reserved. */
4556	uint32_t u32Reserved2[2];
4557	/* IST */
4558	uint64_t ist1;
4559	uint64_t ist2;
4560	uint64_t ist3;
4561	uint64_t ist4;
4562	uint64_t ist5;
4563	uint64_t ist6;
4564	uint64_t ist7;
4565	/* Reserved. */
4566	uint16_t u16Reserved[5];
4567	/** Offset relative to the TSS of the start of the I/O Bitmap
4568	* and the end of the interrupt redirection bitmap. */
4569	uint16_t offIoBitmap;
4570	} X86TSS64;
4571	#pragma pack()
4572	/** Pointer to a 64-bit task segment. */
4573	typedef X86TSS64 *PX86TSS64;
4574	/** Pointer to a const 64-bit task segment. */
4575	typedef const X86TSS64 *PCX86TSS64;
4576	#ifndef VBOX_FOR_DTRACE_LIB
4577	AssertCompileSize(X86TSS64, X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN + 1);
4578	#endif
4579
4580	/** @} */
4581
4582
4583	/** @name Selectors.
4584	* @{
4585	*/
4586
4587	/**
4588	* The shift used to convert a selector from and to index an index (C).
4589	*/
4590	#define X86_SEL_SHIFT 3
4591
4592	/**
4593	* The mask used to mask off the table indicator and RPL of an selector.
4594	*/
4595	#define X86_SEL_MASK 0xfff8U
4596
4597	/**
4598	* The mask used to mask off the RPL of an selector.
4599	* This is suitable for checking for NULL selectors.
4600	*/
4601	#define X86_SEL_MASK_OFF_RPL 0xfffcU
4602
4603	/**
4604	* The bit indicating that a selector is in the LDT and not in the GDT.
4605	*/
4606	#define X86_SEL_LDT 0x0004U
4607
4608	/**
4609	* The bit mask for getting the RPL of a selector.
4610	*/
4611	#define X86_SEL_RPL 0x0003U
4612
4613	/**
4614	* The mask covering both RPL and LDT.
4615	* This is incidentally the same as sizeof(X86DESC) - 1, so good for limit
4616	* checks.
4617	*/
4618	#define X86_SEL_RPL_LDT 0x0007U
4619
4620	/** @} */
4621
4622
4623	/**
4624	* x86 Exceptions/Faults/Traps.
4625	*/
4626	typedef enum X86XCPT
4627	{
4628	/** \#DE - Divide error. */
4629	X86_XCPT_DE = 0x00,
4630	/** \#DB - Debug event (single step, DRx, ..) */
4631	X86_XCPT_DB = 0x01,
4632	/** NMI - Non-Maskable Interrupt */
4633	X86_XCPT_NMI = 0x02,
4634	/** \#BP - Breakpoint (INT3). */
4635	X86_XCPT_BP = 0x03,
4636	/** \#OF - Overflow (INTO). */
4637	X86_XCPT_OF = 0x04,
4638	/** \#BR - Bound range exceeded (BOUND). */
4639	X86_XCPT_BR = 0x05,
4640	/** \#UD - Undefined opcode. */
4641	X86_XCPT_UD = 0x06,
4642	/** \#NM - Device not available (math coprocessor device). */
4643	X86_XCPT_NM = 0x07,
4644	/** \#DF - Double fault. */
4645	X86_XCPT_DF = 0x08,
4646	/** ??? - Coprocessor segment overrun (obsolete). */
4647	X86_XCPT_CO_SEG_OVERRUN = 0x09,
4648	/** \#TS - Taskswitch (TSS). */
4649	X86_XCPT_TS = 0x0a,
4650	/** \#NP - Segment no present. */
4651	X86_XCPT_NP = 0x0b,
4652	/** \#SS - Stack segment fault. */
4653	X86_XCPT_SS = 0x0c,
4654	/** \#GP - General protection fault. */
4655	X86_XCPT_GP = 0x0d,
4656	/** \#PF - Page fault. */
4657	X86_XCPT_PF = 0x0e,
4658	/* 0x0f is reserved (to avoid conflict with spurious interrupts in BIOS setup). */
4659	/** \#MF - Math fault (FPU). */
4660	X86_XCPT_MF = 0x10,
4661	/** \#AC - Alignment check. */
4662	X86_XCPT_AC = 0x11,
4663	/** \#MC - Machine check. */
4664	X86_XCPT_MC = 0x12,
4665	/** \#XF - SIMD Floating-Point Exception. */
4666	X86_XCPT_XF = 0x13,
4667	/** \#VE - Virtualization Exception (Intel only). */
4668	X86_XCPT_VE = 0x14,
4669	/** \#CP - Control Protection Exception (Intel only). */
4670	X86_XCPT_CP = 0x15,
4671	/** \#VC - VMM Communication Exception (AMD only). */
4672	X86_XCPT_VC = 0x1d,
4673	/** \#SX - Security Exception (AMD only). */
4674	X86_XCPT_SX = 0x1e
4675	} X86XCPT;
4676	/** Pointer to a x86 exception code. */
4677	typedef X86XCPT *PX86XCPT;
4678	/** Pointer to a const x86 exception code. */
4679	typedef const X86XCPT *PCX86XCPT;
4680	/** The last valid (currently reserved) exception value. */
4681	#define X86_XCPT_LAST 0x1f
4682
4683
4684	/** @name Trap Error Codes
4685	* @{
4686	*/
4687	/** External indicator. */
4688	#define X86_TRAP_ERR_EXTERNAL 1
4689	/** IDT indicator. */
4690	#define X86_TRAP_ERR_IDT 2
4691	/** Descriptor table indicator - If set LDT, if clear GDT. */
4692	#define X86_TRAP_ERR_TI 4
4693	/** Mask for getting the selector. */
4694	#define X86_TRAP_ERR_SEL_MASK 0xfff8
4695	/** Shift for getting the selector table index (C type index). */
4696	#define X86_TRAP_ERR_SEL_SHIFT 3
4697	/** @} */
4698
4699
4700	/** @name \#PF Trap Error Codes
4701	* @{
4702	*/
4703	/** Bit 0 - P - Not present (clear) or page level protection (set) fault. */
4704	#define X86_TRAP_PF_P RT_BIT_32(0)
4705	/** Bit 1 - R/W - Read (clear) or write (set) access. */
4706	#define X86_TRAP_PF_RW RT_BIT_32(1)
4707	/** Bit 2 - U/S - CPU executing in user mode (set) or supervisor mode (clear). */
4708	#define X86_TRAP_PF_US RT_BIT_32(2)
4709	/** Bit 3 - RSVD- Reserved bit violation (set), i.e. reserved bit was set to 1. */
4710	#define X86_TRAP_PF_RSVD RT_BIT_32(3)
4711	/** Bit 4 - I/D - Instruction fetch (set) / Data access (clear) - PAE + NXE. */
4712	#define X86_TRAP_PF_ID RT_BIT_32(4)
4713	/** Bit 5 - PK - Protection-key violation (AMD64 mode only). */
4714	#define X86_TRAP_PF_PK RT_BIT_32(5)
4715	/** @} */
4716
4717	#pragma pack(1)
4718	/**
4719	* 16-bit IDTR.
4720	*/
4721	typedef struct X86IDTR16
4722	{
4723	/** Offset. */
4724	uint16_t offSel;
4725	/** Selector. */
4726	uint16_t uSel;
4727	} X86IDTR16, *PX86IDTR16;
4728	#pragma pack()
4729
4730	#pragma pack(1)
4731	/**
4732	* 32-bit IDTR/GDTR.
4733	*/
4734	typedef struct X86XDTR32
4735	{
4736	/** Size of the descriptor table. */
4737	uint16_t cb;
4738	/** Address of the descriptor table. */
4739	#ifndef VBOX_FOR_DTRACE_LIB
4740	uint32_t uAddr;
4741	#else
4742	uint16_t au16Addr[2];
4743	#endif
4744	} X86XDTR32, *PX86XDTR32;
4745	#pragma pack()
4746
4747	#pragma pack(1)
4748	/**
4749	* 64-bit IDTR/GDTR.
4750	*/
4751	typedef struct X86XDTR64
4752	{
4753	/** Size of the descriptor table. */
4754	uint16_t cb;
4755	/** Address of the descriptor table. */
4756	#ifndef VBOX_FOR_DTRACE_LIB
4757	uint64_t uAddr;
4758	#else
4759	uint16_t au16Addr[4];
4760	#endif
4761	} X86XDTR64, *PX86XDTR64;
4762	#pragma pack()
4763
4764
4765	/** @name ModR/M
4766	* @{ */
4767	#define X86_MODRM_RM_MASK UINT8_C(0x07)
4768	#define X86_MODRM_REG_MASK UINT8_C(0x38)
4769	#define X86_MODRM_REG_SMASK UINT8_C(0x07)
4770	#define X86_MODRM_REG_SHIFT 3
4771	#define X86_MODRM_MOD_MASK UINT8_C(0xc0)
4772	#define X86_MODRM_MOD_SMASK UINT8_C(0x03)
4773	#define X86_MODRM_MOD_SHIFT 6
4774	#ifndef VBOX_FOR_DTRACE_LIB
4775	AssertCompile((X86_MODRM_RM_MASK \| X86_MODRM_REG_MASK \| X86_MODRM_MOD_MASK) == 0xff);
4776	AssertCompile((X86_MODRM_REG_MASK >> X86_MODRM_REG_SHIFT) == X86_MODRM_REG_SMASK);
4777	AssertCompile((X86_MODRM_MOD_MASK >> X86_MODRM_MOD_SHIFT) == X86_MODRM_MOD_SMASK);
4778	/** @def X86_MODRM_MAKE
4779	* @param a_Mod The mod value (0..3).
4780	* @param a_Reg The register value (0..7).
4781	* @param a_RegMem The register or memory value (0..7). */
4782	# define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
4783	#endif
4784	/** @} */
4785
4786	/** @name SIB
4787	* @{ */
4788	#define X86_SIB_BASE_MASK UINT8_C(0x07)
4789	#define X86_SIB_INDEX_MASK UINT8_C(0x38)
4790	#define X86_SIB_INDEX_SMASK UINT8_C(0x07)
4791	#define X86_SIB_INDEX_SHIFT 3
4792	#define X86_SIB_SCALE_MASK UINT8_C(0xc0)
4793	#define X86_SIB_SCALE_SMASK UINT8_C(0x03)
4794	#define X86_SIB_SCALE_SHIFT 6
4795	#ifndef VBOX_FOR_DTRACE_LIB
4796	AssertCompile((X86_SIB_BASE_MASK \| X86_SIB_INDEX_MASK \| X86_SIB_SCALE_MASK) == 0xff);
4797	AssertCompile((X86_SIB_INDEX_MASK >> X86_SIB_INDEX_SHIFT) == X86_SIB_INDEX_SMASK);
4798	AssertCompile((X86_SIB_SCALE_MASK >> X86_SIB_SCALE_SHIFT) == X86_SIB_SCALE_SMASK);
4799	#endif
4800	/** @} */
4801
4802	/** @name General register indexes.
4803	* @{ */
4804	#define X86_GREG_xAX 0
4805	#define X86_GREG_xCX 1
4806	#define X86_GREG_xDX 2
4807	#define X86_GREG_xBX 3
4808	#define X86_GREG_xSP 4
4809	#define X86_GREG_xBP 5
4810	#define X86_GREG_xSI 6
4811	#define X86_GREG_xDI 7
4812	#define X86_GREG_x8 8
4813	#define X86_GREG_x9 9
4814	#define X86_GREG_x10 10
4815	#define X86_GREG_x11 11
4816	#define X86_GREG_x12 12
4817	#define X86_GREG_x13 13
4818	#define X86_GREG_x14 14
4819	#define X86_GREG_x15 15
4820	/** @} */
4821	/** General register count. */
4822	#define X86_GREG_COUNT 16
4823
4824	/** @name X86_SREG_XXX - Segment register indexes.
4825	* @{ */
4826	#define X86_SREG_ES 0
4827	#define X86_SREG_CS 1
4828	#define X86_SREG_SS 2
4829	#define X86_SREG_DS 3
4830	#define X86_SREG_FS 4
4831	#define X86_SREG_GS 5
4832	/** @} */
4833	/** Segment register count. */
4834	#define X86_SREG_COUNT 6
4835
4836
4837	/** @name X86_OP_XXX - Prefixes
4838	* @{ */
4839	#define X86_OP_PRF_CS UINT8_C(0x2e)
4840	#define X86_OP_PRF_SS UINT8_C(0x36)
4841	#define X86_OP_PRF_DS UINT8_C(0x3e)
4842	#define X86_OP_PRF_ES UINT8_C(0x26)
4843	#define X86_OP_PRF_FS UINT8_C(0x64)
4844	#define X86_OP_PRF_GS UINT8_C(0x65)
4845	#define X86_OP_PRF_SIZE_OP UINT8_C(0x66)
4846	#define X86_OP_PRF_SIZE_ADDR UINT8_C(0x67)
4847	#define X86_OP_PRF_LOCK UINT8_C(0xf0)
4848	#define X86_OP_PRF_REPZ UINT8_C(0xf3)
4849	#define X86_OP_PRF_REPNZ UINT8_C(0xf2)
4850	#define X86_OP_REX_B UINT8_C(0x41)
4851	#define X86_OP_REX_X UINT8_C(0x42)
4852	#define X86_OP_REX_R UINT8_C(0x44)
4853	#define X86_OP_REX_W UINT8_C(0x48)
4854	/** @} */
4855
4856
4857	/** @} */
4858
4859	#endif /* !IPRT_INCLUDED_x86_h */
4860

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source: vbox/trunk/include/iprt/x86.h@ 99026

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