VirtualBox

source: vbox/trunk/include/iprt/x86.mac@ 69202

Last change on this file since 69202 was 69202, checked in by vboxsync, 7 years ago

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1;; @file
2; IPRT - X86 and AMD64 Structures and Definitions.
3;
4; Automatically generated by various.sed. DO NOT EDIT!
5;
6
7;
8; Copyright (C) 2006-2017 Oracle Corporation
9;
10; This file is part of VirtualBox Open Source Edition (OSE), as
11; available from http://www.virtualbox.org. This file is free software;
12; you can redistribute it and/or modify it under the terms of the GNU
13; General Public License (GPL) as published by the Free Software
14; Foundation, in version 2 as it comes in the "COPYING" file of the
15; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17;
18; The contents of this file may alternatively be used under the terms
19; of the Common Development and Distribution License Version 1.0
20; (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21; VirtualBox OSE distribution, in which case the provisions of the
22; CDDL are applicable instead of those of the GPL.
23;
24; You may elect to license modified versions of this file under the
25; terms and conditions of either the GPL or the CDDL or both.
26;
27
28%ifndef ___iprt_x86_h
29%define ___iprt_x86_h
30%ifndef VBOX_FOR_DTRACE_LIB
31%else
32%endif
33%ifdef RT_OS_SOLARIS
34%endif
35%ifndef VBOX_FOR_DTRACE_LIB
36%endif
37%ifndef VBOX_FOR_DTRACE_LIB
38%endif
39%ifndef VBOX_FOR_DTRACE_LIB
40%endif
41%define X86_EFL_CF RT_BIT_32(0)
42%define X86_EFL_CF_BIT 0
43%define X86_EFL_1 RT_BIT_32(1)
44%define X86_EFL_PF RT_BIT_32(2)
45%define X86_EFL_AF RT_BIT_32(4)
46%define X86_EFL_AF_BIT 4
47%define X86_EFL_ZF RT_BIT_32(6)
48%define X86_EFL_ZF_BIT 6
49%define X86_EFL_SF RT_BIT_32(7)
50%define X86_EFL_SF_BIT 7
51%define X86_EFL_TF RT_BIT_32(8)
52%define X86_EFL_IF RT_BIT_32(9)
53%define X86_EFL_DF RT_BIT_32(10)
54%define X86_EFL_OF RT_BIT_32(11)
55%define X86_EFL_OF_BIT 11
56%define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
57%define X86_EFL_NT RT_BIT_32(14)
58%define X86_EFL_RF RT_BIT_32(16)
59%define X86_EFL_VM RT_BIT_32(17)
60%define X86_EFL_AC RT_BIT_32(18)
61%define X86_EFL_VIF RT_BIT_32(19)
62%define X86_EFL_VIP RT_BIT_32(20)
63%define X86_EFL_ID RT_BIT_32(21)
64%define X86_EFL_LIVE_MASK 0x003f7fd5
65%define X86_EFL_RA1_MASK RT_BIT_32(1)
66%define X86_EFL_IOPL_SHIFT 12
67%define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
68%define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
69 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
70%define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
71 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
72%define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
73%ifndef VBOX_FOR_DTRACE_LIB
74%else
75%endif
76%ifndef VBOX_FOR_DTRACE_LIB
77%else
78%endif
79%define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547
80%define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e
81%define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69
82%define X86_CPUID_VENDOR_AMD_EBX 0x68747541
83%define X86_CPUID_VENDOR_AMD_ECX 0x444d4163
84%define X86_CPUID_VENDOR_AMD_EDX 0x69746e65
85%define X86_CPUID_VENDOR_VIA_EBX 0x746e6543
86%define X86_CPUID_VENDOR_VIA_ECX 0x736c7561
87%define X86_CPUID_VENDOR_VIA_EDX 0x48727561
88%define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
89%define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
90%define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
91%define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
92%define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
93%define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
94%define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
95%define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
96%define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
97%define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
98%define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
99%define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
100%define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
101%define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
102%define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
103%define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
104%define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
105%define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
106%define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
107%define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
108%define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
109%define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
110%define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
111%define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
112%define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
113%define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
114%define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
115%define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
116%define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
117%define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
118%define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
119%define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
120%define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
121%define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
122%define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
123%define X86_CPUID_FEATURE_EDX_PSE_BIT 3
124%define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
125%define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
126%define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
127%define X86_CPUID_FEATURE_EDX_PAE_BIT 6
128%define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
129%define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
130%define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
131%define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
132%define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
133%define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
134%define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
135%define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
136%define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
137%define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
138%define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
139%define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
140%define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
141%define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
142%define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
143%define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
144%define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
145%define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
146%define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
147%define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
148%define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
149%define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
150%define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
151%define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
152%define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
153%define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
154%define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
155%define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
156%define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
157%define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
158%define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
159%define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
160%define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
161%define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
162%define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
163%define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
164%define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
165%define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
166%define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
167%define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
168%define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
169%define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
170%define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
171%define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
172%define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
173%define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
174%define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
175%define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
176%define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
177%define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
178%define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
179%define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
180%define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
181%define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
182%define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
183%define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
184%define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
185%define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
186%define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
187%define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
188%define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
189%define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
190%define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
191%define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
192%define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
193%define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
194%define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
195%define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
196%define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
197%define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
198%define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
199%define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
200%define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
201%define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
202%define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
203%define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
204%define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
205%define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
206%define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
207%define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
208%define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
209%define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
210%define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
211%define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
212%define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
213%define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
214%define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
215%define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
216%define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
217%define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
218%define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
219%define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
220%define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
221%define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
222%define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
223%define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
224%define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
225%define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
226%define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
227%define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
228%define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
229%define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
230%define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
231%define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
232%define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
233%define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
234%define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
235%define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
236%define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
237%define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
238%define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
239%define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
240%define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
241%define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
242%define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
243%define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
244%define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
245%define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST RT_BIT(7)
246%define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
247%define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
248%define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
249%define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
250%define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
251%define X86_CR0_PE RT_BIT_32(0)
252%define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
253%define X86_CR0_MP RT_BIT_32(1)
254%define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
255%define X86_CR0_EM RT_BIT_32(2)
256%define X86_CR0_EMULATE_FPU RT_BIT_32(2)
257%define X86_CR0_TS RT_BIT_32(3)
258%define X86_CR0_TASK_SWITCH RT_BIT_32(3)
259%define X86_CR0_ET RT_BIT_32(4)
260%define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
261%define X86_CR0_NE RT_BIT_32(5)
262%define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
263%define X86_CR0_WP RT_BIT_32(16)
264%define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
265%define X86_CR0_AM RT_BIT_32(18)
266%define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
267%define X86_CR0_NW RT_BIT_32(29)
268%define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
269%define X86_CR0_CD RT_BIT_32(30)
270%define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
271%define X86_CR0_PG RT_BIT_32(31)
272%define X86_CR0_PAGING RT_BIT_32(31)
273%define X86_CR3_PWT RT_BIT_32(3)
274%define X86_CR3_PCD RT_BIT_32(4)
275%define X86_CR3_PAGE_MASK (0xfffff000)
276%define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
277%define X86_CR3_AMD64_PAGE_MASK 0x000ffffffffff000
278%define X86_CR4_VME RT_BIT_32(0)
279%define X86_CR4_PVI RT_BIT_32(1)
280%define X86_CR4_TSD RT_BIT_32(2)
281%define X86_CR4_DE RT_BIT_32(3)
282%define X86_CR4_PSE RT_BIT_32(4)
283%define X86_CR4_PAE RT_BIT_32(5)
284%define X86_CR4_MCE RT_BIT_32(6)
285%define X86_CR4_PGE RT_BIT_32(7)
286%define X86_CR4_PCE RT_BIT_32(8)
287%define X86_CR4_OSFXSR RT_BIT_32(9)
288%define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
289%define X86_CR4_VMXE RT_BIT_32(13)
290%define X86_CR4_SMXE RT_BIT_32(14)
291%define X86_CR4_PCIDE RT_BIT_32(17)
292%define X86_CR4_OSXSAVE RT_BIT_32(18)
293%define X86_CR4_SMEP RT_BIT_32(20)
294%define X86_CR4_SMAP RT_BIT_32(21)
295%define X86_CR4_PKE RT_BIT_32(22)
296%define X86_DR6_B0 RT_BIT_32(0)
297%define X86_DR6_B1 RT_BIT_32(1)
298%define X86_DR6_B2 RT_BIT_32(2)
299%define X86_DR6_B3 RT_BIT_32(3)
300%define X86_DR6_B_MASK 0x0000000f
301%define X86_DR6_BD RT_BIT_32(13)
302%define X86_DR6_BS RT_BIT_32(14)
303%define X86_DR6_BT RT_BIT_32(15)
304%define X86_DR6_INIT_VAL 0xFFFF0FF0
305%define X86_DR6_RA1_MASK 0xffff0ff0
306%define X86_DR6_RAZ_MASK RT_BIT_64(12)
307%define X86_DR6_MBZ_MASK 0xffffffff00000000
308%define X86_DR6_B(iBp) RT_BIT_64(iBp)
309%define X86_DR7_L0 RT_BIT_32(0)
310%define X86_DR7_G0 RT_BIT_32(1)
311%define X86_DR7_L1 RT_BIT_32(2)
312%define X86_DR7_G1 RT_BIT_32(3)
313%define X86_DR7_L2 RT_BIT_32(4)
314%define X86_DR7_G2 RT_BIT_32(5)
315%define X86_DR7_L3 RT_BIT_32(6)
316%define X86_DR7_G3 RT_BIT_32(7)
317%define X86_DR7_LE RT_BIT_32(8)
318%define X86_DR7_GE RT_BIT_32(9)
319%define X86_DR7_LE_ALL 0x0000000000000055
320%define X86_DR7_GE_ALL 0x00000000000000aa
321%define X86_DR7_ICE_IR RT_BIT_32(12)
322%define X86_DR7_GD RT_BIT_32(13)
323%define X86_DR7_ICE_TR1 RT_BIT_32(14)
324%define X86_DR7_ICE_TR2 RT_BIT_32(15)
325%define X86_DR7_RW0_MASK (3 << 16)
326%define X86_DR7_LEN0_MASK (3 << 18)
327%define X86_DR7_RW1_MASK (3 << 20)
328%define X86_DR7_LEN1_MASK (3 << 22)
329%define X86_DR7_RW2_MASK (3 << 24)
330%define X86_DR7_LEN2_MASK (3 << 26)
331%define X86_DR7_RW3_MASK (3 << 28)
332%define X86_DR7_LEN3_MASK (3 << 30)
333%define X86_DR7_RA1_MASK RT_BIT_32(10)
334%define X86_DR7_RAZ_MASK 0x0000d800
335%define X86_DR7_MBZ_MASK 0xffffffff00000000
336%define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
337%define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
338%define X86_DR7_L_G(iBp) ( 3 << (iBp * 2) )
339%define X86_DR7_RW_EO 0
340%define X86_DR7_RW_WO 1
341%define X86_DR7_RW_IO 2
342%define X86_DR7_RW_RW 3
343%define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
344%define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & 3 )
345%define X86_DR7_RW_ALL_MASKS 0x33330000
346%ifndef VBOX_FOR_DTRACE_LIB
347 %define X86_DR7_ANY_RW_IO(uDR7) \
348 ( ( 0x22220000 & (uDR7) )
349%endif
350%define X86_DR7_LEN_BYTE 0
351%define X86_DR7_LEN_WORD 1
352%define X86_DR7_LEN_QWORD 2
353%define X86_DR7_LEN_DWORD 3
354%define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
355%define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3 )
356%define X86_DR7_ENABLED_MASK 0x000000ff
357%define X86_DR7_LEN_ALL_MASKS 0xcccc0000
358%define X86_DR7_RW_LEN_ALL_MASKS 0xffff0000
359%define X86_DR7_INIT_VAL 0x400
360%define MSR_P5_MC_ADDR 0x00000000
361%define MSR_P5_MC_TYPE 0x00000001
362%define MSR_IA32_TSC 0x10
363%define MSR_IA32_CESR 0x00000011
364%define MSR_IA32_CTR0 0x00000012
365%define MSR_IA32_CTR1 0x00000013
366%define MSR_IA32_PLATFORM_ID 0x17
367%ifndef MSR_IA32_APICBASE
368 %define MSR_IA32_APICBASE 0x1b
369 %define MSR_IA32_APICBASE_EN RT_BIT_64(11)
370 %define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
371 %define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
372 %define MSR_IA32_APICBASE_BASE_MIN 0x0000000ffffff000
373 %define MSR_IA32_APICBASE_ADDR 0x00000000fee00000
374 %define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
375%endif
376%define MSR_CORE_THREAD_COUNT 0x35
377%define MSR_IA32_FEATURE_CONTROL 0x3A
378%define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_32(0)
379%define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_32(1)
380%define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_32(2)
381%define MSR_IA32_TSC_ADJUST 0x3B
382%define MSR_IA32_BIOS_UPDT_TRIG 0x79
383%define MSR_IA32_BIOS_SIGN_ID 0x8B
384%define MSR_IA32_SMM_MONITOR_CTL 0x9B
385%define MSR_IA32_PMC0 0xC1
386%define MSR_IA32_PMC1 0xC2
387%define MSR_IA32_PMC2 0xC3
388%define MSR_IA32_PMC3 0xC4
389%define MSR_IA32_PLATFORM_INFO 0xCE
390%define MSR_IA32_FSB_CLOCK_STS 0xCD
391%define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
392%define MSR_IA32_MPERF 0xE7
393%define MSR_IA32_APERF 0xE8
394%define MSR_IA32_MTRR_CAP 0xFE
395%define MSR_BBL_CR_CTL3 0x11e
396%ifndef MSR_IA32_SYSENTER_CS
397%define MSR_IA32_SYSENTER_CS 0x174
398%define MSR_IA32_SYSENTER_ESP 0x175
399%define MSR_IA32_SYSENTER_EIP 0x176
400%endif
401%define MSR_IA32_MCG_CAP 0x179
402%define MSR_IA32_MCG_STATUS 0x17A
403%define MSR_IA32_MCG_CTRL 0x17B
404%define MSR_IA32_CR_PAT 0x277
405%define MSR_IA32_PERFEVTSEL0 0x186
406%define MSR_IA32_PERFEVTSEL1 0x187
407%define MSR_FLEX_RATIO 0x194
408%define MSR_IA32_PERF_STATUS 0x198
409%define MSR_IA32_PERF_CTL 0x199
410%define MSR_IA32_THERM_STATUS 0x19c
411%define MSR_IA32_MISC_ENABLE 0x1A0
412%define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
413%define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
414%define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
415%define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
416%define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
417%define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
418%define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
419%define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
420%define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
421%define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
422%define MSR_IA32_DEBUGCTL 0x000001d9
423%define MSR_P4_LASTBRANCH_TOS 0x000001da
424%define MSR_P4_LASTBRANCH_0 0x000001db
425%define MSR_P4_LASTBRANCH_1 0x000001dc
426%define MSR_P4_LASTBRANCH_2 0x000001dd
427%define MSR_P4_LASTBRANCH_3 0x000001de
428%define IA32_MTRR_PHYSBASE0 0x200
429%define IA32_MTRR_PHYSMASK0 0x201
430%define IA32_MTRR_PHYSBASE1 0x202
431%define IA32_MTRR_PHYSMASK1 0x203
432%define IA32_MTRR_PHYSBASE2 0x204
433%define IA32_MTRR_PHYSMASK2 0x205
434%define IA32_MTRR_PHYSBASE3 0x206
435%define IA32_MTRR_PHYSMASK3 0x207
436%define IA32_MTRR_PHYSBASE4 0x208
437%define IA32_MTRR_PHYSMASK4 0x209
438%define IA32_MTRR_PHYSBASE5 0x20a
439%define IA32_MTRR_PHYSMASK5 0x20b
440%define IA32_MTRR_PHYSBASE6 0x20c
441%define IA32_MTRR_PHYSMASK6 0x20d
442%define IA32_MTRR_PHYSBASE7 0x20e
443%define IA32_MTRR_PHYSMASK7 0x20f
444%define IA32_MTRR_PHYSBASE8 0x210
445%define IA32_MTRR_PHYSMASK8 0x211
446%define IA32_MTRR_PHYSBASE9 0x212
447%define IA32_MTRR_PHYSMASK9 0x213
448%define IA32_MTRR_FIX64K_00000 0x250
449%define IA32_MTRR_FIX16K_80000 0x258
450%define IA32_MTRR_FIX16K_A0000 0x259
451%define IA32_MTRR_FIX4K_C0000 0x268
452%define IA32_MTRR_FIX4K_C8000 0x269
453%define IA32_MTRR_FIX4K_D0000 0x26a
454%define IA32_MTRR_FIX4K_D8000 0x26b
455%define IA32_MTRR_FIX4K_E0000 0x26c
456%define IA32_MTRR_FIX4K_E8000 0x26d
457%define IA32_MTRR_FIX4K_F0000 0x26e
458%define IA32_MTRR_FIX4K_F8000 0x26f
459%define MSR_IA32_MTRR_DEF_TYPE 0x2FF
460%define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
461%define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
462%define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
463%define MSR_IA32_PEBS_ENABLE 0x3F1
464%define MSR_IA32_MC0_CTL 0x400
465%define MSR_IA32_MC0_STATUS 0x401
466%define MSR_IA32_VMX_BASIC_INFO 0x480
467%define MSR_IA32_VMX_PINBASED_CTLS 0x481
468%define MSR_IA32_VMX_PROCBASED_CTLS 0x482
469%define MSR_IA32_VMX_EXIT_CTLS 0x483
470%define MSR_IA32_VMX_ENTRY_CTLS 0x484
471%define MSR_IA32_VMX_MISC 0x485
472%define MSR_IA32_VMX_CR0_FIXED0 0x486
473%define MSR_IA32_VMX_CR0_FIXED1 0x487
474%define MSR_IA32_VMX_CR4_FIXED0 0x488
475%define MSR_IA32_VMX_CR4_FIXED1 0x489
476%define MSR_IA32_VMX_VMCS_ENUM 0x48A
477%define MSR_IA32_VMX_VMFUNC 0x491
478%define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
479%define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
480%define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
481%define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
482%define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
483%define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
484%define MSR_IA32_DS_AREA 0x600
485%define MSR_RAPL_POWER_UNIT 0x606
486%define MSR_IA32_X2APIC_START 0x800
487%define MSR_IA32_X2APIC_ID 0x802
488%define MSR_IA32_X2APIC_VERSION 0x803
489%define MSR_IA32_X2APIC_TPR 0x808
490%define MSR_IA32_X2APIC_PPR 0x80A
491%define MSR_IA32_X2APIC_EOI 0x80B
492%define MSR_IA32_X2APIC_LDR 0x80D
493%define MSR_IA32_X2APIC_SVR 0x80F
494%define MSR_IA32_X2APIC_ISR0 0x810
495%define MSR_IA32_X2APIC_ISR1 0x811
496%define MSR_IA32_X2APIC_ISR2 0x812
497%define MSR_IA32_X2APIC_ISR3 0x813
498%define MSR_IA32_X2APIC_ISR4 0x814
499%define MSR_IA32_X2APIC_ISR5 0x815
500%define MSR_IA32_X2APIC_ISR6 0x816
501%define MSR_IA32_X2APIC_ISR7 0x817
502%define MSR_IA32_X2APIC_TMR0 0x818
503%define MSR_IA32_X2APIC_TMR1 0x819
504%define MSR_IA32_X2APIC_TMR2 0x81A
505%define MSR_IA32_X2APIC_TMR3 0x81B
506%define MSR_IA32_X2APIC_TMR4 0x81C
507%define MSR_IA32_X2APIC_TMR5 0x81D
508%define MSR_IA32_X2APIC_TMR6 0x81E
509%define MSR_IA32_X2APIC_TMR7 0x81F
510%define MSR_IA32_X2APIC_IRR0 0x820
511%define MSR_IA32_X2APIC_IRR1 0x821
512%define MSR_IA32_X2APIC_IRR2 0x822
513%define MSR_IA32_X2APIC_IRR3 0x823
514%define MSR_IA32_X2APIC_IRR4 0x824
515%define MSR_IA32_X2APIC_IRR5 0x825
516%define MSR_IA32_X2APIC_IRR6 0x826
517%define MSR_IA32_X2APIC_IRR7 0x827
518%define MSR_IA32_X2APIC_ESR 0x828
519%define MSR_IA32_X2APIC_LVT_CMCI 0x82F
520%define MSR_IA32_X2APIC_ICR 0x830
521%define MSR_IA32_X2APIC_LVT_TIMER 0x832
522%define MSR_IA32_X2APIC_LVT_THERMAL 0x833
523%define MSR_IA32_X2APIC_LVT_PERF 0x834
524%define MSR_IA32_X2APIC_LVT_LINT0 0x835
525%define MSR_IA32_X2APIC_LVT_LINT1 0x836
526%define MSR_IA32_X2APIC_LVT_ERROR 0x837
527%define MSR_IA32_X2APIC_TIMER_ICR 0x838
528%define MSR_IA32_X2APIC_TIMER_CCR 0x839
529%define MSR_IA32_X2APIC_TIMER_DCR 0x83E
530%define MSR_IA32_X2APIC_SELF_IPI 0x83F
531%define MSR_IA32_X2APIC_END 0xBFF
532%define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
533%define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
534%define MSR_K6_EFER 0xc0000080
535%define MSR_K6_EFER_SCE RT_BIT_32(0)
536%define MSR_K6_EFER_LME RT_BIT_32(8)
537%define MSR_K6_EFER_LMA RT_BIT_32(10)
538%define MSR_K6_EFER_NXE RT_BIT_32(11)
539%define MSR_K6_EFER_BIT_NXE 11
540%define MSR_K6_EFER_SVME RT_BIT_32(12)
541%define MSR_K6_EFER_LMSLE RT_BIT_32(13)
542%define MSR_K6_EFER_FFXSR RT_BIT_32(14)
543%define MSR_K6_EFER_TCE RT_BIT_32(15)
544%define MSR_K6_STAR 0xc0000081
545%define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
546%define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
547%define MSR_K6_STAR_SEL_MASK 0xffff
548%define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
549%define MSR_K6_WHCR 0xc0000082
550%define MSR_K6_UWCCR 0xc0000085
551%define MSR_K6_PSOR 0xc0000087
552%define MSR_K6_PFIR 0xc0000088
553%define MSR_K7_EVNTSEL0 0xc0010000
554%define MSR_K7_EVNTSEL1 0xc0010001
555%define MSR_K7_EVNTSEL2 0xc0010002
556%define MSR_K7_EVNTSEL3 0xc0010003
557%define MSR_K7_PERFCTR0 0xc0010004
558%define MSR_K7_PERFCTR1 0xc0010005
559%define MSR_K7_PERFCTR2 0xc0010006
560%define MSR_K7_PERFCTR3 0xc0010007
561%define MSR_K8_LSTAR 0xc0000082
562%define MSR_K8_CSTAR 0xc0000083
563%define MSR_K8_SF_MASK 0xc0000084
564%define MSR_K8_FS_BASE 0xc0000100
565%define MSR_K8_GS_BASE 0xc0000101
566%define MSR_K8_KERNEL_GS_BASE 0xc0000102
567%define MSR_K8_TSC_AUX 0xc0000103
568%define MSR_K8_SYSCFG 0xc0010010
569%define MSR_K8_HWCR 0xc0010015
570%define MSR_K8_IORRBASE0 0xc0010016
571%define MSR_K8_IORRMASK0 0xc0010017
572%define MSR_K8_IORRBASE1 0xc0010018
573%define MSR_K8_IORRMASK1 0xc0010019
574%define MSR_K8_TOP_MEM1 0xc001001a
575%define MSR_K8_TOP_MEM2 0xc001001d
576%define MSR_K8_NB_CFG 0xc001001f
577%define MSR_K8_INT_PENDING 0xc0010055
578%define MSR_K8_VM_CR 0xc0010114
579%define MSR_K8_VM_CR_DPD RT_BIT_32(0)
580%define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
581%define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
582%define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
583%define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
584%define MSR_K8_IGNNE 0xc0010115
585%define MSR_K8_SMM_CTL 0xc0010116
586%define MSR_K8_VM_HSAVE_PA 0xc0010117
587%define X86_PG_ENTRIES 1024
588%define X86_PG_PAE_ENTRIES 512
589%define X86_PG_PAE_PDPE_ENTRIES 4
590%define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
591%define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
592%define X86_PAGE_SIZE X86_PAGE_4K_SIZE
593%define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
594%define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
595%define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
596%define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
597%define X86_PAGE_4K_SIZE _4K
598%define X86_PAGE_4K_SHIFT 12
599%define X86_PAGE_4K_OFFSET_MASK 0xfff
600%define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000
601%define X86_PAGE_4K_BASE_MASK_32 0xfffff000
602%define X86_PAGE_2M_SIZE _2M
603%define X86_PAGE_2M_SHIFT 21
604%define X86_PAGE_2M_OFFSET_MASK 0x001fffff
605%define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000
606%define X86_PAGE_2M_BASE_MASK_32 0xffe00000
607%define X86_PAGE_4M_SIZE _4M
608%define X86_PAGE_4M_SHIFT 22
609%define X86_PAGE_4M_OFFSET_MASK 0x003fffff
610%define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000
611%define X86_PAGE_4M_BASE_MASK_32 0xffc00000
612%define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + 0x800000000000 < UINT64_C(0x1000000000000))
613%define X86_PTE_BIT_P 0
614%define X86_PTE_BIT_RW 1
615%define X86_PTE_BIT_US 2
616%define X86_PTE_BIT_PWT 3
617%define X86_PTE_BIT_PCD 4
618%define X86_PTE_BIT_A 5
619%define X86_PTE_BIT_D 6
620%define X86_PTE_BIT_PAT 7
621%define X86_PTE_BIT_G 8
622%define X86_PTE_PAE_BIT_NX 63
623%define X86_PTE_P RT_BIT_32(0)
624%define X86_PTE_RW RT_BIT_32(1)
625%define X86_PTE_US RT_BIT_32(2)
626%define X86_PTE_PWT RT_BIT_32(3)
627%define X86_PTE_PCD RT_BIT_32(4)
628%define X86_PTE_A RT_BIT_32(5)
629%define X86_PTE_D RT_BIT_32(6)
630%define X86_PTE_PAT RT_BIT_32(7)
631%define X86_PTE_G RT_BIT_32(8)
632%define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
633%define X86_PTE_PG_MASK ( 0xfffff000 )
634%define X86_PTE_PAE_PG_MASK 0x000ffffffffff000
635%define X86_PTE_PAE_NX RT_BIT_64(63)
636%define X86_PTE_PAE_MBZ_MASK_NX 0x7ff0000000000000
637%define X86_PTE_PAE_MBZ_MASK_NO_NX 0xfff0000000000000
638%define X86_PTE_LM_MBZ_MASK_NX 0x0000000000000000
639%define X86_PTE_LM_MBZ_MASK_NO_NX 0x8000000000000000
640%ifndef VBOX_FOR_DTRACE_LIB
641%endif
642%ifndef VBOX_FOR_DTRACE_LIB
643%endif
644%ifndef VBOX_FOR_DTRACE_LIB
645%endif
646%ifndef VBOX_FOR_DTRACE_LIB
647%endif
648%ifndef VBOX_FOR_DTRACE_LIB
649%endif
650%define X86_PT_SHIFT 12
651%define X86_PT_MASK 0x3ff
652%ifndef VBOX_FOR_DTRACE_LIB
653%endif
654%define X86_PT_PAE_SHIFT 12
655%define X86_PT_PAE_MASK 0x1ff
656%define X86_PDE_P RT_BIT_32(0)
657%define X86_PDE_RW RT_BIT_32(1)
658%define X86_PDE_US RT_BIT_32(2)
659%define X86_PDE_PWT RT_BIT_32(3)
660%define X86_PDE_PCD RT_BIT_32(4)
661%define X86_PDE_A RT_BIT_32(5)
662%define X86_PDE_PS RT_BIT_32(7)
663%define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
664%define X86_PDE_PG_MASK ( 0xfffff000 )
665%define X86_PDE_PAE_PG_MASK 0x000ffffffffff000
666%define X86_PDE_PAE_NX RT_BIT_64(63)
667%define X86_PDE_PAE_MBZ_MASK_NX 0x7ff0000000000080
668%define X86_PDE_PAE_MBZ_MASK_NO_NX 0xfff0000000000080
669%define X86_PDE_LM_MBZ_MASK_NX 0x0000000000000080
670%define X86_PDE_LM_MBZ_MASK_NO_NX 0x8000000000000080
671%ifndef VBOX_FOR_DTRACE_LIB
672%endif
673%ifndef VBOX_FOR_DTRACE_LIB
674%endif
675%define X86_PDE4M_P RT_BIT_32(0)
676%define X86_PDE4M_RW RT_BIT_32(1)
677%define X86_PDE4M_US RT_BIT_32(2)
678%define X86_PDE4M_PWT RT_BIT_32(3)
679%define X86_PDE4M_PCD RT_BIT_32(4)
680%define X86_PDE4M_A RT_BIT_32(5)
681%define X86_PDE4M_D RT_BIT_32(6)
682%define X86_PDE4M_PS RT_BIT_32(7)
683%define X86_PDE4M_G RT_BIT_32(8)
684%define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
685%define X86_PDE4M_PAT RT_BIT_32(12)
686%define X86_PDE4M_PAT_SHIFT (12 - 7)
687%define X86_PDE4M_PG_MASK ( 0xffc00000 )
688%define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
689%define X86_PDE4M_PG_HIGH_SHIFT 19
690%define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
691%define X86_PDE2M_PAE_PG_MASK 0x000fffffffe00000
692%define X86_PDE2M_PAE_NX RT_BIT_64(63)
693%define X86_PDE2M_PAE_MBZ_MASK_NX 0x7ff00000001fe000
694%define X86_PDE2M_PAE_MBZ_MASK_NO_NX 0xfff00000001fe000
695%define X86_PDE2M_LM_MBZ_MASK_NX 0x00000000001fe000
696%define X86_PDE2M_LM_MBZ_MASK_NO_NX 0x80000000001fe000
697%ifndef VBOX_FOR_DTRACE_LIB
698%endif
699%ifndef VBOX_FOR_DTRACE_LIB
700%endif
701%ifndef VBOX_FOR_DTRACE_LIB
702%endif
703%ifndef VBOX_FOR_DTRACE_LIB
704%endif
705%ifndef VBOX_FOR_DTRACE_LIB
706%endif
707%define X86_PD_SHIFT 22
708%define X86_PD_MASK 0x3ff
709%ifndef VBOX_FOR_DTRACE_LIB
710%endif
711%define X86_PD_PAE_SHIFT 21
712%define X86_PD_PAE_MASK 0x1ff
713%define X86_PDPE_P RT_BIT_32(0)
714%define X86_PDPE_RW RT_BIT_32(1)
715%define X86_PDPE_US RT_BIT_32(2)
716%define X86_PDPE_PWT RT_BIT_32(3)
717%define X86_PDPE_PCD RT_BIT_32(4)
718%define X86_PDPE_A RT_BIT_32(5)
719%define X86_PDPE_LM_PS RT_BIT_32(7)
720%define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
721%define X86_PDPE_PG_MASK 0x000ffffffffff000
722%define X86_PDPE_PAE_MBZ_MASK 0xfff00000000001e6
723%define X86_PDPE_LM_NX RT_BIT_64(63)
724%define X86_PDPE_LM_MBZ_MASK_NX 0x0000000000000180
725%define X86_PDPE_LM_MBZ_MASK_NO_NX 0x8000000000000180
726%define X86_PDPE1G_LM_MBZ_MASK_NX 0x000000003fffe000
727%define X86_PDPE1G_LM_MBZ_MASK_NO_NX 0x800000003fffe000
728%ifndef VBOX_FOR_DTRACE_LIB
729%endif
730%ifndef VBOX_FOR_DTRACE_LIB
731%endif
732%ifndef VBOX_FOR_DTRACE_LIB
733%endif
734%ifndef VBOX_FOR_DTRACE_LIB
735%endif
736%ifndef VBOX_FOR_DTRACE_LIB
737%endif
738%define X86_PDPT_SHIFT 30
739%define X86_PDPT_MASK_PAE 0x3
740%define X86_PDPT_MASK_AMD64 0x1ff
741%define X86_PML4E_P RT_BIT_32(0)
742%define X86_PML4E_RW RT_BIT_32(1)
743%define X86_PML4E_US RT_BIT_32(2)
744%define X86_PML4E_PWT RT_BIT_32(3)
745%define X86_PML4E_PCD RT_BIT_32(4)
746%define X86_PML4E_A RT_BIT_32(5)
747%define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
748%define X86_PML4E_PG_MASK 0x000ffffffffff000
749%define X86_PML4E_MBZ_MASK_NX 0x0000000000000080
750%define X86_PML4E_MBZ_MASK_NO_NX 0x8000000000000080
751%define X86_PML4E_NX RT_BIT_64(63)
752%ifndef VBOX_FOR_DTRACE_LIB
753%endif
754%ifndef VBOX_FOR_DTRACE_LIB
755%endif
756%ifndef VBOX_FOR_DTRACE_LIB
757%endif
758%define X86_PML4_SHIFT 39
759%define X86_PML4_MASK 0x1ff
760%ifndef VBOX_FOR_DTRACE_LIB
761%endif
762%ifndef VBOX_FOR_DTRACE_LIB
763%endif
764%ifndef VBOX_FOR_DTRACE_LIB
765%endif
766%ifndef VBOX_FOR_DTRACE_LIB
767%endif
768%ifndef VBOX_FOR_DTRACE_LIB
769%endif
770%define X86_OFF_FXSTATE_RSVD 0x1d0
771%define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
772%ifndef VBOX_FOR_DTRACE_LIB
773%endif
774%define X86_FSW_IE RT_BIT_32(0)
775%define X86_FSW_DE RT_BIT_32(1)
776%define X86_FSW_ZE RT_BIT_32(2)
777%define X86_FSW_OE RT_BIT_32(3)
778%define X86_FSW_UE RT_BIT_32(4)
779%define X86_FSW_PE RT_BIT_32(5)
780%define X86_FSW_SF RT_BIT_32(6)
781%define X86_FSW_ES RT_BIT_32(7)
782%define X86_FSW_XCPT_MASK 0x007f
783%define X86_FSW_XCPT_ES_MASK 0x00ff
784%define X86_FSW_C0 RT_BIT_32(8)
785%define X86_FSW_C1 RT_BIT_32(9)
786%define X86_FSW_C2 RT_BIT_32(10)
787%define X86_FSW_TOP_MASK 0x3800
788%define X86_FSW_TOP_SHIFT 11
789%define X86_FSW_TOP_SMASK 0x0007
790%define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
791%define X86_FSW_C3 RT_BIT_32(14)
792%define X86_FSW_C_MASK 0x4700
793%define X86_FSW_B RT_BIT_32(15)
794%define X86_FCW_IM RT_BIT_32(0)
795%define X86_FCW_DM RT_BIT_32(1)
796%define X86_FCW_ZM RT_BIT_32(2)
797%define X86_FCW_OM RT_BIT_32(3)
798%define X86_FCW_UM RT_BIT_32(4)
799%define X86_FCW_PM RT_BIT_32(5)
800%define X86_FCW_MASK_ALL 0x007f
801%define X86_FCW_XCPT_MASK 0x003f
802%define X86_FCW_PC_MASK 0x0300
803%define X86_FCW_PC_24 0x0000
804%define X86_FCW_PC_RSVD 0x0100
805%define X86_FCW_PC_53 0x0200
806%define X86_FCW_PC_64 0x0300
807%define X86_FCW_RC_MASK 0x0c00
808%define X86_FCW_RC_NEAREST 0x0000
809%define X86_FCW_RC_DOWN 0x0400
810%define X86_FCW_RC_UP 0x0800
811%define X86_FCW_RC_ZERO 0x0c00
812%define X86_FCW_ZERO_MASK 0xf080
813%define X86_MXCSR_IE RT_BIT_32(0)
814%define X86_MXCSR_DE RT_BIT_32(1)
815%define X86_MXCSR_ZE RT_BIT_32(2)
816%define X86_MXCSR_OE RT_BIT_32(3)
817%define X86_MXCSR_UE RT_BIT_32(4)
818%define X86_MXCSR_PE RT_BIT_32(5)
819%define X86_MXCSR_DAZ RT_BIT_32(6)
820%define X86_MXCSR_IM RT_BIT_32(7)
821%define X86_MXCSR_DM RT_BIT_32(8)
822%define X86_MXCSR_ZM RT_BIT_32(9)
823%define X86_MXCSR_OM RT_BIT_32(10)
824%define X86_MXCSR_UM RT_BIT_32(11)
825%define X86_MXCSR_PM RT_BIT_32(12)
826%define X86_MXCSR_RC_MASK 0x6000
827%define X86_MXCSR_RC_NEAREST 0x0000
828%define X86_MXCSR_RC_DOWN 0x2000
829%define X86_MXCSR_RC_UP 0x4000
830%define X86_MXCSR_RC_ZERO 0x6000
831%define X86_MXCSR_FZ RT_BIT_32(15)
832%define X86_MXCSR_MM RT_BIT_32(17)
833%ifndef VBOX_FOR_DTRACE_LIB
834%endif
835%ifndef VBOX_FOR_DTRACE_LIB
836%endif
837%ifndef VBOX_FOR_DTRACE_LIB
838%endif
839%ifndef VBOX_FOR_DTRACE_LIB
840%endif
841%ifndef VBOX_FOR_DTRACE_LIB
842%endif
843%ifndef VBOX_FOR_DTRACE_LIB
844%endif
845%ifndef VBOX_FOR_DTRACE_LIB
846%endif
847%ifndef VBOX_FOR_DTRACE_LIB
848%endif
849%ifndef VBOX_FOR_DTRACE_LIB
850%endif
851%define XSAVE_C_X87_BIT 0
852%define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
853%define XSAVE_C_SSE_BIT 1
854%define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
855%define XSAVE_C_YMM_BIT 2
856%define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
857%define XSAVE_C_BNDREGS_BIT 3
858%define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
859%define XSAVE_C_BNDCSR_BIT 4
860%define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
861%define XSAVE_C_OPMASK_BIT 5
862%define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
863%define XSAVE_C_ZMM_HI256_BIT 6
864%define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
865%define XSAVE_C_ZMM_16HI_BIT 7
866%define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
867%define XSAVE_C_PKRU_BIT 9
868%define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
869%define XSAVE_C_LWP_BIT 62
870%define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
871%define XSAVE_C_X_BIT 63
872%define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
873%ifndef VBOX_FOR_DTRACE_LIB
874%endif
875%define X86DESCATTR_TYPE 0x0000000f
876%define X86DESCATTR_DT 0x00000010
877%define X86DESCATTR_DPL 0x00000060
878%define X86DESCATTR_DPL_SHIFT 5
879%define X86DESCATTR_P 0x00000080
880%define X86DESCATTR_LIMIT_HIGH 0x00000f00
881%define X86DESCATTR_AVL 0x00001000
882%define X86DESCATTR_L 0x00002000
883%define X86DESCATTR_D 0x00004000
884%define X86DESCATTR_G 0x00008000
885%define X86DESCATTR_UNUSABLE 0x00010000
886%ifndef VBOX_FOR_DTRACE_LIB
887%endif
888%ifndef VBOX_FOR_DTRACE_LIB
889%define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0)
890%define X86DESCGENERIC_BIT_OFF_BASE_LOW (16)
891%define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32)
892%define X86DESCGENERIC_BIT_OFF_TYPE (40)
893%define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44)
894%define X86DESCGENERIC_BIT_OFF_DPL (45)
895%define X86DESCGENERIC_BIT_OFF_PRESENT (47)
896%define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48)
897%define X86DESCGENERIC_BIT_OFF_AVAILABLE (52)
898%define X86DESCGENERIC_BIT_OFF_LONG (53)
899%define X86DESCGENERIC_BIT_OFF_DEF_BIG (54)
900%define X86DESCGENERIC_BIT_OFF_GRANULARITY (55)
901%define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56)
902%define X86LAR_F_TYPE 0x0f00
903%define X86LAR_F_DT 0x1000
904%define X86LAR_F_DPL 0x6000
905%define X86LAR_F_DPL_SHIFT 13
906%define X86LAR_F_P 0x8000
907%define X86LAR_F_AVL 0x00100000
908%define X86LAR_F_L 0x00200000
909%define X86LAR_F_D 0x00400000
910%define X86LAR_F_G 0x00800000
911%endif
912%ifndef VBOX_FOR_DTRACE_LIB
913%endif
914%ifndef VBOX_FOR_DTRACE_LIB
915%endif
916%ifndef VBOX_FOR_DTRACE_LIB
917%endif
918%ifndef VBOX_FOR_DTRACE_LIB
919%endif
920%ifndef VBOX_FOR_DTRACE_LIB
921%endif
922%if HC_ARCH_BITS == 64
923%else
924%endif
925%if HC_ARCH_BITS == 64
926%else
927%endif
928%if HC_ARCH_BITS == 64
929%else
930%endif
931%define X86_SEL_TYPE_CODE 8
932%define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
933%define X86_SEL_TYPE_ACCESSED 1
934%define X86_SEL_TYPE_DOWN 4
935%define X86_SEL_TYPE_CONF 4
936%define X86_SEL_TYPE_WRITE 2
937%define X86_SEL_TYPE_READ 2
938%define X86_SEL_TYPE_READ_BIT 1
939%define X86_SEL_TYPE_RO 0
940%define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
941%define X86_SEL_TYPE_RW 2
942%define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
943%define X86_SEL_TYPE_RO_DOWN 4
944%define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
945%define X86_SEL_TYPE_RW_DOWN 6
946%define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
947%define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
948%define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
949%define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
950%define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
951%define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
952%define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
953%define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
954%define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
955%define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
956%define X86_SEL_TYPE_SYS_UNDEFINED 0
957%define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
958%define X86_SEL_TYPE_SYS_LDT 2
959%define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
960%define X86_SEL_TYPE_SYS_286_CALL_GATE 4
961%define X86_SEL_TYPE_SYS_TASK_GATE 5
962%define X86_SEL_TYPE_SYS_286_INT_GATE 6
963%define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
964%define X86_SEL_TYPE_SYS_UNDEFINED2 8
965%define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
966%define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
967%define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
968%define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
969%define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
970%define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
971%define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
972%define AMD64_SEL_TYPE_SYS_LDT 2
973%define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
974%define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
975%define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
976%define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
977%define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
978%define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
979%define X86_DESC_S RT_BIT_32(12)
980%define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
981%define X86_DESC_P RT_BIT_32(15)
982%define X86_DESC_AVL RT_BIT_32(20)
983%define X86_DESC_DB RT_BIT_32(22)
984%define X86_DESC_G RT_BIT_32(23)
985%define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
986%define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
987%ifndef VBOX_FOR_DTRACE_LIB
988%endif
989%ifndef VBOX_FOR_DTRACE_LIB
990%endif
991%ifndef VBOX_FOR_DTRACE_LIB
992%endif
993%define X86_SEL_SHIFT 3
994%define X86_SEL_MASK 0xfff8
995%define X86_SEL_MASK_OFF_RPL 0xfffc
996%define X86_SEL_LDT 0x0004
997%define X86_SEL_RPL 0x0003
998%define X86_SEL_RPL_LDT 0x0007
999%define X86_XCPT_LAST 0x1f
1000%define X86_TRAP_ERR_EXTERNAL 1
1001%define X86_TRAP_ERR_IDT 2
1002%define X86_TRAP_ERR_TI 4
1003%define X86_TRAP_ERR_SEL_MASK 0xfff8
1004%define X86_TRAP_ERR_SEL_SHIFT 3
1005%define X86_TRAP_PF_P RT_BIT_32(0)
1006%define X86_TRAP_PF_RW RT_BIT_32(1)
1007%define X86_TRAP_PF_US RT_BIT_32(2)
1008%define X86_TRAP_PF_RSVD RT_BIT_32(3)
1009%define X86_TRAP_PF_ID RT_BIT_32(4)
1010%define X86_TRAP_PF_PK RT_BIT_32(5)
1011%ifndef VBOX_FOR_DTRACE_LIB
1012%else
1013%endif
1014%ifndef VBOX_FOR_DTRACE_LIB
1015%else
1016%endif
1017%define X86_MODRM_RM_MASK 0x07
1018%define X86_MODRM_REG_MASK 0x38
1019%define X86_MODRM_REG_SMASK 0x07
1020%define X86_MODRM_REG_SHIFT 3
1021%define X86_MODRM_MOD_MASK 0xc0
1022%define X86_MODRM_MOD_SMASK 0x03
1023%define X86_MODRM_MOD_SHIFT 6
1024%ifndef VBOX_FOR_DTRACE_LIB
1025 %define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
1026%endif
1027%define X86_SIB_BASE_MASK 0x07
1028%define X86_SIB_INDEX_MASK 0x38
1029%define X86_SIB_INDEX_SMASK 0x07
1030%define X86_SIB_INDEX_SHIFT 3
1031%define X86_SIB_SCALE_MASK 0xc0
1032%define X86_SIB_SCALE_SMASK 0x03
1033%define X86_SIB_SCALE_SHIFT 6
1034%ifndef VBOX_FOR_DTRACE_LIB
1035%endif
1036%define X86_GREG_xAX 0
1037%define X86_GREG_xCX 1
1038%define X86_GREG_xDX 2
1039%define X86_GREG_xBX 3
1040%define X86_GREG_xSP 4
1041%define X86_GREG_xBP 5
1042%define X86_GREG_xSI 6
1043%define X86_GREG_xDI 7
1044%define X86_GREG_x8 8
1045%define X86_GREG_x9 9
1046%define X86_GREG_x10 10
1047%define X86_GREG_x11 11
1048%define X86_GREG_x12 12
1049%define X86_GREG_x13 13
1050%define X86_GREG_x14 14
1051%define X86_GREG_x15 15
1052%define X86_SREG_ES 0
1053%define X86_SREG_CS 1
1054%define X86_SREG_SS 2
1055%define X86_SREG_DS 3
1056%define X86_SREG_FS 4
1057%define X86_SREG_GS 5
1058%define X86_SREG_COUNT 6
1059%define X86_OP_PRF_CS 0x2e
1060%define X86_OP_PRF_SS 0x36
1061%define X86_OP_PRF_DS 0x3e
1062%define X86_OP_PRF_ES 0x26
1063%define X86_OP_PRF_FS 0x64
1064%define X86_OP_PRF_GS 0x65
1065%define X86_OP_PRF_SIZE_OP 0x66
1066%define X86_OP_PRF_SIZE_ADDR 0x67
1067%define X86_OP_PRF_LOCK 0xf0
1068%define X86_OP_PRF_REPZ 0xf3
1069%define X86_OP_PRF_REPNZ 0xf2
1070%define X86_OP_REX_B 0x41
1071%define X86_OP_REX_X 0x42
1072%define X86_OP_REX_R 0x44
1073%define X86_OP_REX_W 0x48
1074%endif
1075%include "iprt/x86extra.mac"
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