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source: vbox/trunk/include/iprt/x86.mac@ 38761

Last change on this file since 38761 was 37968, checked in by vboxsync, 13 years ago

include/*/*.mac: regenerated assmebly headers.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 29.3 KB
Line 
1%ifndef ___iprt_x86_h
2%define ___iprt_x86_h
3%ifdef RT_OS_SOLARIS
4%endif
5%define X86_EFL_CF RT_BIT(0)
6%define X86_EFL_1 RT_BIT(1)
7%define X86_EFL_PF RT_BIT(2)
8%define X86_EFL_AF RT_BIT(4)
9%define X86_EFL_ZF RT_BIT(6)
10%define X86_EFL_SF RT_BIT(7)
11%define X86_EFL_TF RT_BIT(8)
12%define X86_EFL_IF RT_BIT(9)
13%define X86_EFL_DF RT_BIT(10)
14%define X86_EFL_OF RT_BIT(11)
15%define X86_EFL_IOPL (RT_BIT(12) | RT_BIT(13))
16%define X86_EFL_NT RT_BIT(14)
17%define X86_EFL_RF RT_BIT(16)
18%define X86_EFL_VM RT_BIT(17)
19%define X86_EFL_AC RT_BIT(18)
20%define X86_EFL_VIF RT_BIT(19)
21%define X86_EFL_VIP RT_BIT(20)
22%define X86_EFL_ID RT_BIT(21)
23%define X86_EFL_IOPL_SHIFT 12
24%define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
25%define X86_EFL_POPF_BITS (X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID)
26%define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547
27%define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e
28%define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69
29%define X86_CPUID_VENDOR_AMD_EBX 0x68747541
30%define X86_CPUID_VENDOR_AMD_ECX 0x444d4163
31%define X86_CPUID_VENDOR_AMD_EDX 0x69746e65
32%define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
33%define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
34%define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
35%define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
36%define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
37%define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
38%define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
39%define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
40%define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
41%define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
42%define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
43%define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
44%define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
45%define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
46%define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
47%define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
48%define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
49%define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
50%define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
51%define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
52%define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
53%define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
54%define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
55%define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
56%define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
57%define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
58%define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
59%define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
60%define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
61%define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
62%define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
63%define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
64%define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
65%define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
66%define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
67%define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
68%define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
69%define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
70%define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
71%define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
72%define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
73%define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
74%define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
75%define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
76%define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
77%define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
78%define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
79%define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
80%define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
81%define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
82%define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
83%define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
84%define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
85%define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
86%define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
87%define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
88%define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
89%define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
90%define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
91%define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
92%define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
93%define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
94%define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
95%define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
96%define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
97%define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
98%define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
99%define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
100%define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
101%define X86_CPUID_AMD_FEATURE_EDX_SEP RT_BIT(11)
102%define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
103%define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
104%define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
105%define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
106%define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
107%define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
108%define X86_CPUID_AMD_FEATURE_EDX_NX RT_BIT(20)
109%define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
110%define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
111%define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
112%define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
113%define X86_CPUID_AMD_FEATURE_EDX_PAGE1GB RT_BIT(26)
114%define X86_CPUID_AMD_FEATURE_EDX_RDTSCP RT_BIT(27)
115%define X86_CPUID_AMD_FEATURE_EDX_LONG_MODE RT_BIT(29)
116%define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
117%define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
118%define X86_CPUID_AMD_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
119%define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
120%define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
121%define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
122%define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
123%define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
124%define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
125%define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
126%define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
127%define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
128%define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
129%define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
130%define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
131%define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
132%define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
133%define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
134%define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
135%define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
136%define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
137%define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
138%define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
139%define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
140%define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
141%define X86_CR0_PE RT_BIT(0)
142%define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
143%define X86_CR0_MP RT_BIT(1)
144%define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
145%define X86_CR0_EM RT_BIT(2)
146%define X86_CR0_EMULATE_FPU RT_BIT(2)
147%define X86_CR0_TS RT_BIT(3)
148%define X86_CR0_TASK_SWITCH RT_BIT(3)
149%define X86_CR0_ET RT_BIT(4)
150%define X86_CR0_EXTENSION_TYPE RT_BIT(4)
151%define X86_CR0_NE RT_BIT(5)
152%define X86_CR0_NUMERIC_ERROR RT_BIT(5)
153%define X86_CR0_WP RT_BIT(16)
154%define X86_CR0_WRITE_PROTECT RT_BIT(16)
155%define X86_CR0_AM RT_BIT(18)
156%define X86_CR0_ALIGMENT_MASK RT_BIT(18)
157%define X86_CR0_NW RT_BIT(29)
158%define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
159%define X86_CR0_CD RT_BIT(30)
160%define X86_CR0_CACHE_DISABLE RT_BIT(30)
161%define X86_CR0_PG RT_BIT(31)
162%define X86_CR0_PAGING RT_BIT(31)
163%define X86_CR3_PWT RT_BIT(3)
164%define X86_CR3_PCD RT_BIT(4)
165%define X86_CR3_PAGE_MASK (0xfffff000)
166%define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
167%define X86_CR3_AMD64_PAGE_MASK 0x000ffffffffff000
168%define X86_CR4_VME RT_BIT(0)
169%define X86_CR4_PVI RT_BIT(1)
170%define X86_CR4_TSD RT_BIT(2)
171%define X86_CR4_DE RT_BIT(3)
172%define X86_CR4_PSE RT_BIT(4)
173%define X86_CR4_PAE RT_BIT(5)
174%define X86_CR4_MCE RT_BIT(6)
175%define X86_CR4_PGE RT_BIT(7)
176%define X86_CR4_PCE RT_BIT(8)
177%define X86_CR4_OSFSXR RT_BIT(9)
178%define X86_CR4_OSXMMEEXCPT RT_BIT(10)
179%define X86_CR4_VMXE RT_BIT(13)
180%define X86_CR4_SMXE RT_BIT(14)
181%define X86_CR4_PCIDE RT_BIT(17)
182%define X86_CR4_OSXSAVE RT_BIT(18)
183%define X86_CR4_SMEP RT_BIT(20)
184%define X86_DR6_B0 RT_BIT(0)
185%define X86_DR6_B1 RT_BIT(1)
186%define X86_DR6_B2 RT_BIT(2)
187%define X86_DR6_B3 RT_BIT(3)
188%define X86_DR6_BD RT_BIT(13)
189%define X86_DR6_BS RT_BIT(14)
190%define X86_DR6_BT RT_BIT(15)
191%define X86_DR6_INIT_VAL 0xFFFF0FF0
192%define X86_DR7_L0 RT_BIT(0)
193%define X86_DR7_G0 RT_BIT(1)
194%define X86_DR7_L1 RT_BIT(2)
195%define X86_DR7_G1 RT_BIT(3)
196%define X86_DR7_L2 RT_BIT(4)
197%define X86_DR7_G2 RT_BIT(5)
198%define X86_DR7_L3 RT_BIT(6)
199%define X86_DR7_G3 RT_BIT(7)
200%define X86_DR7_LE RT_BIT(8)
201%define X86_DR7_GE RT_BIT(9)
202%define X86_DR7_GD RT_BIT(13)
203%define X86_DR7_RW0_MASK (3 << 16)
204%define X86_DR7_LEN0_MASK (3 << 18)
205%define X86_DR7_RW1_MASK (3 << 20)
206%define X86_DR7_LEN1_MASK (3 << 22)
207%define X86_DR7_RW2_MASK (3 << 24)
208%define X86_DR7_LEN2_MASK (3 << 26)
209%define X86_DR7_RW3_MASK (3 << 28)
210%define X86_DR7_LEN3_MASK (3 << 30)
211%define X86_DR7_MB1_MASK (RT_BIT(10))
212%define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
213%define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
214%define X86_DR7_RW_EO 0
215%define X86_DR7_RW_WO 1
216%define X86_DR7_RW_IO 2
217%define X86_DR7_RW_RW 3
218%define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
219%define X86_DR7_LEN_BYTE 0
220%define X86_DR7_LEN_WORD 1
221%define X86_DR7_LEN_QWORD 2
222%define X86_DR7_LEN_DWORD 3
223%define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
224%define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3)
225%define X86_DR7_ENABLED_MASK (RT_BIT(0) | RT_BIT(1) | RT_BIT(2) | RT_BIT(3) | RT_BIT(4) | RT_BIT(5) | RT_BIT(6) | RT_BIT(7))
226%define X86_DR7_IO_ENABLED_MASK (X86_DR7_RW(0, X86_DR7_RW_IO) | X86_DR7_RW(1, X86_DR7_RW_IO) | X86_DR7_RW(2, X86_DR7_RW_IO) | X86_DR7_RW(3, X86_DR7_RW_IO))
227%define X86_DR7_INIT_VAL 0x400
228%define MSR_IA32_TSC 0x10
229%define MSR_IA32_PLATFORM_ID 0x17
230%ifndef MSR_IA32_APICBASE
231%define MSR_IA32_APICBASE 0x1b
232%endif
233%define MSR_IA32_FEATURE_CONTROL 0x3A
234%define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
235%define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
236%define MSR_IA32_BIOS_UPDT_TRIG 0x79
237%define MSR_IA32_BIOS_SIGN_ID 0x8B
238%define MSR_IA32_PMC0 0xC1
239%define MSR_IA32_PMC1 0xC2
240%define MSR_IA32_PMC2 0xC3
241%define MSR_IA32_PMC3 0xC4
242%define MSR_IA32_PLATFORM_INFO 0xCE
243%define MSR_IA32_FSB_CLOCK_STS 0xCD
244%define MSR_IA32_MTRR_CAP 0xFE
245%ifndef MSR_IA32_SYSENTER_CS
246%define MSR_IA32_SYSENTER_CS 0x174
247%define MSR_IA32_SYSENTER_ESP 0x175
248%define MSR_IA32_SYSENTER_EIP 0x176
249%endif
250%define MSR_IA32_MCP_CAP 0x179
251%define MSR_IA32_MCP_STATUS 0x17A
252%define MSR_IA32_MCP_CTRL 0x17B
253%define MSR_IA32_DEBUGCTL 0x1D9
254%define MSR_IA32_CR_PAT 0x277
255%define MSR_IA32_PERFEVTSEL0 0x186
256%define MSR_IA32_PERFEVTSEL1 0x187
257%define MSR_IA32_FLEX_RATIO 0x194
258%define MSR_IA32_PERF_STATUS 0x198
259%define MSR_IA32_PERF_CTL 0x199
260%define MSR_IA32_THERM_STATUS 0x19c
261%define MSR_IA32_MISC_ENABLE 0x1A0
262%define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT(0)
263%define MSR_IA32_MISC_ENABLE_TCC RT_BIT(3)
264%define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT(7)
265%define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT(11)
266%define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT(12)
267%define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT(16)
268%define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT(18)
269%define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT(22)
270%define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT(23)
271%define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT(34)
272%define MSR_IA32_MTRR_DEF_TYPE 0x2FF
273%define MSR_IA32_MC0_CTL 0x400
274%define MSR_IA32_MC0_STATUS 0x401
275%define MSR_IA32_VMX_BASIC_INFO 0x480
276%define MSR_IA32_VMX_PINBASED_CTLS 0x481
277%define MSR_IA32_VMX_PROCBASED_CTLS 0x482
278%define MSR_IA32_VMX_EXIT_CTLS 0x483
279%define MSR_IA32_VMX_ENTRY_CTLS 0x484
280%define MSR_IA32_VMX_MISC 0x485
281%define MSR_IA32_VMX_CR0_FIXED0 0x486
282%define MSR_IA32_VMX_CR0_FIXED1 0x487
283%define MSR_IA32_VMX_CR4_FIXED0 0x488
284%define MSR_IA32_VMX_CR4_FIXED1 0x489
285%define MSR_IA32_VMX_VMCS_ENUM 0x48A
286%define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
287%define MSR_IA32_VMX_EPT_CAPS 0x48C
288%define MSR_IA32_DS_AREA 0x600
289%define MSR_IA32_APIC_START 0x800
290%define MSR_IA32_APIC_END 0x900
291%define MSR_K6_EFER 0xc0000080
292%define MSR_K6_EFER_SCE RT_BIT(0)
293%define MSR_K6_EFER_LME RT_BIT(8)
294%define MSR_K6_EFER_LMA RT_BIT(10)
295%define MSR_K6_EFER_NXE RT_BIT(11)
296%define MSR_K6_EFER_SVME RT_BIT(12)
297%define MSR_K6_EFER_LMSLE RT_BIT(13)
298%define MSR_K6_EFER_FFXSR RT_BIT(14)
299%define MSR_K6_STAR 0xc0000081
300%define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
301%define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
302%define MSR_K6_STAR_SEL_MASK 0xffff
303%define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
304%define MSR_K6_WHCR 0xc0000082
305%define MSR_K6_UWCCR 0xc0000085
306%define MSR_K6_PSOR 0xc0000087
307%define MSR_K6_PFIR 0xc0000088
308%define MSR_K7_EVNTSEL0 0xc0010000
309%define MSR_K7_EVNTSEL1 0xc0010001
310%define MSR_K7_EVNTSEL2 0xc0010002
311%define MSR_K7_EVNTSEL3 0xc0010003
312%define MSR_K7_PERFCTR0 0xc0010004
313%define MSR_K7_PERFCTR1 0xc0010005
314%define MSR_K7_PERFCTR2 0xc0010006
315%define MSR_K7_PERFCTR3 0xc0010007
316%define MSR_K8_HWCR 0xc0010015
317%define MSR_K8_LSTAR 0xc0000082
318%define MSR_K8_CSTAR 0xc0000083
319%define MSR_K8_SF_MASK 0xc0000084
320%define MSR_K8_FS_BASE 0xc0000100
321%define MSR_K8_GS_BASE 0xc0000101
322%define MSR_K8_KERNEL_GS_BASE 0xc0000102
323%define MSR_K8_TSC_AUX 0xc0000103
324%define MSR_K8_SYSCFG 0xc0010010
325%define MSR_K8_HWCR 0xc0010015
326%define MSR_K8_IORRBASE0 0xc0010016
327%define MSR_K8_IORRMASK0 0xc0010017
328%define MSR_K8_IORRBASE1 0xc0010018
329%define MSR_K8_IORRMASK1 0xc0010019
330%define MSR_K8_TOP_MEM1 0xc001001a
331%define MSR_K8_TOP_MEM2 0xc001001d
332%define MSR_K8_VM_CR 0xc0010114
333%define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
334%define MSR_K8_IGNNE 0xc0010115
335%define MSR_K8_SMM_CTL 0xc0010116
336%define MSR_K8_VM_HSAVE_PA 0xc0010117
337%define X86_PG_ENTRIES 1024
338%define X86_PG_PAE_ENTRIES 512
339%define X86_PG_PAE_PDPE_ENTRIES 4
340%define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
341%define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
342%define X86_PAGE_4K_SIZE _4K
343%define X86_PAGE_4K_SHIFT 12
344%define X86_PAGE_4K_OFFSET_MASK 0xfff
345%define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000
346%define X86_PAGE_4K_BASE_MASK_32 0xfffff000
347%define X86_PAGE_2M_SIZE _2M
348%define X86_PAGE_2M_SHIFT 21
349%define X86_PAGE_2M_OFFSET_MASK 0x001fffff
350%define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000
351%define X86_PAGE_2M_BASE_MASK_32 0xffe00000
352%define X86_PAGE_4M_SIZE _4M
353%define X86_PAGE_4M_SHIFT 22
354%define X86_PAGE_4M_OFFSET_MASK 0x003fffff
355%define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000
356%define X86_PAGE_4M_BASE_MASK_32 0xffc00000
357%define X86_PTE_BIT_P 0
358%define X86_PTE_BIT_RW 1
359%define X86_PTE_BIT_US 2
360%define X86_PTE_BIT_PWT 3
361%define X86_PTE_BIT_PCD 4
362%define X86_PTE_BIT_A 5
363%define X86_PTE_BIT_D 6
364%define X86_PTE_BIT_PAT 7
365%define X86_PTE_BIT_G 8
366%define X86_PTE_P RT_BIT(0)
367%define X86_PTE_RW RT_BIT(1)
368%define X86_PTE_US RT_BIT(2)
369%define X86_PTE_PWT RT_BIT(3)
370%define X86_PTE_PCD RT_BIT(4)
371%define X86_PTE_A RT_BIT(5)
372%define X86_PTE_D RT_BIT(6)
373%define X86_PTE_PAT RT_BIT(7)
374%define X86_PTE_G RT_BIT(8)
375%define X86_PTE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
376%define X86_PTE_PG_MASK ( 0xfffff000 )
377%define X86_PTE_PAE_PG_MASK 0x000ffffffffff000
378%define X86_PTE_PAE_NX RT_BIT_64(63)
379%define X86_PTE_PAE_MBZ_MASK_NX 0x7ff0000000000000
380%define X86_PTE_PAE_MBZ_MASK_NO_NX 0xfff0000000000000
381%define X86_PTE_LM_MBZ_MASK_NX 0x0000000000000000
382%define X86_PTE_LM_MBZ_MASK_NO_NX 0x8000000000000000
383%define X86_PT_SHIFT 12
384%define X86_PT_MASK 0x3ff
385%define X86_PT_PAE_SHIFT 12
386%define X86_PT_PAE_MASK 0x1ff
387%define X86_PDE_P RT_BIT(0)
388%define X86_PDE_RW RT_BIT(1)
389%define X86_PDE_US RT_BIT(2)
390%define X86_PDE_PWT RT_BIT(3)
391%define X86_PDE_PCD RT_BIT(4)
392%define X86_PDE_A RT_BIT(5)
393%define X86_PDE_PS RT_BIT(7)
394%define X86_PDE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
395%define X86_PDE_PG_MASK ( 0xfffff000 )
396%define X86_PDE_PAE_PG_MASK 0x000ffffffffff000
397%define X86_PDE_PAE_NX RT_BIT_64(63)
398%define X86_PDE_PAE_MBZ_MASK_NX 0x7ff0000000000080
399%define X86_PDE_PAE_MBZ_MASK_NO_NX 0xfff0000000000080
400%define X86_PDE_LM_MBZ_MASK_NX 0x0000000000000080
401%define X86_PDE_LM_MBZ_MASK_NO_NX 0x8000000000000080
402%define X86_PDE4M_P RT_BIT(0)
403%define X86_PDE4M_RW RT_BIT(1)
404%define X86_PDE4M_US RT_BIT(2)
405%define X86_PDE4M_PWT RT_BIT(3)
406%define X86_PDE4M_PCD RT_BIT(4)
407%define X86_PDE4M_A RT_BIT(5)
408%define X86_PDE4M_D RT_BIT(6)
409%define X86_PDE4M_PS RT_BIT(7)
410%define X86_PDE4M_G RT_BIT(8)
411%define X86_PDE4M_AVL (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
412%define X86_PDE4M_PAT RT_BIT(12)
413%define X86_PDE4M_PAT_SHIFT (12 - 7)
414%define X86_PDE4M_PG_MASK ( 0xffc00000 )
415%define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
416%define X86_PDE4M_PG_HIGH_SHIFT 19
417%define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
418%define X86_PDE2M_PAE_PG_MASK 0x000fffffffe00000
419%define X86_PDE2M_PAE_NX RT_BIT_64(63)
420%define X86_PDE2M_PAE_MBZ_MASK_NX 0x7ff00000001fe000
421%define X86_PDE2M_PAE_MBZ_MASK_NO_NX 0xfff00000001fe000
422%define X86_PDE2M_LM_MBZ_MASK_NX 0x00000000001fe000
423%define X86_PDE2M_LM_MBZ_MASK_NO_NX 0x80000000001fe000
424%define X86_PD_SHIFT 22
425%define X86_PD_MASK 0x3ff
426%define X86_PD_PAE_SHIFT 21
427%define X86_PD_PAE_MASK 0x1ff
428%define X86_PDPE_P RT_BIT(0)
429%define X86_PDPE_RW RT_BIT(1)
430%define X86_PDPE_US RT_BIT(2)
431%define X86_PDPE_PWT RT_BIT(3)
432%define X86_PDPE_PCD RT_BIT(4)
433%define X86_PDPE_A RT_BIT(5)
434%define X86_PDPE_LM_PS RT_BIT(7)
435%define X86_PDPE_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
436%define X86_PDPE_PG_MASK 0x000ffffffffff000
437%define X86_PDPE_PAE_MBZ_MASK 0xfff00000000001e6
438%define X86_PDPE_LM_NX RT_BIT_64(63)
439%define X86_PDPE_LM_MBZ_MASK_NX 0x0000000000000180
440%define X86_PDPE_LM_MBZ_MASK_NO_NX 0x8000000000000180
441%define X86_PDPE1G_LM_MBZ_MASK_NX 0x000000003fffe000
442%define X86_PDPE1G_LM_MBZ_MASK_NO_NX 0x800000003fffe000
443%define X86_PDPT_SHIFT 30
444%define X86_PDPT_MASK_PAE 0x3
445%define X86_PDPT_MASK_AMD64 0x1ff
446%define X86_PML4E_P RT_BIT(0)
447%define X86_PML4E_RW RT_BIT(1)
448%define X86_PML4E_US RT_BIT(2)
449%define X86_PML4E_PWT RT_BIT(3)
450%define X86_PML4E_PCD RT_BIT(4)
451%define X86_PML4E_A RT_BIT(5)
452%define X86_PML4E_AVL_MASK (RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
453%define X86_PML4E_PG_MASK 0x000ffffffffff000
454%define X86_PML4E_MBZ_MASK_NX 0x0000000000000080
455%define X86_PML4E_MBZ_MASK_NO_NX 0x8000000000000080
456%define X86_PML4E_NX RT_BIT_64(63)
457%define X86_PML4_SHIFT 39
458%define X86_PML4_MASK 0x1ff
459%define X86_FSW_IE RT_BIT(0)
460%define X86_FSW_DE RT_BIT(1)
461%define X86_FSW_ZE RT_BIT(2)
462%define X86_FSW_OE RT_BIT(3)
463%define X86_FSW_UE RT_BIT(4)
464%define X86_FSW_PE RT_BIT(5)
465%define X86_FSW_SF RT_BIT(6)
466%define X86_FSW_ES RT_BIT(7)
467%define X86_FSW_C0 RT_BIT(8)
468%define X86_FSW_C1 RT_BIT(9)
469%define X86_FSW_C2 RT_BIT(10)
470%define X86_FSW_TOP_MASK 0x3800
471%define X86_FSW_TOP_SHIFT 11
472%define X86_FSW_TOP_SMASK 0x0007
473%define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
474%define X86_FSW_C3 RT_BIT(14)
475%define X86_FSW_B RT_BIT(15)
476%if HC_ARCH_BITS == 64
477%else
478%endif
479%if HC_ARCH_BITS == 64
480%else
481%endif
482%if HC_ARCH_BITS == 64
483%else
484%endif
485%define X86_SEL_TYPE_CODE 8
486%define X86_SEL_TYPE_MEMORY RT_BIT(4)
487%define X86_SEL_TYPE_ACCESSED 1
488%define X86_SEL_TYPE_DOWN 4
489%define X86_SEL_TYPE_CONF 4
490%define X86_SEL_TYPE_WRITE 2
491%define X86_SEL_TYPE_READ 2
492%define X86_SEL_TYPE_RO 0
493%define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
494%define X86_SEL_TYPE_RW 2
495%define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
496%define X86_SEL_TYPE_RO_DOWN 4
497%define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
498%define X86_SEL_TYPE_RW_DOWN 6
499%define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
500%define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
501%define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
502%define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
503%define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
504%define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
505%define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
506%define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
507%define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
508%define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
509%define X86_SEL_TYPE_SYS_UNDEFINED 0
510%define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
511%define X86_SEL_TYPE_SYS_LDT 2
512%define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
513%define X86_SEL_TYPE_SYS_286_CALL_GATE 4
514%define X86_SEL_TYPE_SYS_TASK_GATE 5
515%define X86_SEL_TYPE_SYS_286_INT_GATE 6
516%define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
517%define X86_SEL_TYPE_SYS_UNDEFINED2 8
518%define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
519%define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
520%define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
521%define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
522%define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
523%define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
524%define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
525%define AMD64_SEL_TYPE_SYS_LDT 2
526%define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
527%define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
528%define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
529%define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
530%define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
531%define X86_DESC_TYPE_MASK (RT_BIT(8) | RT_BIT(9) | RT_BIT(10) | RT_BIT(11))
532%define X86_DESC_S RT_BIT(12)
533%define X86_DESC_DPL (RT_BIT(13) | RT_BIT(14))
534%define X86_DESC_P RT_BIT(15)
535%define X86_DESC_AVL RT_BIT(20)
536%define X86_DESC_DB RT_BIT(22)
537%define X86_DESC_G RT_BIT(23)
538%define X86_SEL_SHIFT 3
539%define X86_SEL_MASK 0xfff8
540%define X86_SEL_LDT 0x0004
541%define X86_SEL_RPL 0x0003
542%define X86_TRAP_ERR_EXTERNAL 1
543%define X86_TRAP_ERR_IDT 2
544%define X86_TRAP_ERR_TI 4
545%define X86_TRAP_ERR_SEL_MASK 0xfff8
546%define X86_TRAP_ERR_SEL_SHIFT 3
547%define X86_TRAP_PF_P RT_BIT(0)
548%define X86_TRAP_PF_RW RT_BIT(1)
549%define X86_TRAP_PF_US RT_BIT(2)
550%define X86_TRAP_PF_RSVD RT_BIT(3)
551%define X86_TRAP_PF_ID RT_BIT(4)
552%define X86_MODRM_RM_MASK 0x07
553%define X86_MODRM_REG_MASK 0x38
554%define X86_MODRM_REG_SMASK 0x07
555%define X86_MODRM_REG_SHIFT 3
556%define X86_MODRM_MOD_MASK 0xc0
557%define X86_MODRM_MOD_SMASK 0x03
558%define X86_MODRM_MOD_SHIFT 6
559%define X86_SIB_BASE_MASK 0x07
560%define X86_SIB_INDEX_MASK 0x38
561%define X86_SIB_INDEX_SMASK 0x07
562%define X86_SIB_INDEX_SHIFT 3
563%define X86_SIB_SCALE_MASK 0xc0
564%define X86_SIB_SCALE_SMASK 0x03
565%define X86_SIB_SCALE_SHIFT 6
566%define X86_GREG_xAX 0
567%define X86_GREG_xCX 1
568%define X86_GREG_xDX 2
569%define X86_GREG_xBX 3
570%define X86_GREG_xSP 4
571%define X86_GREG_xBP 5
572%define X86_GREG_xSI 6
573%define X86_GREG_xDI 7
574%define X86_GREG_x8 8
575%define X86_GREG_x9 9
576%define X86_GREG_x10 10
577%define X86_GREG_x11 11
578%define X86_GREG_x12 12
579%define X86_GREG_x13 13
580%define X86_GREG_x14 14
581%define X86_GREG_x15 15
582%define X86_SREG_ES 0
583%define X86_SREG_CS 1
584%define X86_SREG_SS 2
585%define X86_SREG_DS 3
586%define X86_SREG_FS 4
587%define X86_SREG_GS 5
588%endif
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