x86.mac@ 47660

Last change on this file since 47660 was 47442, checked in by vboxsync, 11 years ago
Adjusted some HMVMX status codes so that VERR_VMX_INVALID_VMCS_PTR and VERR_VMX_INVALID_VMCS_FIELD can be ORed together with (according to my calculator) with VERR_VMX_INVALID_VMCS_PTR as the result.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 35.7 KB

Line
1	%ifndef ___iprt_x86_h
2	%define ___iprt_x86_h
3	%ifndef VBOX_FOR_DTRACE_LIB
4	%else
5	%endif
6	%ifdef RT_OS_SOLARIS
7	%endif
8	%ifndef VBOX_FOR_DTRACE_LIB
9	%endif
10	%ifndef VBOX_FOR_DTRACE_LIB
11	%endif
12	%ifndef VBOX_FOR_DTRACE_LIB
13	%endif
14	%define X86_EFL_CF RT_BIT(0)
15	%define X86_EFL_1 RT_BIT(1)
16	%define X86_EFL_PF RT_BIT(2)
17	%define X86_EFL_AF RT_BIT(4)
18	%define X86_EFL_ZF RT_BIT(6)
19	%define X86_EFL_SF RT_BIT(7)
20	%define X86_EFL_TF RT_BIT(8)
21	%define X86_EFL_IF RT_BIT(9)
22	%define X86_EFL_DF RT_BIT(10)
23	%define X86_EFL_OF RT_BIT(11)
24	%define X86_EFL_IOPL (RT_BIT(12) \| RT_BIT(13))
25	%define X86_EFL_NT RT_BIT(14)
26	%define X86_EFL_RF RT_BIT(16)
27	%define X86_EFL_VM RT_BIT(17)
28	%define X86_EFL_AC RT_BIT(18)
29	%define X86_EFL_VIF RT_BIT(19)
30	%define X86_EFL_VIP RT_BIT(20)
31	%define X86_EFL_ID RT_BIT(21)
32	%define X86_EFL_IOPL_SHIFT 12
33	%define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
34	%define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
35	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
36	%ifndef VBOX_FOR_DTRACE_LIB
37	%else
38	%endif
39	%ifndef VBOX_FOR_DTRACE_LIB
40	%else
41	%endif
42	%define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547
43	%define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e
44	%define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69
45	%define X86_CPUID_VENDOR_AMD_EBX 0x68747541
46	%define X86_CPUID_VENDOR_AMD_ECX 0x444d4163
47	%define X86_CPUID_VENDOR_AMD_EDX 0x69746e65
48	%define X86_CPUID_VENDOR_VIA_EBX 0x746e6543
49	%define X86_CPUID_VENDOR_VIA_ECX 0x736c7561
50	%define X86_CPUID_VENDOR_VIA_EDX 0x48727561
51	%define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT(0)
52	%define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT(1)
53	%define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT(2)
54	%define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT(3)
55	%define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT(4)
56	%define X86_CPUID_FEATURE_ECX_VMX RT_BIT(5)
57	%define X86_CPUID_FEATURE_ECX_SMX RT_BIT(6)
58	%define X86_CPUID_FEATURE_ECX_EST RT_BIT(7)
59	%define X86_CPUID_FEATURE_ECX_TM2 RT_BIT(8)
60	%define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT(9)
61	%define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT(10)
62	%define X86_CPUID_FEATURE_ECX_FMA RT_BIT(12)
63	%define X86_CPUID_FEATURE_ECX_CX16 RT_BIT(13)
64	%define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT(14)
65	%define X86_CPUID_FEATURE_ECX_PDCM RT_BIT(15)
66	%define X86_CPUID_FEATURE_ECX_PCID RT_BIT(17)
67	%define X86_CPUID_FEATURE_ECX_DCA RT_BIT(18)
68	%define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT(19)
69	%define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT(20)
70	%define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT(21)
71	%define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT(22)
72	%define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT(23)
73	%define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT(24)
74	%define X86_CPUID_FEATURE_ECX_AES RT_BIT(25)
75	%define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT(26)
76	%define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT(27)
77	%define X86_CPUID_FEATURE_ECX_AVX RT_BIT(28)
78	%define X86_CPUID_FEATURE_ECX_HVP RT_BIT(31)
79	%define X86_CPUID_FEATURE_EDX_FPU RT_BIT(0)
80	%define X86_CPUID_FEATURE_EDX_VME RT_BIT(1)
81	%define X86_CPUID_FEATURE_EDX_DE RT_BIT(2)
82	%define X86_CPUID_FEATURE_EDX_PSE RT_BIT(3)
83	%define X86_CPUID_FEATURE_EDX_TSC RT_BIT(4)
84	%define X86_CPUID_FEATURE_EDX_MSR RT_BIT(5)
85	%define X86_CPUID_FEATURE_EDX_PAE RT_BIT(6)
86	%define X86_CPUID_FEATURE_EDX_MCE RT_BIT(7)
87	%define X86_CPUID_FEATURE_EDX_CX8 RT_BIT(8)
88	%define X86_CPUID_FEATURE_EDX_APIC RT_BIT(9)
89	%define X86_CPUID_FEATURE_EDX_SEP RT_BIT(11)
90	%define X86_CPUID_FEATURE_EDX_MTRR RT_BIT(12)
91	%define X86_CPUID_FEATURE_EDX_PGE RT_BIT(13)
92	%define X86_CPUID_FEATURE_EDX_MCA RT_BIT(14)
93	%define X86_CPUID_FEATURE_EDX_CMOV RT_BIT(15)
94	%define X86_CPUID_FEATURE_EDX_PAT RT_BIT(16)
95	%define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT(17)
96	%define X86_CPUID_FEATURE_EDX_PSN RT_BIT(18)
97	%define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT(19)
98	%define X86_CPUID_FEATURE_EDX_DS RT_BIT(21)
99	%define X86_CPUID_FEATURE_EDX_ACPI RT_BIT(22)
100	%define X86_CPUID_FEATURE_EDX_MMX RT_BIT(23)
101	%define X86_CPUID_FEATURE_EDX_FXSR RT_BIT(24)
102	%define X86_CPUID_FEATURE_EDX_SSE RT_BIT(25)
103	%define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT(26)
104	%define X86_CPUID_FEATURE_EDX_SS RT_BIT(27)
105	%define X86_CPUID_FEATURE_EDX_HTT RT_BIT(28)
106	%define X86_CPUID_FEATURE_EDX_TM RT_BIT(29)
107	%define X86_CPUID_FEATURE_EDX_PBE RT_BIT(31)
108	%define X86_CPUID_MWAIT_ECX_EXT RT_BIT(0)
109	%define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT(1)
110	%define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT(0)
111	%define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT(11)
112	%define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT(20)
113	%define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT(26)
114	%define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT(27)
115	%define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT(29)
116	%define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT(0)
117	%define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT(1)
118	%define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT(2)
119	%define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT(3)
120	%define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT(4)
121	%define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT(5)
122	%define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT(6)
123	%define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT(7)
124	%define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT(8)
125	%define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT(9)
126	%define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT(12)
127	%define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT(13)
128	%define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT(14)
129	%define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT(15)
130	%define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT(16)
131	%define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT(17)
132	%define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT(22)
133	%define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT(23)
134	%define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT(24)
135	%define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT(25)
136	%define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT(30)
137	%define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT(31)
138	%define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT(1)
139	%define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT(2)
140	%define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT(3)
141	%define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT(4)
142	%define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT(5)
143	%define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT(6)
144	%define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT(7)
145	%define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT(8)
146	%define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT(9)
147	%define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT(10)
148	%define X86_CPUID_AMD_FEATURE_ECX_SSE5 RT_BIT(11)
149	%define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT(12)
150	%define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT(13)
151	%define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT(0)
152	%define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT(1)
153	%define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT(2)
154	%define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT(3)
155	%define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT(4)
156	%define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT(5)
157	%define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT(6)
158	%define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT(7)
159	%define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT(8)
160	%define X86_CR0_PE RT_BIT(0)
161	%define X86_CR0_PROTECTION_ENABLE RT_BIT(0)
162	%define X86_CR0_MP RT_BIT(1)
163	%define X86_CR0_MONITOR_COPROCESSOR RT_BIT(1)
164	%define X86_CR0_EM RT_BIT(2)
165	%define X86_CR0_EMULATE_FPU RT_BIT(2)
166	%define X86_CR0_TS RT_BIT(3)
167	%define X86_CR0_TASK_SWITCH RT_BIT(3)
168	%define X86_CR0_ET RT_BIT(4)
169	%define X86_CR0_EXTENSION_TYPE RT_BIT(4)
170	%define X86_CR0_NE RT_BIT(5)
171	%define X86_CR0_NUMERIC_ERROR RT_BIT(5)
172	%define X86_CR0_WP RT_BIT(16)
173	%define X86_CR0_WRITE_PROTECT RT_BIT(16)
174	%define X86_CR0_AM RT_BIT(18)
175	%define X86_CR0_ALIGMENT_MASK RT_BIT(18)
176	%define X86_CR0_NW RT_BIT(29)
177	%define X86_CR0_NOT_WRITE_THROUGH RT_BIT(29)
178	%define X86_CR0_CD RT_BIT(30)
179	%define X86_CR0_CACHE_DISABLE RT_BIT(30)
180	%define X86_CR0_PG RT_BIT(31)
181	%define X86_CR0_PAGING RT_BIT(31)
182	%define X86_CR3_PWT RT_BIT(3)
183	%define X86_CR3_PCD RT_BIT(4)
184	%define X86_CR3_PAGE_MASK (0xfffff000)
185	%define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
186	%define X86_CR3_AMD64_PAGE_MASK 0x000ffffffffff000
187	%define X86_CR4_VME RT_BIT(0)
188	%define X86_CR4_PVI RT_BIT(1)
189	%define X86_CR4_TSD RT_BIT(2)
190	%define X86_CR4_DE RT_BIT(3)
191	%define X86_CR4_PSE RT_BIT(4)
192	%define X86_CR4_PAE RT_BIT(5)
193	%define X86_CR4_MCE RT_BIT(6)
194	%define X86_CR4_PGE RT_BIT(7)
195	%define X86_CR4_PCE RT_BIT(8)
196	%define X86_CR4_OSFSXR RT_BIT(9)
197	%define X86_CR4_OSXMMEEXCPT RT_BIT(10)
198	%define X86_CR4_VMXE RT_BIT(13)
199	%define X86_CR4_SMXE RT_BIT(14)
200	%define X86_CR4_PCIDE RT_BIT(17)
201	%define X86_CR4_OSXSAVE RT_BIT(18)
202	%define X86_CR4_SMEP RT_BIT(20)
203	%define X86_DR6_B0 RT_BIT(0)
204	%define X86_DR6_B1 RT_BIT(1)
205	%define X86_DR6_B2 RT_BIT(2)
206	%define X86_DR6_B3 RT_BIT(3)
207	%define X86_DR6_B_MASK 0x0000000f
208	%define X86_DR6_BD RT_BIT(13)
209	%define X86_DR6_BS RT_BIT(14)
210	%define X86_DR6_BT RT_BIT(15)
211	%define X86_DR6_INIT_VAL 0xFFFF0FF0
212	%define X86_DR6_RA1_MASK 0xffff0ff0
213	%define X86_DR6_RAZ_MASK RT_BIT_64(12)
214	%define X86_DR6_MBZ_MASK 0xffffffff00000000
215	%define X86_DR6_B(iBp) RT_BIT_64(iBp)
216	%define X86_DR7_L0 RT_BIT(0)
217	%define X86_DR7_G0 RT_BIT(1)
218	%define X86_DR7_L1 RT_BIT(2)
219	%define X86_DR7_G1 RT_BIT(3)
220	%define X86_DR7_L2 RT_BIT(4)
221	%define X86_DR7_G2 RT_BIT(5)
222	%define X86_DR7_L3 RT_BIT(6)
223	%define X86_DR7_G3 RT_BIT(7)
224	%define X86_DR7_LE RT_BIT(8)
225	%define X86_DR7_GE RT_BIT(9)
226	%define X86_DR7_GD RT_BIT(13)
227	%define X86_DR7_RW0_MASK (3 << 16)
228	%define X86_DR7_LEN0_MASK (3 << 18)
229	%define X86_DR7_RW1_MASK (3 << 20)
230	%define X86_DR7_LEN1_MASK (3 << 22)
231	%define X86_DR7_RW2_MASK (3 << 24)
232	%define X86_DR7_LEN2_MASK (3 << 26)
233	%define X86_DR7_RW3_MASK (3 << 28)
234	%define X86_DR7_LEN3_MASK (3 << 30)
235	%define X86_DR7_RA1_MASK (RT_BIT(10))
236	%define X86_DR7_RAZ_MASK 0x0000d800
237	%define X86_DR7_MBZ_MASK 0xffffffff00000000
238	%define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
239	%define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
240	%define X86_DR7_L_G(iBp) ( 3 << (iBp * 2) )
241	%define X86_DR7_RW_EO 0
242	%define X86_DR7_RW_WO 1
243	%define X86_DR7_RW_IO 2
244	%define X86_DR7_RW_RW 3
245	%define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
246	%define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & 3 )
247	%define X86_DR7_RW_ALL_MASKS 0x33330000
248	%define X86_DR7_ANY_RW_IO(uDR7) \
249	( ( 0x22220000 & (uDR7) )
250	%define X86_DR7_LEN_BYTE 0
251	%define X86_DR7_LEN_WORD 1
252	%define X86_DR7_LEN_QWORD 2
253	%define X86_DR7_LEN_DWORD 3
254	%define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
255	%define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3 )
256	%define X86_DR7_ENABLED_MASK 0x000000ff
257	%define X86_DR7_INIT_VAL 0x400
258	%define MSR_IA32_TSC 0x10
259	%define MSR_IA32_PLATFORM_ID 0x17
260	%ifndef MSR_IA32_APICBASE
261	%define MSR_IA32_APICBASE 0x1b
262	%endif
263	%define MSR_IA32_FEATURE_CONTROL 0x3A
264	%define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT(0)
265	%define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT(2)
266	%define MSR_IA32_BIOS_UPDT_TRIG 0x79
267	%define MSR_IA32_BIOS_SIGN_ID 0x8B
268	%define MSR_IA32_PMC0 0xC1
269	%define MSR_IA32_PMC1 0xC2
270	%define MSR_IA32_PMC2 0xC3
271	%define MSR_IA32_PMC3 0xC4
272	%define MSR_IA32_PLATFORM_INFO 0xCE
273	%define MSR_IA32_FSB_CLOCK_STS 0xCD
274	%define MSR_IA32_MTRR_CAP 0xFE
275	%ifndef MSR_IA32_SYSENTER_CS
276	%define MSR_IA32_SYSENTER_CS 0x174
277	%define MSR_IA32_SYSENTER_ESP 0x175
278	%define MSR_IA32_SYSENTER_EIP 0x176
279	%endif
280	%define MSR_IA32_MCP_CAP 0x179
281	%define MSR_IA32_MCP_STATUS 0x17A
282	%define MSR_IA32_MCP_CTRL 0x17B
283	%define MSR_IA32_DEBUGCTL 0x1D9
284	%define MSR_IA32_CR_PAT 0x277
285	%define MSR_IA32_PERFEVTSEL0 0x186
286	%define MSR_IA32_PERFEVTSEL1 0x187
287	%define MSR_IA32_FLEX_RATIO 0x194
288	%define MSR_IA32_PERF_STATUS 0x198
289	%define MSR_IA32_PERF_CTL 0x199
290	%define MSR_IA32_THERM_STATUS 0x19c
291	%define MSR_IA32_MISC_ENABLE 0x1A0
292	%define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT(0)
293	%define MSR_IA32_MISC_ENABLE_TCC RT_BIT(3)
294	%define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT(7)
295	%define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT(11)
296	%define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT(12)
297	%define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT(16)
298	%define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT(18)
299	%define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT(22)
300	%define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT(23)
301	%define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT(34)
302	%define IA32_MTRR_PHYSBASE0 0x200
303	%define IA32_MTRR_PHYSMASK0 0x201
304	%define IA32_MTRR_PHYSBASE1 0x202
305	%define IA32_MTRR_PHYSMASK1 0x203
306	%define IA32_MTRR_PHYSBASE2 0x204
307	%define IA32_MTRR_PHYSMASK2 0x205
308	%define IA32_MTRR_PHYSBASE3 0x206
309	%define IA32_MTRR_PHYSMASK3 0x207
310	%define IA32_MTRR_PHYSBASE4 0x208
311	%define IA32_MTRR_PHYSMASK4 0x209
312	%define IA32_MTRR_PHYSBASE5 0x20a
313	%define IA32_MTRR_PHYSMASK5 0x20b
314	%define IA32_MTRR_PHYSBASE6 0x20c
315	%define IA32_MTRR_PHYSMASK6 0x20d
316	%define IA32_MTRR_PHYSBASE7 0x20e
317	%define IA32_MTRR_PHYSMASK7 0x20f
318	%define IA32_MTRR_PHYSBASE8 0x210
319	%define IA32_MTRR_PHYSMASK8 0x211
320	%define IA32_MTRR_PHYSBASE9 0x212
321	%define IA32_MTRR_PHYSMASK9 0x213
322	%define IA32_MTRR_FIX64K_00000 0x250
323	%define IA32_MTRR_FIX16K_80000 0x258
324	%define IA32_MTRR_FIX16K_A0000 0x259
325	%define IA32_MTRR_FIX4K_C0000 0x268
326	%define IA32_MTRR_FIX4K_C8000 0x269
327	%define IA32_MTRR_FIX4K_D0000 0x26a
328	%define IA32_MTRR_FIX4K_D8000 0x26b
329	%define IA32_MTRR_FIX4K_E0000 0x26c
330	%define IA32_MTRR_FIX4K_E8000 0x26d
331	%define IA32_MTRR_FIX4K_F0000 0x26e
332	%define IA32_MTRR_FIX4K_F8000 0x26f
333	%define MSR_IA32_MTRR_DEF_TYPE 0x2FF
334	%define MSR_IA32_MC0_CTL 0x400
335	%define MSR_IA32_MC0_STATUS 0x401
336	%define MSR_IA32_VMX_BASIC_INFO 0x480
337	%define MSR_IA32_VMX_PINBASED_CTLS 0x481
338	%define MSR_IA32_VMX_PROCBASED_CTLS 0x482
339	%define MSR_IA32_VMX_EXIT_CTLS 0x483
340	%define MSR_IA32_VMX_ENTRY_CTLS 0x484
341	%define MSR_IA32_VMX_MISC 0x485
342	%define MSR_IA32_VMX_CR0_FIXED0 0x486
343	%define MSR_IA32_VMX_CR0_FIXED1 0x487
344	%define MSR_IA32_VMX_CR4_FIXED0 0x488
345	%define MSR_IA32_VMX_CR4_FIXED1 0x489
346	%define MSR_IA32_VMX_VMCS_ENUM 0x48A
347	%define MSR_IA32_VMX_VMFUNC 0x491
348	%define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
349	%define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
350	%define MSR_IA32_DS_AREA 0x600
351	%define MSR_IA32_X2APIC_START 0x800
352	%define MSR_IA32_X2APIC_TPR 0x808
353	%define MSR_IA32_X2APIC_END 0xBFF
354	%define MSR_K6_EFER 0xc0000080
355	%define MSR_K6_EFER_SCE RT_BIT(0)
356	%define MSR_K6_EFER_LME RT_BIT(8)
357	%define MSR_K6_EFER_LMA RT_BIT(10)
358	%define MSR_K6_EFER_NXE RT_BIT(11)
359	%define MSR_K6_EFER_SVME RT_BIT(12)
360	%define MSR_K6_EFER_LMSLE RT_BIT(13)
361	%define MSR_K6_EFER_FFXSR RT_BIT(14)
362	%define MSR_K6_STAR 0xc0000081
363	%define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
364	%define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
365	%define MSR_K6_STAR_SEL_MASK 0xffff
366	%define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
367	%define MSR_K6_WHCR 0xc0000082
368	%define MSR_K6_UWCCR 0xc0000085
369	%define MSR_K6_PSOR 0xc0000087
370	%define MSR_K6_PFIR 0xc0000088
371	%define MSR_K7_EVNTSEL0 0xc0010000
372	%define MSR_K7_EVNTSEL1 0xc0010001
373	%define MSR_K7_EVNTSEL2 0xc0010002
374	%define MSR_K7_EVNTSEL3 0xc0010003
375	%define MSR_K7_PERFCTR0 0xc0010004
376	%define MSR_K7_PERFCTR1 0xc0010005
377	%define MSR_K7_PERFCTR2 0xc0010006
378	%define MSR_K7_PERFCTR3 0xc0010007
379	%define MSR_K8_LSTAR 0xc0000082
380	%define MSR_K8_CSTAR 0xc0000083
381	%define MSR_K8_SF_MASK 0xc0000084
382	%define MSR_K8_FS_BASE 0xc0000100
383	%define MSR_K8_GS_BASE 0xc0000101
384	%define MSR_K8_KERNEL_GS_BASE 0xc0000102
385	%define MSR_K8_TSC_AUX 0xc0000103
386	%define MSR_K8_SYSCFG 0xc0010010
387	%define MSR_K8_HWCR 0xc0010015
388	%define MSR_K8_IORRBASE0 0xc0010016
389	%define MSR_K8_IORRMASK0 0xc0010017
390	%define MSR_K8_IORRBASE1 0xc0010018
391	%define MSR_K8_IORRMASK1 0xc0010019
392	%define MSR_K8_TOP_MEM1 0xc001001a
393	%define MSR_K8_TOP_MEM2 0xc001001d
394	%define MSR_K8_VM_CR 0xc0010114
395	%define MSR_K8_VM_CR_SVM_DISABLE RT_BIT(4)
396	%define MSR_K8_IGNNE 0xc0010115
397	%define MSR_K8_SMM_CTL 0xc0010116
398	%define MSR_K8_VM_HSAVE_PA 0xc0010117
399	%define X86_PG_ENTRIES 1024
400	%define X86_PG_PAE_ENTRIES 512
401	%define X86_PG_PAE_PDPE_ENTRIES 4
402	%define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
403	%define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
404	%define X86_PAGE_4K_SIZE _4K
405	%define X86_PAGE_4K_SHIFT 12
406	%define X86_PAGE_4K_OFFSET_MASK 0xfff
407	%define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000
408	%define X86_PAGE_4K_BASE_MASK_32 0xfffff000
409	%define X86_PAGE_2M_SIZE _2M
410	%define X86_PAGE_2M_SHIFT 21
411	%define X86_PAGE_2M_OFFSET_MASK 0x001fffff
412	%define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000
413	%define X86_PAGE_2M_BASE_MASK_32 0xffe00000
414	%define X86_PAGE_4M_SIZE _4M
415	%define X86_PAGE_4M_SHIFT 22
416	%define X86_PAGE_4M_OFFSET_MASK 0x003fffff
417	%define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000
418	%define X86_PAGE_4M_BASE_MASK_32 0xffc00000
419	%define X86_PTE_BIT_P 0
420	%define X86_PTE_BIT_RW 1
421	%define X86_PTE_BIT_US 2
422	%define X86_PTE_BIT_PWT 3
423	%define X86_PTE_BIT_PCD 4
424	%define X86_PTE_BIT_A 5
425	%define X86_PTE_BIT_D 6
426	%define X86_PTE_BIT_PAT 7
427	%define X86_PTE_BIT_G 8
428	%define X86_PTE_P RT_BIT(0)
429	%define X86_PTE_RW RT_BIT(1)
430	%define X86_PTE_US RT_BIT(2)
431	%define X86_PTE_PWT RT_BIT(3)
432	%define X86_PTE_PCD RT_BIT(4)
433	%define X86_PTE_A RT_BIT(5)
434	%define X86_PTE_D RT_BIT(6)
435	%define X86_PTE_PAT RT_BIT(7)
436	%define X86_PTE_G RT_BIT(8)
437	%define X86_PTE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
438	%define X86_PTE_PG_MASK ( 0xfffff000 )
439	%define X86_PTE_PAE_PG_MASK 0x000ffffffffff000
440	%define X86_PTE_PAE_NX RT_BIT_64(63)
441	%define X86_PTE_PAE_MBZ_MASK_NX 0x7ff0000000000000
442	%define X86_PTE_PAE_MBZ_MASK_NO_NX 0xfff0000000000000
443	%define X86_PTE_LM_MBZ_MASK_NX 0x0000000000000000
444	%define X86_PTE_LM_MBZ_MASK_NO_NX 0x8000000000000000
445	%define X86_PT_SHIFT 12
446	%define X86_PT_MASK 0x3ff
447	%define X86_PT_PAE_SHIFT 12
448	%define X86_PT_PAE_MASK 0x1ff
449	%define X86_PDE_P RT_BIT(0)
450	%define X86_PDE_RW RT_BIT(1)
451	%define X86_PDE_US RT_BIT(2)
452	%define X86_PDE_PWT RT_BIT(3)
453	%define X86_PDE_PCD RT_BIT(4)
454	%define X86_PDE_A RT_BIT(5)
455	%define X86_PDE_PS RT_BIT(7)
456	%define X86_PDE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
457	%define X86_PDE_PG_MASK ( 0xfffff000 )
458	%define X86_PDE_PAE_PG_MASK 0x000ffffffffff000
459	%define X86_PDE_PAE_NX RT_BIT_64(63)
460	%define X86_PDE_PAE_MBZ_MASK_NX 0x7ff0000000000080
461	%define X86_PDE_PAE_MBZ_MASK_NO_NX 0xfff0000000000080
462	%define X86_PDE_LM_MBZ_MASK_NX 0x0000000000000080
463	%define X86_PDE_LM_MBZ_MASK_NO_NX 0x8000000000000080
464	%define X86_PDE4M_P RT_BIT(0)
465	%define X86_PDE4M_RW RT_BIT(1)
466	%define X86_PDE4M_US RT_BIT(2)
467	%define X86_PDE4M_PWT RT_BIT(3)
468	%define X86_PDE4M_PCD RT_BIT(4)
469	%define X86_PDE4M_A RT_BIT(5)
470	%define X86_PDE4M_D RT_BIT(6)
471	%define X86_PDE4M_PS RT_BIT(7)
472	%define X86_PDE4M_G RT_BIT(8)
473	%define X86_PDE4M_AVL (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
474	%define X86_PDE4M_PAT RT_BIT(12)
475	%define X86_PDE4M_PAT_SHIFT (12 - 7)
476	%define X86_PDE4M_PG_MASK ( 0xffc00000 )
477	%define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
478	%define X86_PDE4M_PG_HIGH_SHIFT 19
479	%define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
480	%define X86_PDE2M_PAE_PG_MASK 0x000fffffffe00000
481	%define X86_PDE2M_PAE_NX RT_BIT_64(63)
482	%define X86_PDE2M_PAE_MBZ_MASK_NX 0x7ff00000001fe000
483	%define X86_PDE2M_PAE_MBZ_MASK_NO_NX 0xfff00000001fe000
484	%define X86_PDE2M_LM_MBZ_MASK_NX 0x00000000001fe000
485	%define X86_PDE2M_LM_MBZ_MASK_NO_NX 0x80000000001fe000
486	%define X86_PD_SHIFT 22
487	%define X86_PD_MASK 0x3ff
488	%define X86_PD_PAE_SHIFT 21
489	%define X86_PD_PAE_MASK 0x1ff
490	%define X86_PDPE_P RT_BIT(0)
491	%define X86_PDPE_RW RT_BIT(1)
492	%define X86_PDPE_US RT_BIT(2)
493	%define X86_PDPE_PWT RT_BIT(3)
494	%define X86_PDPE_PCD RT_BIT(4)
495	%define X86_PDPE_A RT_BIT(5)
496	%define X86_PDPE_LM_PS RT_BIT(7)
497	%define X86_PDPE_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
498	%define X86_PDPE_PG_MASK 0x000ffffffffff000
499	%define X86_PDPE_PAE_MBZ_MASK 0xfff00000000001e6
500	%define X86_PDPE_LM_NX RT_BIT_64(63)
501	%define X86_PDPE_LM_MBZ_MASK_NX 0x0000000000000180
502	%define X86_PDPE_LM_MBZ_MASK_NO_NX 0x8000000000000180
503	%define X86_PDPE1G_LM_MBZ_MASK_NX 0x000000003fffe000
504	%define X86_PDPE1G_LM_MBZ_MASK_NO_NX 0x800000003fffe000
505	%define X86_PDPT_SHIFT 30
506	%define X86_PDPT_MASK_PAE 0x3
507	%define X86_PDPT_MASK_AMD64 0x1ff
508	%define X86_PML4E_P RT_BIT(0)
509	%define X86_PML4E_RW RT_BIT(1)
510	%define X86_PML4E_US RT_BIT(2)
511	%define X86_PML4E_PWT RT_BIT(3)
512	%define X86_PML4E_PCD RT_BIT(4)
513	%define X86_PML4E_A RT_BIT(5)
514	%define X86_PML4E_AVL_MASK (RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
515	%define X86_PML4E_PG_MASK 0x000ffffffffff000
516	%define X86_PML4E_MBZ_MASK_NX 0x0000000000000080
517	%define X86_PML4E_MBZ_MASK_NO_NX 0x8000000000000080
518	%define X86_PML4E_NX RT_BIT_64(63)
519	%define X86_PML4_SHIFT 39
520	%define X86_PML4_MASK 0x1ff
521	%define X86_FSW_IE RT_BIT(0)
522	%define X86_FSW_DE RT_BIT(1)
523	%define X86_FSW_ZE RT_BIT(2)
524	%define X86_FSW_OE RT_BIT(3)
525	%define X86_FSW_UE RT_BIT(4)
526	%define X86_FSW_PE RT_BIT(5)
527	%define X86_FSW_SF RT_BIT(6)
528	%define X86_FSW_ES RT_BIT(7)
529	%define X86_FSW_XCPT_MASK 0x007f
530	%define X86_FSW_XCPT_ES_MASK 0x00ff
531	%define X86_FSW_C0 RT_BIT(8)
532	%define X86_FSW_C1 RT_BIT(9)
533	%define X86_FSW_C2 RT_BIT(10)
534	%define X86_FSW_TOP_MASK 0x3800
535	%define X86_FSW_TOP_SHIFT 11
536	%define X86_FSW_TOP_SMASK 0x0007
537	%define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
538	%define X86_FSW_C3 RT_BIT(14)
539	%define X86_FSW_C_MASK 0x4700
540	%define X86_FSW_B RT_BIT(15)
541	%define X86_FCW_IM RT_BIT(0)
542	%define X86_FCW_DM RT_BIT(1)
543	%define X86_FCW_ZM RT_BIT(2)
544	%define X86_FCW_OM RT_BIT(3)
545	%define X86_FCW_UM RT_BIT(4)
546	%define X86_FCW_PM RT_BIT(5)
547	%define X86_FCW_MASK_ALL 0x007f
548	%define X86_FCW_XCPT_MASK 0x003f
549	%define X86_FCW_PC_MASK 0x0300
550	%define X86_FCW_PC_24 0x0000
551	%define X86_FCW_PC_RSVD 0x0100
552	%define X86_FCW_PC_53 0x0200
553	%define X86_FCW_PC_64 0x0300
554	%define X86_FCW_RC_MASK 0x0c00
555	%define X86_FCW_RC_NEAREST 0x0000
556	%define X86_FCW_RC_DOWN 0x0400
557	%define X86_FCW_RC_UP 0x0800
558	%define X86_FCW_RC_ZERO 0x0c00
559	%define X86_FCW_ZERO_MASK 0xf080
560	%define X86_MSXCR_IE RT_BIT(0)
561	%define X86_MSXCR_DE RT_BIT(1)
562	%define X86_MSXCR_ZE RT_BIT(2)
563	%define X86_MSXCR_OE RT_BIT(3)
564	%define X86_MSXCR_UE RT_BIT(4)
565	%define X86_MSXCR_PE RT_BIT(5)
566	%define X86_MSXCR_DAZ RT_BIT(6)
567	%define X86_MSXCR_IM RT_BIT(7)
568	%define X86_MSXCR_DM RT_BIT(8)
569	%define X86_MSXCR_ZM RT_BIT(9)
570	%define X86_MSXCR_OM RT_BIT(10)
571	%define X86_MSXCR_UM RT_BIT(11)
572	%define X86_MSXCR_PM RT_BIT(12)
573	%define X86_MSXCR_RC_MASK 0x6000
574	%define X86_MSXCR_RC_NEAREST 0x0000
575	%define X86_MSXCR_RC_DOWN 0x2000
576	%define X86_MSXCR_RC_UP 0x4000
577	%define X86_MSXCR_RC_ZERO 0x6000
578	%define X86_MSXCR_FZ RT_BIT(15)
579	%define X86_MSXCR_MM RT_BIT(16)
580	%ifndef VBOX_FOR_DTRACE_LIB
581	%endif
582	%define X86DESCATTR_TYPE 0x0000000f
583	%define X86DESCATTR_DT 0x00000010
584	%define X86DESCATTR_DPL 0x00000060
585	%define X86DESCATTR_DPL_SHIFT 5
586	%define X86DESCATTR_P 0x00000800
587	%define X86DESCATTR_LIMIT_HIGH 0x00000f00
588	%define X86DESCATTR_AVL 0x00001000
589	%define X86DESCATTR_L 0x00002000
590	%define X86DESCATTR_D 0x00004000
591	%define X86DESCATTR_G 0x00008000
592	%define X86DESCATTR_UNUSABLE 0x00010000
593	%ifndef VBOX_FOR_DTRACE_LIB
594	%endif
595	%ifndef VBOX_FOR_DTRACE_LIB
596	%define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0)
597	%define X86DESCGENERIC_BIT_OFF_BASE_LOW (16)
598	%define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32)
599	%define X86DESCGENERIC_BIT_OFF_TYPE (40)
600	%define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44)
601	%define X86DESCGENERIC_BIT_OFF_DPL (45)
602	%define X86DESCGENERIC_BIT_OFF_PRESENT (47)
603	%define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48)
604	%define X86DESCGENERIC_BIT_OFF_AVAILABLE (52)
605	%define X86DESCGENERIC_BIT_OFF_LONG (53)
606	%define X86DESCGENERIC_BIT_OFF_DEF_BIG (54)
607	%define X86DESCGENERIC_BIT_OFF_GRANULARITY (55)
608	%define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56)
609	%endif
610	%ifndef VBOX_FOR_DTRACE_LIB
611	%endif
612	%ifndef VBOX_FOR_DTRACE_LIB
613	%endif
614	%ifndef VBOX_FOR_DTRACE_LIB
615	%endif
616	%ifndef VBOX_FOR_DTRACE_LIB
617	%endif
618	%ifndef VBOX_FOR_DTRACE_LIB
619	%endif
620	%if HC_ARCH_BITS == 64
621	%else
622	%endif
623	%if HC_ARCH_BITS == 64
624	%else
625	%endif
626	%if HC_ARCH_BITS == 64
627	%else
628	%endif
629	%define X86_SEL_TYPE_CODE 8
630	%define X86_SEL_TYPE_MEMORY RT_BIT(4)
631	%define X86_SEL_TYPE_ACCESSED 1
632	%define X86_SEL_TYPE_DOWN 4
633	%define X86_SEL_TYPE_CONF 4
634	%define X86_SEL_TYPE_WRITE 2
635	%define X86_SEL_TYPE_READ 2
636	%define X86_SEL_TYPE_READ_BIT 1
637	%define X86_SEL_TYPE_RO 0
638	%define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
639	%define X86_SEL_TYPE_RW 2
640	%define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
641	%define X86_SEL_TYPE_RO_DOWN 4
642	%define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
643	%define X86_SEL_TYPE_RW_DOWN 6
644	%define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
645	%define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
646	%define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
647	%define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
648	%define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
649	%define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
650	%define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
651	%define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
652	%define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
653	%define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
654	%define X86_SEL_TYPE_SYS_UNDEFINED 0
655	%define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
656	%define X86_SEL_TYPE_SYS_LDT 2
657	%define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
658	%define X86_SEL_TYPE_SYS_286_CALL_GATE 4
659	%define X86_SEL_TYPE_SYS_TASK_GATE 5
660	%define X86_SEL_TYPE_SYS_286_INT_GATE 6
661	%define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
662	%define X86_SEL_TYPE_SYS_UNDEFINED2 8
663	%define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
664	%define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
665	%define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
666	%define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
667	%define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
668	%define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
669	%define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
670	%define AMD64_SEL_TYPE_SYS_LDT 2
671	%define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
672	%define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
673	%define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
674	%define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
675	%define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
676	%define X86_DESC_TYPE_MASK (RT_BIT(8) \| RT_BIT(9) \| RT_BIT(10) \| RT_BIT(11))
677	%define X86_DESC_S RT_BIT(12)
678	%define X86_DESC_DPL (RT_BIT(13) \| RT_BIT(14))
679	%define X86_DESC_P RT_BIT(15)
680	%define X86_DESC_AVL RT_BIT(20)
681	%define X86_DESC_DB RT_BIT(22)
682	%define X86_DESC_G RT_BIT(23)
683	%ifndef VBOX_FOR_DTRACE_LIB
684	%endif
685	%ifndef VBOX_FOR_DTRACE_LIB
686	%endif
687	%define X86_SEL_SHIFT 3
688	%define X86_SEL_MASK 0xfff8
689	%define X86_SEL_MASK_OFF_RPL 0xfffc
690	%define X86_SEL_LDT 0x0004
691	%define X86_SEL_RPL 0x0003
692	%define X86_SEL_RPL_LDT 0x0007
693	%define X86_XCPT_MAX (X86_XCPT_SX)
694	%define X86_TRAP_ERR_EXTERNAL 1
695	%define X86_TRAP_ERR_IDT 2
696	%define X86_TRAP_ERR_TI 4
697	%define X86_TRAP_ERR_SEL_MASK 0xfff8
698	%define X86_TRAP_ERR_SEL_SHIFT 3
699	%define X86_TRAP_PF_P RT_BIT(0)
700	%define X86_TRAP_PF_RW RT_BIT(1)
701	%define X86_TRAP_PF_US RT_BIT(2)
702	%define X86_TRAP_PF_RSVD RT_BIT(3)
703	%define X86_TRAP_PF_ID RT_BIT(4)
704	%ifndef VBOX_FOR_DTRACE_LIB
705	%else
706	%endif
707	%ifndef VBOX_FOR_DTRACE_LIB
708	%else
709	%endif
710	%define X86_MODRM_RM_MASK 0x07
711	%define X86_MODRM_REG_MASK 0x38
712	%define X86_MODRM_REG_SMASK 0x07
713	%define X86_MODRM_REG_SHIFT 3
714	%define X86_MODRM_MOD_MASK 0xc0
715	%define X86_MODRM_MOD_SMASK 0x03
716	%define X86_MODRM_MOD_SHIFT 6
717	%ifndef VBOX_FOR_DTRACE_LIB
718	%endif
719	%define X86_SIB_BASE_MASK 0x07
720	%define X86_SIB_INDEX_MASK 0x38
721	%define X86_SIB_INDEX_SMASK 0x07
722	%define X86_SIB_INDEX_SHIFT 3
723	%define X86_SIB_SCALE_MASK 0xc0
724	%define X86_SIB_SCALE_SMASK 0x03
725	%define X86_SIB_SCALE_SHIFT 6
726	%ifndef VBOX_FOR_DTRACE_LIB
727	%endif
728	%define X86_GREG_xAX 0
729	%define X86_GREG_xCX 1
730	%define X86_GREG_xDX 2
731	%define X86_GREG_xBX 3
732	%define X86_GREG_xSP 4
733	%define X86_GREG_xBP 5
734	%define X86_GREG_xSI 6
735	%define X86_GREG_xDI 7
736	%define X86_GREG_x8 8
737	%define X86_GREG_x9 9
738	%define X86_GREG_x10 10
739	%define X86_GREG_x11 11
740	%define X86_GREG_x12 12
741	%define X86_GREG_x13 13
742	%define X86_GREG_x14 14
743	%define X86_GREG_x15 15
744	%define X86_SREG_ES 0
745	%define X86_SREG_CS 1
746	%define X86_SREG_SS 2
747	%define X86_SREG_DS 3
748	%define X86_SREG_FS 4
749	%define X86_SREG_GS 5
750	%define X86_SREG_COUNT 6
751	%define X86_OP_PRF_CS 0x2e
752	%define X86_OP_PRF_SS 0x36
753	%define X86_OP_PRF_DS 0x3e
754	%define X86_OP_PRF_ES 0x26
755	%define X86_OP_PRF_FS 0x64
756	%define X86_OP_PRF_GS 0x65
757	%define X86_OP_PRF_SIZE_OP 0x66
758	%define X86_OP_PRF_SIZE_ADDR 0x67
759	%define X86_OP_PRF_LOCK 0xf0
760	%define X86_OP_PRF_REPZ 0xf2
761	%define X86_OP_PRF_REPNZ 0xf3
762	%define X86_OP_REX_B 0x41
763	%define X86_OP_REX_X 0x42
764	%define X86_OP_REX_R 0x44
765	%define X86_OP_REX_W 0x48
766	%endif
767	%include "iprt/x86extra.mac"

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