x86.mac@ 73886

Last change on this file since 73886 was 70606, checked in by vboxsync, 7 years ago
updates (bugref:9087)
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 51.7 KB

Line
1	;; @file
2	; IPRT - X86 and AMD64 Structures and Definitions.
3	;
4	; Automatically generated by various.sed. DO NOT EDIT!
5	;
6
7	;
8	; Copyright (C) 2006-2017 Oracle Corporation
9	;
10	; This file is part of VirtualBox Open Source Edition (OSE), as
11	; available from http://www.virtualbox.org. This file is free software;
12	; you can redistribute it and/or modify it under the terms of the GNU
13	; General Public License (GPL) as published by the Free Software
14	; Foundation, in version 2 as it comes in the "COPYING" file of the
15	; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	;
18	; The contents of this file may alternatively be used under the terms
19	; of the Common Development and Distribution License Version 1.0
20	; (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21	; VirtualBox OSE distribution, in which case the provisions of the
22	; CDDL are applicable instead of those of the GPL.
23	;
24	; You may elect to license modified versions of this file under the
25	; terms and conditions of either the GPL or the CDDL or both.
26	;
27
28	%ifndef ___iprt_x86_h
29	%define ___iprt_x86_h
30	%ifndef VBOX_FOR_DTRACE_LIB
31	%else
32	%endif
33	%ifdef RT_OS_SOLARIS
34	%endif
35	%ifndef VBOX_FOR_DTRACE_LIB
36	%endif
37	%ifndef VBOX_FOR_DTRACE_LIB
38	%endif
39	%ifndef VBOX_FOR_DTRACE_LIB
40	%endif
41	%define X86_EFL_CF RT_BIT_32(0)
42	%define X86_EFL_CF_BIT 0
43	%define X86_EFL_1 RT_BIT_32(1)
44	%define X86_EFL_PF RT_BIT_32(2)
45	%define X86_EFL_AF RT_BIT_32(4)
46	%define X86_EFL_AF_BIT 4
47	%define X86_EFL_ZF RT_BIT_32(6)
48	%define X86_EFL_ZF_BIT 6
49	%define X86_EFL_SF RT_BIT_32(7)
50	%define X86_EFL_SF_BIT 7
51	%define X86_EFL_TF RT_BIT_32(8)
52	%define X86_EFL_IF RT_BIT_32(9)
53	%define X86_EFL_DF RT_BIT_32(10)
54	%define X86_EFL_OF RT_BIT_32(11)
55	%define X86_EFL_OF_BIT 11
56	%define X86_EFL_IOPL (RT_BIT_32(12) \| RT_BIT_32(13))
57	%define X86_EFL_NT RT_BIT_32(14)
58	%define X86_EFL_RF RT_BIT_32(16)
59	%define X86_EFL_VM RT_BIT_32(17)
60	%define X86_EFL_AC RT_BIT_32(18)
61	%define X86_EFL_VIF RT_BIT_32(19)
62	%define X86_EFL_VIP RT_BIT_32(20)
63	%define X86_EFL_ID RT_BIT_32(21)
64	%define X86_EFL_LIVE_MASK 0x003f7fd5
65	%define X86_EFL_RA1_MASK RT_BIT_32(1)
66	%define X86_EFL_IOPL_SHIFT 12
67	%define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
68	%define X86_EFL_POPF_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
69	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT \| X86_EFL_AC \| X86_EFL_ID )
70	%define X86_EFL_POPF_BITS_386 ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_TF \| X86_EFL_IF \
71	\| X86_EFL_DF \| X86_EFL_OF \| X86_EFL_IOPL \| X86_EFL_NT )
72	%define X86_EFL_STATUS_BITS ( X86_EFL_CF \| X86_EFL_PF \| X86_EFL_AF \| X86_EFL_ZF \| X86_EFL_SF \| X86_EFL_OF )
73	%ifndef VBOX_FOR_DTRACE_LIB
74	%else
75	%endif
76	%ifndef VBOX_FOR_DTRACE_LIB
77	%else
78	%endif
79	%define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547
80	%define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e
81	%define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69
82	%define X86_CPUID_VENDOR_AMD_EBX 0x68747541
83	%define X86_CPUID_VENDOR_AMD_ECX 0x444d4163
84	%define X86_CPUID_VENDOR_AMD_EDX 0x69746e65
85	%define X86_CPUID_VENDOR_VIA_EBX 0x746e6543
86	%define X86_CPUID_VENDOR_VIA_ECX 0x736c7561
87	%define X86_CPUID_VENDOR_VIA_EDX 0x48727561
88	%define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
89	%define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
90	%define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
91	%define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
92	%define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
93	%define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
94	%define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
95	%define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
96	%define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
97	%define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
98	%define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
99	%define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
100	%define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
101	%define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
102	%define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
103	%define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
104	%define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
105	%define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
106	%define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
107	%define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
108	%define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
109	%define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
110	%define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
111	%define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
112	%define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
113	%define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
114	%define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
115	%define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
116	%define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
117	%define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
118	%define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
119	%define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
120	%define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
121	%define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
122	%define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
123	%define X86_CPUID_FEATURE_EDX_PSE_BIT 3
124	%define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
125	%define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
126	%define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
127	%define X86_CPUID_FEATURE_EDX_PAE_BIT 6
128	%define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
129	%define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
130	%define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
131	%define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
132	%define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
133	%define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
134	%define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
135	%define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
136	%define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
137	%define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
138	%define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
139	%define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
140	%define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
141	%define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
142	%define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
143	%define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
144	%define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
145	%define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
146	%define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
147	%define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
148	%define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
149	%define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
150	%define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
151	%define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
152	%define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
153	%define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
154	%define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
155	%define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
156	%define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
157	%define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
158	%define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
159	%define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
160	%define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
161	%define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
162	%define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
163	%define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
164	%define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
165	%define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
166	%define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
167	%define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
168	%define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
169	%define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
170	%define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
171	%define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
172	%define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
173	%define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
174	%define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
175	%define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
176	%define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
177	%define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
178	%define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
179	%define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
180	%define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
181	%define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
182	%define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
183	%define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
184	%define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
185	%define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
186	%define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
187	%define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
188	%define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
189	%define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
190	%define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
191	%define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
192	%define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
193	%define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
194	%define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
195	%define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
196	%define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
197	%define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
198	%define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
199	%define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
200	%define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
201	%define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
202	%define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
203	%define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
204	%define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
205	%define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
206	%define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
207	%define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
208	%define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
209	%define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
210	%define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
211	%define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
212	%define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
213	%define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
214	%define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
215	%define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
216	%define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
217	%define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
218	%define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
219	%define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
220	%define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
221	%define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
222	%define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
223	%define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
224	%define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
225	%define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
226	%define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
227	%define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
228	%define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
229	%define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
230	%define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
231	%define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
232	%define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
233	%define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
234	%define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
235	%define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
236	%define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
237	%define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
238	%define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
239	%define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
240	%define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
241	%define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
242	%define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
243	%define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
244	%define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
245	%define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
246	%define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
247	%define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
248	%define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
249	%define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
250	%define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
251	%define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
252	%define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
253	%define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
254	%define X86_CR0_PE RT_BIT_32(0)
255	%define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
256	%define X86_CR0_MP RT_BIT_32(1)
257	%define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
258	%define X86_CR0_EM RT_BIT_32(2)
259	%define X86_CR0_EMULATE_FPU RT_BIT_32(2)
260	%define X86_CR0_TS RT_BIT_32(3)
261	%define X86_CR0_TASK_SWITCH RT_BIT_32(3)
262	%define X86_CR0_ET RT_BIT_32(4)
263	%define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
264	%define X86_CR0_NE RT_BIT_32(5)
265	%define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
266	%define X86_CR0_WP RT_BIT_32(16)
267	%define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
268	%define X86_CR0_AM RT_BIT_32(18)
269	%define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
270	%define X86_CR0_NW RT_BIT_32(29)
271	%define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
272	%define X86_CR0_CD RT_BIT_32(30)
273	%define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
274	%define X86_CR0_PG RT_BIT_32(31)
275	%define X86_CR0_PAGING RT_BIT_32(31)
276	%define X86_CR3_PWT RT_BIT_32(3)
277	%define X86_CR3_PCD RT_BIT_32(4)
278	%define X86_CR3_PAGE_MASK (0xfffff000)
279	%define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
280	%define X86_CR3_AMD64_PAGE_MASK 0x000ffffffffff000
281	%define X86_CR4_VME RT_BIT_32(0)
282	%define X86_CR4_PVI RT_BIT_32(1)
283	%define X86_CR4_TSD RT_BIT_32(2)
284	%define X86_CR4_DE RT_BIT_32(3)
285	%define X86_CR4_PSE RT_BIT_32(4)
286	%define X86_CR4_PAE RT_BIT_32(5)
287	%define X86_CR4_MCE RT_BIT_32(6)
288	%define X86_CR4_PGE RT_BIT_32(7)
289	%define X86_CR4_PCE RT_BIT_32(8)
290	%define X86_CR4_OSFXSR RT_BIT_32(9)
291	%define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
292	%define X86_CR4_VMXE RT_BIT_32(13)
293	%define X86_CR4_SMXE RT_BIT_32(14)
294	%define X86_CR4_PCIDE RT_BIT_32(17)
295	%define X86_CR4_OSXSAVE RT_BIT_32(18)
296	%define X86_CR4_SMEP RT_BIT_32(20)
297	%define X86_CR4_SMAP RT_BIT_32(21)
298	%define X86_CR4_PKE RT_BIT_32(22)
299	%define X86_DR6_B0 RT_BIT_32(0)
300	%define X86_DR6_B1 RT_BIT_32(1)
301	%define X86_DR6_B2 RT_BIT_32(2)
302	%define X86_DR6_B3 RT_BIT_32(3)
303	%define X86_DR6_B_MASK 0x0000000f
304	%define X86_DR6_BD RT_BIT_32(13)
305	%define X86_DR6_BS RT_BIT_32(14)
306	%define X86_DR6_BT RT_BIT_32(15)
307	%define X86_DR6_INIT_VAL 0xFFFF0FF0
308	%define X86_DR6_RA1_MASK 0xffff0ff0
309	%define X86_DR6_RAZ_MASK RT_BIT_64(12)
310	%define X86_DR6_MBZ_MASK 0xffffffff00000000
311	%define X86_DR6_B(iBp) RT_BIT_64(iBp)
312	%define X86_DR7_L0 RT_BIT_32(0)
313	%define X86_DR7_G0 RT_BIT_32(1)
314	%define X86_DR7_L1 RT_BIT_32(2)
315	%define X86_DR7_G1 RT_BIT_32(3)
316	%define X86_DR7_L2 RT_BIT_32(4)
317	%define X86_DR7_G2 RT_BIT_32(5)
318	%define X86_DR7_L3 RT_BIT_32(6)
319	%define X86_DR7_G3 RT_BIT_32(7)
320	%define X86_DR7_LE RT_BIT_32(8)
321	%define X86_DR7_GE RT_BIT_32(9)
322	%define X86_DR7_LE_ALL 0x0000000000000055
323	%define X86_DR7_GE_ALL 0x00000000000000aa
324	%define X86_DR7_ICE_IR RT_BIT_32(12)
325	%define X86_DR7_GD RT_BIT_32(13)
326	%define X86_DR7_ICE_TR1 RT_BIT_32(14)
327	%define X86_DR7_ICE_TR2 RT_BIT_32(15)
328	%define X86_DR7_RW0_MASK (3 << 16)
329	%define X86_DR7_LEN0_MASK (3 << 18)
330	%define X86_DR7_RW1_MASK (3 << 20)
331	%define X86_DR7_LEN1_MASK (3 << 22)
332	%define X86_DR7_RW2_MASK (3 << 24)
333	%define X86_DR7_LEN2_MASK (3 << 26)
334	%define X86_DR7_RW3_MASK (3 << 28)
335	%define X86_DR7_LEN3_MASK (3 << 30)
336	%define X86_DR7_RA1_MASK RT_BIT_32(10)
337	%define X86_DR7_RAZ_MASK 0x0000d800
338	%define X86_DR7_MBZ_MASK 0xffffffff00000000
339	%define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
340	%define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
341	%define X86_DR7_L_G(iBp) ( 3 << (iBp * 2) )
342	%define X86_DR7_RW_EO 0
343	%define X86_DR7_RW_WO 1
344	%define X86_DR7_RW_IO 2
345	%define X86_DR7_RW_RW 3
346	%define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
347	%define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & 3 )
348	%define X86_DR7_RW_ALL_MASKS 0x33330000
349	%ifndef VBOX_FOR_DTRACE_LIB
350	%define X86_DR7_ANY_RW_IO(uDR7) \
351	( ( 0x22220000 & (uDR7) )
352	%endif
353	%define X86_DR7_LEN_BYTE 0
354	%define X86_DR7_LEN_WORD 1
355	%define X86_DR7_LEN_QWORD 2
356	%define X86_DR7_LEN_DWORD 3
357	%define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
358	%define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3 )
359	%define X86_DR7_ENABLED_MASK 0x000000ff
360	%define X86_DR7_LEN_ALL_MASKS 0xcccc0000
361	%define X86_DR7_RW_LEN_ALL_MASKS 0xffff0000
362	%define X86_DR7_INIT_VAL 0x400
363	%define MSR_P5_MC_ADDR 0x00000000
364	%define MSR_P5_MC_TYPE 0x00000001
365	%define MSR_IA32_TSC 0x10
366	%define MSR_IA32_CESR 0x00000011
367	%define MSR_IA32_CTR0 0x00000012
368	%define MSR_IA32_CTR1 0x00000013
369	%define MSR_IA32_PLATFORM_ID 0x17
370	%ifndef MSR_IA32_APICBASE
371	%define MSR_IA32_APICBASE 0x1b
372	%define MSR_IA32_APICBASE_EN RT_BIT_64(11)
373	%define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
374	%define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
375	%define MSR_IA32_APICBASE_BASE_MIN 0x0000000ffffff000
376	%define MSR_IA32_APICBASE_ADDR 0x00000000fee00000
377	%define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
378	%endif
379	%define MSR_CORE_THREAD_COUNT 0x35
380	%define MSR_IA32_FEATURE_CONTROL 0x3A
381	%define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_32(0)
382	%define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_32(1)
383	%define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_32(2)
384	%define MSR_IA32_TSC_ADJUST 0x3B
385	%define MSR_IA32_SPEC_CTRL 0x48
386	%define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
387	%define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
388	%define MSR_IA32_PRED_CMD 0x49
389	%define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
390	%define MSR_IA32_BIOS_UPDT_TRIG 0x79
391	%define MSR_IA32_BIOS_SIGN_ID 0x8B
392	%define MSR_IA32_SMM_MONITOR_CTL 0x9B
393	%define MSR_IA32_PMC0 0xC1
394	%define MSR_IA32_PMC1 0xC2
395	%define MSR_IA32_PMC2 0xC3
396	%define MSR_IA32_PMC3 0xC4
397	%define MSR_IA32_PLATFORM_INFO 0xCE
398	%define MSR_IA32_FSB_CLOCK_STS 0xCD
399	%define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
400	%define MSR_IA32_MPERF 0xE7
401	%define MSR_IA32_APERF 0xE8
402	%define MSR_IA32_MTRR_CAP 0xFE
403	%define MSR_IA32_ARCH_CAP 0x10a
404	%define MSR_IA32_ARCH_CAP_F_SPECTRE_FIX RT_BIT_32(0)
405	%define MSR_IA32_ARCH_CAP_F_BETTER_IBRS RT_BIT_32(1)
406	%define MSR_BBL_CR_CTL3 0x11e
407	%ifndef MSR_IA32_SYSENTER_CS
408	%define MSR_IA32_SYSENTER_CS 0x174
409	%define MSR_IA32_SYSENTER_ESP 0x175
410	%define MSR_IA32_SYSENTER_EIP 0x176
411	%endif
412	%define MSR_IA32_MCG_CAP 0x179
413	%define MSR_IA32_MCG_STATUS 0x17A
414	%define MSR_IA32_MCG_CTRL 0x17B
415	%define MSR_IA32_CR_PAT 0x277
416	%define MSR_IA32_PERFEVTSEL0 0x186
417	%define MSR_IA32_PERFEVTSEL1 0x187
418	%define MSR_FLEX_RATIO 0x194
419	%define MSR_IA32_PERF_STATUS 0x198
420	%define MSR_IA32_PERF_CTL 0x199
421	%define MSR_IA32_THERM_STATUS 0x19c
422	%define MSR_IA32_MISC_ENABLE 0x1A0
423	%define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
424	%define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
425	%define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
426	%define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
427	%define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
428	%define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
429	%define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
430	%define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
431	%define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
432	%define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
433	%define MSR_IA32_DEBUGCTL 0x000001d9
434	%define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
435	%define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
436	%define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
437	%define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
438	%define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
439	%define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
440	%define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
441	%define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
442	%define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
443	%define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
444	%define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
445	%define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
446	%define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
447	%define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
448	%define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
449	%define MSR_P4_LASTBRANCH_TOS 0x000001da
450	%define MSR_P4_LASTBRANCH_0 0x000001db
451	%define MSR_P4_LASTBRANCH_1 0x000001dc
452	%define MSR_P4_LASTBRANCH_2 0x000001dd
453	%define MSR_P4_LASTBRANCH_3 0x000001de
454	%define IA32_MTRR_PHYSBASE0 0x200
455	%define IA32_MTRR_PHYSMASK0 0x201
456	%define IA32_MTRR_PHYSBASE1 0x202
457	%define IA32_MTRR_PHYSMASK1 0x203
458	%define IA32_MTRR_PHYSBASE2 0x204
459	%define IA32_MTRR_PHYSMASK2 0x205
460	%define IA32_MTRR_PHYSBASE3 0x206
461	%define IA32_MTRR_PHYSMASK3 0x207
462	%define IA32_MTRR_PHYSBASE4 0x208
463	%define IA32_MTRR_PHYSMASK4 0x209
464	%define IA32_MTRR_PHYSBASE5 0x20a
465	%define IA32_MTRR_PHYSMASK5 0x20b
466	%define IA32_MTRR_PHYSBASE6 0x20c
467	%define IA32_MTRR_PHYSMASK6 0x20d
468	%define IA32_MTRR_PHYSBASE7 0x20e
469	%define IA32_MTRR_PHYSMASK7 0x20f
470	%define IA32_MTRR_PHYSBASE8 0x210
471	%define IA32_MTRR_PHYSMASK8 0x211
472	%define IA32_MTRR_PHYSBASE9 0x212
473	%define IA32_MTRR_PHYSMASK9 0x213
474	%define IA32_MTRR_FIX64K_00000 0x250
475	%define IA32_MTRR_FIX16K_80000 0x258
476	%define IA32_MTRR_FIX16K_A0000 0x259
477	%define IA32_MTRR_FIX4K_C0000 0x268
478	%define IA32_MTRR_FIX4K_C8000 0x269
479	%define IA32_MTRR_FIX4K_D0000 0x26a
480	%define IA32_MTRR_FIX4K_D8000 0x26b
481	%define IA32_MTRR_FIX4K_E0000 0x26c
482	%define IA32_MTRR_FIX4K_E8000 0x26d
483	%define IA32_MTRR_FIX4K_F0000 0x26e
484	%define IA32_MTRR_FIX4K_F8000 0x26f
485	%define MSR_IA32_MTRR_DEF_TYPE 0x2FF
486	%define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
487	%define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
488	%define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
489	%define MSR_IA32_PEBS_ENABLE 0x3F1
490	%define MSR_IA32_MC0_CTL 0x400
491	%define MSR_IA32_MC0_STATUS 0x401
492	%define MSR_IA32_VMX_BASIC_INFO 0x480
493	%define MSR_IA32_VMX_PINBASED_CTLS 0x481
494	%define MSR_IA32_VMX_PROCBASED_CTLS 0x482
495	%define MSR_IA32_VMX_EXIT_CTLS 0x483
496	%define MSR_IA32_VMX_ENTRY_CTLS 0x484
497	%define MSR_IA32_VMX_MISC 0x485
498	%define MSR_IA32_VMX_CR0_FIXED0 0x486
499	%define MSR_IA32_VMX_CR0_FIXED1 0x487
500	%define MSR_IA32_VMX_CR4_FIXED0 0x488
501	%define MSR_IA32_VMX_CR4_FIXED1 0x489
502	%define MSR_IA32_VMX_VMCS_ENUM 0x48A
503	%define MSR_IA32_VMX_VMFUNC 0x491
504	%define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
505	%define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
506	%define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
507	%define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
508	%define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
509	%define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
510	%define MSR_IA32_DS_AREA 0x600
511	%define MSR_RAPL_POWER_UNIT 0x606
512	%define MSR_IA32_X2APIC_START 0x800
513	%define MSR_IA32_X2APIC_ID 0x802
514	%define MSR_IA32_X2APIC_VERSION 0x803
515	%define MSR_IA32_X2APIC_TPR 0x808
516	%define MSR_IA32_X2APIC_PPR 0x80A
517	%define MSR_IA32_X2APIC_EOI 0x80B
518	%define MSR_IA32_X2APIC_LDR 0x80D
519	%define MSR_IA32_X2APIC_SVR 0x80F
520	%define MSR_IA32_X2APIC_ISR0 0x810
521	%define MSR_IA32_X2APIC_ISR1 0x811
522	%define MSR_IA32_X2APIC_ISR2 0x812
523	%define MSR_IA32_X2APIC_ISR3 0x813
524	%define MSR_IA32_X2APIC_ISR4 0x814
525	%define MSR_IA32_X2APIC_ISR5 0x815
526	%define MSR_IA32_X2APIC_ISR6 0x816
527	%define MSR_IA32_X2APIC_ISR7 0x817
528	%define MSR_IA32_X2APIC_TMR0 0x818
529	%define MSR_IA32_X2APIC_TMR1 0x819
530	%define MSR_IA32_X2APIC_TMR2 0x81A
531	%define MSR_IA32_X2APIC_TMR3 0x81B
532	%define MSR_IA32_X2APIC_TMR4 0x81C
533	%define MSR_IA32_X2APIC_TMR5 0x81D
534	%define MSR_IA32_X2APIC_TMR6 0x81E
535	%define MSR_IA32_X2APIC_TMR7 0x81F
536	%define MSR_IA32_X2APIC_IRR0 0x820
537	%define MSR_IA32_X2APIC_IRR1 0x821
538	%define MSR_IA32_X2APIC_IRR2 0x822
539	%define MSR_IA32_X2APIC_IRR3 0x823
540	%define MSR_IA32_X2APIC_IRR4 0x824
541	%define MSR_IA32_X2APIC_IRR5 0x825
542	%define MSR_IA32_X2APIC_IRR6 0x826
543	%define MSR_IA32_X2APIC_IRR7 0x827
544	%define MSR_IA32_X2APIC_ESR 0x828
545	%define MSR_IA32_X2APIC_LVT_CMCI 0x82F
546	%define MSR_IA32_X2APIC_ICR 0x830
547	%define MSR_IA32_X2APIC_LVT_TIMER 0x832
548	%define MSR_IA32_X2APIC_LVT_THERMAL 0x833
549	%define MSR_IA32_X2APIC_LVT_PERF 0x834
550	%define MSR_IA32_X2APIC_LVT_LINT0 0x835
551	%define MSR_IA32_X2APIC_LVT_LINT1 0x836
552	%define MSR_IA32_X2APIC_LVT_ERROR 0x837
553	%define MSR_IA32_X2APIC_TIMER_ICR 0x838
554	%define MSR_IA32_X2APIC_TIMER_CCR 0x839
555	%define MSR_IA32_X2APIC_TIMER_DCR 0x83E
556	%define MSR_IA32_X2APIC_SELF_IPI 0x83F
557	%define MSR_IA32_X2APIC_END 0xBFF
558	%define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
559	%define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
560	%define MSR_K6_EFER 0xc0000080
561	%define MSR_K6_EFER_SCE RT_BIT_32(0)
562	%define MSR_K6_EFER_LME RT_BIT_32(8)
563	%define MSR_K6_EFER_LMA RT_BIT_32(10)
564	%define MSR_K6_EFER_NXE RT_BIT_32(11)
565	%define MSR_K6_EFER_BIT_NXE 11
566	%define MSR_K6_EFER_SVME RT_BIT_32(12)
567	%define MSR_K6_EFER_LMSLE RT_BIT_32(13)
568	%define MSR_K6_EFER_FFXSR RT_BIT_32(14)
569	%define MSR_K6_EFER_TCE RT_BIT_32(15)
570	%define MSR_K6_STAR 0xc0000081
571	%define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
572	%define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
573	%define MSR_K6_STAR_SEL_MASK 0xffff
574	%define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
575	%define MSR_K6_WHCR 0xc0000082
576	%define MSR_K6_UWCCR 0xc0000085
577	%define MSR_K6_PSOR 0xc0000087
578	%define MSR_K6_PFIR 0xc0000088
579	%define MSR_K7_EVNTSEL0 0xc0010000
580	%define MSR_K7_EVNTSEL1 0xc0010001
581	%define MSR_K7_EVNTSEL2 0xc0010002
582	%define MSR_K7_EVNTSEL3 0xc0010003
583	%define MSR_K7_PERFCTR0 0xc0010004
584	%define MSR_K7_PERFCTR1 0xc0010005
585	%define MSR_K7_PERFCTR2 0xc0010006
586	%define MSR_K7_PERFCTR3 0xc0010007
587	%define MSR_K8_LSTAR 0xc0000082
588	%define MSR_K8_CSTAR 0xc0000083
589	%define MSR_K8_SF_MASK 0xc0000084
590	%define MSR_K8_FS_BASE 0xc0000100
591	%define MSR_K8_GS_BASE 0xc0000101
592	%define MSR_K8_KERNEL_GS_BASE 0xc0000102
593	%define MSR_K8_TSC_AUX 0xc0000103
594	%define MSR_K8_SYSCFG 0xc0010010
595	%define MSR_K8_HWCR 0xc0010015
596	%define MSR_K8_IORRBASE0 0xc0010016
597	%define MSR_K8_IORRMASK0 0xc0010017
598	%define MSR_K8_IORRBASE1 0xc0010018
599	%define MSR_K8_IORRMASK1 0xc0010019
600	%define MSR_K8_TOP_MEM1 0xc001001a
601	%define MSR_K8_TOP_MEM2 0xc001001d
602	%define MSR_K8_NB_CFG 0xc001001f
603	%define MSR_K8_INT_PENDING 0xc0010055
604	%define MSR_K8_VM_CR 0xc0010114
605	%define MSR_K8_VM_CR_DPD RT_BIT_32(0)
606	%define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
607	%define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
608	%define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
609	%define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
610	%define MSR_K8_IGNNE 0xc0010115
611	%define MSR_K8_SMM_CTL 0xc0010116
612	%define MSR_K8_VM_HSAVE_PA 0xc0010117
613	%define X86_PG_ENTRIES 1024
614	%define X86_PG_PAE_ENTRIES 512
615	%define X86_PG_PAE_PDPE_ENTRIES 4
616	%define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
617	%define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
618	%define X86_PAGE_SIZE X86_PAGE_4K_SIZE
619	%define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
620	%define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
621	%define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
622	%define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
623	%define X86_PAGE_4K_SIZE _4K
624	%define X86_PAGE_4K_SHIFT 12
625	%define X86_PAGE_4K_OFFSET_MASK 0xfff
626	%define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000
627	%define X86_PAGE_4K_BASE_MASK_32 0xfffff000
628	%define X86_PAGE_2M_SIZE _2M
629	%define X86_PAGE_2M_SHIFT 21
630	%define X86_PAGE_2M_OFFSET_MASK 0x001fffff
631	%define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000
632	%define X86_PAGE_2M_BASE_MASK_32 0xffe00000
633	%define X86_PAGE_4M_SIZE _4M
634	%define X86_PAGE_4M_SHIFT 22
635	%define X86_PAGE_4M_OFFSET_MASK 0x003fffff
636	%define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000
637	%define X86_PAGE_4M_BASE_MASK_32 0xffc00000
638	%define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + 0x800000000000 < UINT64_C(0x1000000000000))
639	%define X86_PTE_BIT_P 0
640	%define X86_PTE_BIT_RW 1
641	%define X86_PTE_BIT_US 2
642	%define X86_PTE_BIT_PWT 3
643	%define X86_PTE_BIT_PCD 4
644	%define X86_PTE_BIT_A 5
645	%define X86_PTE_BIT_D 6
646	%define X86_PTE_BIT_PAT 7
647	%define X86_PTE_BIT_G 8
648	%define X86_PTE_PAE_BIT_NX 63
649	%define X86_PTE_P RT_BIT_32(0)
650	%define X86_PTE_RW RT_BIT_32(1)
651	%define X86_PTE_US RT_BIT_32(2)
652	%define X86_PTE_PWT RT_BIT_32(3)
653	%define X86_PTE_PCD RT_BIT_32(4)
654	%define X86_PTE_A RT_BIT_32(5)
655	%define X86_PTE_D RT_BIT_32(6)
656	%define X86_PTE_PAT RT_BIT_32(7)
657	%define X86_PTE_G RT_BIT_32(8)
658	%define X86_PTE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
659	%define X86_PTE_PG_MASK ( 0xfffff000 )
660	%define X86_PTE_PAE_PG_MASK 0x000ffffffffff000
661	%define X86_PTE_PAE_NX RT_BIT_64(63)
662	%define X86_PTE_PAE_MBZ_MASK_NX 0x7ff0000000000000
663	%define X86_PTE_PAE_MBZ_MASK_NO_NX 0xfff0000000000000
664	%define X86_PTE_LM_MBZ_MASK_NX 0x0000000000000000
665	%define X86_PTE_LM_MBZ_MASK_NO_NX 0x8000000000000000
666	%ifndef VBOX_FOR_DTRACE_LIB
667	%endif
668	%ifndef VBOX_FOR_DTRACE_LIB
669	%endif
670	%ifndef VBOX_FOR_DTRACE_LIB
671	%endif
672	%ifndef VBOX_FOR_DTRACE_LIB
673	%endif
674	%ifndef VBOX_FOR_DTRACE_LIB
675	%endif
676	%define X86_PT_SHIFT 12
677	%define X86_PT_MASK 0x3ff
678	%ifndef VBOX_FOR_DTRACE_LIB
679	%endif
680	%define X86_PT_PAE_SHIFT 12
681	%define X86_PT_PAE_MASK 0x1ff
682	%define X86_PDE_P RT_BIT_32(0)
683	%define X86_PDE_RW RT_BIT_32(1)
684	%define X86_PDE_US RT_BIT_32(2)
685	%define X86_PDE_PWT RT_BIT_32(3)
686	%define X86_PDE_PCD RT_BIT_32(4)
687	%define X86_PDE_A RT_BIT_32(5)
688	%define X86_PDE_PS RT_BIT_32(7)
689	%define X86_PDE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
690	%define X86_PDE_PG_MASK ( 0xfffff000 )
691	%define X86_PDE_PAE_PG_MASK 0x000ffffffffff000
692	%define X86_PDE_PAE_NX RT_BIT_64(63)
693	%define X86_PDE_PAE_MBZ_MASK_NX 0x7ff0000000000080
694	%define X86_PDE_PAE_MBZ_MASK_NO_NX 0xfff0000000000080
695	%define X86_PDE_LM_MBZ_MASK_NX 0x0000000000000080
696	%define X86_PDE_LM_MBZ_MASK_NO_NX 0x8000000000000080
697	%ifndef VBOX_FOR_DTRACE_LIB
698	%endif
699	%ifndef VBOX_FOR_DTRACE_LIB
700	%endif
701	%define X86_PDE4M_P RT_BIT_32(0)
702	%define X86_PDE4M_RW RT_BIT_32(1)
703	%define X86_PDE4M_US RT_BIT_32(2)
704	%define X86_PDE4M_PWT RT_BIT_32(3)
705	%define X86_PDE4M_PCD RT_BIT_32(4)
706	%define X86_PDE4M_A RT_BIT_32(5)
707	%define X86_PDE4M_D RT_BIT_32(6)
708	%define X86_PDE4M_PS RT_BIT_32(7)
709	%define X86_PDE4M_G RT_BIT_32(8)
710	%define X86_PDE4M_AVL (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
711	%define X86_PDE4M_PAT RT_BIT_32(12)
712	%define X86_PDE4M_PAT_SHIFT (12 - 7)
713	%define X86_PDE4M_PG_MASK ( 0xffc00000 )
714	%define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
715	%define X86_PDE4M_PG_HIGH_SHIFT 19
716	%define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
717	%define X86_PDE2M_PAE_PG_MASK 0x000fffffffe00000
718	%define X86_PDE2M_PAE_NX RT_BIT_64(63)
719	%define X86_PDE2M_PAE_MBZ_MASK_NX 0x7ff00000001fe000
720	%define X86_PDE2M_PAE_MBZ_MASK_NO_NX 0xfff00000001fe000
721	%define X86_PDE2M_LM_MBZ_MASK_NX 0x00000000001fe000
722	%define X86_PDE2M_LM_MBZ_MASK_NO_NX 0x80000000001fe000
723	%ifndef VBOX_FOR_DTRACE_LIB
724	%endif
725	%ifndef VBOX_FOR_DTRACE_LIB
726	%endif
727	%ifndef VBOX_FOR_DTRACE_LIB
728	%endif
729	%ifndef VBOX_FOR_DTRACE_LIB
730	%endif
731	%ifndef VBOX_FOR_DTRACE_LIB
732	%endif
733	%define X86_PD_SHIFT 22
734	%define X86_PD_MASK 0x3ff
735	%ifndef VBOX_FOR_DTRACE_LIB
736	%endif
737	%define X86_PD_PAE_SHIFT 21
738	%define X86_PD_PAE_MASK 0x1ff
739	%define X86_PDPE_P RT_BIT_32(0)
740	%define X86_PDPE_RW RT_BIT_32(1)
741	%define X86_PDPE_US RT_BIT_32(2)
742	%define X86_PDPE_PWT RT_BIT_32(3)
743	%define X86_PDPE_PCD RT_BIT_32(4)
744	%define X86_PDPE_A RT_BIT_32(5)
745	%define X86_PDPE_LM_PS RT_BIT_32(7)
746	%define X86_PDPE_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
747	%define X86_PDPE_PG_MASK 0x000ffffffffff000
748	%define X86_PDPE_PAE_MBZ_MASK 0xfff00000000001e6
749	%define X86_PDPE_LM_NX RT_BIT_64(63)
750	%define X86_PDPE_LM_MBZ_MASK_NX 0x0000000000000180
751	%define X86_PDPE_LM_MBZ_MASK_NO_NX 0x8000000000000180
752	%define X86_PDPE1G_LM_MBZ_MASK_NX 0x000000003fffe000
753	%define X86_PDPE1G_LM_MBZ_MASK_NO_NX 0x800000003fffe000
754	%ifndef VBOX_FOR_DTRACE_LIB
755	%endif
756	%ifndef VBOX_FOR_DTRACE_LIB
757	%endif
758	%ifndef VBOX_FOR_DTRACE_LIB
759	%endif
760	%ifndef VBOX_FOR_DTRACE_LIB
761	%endif
762	%ifndef VBOX_FOR_DTRACE_LIB
763	%endif
764	%define X86_PDPT_SHIFT 30
765	%define X86_PDPT_MASK_PAE 0x3
766	%define X86_PDPT_MASK_AMD64 0x1ff
767	%define X86_PML4E_P RT_BIT_32(0)
768	%define X86_PML4E_RW RT_BIT_32(1)
769	%define X86_PML4E_US RT_BIT_32(2)
770	%define X86_PML4E_PWT RT_BIT_32(3)
771	%define X86_PML4E_PCD RT_BIT_32(4)
772	%define X86_PML4E_A RT_BIT_32(5)
773	%define X86_PML4E_AVL_MASK (RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
774	%define X86_PML4E_PG_MASK 0x000ffffffffff000
775	%define X86_PML4E_MBZ_MASK_NX 0x0000000000000080
776	%define X86_PML4E_MBZ_MASK_NO_NX 0x8000000000000080
777	%define X86_PML4E_NX RT_BIT_64(63)
778	%ifndef VBOX_FOR_DTRACE_LIB
779	%endif
780	%ifndef VBOX_FOR_DTRACE_LIB
781	%endif
782	%ifndef VBOX_FOR_DTRACE_LIB
783	%endif
784	%define X86_PML4_SHIFT 39
785	%define X86_PML4_MASK 0x1ff
786	%ifndef VBOX_FOR_DTRACE_LIB
787	%endif
788	%ifndef VBOX_FOR_DTRACE_LIB
789	%endif
790	%ifndef VBOX_FOR_DTRACE_LIB
791	%endif
792	%ifndef VBOX_FOR_DTRACE_LIB
793	%endif
794	%ifndef VBOX_FOR_DTRACE_LIB
795	%endif
796	%define X86_OFF_FXSTATE_RSVD 0x1d0
797	%define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
798	%ifndef VBOX_FOR_DTRACE_LIB
799	%endif
800	%define X86_FSW_IE RT_BIT_32(0)
801	%define X86_FSW_DE RT_BIT_32(1)
802	%define X86_FSW_ZE RT_BIT_32(2)
803	%define X86_FSW_OE RT_BIT_32(3)
804	%define X86_FSW_UE RT_BIT_32(4)
805	%define X86_FSW_PE RT_BIT_32(5)
806	%define X86_FSW_SF RT_BIT_32(6)
807	%define X86_FSW_ES RT_BIT_32(7)
808	%define X86_FSW_XCPT_MASK 0x007f
809	%define X86_FSW_XCPT_ES_MASK 0x00ff
810	%define X86_FSW_C0 RT_BIT_32(8)
811	%define X86_FSW_C1 RT_BIT_32(9)
812	%define X86_FSW_C2 RT_BIT_32(10)
813	%define X86_FSW_TOP_MASK 0x3800
814	%define X86_FSW_TOP_SHIFT 11
815	%define X86_FSW_TOP_SMASK 0x0007
816	%define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
817	%define X86_FSW_C3 RT_BIT_32(14)
818	%define X86_FSW_C_MASK 0x4700
819	%define X86_FSW_B RT_BIT_32(15)
820	%define X86_FCW_IM RT_BIT_32(0)
821	%define X86_FCW_DM RT_BIT_32(1)
822	%define X86_FCW_ZM RT_BIT_32(2)
823	%define X86_FCW_OM RT_BIT_32(3)
824	%define X86_FCW_UM RT_BIT_32(4)
825	%define X86_FCW_PM RT_BIT_32(5)
826	%define X86_FCW_MASK_ALL 0x007f
827	%define X86_FCW_XCPT_MASK 0x003f
828	%define X86_FCW_PC_MASK 0x0300
829	%define X86_FCW_PC_24 0x0000
830	%define X86_FCW_PC_RSVD 0x0100
831	%define X86_FCW_PC_53 0x0200
832	%define X86_FCW_PC_64 0x0300
833	%define X86_FCW_RC_MASK 0x0c00
834	%define X86_FCW_RC_NEAREST 0x0000
835	%define X86_FCW_RC_DOWN 0x0400
836	%define X86_FCW_RC_UP 0x0800
837	%define X86_FCW_RC_ZERO 0x0c00
838	%define X86_FCW_ZERO_MASK 0xf080
839	%define X86_MXCSR_IE RT_BIT_32(0)
840	%define X86_MXCSR_DE RT_BIT_32(1)
841	%define X86_MXCSR_ZE RT_BIT_32(2)
842	%define X86_MXCSR_OE RT_BIT_32(3)
843	%define X86_MXCSR_UE RT_BIT_32(4)
844	%define X86_MXCSR_PE RT_BIT_32(5)
845	%define X86_MXCSR_DAZ RT_BIT_32(6)
846	%define X86_MXCSR_IM RT_BIT_32(7)
847	%define X86_MXCSR_DM RT_BIT_32(8)
848	%define X86_MXCSR_ZM RT_BIT_32(9)
849	%define X86_MXCSR_OM RT_BIT_32(10)
850	%define X86_MXCSR_UM RT_BIT_32(11)
851	%define X86_MXCSR_PM RT_BIT_32(12)
852	%define X86_MXCSR_RC_MASK 0x6000
853	%define X86_MXCSR_RC_NEAREST 0x0000
854	%define X86_MXCSR_RC_DOWN 0x2000
855	%define X86_MXCSR_RC_UP 0x4000
856	%define X86_MXCSR_RC_ZERO 0x6000
857	%define X86_MXCSR_FZ RT_BIT_32(15)
858	%define X86_MXCSR_MM RT_BIT_32(17)
859	%ifndef VBOX_FOR_DTRACE_LIB
860	%endif
861	%ifndef VBOX_FOR_DTRACE_LIB
862	%endif
863	%ifndef VBOX_FOR_DTRACE_LIB
864	%endif
865	%ifndef VBOX_FOR_DTRACE_LIB
866	%endif
867	%ifndef VBOX_FOR_DTRACE_LIB
868	%endif
869	%ifndef VBOX_FOR_DTRACE_LIB
870	%endif
871	%ifndef VBOX_FOR_DTRACE_LIB
872	%endif
873	%ifndef VBOX_FOR_DTRACE_LIB
874	%endif
875	%ifndef VBOX_FOR_DTRACE_LIB
876	%endif
877	%define XSAVE_C_X87_BIT 0
878	%define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
879	%define XSAVE_C_SSE_BIT 1
880	%define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
881	%define XSAVE_C_YMM_BIT 2
882	%define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
883	%define XSAVE_C_BNDREGS_BIT 3
884	%define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
885	%define XSAVE_C_BNDCSR_BIT 4
886	%define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
887	%define XSAVE_C_OPMASK_BIT 5
888	%define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
889	%define XSAVE_C_ZMM_HI256_BIT 6
890	%define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
891	%define XSAVE_C_ZMM_16HI_BIT 7
892	%define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
893	%define XSAVE_C_PKRU_BIT 9
894	%define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
895	%define XSAVE_C_LWP_BIT 62
896	%define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
897	%define XSAVE_C_X_BIT 63
898	%define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
899	%ifndef VBOX_FOR_DTRACE_LIB
900	%endif
901	%define X86DESCATTR_TYPE 0x0000000f
902	%define X86DESCATTR_DT 0x00000010
903	%define X86DESCATTR_DPL 0x00000060
904	%define X86DESCATTR_DPL_SHIFT 5
905	%define X86DESCATTR_P 0x00000080
906	%define X86DESCATTR_LIMIT_HIGH 0x00000f00
907	%define X86DESCATTR_AVL 0x00001000
908	%define X86DESCATTR_L 0x00002000
909	%define X86DESCATTR_D 0x00004000
910	%define X86DESCATTR_G 0x00008000
911	%define X86DESCATTR_UNUSABLE 0x00010000
912	%ifndef VBOX_FOR_DTRACE_LIB
913	%endif
914	%ifndef VBOX_FOR_DTRACE_LIB
915	%define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0)
916	%define X86DESCGENERIC_BIT_OFF_BASE_LOW (16)
917	%define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32)
918	%define X86DESCGENERIC_BIT_OFF_TYPE (40)
919	%define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44)
920	%define X86DESCGENERIC_BIT_OFF_DPL (45)
921	%define X86DESCGENERIC_BIT_OFF_PRESENT (47)
922	%define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48)
923	%define X86DESCGENERIC_BIT_OFF_AVAILABLE (52)
924	%define X86DESCGENERIC_BIT_OFF_LONG (53)
925	%define X86DESCGENERIC_BIT_OFF_DEF_BIG (54)
926	%define X86DESCGENERIC_BIT_OFF_GRANULARITY (55)
927	%define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56)
928	%define X86LAR_F_TYPE 0x0f00
929	%define X86LAR_F_DT 0x1000
930	%define X86LAR_F_DPL 0x6000
931	%define X86LAR_F_DPL_SHIFT 13
932	%define X86LAR_F_P 0x8000
933	%define X86LAR_F_AVL 0x00100000
934	%define X86LAR_F_L 0x00200000
935	%define X86LAR_F_D 0x00400000
936	%define X86LAR_F_G 0x00800000
937	%endif
938	%ifndef VBOX_FOR_DTRACE_LIB
939	%endif
940	%ifndef VBOX_FOR_DTRACE_LIB
941	%endif
942	%ifndef VBOX_FOR_DTRACE_LIB
943	%endif
944	%ifndef VBOX_FOR_DTRACE_LIB
945	%endif
946	%ifndef VBOX_FOR_DTRACE_LIB
947	%endif
948	%if HC_ARCH_BITS == 64
949	%else
950	%endif
951	%if HC_ARCH_BITS == 64
952	%else
953	%endif
954	%if HC_ARCH_BITS == 64
955	%else
956	%endif
957	%define X86_SEL_TYPE_CODE 8
958	%define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
959	%define X86_SEL_TYPE_ACCESSED 1
960	%define X86_SEL_TYPE_DOWN 4
961	%define X86_SEL_TYPE_CONF 4
962	%define X86_SEL_TYPE_WRITE 2
963	%define X86_SEL_TYPE_READ 2
964	%define X86_SEL_TYPE_READ_BIT 1
965	%define X86_SEL_TYPE_RO 0
966	%define X86_SEL_TYPE_RO_ACC (0 \| X86_SEL_TYPE_ACCESSED)
967	%define X86_SEL_TYPE_RW 2
968	%define X86_SEL_TYPE_RW_ACC (2 \| X86_SEL_TYPE_ACCESSED)
969	%define X86_SEL_TYPE_RO_DOWN 4
970	%define X86_SEL_TYPE_RO_DOWN_ACC (4 \| X86_SEL_TYPE_ACCESSED)
971	%define X86_SEL_TYPE_RW_DOWN 6
972	%define X86_SEL_TYPE_RW_DOWN_ACC (6 \| X86_SEL_TYPE_ACCESSED)
973	%define X86_SEL_TYPE_EO (0 \| X86_SEL_TYPE_CODE)
974	%define X86_SEL_TYPE_EO_ACC (0 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
975	%define X86_SEL_TYPE_ER (2 \| X86_SEL_TYPE_CODE)
976	%define X86_SEL_TYPE_ER_ACC (2 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
977	%define X86_SEL_TYPE_EO_CONF (4 \| X86_SEL_TYPE_CODE)
978	%define X86_SEL_TYPE_EO_CONF_ACC (4 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
979	%define X86_SEL_TYPE_ER_CONF (6 \| X86_SEL_TYPE_CODE)
980	%define X86_SEL_TYPE_ER_CONF_ACC (6 \| X86_SEL_TYPE_CODE \| X86_SEL_TYPE_ACCESSED)
981	%define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
982	%define X86_SEL_TYPE_SYS_UNDEFINED 0
983	%define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
984	%define X86_SEL_TYPE_SYS_LDT 2
985	%define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
986	%define X86_SEL_TYPE_SYS_286_CALL_GATE 4
987	%define X86_SEL_TYPE_SYS_TASK_GATE 5
988	%define X86_SEL_TYPE_SYS_286_INT_GATE 6
989	%define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
990	%define X86_SEL_TYPE_SYS_UNDEFINED2 8
991	%define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
992	%define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
993	%define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
994	%define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
995	%define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
996	%define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
997	%define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
998	%define AMD64_SEL_TYPE_SYS_LDT 2
999	%define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
1000	%define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
1001	%define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
1002	%define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
1003	%define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
1004	%define X86_DESC_TYPE_MASK (RT_BIT_32(8) \| RT_BIT_32(9) \| RT_BIT_32(10) \| RT_BIT_32(11))
1005	%define X86_DESC_S RT_BIT_32(12)
1006	%define X86_DESC_DPL (RT_BIT_32(13) \| RT_BIT_32(14))
1007	%define X86_DESC_P RT_BIT_32(15)
1008	%define X86_DESC_AVL RT_BIT_32(20)
1009	%define X86_DESC_DB RT_BIT_32(22)
1010	%define X86_DESC_G RT_BIT_32(23)
1011	%define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
1012	%define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
1013	%ifndef VBOX_FOR_DTRACE_LIB
1014	%endif
1015	%ifndef VBOX_FOR_DTRACE_LIB
1016	%endif
1017	%ifndef VBOX_FOR_DTRACE_LIB
1018	%endif
1019	%define X86_SEL_SHIFT 3
1020	%define X86_SEL_MASK 0xfff8
1021	%define X86_SEL_MASK_OFF_RPL 0xfffc
1022	%define X86_SEL_LDT 0x0004
1023	%define X86_SEL_RPL 0x0003
1024	%define X86_SEL_RPL_LDT 0x0007
1025	%define X86_XCPT_LAST 0x1f
1026	%define X86_TRAP_ERR_EXTERNAL 1
1027	%define X86_TRAP_ERR_IDT 2
1028	%define X86_TRAP_ERR_TI 4
1029	%define X86_TRAP_ERR_SEL_MASK 0xfff8
1030	%define X86_TRAP_ERR_SEL_SHIFT 3
1031	%define X86_TRAP_PF_P RT_BIT_32(0)
1032	%define X86_TRAP_PF_RW RT_BIT_32(1)
1033	%define X86_TRAP_PF_US RT_BIT_32(2)
1034	%define X86_TRAP_PF_RSVD RT_BIT_32(3)
1035	%define X86_TRAP_PF_ID RT_BIT_32(4)
1036	%define X86_TRAP_PF_PK RT_BIT_32(5)
1037	%ifndef VBOX_FOR_DTRACE_LIB
1038	%else
1039	%endif
1040	%ifndef VBOX_FOR_DTRACE_LIB
1041	%else
1042	%endif
1043	%define X86_MODRM_RM_MASK 0x07
1044	%define X86_MODRM_REG_MASK 0x38
1045	%define X86_MODRM_REG_SMASK 0x07
1046	%define X86_MODRM_REG_SHIFT 3
1047	%define X86_MODRM_MOD_MASK 0xc0
1048	%define X86_MODRM_MOD_SMASK 0x03
1049	%define X86_MODRM_MOD_SHIFT 6
1050	%ifndef VBOX_FOR_DTRACE_LIB
1051	%define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) \| ((a_Reg) << X86_MODRM_REG_SHIFT) \| (a_RegMem))
1052	%endif
1053	%define X86_SIB_BASE_MASK 0x07
1054	%define X86_SIB_INDEX_MASK 0x38
1055	%define X86_SIB_INDEX_SMASK 0x07
1056	%define X86_SIB_INDEX_SHIFT 3
1057	%define X86_SIB_SCALE_MASK 0xc0
1058	%define X86_SIB_SCALE_SMASK 0x03
1059	%define X86_SIB_SCALE_SHIFT 6
1060	%ifndef VBOX_FOR_DTRACE_LIB
1061	%endif
1062	%define X86_GREG_xAX 0
1063	%define X86_GREG_xCX 1
1064	%define X86_GREG_xDX 2
1065	%define X86_GREG_xBX 3
1066	%define X86_GREG_xSP 4
1067	%define X86_GREG_xBP 5
1068	%define X86_GREG_xSI 6
1069	%define X86_GREG_xDI 7
1070	%define X86_GREG_x8 8
1071	%define X86_GREG_x9 9
1072	%define X86_GREG_x10 10
1073	%define X86_GREG_x11 11
1074	%define X86_GREG_x12 12
1075	%define X86_GREG_x13 13
1076	%define X86_GREG_x14 14
1077	%define X86_GREG_x15 15
1078	%define X86_SREG_ES 0
1079	%define X86_SREG_CS 1
1080	%define X86_SREG_SS 2
1081	%define X86_SREG_DS 3
1082	%define X86_SREG_FS 4
1083	%define X86_SREG_GS 5
1084	%define X86_SREG_COUNT 6
1085	%define X86_OP_PRF_CS 0x2e
1086	%define X86_OP_PRF_SS 0x36
1087	%define X86_OP_PRF_DS 0x3e
1088	%define X86_OP_PRF_ES 0x26
1089	%define X86_OP_PRF_FS 0x64
1090	%define X86_OP_PRF_GS 0x65
1091	%define X86_OP_PRF_SIZE_OP 0x66
1092	%define X86_OP_PRF_SIZE_ADDR 0x67
1093	%define X86_OP_PRF_LOCK 0xf0
1094	%define X86_OP_PRF_REPZ 0xf3
1095	%define X86_OP_PRF_REPNZ 0xf2
1096	%define X86_OP_REX_B 0x41
1097	%define X86_OP_REX_X 0x42
1098	%define X86_OP_REX_R 0x44
1099	%define X86_OP_REX_W 0x48
1100	%endif
1101	%include "iprt/x86extra.mac"

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