VirtualBox

source: vbox/trunk/include/iprt/x86.mac@ 94564

Last change on this file since 94564 was 93115, checked in by vboxsync, 3 years ago

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1;; @file
2; IPRT - X86 and AMD64 Structures and Definitions.
3;
4; Automatically generated by various.sed. DO NOT EDIT!
5;
6
7;
8; Copyright (C) 2006-2022 Oracle Corporation
9;
10; This file is part of VirtualBox Open Source Edition (OSE), as
11; available from http://www.virtualbox.org. This file is free software;
12; you can redistribute it and/or modify it under the terms of the GNU
13; General Public License (GPL) as published by the Free Software
14; Foundation, in version 2 as it comes in the "COPYING" file of the
15; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17;
18; The contents of this file may alternatively be used under the terms
19; of the Common Development and Distribution License Version 1.0
20; (CDDL) only, as it comes in the "COPYING.CDDL" file of the
21; VirtualBox OSE distribution, in which case the provisions of the
22; CDDL are applicable instead of those of the GPL.
23;
24; You may elect to license modified versions of this file under the
25; terms and conditions of either the GPL or the CDDL or both.
26;
27
28%ifndef IPRT_INCLUDED_x86_h
29%define IPRT_INCLUDED_x86_h
30%ifndef RT_WITHOUT_PRAGMA_ONCE
31%endif
32%ifndef VBOX_FOR_DTRACE_LIB
33%else
34%endif
35%ifdef RT_OS_SOLARIS
36%endif
37%ifndef VBOX_FOR_DTRACE_LIB
38%endif
39%ifndef VBOX_FOR_DTRACE_LIB
40%endif
41%ifndef VBOX_FOR_DTRACE_LIB
42%endif
43%define X86_EFL_CF RT_BIT_32(0)
44%define X86_EFL_CF_BIT 0
45%define X86_EFL_1 RT_BIT_32(1)
46%define X86_EFL_PF RT_BIT_32(2)
47%define X86_EFL_AF RT_BIT_32(4)
48%define X86_EFL_AF_BIT 4
49%define X86_EFL_ZF RT_BIT_32(6)
50%define X86_EFL_ZF_BIT 6
51%define X86_EFL_SF RT_BIT_32(7)
52%define X86_EFL_SF_BIT 7
53%define X86_EFL_TF RT_BIT_32(8)
54%define X86_EFL_IF RT_BIT_32(9)
55%define X86_EFL_DF RT_BIT_32(10)
56%define X86_EFL_OF RT_BIT_32(11)
57%define X86_EFL_OF_BIT 11
58%define X86_EFL_IOPL (RT_BIT_32(12) | RT_BIT_32(13))
59%define X86_EFL_NT RT_BIT_32(14)
60%define X86_EFL_RF RT_BIT_32(16)
61%define X86_EFL_VM RT_BIT_32(17)
62%define X86_EFL_AC RT_BIT_32(18)
63%define X86_EFL_VIF RT_BIT_32(19)
64%define X86_EFL_VIP RT_BIT_32(20)
65%define X86_EFL_ID RT_BIT_32(21)
66%define X86_EFL_LIVE_MASK 0x003f7fd5
67%define X86_EFL_RA1_MASK RT_BIT_32(1)
68%define X86_EFL_IOPL_SHIFT 12
69%define X86_EFL_GET_IOPL(efl) (((efl) >> X86_EFL_IOPL_SHIFT) & 3)
70%define X86_EFL_POPF_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
71 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT | X86_EFL_AC | X86_EFL_ID )
72%define X86_EFL_POPF_BITS_386 ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_TF | X86_EFL_IF \
73 | X86_EFL_DF | X86_EFL_OF | X86_EFL_IOPL | X86_EFL_NT )
74%define X86_EFL_STATUS_BITS ( X86_EFL_CF | X86_EFL_PF | X86_EFL_AF | X86_EFL_ZF | X86_EFL_SF | X86_EFL_OF )
75%ifndef VBOX_FOR_DTRACE_LIB
76%else
77%endif
78%ifndef VBOX_FOR_DTRACE_LIB
79%else
80%endif
81%define X86_CPUID_VENDOR_INTEL_EBX 0x756e6547
82%define X86_CPUID_VENDOR_INTEL_ECX 0x6c65746e
83%define X86_CPUID_VENDOR_INTEL_EDX 0x49656e69
84%define X86_CPUID_VENDOR_AMD_EBX 0x68747541
85%define X86_CPUID_VENDOR_AMD_ECX 0x444d4163
86%define X86_CPUID_VENDOR_AMD_EDX 0x69746e65
87%define X86_CPUID_VENDOR_VIA_EBX 0x746e6543
88%define X86_CPUID_VENDOR_VIA_ECX 0x736c7561
89%define X86_CPUID_VENDOR_VIA_EDX 0x48727561
90%define X86_CPUID_VENDOR_SHANGHAI_EBX 0x68532020
91%define X86_CPUID_VENDOR_SHANGHAI_ECX 0x20206961
92%define X86_CPUID_VENDOR_SHANGHAI_EDX 0x68676e61
93%define X86_CPUID_VENDOR_HYGON_EBX 0x6f677948
94%define X86_CPUID_VENDOR_HYGON_ECX 0x656e6975
95%define X86_CPUID_VENDOR_HYGON_EDX 0x6e65476e
96%define X86_CPUID_FEATURE_ECX_SSE3 RT_BIT_32(0)
97%define X86_CPUID_FEATURE_ECX_PCLMUL RT_BIT_32(1)
98%define X86_CPUID_FEATURE_ECX_DTES64 RT_BIT_32(2)
99%define X86_CPUID_FEATURE_ECX_MONITOR RT_BIT_32(3)
100%define X86_CPUID_FEATURE_ECX_CPLDS RT_BIT_32(4)
101%define X86_CPUID_FEATURE_ECX_VMX RT_BIT_32(5)
102%define X86_CPUID_FEATURE_ECX_SMX RT_BIT_32(6)
103%define X86_CPUID_FEATURE_ECX_EST RT_BIT_32(7)
104%define X86_CPUID_FEATURE_ECX_TM2 RT_BIT_32(8)
105%define X86_CPUID_FEATURE_ECX_SSSE3 RT_BIT_32(9)
106%define X86_CPUID_FEATURE_ECX_CNTXID RT_BIT_32(10)
107%define X86_CPUID_FEATURE_ECX_SDBG RT_BIT_32(11)
108%define X86_CPUID_FEATURE_ECX_FMA RT_BIT_32(12)
109%define X86_CPUID_FEATURE_ECX_CX16 RT_BIT_32(13)
110%define X86_CPUID_FEATURE_ECX_TPRUPDATE RT_BIT_32(14)
111%define X86_CPUID_FEATURE_ECX_PDCM RT_BIT_32(15)
112%define X86_CPUID_FEATURE_ECX_PCID RT_BIT_32(17)
113%define X86_CPUID_FEATURE_ECX_DCA RT_BIT_32(18)
114%define X86_CPUID_FEATURE_ECX_SSE4_1 RT_BIT_32(19)
115%define X86_CPUID_FEATURE_ECX_SSE4_2 RT_BIT_32(20)
116%define X86_CPUID_FEATURE_ECX_X2APIC RT_BIT_32(21)
117%define X86_CPUID_FEATURE_ECX_MOVBE RT_BIT_32(22)
118%define X86_CPUID_FEATURE_ECX_POPCNT RT_BIT_32(23)
119%define X86_CPUID_FEATURE_ECX_TSCDEADL RT_BIT_32(24)
120%define X86_CPUID_FEATURE_ECX_AES RT_BIT_32(25)
121%define X86_CPUID_FEATURE_ECX_XSAVE RT_BIT_32(26)
122%define X86_CPUID_FEATURE_ECX_OSXSAVE RT_BIT_32(27)
123%define X86_CPUID_FEATURE_ECX_AVX RT_BIT_32(28)
124%define X86_CPUID_FEATURE_ECX_F16C RT_BIT_32(29)
125%define X86_CPUID_FEATURE_ECX_RDRAND RT_BIT_32(30)
126%define X86_CPUID_FEATURE_ECX_HVP RT_BIT_32(31)
127%define X86_CPUID_FEATURE_EDX_FPU RT_BIT_32(0)
128%define X86_CPUID_FEATURE_EDX_VME RT_BIT_32(1)
129%define X86_CPUID_FEATURE_EDX_DE RT_BIT_32(2)
130%define X86_CPUID_FEATURE_EDX_PSE RT_BIT_32(3)
131%define X86_CPUID_FEATURE_EDX_PSE_BIT 3
132%define X86_CPUID_FEATURE_EDX_TSC RT_BIT_32(4)
133%define X86_CPUID_FEATURE_EDX_MSR RT_BIT_32(5)
134%define X86_CPUID_FEATURE_EDX_PAE RT_BIT_32(6)
135%define X86_CPUID_FEATURE_EDX_PAE_BIT 6
136%define X86_CPUID_FEATURE_EDX_MCE RT_BIT_32(7)
137%define X86_CPUID_FEATURE_EDX_CX8 RT_BIT_32(8)
138%define X86_CPUID_FEATURE_EDX_APIC RT_BIT_32(9)
139%define X86_CPUID_FEATURE_EDX_SEP RT_BIT_32(11)
140%define X86_CPUID_FEATURE_EDX_MTRR RT_BIT_32(12)
141%define X86_CPUID_FEATURE_EDX_PGE RT_BIT_32(13)
142%define X86_CPUID_FEATURE_EDX_MCA RT_BIT_32(14)
143%define X86_CPUID_FEATURE_EDX_CMOV RT_BIT_32(15)
144%define X86_CPUID_FEATURE_EDX_PAT RT_BIT_32(16)
145%define X86_CPUID_FEATURE_EDX_PSE36 RT_BIT_32(17)
146%define X86_CPUID_FEATURE_EDX_PSN RT_BIT_32(18)
147%define X86_CPUID_FEATURE_EDX_CLFSH RT_BIT_32(19)
148%define X86_CPUID_FEATURE_EDX_DS RT_BIT_32(21)
149%define X86_CPUID_FEATURE_EDX_ACPI RT_BIT_32(22)
150%define X86_CPUID_FEATURE_EDX_MMX RT_BIT_32(23)
151%define X86_CPUID_FEATURE_EDX_FXSR RT_BIT_32(24)
152%define X86_CPUID_FEATURE_EDX_SSE RT_BIT_32(25)
153%define X86_CPUID_FEATURE_EDX_SSE2 RT_BIT_32(26)
154%define X86_CPUID_FEATURE_EDX_SS RT_BIT_32(27)
155%define X86_CPUID_FEATURE_EDX_HTT RT_BIT_32(28)
156%define X86_CPUID_FEATURE_EDX_TM RT_BIT_32(29)
157%define X86_CPUID_FEATURE_EDX_PBE RT_BIT_32(31)
158%define X86_CPUID_MWAIT_ECX_EXT RT_BIT_32(0)
159%define X86_CPUID_MWAIT_ECX_BREAKIRQIF0 RT_BIT_32(1)
160%define X86_CPUID_STEXT_FEATURE_EBX_FSGSBASE RT_BIT_32(0)
161%define X86_CPUID_STEXT_FEATURE_EBX_TSC_ADJUST RT_BIT_32(1)
162%define X86_CPUID_STEXT_FEATURE_EBX_SGX RT_BIT_32(2)
163%define X86_CPUID_STEXT_FEATURE_EBX_BMI1 RT_BIT_32(3)
164%define X86_CPUID_STEXT_FEATURE_EBX_HLE RT_BIT_32(4)
165%define X86_CPUID_STEXT_FEATURE_EBX_AVX2 RT_BIT_32(5)
166%define X86_CPUID_STEXT_FEATURE_EBX_FDP_EXCPTN_ONLY RT_BIT_32(6)
167%define X86_CPUID_STEXT_FEATURE_EBX_SMEP RT_BIT_32(7)
168%define X86_CPUID_STEXT_FEATURE_EBX_BMI2 RT_BIT_32(8)
169%define X86_CPUID_STEXT_FEATURE_EBX_ERMS RT_BIT_32(9)
170%define X86_CPUID_STEXT_FEATURE_EBX_INVPCID RT_BIT_32(10)
171%define X86_CPUID_STEXT_FEATURE_EBX_RTM RT_BIT_32(11)
172%define X86_CPUID_STEXT_FEATURE_EBX_PQM RT_BIT_32(12)
173%define X86_CPUID_STEXT_FEATURE_EBX_DEPR_FPU_CS_DS RT_BIT_32(13)
174%define X86_CPUID_STEXT_FEATURE_EBX_MPE RT_BIT_32(14)
175%define X86_CPUID_STEXT_FEATURE_EBX_PQE RT_BIT_32(15)
176%define X86_CPUID_STEXT_FEATURE_EBX_AVX512F RT_BIT_32(16)
177%define X86_CPUID_STEXT_FEATURE_EBX_RDSEED RT_BIT_32(18)
178%define X86_CPUID_STEXT_FEATURE_EBX_ADX RT_BIT_32(19)
179%define X86_CPUID_STEXT_FEATURE_EBX_SMAP RT_BIT_32(20)
180%define X86_CPUID_STEXT_FEATURE_EBX_CLFLUSHOPT RT_BIT_32(23)
181%define X86_CPUID_STEXT_FEATURE_EBX_INTEL_PT RT_BIT_32(25)
182%define X86_CPUID_STEXT_FEATURE_EBX_AVX512PF RT_BIT_32(26)
183%define X86_CPUID_STEXT_FEATURE_EBX_AVX512ER RT_BIT_32(27)
184%define X86_CPUID_STEXT_FEATURE_EBX_AVX512CD RT_BIT_32(28)
185%define X86_CPUID_STEXT_FEATURE_EBX_SHA RT_BIT_32(29)
186%define X86_CPUID_STEXT_FEATURE_ECX_PREFETCHWT1 RT_BIT_32(0)
187%define X86_CPUID_STEXT_FEATURE_ECX_UMIP RT_BIT_32(2)
188%define X86_CPUID_STEXT_FEATURE_ECX_PKU RT_BIT_32(3)
189%define X86_CPUID_STEXT_FEATURE_ECX_OSPKE RT_BIT_32(4)
190%define X86_CPUID_STEXT_FEATURE_ECX_MAWAU 0x003e0000
191%define X86_CPUID_STEXT_FEATURE_ECX_RDPID RT_BIT_32(2)
192%define X86_CPUID_STEXT_FEATURE_ECX_SGX_LC RT_BIT_32(30)
193%define X86_CPUID_STEXT_FEATURE_EDX_MD_CLEAR RT_BIT_32(10)
194%define X86_CPUID_STEXT_FEATURE_EDX_IBRS_IBPB RT_BIT_32(26)
195%define X86_CPUID_STEXT_FEATURE_EDX_STIBP RT_BIT_32(27)
196%define X86_CPUID_STEXT_FEATURE_EDX_FLUSH_CMD RT_BIT_32(28)
197%define X86_CPUID_STEXT_FEATURE_EDX_ARCHCAP RT_BIT_32(29)
198%define X86_CPUID_STEXT_FEATURE_EDX_SSBD RT_BIT_32(31)
199%define X86_CPUID_EXT_FEATURE_ECX_LAHF_SAHF RT_BIT_32(0)
200%define X86_CPUID_EXT_FEATURE_EDX_SYSCALL RT_BIT_32(11)
201%define X86_CPUID_EXT_FEATURE_EDX_NX RT_BIT_32(20)
202%define X86_CPUID_EXT_FEATURE_EDX_PAGE1GB RT_BIT_32(26)
203%define X86_CPUID_EXT_FEATURE_EDX_RDTSCP RT_BIT_32(27)
204%define X86_CPUID_EXT_FEATURE_EDX_LONG_MODE RT_BIT_32(29)
205%define X86_CPUID_AMD_FEATURE_EDX_FPU RT_BIT_32(0)
206%define X86_CPUID_AMD_FEATURE_EDX_VME RT_BIT_32(1)
207%define X86_CPUID_AMD_FEATURE_EDX_DE RT_BIT_32(2)
208%define X86_CPUID_AMD_FEATURE_EDX_PSE RT_BIT_32(3)
209%define X86_CPUID_AMD_FEATURE_EDX_TSC RT_BIT_32(4)
210%define X86_CPUID_AMD_FEATURE_EDX_MSR RT_BIT_32(5)
211%define X86_CPUID_AMD_FEATURE_EDX_PAE RT_BIT_32(6)
212%define X86_CPUID_AMD_FEATURE_EDX_MCE RT_BIT_32(7)
213%define X86_CPUID_AMD_FEATURE_EDX_CX8 RT_BIT_32(8)
214%define X86_CPUID_AMD_FEATURE_EDX_APIC RT_BIT_32(9)
215%define X86_CPUID_AMD_FEATURE_EDX_MTRR RT_BIT_32(12)
216%define X86_CPUID_AMD_FEATURE_EDX_PGE RT_BIT_32(13)
217%define X86_CPUID_AMD_FEATURE_EDX_MCA RT_BIT_32(14)
218%define X86_CPUID_AMD_FEATURE_EDX_CMOV RT_BIT_32(15)
219%define X86_CPUID_AMD_FEATURE_EDX_PAT RT_BIT_32(16)
220%define X86_CPUID_AMD_FEATURE_EDX_PSE36 RT_BIT_32(17)
221%define X86_CPUID_AMD_FEATURE_EDX_AXMMX RT_BIT_32(22)
222%define X86_CPUID_AMD_FEATURE_EDX_MMX RT_BIT_32(23)
223%define X86_CPUID_AMD_FEATURE_EDX_FXSR RT_BIT_32(24)
224%define X86_CPUID_AMD_FEATURE_EDX_FFXSR RT_BIT_32(25)
225%define X86_CPUID_AMD_FEATURE_EDX_3DNOW_EX RT_BIT_32(30)
226%define X86_CPUID_AMD_FEATURE_EDX_3DNOW RT_BIT_32(31)
227%define X86_CPUID_AMD_FEATURE_ECX_CMPL RT_BIT_32(1)
228%define X86_CPUID_AMD_FEATURE_ECX_SVM RT_BIT_32(2)
229%define X86_CPUID_AMD_FEATURE_ECX_EXT_APIC RT_BIT_32(3)
230%define X86_CPUID_AMD_FEATURE_ECX_CR8L RT_BIT_32(4)
231%define X86_CPUID_AMD_FEATURE_ECX_ABM RT_BIT_32(5)
232%define X86_CPUID_AMD_FEATURE_ECX_SSE4A RT_BIT_32(6)
233%define X86_CPUID_AMD_FEATURE_ECX_MISALNSSE RT_BIT_32(7)
234%define X86_CPUID_AMD_FEATURE_ECX_3DNOWPRF RT_BIT_32(8)
235%define X86_CPUID_AMD_FEATURE_ECX_OSVW RT_BIT_32(9)
236%define X86_CPUID_AMD_FEATURE_ECX_IBS RT_BIT_32(10)
237%define X86_CPUID_AMD_FEATURE_ECX_XOP RT_BIT_32(11)
238%define X86_CPUID_AMD_FEATURE_ECX_SKINIT RT_BIT_32(12)
239%define X86_CPUID_AMD_FEATURE_ECX_WDT RT_BIT_32(13)
240%define X86_CPUID_AMD_FEATURE_ECX_LWP RT_BIT_32(15)
241%define X86_CPUID_AMD_FEATURE_ECX_FMA4 RT_BIT_32(16)
242%define X86_CPUID_AMD_FEATURE_ECX_NODEID RT_BIT_32(19)
243%define X86_CPUID_AMD_FEATURE_ECX_TBM RT_BIT_32(21)
244%define X86_CPUID_AMD_FEATURE_ECX_TOPOEXT RT_BIT_32(22)
245%define X86_CPUID_AMD_ADVPOWER_EDX_TS RT_BIT_32(0)
246%define X86_CPUID_AMD_ADVPOWER_EDX_FID RT_BIT_32(1)
247%define X86_CPUID_AMD_ADVPOWER_EDX_VID RT_BIT_32(2)
248%define X86_CPUID_AMD_ADVPOWER_EDX_TTP RT_BIT_32(3)
249%define X86_CPUID_AMD_ADVPOWER_EDX_TM RT_BIT_32(4)
250%define X86_CPUID_AMD_ADVPOWER_EDX_STC RT_BIT_32(5)
251%define X86_CPUID_AMD_ADVPOWER_EDX_MC RT_BIT_32(6)
252%define X86_CPUID_AMD_ADVPOWER_EDX_HWPSTATE RT_BIT_32(7)
253%define X86_CPUID_AMD_ADVPOWER_EDX_TSCINVAR RT_BIT_32(8)
254%define X86_CPUID_AMD_ADVPOWER_EDX_CPB RT_BIT_32(9)
255%define X86_CPUID_AMD_ADVPOWER_EDX_EFRO RT_BIT_32(10)
256%define X86_CPUID_AMD_ADVPOWER_EDX_PFI RT_BIT_32(11)
257%define X86_CPUID_AMD_ADVPOWER_EDX_PA RT_BIT_32(12)
258%define X86_CPUID_AMD_EFEID_EBX_CLZERO RT_BIT_32(0)
259%define X86_CPUID_AMD_EFEID_EBX_IRPERF RT_BIT_32(1)
260%define X86_CPUID_AMD_EFEID_EBX_XSAVE_ER_PTR RT_BIT_32(2)
261%define X86_CPUID_AMD_EFEID_EBX_RDPRU RT_BIT_32(4)
262%define X86_CPUID_AMD_EFEID_EBX_MCOMMIT RT_BIT_32(8)
263%define X86_CPUID_AMD_EFEID_EBX_IBPB RT_BIT_32(12)
264%define X86_CPUID_AMD_EFEID_EBX_IBRS RT_BIT_32(14)
265%define X86_CPUID_AMD_EFEID_EBX_STIBP RT_BIT_32(15)
266%define X86_CPUID_AMD_EFEID_EBX_IBRS_ALWAYS_ON RT_BIT_32(16)
267%define X86_CPUID_AMD_EFEID_EBX_STIBP_ALWAYS_ON RT_BIT_32(17)
268%define X86_CPUID_AMD_EFEID_EBX_IBRS_PREFERRED RT_BIT_32(18)
269%define X86_CPUID_AMD_EFEID_EBX_SPEC_CTRL_SSBD RT_BIT_32(24)
270%define X86_CPUID_AMD_EFEID_EBX_VIRT_SPEC_CTRL_SSBD RT_BIT_32(25)
271%define X86_CPUID_AMD_EFEID_EBX_NO_SSBD_REQUIRED RT_BIT_32(26)
272%define X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING RT_BIT(0)
273%define X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT RT_BIT(1)
274%define X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK RT_BIT(2)
275%define X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE RT_BIT(3)
276%define X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR RT_BIT(4)
277%define X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN RT_BIT(5)
278%define X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID RT_BIT(6)
279%define X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS RT_BIT(7)
280%define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER RT_BIT(10)
281%define X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD RT_BIT(12)
282%define X86_CPUID_SVM_FEATURE_EDX_AVIC RT_BIT(13)
283%define X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD RT_BIT(15)
284%define X86_CPUID_SVM_FEATURE_EDX_VGIF RT_BIT(16)
285%define X86_CPUID_SVM_FEATURE_EDX_GMET RT_BIT(17)
286%define X86_CR0_PE RT_BIT_32(0)
287%define X86_CR0_PROTECTION_ENABLE RT_BIT_32(0)
288%define X86_CR0_MP RT_BIT_32(1)
289%define X86_CR0_MONITOR_COPROCESSOR RT_BIT_32(1)
290%define X86_CR0_EM RT_BIT_32(2)
291%define X86_CR0_EMULATE_FPU RT_BIT_32(2)
292%define X86_CR0_TS RT_BIT_32(3)
293%define X86_CR0_TASK_SWITCH RT_BIT_32(3)
294%define X86_CR0_ET RT_BIT_32(4)
295%define X86_CR0_EXTENSION_TYPE RT_BIT_32(4)
296%define X86_CR0_NE RT_BIT_32(5)
297%define X86_CR0_NUMERIC_ERROR RT_BIT_32(5)
298%define X86_CR0_WP RT_BIT_32(16)
299%define X86_CR0_WRITE_PROTECT RT_BIT_32(16)
300%define X86_CR0_AM RT_BIT_32(18)
301%define X86_CR0_ALIGMENT_MASK RT_BIT_32(18)
302%define X86_CR0_NW RT_BIT_32(29)
303%define X86_CR0_NOT_WRITE_THROUGH RT_BIT_32(29)
304%define X86_CR0_CD RT_BIT_32(30)
305%define X86_CR0_CACHE_DISABLE RT_BIT_32(30)
306%define X86_CR0_PG RT_BIT_32(31)
307%define X86_CR0_PAGING RT_BIT_32(31)
308%define X86_CR0_BIT_PG 31
309%define X86_CR3_PWT RT_BIT_32(3)
310%define X86_CR3_PCD RT_BIT_32(4)
311%define X86_CR3_PAGE_MASK (0xfffff000)
312%define X86_CR3_PAE_PAGE_MASK (0xffffffe0)
313%define X86_CR3_AMD64_PAGE_MASK 0x000ffffffffff000
314%define X86_CR4_VME RT_BIT_32(0)
315%define X86_CR4_PVI RT_BIT_32(1)
316%define X86_CR4_TSD RT_BIT_32(2)
317%define X86_CR4_DE RT_BIT_32(3)
318%define X86_CR4_PSE RT_BIT_32(4)
319%define X86_CR4_PAE RT_BIT_32(5)
320%define X86_CR4_MCE RT_BIT_32(6)
321%define X86_CR4_PGE RT_BIT_32(7)
322%define X86_CR4_PCE RT_BIT_32(8)
323%define X86_CR4_OSFXSR RT_BIT_32(9)
324%define X86_CR4_OSXMMEEXCPT RT_BIT_32(10)
325%define X86_CR4_UMIP RT_BIT_32(11)
326%define X86_CR4_VMXE RT_BIT_32(13)
327%define X86_CR4_SMXE RT_BIT_32(14)
328%define X86_CR4_FSGSBASE RT_BIT_32(16)
329%define X86_CR4_PCIDE RT_BIT_32(17)
330%define X86_CR4_OSXSAVE RT_BIT_32(18)
331%define X86_CR4_SMEP RT_BIT_32(20)
332%define X86_CR4_SMAP RT_BIT_32(21)
333%define X86_CR4_PKE RT_BIT_32(22)
334%define X86_CR4_CET RT_BIT_32(23)
335%define X86_DR6_B0 RT_BIT_32(0)
336%define X86_DR6_B1 RT_BIT_32(1)
337%define X86_DR6_B2 RT_BIT_32(2)
338%define X86_DR6_B3 RT_BIT_32(3)
339%define X86_DR6_B_MASK 0x0000000f
340%define X86_DR6_BD RT_BIT_32(13)
341%define X86_DR6_BS RT_BIT_32(14)
342%define X86_DR6_BT RT_BIT_32(15)
343%define X86_DR6_RTM RT_BIT_32(16)
344%define X86_DR6_INIT_VAL 0xffff0ff0
345%define X86_DR6_RA1_MASK 0xffff0ff0
346%define X86_DR6_RA1_MASK_RTM 0xfffe0ff0
347%define X86_DR6_RAZ_MASK RT_BIT_64(12)
348%define X86_DR6_MBZ_MASK 0xffffffff00000000
349%define X86_DR6_B(iBp) RT_BIT_64(iBp)
350%define X86_DR7_L0 RT_BIT_32(0)
351%define X86_DR7_G0 RT_BIT_32(1)
352%define X86_DR7_L1 RT_BIT_32(2)
353%define X86_DR7_G1 RT_BIT_32(3)
354%define X86_DR7_L2 RT_BIT_32(4)
355%define X86_DR7_G2 RT_BIT_32(5)
356%define X86_DR7_L3 RT_BIT_32(6)
357%define X86_DR7_G3 RT_BIT_32(7)
358%define X86_DR7_LE RT_BIT_32(8)
359%define X86_DR7_GE RT_BIT_32(9)
360%define X86_DR7_LE_ALL 0x0000000000000055
361%define X86_DR7_GE_ALL 0x00000000000000aa
362%define X86_DR7_RTM RT_BIT_32(11)
363%define X86_DR7_ICE_IR RT_BIT_32(12)
364%define X86_DR7_GD RT_BIT_32(13)
365%define X86_DR7_ICE_TR1 RT_BIT_32(14)
366%define X86_DR7_ICE_TR2 RT_BIT_32(15)
367%define X86_DR7_RW0_MASK (3 << 16)
368%define X86_DR7_LEN0_MASK (3 << 18)
369%define X86_DR7_RW1_MASK (3 << 20)
370%define X86_DR7_LEN1_MASK (3 << 22)
371%define X86_DR7_RW2_MASK (3 << 24)
372%define X86_DR7_LEN2_MASK (3 << 26)
373%define X86_DR7_RW3_MASK (3 << 28)
374%define X86_DR7_LEN3_MASK (3 << 30)
375%define X86_DR7_RA1_MASK RT_BIT_32(10)
376%define X86_DR7_RAZ_MASK 0x0000d800
377%define X86_DR7_MBZ_MASK 0xffffffff00000000
378%define X86_DR7_L(iBp) ( 1 << (iBp * 2) )
379%define X86_DR7_G(iBp) ( 1 << (iBp * 2 + 1) )
380%define X86_DR7_L_G(iBp) ( 3 << (iBp * 2) )
381%define X86_DR7_RW_EO 0
382%define X86_DR7_RW_WO 1
383%define X86_DR7_RW_IO 2
384%define X86_DR7_RW_RW 3
385%define X86_DR7_RW(iBp, fRw) ( (fRw) << ((iBp) * 4 + 16) )
386%define X86_DR7_GET_RW(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 16) ) & 3 )
387%define X86_DR7_RW_ALL_MASKS 0x33330000
388%ifndef VBOX_FOR_DTRACE_LIB
389 %define X86_DR7_ANY_RW_IO(uDR7) \
390 ( ( 0x22220000 & (uDR7) )
391%endif
392%define X86_DR7_LEN_BYTE 0
393%define X86_DR7_LEN_WORD 1
394%define X86_DR7_LEN_QWORD 2
395%define X86_DR7_LEN_DWORD 3
396%define X86_DR7_LEN(iBp, cb) ( (cb) << ((iBp) * 4 + 18) )
397%define X86_DR7_GET_LEN(uDR7, iBp) ( ( (uDR7) >> ((iBp) * 4 + 18) ) & 0x3 )
398%define X86_DR7_ENABLED_MASK 0x000000ff
399%define X86_DR7_LEN_ALL_MASKS 0xcccc0000
400%define X86_DR7_RW_LEN_ALL_MASKS 0xffff0000
401%define X86_DR7_INIT_VAL 0x400
402%define MSR_P5_MC_ADDR 0x00000000
403%define MSR_P5_MC_TYPE 0x00000001
404%define MSR_IA32_TSC 0x10
405%define MSR_IA32_CESR 0x00000011
406%define MSR_IA32_CTR0 0x00000012
407%define MSR_IA32_CTR1 0x00000013
408%define MSR_IA32_PLATFORM_ID 0x17
409%ifndef MSR_IA32_APICBASE
410 %define MSR_IA32_APICBASE 0x1b
411 %define MSR_IA32_APICBASE_EN RT_BIT_64(11)
412 %define MSR_IA32_APICBASE_EXTD RT_BIT_64(10)
413 %define MSR_IA32_APICBASE_BSP RT_BIT_64(8)
414 %define MSR_IA32_APICBASE_BASE_MIN 0x0000000ffffff000
415 %define MSR_IA32_APICBASE_ADDR 0x00000000fee00000
416 %define MSR_IA32_APICBASE_GET_ADDR(a_Msr) ((a_Msr) & X86_PAGE_4K_BASE_MASK)
417%endif
418%define MSR_CORE_THREAD_COUNT 0x35
419%define MSR_IA32_FEATURE_CONTROL 0x3A
420%define MSR_IA32_FEATURE_CONTROL_LOCK RT_BIT_64(0)
421%define MSR_IA32_FEATURE_CONTROL_SMX_VMXON RT_BIT_64(1)
422%define MSR_IA32_FEATURE_CONTROL_VMXON RT_BIT_64(2)
423%define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0 RT_BIT_64(8)
424%define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1 RT_BIT_64(9)
425%define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2 RT_BIT_64(10)
426%define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3 RT_BIT_64(11)
427%define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4 RT_BIT_64(12)
428%define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5 RT_BIT_64(13)
429%define MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6 RT_BIT_64(14)
430%define MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN RT_BIT_64(15)
431%define MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN RT_BIT_64(17)
432%define MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN RT_BIT_64(18)
433%define MSR_IA32_FEATURE_CONTROL_LMCE RT_BIT_64(20)
434%define MSR_IA32_TSC_ADJUST 0x3B
435%define MSR_IA32_SPEC_CTRL 0x48
436%define MSR_IA32_SPEC_CTRL_F_IBRS RT_BIT_32(0)
437%define MSR_IA32_SPEC_CTRL_F_STIBP RT_BIT_32(1)
438%define MSR_IA32_SPEC_CTRL_F_SSBD RT_BIT_32(2)
439%define MSR_IA32_PRED_CMD 0x49
440%define MSR_IA32_PRED_CMD_F_IBPB RT_BIT_32(0)
441%define MSR_IA32_BIOS_UPDT_TRIG 0x79
442%define MSR_IA32_BIOS_SIGN_ID 0x8B
443%define MSR_IA32_SMM_MONITOR_CTL 0x9B
444%define MSR_IA32_SMM_MONITOR_VALID RT_BIT_64(0)
445%define MSR_IA32_SMM_MONITOR_VMXOFF_UNBLOCK_SMI RT_BIT_64(2)
446%define MSR_IA32_SMM_MONITOR_MSGEG_PHYSADDR(a) (((a) >> 12) & 0xfffff)
447%define MSR_IA32_SMBASE 0x9E
448%define MSR_IA32_PMC0 0xC1
449%define MSR_IA32_PMC1 0xC2
450%define MSR_IA32_PMC2 0xC3
451%define MSR_IA32_PMC3 0xC4
452%define MSR_IA32_PMC4 0xC5
453%define MSR_IA32_PMC5 0xC6
454%define MSR_IA32_PMC6 0xC7
455%define MSR_IA32_PMC7 0xC8
456%define MSR_IA32_PLATFORM_INFO 0xCE
457%define MSR_IA32_FSB_CLOCK_STS 0xCD
458%define MSR_PKG_CST_CONFIG_CONTROL 0x000000e2
459%define MSR_IA32_MPERF 0xE7
460%define MSR_IA32_APERF 0xE8
461%define MSR_IA32_MTRR_CAP 0xFE
462%define MSR_IA32_ARCH_CAPABILITIES 0x10a
463%define MSR_IA32_ARCH_CAP_F_RDCL_NO RT_BIT_32(0)
464%define MSR_IA32_ARCH_CAP_F_IBRS_ALL RT_BIT_32(1)
465%define MSR_IA32_ARCH_CAP_F_RSBO RT_BIT_32(2)
466%define MSR_IA32_ARCH_CAP_F_VMM_NEED_NOT_FLUSH_L1D RT_BIT_32(3)
467%define MSR_IA32_ARCH_CAP_F_MDS_NO RT_BIT_32(4)
468%define MSR_IA32_FLUSH_CMD 0x10b
469%define MSR_IA32_FLUSH_CMD_F_L1D RT_BIT_32(0)
470%define MSR_BBL_CR_CTL3 0x11e
471%ifndef MSR_IA32_SYSENTER_CS
472%define MSR_IA32_SYSENTER_CS 0x174
473%define MSR_IA32_SYSENTER_ESP 0x175
474%define MSR_IA32_SYSENTER_EIP 0x176
475%endif
476%define MSR_IA32_MCG_CAP 0x179
477%define MSR_IA32_MCG_STATUS 0x17A
478%define MSR_IA32_MCG_CTRL 0x17B
479%define MSR_IA32_CR_PAT 0x277
480%define MSR_IA32_CR_PAT_INIT_VAL 0x0007040600070406
481%define MSR_IA32_PERFEVTSEL0 0x186
482%define MSR_IA32_PERFEVTSEL1 0x187
483%define MSR_IA32_PERFEVTSEL2 0x188
484%define MSR_IA32_PERFEVTSEL3 0x189
485%define MSR_FLEX_RATIO 0x194
486%define MSR_IA32_PERF_STATUS 0x198
487%define MSR_IA32_PERF_CTL 0x199
488%define MSR_IA32_THERM_STATUS 0x19c
489%define MSR_OFFCORE_RSP_0 0x1a6
490%define MSR_OFFCORE_RSP_1 0x1a7
491%define MSR_IA32_MISC_ENABLE 0x1A0
492%define MSR_IA32_MISC_ENABLE_FAST_STRINGS RT_BIT_64(0)
493%define MSR_IA32_MISC_ENABLE_TCC RT_BIT_64(3)
494%define MSR_IA32_MISC_ENABLE_PERF_MON RT_BIT_64(7)
495%define MSR_IA32_MISC_ENABLE_BTS_UNAVAIL RT_BIT_64(11)
496%define MSR_IA32_MISC_ENABLE_PEBS_UNAVAIL RT_BIT_64(12)
497%define MSR_IA32_MISC_ENABLE_SST_ENABLE RT_BIT_64(16)
498%define MSR_IA32_MISC_ENABLE_MONITOR RT_BIT_64(18)
499%define MSR_IA32_MISC_ENABLE_LIMIT_CPUID RT_BIT_64(22)
500%define MSR_IA32_MISC_ENABLE_XTPR_MSG_DISABLE RT_BIT_64(23)
501%define MSR_IA32_MISC_ENABLE_XD_DISABLE RT_BIT_64(34)
502%define MSR_IA32_DEBUGCTL 0x000001d9
503%define MSR_IA32_DEBUGCTL_LBR RT_BIT_64(0)
504%define MSR_IA32_DEBUGCTL_BTF RT_BIT_64(1)
505%define MSR_IA32_DEBUGCTL_PB0 RT_BIT_64(2)
506%define MSR_IA32_DEBUGCTL_PB1 RT_BIT_64(3)
507%define MSR_IA32_DEBUGCTL_PB2 RT_BIT_64(4)
508%define MSR_IA32_DEBUGCTL_PB3 RT_BIT_64(5)
509%define MSR_IA32_DEBUGCTL_TR RT_BIT_64(6)
510%define MSR_IA32_DEBUGCTL_BTS RT_BIT_64(7)
511%define MSR_IA32_DEBUGCTL_BTINT RT_BIT_64(8)
512%define MSR_IA32_DEBUGCTL_BTS_OFF_OS RT_BIT_64(9)
513%define MSR_IA32_DEBUGCTL_BTS_OFF_USER RT_BIT_64(10)
514%define MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI RT_BIT_64(11)
515%define MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI RT_BIT_64(12)
516%define MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM RT_BIT_64(14)
517%define MSR_IA32_DEBUGCTL_RTM RT_BIT_64(15)
518%define MSR_IA32_DEBUGCTL_VALID_MASK_INTEL ( MSR_IA32_DEBUGCTL_LBR | MSR_IA32_DEBUGCTL_BTF | MSR_IA32_DEBUGCTL_TR \
519 | MSR_IA32_DEBUGCTL_BTS | MSR_IA32_DEBUGCTL_BTINT | MSR_IA32_DEBUGCTL_BTS_OFF_OS \
520 | MSR_IA32_DEBUGCTL_BTS_OFF_USER | MSR_IA32_DEBUGCTL_FREEZE_LBR_ON_PMI \
521 | MSR_IA32_DEBUGCTL_FREEZE_PERFMON_ON_PMI | MSR_IA32_DEBUGCTL_FREEZE_WHILE_SMM_EM \
522 | MSR_IA32_DEBUGCTL_RTM)
523%define MSR_P4_LASTBRANCH_0 0x1db
524%define MSR_P4_LASTBRANCH_1 0x1dc
525%define MSR_P4_LASTBRANCH_2 0x1dd
526%define MSR_P4_LASTBRANCH_3 0x1de
527%define MSR_P4_LASTBRANCH_TOS 0x1da
528%define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x40
529%define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x41
530%define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x42
531%define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x43
532%define MSR_CORE2_LASTBRANCH_0_TO_IP 0x60
533%define MSR_CORE2_LASTBRANCH_1_TO_IP 0x61
534%define MSR_CORE2_LASTBRANCH_2_TO_IP 0x62
535%define MSR_CORE2_LASTBRANCH_3_TO_IP 0x63
536%define MSR_CORE2_LASTBRANCH_TOS 0x1c9
537%define MSR_LASTBRANCH_0_FROM_IP 0x680
538%define MSR_LASTBRANCH_1_FROM_IP 0x681
539%define MSR_LASTBRANCH_2_FROM_IP 0x682
540%define MSR_LASTBRANCH_3_FROM_IP 0x683
541%define MSR_LASTBRANCH_4_FROM_IP 0x684
542%define MSR_LASTBRANCH_5_FROM_IP 0x685
543%define MSR_LASTBRANCH_6_FROM_IP 0x686
544%define MSR_LASTBRANCH_7_FROM_IP 0x687
545%define MSR_LASTBRANCH_8_FROM_IP 0x688
546%define MSR_LASTBRANCH_9_FROM_IP 0x689
547%define MSR_LASTBRANCH_10_FROM_IP 0x68a
548%define MSR_LASTBRANCH_11_FROM_IP 0x68b
549%define MSR_LASTBRANCH_12_FROM_IP 0x68c
550%define MSR_LASTBRANCH_13_FROM_IP 0x68d
551%define MSR_LASTBRANCH_14_FROM_IP 0x68e
552%define MSR_LASTBRANCH_15_FROM_IP 0x68f
553%define MSR_LASTBRANCH_16_FROM_IP 0x690
554%define MSR_LASTBRANCH_17_FROM_IP 0x691
555%define MSR_LASTBRANCH_18_FROM_IP 0x692
556%define MSR_LASTBRANCH_19_FROM_IP 0x693
557%define MSR_LASTBRANCH_20_FROM_IP 0x694
558%define MSR_LASTBRANCH_21_FROM_IP 0x695
559%define MSR_LASTBRANCH_22_FROM_IP 0x696
560%define MSR_LASTBRANCH_23_FROM_IP 0x697
561%define MSR_LASTBRANCH_24_FROM_IP 0x698
562%define MSR_LASTBRANCH_25_FROM_IP 0x699
563%define MSR_LASTBRANCH_26_FROM_IP 0x69a
564%define MSR_LASTBRANCH_27_FROM_IP 0x69b
565%define MSR_LASTBRANCH_28_FROM_IP 0x69c
566%define MSR_LASTBRANCH_29_FROM_IP 0x69d
567%define MSR_LASTBRANCH_30_FROM_IP 0x69e
568%define MSR_LASTBRANCH_31_FROM_IP 0x69f
569%define MSR_LASTBRANCH_0_TO_IP 0x6c0
570%define MSR_LASTBRANCH_1_TO_IP 0x6c1
571%define MSR_LASTBRANCH_2_TO_IP 0x6c2
572%define MSR_LASTBRANCH_3_TO_IP 0x6c3
573%define MSR_LASTBRANCH_4_TO_IP 0x6c4
574%define MSR_LASTBRANCH_5_TO_IP 0x6c5
575%define MSR_LASTBRANCH_6_TO_IP 0x6c6
576%define MSR_LASTBRANCH_7_TO_IP 0x6c7
577%define MSR_LASTBRANCH_8_TO_IP 0x6c8
578%define MSR_LASTBRANCH_9_TO_IP 0x6c9
579%define MSR_LASTBRANCH_10_TO_IP 0x6ca
580%define MSR_LASTBRANCH_11_TO_IP 0x6cb
581%define MSR_LASTBRANCH_12_TO_IP 0x6cc
582%define MSR_LASTBRANCH_13_TO_IP 0x6cd
583%define MSR_LASTBRANCH_14_TO_IP 0x6ce
584%define MSR_LASTBRANCH_15_TO_IP 0x6cf
585%define MSR_LASTBRANCH_16_TO_IP 0x6d0
586%define MSR_LASTBRANCH_17_TO_IP 0x6d1
587%define MSR_LASTBRANCH_18_TO_IP 0x6d2
588%define MSR_LASTBRANCH_19_TO_IP 0x6d3
589%define MSR_LASTBRANCH_20_TO_IP 0x6d4
590%define MSR_LASTBRANCH_21_TO_IP 0x6d5
591%define MSR_LASTBRANCH_22_TO_IP 0x6d6
592%define MSR_LASTBRANCH_23_TO_IP 0x6d7
593%define MSR_LASTBRANCH_24_TO_IP 0x6d8
594%define MSR_LASTBRANCH_25_TO_IP 0x6d9
595%define MSR_LASTBRANCH_26_TO_IP 0x6da
596%define MSR_LASTBRANCH_27_TO_IP 0x6db
597%define MSR_LASTBRANCH_28_TO_IP 0x6dc
598%define MSR_LASTBRANCH_29_TO_IP 0x6dd
599%define MSR_LASTBRANCH_30_TO_IP 0x6de
600%define MSR_LASTBRANCH_31_TO_IP 0x6df
601%define MSR_LASTBRANCH_TOS 0x1c9
602%define MSR_IA32_TSX_CTRL 0x122
603%define MSR_IA32_MTRR_PHYSBASE0 0x200
604%define MSR_IA32_MTRR_PHYSMASK0 0x201
605%define MSR_IA32_MTRR_PHYSBASE1 0x202
606%define MSR_IA32_MTRR_PHYSMASK1 0x203
607%define MSR_IA32_MTRR_PHYSBASE2 0x204
608%define MSR_IA32_MTRR_PHYSMASK2 0x205
609%define MSR_IA32_MTRR_PHYSBASE3 0x206
610%define MSR_IA32_MTRR_PHYSMASK3 0x207
611%define MSR_IA32_MTRR_PHYSBASE4 0x208
612%define MSR_IA32_MTRR_PHYSMASK4 0x209
613%define MSR_IA32_MTRR_PHYSBASE5 0x20a
614%define MSR_IA32_MTRR_PHYSMASK5 0x20b
615%define MSR_IA32_MTRR_PHYSBASE6 0x20c
616%define MSR_IA32_MTRR_PHYSMASK6 0x20d
617%define MSR_IA32_MTRR_PHYSBASE7 0x20e
618%define MSR_IA32_MTRR_PHYSMASK7 0x20f
619%define MSR_IA32_MTRR_PHYSBASE8 0x210
620%define MSR_IA32_MTRR_PHYSMASK8 0x211
621%define MSR_IA32_MTRR_PHYSBASE9 0x212
622%define MSR_IA32_MTRR_PHYSMASK9 0x213
623%define MSR_IA32_MTRR_FIX64K_00000 0x250
624%define MSR_IA32_MTRR_FIX16K_80000 0x258
625%define MSR_IA32_MTRR_FIX16K_A0000 0x259
626%define MSR_IA32_MTRR_FIX4K_C0000 0x268
627%define MSR_IA32_MTRR_FIX4K_C8000 0x269
628%define MSR_IA32_MTRR_FIX4K_D0000 0x26a
629%define MSR_IA32_MTRR_FIX4K_D8000 0x26b
630%define MSR_IA32_MTRR_FIX4K_E0000 0x26c
631%define MSR_IA32_MTRR_FIX4K_E8000 0x26d
632%define MSR_IA32_MTRR_FIX4K_F0000 0x26e
633%define MSR_IA32_MTRR_FIX4K_F8000 0x26f
634%define MSR_IA32_MTRR_DEF_TYPE 0x2FF
635%define MSR_IA32_PERF_GLOBAL_STATUS 0x38E
636%define MSR_IA32_PERF_GLOBAL_CTRL 0x38F
637%define MSR_IA32_PERF_GLOBAL_OVF_CTRL 0x390
638%define MSR_IA32_PEBS_ENABLE 0x3F1
639%define MSR_IA32_MC0_CTL 0x400
640%define MSR_IA32_MC0_STATUS 0x401
641%define MSR_IA32_VMX_BASIC 0x480
642%define MSR_IA32_VMX_PINBASED_CTLS 0x481
643%define MSR_IA32_VMX_PROCBASED_CTLS 0x482
644%define MSR_IA32_VMX_EXIT_CTLS 0x483
645%define MSR_IA32_VMX_ENTRY_CTLS 0x484
646%define MSR_IA32_VMX_MISC 0x485
647%define MSR_IA32_VMX_CR0_FIXED0 0x486
648%define MSR_IA32_VMX_CR0_FIXED1 0x487
649%define MSR_IA32_VMX_CR4_FIXED0 0x488
650%define MSR_IA32_VMX_CR4_FIXED1 0x489
651%define MSR_IA32_VMX_VMCS_ENUM 0x48A
652%define MSR_IA32_VMX_PROCBASED_CTLS2 0x48B
653%define MSR_IA32_VMX_EPT_VPID_CAP 0x48C
654%define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x48D
655%define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x48E
656%define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x48F
657%define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x490
658%define MSR_IA32_VMX_VMFUNC 0x491
659%define MSR_IA32_RTIT_CTL 0x570
660%define MSR_IA32_DS_AREA 0x600
661%define MSR_RAPL_POWER_UNIT 0x606
662%define MSR_PKGC3_IRTL 0x60a
663%define MSR_PKGC_IRTL1 0x60b
664%define MSR_PKGC_IRTL2 0x60c
665%define MSR_PKG_C2_RESIDENCY 0x60d
666%define MSR_PKG_POWER_LIMIT 0x610
667%define MSR_PKG_ENERGY_STATUS 0x611
668%define MSR_PKG_PERF_STATUS 0x613
669%define MSR_PKG_POWER_INFO 0x614
670%define MSR_DRAM_POWER_LIMIT 0x618
671%define MSR_DRAM_ENERGY_STATUS 0x619
672%define MSR_DRAM_PERF_STATUS 0x61b
673%define MSR_DRAM_POWER_INFO 0x61c
674%define MSR_PKG_C10_RESIDENCY 0x632
675%define MSR_PP0_ENERGY_STATUS 0x639
676%define MSR_PP1_ENERGY_STATUS 0x641
677%define MSR_TURBO_ACTIVATION_RATIO 0x64c
678%define MSR_CORE_PERF_LIMIT_REASONS 0x64f
679%define MSR_IA32_X2APIC_START 0x800
680%define MSR_IA32_X2APIC_ID 0x802
681%define MSR_IA32_X2APIC_VERSION 0x803
682%define MSR_IA32_X2APIC_TPR 0x808
683%define MSR_IA32_X2APIC_PPR 0x80A
684%define MSR_IA32_X2APIC_EOI 0x80B
685%define MSR_IA32_X2APIC_LDR 0x80D
686%define MSR_IA32_X2APIC_SVR 0x80F
687%define MSR_IA32_X2APIC_ISR0 0x810
688%define MSR_IA32_X2APIC_ISR1 0x811
689%define MSR_IA32_X2APIC_ISR2 0x812
690%define MSR_IA32_X2APIC_ISR3 0x813
691%define MSR_IA32_X2APIC_ISR4 0x814
692%define MSR_IA32_X2APIC_ISR5 0x815
693%define MSR_IA32_X2APIC_ISR6 0x816
694%define MSR_IA32_X2APIC_ISR7 0x817
695%define MSR_IA32_X2APIC_TMR0 0x818
696%define MSR_IA32_X2APIC_TMR1 0x819
697%define MSR_IA32_X2APIC_TMR2 0x81A
698%define MSR_IA32_X2APIC_TMR3 0x81B
699%define MSR_IA32_X2APIC_TMR4 0x81C
700%define MSR_IA32_X2APIC_TMR5 0x81D
701%define MSR_IA32_X2APIC_TMR6 0x81E
702%define MSR_IA32_X2APIC_TMR7 0x81F
703%define MSR_IA32_X2APIC_IRR0 0x820
704%define MSR_IA32_X2APIC_IRR1 0x821
705%define MSR_IA32_X2APIC_IRR2 0x822
706%define MSR_IA32_X2APIC_IRR3 0x823
707%define MSR_IA32_X2APIC_IRR4 0x824
708%define MSR_IA32_X2APIC_IRR5 0x825
709%define MSR_IA32_X2APIC_IRR6 0x826
710%define MSR_IA32_X2APIC_IRR7 0x827
711%define MSR_IA32_X2APIC_ESR 0x828
712%define MSR_IA32_X2APIC_LVT_CMCI 0x82F
713%define MSR_IA32_X2APIC_ICR 0x830
714%define MSR_IA32_X2APIC_LVT_TIMER 0x832
715%define MSR_IA32_X2APIC_LVT_THERMAL 0x833
716%define MSR_IA32_X2APIC_LVT_PERF 0x834
717%define MSR_IA32_X2APIC_LVT_LINT0 0x835
718%define MSR_IA32_X2APIC_LVT_LINT1 0x836
719%define MSR_IA32_X2APIC_LVT_ERROR 0x837
720%define MSR_IA32_X2APIC_TIMER_ICR 0x838
721%define MSR_IA32_X2APIC_TIMER_CCR 0x839
722%define MSR_IA32_X2APIC_TIMER_DCR 0x83E
723%define MSR_IA32_X2APIC_SELF_IPI 0x83F
724%define MSR_IA32_X2APIC_END 0x8FF
725%define MSR_IA32_X2APIC_LVT_START MSR_IA32_X2APIC_LVT_TIMER
726%define MSR_IA32_X2APIC_LVT_END MSR_IA32_X2APIC_LVT_ERROR
727%define MSR_K6_EFER 0xc0000080
728%define MSR_K6_EFER_SCE RT_BIT_32(0)
729%define MSR_K6_EFER_LME RT_BIT_32(8)
730%define MSR_K6_EFER_BIT_LME 8
731%define MSR_K6_EFER_LMA RT_BIT_32(10)
732%define MSR_K6_EFER_BIT_LMA 10
733%define MSR_K6_EFER_NXE RT_BIT_32(11)
734%define MSR_K6_EFER_BIT_NXE 11
735%define MSR_K6_EFER_SVME RT_BIT_32(12)
736%define MSR_K6_EFER_LMSLE RT_BIT_32(13)
737%define MSR_K6_EFER_FFXSR RT_BIT_32(14)
738%define MSR_K6_EFER_TCE RT_BIT_32(15)
739%define MSR_K6_EFER_MCOMMIT RT_BIT_32(17)
740%define MSR_K6_STAR 0xc0000081
741%define MSR_K6_STAR_SYSRET_CS_SS_SHIFT 48
742%define MSR_K6_STAR_SYSCALL_CS_SS_SHIFT 32
743%define MSR_K6_STAR_SEL_MASK 0xffff
744%define MSR_K6_STAR_SYSCALL_EIP_MASK 0xffffffff
745%define MSR_K6_WHCR 0xc0000082
746%define MSR_K6_UWCCR 0xc0000085
747%define MSR_K6_PSOR 0xc0000087
748%define MSR_K6_PFIR 0xc0000088
749%define MSR_K7_EVNTSEL0 0xc0010000
750%define MSR_K7_EVNTSEL1 0xc0010001
751%define MSR_K7_EVNTSEL2 0xc0010002
752%define MSR_K7_EVNTSEL3 0xc0010003
753%define MSR_K7_PERFCTR0 0xc0010004
754%define MSR_K7_PERFCTR1 0xc0010005
755%define MSR_K7_PERFCTR2 0xc0010006
756%define MSR_K7_PERFCTR3 0xc0010007
757%define MSR_K8_LSTAR 0xc0000082
758%define MSR_K8_CSTAR 0xc0000083
759%define MSR_K8_SF_MASK 0xc0000084
760%define MSR_K8_FS_BASE 0xc0000100
761%define MSR_K8_GS_BASE 0xc0000101
762%define MSR_K8_KERNEL_GS_BASE 0xc0000102
763%define MSR_K8_TSC_AUX 0xc0000103
764%define MSR_K8_SYSCFG 0xc0010010
765%define MSR_K8_HWCR 0xc0010015
766%define MSR_K8_IORRBASE0 0xc0010016
767%define MSR_K8_IORRMASK0 0xc0010017
768%define MSR_K8_IORRBASE1 0xc0010018
769%define MSR_K8_IORRMASK1 0xc0010019
770%define MSR_K8_TOP_MEM1 0xc001001a
771%define MSR_K8_TOP_MEM2 0xc001001d
772%define MSR_K7_SMBASE 0xc0010111
773%define MSR_K7_SMM_ADDR 0xc0010112
774%define MSR_K7_SMM_MASK 0xc0010113
775%define MSR_K8_NB_CFG 0xc001001f
776%define MSR_K8_INT_PENDING 0xc0010055
777%define MSR_K8_VM_CR 0xc0010114
778%define MSR_K8_VM_CR_DPD RT_BIT_32(0)
779%define MSR_K8_VM_CR_R_INIT RT_BIT_32(1)
780%define MSR_K8_VM_CR_DIS_A20M RT_BIT_32(2)
781%define MSR_K8_VM_CR_LOCK RT_BIT_32(3)
782%define MSR_K8_VM_CR_SVM_DISABLE RT_BIT_32(4)
783%define MSR_K8_IGNNE 0xc0010115
784%define MSR_K8_SMM_CTL 0xc0010116
785%define MSR_K8_VM_HSAVE_PA 0xc0010117
786%define MSR_AMD_VIRT_SPEC_CTL 0xc001011f
787 %define MSR_AMD_VIRT_SPEC_CTL_F_SSBD RT_BIT(2)
788%define X86_PG_ENTRIES 1024
789%define X86_PG_PAE_ENTRIES 512
790%define X86_PG_PAE_PDPE_ENTRIES 4
791%define X86_PG_AMD64_ENTRIES X86_PG_PAE_ENTRIES
792%define X86_PG_AMD64_PDPE_ENTRIES X86_PG_AMD64_ENTRIES
793%define X86_PAGE_SIZE X86_PAGE_4K_SIZE
794%define X86_PAGE_SHIFT X86_PAGE_4K_SHIFT
795%define X86_PAGE_OFFSET_MASK X86_PAGE_4K_OFFSET_MASK
796%define X86_PAGE_BASE_MASK X86_PAGE_4K_BASE_MASK
797%define X86_PAGE_BASE_MASK_32 X86_PAGE_4K_BASE_MASK_32
798%define X86_PAGE_4K_SIZE _4K
799%define X86_PAGE_4K_SHIFT 12
800%define X86_PAGE_4K_OFFSET_MASK 0xfff
801%define X86_PAGE_4K_BASE_MASK 0xfffffffffffff000
802%define X86_PAGE_4K_BASE_MASK_32 0xfffff000
803%define X86_PAGE_2M_SIZE _2M
804%define X86_PAGE_2M_SHIFT 21
805%define X86_PAGE_2M_OFFSET_MASK 0x001fffff
806%define X86_PAGE_2M_BASE_MASK 0xffffffffffe00000
807%define X86_PAGE_2M_BASE_MASK_32 0xffe00000
808%define X86_PAGE_4M_SIZE _4M
809%define X86_PAGE_4M_SHIFT 22
810%define X86_PAGE_4M_OFFSET_MASK 0x003fffff
811%define X86_PAGE_4M_BASE_MASK 0xffffffffffc00000
812%define X86_PAGE_4M_BASE_MASK_32 0xffc00000
813%define X86_PAGE_1G_SIZE _1G
814%define X86_PAGE_1G_SHIFT 30
815%define X86_PAGE_1G_OFFSET_MASK 0x3fffffff
816%define X86_PAGE_1G_BASE_MASK 0xffffffffc0000000
817%define X86_IS_CANONICAL(a_u64Addr) ((uint64_t)(a_u64Addr) + 0x800000000000 < UINT64_C(0x1000000000000))
818%define X86_PTE_BIT_P 0
819%define X86_PTE_BIT_RW 1
820%define X86_PTE_BIT_US 2
821%define X86_PTE_BIT_PWT 3
822%define X86_PTE_BIT_PCD 4
823%define X86_PTE_BIT_A 5
824%define X86_PTE_BIT_D 6
825%define X86_PTE_BIT_PAT 7
826%define X86_PTE_BIT_G 8
827%define X86_PTE_PAE_BIT_NX 63
828%define X86_PTE_P RT_BIT_32(0)
829%define X86_PTE_RW RT_BIT_32(1)
830%define X86_PTE_US RT_BIT_32(2)
831%define X86_PTE_PWT RT_BIT_32(3)
832%define X86_PTE_PCD RT_BIT_32(4)
833%define X86_PTE_A RT_BIT_32(5)
834%define X86_PTE_D RT_BIT_32(6)
835%define X86_PTE_PAT RT_BIT_32(7)
836%define X86_PTE_G RT_BIT_32(8)
837%define X86_PTE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
838%define X86_PTE_PG_MASK ( 0xfffff000 )
839%define X86_PTE_PAE_PG_MASK 0x000ffffffffff000
840%define X86_PTE_PAE_NX RT_BIT_64(63)
841%define X86_PTE_PAE_MBZ_MASK_NX 0x7ff0000000000000
842%define X86_PTE_PAE_MBZ_MASK_NO_NX 0xfff0000000000000
843%define X86_PTE_LM_MBZ_MASK_NX 0x0000000000000000
844%define X86_PTE_LM_MBZ_MASK_NO_NX 0x8000000000000000
845%ifndef VBOX_FOR_DTRACE_LIB
846%endif
847%ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
848%endif
849%ifndef VBOX_FOR_DTRACE_LIB
850%endif
851%ifndef VBOX_FOR_DTRACE_LIB
852%endif
853%ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
854%endif
855%ifndef VBOX_FOR_DTRACE_LIB
856%endif
857%ifndef VBOX_FOR_DTRACE_LIB
858%endif
859%define X86_PT_SHIFT 12
860%define X86_PT_MASK 0x3ff
861%ifndef VBOX_FOR_DTRACE_LIB
862%endif
863%define X86_PT_PAE_SHIFT 12
864%define X86_PT_PAE_MASK 0x1ff
865%define X86_PDE_P RT_BIT_32(0)
866%define X86_PDE_RW RT_BIT_32(1)
867%define X86_PDE_US RT_BIT_32(2)
868%define X86_PDE_PWT RT_BIT_32(3)
869%define X86_PDE_PCD RT_BIT_32(4)
870%define X86_PDE_A RT_BIT_32(5)
871%define X86_PDE_PS RT_BIT_32(7)
872%define X86_PDE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
873%define X86_PDE_PG_MASK ( 0xfffff000 )
874%define X86_PDE_PAE_PG_MASK 0x000ffffffffff000
875%define X86_PDE_PAE_NX RT_BIT_64(63)
876%define X86_PDE_PAE_MBZ_MASK_NX 0x7ff0000000000080
877%define X86_PDE_PAE_MBZ_MASK_NO_NX 0xfff0000000000080
878%define X86_PDE_LM_MBZ_MASK_NX 0x0000000000000080
879%define X86_PDE_LM_MBZ_MASK_NO_NX 0x8000000000000080
880%ifndef VBOX_FOR_DTRACE_LIB
881%endif
882%ifndef VBOX_FOR_DTRACE_LIB
883%endif
884%define X86_PDE4M_P RT_BIT_32(0)
885%define X86_PDE4M_RW RT_BIT_32(1)
886%define X86_PDE4M_US RT_BIT_32(2)
887%define X86_PDE4M_PWT RT_BIT_32(3)
888%define X86_PDE4M_PCD RT_BIT_32(4)
889%define X86_PDE4M_A RT_BIT_32(5)
890%define X86_PDE4M_D RT_BIT_32(6)
891%define X86_PDE4M_PS RT_BIT_32(7)
892%define X86_PDE4M_G RT_BIT_32(8)
893%define X86_PDE4M_AVL (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
894%define X86_PDE4M_PAT RT_BIT_32(12)
895%define X86_PDE4M_PAT_SHIFT (12 - 7)
896%define X86_PDE4M_PG_MASK ( 0xffc00000 )
897%define X86_PDE4M_PG_HIGH_MASK ( 0x001fe000 )
898%define X86_PDE4M_PG_HIGH_SHIFT 19
899%define X86_PDE4M_MBZ_MASK RT_BIT_32(21)
900%define X86_PDE2M_PAE_PG_MASK 0x000fffffffe00000
901%define X86_PDE2M_PAE_NX RT_BIT_64(63)
902%define X86_PDE2M_PAE_MBZ_MASK_NX 0x7ff00000001fe000
903%define X86_PDE2M_PAE_MBZ_MASK_NO_NX 0xfff00000001fe000
904%define X86_PDE2M_LM_MBZ_MASK_NX 0x00000000001fe000
905%define X86_PDE2M_LM_MBZ_MASK_NO_NX 0x80000000001fe000
906%ifndef VBOX_FOR_DTRACE_LIB
907%endif
908%ifndef VBOX_FOR_DTRACE_LIB
909%endif
910%ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
911%endif
912%ifndef VBOX_FOR_DTRACE_LIB
913%endif
914%ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
915%endif
916%ifndef VBOX_FOR_DTRACE_LIB
917%endif
918%ifndef VBOX_FOR_DTRACE_LIB
919%endif
920%define X86_PD_SHIFT 22
921%define X86_PD_MASK 0x3ff
922%ifndef VBOX_FOR_DTRACE_LIB
923%endif
924%define X86_PD_PAE_SHIFT 21
925%define X86_PD_PAE_MASK 0x1ff
926%define X86_PDPE_P RT_BIT_32(0)
927%define X86_PDPE_RW RT_BIT_32(1)
928%define X86_PDPE_US RT_BIT_32(2)
929%define X86_PDPE_PWT RT_BIT_32(3)
930%define X86_PDPE_PCD RT_BIT_32(4)
931%define X86_PDPE_A RT_BIT_32(5)
932%define X86_PDPE_LM_PS RT_BIT_32(7)
933%define X86_PDPE_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
934%define X86_PDPE_PG_MASK 0x000ffffffffff000
935%define X86_PDPE_PAE_MBZ_MASK 0xfff00000000001e6
936%define X86_PDPE_LM_NX RT_BIT_64(63)
937%define X86_PDPE_LM_MBZ_MASK_NX 0x0000000000000180
938%define X86_PDPE_LM_MBZ_MASK_NO_NX 0x8000000000000180
939%define X86_PDPE1G_LM_MBZ_MASK_NX 0x000000003fffe000
940%define X86_PDPE1G_LM_MBZ_MASK_NO_NX 0x800000003fffe000
941%ifndef VBOX_FOR_DTRACE_LIB
942%endif
943%ifndef VBOX_FOR_DTRACE_LIB
944%endif
945%ifndef VBOX_FOR_DTRACE_LIB
946%endif
947%ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
948%endif
949%ifndef VBOX_FOR_DTRACE_LIB
950%endif
951%ifndef VBOX_FOR_DTRACE_LIB
952%endif
953%define X86_PDPT_SHIFT 30
954%define X86_PDPT_MASK_PAE 0x3
955%define X86_PDPT_MASK_AMD64 0x1ff
956%define X86_PML4E_P RT_BIT_32(0)
957%define X86_PML4E_RW RT_BIT_32(1)
958%define X86_PML4E_US RT_BIT_32(2)
959%define X86_PML4E_PWT RT_BIT_32(3)
960%define X86_PML4E_PCD RT_BIT_32(4)
961%define X86_PML4E_A RT_BIT_32(5)
962%define X86_PML4E_AVL_MASK (RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
963%define X86_PML4E_PG_MASK 0x000ffffffffff000
964%define X86_PML4E_MBZ_MASK_NX 0x0000000000000080
965%define X86_PML4E_MBZ_MASK_NO_NX 0x8000000000000080
966%define X86_PML4E_NX RT_BIT_64(63)
967%ifndef VBOX_FOR_DTRACE_LIB
968%endif
969%ifndef VBOX_WITHOUT_PAGING_BIT_FIELDS
970%endif
971%ifndef VBOX_FOR_DTRACE_LIB
972%endif
973%ifndef VBOX_FOR_DTRACE_LIB
974%endif
975%define X86_PML4_SHIFT 39
976%define X86_PML4_MASK 0x1ff
977%define X86_INVPCID_TYPE_INDV_ADDR 0
978%define X86_INVPCID_TYPE_SINGLE_CONTEXT 1
979%define X86_INVPCID_TYPE_ALL_CONTEXT_INCL_GLOBAL 2
980%define X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL 3
981%define X86_INVPCID_TYPE_MAX_VALID X86_INVPCID_TYPE_ALL_CONTEXT_EXCL_GLOBAL
982%ifndef VBOX_FOR_DTRACE_LIB
983%endif
984%ifndef VBOX_FOR_DTRACE_LIB
985%endif
986%ifndef VBOX_FOR_DTRACE_LIB
987%endif
988%ifndef VBOX_FOR_DTRACE_LIB
989%endif
990%ifndef VBOX_FOR_DTRACE_LIB
991%endif
992%ifndef VBOX_FOR_DTRACE_LIB
993%endif
994%ifndef VBOX_FOR_DTRACE_LIB
995%endif
996%define X86_OFF_FXSTATE_RSVD 0x1d0
997%define X86_FXSTATE_RSVD_32BIT_MAGIC 0x32b3232b
998%ifndef VBOX_FOR_DTRACE_LIB
999%endif
1000%define X86_FSW_IE RT_BIT_32(0)
1001%define X86_FSW_DE RT_BIT_32(1)
1002%define X86_FSW_ZE RT_BIT_32(2)
1003%define X86_FSW_OE RT_BIT_32(3)
1004%define X86_FSW_UE RT_BIT_32(4)
1005%define X86_FSW_PE RT_BIT_32(5)
1006%define X86_FSW_SF RT_BIT_32(6)
1007%define X86_FSW_ES RT_BIT_32(7)
1008%define X86_FSW_XCPT_MASK 0x007f
1009%define X86_FSW_XCPT_ES_MASK 0x00ff
1010%define X86_FSW_C0 RT_BIT_32(8)
1011%define X86_FSW_C1 RT_BIT_32(9)
1012%define X86_FSW_C2 RT_BIT_32(10)
1013%define X86_FSW_TOP_MASK 0x3800
1014%define X86_FSW_TOP_SHIFT 11
1015%define X86_FSW_TOP_SMASK 0x0007
1016%define X86_FSW_TOP_GET(a_uFsw) (((a_uFsw) >> X86_FSW_TOP_SHIFT) & X86_FSW_TOP_SMASK)
1017%define X86_FSW_C3 RT_BIT_32(14)
1018%define X86_FSW_C_MASK 0x4700
1019%define X86_FSW_B RT_BIT_32(15)
1020%define X86_FCW_IM RT_BIT_32(0)
1021%define X86_FCW_DM RT_BIT_32(1)
1022%define X86_FCW_ZM RT_BIT_32(2)
1023%define X86_FCW_OM RT_BIT_32(3)
1024%define X86_FCW_UM RT_BIT_32(4)
1025%define X86_FCW_PM RT_BIT_32(5)
1026%define X86_FCW_MASK_ALL 0x007f
1027%define X86_FCW_XCPT_MASK 0x003f
1028%define X86_FCW_PC_MASK 0x0300
1029%define X86_FCW_PC_24 0x0000
1030%define X86_FCW_PC_RSVD 0x0100
1031%define X86_FCW_PC_53 0x0200
1032%define X86_FCW_PC_64 0x0300
1033%define X86_FCW_RC_MASK 0x0c00
1034%define X86_FCW_RC_NEAREST 0x0000
1035%define X86_FCW_RC_DOWN 0x0400
1036%define X86_FCW_RC_UP 0x0800
1037%define X86_FCW_RC_ZERO 0x0c00
1038%define X86_FCW_ZERO_MASK 0xf080
1039%define X86_MXCSR_IE RT_BIT_32(0)
1040%define X86_MXCSR_DE RT_BIT_32(1)
1041%define X86_MXCSR_ZE RT_BIT_32(2)
1042%define X86_MXCSR_OE RT_BIT_32(3)
1043%define X86_MXCSR_UE RT_BIT_32(4)
1044%define X86_MXCSR_PE RT_BIT_32(5)
1045%define X86_MXCSR_DAZ RT_BIT_32(6)
1046%define X86_MXCSR_IM RT_BIT_32(7)
1047%define X86_MXCSR_DM RT_BIT_32(8)
1048%define X86_MXCSR_ZM RT_BIT_32(9)
1049%define X86_MXCSR_OM RT_BIT_32(10)
1050%define X86_MXCSR_UM RT_BIT_32(11)
1051%define X86_MXCSR_PM RT_BIT_32(12)
1052%define X86_MXCSR_RC_MASK 0x6000
1053%define X86_MXCSR_RC_NEAREST 0x0000
1054%define X86_MXCSR_RC_DOWN 0x2000
1055%define X86_MXCSR_RC_UP 0x4000
1056%define X86_MXCSR_RC_ZERO 0x6000
1057%define X86_MXCSR_FZ RT_BIT_32(15)
1058%define X86_MXCSR_MM RT_BIT_32(17)
1059%ifndef VBOX_FOR_DTRACE_LIB
1060%endif
1061%ifndef VBOX_FOR_DTRACE_LIB
1062%endif
1063%ifndef VBOX_FOR_DTRACE_LIB
1064%endif
1065%ifndef VBOX_FOR_DTRACE_LIB
1066%endif
1067%ifndef VBOX_FOR_DTRACE_LIB
1068%endif
1069%ifndef VBOX_FOR_DTRACE_LIB
1070%endif
1071%ifndef VBOX_FOR_DTRACE_LIB
1072%endif
1073%ifndef VBOX_FOR_DTRACE_LIB
1074%endif
1075%ifndef VBOX_FOR_DTRACE_LIB
1076%endif
1077%define XSAVE_C_X87_BIT 0
1078%define XSAVE_C_X87 RT_BIT_64(XSAVE_C_X87_BIT)
1079%define XSAVE_C_SSE_BIT 1
1080%define XSAVE_C_SSE RT_BIT_64(XSAVE_C_SSE_BIT)
1081%define XSAVE_C_YMM_BIT 2
1082%define XSAVE_C_YMM RT_BIT_64(XSAVE_C_YMM_BIT)
1083%define XSAVE_C_BNDREGS_BIT 3
1084%define XSAVE_C_BNDREGS RT_BIT_64(XSAVE_C_BNDREGS_BIT)
1085%define XSAVE_C_BNDCSR_BIT 4
1086%define XSAVE_C_BNDCSR RT_BIT_64(XSAVE_C_BNDCSR_BIT)
1087%define XSAVE_C_OPMASK_BIT 5
1088%define XSAVE_C_OPMASK RT_BIT_64(XSAVE_C_OPMASK_BIT)
1089%define XSAVE_C_ZMM_HI256_BIT 6
1090%define XSAVE_C_ZMM_HI256 RT_BIT_64(XSAVE_C_ZMM_HI256_BIT)
1091%define XSAVE_C_ZMM_16HI_BIT 7
1092%define XSAVE_C_ZMM_16HI RT_BIT_64(XSAVE_C_ZMM_16HI_BIT)
1093%define XSAVE_C_PKRU_BIT 9
1094%define XSAVE_C_PKRU RT_BIT_64(XSAVE_C_PKRU_BIT)
1095%define XSAVE_C_LWP_BIT 62
1096%define XSAVE_C_LWP RT_BIT_64(XSAVE_C_LWP_BIT)
1097%define XSAVE_C_X_BIT 63
1098%define XSAVE_C_X RT_BIT_64(XSAVE_C_X_BIT)
1099%ifndef VBOX_FOR_DTRACE_LIB
1100%endif
1101%define X86DESCATTR_TYPE 0x0000000f
1102%define X86DESCATTR_DT 0x00000010
1103%define X86DESCATTR_DPL 0x00000060
1104%define X86DESCATTR_DPL_SHIFT 5
1105%define X86DESCATTR_P 0x00000080
1106%define X86DESCATTR_LIMIT_HIGH 0x00000f00
1107%define X86DESCATTR_AVL 0x00001000
1108%define X86DESCATTR_L 0x00002000
1109%define X86DESCATTR_D 0x00004000
1110%define X86DESCATTR_G 0x00008000
1111%define X86DESCATTR_UNUSABLE 0x00010000
1112%ifndef VBOX_FOR_DTRACE_LIB
1113%endif
1114%ifndef VBOX_FOR_DTRACE_LIB
1115%define X86DESCGENERIC_BIT_OFF_LIMIT_LOW (0)
1116%define X86DESCGENERIC_BIT_OFF_BASE_LOW (16)
1117%define X86DESCGENERIC_BIT_OFF_BASE_HIGH1 (32)
1118%define X86DESCGENERIC_BIT_OFF_TYPE (40)
1119%define X86DESCGENERIC_BIT_OFF_DESC_TYPE (44)
1120%define X86DESCGENERIC_BIT_OFF_DPL (45)
1121%define X86DESCGENERIC_BIT_OFF_PRESENT (47)
1122%define X86DESCGENERIC_BIT_OFF_LIMIT_HIGH (48)
1123%define X86DESCGENERIC_BIT_OFF_AVAILABLE (52)
1124%define X86DESCGENERIC_BIT_OFF_LONG (53)
1125%define X86DESCGENERIC_BIT_OFF_DEF_BIG (54)
1126%define X86DESCGENERIC_BIT_OFF_GRANULARITY (55)
1127%define X86DESCGENERIC_BIT_OFF_BASE_HIGH2 (56)
1128%define X86LAR_F_TYPE 0x0f00
1129%define X86LAR_F_DT 0x1000
1130%define X86LAR_F_DPL 0x6000
1131%define X86LAR_F_DPL_SHIFT 13
1132%define X86LAR_F_P 0x8000
1133%define X86LAR_F_AVL 0x00100000
1134%define X86LAR_F_L 0x00200000
1135%define X86LAR_F_D 0x00400000
1136%define X86LAR_F_G 0x00800000
1137%endif
1138%ifndef VBOX_FOR_DTRACE_LIB
1139%endif
1140%ifndef VBOX_FOR_DTRACE_LIB
1141%endif
1142%ifndef VBOX_FOR_DTRACE_LIB
1143%endif
1144%ifndef VBOX_FOR_DTRACE_LIB
1145%endif
1146%ifndef VBOX_FOR_DTRACE_LIB
1147%endif
1148%if HC_ARCH_BITS == 64
1149%else
1150%endif
1151%if HC_ARCH_BITS == 64
1152%else
1153%endif
1154%if HC_ARCH_BITS == 64
1155%else
1156%endif
1157%define X86_SEL_TYPE_CODE 8
1158%define X86_SEL_TYPE_MEMORY RT_BIT_32(4)
1159%define X86_SEL_TYPE_ACCESSED 1
1160%define X86_SEL_TYPE_DOWN 4
1161%define X86_SEL_TYPE_CONF 4
1162%define X86_SEL_TYPE_WRITE 2
1163%define X86_SEL_TYPE_READ 2
1164%define X86_SEL_TYPE_READ_BIT 1
1165%define X86_SEL_TYPE_RO 0
1166%define X86_SEL_TYPE_RO_ACC (0 | X86_SEL_TYPE_ACCESSED)
1167%define X86_SEL_TYPE_RW 2
1168%define X86_SEL_TYPE_RW_ACC (2 | X86_SEL_TYPE_ACCESSED)
1169%define X86_SEL_TYPE_RO_DOWN 4
1170%define X86_SEL_TYPE_RO_DOWN_ACC (4 | X86_SEL_TYPE_ACCESSED)
1171%define X86_SEL_TYPE_RW_DOWN 6
1172%define X86_SEL_TYPE_RW_DOWN_ACC (6 | X86_SEL_TYPE_ACCESSED)
1173%define X86_SEL_TYPE_EO (0 | X86_SEL_TYPE_CODE)
1174%define X86_SEL_TYPE_EO_ACC (0 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
1175%define X86_SEL_TYPE_ER (2 | X86_SEL_TYPE_CODE)
1176%define X86_SEL_TYPE_ER_ACC (2 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
1177%define X86_SEL_TYPE_EO_CONF (4 | X86_SEL_TYPE_CODE)
1178%define X86_SEL_TYPE_EO_CONF_ACC (4 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
1179%define X86_SEL_TYPE_ER_CONF (6 | X86_SEL_TYPE_CODE)
1180%define X86_SEL_TYPE_ER_CONF_ACC (6 | X86_SEL_TYPE_CODE | X86_SEL_TYPE_ACCESSED)
1181%define X86_SEL_TYPE_SYS_TSS_BUSY_MASK 2
1182%define X86_SEL_TYPE_SYS_UNDEFINED 0
1183%define X86_SEL_TYPE_SYS_286_TSS_AVAIL 1
1184%define X86_SEL_TYPE_SYS_LDT 2
1185%define X86_SEL_TYPE_SYS_286_TSS_BUSY 3
1186%define X86_SEL_TYPE_SYS_286_CALL_GATE 4
1187%define X86_SEL_TYPE_SYS_TASK_GATE 5
1188%define X86_SEL_TYPE_SYS_286_INT_GATE 6
1189%define X86_SEL_TYPE_SYS_286_TRAP_GATE 7
1190%define X86_SEL_TYPE_SYS_UNDEFINED2 8
1191%define X86_SEL_TYPE_SYS_386_TSS_AVAIL 9
1192%define X86_SEL_TYPE_SYS_UNDEFINED3 0xA
1193%define X86_SEL_TYPE_SYS_386_TSS_BUSY 0xB
1194%define X86_SEL_TYPE_SYS_386_CALL_GATE 0xC
1195%define X86_SEL_TYPE_SYS_UNDEFINED4 0xD
1196%define X86_SEL_TYPE_SYS_386_INT_GATE 0xE
1197%define X86_SEL_TYPE_SYS_386_TRAP_GATE 0xF
1198%define AMD64_SEL_TYPE_SYS_LDT 2
1199%define AMD64_SEL_TYPE_SYS_TSS_AVAIL 9
1200%define AMD64_SEL_TYPE_SYS_TSS_BUSY 0xB
1201%define AMD64_SEL_TYPE_SYS_CALL_GATE 0xC
1202%define AMD64_SEL_TYPE_SYS_INT_GATE 0xE
1203%define AMD64_SEL_TYPE_SYS_TRAP_GATE 0xF
1204%define X86_DESC_TYPE_MASK (RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11))
1205%define X86_DESC_S RT_BIT_32(12)
1206%define X86_DESC_DPL (RT_BIT_32(13) | RT_BIT_32(14))
1207%define X86_DESC_P RT_BIT_32(15)
1208%define X86_DESC_AVL RT_BIT_32(20)
1209%define X86_DESC_DB RT_BIT_32(22)
1210%define X86_DESC_G RT_BIT_32(23)
1211%define X86_SEL_TYPE_SYS_286_TSS_LIMIT_MIN 0x2b
1212%define X86_SEL_TYPE_SYS_386_TSS_LIMIT_MIN 0x67
1213%ifndef VBOX_FOR_DTRACE_LIB
1214%endif
1215%ifndef VBOX_FOR_DTRACE_LIB
1216%endif
1217%ifndef VBOX_FOR_DTRACE_LIB
1218%endif
1219%define X86_SEL_SHIFT 3
1220%define X86_SEL_MASK 0xfff8
1221%define X86_SEL_MASK_OFF_RPL 0xfffc
1222%define X86_SEL_LDT 0x0004
1223%define X86_SEL_RPL 0x0003
1224%define X86_SEL_RPL_LDT 0x0007
1225%define X86_XCPT_LAST 0x1f
1226%define X86_TRAP_ERR_EXTERNAL 1
1227%define X86_TRAP_ERR_IDT 2
1228%define X86_TRAP_ERR_TI 4
1229%define X86_TRAP_ERR_SEL_MASK 0xfff8
1230%define X86_TRAP_ERR_SEL_SHIFT 3
1231%define X86_TRAP_PF_P RT_BIT_32(0)
1232%define X86_TRAP_PF_RW RT_BIT_32(1)
1233%define X86_TRAP_PF_US RT_BIT_32(2)
1234%define X86_TRAP_PF_RSVD RT_BIT_32(3)
1235%define X86_TRAP_PF_ID RT_BIT_32(4)
1236%define X86_TRAP_PF_PK RT_BIT_32(5)
1237%ifndef VBOX_FOR_DTRACE_LIB
1238%else
1239%endif
1240%ifndef VBOX_FOR_DTRACE_LIB
1241%else
1242%endif
1243%define X86_MODRM_RM_MASK 0x07
1244%define X86_MODRM_REG_MASK 0x38
1245%define X86_MODRM_REG_SMASK 0x07
1246%define X86_MODRM_REG_SHIFT 3
1247%define X86_MODRM_MOD_MASK 0xc0
1248%define X86_MODRM_MOD_SMASK 0x03
1249%define X86_MODRM_MOD_SHIFT 6
1250%ifndef VBOX_FOR_DTRACE_LIB
1251 %define X86_MODRM_MAKE(a_Mod, a_Reg, a_RegMem) (((a_Mod) << X86_MODRM_MOD_SHIFT) | ((a_Reg) << X86_MODRM_REG_SHIFT) | (a_RegMem))
1252%endif
1253%define X86_SIB_BASE_MASK 0x07
1254%define X86_SIB_INDEX_MASK 0x38
1255%define X86_SIB_INDEX_SMASK 0x07
1256%define X86_SIB_INDEX_SHIFT 3
1257%define X86_SIB_SCALE_MASK 0xc0
1258%define X86_SIB_SCALE_SMASK 0x03
1259%define X86_SIB_SCALE_SHIFT 6
1260%ifndef VBOX_FOR_DTRACE_LIB
1261%endif
1262%define X86_GREG_xAX 0
1263%define X86_GREG_xCX 1
1264%define X86_GREG_xDX 2
1265%define X86_GREG_xBX 3
1266%define X86_GREG_xSP 4
1267%define X86_GREG_xBP 5
1268%define X86_GREG_xSI 6
1269%define X86_GREG_xDI 7
1270%define X86_GREG_x8 8
1271%define X86_GREG_x9 9
1272%define X86_GREG_x10 10
1273%define X86_GREG_x11 11
1274%define X86_GREG_x12 12
1275%define X86_GREG_x13 13
1276%define X86_GREG_x14 14
1277%define X86_GREG_x15 15
1278%define X86_GREG_COUNT 16
1279%define X86_SREG_ES 0
1280%define X86_SREG_CS 1
1281%define X86_SREG_SS 2
1282%define X86_SREG_DS 3
1283%define X86_SREG_FS 4
1284%define X86_SREG_GS 5
1285%define X86_SREG_COUNT 6
1286%define X86_OP_PRF_CS 0x2e
1287%define X86_OP_PRF_SS 0x36
1288%define X86_OP_PRF_DS 0x3e
1289%define X86_OP_PRF_ES 0x26
1290%define X86_OP_PRF_FS 0x64
1291%define X86_OP_PRF_GS 0x65
1292%define X86_OP_PRF_SIZE_OP 0x66
1293%define X86_OP_PRF_SIZE_ADDR 0x67
1294%define X86_OP_PRF_LOCK 0xf0
1295%define X86_OP_PRF_REPZ 0xf3
1296%define X86_OP_PRF_REPNZ 0xf2
1297%define X86_OP_REX_B 0x41
1298%define X86_OP_REX_X 0x42
1299%define X86_OP_REX_R 0x44
1300%define X86_OP_REX_W 0x48
1301%endif
1302%include "iprt/x86extra.mac"
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