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Last change
on this file since 40138 was 40138, checked in by vboxsync, 13 years ago |
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IEM: fdiv work. Added x86extra.mac for non-automatic x86.h bits.
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Author Date Id Revision
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File size:
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| 1 | ;; @file
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| 2 | ; IPRT - X86 and AMD64 Structures and Definitions that are not automatically
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| 3 | ; converted from the C header file.
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| 4 | ;
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| 5 |
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| 6 | ;
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| 7 | ; Copyright (C) 2012 Oracle Corporation
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| 8 | ;
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| 9 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | ; available from http://www.virtualbox.org. This file is free software;
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| 11 | ; you can redistribute it and/or modify it under the terms of the GNU
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| 12 | ; General Public License (GPL) as published by the Free Software
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| 13 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | ;
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| 17 | ; The contents of this file may alternatively be used under the terms
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| 18 | ; of the Common Development and Distribution License Version 1.0
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| 19 | ; (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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| 20 | ; VirtualBox OSE distribution, in which case the provisions of the
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| 21 | ; CDDL are applicable instead of those of the GPL.
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| 22 | ;
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| 23 | ; You may elect to license modified versions of this file under the
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| 24 | ; terms and conditions of either the GPL or the CDDL or both.
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| 25 | ;
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| 26 |
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| 27 | %ifndef ___iprt_x86extra_mac
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| 28 | %define ___iprt_x86extra_mac
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| 29 |
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| 30 |
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| 31 | ;;
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| 32 | ; 32-bit protected mode fstenv image.
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| 33 | ;
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| 34 | struc X86FSTENV32P
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| 35 | .FCW resw 1
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| 36 | .padding1 resw 1
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| 37 | .FSW resw 1
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| 38 | .padding2 resw 1
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| 39 | .FTW resw 1
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| 40 | .padding3 resw 1
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| 41 | .FPUIP resd 1
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| 42 | .FPUCS resw 1
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| 43 | .FOP resw 1
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| 44 | .FPUDP resd 1
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| 45 | .FPUDS resw 1
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| 46 | .padding4 resw 1
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| 47 | endstruc
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| 48 |
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| 49 |
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| 50 | ;;
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| 51 | ; The image saved by FXSAVE.
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| 52 | ;
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| 53 | struc X86FXSTATE
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| 54 | .FCW resw 1
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| 55 | .FSW resw 1
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| 56 | .FTW resw 1
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| 57 | .FOP resw 1
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| 58 | .FPUIP resd 1
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| 59 | .FPUCS resw 1
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| 60 | .Rsrvd1 resw 1
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| 61 | .FPUDP resd 1
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| 62 | .FPUDS resw 1
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| 63 | .Rsrvd2 resw 1
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| 64 | .MXCSR resd 1
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| 65 | .MXCSR_MASK resd 1
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| 66 | .st0 resd 4
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| 67 | .st1 resd 4
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| 68 | .st2 resd 4
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| 69 | .st3 resd 4
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| 70 | .st4 resd 4
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| 71 | .st5 resd 4
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| 72 | .st6 resd 4
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| 73 | .st7 resd 4
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| 74 | .xmm0 resd 4
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| 75 | .xmm1 resd 4
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| 76 | .xmm2 resd 4
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| 77 | .xmm3 resd 4
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| 78 | .xmm4 resd 4
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| 79 | .xmm5 resd 4
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| 80 | .xmm6 resd 4
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| 81 | .xmm7 resd 4
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| 82 | .xmm8 resd 4
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| 83 | .xmm9 resd 4
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| 84 | .xmm10 resd 4
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| 85 | .xmm11 resd 4
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| 86 | .xmm12 resd 4
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| 87 | .xmm13 resd 4
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| 88 | .xmm14 resd 4
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| 89 | .xmm15 resd 4
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| 90 | .au32RsrvdRest resd 24
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| 91 | endstruc
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| 92 |
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| 93 |
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| 94 | %endif
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| 95 |
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