Last change
on this file since 40140 was 40140, checked in by vboxsync, 13 years ago |
Move X86_XCPT_* to x86extra.mac.
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Author Date Id Revision
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1 | ;; @file
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2 | ; IPRT - X86 and AMD64 Structures and Definitions that are not automatically
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3 | ; converted from the C header file.
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4 | ;
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5 |
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6 | ;
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7 | ; Copyright (C) 2012 Oracle Corporation
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8 | ;
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9 | ; This file is part of VirtualBox Open Source Edition (OSE), as
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10 | ; available from http://www.virtualbox.org. This file is free software;
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11 | ; you can redistribute it and/or modify it under the terms of the GNU
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12 | ; General Public License (GPL) as published by the Free Software
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13 | ; Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | ; VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | ; hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | ;
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17 | ; The contents of this file may alternatively be used under the terms
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18 | ; of the Common Development and Distribution License Version 1.0
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19 | ; (CDDL) only, as it comes in the "COPYING.CDDL" file of the
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20 | ; VirtualBox OSE distribution, in which case the provisions of the
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21 | ; CDDL are applicable instead of those of the GPL.
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22 | ;
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23 | ; You may elect to license modified versions of this file under the
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24 | ; terms and conditions of either the GPL or the CDDL or both.
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25 | ;
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26 |
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27 | %ifndef ___iprt_x86extra_mac
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28 | %define ___iprt_x86extra_mac
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29 |
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30 |
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31 | %define X86_XCPT_UD 6
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32 | %define X86_XCPT_GP 13
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33 | %define X86_XCPT_PF 14
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34 | %define X86_XCPT_MF 16
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35 |
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36 | %define PAGE_SIZE 0x1000
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37 |
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38 |
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39 | ;;
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40 | ; 32-bit protected mode fstenv image.
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41 | ;
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42 | struc X86FSTENV32P
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43 | .FCW resw 1
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44 | .padding1 resw 1
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45 | .FSW resw 1
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46 | .padding2 resw 1
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47 | .FTW resw 1
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48 | .padding3 resw 1
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49 | .FPUIP resd 1
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50 | .FPUCS resw 1
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51 | .FOP resw 1
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52 | .FPUDP resd 1
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53 | .FPUDS resw 1
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54 | .padding4 resw 1
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55 | endstruc
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56 |
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57 |
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58 | ;;
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59 | ; The image saved by FXSAVE.
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60 | ;
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61 | struc X86FXSTATE
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62 | .FCW resw 1
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63 | .FSW resw 1
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64 | .FTW resw 1
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65 | .FOP resw 1
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66 | .FPUIP resd 1
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67 | .FPUCS resw 1
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68 | .Rsrvd1 resw 1
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69 | .FPUDP resd 1
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70 | .FPUDS resw 1
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71 | .Rsrvd2 resw 1
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72 | .MXCSR resd 1
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73 | .MXCSR_MASK resd 1
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74 | .st0 resd 4
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75 | .st1 resd 4
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76 | .st2 resd 4
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77 | .st3 resd 4
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78 | .st4 resd 4
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79 | .st5 resd 4
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80 | .st6 resd 4
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81 | .st7 resd 4
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82 | .xmm0 resd 4
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83 | .xmm1 resd 4
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84 | .xmm2 resd 4
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85 | .xmm3 resd 4
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86 | .xmm4 resd 4
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87 | .xmm5 resd 4
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88 | .xmm6 resd 4
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89 | .xmm7 resd 4
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90 | .xmm8 resd 4
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91 | .xmm9 resd 4
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92 | .xmm10 resd 4
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93 | .xmm11 resd 4
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94 | .xmm12 resd 4
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95 | .xmm13 resd 4
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96 | .xmm14 resd 4
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97 | .xmm15 resd 4
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98 | .au32RsrvdRest resd 24
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99 | endstruc
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100 |
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101 |
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102 | %endif
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103 |
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