| 1 | /*
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| 2 | * File cvconst.h - MS debug information
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| 3 | *
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| 4 | * Copyright (C) 2004, Eric Pouech
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| 5 | *
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| 6 | * This library is free software; you can redistribute it and/or
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| 7 | * modify it under the terms of the GNU Lesser General Public
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| 8 | * License as published by the Free Software Foundation; either
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| 9 | * version 2.1 of the License, or (at your option) any later version.
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| 10 | *
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| 11 | * This library is distributed in the hope that it will be useful,
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| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 14 | * Lesser General Public License for more details.
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| 15 | *
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| 16 | * You should have received a copy of the GNU Lesser General Public
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| 17 | * License along with this library; if not, write to the Free Software
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| 18 | * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA
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| 19 | */
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| 20 |
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| 21 | /*
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| 22 | * Sun LGPL Disclaimer: For the avoidance of doubt, except that if any license choice
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| 23 | * other than GPL or LGPL is available it will apply instead, Sun elects to use only
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| 24 | * the Lesser General Public License version 2.1 (LGPLv2) at this time for any software where
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| 25 | * a choice of LGPL license versions is made available with the language indicating
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| 26 | * that LGPLv2 or any later version may be used, or where a choice of which version
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| 27 | * of the LGPL is applied is otherwise unspecified.
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| 28 | */
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| 29 |
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| 30 | /* information in this file is highly derived from MSDN DIA information pages */
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| 31 |
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| 32 | /* symbols & types enumeration */
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| 33 | enum SymTagEnum
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| 34 | {
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| 35 | SymTagNull,
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| 36 | SymTagExe,
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| 37 | SymTagCompiland,
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| 38 | SymTagCompilandDetails,
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| 39 | SymTagCompilandEnv,
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| 40 | SymTagFunction,
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| 41 | SymTagBlock,
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| 42 | SymTagData,
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| 43 | SymTagAnnotation,
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| 44 | SymTagLabel,
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| 45 | SymTagPublicSymbol,
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| 46 | SymTagUDT,
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| 47 | SymTagEnum,
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| 48 | SymTagFunctionType,
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| 49 | SymTagPointerType,
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| 50 | SymTagArrayType,
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| 51 | SymTagBaseType,
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| 52 | SymTagTypedef,
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| 53 | SymTagBaseClass,
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| 54 | SymTagFriend,
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| 55 | SymTagFunctionArgType,
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| 56 | SymTagFuncDebugStart,
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| 57 | SymTagFuncDebugEnd,
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| 58 | SymTagUsingNamespace,
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| 59 | SymTagVTableShape,
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| 60 | SymTagVTable,
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| 61 | SymTagCustom,
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| 62 | SymTagThunk,
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| 63 | SymTagCustomType,
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| 64 | SymTagManagedType,
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| 65 | SymTagDimension,
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| 66 | SymTagMax
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| 67 | };
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| 68 |
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| 69 | enum BasicType
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| 70 | {
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| 71 | btNoType = 0,
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| 72 | btVoid = 1,
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| 73 | btChar = 2,
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| 74 | btWChar = 3,
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| 75 | btInt = 6,
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| 76 | btUInt = 7,
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| 77 | btFloat = 8,
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| 78 | btBCD = 9,
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| 79 | btBool = 10,
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| 80 | btLong = 13,
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| 81 | btULong = 14,
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| 82 | btCurrency = 25,
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| 83 | btDate = 26,
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| 84 | btVariant = 27,
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| 85 | btComplex = 28,
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| 86 | btBit = 29,
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| 87 | btBSTR = 30,
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| 88 | btHresult = 31,
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| 89 | };
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| 90 |
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| 91 | /* kind of UDT */
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| 92 | enum UdtKind
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| 93 | {
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| 94 | UdtStruct,
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| 95 | UdtClass,
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| 96 | UdtUnion
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| 97 | };
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| 98 |
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| 99 | /* where a SymTagData is */
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| 100 | enum LocationType
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| 101 | {
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| 102 | LocIsNull,
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| 103 | LocIsStatic,
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| 104 | LocIsTLS,
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| 105 | LocIsRegRel,
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| 106 | LocIsThisRel,
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| 107 | LocIsEnregistered,
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| 108 | LocIsBitField,
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| 109 | LocIsSlot,
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| 110 | LocIsIlRel,
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| 111 | LocInMetaData,
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| 112 | LocIsConstant
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| 113 | };
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| 114 |
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| 115 | /* kind of SymTagData */
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| 116 | enum DataKind
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| 117 | {
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| 118 | DataIsUnknown,
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| 119 | DataIsLocal,
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| 120 | DataIsStaticLocal,
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| 121 | DataIsParam,
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| 122 | DataIsObjectPtr,
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| 123 | DataIsFileStatic,
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| 124 | DataIsGlobal,
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| 125 | DataIsMember,
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| 126 | DataIsStaticMember,
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| 127 | DataIsConstant
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| 128 | };
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| 129 |
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| 130 | /* values for registers (on different CPUs) */
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| 131 | enum CV_HREG_e
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| 132 | {
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| 133 | /* those values are common to all supported CPUs (and CPU independent) */
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| 134 | CV_ALLREG_ERR = 30000,
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| 135 | CV_ALLREG_TEB = 30001,
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| 136 | CV_ALLREG_TIMER = 30002,
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| 137 | CV_ALLREG_EFAD1 = 30003,
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| 138 | CV_ALLREG_EFAD2 = 30004,
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| 139 | CV_ALLREG_EFAD3 = 30005,
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| 140 | CV_ALLREG_VFRAME = 30006,
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| 141 | CV_ALLREG_HANDLE = 30007,
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| 142 | CV_ALLREG_PARAMS = 30008,
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| 143 | CV_ALLREG_LOCALS = 30009,
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| 144 |
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| 145 | /* Intel x86 CPU */
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| 146 | CV_REG_NONE = 0,
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| 147 | CV_REG_AL = 1,
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| 148 | CV_REG_CL = 2,
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| 149 | CV_REG_DL = 3,
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| 150 | CV_REG_BL = 4,
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| 151 | CV_REG_AH = 5,
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| 152 | CV_REG_CH = 6,
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| 153 | CV_REG_DH = 7,
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| 154 | CV_REG_BH = 8,
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| 155 | CV_REG_AX = 9,
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| 156 | CV_REG_CX = 10,
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| 157 | CV_REG_DX = 11,
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| 158 | CV_REG_BX = 12,
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| 159 | CV_REG_SP = 13,
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| 160 | CV_REG_BP = 14,
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| 161 | CV_REG_SI = 15,
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| 162 | CV_REG_DI = 16,
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| 163 | CV_REG_EAX = 17,
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| 164 | CV_REG_ECX = 18,
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| 165 | CV_REG_EDX = 19,
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| 166 | CV_REG_EBX = 20,
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| 167 | CV_REG_ESP = 21,
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| 168 | CV_REG_EBP = 22,
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| 169 | CV_REG_ESI = 23,
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| 170 | CV_REG_EDI = 24,
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| 171 | CV_REG_ES = 25,
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| 172 | CV_REG_CS = 26,
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| 173 | CV_REG_SS = 27,
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| 174 | CV_REG_DS = 28,
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| 175 | CV_REG_FS = 29,
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| 176 | CV_REG_GS = 30,
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| 177 | CV_REG_IP = 31,
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| 178 | CV_REG_FLAGS = 32,
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| 179 | CV_REG_EIP = 33,
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| 180 | CV_REG_EFLAGS = 34,
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| 181 |
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| 182 | /* <pcode> */
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| 183 | CV_REG_TEMP = 40,
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| 184 | CV_REG_TEMPH = 41,
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| 185 | CV_REG_QUOTE = 42,
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| 186 | CV_REG_PCDR3 = 43, /* this includes PCDR4 to PCDR7 */
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| 187 | CV_REG_CR0 = 80, /* this includes CR1 to CR4 */
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| 188 | CV_REG_DR0 = 90, /* this includes DR1 to DR7 */
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| 189 | /* </pcode> */
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| 190 |
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| 191 | CV_REG_GDTR = 110,
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| 192 | CV_REG_GDTL = 111,
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| 193 | CV_REG_IDTR = 112,
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| 194 | CV_REG_IDTL = 113,
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| 195 | CV_REG_LDTR = 114,
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| 196 | CV_REG_TR = 115,
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| 197 |
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| 198 | CV_REG_PSEUDO1 = 116, /* this includes Pseudo02 to Pseudo09 */
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| 199 | CV_REG_ST0 = 128, /* this includes ST1 to ST7 */
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| 200 | CV_REG_CTRL = 136,
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| 201 | CV_REG_STAT = 137,
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| 202 | CV_REG_TAG = 138,
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| 203 | CV_REG_FPIP = 139,
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| 204 | CV_REG_FPCS = 140,
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| 205 | CV_REG_FPDO = 141,
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| 206 | CV_REG_FPDS = 142,
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| 207 | CV_REG_ISEM = 143,
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| 208 | CV_REG_FPEIP = 144,
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| 209 | CV_REG_FPEDO = 145,
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| 210 | CV_REG_MM0 = 146, /* this includes MM1 to MM7 */
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| 211 | CV_REG_XMM0 = 154, /* this includes XMM1 to XMM7 */
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| 212 | CV_REG_XMM00 = 162,
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| 213 | CV_REG_XMM0L = 194, /* this includes XMM1L to XMM7L */
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| 214 | CV_REG_XMM0H = 202, /* this includes XMM1H to XMM7H */
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| 215 | CV_REG_MXCSR = 211,
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| 216 | CV_REG_EDXEAX = 212,
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| 217 | CV_REG_EMM0L = 220,
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| 218 | CV_REG_EMM0H = 228,
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| 219 | CV_REG_MM00 = 236,
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| 220 | CV_REG_MM01 = 237,
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| 221 | CV_REG_MM10 = 238,
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| 222 | CV_REG_MM11 = 239,
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| 223 | CV_REG_MM20 = 240,
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| 224 | CV_REG_MM21 = 241,
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| 225 | CV_REG_MM30 = 242,
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| 226 | CV_REG_MM31 = 243,
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| 227 | CV_REG_MM40 = 244,
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| 228 | CV_REG_MM41 = 245,
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| 229 | CV_REG_MM50 = 246,
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| 230 | CV_REG_MM51 = 247,
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| 231 | CV_REG_MM60 = 248,
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| 232 | CV_REG_MM61 = 249,
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| 233 | CV_REG_MM70 = 250,
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| 234 | CV_REG_MM71 = 251,
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| 235 |
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| 236 | /* Motorola 68K CPU */
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| 237 | CV_R68_D0 = 0, /* this includes D1 to D7 too */
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| 238 | CV_R68_A0 = 8, /* this includes A1 to A7 too */
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| 239 | CV_R68_CCR = 16,
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| 240 | CV_R68_SR = 17,
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| 241 | CV_R68_USP = 18,
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| 242 | CV_R68_MSP = 19,
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| 243 | CV_R68_SFC = 20,
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| 244 | CV_R68_DFC = 21,
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| 245 | CV_R68_CACR = 22,
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| 246 | CV_R68_VBR = 23,
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| 247 | CV_R68_CAAR = 24,
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| 248 | CV_R68_ISP = 25,
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| 249 | CV_R68_PC = 26,
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| 250 | CV_R68_FPCR = 28,
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| 251 | CV_R68_FPSR = 29,
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| 252 | CV_R68_FPIAR = 30,
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| 253 | CV_R68_FP0 = 32, /* this includes FP1 to FP7 */
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| 254 | CV_R68_MMUSR030 = 41,
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| 255 | CV_R68_MMUSR = 42,
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| 256 | CV_R68_URP = 43,
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| 257 | CV_R68_DTT0 = 44,
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| 258 | CV_R68_DTT1 = 45,
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| 259 | CV_R68_ITT0 = 46,
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| 260 | CV_R68_ITT1 = 47,
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| 261 | CV_R68_PSR = 51,
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| 262 | CV_R68_PCSR = 52,
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| 263 | CV_R68_VAL = 53,
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| 264 | CV_R68_CRP = 54,
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| 265 | CV_R68_SRP = 55,
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| 266 | CV_R68_DRP = 56,
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| 267 | CV_R68_TC = 57,
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| 268 | CV_R68_AC = 58,
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| 269 | CV_R68_SCC = 59,
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| 270 | CV_R68_CAL = 60,
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| 271 | CV_R68_TT0 = 61,
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| 272 | CV_R68_TT1 = 62,
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| 273 | CV_R68_BAD0 = 64, /* this includes BAD1 to BAD7 */
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| 274 | CV_R68_BAC0 = 72, /* this includes BAC1 to BAC7 */
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| 275 |
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| 276 | /* MIPS 4000 CPU */
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| 277 | CV_M4_NOREG = CV_REG_NONE,
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| 278 | CV_M4_IntZERO = 10,
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| 279 | CV_M4_IntAT = 11,
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| 280 | CV_M4_IntV0 = 12,
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| 281 | CV_M4_IntV1 = 13,
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| 282 | CV_M4_IntA0 = 14, /* this includes IntA1 to IntA3 */
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| 283 | CV_M4_IntT0 = 18, /* this includes IntT1 to IntT7 */
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| 284 | CV_M4_IntS0 = 26, /* this includes IntS1 to IntS7 */
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| 285 | CV_M4_IntT8 = 34,
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| 286 | CV_M4_IntT9 = 35,
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| 287 | CV_M4_IntKT0 = 36,
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| 288 | CV_M4_IntKT1 = 37,
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| 289 | CV_M4_IntGP = 38,
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| 290 | CV_M4_IntSP = 39,
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| 291 | CV_M4_IntS8 = 40,
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| 292 | CV_M4_IntRA = 41,
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| 293 | CV_M4_IntLO = 42,
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| 294 | CV_M4_IntHI = 43,
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| 295 | CV_M4_Fir = 50,
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| 296 | CV_M4_Psr = 51,
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| 297 | CV_M4_FltF0 = 60, /* this includes FltF1 to Flt31 */
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| 298 | CV_M4_FltFsr = 92,
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| 299 |
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| 300 | /* Alpha AXP CPU */
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| 301 | CV_ALPHA_NOREG = CV_REG_NONE,
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| 302 | CV_ALPHA_FltF0 = 10, /* this includes FltF1 to FltF31 */
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| 303 | CV_ALPHA_IntV0 = 42,
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| 304 | CV_ALPHA_IntT0 = 43, /* this includes T1 to T7 */
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| 305 | CV_ALPHA_IntS0 = 51, /* this includes S1 to S5 */
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| 306 | CV_ALPHA_IntFP = 57,
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| 307 | CV_ALPHA_IntA0 = 58, /* this includes A1 to A5 */
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| 308 | CV_ALPHA_IntT8 = 64,
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| 309 | CV_ALPHA_IntT9 = 65,
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| 310 | CV_ALPHA_IntT10 = 66,
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| 311 | CV_ALPHA_IntT11 = 67,
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| 312 | CV_ALPHA_IntRA = 68,
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| 313 | CV_ALPHA_IntT12 = 69,
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| 314 | CV_ALPHA_IntAT = 70,
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| 315 | CV_ALPHA_IntGP = 71,
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| 316 | CV_ALPHA_IntSP = 72,
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| 317 | CV_ALPHA_IntZERO = 73,
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| 318 | CV_ALPHA_Fpcr = 74,
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| 319 | CV_ALPHA_Fir = 75,
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| 320 | CV_ALPHA_Psr = 76,
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| 321 | CV_ALPHA_FltFsr = 77,
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| 322 | CV_ALPHA_SoftFpcr = 78,
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| 323 |
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| 324 | /* Motorola & IBM PowerPC CPU */
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| 325 | CV_PPC_GPR0 = 1, /* this includes GPR1 to GPR31 */
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| 326 | CV_PPC_CR = 33,
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| 327 | CV_PPC_CR0 = 34, /* this includes CR1 to CR7 */
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| 328 | CV_PPC_FPR0 = 42, /* this includes FPR1 to FPR31 */
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| 329 |
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| 330 | CV_PPC_FPSCR = 74,
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| 331 | CV_PPC_MSR = 75,
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| 332 | CV_PPC_SR0 = 76, /* this includes SR1 to SR15 */
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| 333 | /* some PPC registers missing */
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| 334 |
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| 335 | /* Hitachi SH3 CPU */
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| 336 | CV_SH3_NOREG = CV_REG_NONE,
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| 337 | CV_SH3_IntR0 = 10, /* this include R1 to R13 */
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| 338 | CV_SH3_IntFp = 24,
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| 339 | CV_SH3_IntSp = 25,
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| 340 | CV_SH3_Gbr = 38,
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| 341 | CV_SH3_Pr = 39,
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| 342 | CV_SH3_Mach = 40,
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| 343 | CV_SH3_Macl = 41,
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| 344 | CV_SH3_Pc = 50,
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| 345 | CV_SH3_Sr = 51,
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| 346 | CV_SH3_BarA = 60,
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| 347 | CV_SH3_BasrA = 61,
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| 348 | CV_SH3_BamrA = 62,
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| 349 | CV_SH3_BbrA = 63,
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| 350 | CV_SH3_BarB = 64,
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| 351 | CV_SH3_BasrB = 65,
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| 352 | CV_SH3_BamrB = 66,
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| 353 | CV_SH3_BbrB = 67,
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| 354 | CV_SH3_BdrB = 68,
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| 355 | CV_SH3_BdmrB = 69,
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| 356 | CV_SH3_Brcr = 70,
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| 357 | CV_SH_Fpscr = 75,
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| 358 | CV_SH_Fpul = 76,
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| 359 | CV_SH_FpR0 = 80, /* this includes FpR1 to FpR15 */
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| 360 | CV_SH_XFpR0 = 96, /* this includes XFpR1 to XXFpR15 */
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| 361 |
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| 362 | /* ARM CPU */
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| 363 | CV_ARM_NOREG = CV_REG_NONE,
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| 364 | CV_ARM_R0 = 10, /* this includes R1 to R12 */
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| 365 | CV_ARM_SP = 23,
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| 366 | CV_ARM_LR = 24,
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| 367 | CV_ARM_PC = 25,
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| 368 | CV_ARM_CPSR = 26,
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| 369 |
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| 370 | /* Intel IA64 CPU */
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| 371 | CV_IA64_NOREG = CV_REG_NONE,
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| 372 | CV_IA64_Br0 = 512, /* this includes Br1 to Br7 */
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| 373 | CV_IA64_P0 = 704, /* this includes P1 to P63 */
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| 374 | CV_IA64_Preds = 768,
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| 375 | CV_IA64_IntH0 = 832, /* this includes H1 to H15 */
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| 376 | CV_IA64_Ip = 1016,
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| 377 | CV_IA64_Umask = 1017,
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| 378 | CV_IA64_Cfm = 1018,
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| 379 | CV_IA64_Psr = 1019,
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| 380 | CV_IA64_Nats = 1020,
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| 381 | CV_IA64_Nats2 = 1021,
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| 382 | CV_IA64_Nats3 = 1022,
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| 383 | CV_IA64_IntR0 = 1024, /* this includes R1 to R127 */
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| 384 | CV_IA64_FltF0 = 2048, /* this includes FltF1 to FltF127 */
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| 385 | /* some IA64 registers missing */
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| 386 |
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| 387 | /* TriCore CPU */
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| 388 | CV_TRI_NOREG = CV_REG_NONE,
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| 389 | CV_TRI_D0 = 10, /* includes D1 to D15 */
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| 390 | CV_TRI_A0 = 26, /* includes A1 to A15 */
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|---|
| 391 | CV_TRI_E0 = 42,
|
|---|
| 392 | CV_TRI_E2 = 43,
|
|---|
| 393 | CV_TRI_E4 = 44,
|
|---|
| 394 | CV_TRI_E6 = 45,
|
|---|
| 395 | CV_TRI_E8 = 46,
|
|---|
| 396 | CV_TRI_E10 = 47,
|
|---|
| 397 | CV_TRI_E12 = 48,
|
|---|
| 398 | CV_TRI_E14 = 49,
|
|---|
| 399 | CV_TRI_EA0 = 50,
|
|---|
| 400 | CV_TRI_EA2 = 51,
|
|---|
| 401 | CV_TRI_EA4 = 52,
|
|---|
| 402 | CV_TRI_EA6 = 53,
|
|---|
| 403 | CV_TRI_EA8 = 54,
|
|---|
| 404 | CV_TRI_EA10 = 55,
|
|---|
| 405 | CV_TRI_EA12 = 56,
|
|---|
| 406 | CV_TRI_EA14 = 57,
|
|---|
| 407 | /* some TriCode registers missing */
|
|---|
| 408 |
|
|---|
| 409 | /* AM33 (and the likes) CPU */
|
|---|
| 410 | CV_AM33_NOREG = CV_REG_NONE,
|
|---|
| 411 | CV_AM33_E0 = 10, /* this includes E1 to E7 */
|
|---|
| 412 | CV_AM33_A0 = 20, /* this includes A1 to A3 */
|
|---|
| 413 | CV_AM33_D0 = 30, /* this includes D1 to D3 */
|
|---|
| 414 | CV_AM33_FS0 = 40, /* this includes FS1 to FS31 */
|
|---|
| 415 |
|
|---|
| 416 | /* Mitsubishi M32R CPU */
|
|---|
| 417 | CV_M32R_NOREG = CV_REG_NONE,
|
|---|
| 418 | CV_M32R_R0 = 10, /* this includes R1 to R11 */
|
|---|
| 419 | CV_M32R_R12 = 22,
|
|---|
| 420 | CV_M32R_R13 = 23,
|
|---|
| 421 | CV_M32R_R14 = 24,
|
|---|
| 422 | CV_M32R_R15 = 25,
|
|---|
| 423 | CV_M32R_PSW = 26,
|
|---|
| 424 | CV_M32R_CBR = 27,
|
|---|
| 425 | CV_M32R_SPI = 28,
|
|---|
| 426 | CV_M32R_SPU = 29,
|
|---|
| 427 | CV_M32R_SPO = 30,
|
|---|
| 428 | CV_M32R_BPC = 31,
|
|---|
| 429 | CV_M32R_ACHI = 32,
|
|---|
| 430 | CV_M32R_ACLO = 33,
|
|---|
| 431 | CV_M32R_PC = 34,
|
|---|
| 432 |
|
|---|
| 433 | /* AMD/Intel x86_64 CPU */
|
|---|
| 434 | CV_AMD64_NONE = CV_REG_NONE,
|
|---|
| 435 | CV_AMD64_AL = CV_REG_AL,
|
|---|
| 436 | CV_AMD64_CL = CV_REG_CL,
|
|---|
| 437 | CV_AMD64_DL = CV_REG_DL,
|
|---|
| 438 | CV_AMD64_BL = CV_REG_BL,
|
|---|
| 439 | CV_AMD64_AH = CV_REG_AH,
|
|---|
| 440 | CV_AMD64_CH = CV_REG_CH,
|
|---|
| 441 | CV_AMD64_DH = CV_REG_DH,
|
|---|
| 442 | CV_AMD64_BH = CV_REG_BH,
|
|---|
| 443 | CV_AMD64_AX = CV_REG_AX,
|
|---|
| 444 | CV_AMD64_CX = CV_REG_CX,
|
|---|
| 445 | CV_AMD64_DX = CV_REG_DX,
|
|---|
| 446 | CV_AMD64_BX = CV_REG_BX,
|
|---|
| 447 | CV_AMD64_SP = CV_REG_SP,
|
|---|
| 448 | CV_AMD64_BP = CV_REG_BP,
|
|---|
| 449 | CV_AMD64_SI = CV_REG_SI,
|
|---|
| 450 | CV_AMD64_DI = CV_REG_DI,
|
|---|
| 451 | CV_AMD64_EAX = CV_REG_EAX,
|
|---|
| 452 | CV_AMD64_ECX = CV_REG_ECX,
|
|---|
| 453 | CV_AMD64_EDX = CV_REG_EDX,
|
|---|
| 454 | CV_AMD64_EBX = CV_REG_EBX,
|
|---|
| 455 | CV_AMD64_ESP = CV_REG_ESP,
|
|---|
| 456 | CV_AMD64_EBP = CV_REG_EBP,
|
|---|
| 457 | CV_AMD64_ESI = CV_REG_ESI,
|
|---|
| 458 | CV_AMD64_EDI = CV_REG_EDI,
|
|---|
| 459 | CV_AMD64_ES = CV_REG_ES,
|
|---|
| 460 | CV_AMD64_CS = CV_REG_CS,
|
|---|
| 461 | CV_AMD64_SS = CV_REG_SS,
|
|---|
| 462 | CV_AMD64_DS = CV_REG_DS,
|
|---|
| 463 | CV_AMD64_FS = CV_REG_FS,
|
|---|
| 464 | CV_AMD64_GS = CV_REG_GS,
|
|---|
| 465 | CV_AMD64_FLAGS = CV_REG_FLAGS,
|
|---|
| 466 | CV_AMD64_RIP = CV_REG_EIP,
|
|---|
| 467 | CV_AMD64_EFLAGS = CV_REG_EFLAGS,
|
|---|
| 468 |
|
|---|
| 469 | /* <pcode> */
|
|---|
| 470 | CV_AMD64_TEMP = CV_REG_TEMP,
|
|---|
| 471 | CV_AMD64_TEMPH = CV_REG_TEMPH,
|
|---|
| 472 | CV_AMD64_QUOTE = CV_REG_QUOTE,
|
|---|
| 473 | CV_AMD64_PCDR3 = CV_REG_PCDR3, /* this includes PCDR4 to PCDR7 */
|
|---|
| 474 | CV_AMD64_CR0 = CV_REG_CR0, /* this includes CR1 to CR4 */
|
|---|
| 475 | CV_AMD64_DR0 = CV_REG_DR0, /* this includes DR1 to DR7 */
|
|---|
| 476 | /* </pcode> */
|
|---|
| 477 |
|
|---|
| 478 | CV_AMD64_GDTR = CV_REG_GDTR,
|
|---|
| 479 | CV_AMD64_GDTL = CV_REG_GDTL,
|
|---|
| 480 | CV_AMD64_IDTR = CV_REG_IDTR,
|
|---|
| 481 | CV_AMD64_IDTL = CV_REG_IDTL,
|
|---|
| 482 | CV_AMD64_LDTR = CV_REG_LDTR,
|
|---|
| 483 | CV_AMD64_TR = CV_REG_TR,
|
|---|
| 484 |
|
|---|
| 485 | CV_AMD64_PSEUDO1 = CV_REG_PSEUDO1, /* this includes Pseudo02 to Pseudo09 */
|
|---|
| 486 | CV_AMD64_ST0 = CV_REG_ST0, /* this includes ST1 to ST7 */
|
|---|
| 487 | CV_AMD64_CTRL = CV_REG_CTRL,
|
|---|
| 488 | CV_AMD64_STAT = CV_REG_STAT,
|
|---|
| 489 | CV_AMD64_TAG = CV_REG_TAG,
|
|---|
| 490 | CV_AMD64_FPIP = CV_REG_FPIP,
|
|---|
| 491 | CV_AMD64_FPCS = CV_REG_FPCS,
|
|---|
| 492 | CV_AMD64_FPDO = CV_REG_FPDO,
|
|---|
| 493 | CV_AMD64_FPDS = CV_REG_FPDS,
|
|---|
| 494 | CV_AMD64_ISEM = CV_REG_ISEM,
|
|---|
| 495 | CV_AMD64_FPEIP = CV_REG_FPEIP,
|
|---|
| 496 | CV_AMD64_FPEDO = CV_REG_FPEDO,
|
|---|
| 497 | CV_AMD64_MM0 = CV_REG_MM0, /* this includes MM1 to MM7 */
|
|---|
| 498 | CV_AMD64_XMM0 = CV_REG_XMM0, /* this includes XMM1 to XMM7 */
|
|---|
| 499 | CV_AMD64_XMM00 = CV_REG_XMM00,
|
|---|
| 500 | CV_AMD64_XMM0L = CV_REG_XMM0L, /* this includes XMM1L to XMM7L */
|
|---|
| 501 | CV_AMD64_XMM0H = CV_REG_XMM0H, /* this includes XMM1H to XMM7H */
|
|---|
| 502 | CV_AMD64_MXCSR = CV_REG_MXCSR,
|
|---|
| 503 | CV_AMD64_EDXEAX = CV_REG_EDXEAX,
|
|---|
| 504 | CV_AMD64_EMM0L = CV_REG_EMM0L,
|
|---|
| 505 | CV_AMD64_EMM0H = CV_REG_EMM0H,
|
|---|
| 506 | CV_AMD64_MM00 = CV_REG_MM00,
|
|---|
| 507 | CV_AMD64_MM01 = CV_REG_MM01,
|
|---|
| 508 | CV_AMD64_MM10 = CV_REG_MM10,
|
|---|
| 509 | CV_AMD64_MM11 = CV_REG_MM11,
|
|---|
| 510 | CV_AMD64_MM20 = CV_REG_MM20,
|
|---|
| 511 | CV_AMD64_MM21 = CV_REG_MM21,
|
|---|
| 512 | CV_AMD64_MM30 = CV_REG_MM30,
|
|---|
| 513 | CV_AMD64_MM31 = CV_REG_MM31,
|
|---|
| 514 | CV_AMD64_MM40 = CV_REG_MM40,
|
|---|
| 515 | CV_AMD64_MM41 = CV_REG_MM41,
|
|---|
| 516 | CV_AMD64_MM50 = CV_REG_MM50,
|
|---|
| 517 | CV_AMD64_MM51 = CV_REG_MM51,
|
|---|
| 518 | CV_AMD64_MM60 = CV_REG_MM60,
|
|---|
| 519 | CV_AMD64_MM61 = CV_REG_MM61,
|
|---|
| 520 | CV_AMD64_MM70 = CV_REG_MM70,
|
|---|
| 521 | CV_AMD64_MM71 = CV_REG_MM71,
|
|---|
| 522 |
|
|---|
| 523 | CV_AMD64_XMM8 = 252, /* this includes XMM9 to XMM15 */
|
|---|
| 524 |
|
|---|
| 525 | CV_AMD64_RAX = 328,
|
|---|
| 526 | CV_AMD64_RBX = 329,
|
|---|
| 527 | CV_AMD64_RCX = 330,
|
|---|
| 528 | CV_AMD64_RDX = 331,
|
|---|
| 529 | CV_AMD64_RSI = 332,
|
|---|
| 530 | CV_AMD64_RDI = 333,
|
|---|
| 531 | CV_AMD64_RBP = 334,
|
|---|
| 532 | CV_AMD64_RSP = 335,
|
|---|
| 533 |
|
|---|
| 534 | CV_AMD64_R8 = 336,
|
|---|
| 535 | CV_AMD64_R9 = 337,
|
|---|
| 536 | CV_AMD64_R10 = 338,
|
|---|
| 537 | CV_AMD64_R11 = 339,
|
|---|
| 538 | CV_AMD64_R12 = 340,
|
|---|
| 539 | CV_AMD64_R13 = 341,
|
|---|
| 540 | CV_AMD64_R14 = 342,
|
|---|
| 541 | CV_AMD64_R15 = 343,
|
|---|
| 542 | };
|
|---|
| 543 |
|
|---|
| 544 | typedef enum
|
|---|
| 545 | {
|
|---|
| 546 | THUNK_ORDINAL_NOTYPE,
|
|---|
| 547 | THUNK_ORDINAL_ADJUSTOR,
|
|---|
| 548 | THUNK_ORDINAL_VCALL,
|
|---|
| 549 | THUNK_ORDINAL_PCODE,
|
|---|
| 550 | THUNK_ORDINAL_LOAD
|
|---|
| 551 | } THUNK_ORDINAL;
|
|---|
| 552 |
|
|---|
| 553 | typedef enum CV_call_e
|
|---|
| 554 | {
|
|---|
| 555 | CV_CALL_NEAR_C,
|
|---|
| 556 | CV_CALL_FAR_C,
|
|---|
| 557 | CV_CALL_NEAR_PASCAL,
|
|---|
| 558 | CV_CALL_FAR_PASCAL,
|
|---|
| 559 | CV_CALL_NEAR_FAST,
|
|---|
| 560 | CV_CALL_FAR_FAST,
|
|---|
| 561 | CV_CALL_SKIPPED,
|
|---|
| 562 | CV_CALL_NEAR_STD,
|
|---|
| 563 | CV_CALL_FAR_STD,
|
|---|
| 564 | CV_CALL_NEAR_SYS,
|
|---|
| 565 | CV_CALL_FAR_SYS,
|
|---|
| 566 | CV_CALL_THISCALL,
|
|---|
| 567 | CV_CALL_MIPSCALL,
|
|---|
| 568 | CV_CALL_GENERIC,
|
|---|
| 569 | CV_CALL_ALPHACALL,
|
|---|
| 570 | CV_CALL_PPCCALL,
|
|---|
| 571 | CV_CALL_RESERVED,
|
|---|
| 572 | } CV_call_e;
|
|---|
