drm.h@ 76553

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1	/* BEGIN CSTYLED */
2
3	/**
4	* \file drm.h
5	* Header for the Direct Rendering Manager
6	*
7	* \author Rickard E. (Rik) Faith <[email protected]>
8	*
9	* \par Acknowledgments:
10	* Dec 1999, Richard Henderson <[email protected]>, move to generic \c cmpxchg.
11	*/
12
13	/*
14	* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
15	* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
16	* All rights reserved.
17	*
18	* Permission is hereby granted, free of charge, to any person obtaining a
19	* copy of this software and associated documentation files (the "Software"),
20	* to deal in the Software without restriction, including without limitation
21	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
22	* and/or sell copies of the Software, and to permit persons to whom the
23	* Software is furnished to do so, subject to the following conditions:
24	*
25	* The above copyright notice and this permission notice (including the next
26	* paragraph) shall be included in all copies or substantial portions of the
27	* Software.
28	*
29	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
30	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
31	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
32	* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
33	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
34	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
35	* OTHER DEALINGS IN THE SOFTWARE.
36	*/
37
38	/**
39	* \mainpage
40	*
41	* The Direct Rendering Manager (DRM) is a device-independent kernel-level
42	* device driver that provides support for the XFree86 Direct Rendering
43	* Infrastructure (DRI).
44	*
45	* The DRM supports the Direct Rendering Infrastructure (DRI) in four major
46	* ways:
47	* -# The DRM provides synchronized access to the graphics hardware via
48	* the use of an optimized two-tiered lock.
49	* -# The DRM enforces the DRI security policy for access to the graphics
50	* hardware by only allowing authenticated X11 clients access to
51	* restricted regions of memory.
52	* -# The DRM provides a generic DMA engine, complete with multiple
53	* queues and the ability to detect the need for an OpenGL context
54	* switch.
55	* -# The DRM is extensible via the use of small device-specific modules
56	* that rely extensively on the API exported by the DRM module.
57	*
58	*/
59
60	/*
61	* Copyright 2009-2010 Oracle Corporation
62	* All rights reserved.
63	* Use is subject to license terms.
64	*/
65
66	#ifndef _DRM_H_
67	#define _DRM_H_
68
69	#include <sys/types32.h>
70
71	#ifndef __user
72	#define __user
73	#endif
74
75	#ifdef __GNUC__
76	# define DEPRECATED __attribute__ ((deprecated))
77	#else
78	# define DEPRECATED
79	# define __volatile__ volatile
80	#endif
81
82	#if defined(__linux__)
83	#include <asm/ioctl.h> /* For _IO* macros */
84	#define DRM_IOCTL_NR(n) _IOC_NR(n)
85	#define DRM_IOC_VOID _IOC_NONE
86	#define DRM_IOC_READ _IOC_READ
87	#define DRM_IOC_WRITE _IOC_WRITE
88	#define DRM_IOC_READWRITE _IOC_READ\|_IOC_WRITE
89	#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
90	#elif defined(__FreeBSD__) \|\| defined(__FreeBSD_kernel__) \|\| defined(__NetBSD__) \|\| defined(__OpenBSD__) \|\| defined(__DragonFly__)
91	#if (defined(__FreeBSD__) \|\| defined(__FreeBSD_kernel__)) && defined(IN_MODULE)
92	/* Prevent name collision when including sys/ioccom.h */
93	#undef ioctl
94	#include <sys/ioccom.h>
95	#define ioctl(a,b,c) xf86ioctl(a,b,c)
96	#else
97	#include <sys/ioccom.h>
98	#endif /* __FreeBSD__ && xf86ioctl */
99	#define DRM_IOCTL_NR(n) ((n) & 0xff)
100	#define DRM_IOC_VOID IOC_VOID
101	#define DRM_IOC_READ IOC_OUT
102	#define DRM_IOC_WRITE IOC_IN
103	#define DRM_IOC_READWRITE IOC_INOUT
104	#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
105	#endif
106
107	/* Solaris-specific. */
108	#if defined(__SOLARIS__) \|\| defined(sun)
109	#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
110
111	#define _IOC_NRBITS 8
112	#define _IOC_TYPEBITS 8
113	#define _IOC_SIZEBITS 14
114	#define _IOC_DIRBITS 2
115
116	#define _IOC_NRMASK ((1 << _IOC_NRBITS)-1)
117	#define _IOC_TYPEMASK ((1 << _IOC_TYPEBITS)-1)
118	#define _IOC_SIZEMASK ((1 << _IOC_SIZEBITS)-1)
119	#define _IOC_DIRMASK ((1 << _IOC_DIRBITS)-1)
120
121	#define _IOC_NRSHIFT 0
122	#define _IOC_TYPESHIFT (_IOC_NRSHIFT+_IOC_NRBITS)
123	#define _IOC_SIZESHIFT (_IOC_TYPESHIFT+_IOC_TYPEBITS)
124	#define _IOC_DIRSHIFT (_IOC_SIZESHIFT+_IOC_SIZEBITS)
125
126	#define _IOC_NONE 0U
127	#define _IOC_WRITE 1U
128	#define _IOC_READ 2U
129
130	#define _IOC(dir, type, nr, size) \
131	(((dir) << _IOC_DIRSHIFT) \| \
132	((type) << _IOC_TYPESHIFT) \| \
133	((nr) << _IOC_NRSHIFT) \| \
134	((size) << _IOC_SIZESHIFT))
135
136	/* used for X server compile */
137	#if !defined(_KERNEL)
138	#define _IO(type, nr) _IOC(_IOC_NONE, (type), (nr), 0)
139	#define _IOR(type, nr, size) _IOC(_IOC_READ, (type), (nr), sizeof (size))
140	#define _IOW(type, nr, size) _IOC(_IOC_WRITE, (type), (nr), sizeof (size))
141	#define _IOWR(type, nr, size) _IOC(_IOC_READ\|_IOC_WRITE, \
142	(type), (nr), sizeof (size))
143
144	#define _IOC_DIR(nr) (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
145	#define _IOC_TYPE(nr) (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
146	#define _IOC_NR(nr) (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
147	#define _IOC_SIZE(nr) (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
148
149	#define IOC_IN (_IOC_WRITE << _IOC_DIRSHIFT)
150	#define IOC_OUT (_IOC_READ << _IOC_DIRSHIFT)
151	#define IOC_INOUT ((_IOC_WRITE\|_IOC_READ) << _IOC_DIRSHIFT)
152	#define IOCSIZE_MASK (_IOC_SIZEMASK << _IOC_SIZESHIFT)
153	#define IOCSIZE_SHIFT (_IOC_SIZESHIFT)
154	#endif /* _KERNEL */
155
156	#define DRM_IOCTL_NR(n) _IOC_NR(n)
157	#define DRM_IOC_VOID IOC_VOID
158	#define DRM_IOC_READ IOC_OUT
159	#define DRM_IOC_WRITE IOC_IN
160	#define DRM_IOC_READWRITE IOC_INOUT
161	#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
162
163	#endif /* __Solaris__ or sun */
164	#define XFREE86_VERSION(major,minor,patch,snap) \
165	((major << 16) \| (minor << 8) \| patch)
166
167	#ifndef CONFIG_XFREE86_VERSION
168	#define CONFIG_XFREE86_VERSION XFREE86_VERSION(4,1,0,0)
169	#endif
170
171	#if CONFIG_XFREE86_VERSION < XFREE86_VERSION(4,1,0,0)
172	#define DRM_PROC_DEVICES "/proc/devices"
173	#define DRM_PROC_MISC "/proc/misc"
174	#define DRM_PROC_DRM "/proc/drm"
175	#define DRM_DEV_DRM "/dev/drm"
176	#define DRM_DEV_MODE (S_IRUSR\|S_IWUSR\|S_IRGRP\|S_IWGRP)
177	#define DRM_DEV_UID 0
178	#define DRM_DEV_GID 0
179	#endif
180
181	#if CONFIG_XFREE86_VERSION >= XFREE86_VERSION(4,1,0,0)
182	#ifdef __OpenBSD__
183	#define DRM_MAJOR 81
184	#endif
185	#if defined(__linux__) \|\| defined(__NetBSD__)
186	#define DRM_MAJOR 226
187	#endif
188	#define DRM_MAX_MINOR 15
189	#endif
190	#define DRM_NAME "drm" /*< Name in kernel, /dev, and /proc /
191	#define DRM_MIN_ORDER 5 /*< At least 2^5 bytes = 32 bytes /
192	#define DRM_MAX_ORDER 22 /*< Up to 2^22 bytes = 4MB /
193	#define DRM_RAM_PERCENT 10 /*< How much system ram can we lock? /
194
195	#define _DRM_LOCK_HELD 0x80000000U /*< Hardware lock is held /
196	#define _DRM_LOCK_CONT 0x40000000U /*< Hardware lock is contended /
197	#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
198	#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
199	#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD\|_DRM_LOCK_CONT))
200
201	#if defined(__linux__)
202	#if defined(__KERNEL__)
203	typedef __u64 drm_u64_t;
204	#else
205	typedef unsigned long long drm_u64_t;
206	#endif
207
208	typedef unsigned int drm_handle_t;
209	#else
210	#include <sys/types.h>
211	typedef uint64_t drm_u64_t;
212	typedef unsigned long long drm_handle_t; /*< To mapped regions /
213	#endif
214	typedef unsigned int drm_context_t; /*< GLXContext handle /
215	typedef unsigned int drm_drawable_t;
216	typedef unsigned int drm_magic_t; /*< Magic for authentication /
217
218	/**
219	* Cliprect.
220	*
221	* \warning If you change this structure, make sure you change
222	* XF86DRIClipRectRec in the server as well
223	*
224	* \note KW: Actually it's illegal to change either for
225	* backwards-compatibility reasons.
226	*/
227	typedef struct drm_clip_rect {
228	unsigned short x1;
229	unsigned short y1;
230	unsigned short x2;
231	unsigned short y2;
232	} drm_clip_rect_t;
233
234	/**
235	* Drawable information.
236	*/
237	typedef struct drm_drawable_info {
238	unsigned int num_rects;
239	drm_clip_rect_t *rects;
240	} drm_drawable_info_t;
241
242	/**
243	* Texture region,
244	*/
245	typedef struct drm_tex_region {
246	unsigned char next;
247	unsigned char prev;
248	unsigned char in_use;
249	unsigned char padding;
250	unsigned int age;
251	} drm_tex_region_t;
252
253	/**
254	* Hardware lock.
255	*
256	* The lock structure is a simple cache-line aligned integer. To avoid
257	* processor bus contention on a multiprocessor system, there should not be any
258	* other data stored in the same cache line.
259	*/
260	typedef struct drm_hw_lock {
261	__volatile__ unsigned int lock; /*< lock variable /
262	char padding[60]; /*< Pad to cache line /
263	} drm_hw_lock_t;
264
265	/* This is beyond ugly, and only works on GCC. However, it allows me to use
266	* drm.h in places (i.e., in the X-server) where I can't use size_t. The real
267	* fix is to use uint32_t instead of size_t, but that fix will break existing
268	* LP64 (i.e., PowerPC64, SPARC64, IA-64, Alpha, etc.) systems. That will
269	* eventually happen, though. I chose 'unsigned long' to be the fallback type
270	* because that works on all the platforms I know about. Hopefully, the
271	* real fix will happen before that bites us.
272	*/
273
274	#ifdef __SIZE_TYPE__
275	# define DRM_SIZE_T __SIZE_TYPE__
276	#else
277	#if !defined(__SOLARIS__) && !defined(sun)
278	# warning "__SIZE_TYPE__ not defined. Assuming sizeof(size_t) == sizeof(unsigned long)!"
279	#endif
280	# define DRM_SIZE_T unsigned long
281	#endif
282
283	/**
284	* DRM_IOCTL_VERSION ioctl argument type.
285	*
286	* \sa drmGetVersion().
287	*/
288	typedef struct drm_version {
289	int version_major; /*< Major version /
290	int version_minor; /*< Minor version /
291	int version_patchlevel; /*< Patch level /
292	DRM_SIZE_T name_len; /*< Length of name buffer /
293	char __user name; /< Name of driver /
294	DRM_SIZE_T date_len; /*< Length of date buffer /
295	char __user date; /< User-space buffer to hold date /
296	DRM_SIZE_T desc_len; /*< Length of desc buffer /
297	char __user desc; /< User-space buffer to hold desc /
298	} drm_version_t;
299
300	/**
301	* DRM_IOCTL_GET_UNIQUE ioctl argument type.
302	*
303	* \sa drmGetBusid() and drmSetBusId().
304	*/
305	typedef struct drm_unique {
306	DRM_SIZE_T unique_len; /*< Length of unique /
307	char __user unique; /< Unique name for driver instantiation /
308	} drm_unique_t;
309
310	#undef DRM_SIZE_T
311
312	typedef struct drm_list {
313	int count; /*< Length of user-space structures /
314	drm_version_t __user *version;
315	} drm_list_t;
316
317	typedef struct drm_block {
318	int unused;
319	} drm_block_t;
320
321	/**
322	* DRM_IOCTL_CONTROL ioctl argument type.
323	*
324	* \sa drmCtlInstHandler() and drmCtlUninstHandler().
325	*/
326	typedef struct drm_control {
327	enum {
328	DRM_ADD_COMMAND,
329	DRM_RM_COMMAND,
330	DRM_INST_HANDLER,
331	DRM_UNINST_HANDLER
332	} func;
333	int irq;
334	} drm_control_t;
335
336	/**
337	* Type of memory to map.
338	*/
339	typedef enum drm_map_type {
340	_DRM_FRAME_BUFFER = 0, /*< WC (no caching), no core dump /
341	_DRM_REGISTERS = 1, /*< no caching, no core dump /
342	_DRM_SHM = 2, /*< shared, cached /
343	_DRM_AGP = 3, /*< AGP/GART /
344	_DRM_SCATTER_GATHER = 4, /*< Scatter/gather memory for PCI DMA /
345	_DRM_CONSISTENT = 5, /*< Consistent memory for PCI DMA /
346	_DRM_TTM = 6
347	} drm_map_type_t;
348
349	/**
350	* Memory mapping flags.
351	*/
352	typedef enum drm_map_flags {
353	_DRM_RESTRICTED = 0x01, /*< Cannot be mapped to user-virtual /
354	_DRM_READ_ONLY = 0x02,
355	_DRM_LOCKED = 0x04, /*< shared, cached, locked /
356	_DRM_KERNEL = 0x08, /*< kernel requires access /
357	_DRM_WRITE_COMBINING = 0x10, /*< use write-combining if available /
358	_DRM_CONTAINS_LOCK = 0x20, /*< SHM page that contains lock /
359	_DRM_REMOVABLE = 0x40, /*< Removable mapping /
360	_DRM_DRIVER = 0x80 /*< Managed by driver /
361	} drm_map_flags_t;
362
363	typedef struct drm_ctx_priv_map {
364	unsigned int ctx_id; /*< Context requesting private mapping /
365	void handle; /< Handle of map /
366	} drm_ctx_priv_map_t;
367
368	/**
369	* DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
370	* argument type.
371	*
372	* \sa drmAddMap().
373	*/
374	typedef struct drm_map {
375	unsigned long long offset; /*< Requested physical address (0 for SAREA)/
376	unsigned long long handle;
377	/*< User-space: "Handle" to pass to mmap() /
378	/*< Kernel-space: kernel-virtual address /
379	unsigned long size; /*< Requested physical size (bytes) /
380	drm_map_type_t type; /*< Type of memory to map /
381	drm_map_flags_t flags; /*< Flags /
382	int mtrr; /*< MTRR slot used /
383	/* Private data */
384	} drm_map_t;
385
386	/**
387	* DRM_IOCTL_GET_CLIENT ioctl argument type.
388	*/
389	typedef struct drm_client {
390	int idx; /*< Which client desired? /
391	int auth; /*< Is client authenticated? /
392	unsigned long pid; /*< Process ID /
393	unsigned long uid; /*< User ID /
394	unsigned long magic; /*< Magic /
395	unsigned long iocs; /*< Ioctl count /
396	} drm_client_t;
397
398	typedef enum {
399	_DRM_STAT_LOCK,
400	_DRM_STAT_OPENS,
401	_DRM_STAT_CLOSES,
402	_DRM_STAT_IOCTLS,
403	_DRM_STAT_LOCKS,
404	_DRM_STAT_UNLOCKS,
405	_DRM_STAT_VALUE, /*< Generic value /
406	_DRM_STAT_BYTE, /*< Generic byte counter (1024bytes/K) /
407	_DRM_STAT_COUNT, /*< Generic non-byte counter (1000/k) /
408
409	_DRM_STAT_IRQ, /*< IRQ /
410	_DRM_STAT_PRIMARY, /*< Primary DMA bytes /
411	_DRM_STAT_SECONDARY, /*< Secondary DMA bytes /
412	_DRM_STAT_DMA, /*< DMA /
413	_DRM_STAT_SPECIAL, /*< Special DMA (e.g., priority or polled) /
414	_DRM_STAT_MISSED /*< Missed DMA opportunity /
415	/* Add to the END of the list */
416	} drm_stat_type_t;
417
418	/**
419	* DRM_IOCTL_GET_STATS ioctl argument type.
420	*/
421	typedef struct drm_stats {
422	unsigned long count;
423	struct {
424	unsigned long value;
425	drm_stat_type_t type;
426	} data[15];
427	} drm_stats_t;
428
429	/**
430	* Hardware locking flags.
431	*/
432	typedef enum drm_lock_flags {
433	_DRM_LOCK_READY = 0x01, /*< Wait until hardware is ready for DMA /
434	_DRM_LOCK_QUIESCENT = 0x02, /*< Wait until hardware quiescent /
435	_DRM_LOCK_FLUSH = 0x04, /*< Flush this context's DMA queue first /
436	_DRM_LOCK_FLUSH_ALL = 0x08, /*< Flush all DMA queues first /
437	/* These HALT flags aren't supported yet
438	-- they will be used to support the
439	full-screen DGA-like mode. */
440	_DRM_HALT_ALL_QUEUES = 0x10, /*< Halt all current and future queues /
441	_DRM_HALT_CUR_QUEUES = 0x20 /*< Halt all current queues /
442	} drm_lock_flags_t;
443
444	/**
445	* DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
446	*
447	* \sa drmGetLock() and drmUnlock().
448	*/
449	typedef struct drm_lock {
450	int context;
451	drm_lock_flags_t flags;
452	} drm_lock_t;
453
454	/**
455	* DMA flags
456	*
457	* \warning
458	* These values \e must match xf86drm.h.
459	*
460	* \sa drm_dma.
461	*/
462	typedef enum drm_dma_flags {
463	/* Flags for DMA buffer dispatch */
464	_DRM_DMA_BLOCK = 0x01, /**<
465	* Block until buffer dispatched.
466	*
467	* \note The buffer may not yet have
468	* been processed by the hardware --
469	* getting a hardware lock with the
470	* hardware quiescent will ensure
471	* that the buffer has been
472	* processed.
473	*/
474	_DRM_DMA_WHILE_LOCKED = 0x02, /*< Dispatch while lock held /
475	_DRM_DMA_PRIORITY = 0x04, /*< High priority dispatch /
476
477	/* Flags for DMA buffer request */
478	_DRM_DMA_WAIT = 0x10, /*< Wait for free buffers /
479	_DRM_DMA_SMALLER_OK = 0x20, /*< Smaller-than-requested buffers OK /
480	_DRM_DMA_LARGER_OK = 0x40 /*< Larger-than-requested buffers OK /
481	} drm_dma_flags_t;
482
483	/**
484	* DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
485	*
486	* \sa drmAddBufs().
487	*/
488	typedef enum {
489	_DRM_PAGE_ALIGN = 0x01, /*< Align on page boundaries for DMA /
490	_DRM_AGP_BUFFER = 0x02, /*< Buffer is in AGP space /
491	_DRM_SG_BUFFER = 0x04, /*< Scatter/gather memory buffer /
492	_DRM_FB_BUFFER = 0x08, /*< Buffer is in frame buffer /
493	_DRM_PCI_BUFFER_RO = 0x10 /*< Map PCI DMA buffer read-only /
494	} drm_buf_flag;
495	typedef struct drm_buf_desc {
496	int count; /*< Number of buffers of this size /
497	int size; /*< Size in bytes /
498	int low_mark; /*< Low water mark /
499	int high_mark; /*< High water mark /
500	drm_buf_flag flags;
501	unsigned long agp_start; /**<
502	* Start address of where the AGP buffers are
503	* in the AGP aperture
504	*/
505	} drm_buf_desc_t;
506
507	/**
508	* DRM_IOCTL_INFO_BUFS ioctl argument type.
509	*/
510	typedef struct drm_buf_info {
511	int count; /*< Number of buffers described in list /
512	drm_buf_desc_t __user list; /< List of buffer descriptions /
513	} drm_buf_info_t;
514
515	/**
516	* DRM_IOCTL_FREE_BUFS ioctl argument type.
517	*/
518	typedef struct drm_buf_free {
519	int count;
520	int __user *list;
521	} drm_buf_free_t;
522
523	/**
524	* Buffer information
525	*
526	* \sa drm_buf_map.
527	*/
528	typedef struct drm_buf_pub {
529	int idx; /*< Index into the master buffer list /
530	int total; /*< Buffer size /
531	int used; /*< Amount of buffer in use (for DMA) /
532	void __user address; /< Address of buffer /
533	} drm_buf_pub_t;
534
535	/**
536	* DRM_IOCTL_MAP_BUFS ioctl argument type.
537	*/
538	typedef struct drm_buf_map {
539	int count; /*< Length of the buffer list /
540	#if defined(__cplusplus)
541	void __user *c_virtual;
542	#else
543	void __user virtual; /< Mmap'd area in user-virtual /
544	#endif
545	drm_buf_pub_t __user list; /< Buffer information /
546	int fd;
547	} drm_buf_map_t;
548
549	/**
550	* DRM_IOCTL_DMA ioctl argument type.
551	*
552	* Indices here refer to the offset into the buffer list in drm_buf_get.
553	*
554	* \sa drmDMA().
555	*/
556	typedef struct drm_dma {
557	int context; /*< Context handle /
558	int send_count; /*< Number of buffers to send /
559	int __user send_indices; /< List of handles to buffers /
560	int __user send_sizes; /< Lengths of data to send /
561	drm_dma_flags_t flags; /*< Flags /
562	int request_count; /*< Number of buffers requested /
563	int request_size; /*< Desired size for buffers /
564	int __user request_indices; /< Buffer information /
565	int __user *request_sizes;
566	int granted_count; /*< Number of buffers granted /
567	} drm_dma_t;
568
569	typedef enum {
570	_DRM_CONTEXT_PRESERVED = 0x01,
571	_DRM_CONTEXT_2DONLY = 0x02
572	} drm_ctx_flags_t;
573
574	/**
575	* DRM_IOCTL_ADD_CTX ioctl argument type.
576	*
577	* \sa drmCreateContext() and drmDestroyContext().
578	*/
579	typedef struct drm_ctx {
580	drm_context_t handle;
581	drm_ctx_flags_t flags;
582	} drm_ctx_t;
583
584	/**
585	* DRM_IOCTL_RES_CTX ioctl argument type.
586	*/
587	typedef struct drm_ctx_res {
588	int count;
589	drm_ctx_t __user *contexts;
590	} drm_ctx_res_t;
591
592
593	/**
594	* DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
595	*/
596	typedef struct drm_draw {
597	drm_drawable_t handle;
598	} drm_draw_t;
599
600	/**
601	* DRM_IOCTL_UPDATE_DRAW ioctl argument type.
602	*/
603	typedef enum {
604	DRM_DRAWABLE_CLIPRECTS,
605	} drm_drawable_info_type_t;
606
607	typedef struct drm_update_draw {
608	drm_drawable_t handle;
609	unsigned int type;
610	unsigned int num;
611	unsigned long long data;
612	} drm_update_draw_t;
613
614	/**
615	* DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
616	*/
617	typedef struct drm_auth {
618	drm_magic_t magic;
619	} drm_auth_t;
620
621	/**
622	* DRM_IOCTL_IRQ_BUSID ioctl argument type.
623	*
624	* \sa drmGetInterruptFromBusID().
625	*/
626	typedef struct drm_irq_busid {
627	int irq; /*< IRQ number /
628	int busnum; /*< bus number /
629	int devnum; /*< device number /
630	int funcnum; /*< function number /
631	} drm_irq_busid_t;
632
633	typedef enum {
634	_DRM_VBLANK_ABSOLUTE = 0x0, /*< Wait for specific vblank sequence number /
635	_DRM_VBLANK_RELATIVE = 0x1, /*< Wait for given number of vblanks /
636	_DRM_VBLANK_FLIP = 0x8000000, /*< Scheduled buffer swap should flip /
637	_DRM_VBLANK_NEXTONMISS = 0x10000000, /*< If missed, wait for next vblank /
638	_DRM_VBLANK_SECONDARY = 0x20000000, /*< Secondary display controller /
639	_DRM_VBLANK_SIGNAL = 0x40000000 /*< Send signal instead of blocking /
640	} drm_vblank_seq_type_t;
641
642	#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE \| _DRM_VBLANK_RELATIVE)
643	#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_SIGNAL \| _DRM_VBLANK_SECONDARY \| \
644	_DRM_VBLANK_NEXTONMISS)
645
646	struct drm_wait_vblank_request {
647	drm_vblank_seq_type_t type;
648	unsigned int sequence;
649	unsigned long signal;
650	};
651
652	struct drm_wait_vblank_reply {
653	drm_vblank_seq_type_t type;
654	unsigned int sequence;
655	long tval_sec;
656	long tval_usec;
657	};
658
659	/**
660	* DRM_IOCTL_WAIT_VBLANK ioctl argument type.
661	*
662	* \sa drmWaitVBlank().
663	*/
664	typedef union drm_wait_vblank {
665	struct drm_wait_vblank_request request;
666	struct drm_wait_vblank_reply reply;
667	} drm_wait_vblank_t;
668
669	/**
670	* DRM_IOCTL_AGP_ENABLE ioctl argument type.
671	*
672	* \sa drmAgpEnable().
673	*/
674	typedef struct drm_agp_mode {
675	unsigned long mode; /*< AGP mode /
676	} drm_agp_mode_t;
677
678	/**
679	* DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
680	*
681	* \sa drmAgpAlloc() and drmAgpFree().
682	*/
683	typedef struct drm_agp_buffer {
684	unsigned long size; /*< In bytes -- will round to page boundary /
685	unsigned long handle; /*< Used for binding / unbinding /
686	unsigned long type; /*< Type of memory to allocate /
687	unsigned long physical; /*< Physical used by i810 /
688	} drm_agp_buffer_t;
689
690	/**
691	* DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
692	*
693	* \sa drmAgpBind() and drmAgpUnbind().
694	*/
695	typedef struct drm_agp_binding {
696	unsigned long handle; /*< From drm_agp_buffer /
697	unsigned long offset; /*< In bytes -- will round to page boundary /
698	} drm_agp_binding_t;
699
700	/**
701	* DRM_IOCTL_AGP_INFO ioctl argument type.
702	*
703	* \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
704	* drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
705	* drmAgpVendorId() and drmAgpDeviceId().
706	*/
707	typedef struct drm_agp_info {
708	int agp_version_major;
709	int agp_version_minor;
710	unsigned long mode;
711	unsigned long aperture_base; /*< physical address /
712	unsigned long aperture_size; /*< bytes /
713	unsigned long memory_allowed; /*< bytes /
714	unsigned long memory_used;
715
716	/** \name PCI information */
717	/@{ /
718	unsigned short id_vendor;
719	unsigned short id_device;
720	/@} /
721	} drm_agp_info_t;
722
723	/**
724	* DRM_IOCTL_SG_ALLOC ioctl argument type.
725	*/
726	typedef struct drm_scatter_gather {
727	unsigned long size; /*< In bytes -- will round to page boundary /
728	unsigned long handle; /*< Used for mapping / unmapping /
729	} drm_scatter_gather_t;
730
731	/**
732	* DRM_IOCTL_SET_VERSION ioctl argument type.
733	*/
734	typedef struct drm_set_version {
735	int drm_di_major;
736	int drm_di_minor;
737	int drm_dd_major;
738	int drm_dd_minor;
739	} drm_set_version_t;
740
741	/**
742	* \name Ioctls Definitions
743	*/
744	/@{/
745
746	#define DRM_IOCTL_BASE 'd'
747	#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
748	#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
749	#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
750	#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
751
752	#define DRM_IOCTL_VERSION DRM_IOWR(0x00, drm_version_t)
753	#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, drm_unique_t)
754	#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, drm_auth_t)
755	#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, drm_irq_busid_t)
756	#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, drm_map_t)
757	#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, drm_client_t)
758	#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, drm_stats_t)
759	#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, drm_set_version_t)
760
761	#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, drm_unique_t)
762	#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, drm_auth_t)
763	#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, drm_block_t)
764	#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, drm_block_t)
765	#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, drm_control_t)
766	#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, drm_map_t)
767	#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, drm_buf_desc_t)
768	#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, drm_buf_desc_t)
769	#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, drm_buf_info_t)
770	#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, drm_buf_map_t)
771	#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, drm_buf_free_t)
772
773	#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, drm_map_t)
774
775	#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, drm_ctx_priv_map_t)
776	#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, drm_ctx_priv_map_t)
777
778	#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, drm_ctx_t)
779	#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, drm_ctx_t)
780	#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, drm_ctx_t)
781	#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, drm_ctx_t)
782	#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, drm_ctx_t)
783	#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, drm_ctx_t)
784	#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, drm_ctx_res_t)
785	#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, drm_draw_t)
786	#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, drm_draw_t)
787	#define DRM_IOCTL_DMA DRM_IOWR(0x29, drm_dma_t)
788	#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, drm_lock_t)
789	#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, drm_lock_t)
790	#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, drm_lock_t)
791
792	#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
793	#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
794	#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, drm_agp_mode_t)
795	#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, drm_agp_info_t)
796	#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, drm_agp_buffer_t)
797	#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, drm_agp_buffer_t)
798	#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, drm_agp_binding_t)
799	#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, drm_agp_binding_t)
800
801	#define DRM_IOCTL_SG_ALLOC DRM_IOW( 0x38, drm_scatter_gather_t)
802	#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, drm_scatter_gather_t)
803
804	#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, drm_wait_vblank_t)
805
806	#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, drm_update_draw_t)
807	/@}/
808
809	/**
810	* Device specific ioctls should only be in their respective headers
811	* The device specific ioctl range is from 0x40 to 0x99.
812	* Generic IOCTLS restart at 0xA0.
813	*
814	* \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
815	* drmCommandReadWrite().
816	*/
817	#define DRM_COMMAND_BASE 0x40
818	#define DRM_COMMAND_END 0xA0
819
820	#endif /* _DRM_H_ */

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source: vbox/trunk/src/VBox/Additions/solaris/DRM/include/drm.h@ 76553

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