VirtualBox

source: vbox/trunk/src/VBox/Additions/x11/x11include/7.0/xorg/xf86Pci.h@ 6202

Last change on this file since 6202 was 6202, checked in by vboxsync, 17 years ago

re-export x11
  • Property svn:eol-style set to native
File size: 27.9 KB
Line 
1/* $XFree86: xc/programs/Xserver/hw/xfree86/os-support/bus/xf86Pci.h,v 1.39 2003/08/24 17:37:05 dawes Exp $ */
2/*
3 * Copyright 1998 by Concurrent Computer Corporation
4 *
5 * Permission to use, copy, modify, distribute, and sell this software
6 * and its documentation for any purpose is hereby granted without fee,
7 * provided that the above copyright notice appear in all copies and that
8 * both that copyright notice and this permission notice appear in
9 * supporting documentation, and that the name of Concurrent Computer
10 * Corporation not be used in advertising or publicity pertaining to
11 * distribution of the software without specific, written prior
12 * permission. Concurrent Computer Corporation makes no representations
13 * about the suitability of this software for any purpose. It is
14 * provided "as is" without express or implied warranty.
15 *
16 * CONCURRENT COMPUTER CORPORATION DISCLAIMS ALL WARRANTIES WITH REGARD
17 * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
18 * AND FITNESS, IN NO EVENT SHALL CONCURRENT COMPUTER CORPORATION BE
19 * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
20 * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
21 * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
22 * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
23 * SOFTWARE.
24 *
25 * Copyright 1998 by Metro Link Incorporated
26 *
27 * Permission to use, copy, modify, distribute, and sell this software
28 * and its documentation for any purpose is hereby granted without fee,
29 * provided that the above copyright notice appear in all copies and that
30 * both that copyright notice and this permission notice appear in
31 * supporting documentation, and that the name of Metro Link
32 * Incorporated not be used in advertising or publicity pertaining to
33 * distribution of the software without specific, written prior
34 * permission. Metro Link Incorporated makes no representations
35 * about the suitability of this software for any purpose. It is
36 * provided "as is" without express or implied warranty.
37 *
38 * METRO LINK INCORPORATED DISCLAIMS ALL WARRANTIES WITH REGARD
39 * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
40 * AND FITNESS, IN NO EVENT SHALL METRO LINK INCORPORATED BE
41 * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
42 * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS,
43 * WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,
44 * ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS
45 * SOFTWARE.
46 *
47 * This file is derived in part from the original xf86_PCI.h that included
48 * following copyright message:
49 *
50 * Copyright 1995 by Robin Cutshaw <[email protected]>
51 *
52 * Permission to use, copy, modify, distribute, and sell this software and its
53 * documentation for any purpose is hereby granted without fee, provided that
54 * the above copyright notice appear in all copies and that both that
55 * copyright notice and this permission notice appear in supporting
56 * documentation, and that the names of the above listed copyright holder(s)
57 * not be used in advertising or publicity pertaining to distribution of
58 * the software without specific, written prior permission. The above listed
59 * copyright holder(s) make(s) no representations about the suitability of this
60 * software for any purpose. It is provided "as is" without express or
61 * implied warranty.
62 *
63 * THE ABOVE LISTED COPYRIGHT HOLDER(S) DISCLAIM(S) ALL WARRANTIES WITH REGARD
64 * TO THIS SOFTWARE, INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
65 * AND FITNESS, IN NO EVENT SHALL THE ABOVE LISTED COPYRIGHT HOLDER(S) BE
66 * LIABLE FOR ANY SPECIAL, INDIRECT OR CONSEQUENTIAL DAMAGES OR ANY
67 * DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER
68 * IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING
69 * OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
70 *
71 */
72/*
73 * Copyright (c) 1999-2003 by The XFree86 Project, Inc.
74 *
75 * Permission is hereby granted, free of charge, to any person obtaining a
76 * copy of this software and associated documentation files (the "Software"),
77 * to deal in the Software without restriction, including without limitation
78 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
79 * and/or sell copies of the Software, and to permit persons to whom the
80 * Software is furnished to do so, subject to the following conditions:
81 *
82 * The above copyright notice and this permission notice shall be included in
83 * all copies or substantial portions of the Software.
84 *
85 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
86 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
87 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
88 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
89 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
90 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
91 * OTHER DEALINGS IN THE SOFTWARE.
92 *
93 * Except as contained in this notice, the name of the copyright holder(s)
94 * and author(s) shall not be used in advertising or otherwise to promote
95 * the sale, use or other dealings in this Software without prior written
96 * authorization from the copyright holder(s) and author(s).
97 */
98
99
100/*
101 * This file contains just the public interface to the PCI code.
102 * Drivers should use this file rather than Pci.h.
103 */
104
105#ifndef _XF86PCI_H
106#define _XF86PCI_H 1
107#include <X11/Xarch.h>
108#include <X11/Xfuncproto.h>
109#include "misc.h"
110
111#define PCI_NOT_FOUND 0xFFFFFFFFU
112
113/*
114 * PCI cfg space definitions (e.g. stuff right out of the PCI spec)
115 */
116
117/* Device identification register */
118#define PCI_ID_REG 0x00
119
120/* Command and status register */
121#define PCI_CMD_STAT_REG 0x04
122#define PCI_CMD_BASE_REG 0x10
123#define PCI_CMD_BIOS_REG 0x30
124#define PCI_CMD_MASK 0xffff
125#define PCI_CMD_IO_ENABLE 0x01
126#define PCI_CMD_MEM_ENABLE 0x02
127#define PCI_CMD_MASTER_ENABLE 0x04
128#define PCI_CMD_SPECIAL_ENABLE 0x08
129#define PCI_CMD_INVALIDATE_ENABLE 0x10
130#define PCI_CMD_PALETTE_ENABLE 0x20
131#define PCI_CMD_PARITY_ENABLE 0x40
132#define PCI_CMD_STEPPING_ENABLE 0x80
133#define PCI_CMD_SERR_ENABLE 0x100
134#define PCI_CMD_BACKTOBACK_ENABLE 0x200
135#define PCI_CMD_BIOS_ENABLE 0x01
136
137/* base class */
138#define PCI_CLASS_REG 0x08
139#define PCI_CLASS_MASK 0xff000000
140#define PCI_CLASS_SHIFT 24
141#define PCI_CLASS_EXTRACT(x) \
142 (((x) & PCI_CLASS_MASK) >> PCI_CLASS_SHIFT)
143
144/* base class values */
145#define PCI_CLASS_PREHISTORIC 0x00
146#define PCI_CLASS_MASS_STORAGE 0x01
147#define PCI_CLASS_NETWORK 0x02
148#define PCI_CLASS_DISPLAY 0x03
149#define PCI_CLASS_MULTIMEDIA 0x04
150#define PCI_CLASS_MEMORY 0x05
151#define PCI_CLASS_BRIDGE 0x06
152#define PCI_CLASS_COMMUNICATIONS 0x07
153#define PCI_CLASS_SYSPERIPH 0x08
154#define PCI_CLASS_INPUT 0x09
155#define PCI_CLASS_DOCKING 0x0a
156#define PCI_CLASS_PROCESSOR 0x0b
157#define PCI_CLASS_SERIALBUS 0x0c
158#define PCI_CLASS_WIRELESS 0x0d
159#define PCI_CLASS_I2O 0x0e
160#define PCI_CLASS_SATELLITE 0x0f
161#define PCI_CLASS_CRYPT 0x10
162#define PCI_CLASS_DATA_ACQUISTION 0x11
163#define PCI_CLASS_UNDEFINED 0xff
164
165/* sub class */
166#define PCI_SUBCLASS_MASK 0x00ff0000
167#define PCI_SUBCLASS_SHIFT 16
168#define PCI_SUBCLASS_EXTRACT(x) \
169 (((x) & PCI_SUBCLASS_MASK) >> PCI_SUBCLASS_SHIFT)
170
171/* Sub class values */
172/* 0x00 prehistoric subclasses */
173#define PCI_SUBCLASS_PREHISTORIC_MISC 0x00
174#define PCI_SUBCLASS_PREHISTORIC_VGA 0x01
175
176/* 0x01 mass storage subclasses */
177#define PCI_SUBCLASS_MASS_STORAGE_SCSI 0x00
178#define PCI_SUBCLASS_MASS_STORAGE_IDE 0x01
179#define PCI_SUBCLASS_MASS_STORAGE_FLOPPY 0x02
180#define PCI_SUBCLASS_MASS_STORAGE_IPI 0x03
181#define PCI_SUBCLASS_MASS_STORAGE_MISC 0x80
182
183/* 0x02 network subclasses */
184#define PCI_SUBCLASS_NETWORK_ETHERNET 0x00
185#define PCI_SUBCLASS_NETWORK_TOKENRING 0x01
186#define PCI_SUBCLASS_NETWORK_FDDI 0x02
187#define PCI_SUBCLASS_NETWORK_MISC 0x80
188
189/* 0x03 display subclasses */
190#define PCI_SUBCLASS_DISPLAY_VGA 0x00
191#define PCI_SUBCLASS_DISPLAY_XGA 0x01
192#define PCI_SUBCLASS_DISPLAY_MISC 0x80
193
194/* 0x04 multimedia subclasses */
195#define PCI_SUBCLASS_MULTIMEDIA_VIDEO 0x00
196#define PCI_SUBCLASS_MULTIMEDIA_AUDIO 0x01
197#define PCI_SUBCLASS_MULTIMEDIA_MISC 0x80
198
199/* 0x05 memory subclasses */
200#define PCI_SUBCLASS_MEMORY_RAM 0x00
201#define PCI_SUBCLASS_MEMORY_FLASH 0x01
202#define PCI_SUBCLASS_MEMORY_MISC 0x80
203
204/* 0x06 bridge subclasses */
205#define PCI_SUBCLASS_BRIDGE_HOST 0x00
206#define PCI_SUBCLASS_BRIDGE_ISA 0x01
207#define PCI_SUBCLASS_BRIDGE_EISA 0x02
208#define PCI_SUBCLASS_BRIDGE_MC 0x03
209#define PCI_SUBCLASS_BRIDGE_PCI 0x04
210#define PCI_SUBCLASS_BRIDGE_PCMCIA 0x05
211#define PCI_SUBCLASS_BRIDGE_NUBUS 0x06
212#define PCI_SUBCLASS_BRIDGE_CARDBUS 0x07
213#define PCI_SUBCLASS_BRIDGE_RACEWAY 0x08
214#define PCI_SUBCLASS_BRIDGE_MISC 0x80
215#define PCI_IF_BRIDGE_PCI_SUBTRACTIVE 0x01
216
217/* 0x07 communications controller subclasses */
218#define PCI_SUBCLASS_COMMUNICATIONS_SERIAL 0x00
219#define PCI_SUBCLASS_COMMUNICATIONS_PARALLEL 0x01
220#define PCI_SUBCLASS_COMMUNICATIONS_MULTISERIAL 0x02
221#define PCI_SUBCLASS_COMMUNICATIONS_MODEM 0x03
222#define PCI_SUBCLASS_COMMUNICATIONS_MISC 0x80
223
224/* 0x08 generic system peripherals subclasses */
225#define PCI_SUBCLASS_SYSPERIPH_PIC 0x00
226#define PCI_SUBCLASS_SYSPERIPH_DMA 0x01
227#define PCI_SUBCLASS_SYSPERIPH_TIMER 0x02
228#define PCI_SUBCLASS_SYSPERIPH_RTC 0x03
229#define PCI_SUBCLASS_SYSPERIPH_HOTPCI 0x04
230#define PCI_SUBCLASS_SYSPERIPH_MISC 0x80
231
232/* 0x09 input device subclasses */
233#define PCI_SUBCLASS_INPUT_KEYBOARD 0x00
234#define PCI_SUBCLASS_INPUT_DIGITIZER 0x01
235#define PCI_SUBCLASS_INPUT_MOUSE 0x02
236#define PCI_SUBCLASS_INPUT_SCANNER 0x03
237#define PCI_SUBCLASS_INPUT_GAMEPORT 0x04
238#define PCI_SUBCLASS_INPUT_MISC 0x80
239
240/* 0x0a docking station subclasses */
241#define PCI_SUBCLASS_DOCKING_GENERIC 0x00
242#define PCI_SUBCLASS_DOCKING_MISC 0x80
243
244/* 0x0b processor subclasses */
245#define PCI_SUBCLASS_PROCESSOR_386 0x00
246#define PCI_SUBCLASS_PROCESSOR_486 0x01
247#define PCI_SUBCLASS_PROCESSOR_PENTIUM 0x02
248#define PCI_SUBCLASS_PROCESSOR_ALPHA 0x10
249#define PCI_SUBCLASS_PROCESSOR_POWERPC 0x20
250#define PCI_SUBCLASS_PROCESSOR_MIPS 0x30
251#define PCI_SUBCLASS_PROCESSOR_COPROC 0x40
252
253/* 0x0c serial bus controller subclasses */
254#define PCI_SUBCLASS_SERIAL_FIREWIRE 0x00
255#define PCI_SUBCLASS_SERIAL_ACCESS 0x01
256#define PCI_SUBCLASS_SERIAL_SSA 0x02
257#define PCI_SUBCLASS_SERIAL_USB 0x03
258#define PCI_SUBCLASS_SERIAL_FIBRECHANNEL 0x04
259#define PCI_SUBCLASS_SERIAL_SMBUS 0x05
260
261/* 0x0d wireless controller subclasses */
262#define PCI_SUBCLASS_WIRELESS_IRDA 0x00
263#define PCI_SUBCLASS_WIRELESS_CONSUMER_IR 0x01
264#define PCI_SUBCLASS_WIRELESS_RF 0x02
265#define PCI_SUBCLASS_WIRELESS_MISC 0x80
266
267/* 0x0e intelligent I/O controller subclasses */
268#define PCI_SUBCLASS_I2O_I2O 0x00
269
270/* 0x0f satellite communications controller subclasses */
271#define PCI_SUBCLASS_SATELLITE_TV 0x01
272#define PCI_SUBCLASS_SATELLITE_AUDIO 0x02
273#define PCI_SUBCLASS_SATELLITE_VOICE 0x03
274#define PCI_SUBCLASS_SATELLITE_DATA 0x04
275
276/* 0x10 encryption/decryption controller subclasses */
277#define PCI_SUBCLASS_CRYPT_NET_COMPUTING 0x00
278#define PCI_SUBCLASS_CRYPT_ENTERTAINMENT 0x10
279#define PCI_SUBCLASS_CRYPT_MISC 0x80
280
281/* 0x11 data acquisition and signal processing controller subclasses */
282#define PCI_SUBCLASS_DATAACQ_DPIO 0x00
283#define PCI_SUBCLASS_DATAACQ_MISC 0x80
284
285
286/* Header */
287#define PCI_HEADER_MISC 0x0c
288#define PCI_HEADER_MULTIFUNCTION 0x00800000
289
290/* Interrupt configration register */
291#define PCI_INTERRUPT_REG 0x3c
292#define PCI_INTERRUPT_PIN_MASK 0x0000ff00
293#define PCI_INTERRUPT_PIN_EXTRACT(x) \
294 ((((x) & PCI_INTERRUPT_PIN_MASK) >> 8) & 0xff)
295#define PCI_INTERRUPT_PIN_NONE 0x00
296#define PCI_INTERRUPT_PIN_A 0x01
297#define PCI_INTERRUPT_PIN_B 0x02
298#define PCI_INTERRUPT_PIN_C 0x03
299#define PCI_INTERRUPT_PIN_D 0x04
300
301#define PCI_INTERRUPT_LINE_MASK 0x000000ff
302#define PCI_INTERRUPT_LINE_EXTRACT(x) \
303 ((((x) & PCI_INTERRUPT_LINE_MASK) >> 0) & 0xff)
304#define PCI_INTERRUPT_LINE_INSERT(x,v) \
305 (((x) & ~PCI_INTERRUPT_LINE_MASK) | ((v) << 0))
306
307/* Base registers */
308#define PCI_MAP_REG_START 0x10
309#define PCI_MAP_REG_END 0x28
310#define PCI_MAP_ROM_REG 0x30
311
312#define PCI_MAP_MEMORY 0x00000000
313#define PCI_MAP_IO 0x00000001
314
315#define PCI_MAP_MEMORY_TYPE 0x00000007
316#define PCI_MAP_IO_TYPE 0x00000003
317
318#define PCI_MAP_MEMORY_TYPE_32BIT 0x00000000
319#define PCI_MAP_MEMORY_TYPE_32BIT_1M 0x00000002
320#define PCI_MAP_MEMORY_TYPE_64BIT 0x00000004
321#define PCI_MAP_MEMORY_TYPE_MASK 0x00000006
322#define PCI_MAP_MEMORY_CACHABLE 0x00000008
323#define PCI_MAP_MEMORY_ATTR_MASK 0x0000000e
324#define PCI_MAP_MEMORY_ADDRESS_MASK 0xfffffff0
325
326#define PCI_MAP_IO_ATTR_MASK 0x00000003
327
328#define PCI_MAP_IS_IO(b) ((b) & PCI_MAP_IO)
329#define PCI_MAP_IS_MEM(b) (!PCI_MAP_IS_IO(b))
330
331#define PCI_MAP_IS64BITMEM(b) \
332 (((b) & PCI_MAP_MEMORY_TYPE) == PCI_MAP_MEMORY_TYPE_64BIT)
333
334#define PCIGETMEMORY(b) ((b) & PCI_MAP_MEMORY_ADDRESS_MASK)
335#define PCIGETMEMORY64HIGH(b) (*((CARD32*)&(b) + 1))
336#define PCIGETMEMORY64(b) \
337 (PCIGETMEMORY(b) | ((CARD64)PCIGETMEMORY64HIGH(b) << 32))
338
339#define PCI_MAP_IO_ADDRESS_MASK 0xfffffffc
340
341#define PCIGETIO(b) ((b) & PCI_MAP_IO_ADDRESS_MASK)
342
343#define PCI_MAP_ROM_DECODE_ENABLE 0x00000001
344#define PCI_MAP_ROM_ADDRESS_MASK 0xfffff800
345
346#define PCIGETROM(b) ((b) & PCI_MAP_ROM_ADDRESS_MASK)
347
348/* PCI-PCI bridge mapping registers */
349#define PCI_PCI_BRIDGE_BUS_REG 0x18
350#define PCI_SUBORDINATE_BUS_MASK 0x00ff0000
351#define PCI_SECONDARY_BUS_MASK 0x0000ff00
352#define PCI_PRIMARY_BUS_MASK 0x000000ff
353
354#define PCI_PCI_BRIDGE_IO_REG 0x1c
355#define PCI_PCI_BRIDGE_MEM_REG 0x20
356#define PCI_PCI_BRIDGE_PMEM_REG 0x24
357
358#define PCI_PPB_IOBASE_EXTRACT(x) (((x) << 8) & 0xFF00)
359#define PCI_PPB_IOLIMIT_EXTRACT(x) (((x) << 0) & 0xFF00)
360
361#define PCI_PPB_MEMBASE_EXTRACT(x) (((x) << 16) & 0xFFFF0000)
362#define PCI_PPB_MEMLIMIT_EXTRACT(x) (((x) << 0) & 0xFFFF0000)
363
364#define PCI_PCI_BRIDGE_CONTROL_REG 0x3E
365#define PCI_PCI_BRIDGE_PARITY_EN 0x01
366#define PCI_PCI_BRIDGE_SERR_EN 0x02
367#define PCI_PCI_BRIDGE_ISA_EN 0x04
368#define PCI_PCI_BRIDGE_VGA_EN 0x08
369#define PCI_PCI_BRIDGE_MASTER_ABORT_EN 0x20
370#define PCI_PCI_BRIDGE_SECONDARY_RESET 0x40
371#define PCI_PCI_BRIDGE_FAST_B2B_EN 0x80
372/* header type 2 extensions */
373#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
374#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
375#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100
376#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
377#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
378
379#define PCI_CB_SEC_STATUS_REG 0x16 /* Secondary status */
380#define PCI_CB_PRIMARY_BUS_REG 0x18 /* PCI bus number */
381#define PCI_CB_CARD_BUS_REG 0x19 /* CardBus bus number */
382#define PCI_CB_SUBORDINATE_BUS_REG 0x1a /* Subordinate bus number */
383#define PCI_CB_LATENCY_TIMER_REG 0x1b /* CardBus latency timer */
384#define PCI_CB_MEM_BASE_0_REG 0x1c
385#define PCI_CB_MEM_LIMIT_0_REG 0x20
386#define PCI_CB_MEM_BASE_1_REG 0x24
387#define PCI_CB_MEM_LIMIT_1_REG 0x28
388#define PCI_CB_IO_BASE_0_REG 0x2c
389#define PCI_CB_IO_LIMIT_0_REG 0x30
390#define PCI_CB_IO_BASE_1_REG 0x34
391#define PCI_CB_IO_LIMIT_1_REG 0x38
392#define PCI_CB_BRIDGE_CONTROL_REG 0x3E
393
394#define PCI_CB_IO_RANGE_MASK ~0x03
395#define PCI_CB_IOBASE(x) (x & PCI_CB_IO_RANGE_MASK)
396#define PCI_CB_IOLIMIT(x) ((x & PCI_CB_IO_RANGE_MASK) + 3)
397
398/* Subsystem identification register */
399#define PCI_SUBSYSTEM_ID_REG 0x2c
400
401/* User defined cfg space regs */
402#define PCI_REG_USERCONFIG 0x40
403#define PCI_OPTION_REG 0x40
404
405/*
406 * Typedefs, etc...
407 */
408
409/* Primitive Types */
410typedef unsigned long ADDRESS; /* Memory/PCI address */
411typedef unsigned long IOADDRESS; /* Must be large enough for a pointer */
412typedef unsigned long PCITAG;
413
414/*
415 * PCI configuration space
416 */
417typedef struct pci_cfg_regs {
418 /* start of official PCI config space header */
419 union { /* Offset 0x0 - 0x3 */
420 CARD32 device_vendor;
421 struct {
422#if X_BYTE_ORDER == X_BIG_ENDIAN
423 CARD16 device;
424 CARD16 vendor;
425#else
426 CARD16 vendor;
427 CARD16 device;
428#endif
429 } dv;
430 } dv_id;
431
432 union { /* Offset 0x4 - 0x8 */
433 CARD32 status_command;
434 struct {
435#if X_BYTE_ORDER == X_BIG_ENDIAN
436 CARD16 status;
437 CARD16 command;
438#else
439 CARD16 command;
440 CARD16 status;
441#endif
442 } sc;
443 } stat_cmd;
444
445 union { /* Offset 0x8 - 0xb */
446 CARD32 class_revision;
447 struct {
448#if X_BYTE_ORDER == X_BIG_ENDIAN
449 CARD8 base_class;
450 CARD8 sub_class;
451 CARD8 prog_if;
452 CARD8 rev_id;
453#else
454 CARD8 rev_id;
455 CARD8 prog_if;
456 CARD8 sub_class;
457 CARD8 base_class;
458#endif
459 } cr;
460 } class_rev;
461
462 union { /* Offset 0xc - 0xf */
463 CARD32 bist_header_latency_cache;
464 struct {
465#if X_BYTE_ORDER == X_BIG_ENDIAN
466 CARD8 bist;
467 CARD8 header_type;
468 CARD8 latency_timer;
469 CARD8 cache_line_size;
470#else
471 CARD8 cache_line_size;
472 CARD8 latency_timer;
473 CARD8 header_type;
474 CARD8 bist;
475#endif
476 } bhlc;
477 } bhlc;
478 union { /* Offset 0x10 - 0x3b */
479 struct { /* header type 2 */
480 CARD32 cg_rsrvd1; /* 0x10 */
481#if X_BYTE_ORDER == X_BIG_ENDIAN
482 CARD16 secondary_status; /* 0x16 */
483 CARD16 cg_rsrvd2; /* 0x14 */
484
485 union {
486 CARD32 cg_bus_reg;
487 struct {
488 CARD8 latency_timer; /* 0x1b */
489 CARD8 subordinate_bus_number; /* 0x1a */
490 CARD8 cardbus_bus_number; /* 0x19 */
491 CARD8 primary_bus_number; /* 0x18 */
492 } cgbr;
493 } cgbr;
494#else
495 CARD16 cg_rsrvd2; /* 0x14 */
496 CARD16 secondary_status; /* 0x16 */
497
498 union {
499 CARD32 cg_bus_reg;
500 struct {
501 CARD8 primary_bus_number; /* 0x18 */
502 CARD8 cardbus_bus_number; /* 0x19 */
503 CARD8 subordinate_bus_number; /* 0x1a */
504 CARD8 latency_timer; /* 0x1b */
505 } cgbr;
506 } cgbr;
507#endif
508 CARD32 mem_base0; /* 0x1c */
509 CARD32 mem_limit0; /* 0x20 */
510 CARD32 mem_base1; /* 0x24 */
511 CARD32 mem_limit1; /* 0x28 */
512 CARD32 io_base0; /* 0x2c */
513 CARD32 io_limit0; /* 0x30 */
514 CARD32 io_base1; /* 0x34 */
515 CARD32 io_limit1; /* 0x38 */
516 } cg;
517 struct {
518 union { /* Offset 0x10 - 0x27 */
519 struct { /* header type 0 */
520 CARD32 dv_base0;
521 CARD32 dv_base1;
522 CARD32 dv_base2;
523 CARD32 dv_base3;
524 CARD32 dv_base4;
525 CARD32 dv_base5;
526 } dv;
527 struct { /* header type 1 */
528 CARD32 bg_rsrvd[2];
529#if X_BYTE_ORDER == X_BIG_ENDIAN
530 union {
531 CARD32 pp_bus_reg;
532 struct {
533 CARD8 secondary_latency_timer;
534 CARD8 subordinate_bus_number;
535 CARD8 secondary_bus_number;
536 CARD8 primary_bus_number;
537 } ppbr;
538 } ppbr;
539
540 CARD16 secondary_status;
541 CARD8 io_limit;
542 CARD8 io_base;
543
544 CARD16 mem_limit;
545 CARD16 mem_base;
546
547 CARD16 prefetch_mem_limit;
548 CARD16 prefetch_mem_base;
549#else
550 union {
551 CARD32 pp_bus_reg;
552 struct {
553 CARD8 primary_bus_number;
554 CARD8 secondary_bus_number;
555 CARD8 subordinate_bus_number;
556 CARD8 secondary_latency_timer;
557 } ppbr;
558 } ppbr;
559
560 CARD8 io_base;
561 CARD8 io_limit;
562 CARD16 secondary_status;
563
564 CARD16 mem_base;
565 CARD16 mem_limit;
566
567 CARD16 prefetch_mem_base;
568 CARD16 prefetch_mem_limit;
569#endif
570 } bg;
571 } bc;
572 union { /* Offset 0x28 - 0x2b */
573 CARD32 rsvd1;
574 CARD32 pftch_umem_base;
575 CARD32 cardbus_cis_ptr;
576 } um_c_cis;
577 union { /* Offset 0x2c - 0x2f */
578 CARD32 subsys_card_vendor;
579 CARD32 pftch_umem_limit;
580 CARD32 rsvd2;
581 struct {
582#if X_BYTE_ORDER == X_BIG_ENDIAN
583 CARD16 subsys_card;
584 CARD16 subsys_vendor;
585#else
586 CARD16 subsys_vendor;
587 CARD16 subsys_card;
588#endif
589 } ssys;
590 } um_ssys_id;
591 union { /* Offset 0x30 - 0x33 */
592 CARD32 baserom;
593 struct {
594#if X_BYTE_ORDER == X_BIG_ENDIAN
595 CARD16 io_ulimit;
596 CARD16 io_ubase;
597#else
598 CARD16 io_ubase;
599 CARD16 io_ulimit;
600#endif
601 } b_u_io;
602 } uio_rom;
603 struct {
604 CARD32 rsvd3; /* Offset 0x34 - 0x37 */
605 CARD32 rsvd4; /* Offset 0x38 - 0x3b */
606 } rsvd;
607 } cd;
608 } cx;
609 union { /* Offset 0x3c - 0x3f */
610 union { /* header type 0 */
611 CARD32 max_min_ipin_iline;
612 struct {
613#if X_BYTE_ORDER == X_BIG_ENDIAN
614 CARD8 max_lat;
615 CARD8 min_gnt;
616 CARD8 int_pin;
617 CARD8 int_line;
618#else
619 CARD8 int_line;
620 CARD8 int_pin;
621 CARD8 min_gnt;
622 CARD8 max_lat;
623#endif
624 } mmii;
625 } mmii;
626 struct { /* header type 1 */
627#if X_BYTE_ORDER == X_BIG_ENDIAN
628 CARD16 bridge_control; /* upper 8 bits reserved */
629 CARD8 rsvd2;
630 CARD8 rsvd1;
631#else
632 CARD8 rsvd1;
633 CARD8 rsvd2;
634 CARD16 bridge_control; /* upper 8 bits reserved */
635#endif
636 } bctrl;
637 } bm;
638 union { /* Offset 0x40 - 0xff */
639 CARD32 dwords[48];
640 CARD8 bytes[192];
641 } devspf;
642} pciCfgRegs;
643
644typedef union pci_cfg_spc {
645 pciCfgRegs regs;
646 CARD32 dwords[256/sizeof(CARD32)];
647 CARD8 bytes[256/sizeof(CARD8)];
648} pciCfgSpc;
649
650/*
651 * Data structure returned by xf86scanpci including contents of
652 * PCI config space header
653 */
654typedef struct pci_device {
655 PCITAG tag;
656 int busnum;
657 int devnum;
658 int funcnum;
659 pciCfgSpc cfgspc;
660 int basesize[7]; /* number of bits in base addr allocations */
661 Bool minBasesize;
662 CARD32 listed_class;
663 pointer businfo; /* pointer to secondary's bus info structure */
664 Bool fakeDevice; /* Device added by system chipset support */
665} pciDevice, *pciConfigPtr;
666
667typedef enum {
668 PCI_MEM,
669 PCI_MEM_SIZE,
670 PCI_MEM_SPARSE_BASE,
671 PCI_MEM_SPARSE_MASK,
672 PCI_IO,
673 PCI_IO_SIZE,
674 PCI_IO_SPARSE_BASE,
675 PCI_IO_SPARSE_MASK
676} PciAddrType;
677
678#define pci_device_vendor cfgspc.regs.dv_id.device_vendor
679#define pci_vendor cfgspc.regs.dv_id.dv.vendor
680#define pci_device cfgspc.regs.dv_id.dv.device
681#define pci_status_command cfgspc.regs.stat_cmd.status_command
682#define pci_command cfgspc.regs.stat_cmd.sc.command
683#define pci_status cfgspc.regs.stat_cmd.sc.status
684#define pci_class_revision cfgspc.regs.class_rev.class_revision
685#define pci_rev_id cfgspc.regs.class_rev.cr.rev_id
686#define pci_prog_if cfgspc.regs.class_rev.cr.prog_if
687#define pci_sub_class cfgspc.regs.class_rev.cr.sub_class
688#define pci_base_class cfgspc.regs.class_rev.cr.base_class
689#define pci_bist_header_latency_cache cfgspc.regs.bhlc.bist_header_latency_cache
690#define pci_cache_line_size cfgspc.regs.bhlc.bhlc.cache_line_size
691#define pci_latency_timer cfgspc.regs.bhlc.bhlc.latency_timer
692#define pci_header_type cfgspc.regs.bhlc.bhlc.header_type
693#define pci_bist cfgspc.regs.bhlc.bhlc.bist
694#define pci_cb_secondary_status cfgspc.regs.cx.cg.secondary_status
695#define pci_cb_bus_register cfgspc.regs.cx.cg.cgbr.cg_bus_reg
696#define pci_cb_primary_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.primary_bus_number
697#define pci_cb_cardbus_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.cardbus_bus_number
698#define pci_cb_subordinate_bus_number cfgspc.regs.cx.cg.cgbr.cgbr.subordinate_bus_number
699#define pci_cb_latency_timer cfgspc.regs.cx.cg.cgbr.cgbr.latency_timer
700#define pci_cb_membase0 cfgspc.regs.cx.cg.mem_base0
701#define pci_cb_memlimit0 cfgspc.regs.cx.cg.mem_limit0
702#define pci_cb_membase1 cfgspc.regs.cx.cg.mem_base1
703#define pci_cb_memlimit1 cfgspc.regs.cx.cg.mem_limit1
704#define pci_cb_iobase0 cfgspc.regs.cx.cg.io_base0
705#define pci_cb_iolimit0 cfgspc.regs.cx.cg.io_limit0
706#define pci_cb_iobase1 cfgspc.regs.cx.cg.io_base1
707#define pci_cb_iolimit1 cfgspc.regs.cx.cg.io_limit1
708#define pci_base0 cfgspc.regs.cx.cd.bc.dv.dv_base0
709#define pci_base1 cfgspc.regs.cx.cd.bc.dv.dv_base1
710#define pci_base2 cfgspc.regs.cx.cd.bc.dv.dv_base2
711#define pci_base3 cfgspc.regs.cx.cd.bc.dv.dv_base3
712#define pci_base4 cfgspc.regs.cx.cd.bc.dv.dv_base4
713#define pci_base5 cfgspc.regs.cx.cd.bc.dv.dv_base5
714#define pci_cardbus_cis_ptr cfgspc.regs.cx.cd.umem_c_cis.cardbus_cis_ptr
715#define pci_subsys_card_vendor cfgspc.regs.cx.cd.um_ssys_id.subsys_card_vendor
716#define pci_subsys_vendor cfgspc.regs.cx.cd.um_ssys_id.ssys.subsys_vendor
717#define pci_subsys_card cfgspc.regs.cx.cd.um_ssys_id.ssys.subsys_card
718#define pci_baserom cfgspc.regs.cx.cd.uio_rom.baserom
719#define pci_pp_bus_register cfgspc.regs.cx.cd.bc.bg.ppbr.pp_bus_reg
720#define pci_primary_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.primary_bus_number
721#define pci_secondary_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.secondary_bus_number
722#define pci_subordinate_bus_number cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.subordinate_bus_number
723#define pci_secondary_latency_timer cfgspc.regs.cx.cd.bc.bg.ppbr.ppbr.secondary_latency_timer
724#define pci_io_base cfgspc.regs.cx.cd.bc.bg.io_base
725#define pci_io_limit cfgspc.regs.cx.cd.bc.bg.io_limit
726#define pci_secondary_status cfgspc.regs.cx.cd.bc.bg.secondary_status
727#define pci_mem_base cfgspc.regs.cx.cd.bc.bg.mem_base
728#define pci_mem_limit cfgspc.regs.cx.cd.bc.bg.mem_limit
729#define pci_prefetch_mem_base cfgspc.regs.cx.cd.bc.bg.prefetch_mem_base
730#define pci_prefetch_mem_limit cfgspc.regs.cx.cd.bc.bg.prefetch_mem_limit
731#define pci_rsvd1 cfgspc.regs.cx.cd.um_c_cis.rsvd1
732#define pci_rsvd2 cfgspc.regs.cx.cd.um_ssys_id.rsvd2
733#define pci_prefetch_upper_mem_base cfgspc.regs.cx.cd.um_c_cis.pftch_umem_base
734#define pci_prefetch_upper_mem_limit cfgspc.regs.cx.cd.um_ssys_id.pftch_umem_limit
735#define pci_upper_io_base cfgspc.regs.cx.cd.uio_rom.b_u_io.io_ubase
736#define pci_upper_io_limit cfgspc.regs.cx.cd.uio_rom.b_u_io.io_ulimit
737#define pci_int_line cfgspc.regs.bm.mmii.mmii.int_line
738#define pci_int_pin cfgspc.regs.bm.mmii.mmii.int_pin
739#define pci_min_gnt cfgspc.regs.bm.mmii.mmii.min_gnt
740#define pci_max_lat cfgspc.regs.bm.mmii.mmii.max_lat
741#define pci_max_min_ipin_iline cfgspc.regs.bm.mmii.max_min_ipin_iline
742#define pci_bridge_control cfgspc.regs.bm.bctrl.bridge_control
743#define pci_user_config cfgspc.regs.devspf.dwords[0]
744#define pci_user_config_0 cfgspc.regs.devspf.bytes[0]
745#define pci_user_config_1 cfgspc.regs.devspf.bytes[1]
746#define pci_user_config_2 cfgspc.regs.devspf.bytes[2]
747#define pci_user_config_3 cfgspc.regs.devspf.bytes[3]
748
749typedef enum {
750 PCI_BIOS_PC = 0,
751 PCI_BIOS_OPEN_FIRMARE,
752 PCI_BIOS_HP_PA_RISC,
753 PCI_BIOS_OTHER
754} PciBiosType;
755
756/* Public PCI access functions */
757void pciInit(void);
758PCITAG pciFindFirst(CARD32 id, CARD32 mask);
759PCITAG pciFindNext(void);
760CARD32 pciReadLong(PCITAG tag, int offset);
761CARD16 pciReadWord(PCITAG tag, int offset);
762CARD8 pciReadByte(PCITAG tag, int offset);
763void pciWriteLong(PCITAG tag, int offset, CARD32 val);
764void pciWriteWord(PCITAG tag, int offset, CARD16 val);
765void pciWriteByte(PCITAG tag, int offset, CARD8 val);
766void pciSetBitsLong(PCITAG tag, int offset, CARD32 mask, CARD32 val);
767void pciSetBitsByte(PCITAG tag, int offset, CARD8 mask, CARD8 val);
768ADDRESS pciBusAddrToHostAddr(PCITAG tag, PciAddrType type, ADDRESS addr);
769ADDRESS pciHostAddrToBusAddr(PCITAG tag, PciAddrType type, ADDRESS addr);
770PCITAG pciTag(int busnum, int devnum, int funcnum);
771int pciGetBaseSize(PCITAG tag, int indx, Bool destructive, Bool *min);
772CARD32 pciCheckForBrokenBase(PCITAG tag,int basereg);
773pointer xf86MapPciMem(int ScreenNum, int Flags, PCITAG Tag,
774 ADDRESS Base, unsigned long Size);
775int xf86ReadPciBIOS(unsigned long Offset, PCITAG Tag, int basereg,
776 unsigned char *Buf, int Len);
777int xf86ReadPciBIOSByType(unsigned long Offset, PCITAG Tag,
778 int basereg, unsigned char *Buf,
779 int Len, PciBiosType Type);
780int xf86GetAvailablePciBIOSTypes(PCITAG Tag, int basereg,
781 PciBiosType *Buf);
782pciConfigPtr *xf86scanpci(int flags);
783
784extern int pciNumBuses;
785
786/* Domain access functions. Some of these probably shouldn't be public */
787int xf86GetPciDomain(PCITAG tag);
788pointer xf86MapDomainMemory(int ScreenNum, int Flags, PCITAG Tag,
789 ADDRESS Base, unsigned long Size);
790IOADDRESS xf86MapDomainIO(int ScreenNum, int Flags, PCITAG Tag,
791 IOADDRESS Base, unsigned long Size);
792int xf86ReadDomainMemory(PCITAG Tag, ADDRESS Base, int Len,
793 unsigned char *Buf);
794
795typedef enum {
796 ROM_BASE_PRESET = -2,
797 ROM_BASE_BIOS,
798 ROM_BASE_MEM0 = 0,
799 ROM_BASE_MEM1,
800 ROM_BASE_MEM2,
801 ROM_BASE_MEM3,
802 ROM_BASE_MEM4,
803 ROM_BASE_MEM5,
804 ROM_BASE_FIND
805} romBaseSource;
806
807#endif /* _XF86PCI_H */
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette