VirtualBox

source: vbox/trunk/src/VBox/Additions/x11/x11include/libdrm-1.0.5/mach64_drm.h@ 17232

Last change on this file since 17232 was 17232, checked in by vboxsync, 16 years ago

Additions/x11/x11include: added header files needed for DRI support in vboxvideo

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File size: 7.7 KB
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1/* mach64_drm.h -- Public header for the mach64 driver -*- linux-c -*-
2 * Created: Thu Nov 30 20:04:32 2000 by [email protected]
3 *
4 * Copyright 2000 Gareth Hughes
5 * Copyright 2002 Frank C. Earl
6 * Copyright 2002-2003 Leif Delgass
7 * All Rights Reserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE COPYRIGHT OWNER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
24 * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
25 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Gareth Hughes <[email protected]>
29 * Frank C. Earl <[email protected]>
30 * Leif Delgass <[email protected]>
31 */
32
33#ifndef __MACH64_DRM_H__
34#define __MACH64_DRM_H__
35
36/* WARNING: If you change any of these defines, make sure to change the
37 * defines in the Xserver file (mach64_sarea.h)
38 */
39#ifndef __MACH64_SAREA_DEFINES__
40#define __MACH64_SAREA_DEFINES__
41
42/* What needs to be changed for the current vertex buffer?
43 * GH: We're going to be pedantic about this. We want the card to do as
44 * little as possible, so let's avoid having it fetch a whole bunch of
45 * register values that don't change all that often, if at all.
46 */
47#define MACH64_UPLOAD_DST_OFF_PITCH 0x0001
48#define MACH64_UPLOAD_Z_OFF_PITCH 0x0002
49#define MACH64_UPLOAD_Z_ALPHA_CNTL 0x0004
50#define MACH64_UPLOAD_SCALE_3D_CNTL 0x0008
51#define MACH64_UPLOAD_DP_FOG_CLR 0x0010
52#define MACH64_UPLOAD_DP_WRITE_MASK 0x0020
53#define MACH64_UPLOAD_DP_PIX_WIDTH 0x0040
54#define MACH64_UPLOAD_SETUP_CNTL 0x0080
55#define MACH64_UPLOAD_MISC 0x0100
56#define MACH64_UPLOAD_TEXTURE 0x0200
57#define MACH64_UPLOAD_TEX0IMAGE 0x0400
58#define MACH64_UPLOAD_TEX1IMAGE 0x0800
59#define MACH64_UPLOAD_CLIPRECTS 0x1000 /* handled client-side */
60#define MACH64_UPLOAD_CONTEXT 0x00ff
61#define MACH64_UPLOAD_ALL 0x1fff
62
63/* DMA buffer size
64 */
65#define MACH64_BUFFER_SIZE 16384
66
67/* Max number of swaps allowed on the ring
68 * before the client must wait
69 */
70#define MACH64_MAX_QUEUED_FRAMES 3
71
72/* Byte offsets for host blit buffer data
73 */
74#define MACH64_HOSTDATA_BLIT_OFFSET 104
75
76/* Keep these small for testing.
77 */
78#define MACH64_NR_SAREA_CLIPRECTS 8
79
80#define MACH64_CARD_HEAP 0
81#define MACH64_AGP_HEAP 1
82#define MACH64_NR_TEX_HEAPS 2
83#define MACH64_NR_TEX_REGIONS 64
84#define MACH64_LOG_TEX_GRANULARITY 16
85
86#define MACH64_TEX_MAXLEVELS 1
87
88#define MACH64_NR_CONTEXT_REGS 15
89#define MACH64_NR_TEXTURE_REGS 4
90
91#endif /* __MACH64_SAREA_DEFINES__ */
92
93typedef struct {
94 unsigned int dst_off_pitch;
95
96 unsigned int z_off_pitch;
97 unsigned int z_cntl;
98 unsigned int alpha_tst_cntl;
99
100 unsigned int scale_3d_cntl;
101
102 unsigned int sc_left_right;
103 unsigned int sc_top_bottom;
104
105 unsigned int dp_fog_clr;
106 unsigned int dp_write_mask;
107 unsigned int dp_pix_width;
108 unsigned int dp_mix;
109 unsigned int dp_src;
110
111 unsigned int clr_cmp_cntl;
112 unsigned int gui_traj_cntl;
113
114 unsigned int setup_cntl;
115
116 unsigned int tex_size_pitch;
117 unsigned int tex_cntl;
118 unsigned int secondary_tex_off;
119 unsigned int tex_offset;
120} drm_mach64_context_regs_t;
121
122typedef struct drm_mach64_sarea {
123 /* The channel for communication of state information to the kernel
124 * on firing a vertex dma buffer.
125 */
126 drm_mach64_context_regs_t context_state;
127 unsigned int dirty;
128 unsigned int vertsize;
129
130 /* The current cliprects, or a subset thereof.
131 */
132 drm_clip_rect_t boxes[MACH64_NR_SAREA_CLIPRECTS];
133 unsigned int nbox;
134
135 /* Counters for client-side throttling of rendering clients.
136 */
137 unsigned int frames_queued;
138
139 /* Texture memory LRU.
140 */
141 drm_tex_region_t tex_list[MACH64_NR_TEX_HEAPS][MACH64_NR_TEX_REGIONS +
142 1];
143 unsigned int tex_age[MACH64_NR_TEX_HEAPS];
144 int ctx_owner;
145} drm_mach64_sarea_t;
146
147/* WARNING: If you change any of these defines, make sure to change the
148 * defines in the Xserver file (mach64_common.h)
149 */
150
151/* Mach64 specific ioctls
152 * The device specific ioctl range is 0x40 to 0x79.
153 */
154
155#define DRM_MACH64_INIT 0x00
156#define DRM_MACH64_IDLE 0x01
157#define DRM_MACH64_RESET 0x02
158#define DRM_MACH64_SWAP 0x03
159#define DRM_MACH64_CLEAR 0x04
160#define DRM_MACH64_VERTEX 0x05
161#define DRM_MACH64_BLIT 0x06
162#define DRM_MACH64_FLUSH 0x07
163#define DRM_MACH64_GETPARAM 0x08
164
165#define DRM_IOCTL_MACH64_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_INIT, drm_mach64_init_t)
166#define DRM_IOCTL_MACH64_IDLE DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_IDLE )
167#define DRM_IOCTL_MACH64_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_RESET )
168#define DRM_IOCTL_MACH64_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_SWAP )
169#define DRM_IOCTL_MACH64_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_CLEAR, drm_mach64_clear_t)
170#define DRM_IOCTL_MACH64_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_VERTEX, drm_mach64_vertex_t)
171#define DRM_IOCTL_MACH64_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MACH64_BLIT, drm_mach64_blit_t)
172#define DRM_IOCTL_MACH64_FLUSH DRM_IO( DRM_COMMAND_BASE + DRM_MACH64_FLUSH )
173#define DRM_IOCTL_MACH64_GETPARAM DRM_IOWR( DRM_COMMAND_BASE + DRM_MACH64_GETPARAM, drm_mach64_getparam_t)
174
175/* Buffer flags for clears
176 */
177#define MACH64_FRONT 0x1
178#define MACH64_BACK 0x2
179#define MACH64_DEPTH 0x4
180
181/* Primitive types for vertex buffers
182 */
183#define MACH64_PRIM_POINTS 0x00000000
184#define MACH64_PRIM_LINES 0x00000001
185#define MACH64_PRIM_LINE_LOOP 0x00000002
186#define MACH64_PRIM_LINE_STRIP 0x00000003
187#define MACH64_PRIM_TRIANGLES 0x00000004
188#define MACH64_PRIM_TRIANGLE_STRIP 0x00000005
189#define MACH64_PRIM_TRIANGLE_FAN 0x00000006
190#define MACH64_PRIM_QUADS 0x00000007
191#define MACH64_PRIM_QUAD_STRIP 0x00000008
192#define MACH64_PRIM_POLYGON 0x00000009
193
194typedef enum _drm_mach64_dma_mode_t {
195 MACH64_MODE_DMA_ASYNC,
196 MACH64_MODE_DMA_SYNC,
197 MACH64_MODE_MMIO
198} drm_mach64_dma_mode_t;
199
200typedef struct drm_mach64_init {
201 enum {
202 DRM_MACH64_INIT_DMA = 0x01,
203 DRM_MACH64_CLEANUP_DMA = 0x02
204 } func;
205
206 unsigned long sarea_priv_offset;
207 int is_pci;
208 drm_mach64_dma_mode_t dma_mode;
209
210 unsigned int fb_bpp;
211 unsigned int front_offset, front_pitch;
212 unsigned int back_offset, back_pitch;
213
214 unsigned int depth_bpp;
215 unsigned int depth_offset, depth_pitch;
216
217 unsigned long fb_offset;
218 unsigned long mmio_offset;
219 unsigned long ring_offset;
220 unsigned long buffers_offset;
221 unsigned long agp_textures_offset;
222} drm_mach64_init_t;
223
224typedef struct drm_mach64_clear {
225 unsigned int flags;
226 int x, y, w, h;
227 unsigned int clear_color;
228 unsigned int clear_depth;
229} drm_mach64_clear_t;
230
231typedef struct drm_mach64_vertex {
232 int prim;
233 void *buf; /* Address of vertex buffer */
234 unsigned long used; /* Number of bytes in buffer */
235 int discard; /* Client finished with buffer? */
236} drm_mach64_vertex_t;
237
238typedef struct drm_mach64_blit {
239 int idx;
240 int pitch;
241 int offset;
242 int format;
243 unsigned short x, y;
244 unsigned short width, height;
245} drm_mach64_blit_t;
246
247typedef struct drm_mach64_getparam {
248 enum {
249 MACH64_PARAM_FRAMES_QUEUED = 0x01,
250 MACH64_PARAM_IRQ_NR = 0x02
251 } param;
252 void *value;
253} drm_mach64_getparam_t;
254
255#endif
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