| 1 |
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| 2 | #include <xf86RamDac.h>
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| 3 |
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| 4 | extern _X_EXPORT RamDacHelperRecPtr IBMramdacProbe(ScrnInfoPtr pScrn,
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| 5 | RamDacSupportedInfoRecPtr
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| 6 | ramdacs);
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| 7 | extern _X_EXPORT void IBMramdacSave(ScrnInfoPtr pScrn, RamDacRecPtr RamDacRec,
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| 8 | RamDacRegRecPtr RamDacRegRec);
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| 9 | extern _X_EXPORT void IBMramdacRestore(ScrnInfoPtr pScrn,
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| 10 | RamDacRecPtr RamDacRec,
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| 11 | RamDacRegRecPtr RamDacRegRec);
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| 12 | extern _X_EXPORT void IBMramdac526SetBpp(ScrnInfoPtr pScrn,
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| 13 | RamDacRegRecPtr RamDacRegRec);
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| 14 | extern _X_EXPORT void IBMramdac640SetBpp(ScrnInfoPtr pScrn,
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| 15 | RamDacRegRecPtr RamDacRegRec);
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| 16 | extern _X_EXPORT unsigned long IBMramdac526CalculateMNPCForClock(unsigned long
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| 17 | RefClock,
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| 18 | unsigned long
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| 19 | ReqClock,
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| 20 | char
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| 21 | IsPixClock,
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| 22 | unsigned long
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| 23 | MinClock,
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| 24 | unsigned long
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| 25 | MaxClock,
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| 26 | unsigned long
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| 27 | *rM,
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| 28 | unsigned long
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| 29 | *rN,
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| 30 | unsigned long
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| 31 | *rP,
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| 32 | unsigned long
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| 33 | *rC);
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| 34 | extern _X_EXPORT unsigned long IBMramdac640CalculateMNPCForClock(unsigned long
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| 35 | RefClock,
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| 36 | unsigned long
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| 37 | ReqClock,
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| 38 | char
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| 39 | IsPixClock,
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| 40 | unsigned long
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| 41 | MinClock,
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| 42 | unsigned long
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| 43 | MaxClock,
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| 44 | unsigned long
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| 45 | *rM,
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| 46 | unsigned long
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| 47 | *rN,
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| 48 | unsigned long
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| 49 | *rP,
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| 50 | unsigned long
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| 51 | *rC);
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| 52 | extern _X_EXPORT void IBMramdac526HWCursorInit(xf86CursorInfoPtr infoPtr);
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| 53 | extern _X_EXPORT void IBMramdac640HWCursorInit(xf86CursorInfoPtr infoPtr);
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| 54 |
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| 55 | typedef void IBMramdac526SetBppProc(ScrnInfoPtr, RamDacRegRecPtr);
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| 56 | extern _X_EXPORT IBMramdac526SetBppProc *IBMramdac526SetBppWeak(void);
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| 57 |
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| 58 | #define IBM524_RAMDAC ((VENDOR_IBM << 16) | 0x00)
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| 59 | #define IBM524A_RAMDAC ((VENDOR_IBM << 16) | 0x01)
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| 60 | #define IBM525_RAMDAC ((VENDOR_IBM << 16) | 0x02)
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| 61 | #define IBM526_RAMDAC ((VENDOR_IBM << 16) | 0x03)
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| 62 | #define IBM526DB_RAMDAC ((VENDOR_IBM << 16) | 0x04)
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| 63 | #define IBM528_RAMDAC ((VENDOR_IBM << 16) | 0x05)
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| 64 | #define IBM528A_RAMDAC ((VENDOR_IBM << 16) | 0x06)
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| 65 | #define IBM624_RAMDAC ((VENDOR_IBM << 16) | 0x07)
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| 66 | #define IBM624DB_RAMDAC ((VENDOR_IBM << 16) | 0x08)
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| 67 | #define IBM640_RAMDAC ((VENDOR_IBM << 16) | 0x09)
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| 68 |
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| 69 | /*
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| 70 | * IBM Ramdac registers
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| 71 | */
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| 72 |
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| 73 | #define IBMRGB_REF_FREQ_1 14.31818
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| 74 | #define IBMRGB_REF_FREQ_2 50.00000
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| 75 |
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| 76 | #define IBMRGB_rev 0x00
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| 77 | #define IBMRGB_id 0x01
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| 78 | #define IBMRGB_misc_clock 0x02
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| 79 | #define IBMRGB_sync 0x03
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| 80 | #define IBMRGB_hsync_pos 0x04
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| 81 | #define IBMRGB_pwr_mgmt 0x05
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| 82 | #define IBMRGB_dac_op 0x06
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| 83 | #define IBMRGB_pal_ctrl 0x07
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| 84 | #define IBMRGB_sysclk 0x08 /* not RGB525 */
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| 85 | #define IBMRGB_pix_fmt 0x0a
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| 86 | #define IBMRGB_8bpp 0x0b
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| 87 | #define IBMRGB_16bpp 0x0c
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| 88 | #define IBMRGB_24bpp 0x0d
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| 89 | #define IBMRGB_32bpp 0x0e
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| 90 | #define IBMRGB_pll_ctrl1 0x10
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| 91 | #define IBMRGB_pll_ctrl2 0x11
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| 92 | #define IBMRGB_pll_ref_div_fix 0x14
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| 93 | #define IBMRGB_sysclk_ref_div 0x15 /* not RGB525 */
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| 94 | #define IBMRGB_sysclk_vco_div 0x16 /* not RGB525 */
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| 95 | /* #define IBMRGB_f0 0x20 */
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| 96 |
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| 97 | #define IBMRGB_sysclk_n 0x15
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| 98 | #define IBMRGB_sysclk_m 0x16
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| 99 | #define IBMRGB_sysclk_p 0x17
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| 100 | #define IBMRGB_sysclk_c 0x18
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| 101 |
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| 102 | #define IBMRGB_m0 0x20
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| 103 | #define IBMRGB_n0 0x21
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| 104 | #define IBMRGB_p0 0x22
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| 105 | #define IBMRGB_c0 0x23
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| 106 | #define IBMRGB_m1 0x24
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| 107 | #define IBMRGB_n1 0x25
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| 108 | #define IBMRGB_p1 0x26
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| 109 | #define IBMRGB_c1 0x27
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| 110 | #define IBMRGB_m2 0x28
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| 111 | #define IBMRGB_n2 0x29
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| 112 | #define IBMRGB_p2 0x2a
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| 113 | #define IBMRGB_c2 0x2b
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| 114 | #define IBMRGB_m3 0x2c
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| 115 | #define IBMRGB_n3 0x2d
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| 116 | #define IBMRGB_p3 0x2e
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| 117 | #define IBMRGB_c3 0x2f
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| 118 |
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| 119 | #define IBMRGB_curs 0x30
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| 120 | #define IBMRGB_curs_xl 0x31
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| 121 | #define IBMRGB_curs_xh 0x32
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| 122 | #define IBMRGB_curs_yl 0x33
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| 123 | #define IBMRGB_curs_yh 0x34
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| 124 | #define IBMRGB_curs_hot_x 0x35
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| 125 | #define IBMRGB_curs_hot_y 0x36
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| 126 | #define IBMRGB_curs_col1_r 0x40
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| 127 | #define IBMRGB_curs_col1_g 0x41
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| 128 | #define IBMRGB_curs_col1_b 0x42
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| 129 | #define IBMRGB_curs_col2_r 0x43
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| 130 | #define IBMRGB_curs_col2_g 0x44
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| 131 | #define IBMRGB_curs_col2_b 0x45
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| 132 | #define IBMRGB_curs_col3_r 0x46
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| 133 | #define IBMRGB_curs_col3_g 0x47
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| 134 | #define IBMRGB_curs_col3_b 0x48
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| 135 | #define IBMRGB_border_col_r 0x60
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| 136 | #define IBMRGB_border_col_g 0x61
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| 137 | #define IBMRGB_botder_col_b 0x62
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| 138 | #define IBMRGB_key 0x68
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| 139 | #define IBMRGB_key_mask 0x6C
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| 140 | #define IBMRGB_misc1 0x70
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| 141 | #define IBMRGB_misc2 0x71
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| 142 | #define IBMRGB_misc3 0x72
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| 143 | #define IBMRGB_misc4 0x73 /* not RGB525 */
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| 144 | #define IBMRGB_key_control 0x78
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| 145 | #define IBMRGB_dac_sense 0x82
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| 146 | #define IBMRGB_misr_r 0x84
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| 147 | #define IBMRGB_misr_g 0x86
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| 148 | #define IBMRGB_misr_b 0x88
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| 149 | #define IBMRGB_pll_vco_div_in 0x8e
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| 150 | #define IBMRGB_pll_ref_div_in 0x8f
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| 151 | #define IBMRGB_vram_mask_0 0x90
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| 152 | #define IBMRGB_vram_mask_1 0x91
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| 153 | #define IBMRGB_vram_mask_2 0x92
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| 154 | #define IBMRGB_vram_mask_3 0x93
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| 155 | #define IBMRGB_curs_array 0x100
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| 156 |
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| 157 | /* Constants rgb525.h */
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| 158 |
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| 159 | /* RGB525_REVISION_LEVEL */
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| 160 | #define RGB525_PRODUCT_REV_LEVEL 0xf0
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| 161 |
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| 162 | /* RGB525_ID */
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| 163 | #define RGB525_PRODUCT_ID 0x01
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| 164 |
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| 165 | /* RGB525_MISC_CTRL_1 */
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| 166 | #define MISR_CNTL_ENABLE 0x80
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| 167 | #define VMSK_CNTL_ENABLE 0x40
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| 168 | #define PADR_RDMT_RDADDR 0x0
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| 169 | #define PADR_RDMT_PAL_STATE 0x20
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| 170 | #define SENS_DSAB_DISABLE 0x10
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| 171 | #define SENS_SEL_BIT3 0x0
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| 172 | #define SENS_SEL_BIT7 0x08
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| 173 | #define VRAM_SIZE_32 0x0
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| 174 | #define VRAM_SIZE_64 0x01
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| 175 |
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| 176 | /* RGB525_MISC_CTRL_2 */
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| 177 | #define PCLK_SEL_LCLK 0x0
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| 178 | #define PCLK_SEL_PLL 0x40
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| 179 | #define PCLK_SEL_EXT 0x80
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| 180 | #define INTL_MODE_ENABLE 0x20
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| 181 | #define BLANK_CNTL_ENABLE 0x10
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| 182 | #define COL_RES_6BIT 0x0
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| 183 | #define COL_RES_8BIT 0x04
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| 184 | #define PORT_SEL_VGA 0x0
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| 185 | #define PORT_SEL_VRAM 0x01
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| 186 |
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| 187 | /* RGB525_MISC_CTRL_3 */
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| 188 | #define SWAP_RB 0x80
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| 189 | #define SWAP_WORD_LOHI 0x0
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| 190 | #define SWAP_WORD_HILO 0x10
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| 191 | #define SWAP_NIB_HILO 0x0
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| 192 | #define SWAP_NIB_LOHI 0x02
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| 193 |
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| 194 | /* RGB525_MISC_CLK_CTRL */
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| 195 | #define DDOT_CLK_ENABLE 0x0
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| 196 | #define DDOT_CLK_DISABLE 0x80
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| 197 | #define SCLK_ENABLE 0x0
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| 198 | #define SCLK_DISABLE 0x40
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| 199 | #define B24P_DDOT_PLL 0x0
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| 200 | #define B24P_DDOT_SCLK 0x20
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| 201 | #define DDOT_DIV_PLL_1 0x0
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| 202 | #define DDOT_DIV_PLL_2 0x02
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| 203 | #define DDOT_DIV_PLL_4 0x04
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| 204 | #define DDOT_DIV_PLL_8 0x06
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| 205 | #define DDOT_DIV_PLL_16 0x08
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| 206 | #define PLL_DISABLE 0x0
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| 207 | #define PLL_ENABLE 0x01
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| 208 |
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| 209 | /* RGB525_SYNC_CTRL */
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| 210 | #define DLY_CNTL_ADD 0x0
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| 211 | #define DLY_SYNC_NOADD 0x80
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| 212 | #define CSYN_INVT_DISABLE 0x0
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| 213 | #define CSYN_INVT_ENABLE 0x40
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| 214 | #define VSYN_INVT_DISABLE 0x0
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| 215 | #define VSYN_INVT_ENABLE 0x20
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| 216 | #define HSYN_INVT_DISABLE 0x0
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| 217 | #define HSYN_INVT_ENABLE 0x10
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| 218 | #define VSYN_CNTL_NORMAL 0x0
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| 219 | #define VSYN_CNTL_HIGH 0x04
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| 220 | #define VSYN_CNTL_LOW 0x08
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| 221 | #define VSYN_CNTL_DISABLE 0x0C
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| 222 | #define HSYN_CNTL_NORMAL 0x0
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| 223 | #define HSYN_CNTL_HIGH 0x01
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| 224 | #define HSYN_CNTL_LOW 0x02
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| 225 | #define HSYN_CNTL_DISABLE 0x03
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| 226 |
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| 227 | /* RGB525_HSYNC_CTRL */
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| 228 | #define HSYN_POS(n) (n)
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| 229 |
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| 230 | /* RGB525_POWER_MANAGEMENT */
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| 231 | #define SCLK_PWR_NORMAL 0x0
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| 232 | #define SCLK_PWR_DISABLE 0x10
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| 233 | #define DDOT_PWR_NORMAL 0x0
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| 234 | #define DDOT_PWR_DISABLE 0x08
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| 235 | #define SYNC_PWR_NORMAL 0x0
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| 236 | #define SYNC_PWR_DISABLE 0x04
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| 237 | #define ICLK_PWR_NORMAL 0x0
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| 238 | #define ICLK_PWR_DISABLE 0x02
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| 239 | #define DAC_PWR_NORMAL 0x0
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| 240 | #define DAC_PWR_DISABLE 0x01
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| 241 |
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| 242 | /* RGB525_DAC_OPERATION */
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| 243 | #define SOG_DISABLE 0x0
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| 244 | #define SOG_ENABLE 0x08
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| 245 | #define BRB_NORMAL 0x0
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| 246 | #define BRB_ALWAYS 0x04
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| 247 | #define DSR_DAC_SLOW 0x02
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| 248 | #define DSR_DAC_FAST 0x0
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| 249 | #define DPE_DISABLE 0x0
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| 250 | #define DPE_ENABLE 0x01
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| 251 |
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| 252 | /* RGB525_PALETTE_CTRL */
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| 253 | #define SIXBIT_LINEAR_ENABLE 0x0
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| 254 | #define SIXBIT_LINEAR_DISABLE 0x80
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| 255 | #define PALETTE_PARITION(n) (n)
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| 256 |
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| 257 | /* RGB525_PIXEL_FORMAT */
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| 258 | #define PIXEL_FORMAT_4BPP 0x02
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| 259 | #define PIXEL_FORMAT_8BPP 0x03
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| 260 | #define PIXEL_FORMAT_16BPP 0x04
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| 261 | #define PIXEL_FORMAT_24BPP 0x05
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| 262 | #define PIXEL_FORMAT_32BPP 0x06
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| 263 |
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| 264 | /* RGB525_8BPP_CTRL */
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| 265 | #define B8_DCOL_INDIRECT 0x0
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| 266 | #define B8_DCOL_DIRECT 0x01
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| 267 |
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| 268 | /* RGB525_16BPP_CTRL */
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| 269 | #define B16_DCOL_INDIRECT 0x0
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| 270 | #define B16_DCOL_DYNAMIC 0x40
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| 271 | #define B16_DCOL_DIRECT 0xC0
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| 272 | #define B16_POL_FORCE_BYPASS 0x0
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| 273 | #define B16_POL_FORCE_LOOKUP 0x20
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| 274 | #define B16_ZIB 0x0
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| 275 | #define B16_LINEAR 0x04
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| 276 | #define B16_555 0x0
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| 277 | #define B16_565 0x02
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| 278 | #define B16_SPARSE 0x0
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| 279 | #define B16_CONTIGUOUS 0x01
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| 280 |
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| 281 | /* RGB525_24BPP_CTRL */
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| 282 | #define B24_DCOL_INDIRECT 0x0
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| 283 | #define B24_DCOL_DIRECT 0x01
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| 284 |
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| 285 | /* RGB525_32BPP_CTRL */
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| 286 | #define B32_POL_FORCE_BYPASS 0x0
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| 287 | #define B32_POL_FORCE_LOOKUP 0x04
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| 288 | #define B32_DCOL_INDIRECT 0x0
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| 289 | #define B32_DCOL_DYNAMIC 0x01
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| 290 | #define B32_DCOL_DIRECT 0x03
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| 291 |
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| 292 | /* RGB525_PLL_CTRL_1 */
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| 293 | #define REF_SRC_REFCLK 0x0
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| 294 | #define REF_SRC_EXTCLK 0x10
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| 295 | #define PLL_EXT_FS_3_0 0x0
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| 296 | #define PLL_EXT_FS_2_0 0x01
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| 297 | #define PLL_CNTL2_3_0 0x02
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| 298 | #define PLL_CNTL2_2_0 0x03
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| 299 |
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| 300 | /* RGB525_PLL_CTRL_2 */
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| 301 | #define PLL_INT_FS_3_0(n) (n)
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| 302 | #define PLL_INT_FS_2_0(n) (n)
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| 303 |
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| 304 | /* RGB525_PLL_REF_DIV_COUNT */
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| 305 | #define REF_DIV_COUNT(n) (n)
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| 306 |
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| 307 | /* RGB525_F0 - RGB525_F15 */
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| 308 | #define VCO_DIV_COUNT(n) (n)
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| 309 |
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| 310 | /* RGB525_PLL_REFCLK values */
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| 311 | #define RGB525_PLL_REFCLK_MHz(n) ((n)/2)
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| 312 |
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| 313 | /* RGB525_CURSOR_CONTROL */
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| 314 | #define SMLC_PART_0 0x0
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| 315 | #define SMLC_PART_1 0x40
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| 316 | #define SMLC_PART_2 0x80
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| 317 | #define SMLC_PART_3 0xC0
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| 318 | #define PIX_ORDER_RL 0x0
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| 319 | #define PIX_ORDER_LR 0x20
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| 320 | #define LOC_READ_LAST 0x0
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| 321 | #define LOC_READ_ACTUAL 0x10
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| 322 | #define UPDT_CNTL_DELAYED 0x0
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| 323 | #define UPDT_CNTL_IMMEDIATE 0x08
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| 324 | #define CURSOR_SIZE_32 0x0
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| 325 | #define CURSOR_SIZE_64 0x40
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| 326 | #define CURSOR_MODE_OFF 0x0
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| 327 | #define CURSOR_MODE_3_COLOR 0x01
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| 328 | #define CURSOR_MODE_2_COLOR_HL 0x02
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| 329 | #define CURSOR_MODE_2_COLOR 0x03
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| 330 |
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| 331 | /* RGB525_REVISION_LEVEL */
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| 332 | #define REVISION_LEVEL 0xF0 /* predefined */
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| 333 |
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| 334 | /* RGB525_ID */
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| 335 | #define ID_CODE 0x01 /* predefined */
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| 336 |
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| 337 | /* MISR status */
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| 338 | #define RGB525_MISR_DONE 0x01
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| 339 |
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| 340 | /* the IBMRGB640 is rather different from the rest of the RAMDACs,
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| 341 | so we define a completely new set of register names for it */
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| 342 | #define RGB640_SER_07_00 0x02
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| 343 | #define RGB640_SER_15_08 0x03
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| 344 | #define RGB640_SER_23_16 0x04
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| 345 | #define RGB640_SER_31_24 0x05
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| 346 | #define RGB640_SER_WID_03_00 0x06
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| 347 | #define RGB640_SER_WID_07_04 0x07
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| 348 | #define RGB640_SER_MODE 0x08
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| 349 | #define IBM640_SER_2_1 0x00
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| 350 | #define IBM640_SER_4_1 0x01
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| 351 | #define IBM640_SER_8_1 0x02
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| 352 | #define IBM640_SER_16_1 0x03
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| 353 | #define IBM640_SER_16_3 0x05
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| 354 | #define IBM640_SER_5_1 0x06
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| 355 | #define RGB640_PIXEL_INTERLEAVE 0x09
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| 356 | #define RGB640_MISC_CONF 0x0a
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| 357 | #define IBM640_PCLK 0x00
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| 358 | #define IBM640_PCLK_2 0x40
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| 359 | #define IBM640_PCLK_4 0x80
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| 360 | #define IBM640_PCLK_8 0xc0
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| 361 | #define IBM640_PSIZE10 0x10
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| 362 | #define IBM640_LCI 0x08
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| 363 | #define IBM640_WIDCTL_MASK 0x07
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| 364 | #define RGB640_VGA_CONTROL 0x0b
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| 365 | #define IBM640_RDBK 0x04
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| 366 | #define IBM640_PSIZE8 0x02
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| 367 | #define IBM640_VRAM 0x01
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| 368 | #define RGB640_DAC_CONTROL 0x0d
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| 369 | #define IBM640_MONO 0x08
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| 370 | #define IBM640_DACENBL 0x04
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| 371 | #define IBM640_SHUNT 0x02
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| 372 | #define IBM640_SLOWSLEW 0x01
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| 373 | #define RGB640_OUTPUT_CONTROL 0x0e
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| 374 | #define IBM640_RDAI 0x04
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| 375 | #define IBM640_WDAI 0x02
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| 376 | #define IBM640_WATCTL 0x01
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| 377 | #define RGB640_SYNC_CONTROL 0x0f
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| 378 | #define IBM640_PWR 0x20
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| 379 | #define IBM640_VSP 0x10
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| 380 | #define IBM640_HSP 0x08
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| 381 | #define IBM640_CSE 0x04
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| 382 | #define IBM640_CSG 0x02
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| 383 | #define IBM640_BPE 0x01
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| 384 | #define RGB640_PLL_N 0x10
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| 385 | #define RGB640_PLL_M 0x11
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| 386 | #define RGB640_PLL_P 0x12
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| 387 | #define RGB640_PLL_CTL 0x13
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| 388 | #define IBM640_PLL_EN 0x04
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| 389 | #define IBM640_PLL_HIGH 0x10
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| 390 | #define IBM640_PLL_LOW 0x01
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| 391 | #define RGB640_AUX_PLL_CTL 0x17
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| 392 | #define IBM640_AUXPLL 0x04
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| 393 | #define IBM640_AUX_HI 0x02
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| 394 | #define IBM640_AUX_LO 0x01
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| 395 | #define RGB640_CHROMA_KEY0 0x20
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| 396 | #define RGB640_CHROMA_MASK0 0x21
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| 397 | #define RGB640_CURS_X_LOW 0x40
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| 398 | #define RGB640_CURS_X_HIGH 0x41
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| 399 | #define RGB640_CURS_Y_LOW 0x42
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| 400 | #define RGB640_CURS_Y_HIGH 0x43
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| 401 | #define RGB640_CURS_OFFSETX 0x44
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| 402 | #define RGB640_CURS_OFFSETY 0x45
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| 403 | #define RGB640_CURSOR_CONTROL 0x4B
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| 404 | #define IBM640_CURS_OFF 0x00
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| 405 | #define IBM640_CURS_MODE0 0x01
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| 406 | #define IBM640_CURS_MODE1 0x02
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| 407 | #define IBM640_CURS_MODE2 0x03
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| 408 | #define IBM640_CURS_ADV 0x04
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| 409 | #define RGB640_CROSSHAIR_CONTROL 0x57
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| 410 | #define RGB640_VRAM_MASK0 0xf0
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| 411 | #define RGB640_VRAM_MASK1 0xf1
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| 412 | #define RGB640_VRAM_MASK2 0xf2
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| 413 | #define RGB640_DIAGS 0xfa
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| 414 | #define RGB640_CURS_WRITE 0x1000
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| 415 | #define RGB640_CURS_COL0 0x4800
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| 416 | #define RGB640_CURS_COL1 0x4801
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| 417 | #define RGB640_CURS_COL2 0x4802
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| 418 | #define RGB640_CURS_COL3 0x4803
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