DevCodec.cpp@ 33829

Last change on this file since 33829 was 33829, checked in by vboxsync, 14 years ago
Audio/HDA: cosmetic.
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1	/* $Id: DevCodec.cpp 33829 2010-11-08 11:27:31Z vboxsync $ */
2	/** @file
3	* DevCodec - VBox ICH Intel HD Audio Codec.
4	*/
5
6	/*
7	* Copyright (C) 2006-2008 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17	#define LOG_GROUP LOG_GROUP_DEV_AUDIO
18	#include <VBox/pdmdev.h>
19	#include <iprt/assert.h>
20	#include <iprt/uuid.h>
21	#include <iprt/string.h>
22	#include <iprt/mem.h>
23	#include <iprt/asm.h>
24	#include <iprt/cpp/utils.h>
25
26	#include "../Builtins.h"
27	extern "C" {
28	#include "audio.h"
29	}
30	#include "DevCodec.h"
31
32	#define CODEC_CAD_MASK 0xF0000000
33	#define CODEC_CAD_SHIFT 28
34	#define CODEC_DIRECT_MASK RT_BIT(27)
35	#define CODEC_NID_MASK 0x07F00000
36	#define CODEC_NID_SHIFT 20
37	#define CODEC_VERBDATA_MASK 0x000FFFFF
38	#define CODEC_VERB_4BIT_CMD 0x000FFFF0
39	#define CODEC_VERB_4BIT_DATA 0x0000000F
40	#define CODEC_VERB_8BIT_CMD 0x000FFF00
41	#define CODEC_VERB_8BIT_DATA 0x000000FF
42	#define CODEC_VERB_16BIT_CMD 0x000F0000
43	#define CODEC_VERB_16BIT_DATA 0x0000FFFF
44
45	#define CODEC_CAD(cmd) ((cmd) & CODEC_CAD_MASK)
46	#define CODEC_DIRECT(cmd) ((cmd) & CODEC_DIRECT_MASK)
47	#define CODEC_NID(cmd) ((((cmd) & CODEC_NID_MASK)) >> CODEC_NID_SHIFT)
48	#define CODEC_VERBDATA(cmd) ((cmd) & CODEC_VERBDATA_MASK)
49	#define CODEC_VERB_CMD(cmd, mask, x) (((cmd) & (mask)) >> (x))
50	#define CODEC_VERB_CMD4(cmd) (CODEC_VERB_CMD((cmd), CODEC_VERB_4BIT_CMD, 4))
51	#define CODEC_VERB_CMD8(cmd) (CODEC_VERB_CMD((cmd), CODEC_VERB_8BIT_CMD, 8))
52	#define CODEC_VERB_CMD16(cmd) (CODEC_VERB_CMD((cmd), CODEC_VERB_16BIT_CMD, 16))
53
54	#define CODEC_VERB_GET_AMP_DIRECTION RT_BIT(15)
55	#define CODEC_VERB_GET_AMP_SIDE RT_BIT(13)
56	#define CODEC_VERB_GET_AMP_INDEX 0x7
57
58	/* HDA spec 7.3.3.7 NoteA */
59	#define CODEC_GET_AMP_DIRECTION(cmd) (((cmd) & CODEC_VERB_GET_AMP_DIRECTION) >> 15)
60	#define CODEC_GET_AMP_SIDE(cmd) (((cmd) & CODEC_VERB_GET_AMP_SIDE) >> 13)
61	#define CODEC_GET_AMP_INDEX(cmd) (CODEC_GET_AMP_DIRECTION(cmd) ? 0 : ((cmd) & CODEC_VERB_GET_AMP_INDEX))
62
63	/* HDA spec 7.3.3.7 NoteC */
64	#define CODEC_VERB_SET_AMP_OUT_DIRECTION RT_BIT(15)
65	#define CODEC_VERB_SET_AMP_IN_DIRECTION RT_BIT(14)
66	#define CODEC_VERB_SET_AMP_LEFT_SIDE RT_BIT(13)
67	#define CODEC_VERB_SET_AMP_RIGHT_SIDE RT_BIT(12)
68	#define CODEC_VERB_SET_AMP_INDEX (0x7 << 8)
69
70	#define CODEC_SET_AMP_IS_OUT_DIRECTION(cmd) (((cmd) & CODEC_VERB_SET_AMP_OUT_DIRECTION) != 0)
71	#define CODEC_SET_AMP_IS_IN_DIRECTION(cmd) (((cmd) & CODEC_VERB_SET_AMP_IN_DIRECTION) != 0)
72	#define CODEC_SET_AMP_IS_LEFT_SIDE(cmd) (((cmd) & CODEC_VERB_SET_AMP_LEFT_SIDE) != 0)
73	#define CODEC_SET_AMP_IS_RIGHT_SIDE(cmd) (((cmd) & CODEC_VERB_SET_AMP_RIGHT_SIDE) != 0)
74	#define CODEC_SET_AMP_INDEX(cmd) (((cmd) & CODEC_VERB_SET_AMP_INDEX) >> 7)
75
76	/* HDA spec 7.3.3.1 defines layout of configuration registers/verbs (0xF00) */
77	/* VendorID (7.3.4.1) */
78	#define CODEC_MAKE_F00_00(vendorID, deviceID) (((vendorID) << 16) \| (deviceID))
79	/* RevisionID (7.3.4.2)*/
80	#define CODEC_MAKE_F00_02(MajRev, MinRev, RevisionID, SteppingID) (((MajRev) << 20)\|((MinRev) << 16)\|((RevisionID) << 8)\|(SteppingID))
81	/* Subordinate node count (7.3.4.3)*/
82	#define CODEC_MAKE_F00_04(startNodeNumber, totalNodeNumber) ((((startNodeNumber) & 0xFF) << 16)\|((totalNodeNumber) & 0xFF))
83	/*
84	* Function Group Type (7.3.4.4)
85	* 0 & [0x3-0x7f] are reserved types
86	* [0x80 - 0xff] are vendor defined function groups
87	*/
88	#define CODEC_MAKE_F00_05(UnSol, NodeType) ((UnSol)\|(NodeType))
89	#define CODEC_F00_05_UNSOL RT_BIT(8)
90	#define CODEC_F00_05_AFG (0x1)
91	#define CODEC_F00_05_MFG (0x2)
92	/* Audio Function Group capabilities (7.3.4.5) */
93	#define CODEC_MAKE_F00_08(BeepGen, InputDelay, OutputDelay) ((BeepGen)\| (((InputDelay) & 0xF) << 8) \| ((OutputDelay) & 0xF))
94	#define CODEC_F00_08_BEEP_GEN RT_BIT(16)
95
96	/* Widget Capabilities (7.3.4.6) */
97	#define CODEC_MAKE_F00_09(type, delay, chanel_count) \
98	( (((type) & 0xF) << 20) \
99	\| (((delay) & 0xF) << 16) \
100	\| (((chanel_count) & 0xF) << 13))
101	/* note: types 0x8-0xe are reserved */
102	#define CODEC_F00_09_TYPE_AUDIO_OUTPUT (0x0)
103	#define CODEC_F00_09_TYPE_AUDIO_INPUT (0x1)
104	#define CODEC_F00_09_TYPE_AUDIO_MIXER (0x2)
105	#define CODEC_F00_09_TYPE_AUDIO_SELECTOR (0x3)
106	#define CODEC_F00_09_TYPE_PIN_COMPLEX (0x4)
107	#define CODEC_F00_09_TYPE_POWER_WIDGET (0x5)
108	#define CODEC_F00_09_TYPE_VOLUME_KNOB (0x6)
109	#define CODEC_F00_09_TYPE_BEEP_GEN (0x7)
110	#define CODEC_F00_09_TYPE_VENDOR_DEFINED (0xF)
111
112	#define CODEC_F00_09_CAP_CP RT_BIT(12)
113	#define CODEC_F00_09_CAP_L_R_SWAP RT_BIT(11)
114	#define CODEC_F00_09_CAP_POWER_CTRL RT_BIT(10)
115	#define CODEC_F00_09_CAP_DIGITAL RT_BIT(9)
116	#define CODEC_F00_09_CAP_CONNECTION_LIST RT_BIT(8)
117	#define CODEC_F00_09_CAP_UNSOL RT_BIT(7)
118	#define CODEC_F00_09_CAP_PROC_WIDGET RT_BIT(6)
119	#define CODEC_F00_09_CAP_STRIPE RT_BIT(5)
120	#define CODEC_F00_09_CAP_FMT_OVERRIDE RT_BIT(4)
121	#define CODEC_F00_09_CAP_AMP_FMT_OVERRIDE RT_BIT(3)
122	#define CODEC_F00_09_CAP_OUT_AMP_PRESENT RT_BIT(2)
123	#define CODEC_F00_09_CAP_IN_AMP_PRESENT RT_BIT(1)
124	#define CODEC_F00_09_CAP_LSB RT_BIT(0)
125
126	/* Supported PCM size, rates (7.3.4.7) */
127	#define CODEC_F00_0A_32_BIT RT_BIT(19)
128	#define CODEC_F00_0A_24_BIT RT_BIT(18)
129	#define CODEC_F00_0A_16_BIT RT_BIT(17)
130	#define CODEC_F00_0A_8_BIT RT_BIT(16)
131
132	#define CODEC_F00_0A_48KHZ_MULT_8X RT_BIT(11)
133	#define CODEC_F00_0A_48KHZ_MULT_4X RT_BIT(10)
134	#define CODEC_F00_0A_44_1KHZ_MULT_4X RT_BIT(9)
135	#define CODEC_F00_0A_48KHZ_MULT_2X RT_BIT(8)
136	#define CODEC_F00_0A_44_1KHZ_MULT_2X RT_BIT(7)
137	#define CODEC_F00_0A_48KHZ RT_BIT(6)
138	#define CODEC_F00_0A_44_1KHZ RT_BIT(5)
139	/* 2/3 * 48kHz */
140	#define CODEC_F00_0A_48KHZ_2_3X RT_BIT(4)
141	/* 1/2 * 44.1kHz */
142	#define CODEC_F00_0A_44_1KHZ_1_2X RT_BIT(3)
143	/* 1/3 * 48kHz */
144	#define CODEC_F00_0A_48KHZ_1_3X RT_BIT(2)
145	/* 1/4 * 44.1kHz */
146	#define CODEC_F00_0A_44_1KHZ_1_4X RT_BIT(1)
147	/* 1/6 * 48kHz */
148	#define CODEC_F00_0A_48KHZ_1_6X RT_BIT(0)
149
150	/* Supported streams formats (7.3.4.8) */
151	#define CODEC_F00_0B_AC3 RT_BIT(2)
152	#define CODEC_F00_0B_FLOAT32 RT_BIT(1)
153	#define CODEC_F00_0B_PCM RT_BIT(0)
154
155	/* Pin Capabilities (7.3.4.9)*/
156	#define CODEC_MAKE_F00_0C(vref_ctrl) (((vref_ctrl) & 0xFF) << 8)
157	#define CODEC_F00_0C_CAP_HBR RT_BIT(27)
158	#define CODEC_F00_0C_CAP_DP RT_BIT(24)
159	#define CODEC_F00_0C_CAP_EAPD RT_BIT(16)
160	#define CODEC_F00_0C_CAP_HDMI RT_BIT(7)
161	#define CODEC_F00_0C_CAP_BALANCED_IO RT_BIT(6)
162	#define CODEC_F00_0C_CAP_INPUT RT_BIT(5)
163	#define CODEC_F00_0C_CAP_OUTPUT RT_BIT(4)
164	#define CODEC_F00_0C_CAP_HP RT_BIT(3)
165	#define CODEC_F00_0C_CAP_PRESENSE_DETECT RT_BIT(2)
166	#define CODEC_F00_0C_CAP_TRIGGER_REQUIRED RT_BIT(1)
167	#define CODEC_F00_0C_CAP_IMPENDANCE_SENSE RT_BIT(0)
168
169	/* Amplifier capabilities (7.3.4.10) */
170	#define CODEC_MAKE_F00_0D(mute_cap, step_size, num_steps, offset) \
171	( (((mute_cap) & 0x1) << 31) \
172	\| (((step_size) & 0xFF) << 16) \
173	\| (((num_steps) & 0xFF) << 8) \
174	\| ((offset) & 0xFF))
175
176	/* Connection list lenght (7.3.4.11) */
177	#define CODEC_MAKE_F00_0E(long_form, length) \
178	( (((long_form) & 0x1) << 7) \
179	\| ((length) & 0x7F))
180	/* Supported Power States (7.3.4.12) */
181	#define CODEC_F00_0F_EPSS RT_BIT(31)
182	#define CODEC_F00_0F_CLKSTOP RT_BIT(30)
183	#define CODEC_F00_0F_S3D3 RT_BIT(29)
184	#define CODEC_F00_0F_D3COLD RT_BIT(4)
185	#define CODEC_F00_0F_D3 RT_BIT(3)
186	#define CODEC_F00_0F_D2 RT_BIT(2)
187	#define CODEC_F00_0F_D1 RT_BIT(1)
188	#define CODEC_F00_0F_D0 RT_BIT(0)
189
190	/* CP/IO Count (7.3.4.14) */
191	#define CODEC_MAKE_F00_11(wake, unsol, numgpi, numgpo, numgpio) \
192	( (((wake) & 0x1) << 31) \
193	\| (((unsol) & 0x1) << 30) \
194	\| (((numgpi) & 0xFF) << 16) \
195	\| (((numgpo) & 0xFF) << 8) \
196	\| ((numgpio) & 0xFF))
197
198	/* Power States (7.3.3.10) */
199	#define CODEC_MAKE_F05(reset, stopok, error, act, set) \
200	( (((reset) & 0x1) << 10) \
201	\| (((stopok) & 0x1) << 9) \
202	\| (((error) & 0x1) << 8) \
203	\| (((act) & 0x7) << 4) \
204	\| ((set) & 0x7))
205	#define CODEC_F05_D3COLD (4)
206	#define CODEC_F05_D3 (3)
207	#define CODEC_F05_D2 (2)
208	#define CODEC_F05_D1 (1)
209	#define CODEC_F05_D0 (0)
210
211	#define CODEC_F05_IS_RESET(value) (((value) & RT_BIT(10)) != 0)
212	#define CODEC_F05_IS_STOPOK(value) (((value) & RT_BIT(9)) != 0)
213	#define CODEC_F05_IS_ERROR(value) (((value) & RT_BIT(8)) != 0)
214	#define CODEC_F05_ACT(value) (((value) & 0x7) >> 4)
215	#define CODEC_F05_SET(value) (((value) & 0x7))
216
217	/* Converter formats (7.3.3.8) and (3.7.1) */
218	#define CODEC_MAKE_A(fNonPCM, f44_1BaseRate, mult, div, bits, chan) \
219	( (((fNonPCM) & 0x1) << 15) \
220	\| (((f44_1BaseRate) & 0x1) << 14) \
221	\| (((mult) & 0x7) << 11) \
222	\| (((div) & 0x7) << 8) \
223	\| (((bits) & 0x7) << 4) \
224	\| ((chan) & 0xF))
225
226	#define CODEC_A_MULT_1X (0)
227	#define CODEC_A_MULT_2X (1)
228	#define CODEC_A_MULT_3X (2)
229	#define CODEC_A_MULT_4X (3)
230
231	#define CODEC_A_DIV_1X (0)
232	#define CODEC_A_DIV_2X (1)
233	#define CODEC_A_DIV_3X (2)
234	#define CODEC_A_DIV_4X (3)
235	#define CODEC_A_DIV_5X (4)
236	#define CODEC_A_DIV_6X (5)
237	#define CODEC_A_DIV_7X (6)
238	#define CODEC_A_DIV_8X (7)
239
240	#define CODEC_A_8_BIT (0)
241	#define CODEC_A_16_BIT (1)
242	#define CODEC_A_20_BIT (2)
243	#define CODEC_A_24_BIT (3)
244	#define CODEC_A_32_BIT (4)
245
246	/* Pin Sense (7.3.3.15) */
247	#define CODEC_MAKE_F09_ANALOG(fPresent, impedance) \
248	( (((fPresent) & 0x1) << 31) \
249	\| (((impedance) & 0x7FFFFFFF)))
250	#define CODEC_F09_ANALOG_NA 0x7FFFFFFF
251	#define CODEC_MAKE_F09_DIGITAL(fPresent, fELDValid) \
252	( (((fPresent) & 0x1) << 31) \
253	\| (((fELDValid) & 0x1) << 30))
254
255	/* HDA spec 7.3.3.31 defines layout of configuration registers/verbs (0xF1C) */
256	/* Configuration's port connection */
257	#define CODEC_F1C_PORT_MASK (0x3)
258	#define CODEC_F1C_PORT_SHIFT (30)
259
260	#define CODEC_F1C_PORT_COMPLEX (0x0)
261	#define CODEC_F1C_PORT_NO_PHYS (0x1)
262	#define CODEC_F1C_PORT_FIXED (0x2)
263	#define CODEC_F1C_BOTH (0x3)
264
265	/* Configuration's location */
266	#define CODEC_F1C_LOCATION_MASK (0x3F)
267	#define CODEC_F1C_LOCATION_SHIFT (24)
268	/* [4:5] bits of location region means chassis attachment */
269	#define CODEC_F1C_LOCATION_PRIMARY_CHASSIS (0)
270	#define CODEC_F1C_LOCATION_INTERNAL RT_BIT(4)
271	#define CODEC_F1C_LOCATION_SECONDRARY_CHASSIS RT_BIT(5)
272	#define CODEC_F1C_LOCATION_OTHER (RT_BIT(5))
273
274	/* [0:3] bits of location region means geometry location attachment */
275	#define CODEC_F1C_LOCATION_NA (0)
276	#define CODEC_F1C_LOCATION_REAR (0x1)
277	#define CODEC_F1C_LOCATION_FRONT (0x2)
278	#define CODEC_F1C_LOCATION_LEFT (0x3)
279	#define CODEC_F1C_LOCATION_RIGTH (0x4)
280	#define CODEC_F1C_LOCATION_TOP (0x5)
281	#define CODEC_F1C_LOCATION_BOTTOM (0x6)
282	#define CODEC_F1C_LOCATION_SPECIAL_0 (0x7)
283	#define CODEC_F1C_LOCATION_SPECIAL_1 (0x8)
284	#define CODEC_F1C_LOCATION_SPECIAL_3 (0x9)
285
286	/* Configuration's devices */
287	#define CODEC_F1C_DEVICE_MASK (0xF)
288	#define CODEC_F1C_DEVICE_SHIFT (20)
289	#define CODEC_F1C_DEVICE_LINE_OUT (0)
290	#define CODEC_F1C_DEVICE_SPEAKER (0x1)
291	#define CODEC_F1C_DEVICE_HP (0x2)
292	#define CODEC_F1C_DEVICE_CD (0x3)
293	#define CODEC_F1C_DEVICE_SPDIF_OUT (0x4)
294	#define CODEC_F1C_DEVICE_DIGITAL_OTHER_OUT (0x5)
295	#define CODEC_F1C_DEVICE_MODEM_LINE_SIDE (0x6)
296	#define CODEC_F1C_DEVICE_MODEM_HANDSET_SIDE (0x7)
297	#define CODEC_F1C_DEVICE_LINE_IN (0x8)
298	#define CODEC_F1C_DEVICE_AUX (0x9)
299	#define CODEC_F1C_DEVICE_MIC (0xA)
300	#define CODEC_F1C_DEVICE_PHONE (0xB)
301	#define CODEC_F1C_DEVICE_SPDIF_IN (0xC)
302	#define CODEC_F1C_DEVICE_RESERVED (0xE)
303	#define CODEC_F1C_DEVICE_OTHER (0xF)
304
305	/* Configuration's Connection type */
306	#define CODEC_F1C_CONNECTION_TYPE_MASK (0xF)
307	#define CODEC_F1C_CONNECTION_TYPE_SHIFT (16)
308
309	#define CODEC_F1C_CONNECTION_TYPE_UNKNOWN (0)
310	#define CODEC_F1C_CONNECTION_TYPE_1_8INCHES (0x1)
311	#define CODEC_F1C_CONNECTION_TYPE_1_4INCHES (0x2)
312	#define CODEC_F1C_CONNECTION_TYPE_ATAPI (0x3)
313	#define CODEC_F1C_CONNECTION_TYPE_RCA (0x4)
314	#define CODEC_F1C_CONNECTION_TYPE_OPTICAL (0x5)
315	#define CODEC_F1C_CONNECTION_TYPE_OTHER_DIGITAL (0x6)
316	#define CODEC_F1C_CONNECTION_TYPE_ANALOG (0x7)
317	#define CODEC_F1C_CONNECTION_TYPE_DIN (0x8)
318	#define CODEC_F1C_CONNECTION_TYPE_XLR (0x9)
319	#define CODEC_F1C_CONNECTION_TYPE_RJ_11 (0xA)
320	#define CODEC_F1C_CONNECTION_TYPE_COMBO (0xB)
321	#define CODEC_F1C_CONNECTION_TYPE_OTHER (0xF)
322
323	/* Configuration's color */
324	#define CODEC_F1C_COLOR_MASK (0xF)
325	#define CODEC_F1C_COLOR_SHIFT (12)
326	#define CODEC_F1C_COLOR_UNKNOWN (0)
327	#define CODEC_F1C_COLOR_BLACK (0x1)
328	#define CODEC_F1C_COLOR_GREY (0x2)
329	#define CODEC_F1C_COLOR_BLUE (0x3)
330	#define CODEC_F1C_COLOR_GREEN (0x4)
331	#define CODEC_F1C_COLOR_RED (0x5)
332	#define CODEC_F1C_COLOR_ORANGE (0x6)
333	#define CODEC_F1C_COLOR_YELLOW (0x7)
334	#define CODEC_F1C_COLOR_PURPLE (0x8)
335	#define CODEC_F1C_COLOR_PINK (0x9)
336	#define CODEC_F1C_COLOR_RESERVED_0 (0xA)
337	#define CODEC_F1C_COLOR_RESERVED_1 (0xB)
338	#define CODEC_F1C_COLOR_RESERVED_2 (0xC)
339	#define CODEC_F1C_COLOR_RESERVED_3 (0xD)
340	#define CODEC_F1C_COLOR_WHITE (0xE)
341	#define CODEC_F1C_COLOR_OTHER (0xF)
342
343	/* Configuration's misc */
344	#define CODEC_F1C_MISC_MASK (0xF)
345	#define CODEC_F1C_MISC_SHIFT (8)
346	#define CODEC_F1C_MISC_JACK_DETECT RT_BIT(0)
347	#define CODEC_F1C_MISC_RESERVED_0 RT_BIT(1)
348	#define CODEC_F1C_MISC_RESERVED_1 RT_BIT(2)
349	#define CODEC_F1C_MISC_RESERVED_2 RT_BIT(3)
350
351	/* Configuration's association */
352	#define CODEC_F1C_ASSOCIATION_MASK (0xF)
353	#define CODEC_F1C_ASSOCIATION_SHIFT (4)
354	/* Connection's sequence */
355	#define CODEC_F1C_SEQ_MASK (0xF)
356	#define CODEC_F1C_SEQ_SHIFT (0)
357
358	/* Implementation identification (7.3.3.30) */
359	#define CODEC_MAKE_F20(bmid, bsku, aid) \
360	( (((bmid) & 0xFFFF) << 16) \
361	\| (((bsku) & 0xFF) << 8) \
362	\| (((aid) & 0xFF)) \
363	)
364
365	/* macro definition helping in filling the configuration registers. */
366	#define CODEC_MAKE_F1C(port_connectivity, location, device, connection_type, color, misc, association, sequence) \
367	( ((port_connectivity) << CODEC_F1C_PORT_SHIFT) \
368	\| ((location) << CODEC_F1C_LOCATION_SHIFT) \
369	\| ((device) << CODEC_F1C_DEVICE_SHIFT) \
370	\| ((connection_type) << CODEC_F1C_CONNECTION_TYPE_SHIFT) \
371	\| ((color) << CODEC_F1C_COLOR_SHIFT) \
372	\| ((misc) << CODEC_F1C_MISC_SHIFT) \
373	\| ((association) << CODEC_F1C_ASSOCIATION_SHIFT) \
374	\| ((sequence)))
375
376	/* STAC9220 */
377	const static uint8_t au8Stac9220Ports[] = { 0xA, 0xB, 0xC, 0xD, 0xE, 0xF, 0};
378	const static uint8_t au8Stac9220Dacs[] = { 0x2, 0x3, 0x4, 0x5, 0};
379	const static uint8_t au8Stac9220Adcs[] = { 0x6, 0x7, 0};
380	const static uint8_t au8Stac9220SpdifOuts[] = { 0x8, 0 };
381	const static uint8_t au8Stac9220SpdifIns[] = { 0x9, 0 };
382	const static uint8_t au8Stac9220DigOutPins[] = { 0x10, 0 };
383	const static uint8_t au8Stac9220DigInPins[] = { 0x11, 0 };
384	const static uint8_t au8Stac9220AdcVols[] = { 0x17, 0x18, 0};
385	const static uint8_t au8Stac9220AdcMuxs[] = { 0x12, 0x13, 0};
386	const static uint8_t au8Stac9220Pcbeeps[] = { 0x14, 0 };
387	const static uint8_t au8Stac9220Cds[] = { 0x15, 0 };
388	const static uint8_t au8Stac9220VolKnobs[] = { 0x16, 0 };
389	const static uint8_t au8Stac9220Reserveds[] = { 0x9, 0x19, 0x1a, 0x1b, 0 };
390
391	static int stac9220ResetNode(struct CODECState *pState, uint8_t nodenum, PCODECNODE pNode);
392
393	static int stac9220Construct(CODECState *pState)
394	{
395	unconst(pState->cTotalNodes) = 0x1C;
396	pState->pfnCodecNodeReset = stac9220ResetNode;
397	pState->u16VendorId = 0x8384;
398	pState->u16DeviceId = 0x7680;
399	pState->u8BSKU = 0x76;
400	pState->u8AssemblyId = 0x80;
401	pState->pNodes = (PCODECNODE)RTMemAllocZ(sizeof(CODECNODE) * pState->cTotalNodes);
402	pState->fInReset = false;
403	#define STAC9220WIDGET(type) pState->au8##type##s = au8Stac9220##type##s
404	STAC9220WIDGET(Port);
405	STAC9220WIDGET(Dac);
406	STAC9220WIDGET(Adc);
407	STAC9220WIDGET(AdcVol);
408	STAC9220WIDGET(AdcMux);
409	STAC9220WIDGET(Pcbeep);
410	STAC9220WIDGET(SpdifIn);
411	STAC9220WIDGET(SpdifOut);
412	STAC9220WIDGET(DigInPin);
413	STAC9220WIDGET(DigOutPin);
414	STAC9220WIDGET(Cd);
415	STAC9220WIDGET(VolKnob);
416	STAC9220WIDGET(Reserved);
417	#undef STAC9220WIDGET
418	unconst(pState->u8AdcVolsLineIn) = 0x17;
419	unconst(pState->u8DacLineOut) = 0x2;
420
421	return VINF_SUCCESS;
422	}
423
424	static int stac9220ResetNode(struct CODECState *pState, uint8_t nodenum, PCODECNODE pNode)
425	{
426	pNode->node.id = nodenum;
427	pNode->node.au32F00_param[0xF] = 0; /* Power statest Supported: are the same as AFG reports */
428	switch (nodenum)
429	{
430	/* Root Node*/
431	case 0:
432	pNode->root.node.name = "Root";
433	pNode->node.au32F00_param[2] = CODEC_MAKE_F00_02(0x1, 0x0, 0x34, 0x1); /* rev id */
434	break;
435	case 1:
436	pNode->afg.node.name = "AFG";
437	pNode->node.au32F00_param[8] = CODEC_MAKE_F00_08(CODEC_F00_08_BEEP_GEN, 0xd, 0xd);
438	pNode->node.au32F00_param[0xC] = CODEC_MAKE_F00_0C(0x17)
439	\| CODEC_F00_0C_CAP_BALANCED_IO
440	\| CODEC_F00_0C_CAP_INPUT
441	\| CODEC_F00_0C_CAP_PRESENSE_DETECT
442	\| CODEC_F00_0C_CAP_TRIGGER_REQUIRED
443	\| CODEC_F00_0C_CAP_IMPENDANCE_SENSE;//(17 << 8)\|RT_BIT(6)\|RT_BIT(5)\|RT_BIT(2)\|RT_BIT(1)\|RT_BIT(0);
444	pNode->node.au32F00_param[0xB] = CODEC_F00_0B_PCM;
445	pNode->node.au32F00_param[0xD] = CODEC_MAKE_F00_0D(1, 0x5, 0xE, 0);//RT_BIT(31)\|(0x5 << 16)\|(0xE)<<8;
446	pNode->node.au32F00_param[0x12] = RT_BIT(31)\|(0x2 << 16)\|(0x7f << 8)\|0x7f;
447	pNode->node.au32F00_param[0x11] = CODEC_MAKE_F00_11(1, 1, 0, 0, 4);//0xc0000004;
448	pNode->node.au32F00_param[0xF] = CODEC_F00_0F_D3\|CODEC_F00_0F_D2\|CODEC_F00_0F_D1\|CODEC_F00_0F_D0;
449	pNode->afg.u32F05_param = CODEC_MAKE_F05(0, 0, 0, CODEC_F05_D2, CODEC_F05_D2);//0x2 << 4\| 0x2; /* PS-Act: D3, PS->Set D3 */
450	pNode->afg.u32F08_param = 0;
451	pNode->afg.u32F17_param = 0;
452	break;
453	case 2:
454	pNode->dac.node.name = "DAC0";
455	goto dac_init;
456	case 3:
457	pNode->dac.node.name = "DAC1";
458	goto dac_init;
459	case 4:
460	pNode->dac.node.name = "DAC2";
461	goto dac_init;
462	case 5:
463	pNode->dac.node.name = "DAC3";
464	dac_init:
465	memset(pNode->dac.B_params, 0, AMPLIFIER_SIZE);
466	pNode->dac.u32A_param = CODEC_MAKE_A(0, 1, CODEC_A_MULT_1X, CODEC_A_DIV_1X, CODEC_A_16_BIT, 1);//RT_BIT(14)\|(0x1 << 4)\|0x1; /* 441000Hz/16bit/2ch */
467
468	AMPLIFIER_REGISTER(pNode->dac.B_params, AMPLIFIER_OUT, AMPLIFIER_LEFT, 0) = 0x7F \| RT_BIT(7);
469	AMPLIFIER_REGISTER(pNode->dac.B_params, AMPLIFIER_OUT, AMPLIFIER_RIGHT, 0) = 0x7F \| RT_BIT(7);
470
471	pNode->dac.node.au32F00_param[9] = CODEC_MAKE_F00_09(CODEC_F00_09_TYPE_AUDIO_OUTPUT, 0xD, 0)
472	\| CODEC_F00_09_CAP_L_R_SWAP
473	\| CODEC_F00_09_CAP_POWER_CTRL
474	\| CODEC_F00_09_CAP_OUT_AMP_PRESENT
475	\| CODEC_F00_09_CAP_LSB;//(0xD << 16) \| RT_BIT(11) \| RT_BIT(10) \| RT_BIT(2) \| RT_BIT(0);
476	pNode->dac.u32F0c_param = 0;
477	pNode->dac.u32F05_param = CODEC_MAKE_F05(0, 0, 0, CODEC_F05_D3, CODEC_F05_D3);//0x3 << 4 \| 0x3; /* PS-Act: D3, Set: D3 */
478	break;
479	case 6:
480	pNode->adc.node.name = "ADC0";
481	pNode->node.au32F02_param[0] = 0x17;
482	goto adc_init;
483	case 7:
484	pNode->adc.node.name = "ADC1";
485	pNode->node.au32F02_param[0] = 0x18;
486	adc_init:
487	pNode->adc.u32A_param = CODEC_MAKE_A(0, 1, CODEC_A_MULT_1X, CODEC_A_DIV_1X, CODEC_A_16_BIT, 1);//RT_BIT(14)\|(0x1 << 3)\|0x1; /* 441000Hz/16bit/2ch */
488	pNode->adc.node.au32F00_param[0xE] = CODEC_MAKE_F00_0E(0, 1);//RT_BIT(0);
489	pNode->adc.u32F03_param = RT_BIT(0);
490	pNode->adc.u32F05_param = CODEC_MAKE_F05(0, 0, 0, CODEC_F05_D3, CODEC_F05_D3);//0x3 << 4 \| 0x3; /* PS-Act: D3 Set: D3 */
491	pNode->adc.u32F06_param = 0;
492	pNode->adc.node.au32F00_param[9] = CODEC_MAKE_F00_09(CODEC_F00_09_TYPE_AUDIO_INPUT, 0xD, 0)
493	\| CODEC_F00_09_CAP_POWER_CTRL
494	\| CODEC_F00_09_CAP_CONNECTION_LIST
495	\| CODEC_F00_09_CAP_PROC_WIDGET
496	\| CODEC_F00_09_CAP_LSB;//RT_BIT(20)\| (0xd << 16) \| RT_BIT(10) \| RT_BIT(8) \| RT_BIT(6)\| RT_BIT(0);
497	break;
498	case 8:
499	pNode->spdifout.node.name = "SPDIFOut";
500	pNode->spdifout.u32A_param = CODEC_MAKE_A(0, 1, CODEC_A_MULT_1X, CODEC_A_DIV_1X, CODEC_A_16_BIT, 1);//(1<<14)\|(0x1<<4) \| 0x1;
501	pNode->spdifout.node.au32F00_param[9] = CODEC_MAKE_F00_09(CODEC_F00_09_TYPE_AUDIO_OUTPUT, 0x4, 0)
502	\| CODEC_F00_09_CAP_DIGITAL
503	\| CODEC_F00_09_CAP_FMT_OVERRIDE
504	\| CODEC_F00_09_CAP_LSB;//(4 << 16) \| RT_BIT(9)\|RT_BIT(4)\|0x1;
505	pNode->node.au32F00_param[0xa] = pState->pNodes[1].node.au32F00_param[0xA];
506	pNode->spdifout.node.au32F00_param[0xB] = CODEC_F00_0B_PCM;
507	pNode->spdifout.u32F06_param = 0;
508	pNode->spdifout.u32F0d_param = 0;
509	break;
510	case 9:
511	pNode->node.name = "Reserved_0";
512	pNode->spdifin.u32A_param = CODEC_MAKE_A(0, 1, CODEC_A_MULT_1X, CODEC_A_DIV_1X, CODEC_A_16_BIT, 1);//(0x1<<4) \| 0x1;
513	pNode->spdifin.node.au32F00_param[9] = CODEC_MAKE_F00_09(CODEC_F00_09_TYPE_AUDIO_INPUT, 0x4, 0)
514	\| CODEC_F00_09_CAP_DIGITAL
515	\| CODEC_F00_09_CAP_CONNECTION_LIST
516	\| CODEC_F00_09_CAP_FMT_OVERRIDE
517	\| CODEC_F00_09_CAP_LSB;//(0x1 << 20)\|(4 << 16) \| RT_BIT(9)\| RT_BIT(8)\|RT_BIT(4)\|0x1;
518	pNode->node.au32F00_param[0xA] = pState->pNodes[1].node.au32F00_param[0xA];
519	pNode->node.au32F00_param[0xE] = CODEC_MAKE_F00_0E(0, 1);//RT_BIT(0);
520	pNode->node.au32F02_param[0] = 0x11;
521	pNode->spdifin.node.au32F00_param[0xB] = CODEC_F00_0B_PCM;
522	pNode->spdifin.u32F06_param = 0;
523	pNode->spdifin.u32F0d_param = 0;
524	break;
525	case 0xA:
526	pNode->node.name = "PortA";
527	pNode->node.au32F00_param[0xC] = CODEC_MAKE_F00_0C(0x17)
528	\| CODEC_F00_0C_CAP_INPUT
529	\| CODEC_F00_0C_CAP_OUTPUT
530	\| CODEC_F00_0C_CAP_HP
531	\| CODEC_F00_0C_CAP_PRESENSE_DETECT
532	\| CODEC_F00_0C_CAP_TRIGGER_REQUIRED
533	\| CODEC_F00_0C_CAP_IMPENDANCE_SENSE;//0x173f;
534	pNode->node.au32F02_param[0] = 0x2;
535	pNode->port.u32F07_param = 0xc0;//RT_BIT(6);
536	pNode->port.u32F08_param = 0;
537	if (!pState->fInReset)
538	pNode->port.u32F1c_param = CODEC_MAKE_F1C(CODEC_F1C_PORT_COMPLEX,
539	CODEC_F1C_LOCATION_FRONT,
540	CODEC_F1C_DEVICE_HP,
541	CODEC_F1C_CONNECTION_TYPE_1_8INCHES,
542	CODEC_F1C_COLOR_GREEN,
543	CODEC_F1C_MISC_JACK_DETECT,
544	0x2, 0);//RT_MAKE_U32_FROM_U8(0x20, 0x40, 0x21, 0x02);
545	goto port_init;
546	case 0xB:
547	pNode->node.name = "PortB";
548	pNode->node.au32F00_param[0xC] = CODEC_MAKE_F00_0C(0x17)
549	\| CODEC_F00_0C_CAP_INPUT
550	\| CODEC_F00_0C_CAP_OUTPUT
551	\| CODEC_F00_0C_CAP_PRESENSE_DETECT
552	\| CODEC_F00_0C_CAP_TRIGGER_REQUIRED
553	\| CODEC_F00_0C_CAP_IMPENDANCE_SENSE;//0x1737;
554	pNode->node.au32F02_param[0] = 0x4;
555	pNode->port.u32F07_param = RT_BIT(5);
556	if (!pState->fInReset)
557	pNode->port.u32F1c_param = CODEC_MAKE_F1C(CODEC_F1C_PORT_COMPLEX,
558	CODEC_F1C_LOCATION_INTERNAL\|CODEC_F1C_LOCATION_REAR,
559	CODEC_F1C_DEVICE_SPEAKER,
560	CODEC_F1C_CONNECTION_TYPE_1_8INCHES,
561	CODEC_F1C_COLOR_BLACK,
562	CODEC_F1C_MISC_JACK_DETECT,
563	0x1, 0x1);//RT_MAKE_U32_FROM_U8(0x11, 0x60, 0x11, 0x01);
564	goto port_init;
565	case 0xC:
566	pNode->node.name = "PortC";
567	pNode->node.au32F02_param[0] = 0x3;
568	pNode->node.au32F00_param[0xC] = CODEC_MAKE_F00_0C(0x17)
569	\| CODEC_F00_0C_CAP_INPUT
570	\| CODEC_F00_0C_CAP_OUTPUT
571	\| CODEC_F00_0C_CAP_PRESENSE_DETECT
572	\| CODEC_F00_0C_CAP_TRIGGER_REQUIRED
573	\| CODEC_F00_0C_CAP_IMPENDANCE_SENSE;//0x1737;
574	pNode->port.u32F07_param = RT_BIT(5);
575	if (!pState->fInReset)
576	pNode->port.u32F1c_param = CODEC_MAKE_F1C(CODEC_F1C_PORT_COMPLEX,
577	CODEC_F1C_LOCATION_REAR,
578	CODEC_F1C_DEVICE_SPEAKER,
579	CODEC_F1C_CONNECTION_TYPE_1_8INCHES,
580	CODEC_F1C_COLOR_GREEN,
581	0x0, 0x1, 0x0);//RT_MAKE_U32_FROM_U8(0x10, 0x40, 0x11, 0x01);
582	goto port_init;
583	case 0xD:
584	pNode->node.name = "PortD";
585	pNode->node.au32F00_param[0xC] = CODEC_MAKE_F00_0C(0x17)
586	\| CODEC_F00_0C_CAP_INPUT
587	\| CODEC_F00_0C_CAP_OUTPUT
588	\| CODEC_F00_0C_CAP_PRESENSE_DETECT
589	\| CODEC_F00_0C_CAP_TRIGGER_REQUIRED
590	\| CODEC_F00_0C_CAP_IMPENDANCE_SENSE;//0x1737;
591	pNode->port.u32F07_param = RT_BIT(5);
592	pNode->node.au32F02_param[0] = 0x2;
593	if (!pState->fInReset)
594	pNode->port.u32F1c_param = CODEC_MAKE_F1C(CODEC_F1C_PORT_COMPLEX,
595	CODEC_F1C_LOCATION_FRONT,
596	CODEC_F1C_DEVICE_MIC,
597	CODEC_F1C_CONNECTION_TYPE_1_8INCHES,
598	CODEC_F1C_COLOR_PINK,
599	0x0, 0x5, 0x0);//RT_MAKE_U32_FROM_U8(0x50, 0x90, 0xA1, 0x02); /* Microphone */
600	port_init:
601	pNode->port.u32F09_param = CODEC_MAKE_F09_ANALOG(1, CODEC_F09_ANALOG_NA);//RT_BIT(31)\|0x7fffffff;
602	pNode->port.u32F08_param = 0;
603	pNode->node.au32F00_param[9] = CODEC_MAKE_F00_09(CODEC_F00_09_TYPE_PIN_COMPLEX, 0x0, 0)
604	\| CODEC_F00_09_CAP_CONNECTION_LIST
605	\| CODEC_F00_09_CAP_UNSOL
606	\| CODEC_F00_09_CAP_LSB;//(4 << 20)\|RT_BIT(8)\|RT_BIT(7)\|RT_BIT(0);
607	pNode->node.au32F00_param[0xE] = CODEC_MAKE_F00_0E(0, 1);//0x1;
608	break;
609	case 0xE:
610	pNode->node.name = "PortE";
611	pNode->node.au32F00_param[9] = CODEC_MAKE_F00_09(CODEC_F00_09_TYPE_PIN_COMPLEX, 0x0, 0)
612	\| CODEC_F00_09_CAP_UNSOL
613	\| CODEC_F00_09_CAP_LSB;//(4 << 20)\|RT_BIT(7)\|RT_BIT(0);
614	pNode->port.u32F08_param = 0;
615	pNode->node.au32F00_param[0xC] = CODEC_F00_0C_CAP_INPUT
616	\| CODEC_F00_0C_CAP_OUTPUT
617	\| CODEC_F00_0C_CAP_PRESENSE_DETECT;//0x34;
618	pNode->port.u32F07_param = RT_BIT(5);
619	pNode->port.u32F09_param = CODEC_MAKE_F09_ANALOG(0, CODEC_F09_ANALOG_NA);//0x7fffffff;
620	if (!pState->fInReset)
621	pNode->port.u32F1c_param = CODEC_MAKE_F1C(CODEC_F1C_PORT_COMPLEX,
622	CODEC_F1C_LOCATION_REAR,
623	CODEC_F1C_DEVICE_LINE_OUT,
624	CODEC_F1C_CONNECTION_TYPE_1_8INCHES,
625	CODEC_F1C_COLOR_BLUE,
626	0x0, 0x4, 0x0);//0x01013040; /* Line Out */
627	break;
628	case 0xF:
629	pNode->node.name = "PortF";
630	pNode->node.au32F00_param[9] = CODEC_MAKE_F00_09(CODEC_F00_09_TYPE_PIN_COMPLEX, 0x0, 0x0)
631	\| CODEC_F00_09_CAP_CONNECTION_LIST
632	\| CODEC_F00_09_CAP_UNSOL
633	\| CODEC_F00_09_CAP_OUT_AMP_PRESENT
634	\| CODEC_F00_09_CAP_LSB;//(4 << 20)\|RT_BIT(8)\|RT_BIT(7)\|RT_BIT(2)\|RT_BIT(0);
635	pNode->node.au32F00_param[0xC] = CODEC_F00_0C_CAP_INPUT
636	\| CODEC_F00_0C_CAP_OUTPUT
637	\| CODEC_F00_0C_CAP_PRESENSE_DETECT
638	\| CODEC_F00_0C_CAP_TRIGGER_REQUIRED
639	\| CODEC_F00_0C_CAP_IMPENDANCE_SENSE;//0x37;
640	pNode->node.au32F00_param[0xE] = CODEC_MAKE_F00_0E(0, 1);//0x1;
641	pNode->port.u32F08_param = 0;
642	pNode->port.u32F07_param = 0x40;
643	if (!pState->fInReset)
644	pNode->port.u32F1c_param = CODEC_MAKE_F1C(CODEC_F1C_PORT_COMPLEX,
645	CODEC_F1C_LOCATION_REAR,
646	CODEC_F1C_DEVICE_SPEAKER,
647	CODEC_F1C_CONNECTION_TYPE_1_8INCHES,
648	CODEC_F1C_COLOR_ORANGE,
649	0x0, 0x1, 0x2);//RT_MAKE_U32_FROM_U8(0x12, 0x60, 0x11, 0x01);
650	pNode->node.au32F02_param[0] = 0x5;
651	pNode->port.u32F09_param = CODEC_MAKE_F09_ANALOG(0, CODEC_F09_ANALOG_NA);//0x7fffffff;
652	break;
653	case 0x10:
654	pNode->node.name = "DigOut_0";
655	pNode->node.au32F00_param[9] = CODEC_MAKE_F00_09(CODEC_F00_09_TYPE_PIN_COMPLEX, 0x0, 0x0)
656	\| CODEC_F00_09_CAP_DIGITAL
657	\| CODEC_F00_09_CAP_CONNECTION_LIST
658	\| CODEC_F00_09_CAP_LSB;//(4<<20)\|RT_BIT(9)\|RT_BIT(8)\|RT_BIT(0);
659	pNode->node.au32F00_param[0xC] = CODEC_F00_0C_CAP_OUTPUT;//RT_BIT(4);
660	pNode->node.au32F00_param[0xE] = CODEC_MAKE_F00_0E(0, 0x3);
661	pNode->digout.u32F01_param = 0;
662	pNode->node.au32F02_param[0] = RT_MAKE_U32_FROM_U8(0x08, 0x17, 0x19, 0);
663	pNode->digout.u32F07_param = 0;
664	if (!pState->fInReset)
665	pNode->digout.u32F1c_param = CODEC_MAKE_F1C(CODEC_F1C_PORT_COMPLEX,
666	CODEC_F1C_LOCATION_REAR,
667	CODEC_F1C_DEVICE_SPDIF_OUT,
668	CODEC_F1C_CONNECTION_TYPE_DIN,
669	CODEC_F1C_COLOR_BLACK,
670	0x0, 0x3, 0x0);//RT_MAKE_U32_FROM_U8(0x30, 0x10, 0x45, 0x01);
671	break;
672	case 0x11:
673	pNode->node.name = "DigIn_0";
674	pNode->node.au32F00_param[9] = (4 << 20)\|(3<<16)\|RT_BIT(10)\|RT_BIT(9)\|RT_BIT(7)\|RT_BIT(0);
675	pNode->node.au32F00_param[0xC] = CODEC_F00_0C_CAP_EAPD
676	\| CODEC_F00_0C_CAP_INPUT
677	\| CODEC_F00_0C_CAP_PRESENSE_DETECT;//RT_BIT(16)\| RT_BIT(5)\|RT_BIT(2);
678	pNode->digin.u32F05_param = CODEC_MAKE_F05(0, 0, 0, CODEC_F05_D3, CODEC_F05_D3);//0x3 << 4 \| 0x3; /* PS-Act: D3 -> D3 */
679	pNode->digin.u32F07_param = 0;
680	pNode->digin.u32F08_param = 0;
681	pNode->digin.u32F09_param = 0;
682	pNode->digin.u32F0c_param = 0;
683	if (!pState->fInReset)
684	pNode->digin.u32F1c_param = CODEC_MAKE_F1C(CODEC_F1C_PORT_COMPLEX,
685	CODEC_F1C_LOCATION_REAR,
686	CODEC_F1C_DEVICE_SPDIF_IN,
687	CODEC_F1C_CONNECTION_TYPE_OTHER_DIGITAL,
688	CODEC_F1C_COLOR_BLACK,
689	0x0, 0x6, 0x0);//(0x1 << 24) \| (0xc5 << 16) \| (0x10 << 8) \| 0x60;
690	break;
691	case 0x12:
692	pNode->node.name = "ADCMux_0";
693	pNode->adcmux.u32F01_param = 0;
694	goto adcmux_init;
695	case 0x13:
696	pNode->node.name = "ADCMux_1";
697	pNode->adcmux.u32F01_param = 1;
698	adcmux_init:
699	pNode->node.au32F00_param[9] = CODEC_MAKE_F00_09(CODEC_F00_09_TYPE_AUDIO_SELECTOR, 0x0, 0)
700	\| CODEC_F00_09_CAP_CONNECTION_LIST
701	\| CODEC_F00_09_CAP_AMP_FMT_OVERRIDE
702	\| CODEC_F00_09_CAP_OUT_AMP_PRESENT
703	\| CODEC_F00_09_CAP_LSB;//(3<<20)\|RT_BIT(8)\|RT_BIT(3)\|RT_BIT(2)\|RT_BIT(0);
704	pNode->node.au32F00_param[0xe] = CODEC_MAKE_F00_0E(0, 0x7);
705	pNode->node.au32F00_param[0x12] = (0x27 << 16)\|(0x4 << 8);
706	/* STAC 9220 v10 6.21-22.{4,5} both(left and right) out amplefiers inited with 0*/
707	memset(pNode->adcmux.B_params, 0, AMPLIFIER_SIZE);
708	pNode->node.au32F02_param[0] = RT_MAKE_U32_FROM_U8(0xe, 0x15, 0xf, 0xb);
709	pNode->node.au32F02_param[4] = RT_MAKE_U32_FROM_U8(0xc, 0xd, 0xa, 0x0);
710	break;
711	case 0x14:
712	pNode->node.name = "PCBEEP";
713	pNode->node.au32F00_param[9] = CODEC_MAKE_F00_09(CODEC_F00_09_TYPE_BEEP_GEN, 0, 0)
714	\| CODEC_F00_09_CAP_AMP_FMT_OVERRIDE
715	\| CODEC_F00_09_CAP_OUT_AMP_PRESENT;//(7 << 20) \| RT_BIT(3) \| RT_BIT(2);
716	pNode->node.au32F00_param[0x12] = (0x17 << 16)\|(0x3 << 8)\| 0x3;
717	pNode->pcbeep.u32F0a_param = 0;
718	memset(pNode->pcbeep.B_params, 0, AMPLIFIER_SIZE);
719	break;
720	case 0x15:
721	pNode->node.name = "CD";
722	pNode->node.au32F00_param[0x9] = CODEC_MAKE_F00_09(CODEC_F00_09_TYPE_PIN_COMPLEX, 0, 0)
723	\| CODEC_F00_09_CAP_LSB;//(4 << 20)\|RT_BIT(0);
724	pNode->node.au32F00_param[0xc] = CODEC_F00_0C_CAP_INPUT;//RT_BIT(5);
725	pNode->cdnode.u32F07_param = 0;
726	if (!pState->fInReset)
727	pNode->cdnode.u32F1c_param = CODEC_MAKE_F1C(CODEC_F1C_PORT_FIXED,
728	CODEC_F1C_LOCATION_INTERNAL,
729	CODEC_F1C_DEVICE_CD,
730	CODEC_F1C_CONNECTION_TYPE_ATAPI,
731	CODEC_F1C_COLOR_UNKNOWN,
732	0x0, 0x7, 0x0);//RT_MAKE_U32_FROM_U8(0x70, 0x0, 0x33, 0x90);
733	break;
734	case 0x16:
735	pNode->node.name = "VolumeKnob";
736	pNode->node.au32F00_param[0x9] = CODEC_MAKE_F00_09(CODEC_F00_09_TYPE_VOLUME_KNOB, 0x0, 0x0);//(0x6 << 20);
737	pNode->node.au32F00_param[0x13] = RT_BIT(7)\| 0x7F;
738	pNode->node.au32F00_param[0xe] = CODEC_MAKE_F00_0E(0, 0x4);
739	pNode->node.au32F02_param[0] = RT_MAKE_U32_FROM_U8(0x2, 0x3, 0x4, 0x5);
740	pNode->volumeKnob.u32F08_param = 0;
741	pNode->volumeKnob.u32F0f_param = 0x7f;
742	break;
743	case 0x17:
744	pNode->node.name = "ADC0Vol";
745	pNode->node.au32F02_param[0] = 0x12;
746	goto adcvol_init;
747	case 0x18:
748	pNode->node.name = "ADC1Vol";
749	pNode->node.au32F02_param[0] = 0x13;
750	adcvol_init:
751	memset(pNode->adcvol.B_params, 0, AMPLIFIER_SIZE);
752
753	pNode->node.au32F00_param[0x9] = CODEC_MAKE_F00_09(CODEC_F00_09_TYPE_AUDIO_SELECTOR, 0, 0)
754	\| CODEC_F00_09_CAP_L_R_SWAP
755	\| CODEC_F00_09_CAP_CONNECTION_LIST
756	\| CODEC_F00_09_CAP_IN_AMP_PRESENT
757	\| CODEC_F00_09_CAP_LSB;//(0x3 << 20)\|RT_BIT(11)\|RT_BIT(8)\|RT_BIT(1)\|RT_BIT(0);
758	pNode->node.au32F00_param[0xe] = CODEC_MAKE_F00_0E(0, 0x1);
759	AMPLIFIER_REGISTER(pNode->adcvol.B_params, AMPLIFIER_IN, AMPLIFIER_LEFT, 0) = RT_BIT(7);
760	AMPLIFIER_REGISTER(pNode->adcvol.B_params, AMPLIFIER_IN, AMPLIFIER_RIGHT, 0) = RT_BIT(7);
761	pNode->adcvol.u32F0c_param = 0;
762	break;
763	case 0x19:
764	pNode->node.name = "Reserved_1";
765	pNode->node.au32F00_param[0x9] = CODEC_MAKE_F00_09(CODEC_F00_09_TYPE_VENDOR_DEFINED, 0x3, 0)
766	\| CODEC_F00_09_CAP_DIGITAL
767	\| CODEC_F00_09_CAP_LSB;//(0xF << 20)\|(0x3 << 16)\|RT_BIT(9)\|RT_BIT(0);
768	break;
769	case 0x1A:
770	pNode->node.name = "Reserved_2";
771	pNode->node.au32F00_param[0x9] = CODEC_MAKE_F00_09(CODEC_F00_09_TYPE_AUDIO_OUTPUT, 0x3, 0)
772	\| CODEC_F00_09_CAP_DIGITAL
773	\| CODEC_F00_09_CAP_LSB;//(0x3 << 16)\|RT_BIT(9)\|RT_BIT(0);
774	break;
775	case 0x1B:
776	pNode->node.name = "Reserved_3";
777	pNode->node.au32F00_param[0x9] = CODEC_MAKE_F00_09(CODEC_F00_09_TYPE_PIN_COMPLEX, 0, 0)
778	\| CODEC_F00_09_CAP_DIGITAL
779	\| CODEC_F00_09_CAP_CONNECTION_LIST
780	\| CODEC_F00_09_CAP_LSB;//(0x4 << 20)\|RT_BIT(9)\|RT_BIT(8)\|RT_BIT(0);
781	pNode->node.au32F00_param[0xE] = CODEC_MAKE_F00_0E(0, 0x1);
782	pNode->node.au32F00_param[0xC] = CODEC_F00_0C_CAP_OUTPUT;//0x10;
783	pNode->node.au32F02_param[0] = 0x1a;
784	pNode->reserved.u32F07_param = 0;
785	pNode->reserved.u32F1c_param = CODEC_MAKE_F1C(CODEC_F1C_PORT_NO_PHYS,
786	CODEC_F1C_LOCATION_NA,
787	CODEC_F1C_DEVICE_LINE_OUT,
788	CODEC_F1C_CONNECTION_TYPE_UNKNOWN,
789	CODEC_F1C_COLOR_UNKNOWN,
790	0x0, 0x0, 0xf);//0x4000000f;
791	break;
792	default:
793	break;
794	}
795	return VINF_SUCCESS;
796	}
797
798	/* ALC885 */
799	const static uint8_t au8Alc885Ports[] = { 0x14, 0x15, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x1B, 0};
800	const static uint8_t au8Alc885Dacs[] = { 0x2, 0x3, 0x4, 0x5, 0x25, 0};
801	const static uint8_t au8Alc885Adcs[] = { 0x7, 0x8, 0x9, 0};
802	const static uint8_t au8Alc885SpdifOuts[] = { 0x6, 0 };
803	const static uint8_t au8Alc885SpdifIns[] = { 0xA, 0 };
804	const static uint8_t au8Alc885DigOutPins[] = { 0x1E, 0 };
805	const static uint8_t au8Alc885DigInPins[] = { 0x1F, 0 };
806	const static uint8_t au8Alc885AdcVols[] = { 0xE, 0xF, 0xD, 0xC, 0x26, 0xB, 0};
807	const static uint8_t au8Alc885AdcMuxs[] = { 0x22, 0x23, 0x24, 0};
808	const static uint8_t au8Alc885Pcbeeps[] = { 0x1D, 0 };
809	const static uint8_t au8Alc885Cds[] = { 0x1C, 0 };
810	const static uint8_t au8Alc885VolKnobs[] = { 0x21, 0 };
811	const static uint8_t au8Alc885Reserveds[] = { 0x10, 0x11, 0x12, 0x13, 0 };
812
813
814	static int alc885ResetNode(struct CODECState *pState, uint8_t nodenum, PCODECNODE pNode);
815
816	static int alc885Construct(CODECState *pState)
817	{
818	unconst(pState->cTotalNodes) = 0x27;
819	pState->u16VendorId = 0x10ec;
820	pState->u16DeviceId = 0x0885;
821	pState->u8BSKU = 0x08;
822	pState->u8AssemblyId = 0x85;
823	pState->pfnCodecNodeReset = alc885ResetNode;
824	pState->pNodes = (PCODECNODE)RTMemAllocZ(sizeof(CODECNODE) * pState->cTotalNodes);
825	pState->fInReset = false;
826	#define ALC885WIDGET(type) pState->au8##type##s = au8Alc885##type##s
827	ALC885WIDGET(Port);
828	ALC885WIDGET(Dac);
829	ALC885WIDGET(Adc);
830	ALC885WIDGET(AdcVol);
831	ALC885WIDGET(AdcMux);
832	ALC885WIDGET(Pcbeep);
833	ALC885WIDGET(SpdifIn);
834	ALC885WIDGET(SpdifOut);
835	ALC885WIDGET(DigInPin);
836	ALC885WIDGET(DigOutPin);
837	ALC885WIDGET(Cd);
838	ALC885WIDGET(VolKnob);
839	ALC885WIDGET(Reserved);
840	#undef ALC885WIDGET
841	/* @todo: test more */
842	unconst(pState->u8AdcVolsLineIn) = 0x1a;
843	unconst(pState->u8DacLineOut) = 0x0d;
844
845	return VINF_SUCCESS;
846	}
847
848	static int alc885ResetNode(struct CODECState *pState, uint8_t nodenum, PCODECNODE pNode)
849	{
850	pNode->node.id = nodenum;
851	switch (nodenum)
852	{
853	case 0: /* Root */
854	pNode->node.au32F00_param[2] = CODEC_MAKE_F00_02(0x1, 0x0, 0x0, 0x0); /* Realtek 889 (8.1.9)*/
855	pNode->node.au32F00_param[0xA] = pState->pNodes[1].node.au32F00_param[0xA];
856
857	break;
858	case 0x1: /* AFG */
859	pNode->node.au32F00_param[0xB] = CODEC_F00_0B_PCM;
860	pNode->node.au32F00_param[0x11] = RT_BIT(30)\|0x2;
861	break;
862	/* DACs */
863	case 0x2:
864	pNode->node.name = "DAC-0";
865	goto dac_init;
866	case 0x3:
867	pNode->node.name = "DAC-1";
868	goto dac_init;
869	case 0x4:
870	pNode->node.name = "DAC-2";
871	goto dac_init;
872	case 0x5:
873	pNode->node.name = "DAC-3";
874	goto dac_init;
875	case 0x25:
876	pNode->node.name = "DAC-4";
877	dac_init:
878	pNode->node.au32F00_param[0xA] = pState->pNodes[1].node.au32F00_param[0xA];
879	pNode->node.au32F00_param[0x9] = 0x11;
880	pNode->node.au32F00_param[0xB] = CODEC_F00_0B_PCM;
881	pNode->dac.u32A_param = CODEC_MAKE_A(0, 1, CODEC_A_MULT_1X, CODEC_A_DIV_1X, CODEC_A_16_BIT, 1);//(1<<14)\|(0x1<<4) \| 0x1;
882	break;
883	/* SPDIFs */
884	case 0x6:
885	pNode->node.name = "SPDIFOUT-0";
886	pNode->node.au32F00_param[0x9] = 0x211;
887	pNode->node.au32F00_param[0xB] = 0x1;
888	pNode->node.au32F00_param[0xA] = pState->pNodes[1].node.au32F00_param[0xA];
889	pNode->spdifout.u32A_param = CODEC_MAKE_A(0, 1, CODEC_A_MULT_1X, CODEC_A_DIV_1X, CODEC_A_16_BIT, 1);//(1<<14)\|(0x1<<4) \| 0x1;
890	break;
891	case 0xA:
892	pNode->node.name = "SPDIFIN-0";
893	pNode->node.au32F00_param[0x9] = 0x100391;
894	pNode->node.au32F00_param[0xA] = pState->pNodes[1].node.au32F00_param[0xA];
895	pNode->node.au32F00_param[0xB] = 0x1;
896	pNode->node.au32F02_param[0] = RT_MAKE_U32_FROM_U8(0x1F, 0, 0, 0);
897	pNode->node.au32F02_param[1] = RT_MAKE_U32_FROM_U8(0x1F, 0, 0, 0);
898	pNode->node.au32F02_param[2] = RT_MAKE_U32_FROM_U8(0x1F, 0, 0, 0);
899	pNode->node.au32F02_param[3] = RT_MAKE_U32_FROM_U8(0x1F, 0, 0, 0);
900	pNode->node.au32F00_param[0xA] = pState->pNodes[1].node.au32F00_param[0xA];
901	pNode->spdifin.u32A_param = CODEC_MAKE_A(0, 1, CODEC_A_MULT_1X, CODEC_A_DIV_1X, CODEC_A_16_BIT, 1);//(1<<14)\|(0x1<<4) \| 0x1;
902	break;
903	/* VENDOR DEFINE */
904	case 0x10:
905	pNode->node.name = "VENDEF-0";
906	goto vendor_define_init;
907	case 0x11:
908	pNode->node.name = "VENDEF-1";
909	goto vendor_define_init;
910	case 0x12:
911	pNode->node.name = "VENDEF-2";
912	goto vendor_define_init;
913	case 0x13:
914	pNode->node.name = "VENDEF-3";
915	goto vendor_define_init;
916	case 0x20:
917	pNode->node.name = "VENDEF-4";
918	vendor_define_init:
919	pNode->node.au32F00_param[0x9] = 0xf00000;
920	break;
921
922	/* DIGPIN */
923	case 0x1E:
924	pNode->node.name = "DIGOUT-1";
925	pNode->node.au32F00_param[0x9] = 0x400300;
926	pNode->node.au32F00_param[0xE] = 0x1;
927	pNode->port.u32F1c_param = 0x14be060;
928	pNode->node.au32F00_param[0xC] = RT_BIT(4);
929	/* N = 0~3 */
930	pNode->node.au32F02_param[0] = RT_MAKE_U32_FROM_U8(0x6, 0x0, 0x0, 0x0);
931	pNode->node.au32F02_param[1] = RT_MAKE_U32_FROM_U8(0x6, 0x0, 0x0, 0x0);
932	pNode->node.au32F02_param[2] = RT_MAKE_U32_FROM_U8(0x6, 0x0, 0x0, 0x0);
933	pNode->node.au32F02_param[3] = RT_MAKE_U32_FROM_U8(0x6, 0x0, 0x0, 0x0);
934	break;
935	case 0x1F:
936	pNode->node.name = "DIGIN-0";
937	pNode->node.au32F00_param[9] = 0x400200;
938	/* N = 0~3 */
939	pNode->node.au32F02_param[0] = RT_MAKE_U32_FROM_U8(0xA, 0x0, 0x0, 0x0);
940	pNode->node.au32F02_param[1] = RT_MAKE_U32_FROM_U8(0xA, 0x0, 0x0, 0x0);
941	pNode->node.au32F02_param[2] = RT_MAKE_U32_FROM_U8(0xA, 0x0, 0x0, 0x0);
942	pNode->node.au32F02_param[3] = RT_MAKE_U32_FROM_U8(0xA, 0x0, 0x0, 0x0);
943	break;
944	/* ADCs */
945	case 0x7:
946	pNode->node.name = "ADC-0";
947	pNode->node.au32F02_param[0] = RT_MAKE_U32_FROM_U8(0x23, 0, 0, 0);
948	pNode->node.au32F02_param[1] = RT_MAKE_U32_FROM_U8(0x23, 0, 0, 0);
949	pNode->node.au32F02_param[2] = RT_MAKE_U32_FROM_U8(0x23, 0, 0, 0);
950	pNode->node.au32F02_param[3] = RT_MAKE_U32_FROM_U8(0x23, 0, 0, 0);
951	goto adc_init;
952	break;
953	case 0x8:
954	pNode->node.name = "ADC-1";
955	pNode->node.au32F02_param[0] = RT_MAKE_U32_FROM_U8(0x24, 0, 0, 0);
956	pNode->node.au32F02_param[1] = RT_MAKE_U32_FROM_U8(0x24, 0, 0, 0);
957	pNode->node.au32F02_param[2] = RT_MAKE_U32_FROM_U8(0x24, 0, 0, 0);
958	pNode->node.au32F02_param[3] = RT_MAKE_U32_FROM_U8(0x24, 0, 0, 0);
959	goto adc_init;
960	break;
961	case 0x9:
962	pNode->node.name = "ADC-2";
963	pNode->node.au32F02_param[0] = RT_MAKE_U32_FROM_U8(0x22, 0, 0, 0);
964	pNode->node.au32F02_param[1] = RT_MAKE_U32_FROM_U8(0x22, 0, 0, 0);
965	pNode->node.au32F02_param[2] = RT_MAKE_U32_FROM_U8(0x22, 0, 0, 0);
966	pNode->node.au32F02_param[3] = RT_MAKE_U32_FROM_U8(0x22, 0, 0, 0);
967	adc_init:
968	pNode->node.au32F00_param[0xB] = 0x1;
969	pNode->node.au32F00_param[0x9] = 0x10011b;
970	pNode->node.au32F00_param[0xD] = 0x80032e10;
971	pNode->node.au32F00_param[0xE] = 0x1;
972	pNode->node.au32F00_param[0xA] = pState->pNodes[1].node.au32F00_param[0xA];
973	pNode->adc.u32A_param = CODEC_MAKE_A(0, 1, CODEC_A_MULT_1X, CODEC_A_DIV_1X, CODEC_A_16_BIT, 1);//(1<<14)\|(0x1<<4) \| 0x1;
974	break;
975	/* Ports */
976	case 0x14:
977	pNode->node.name = "PORT-D";
978	pNode->port.u32F1c_param = 0x12b4050;
979	pNode->node.au32F00_param[0xC] = RT_BIT(13)\|RT_BIT(12)\|RT_BIT(11)\|RT_BIT(10)\|RT_BIT(9)\|RT_BIT(8)\|RT_BIT(5)\|RT_BIT(4)\|RT_BIT(3)\|RT_BIT(2);
980	goto port_init;
981	break;
982	case 0x15:
983	pNode->node.name = "PORT-A";
984	pNode->port.u32F1c_param = 0x18b3020;
985	pNode->node.au32F00_param[0xC] = RT_BIT(13)\|RT_BIT(12)\|RT_BIT(11)\|RT_BIT(10)\|RT_BIT(9)\|RT_BIT(8)\|RT_BIT(5)\|RT_BIT(4)\|RT_BIT(3)\|RT_BIT(2);
986	goto port_init;
987	break;
988	case 0x16:
989	pNode->node.name = "PORT-G";
990	pNode->port.u32F1c_param = 0x400000f0;
991	pNode->node.au32F00_param[0xC] = RT_BIT(4)\|RT_BIT(3)\|RT_BIT(2);
992	goto port_init;
993	break;
994	case 0x17:
995	pNode->node.name = "PORT-H";
996	pNode->port.u32F1c_param = 0x400000f0;
997	pNode->node.au32F00_param[0xC] = RT_BIT(4)\|RT_BIT(3)\|RT_BIT(2);
998	goto port_init;
999	break;
1000	case 0x18:
1001	pNode->node.name = "PORT-B";
1002	pNode->port.u32F1c_param = 0x90100140;
1003	pNode->node.au32F00_param[0xC] = RT_BIT(13)\|RT_BIT(12)\|RT_BIT(11)\|RT_BIT(10)\|RT_BIT(9)\|RT_BIT(8)\|RT_BIT(5)\|RT_BIT(4)\|RT_BIT(3)\|RT_BIT(2);
1004	goto port_init;
1005	break;
1006	case 0x19:
1007	pNode->node.name = "PORT-F";
1008	pNode->port.u32F1c_param = 0x90a00110;
1009	pNode->node.au32F00_param[0xC] = RT_BIT(13)\|RT_BIT(12)\|RT_BIT(11)\|RT_BIT(10)\|RT_BIT(9)\|RT_BIT(8)\|RT_BIT(5)\|RT_BIT(4)\|RT_BIT(3)\|RT_BIT(2);
1010	goto port_init;
1011	break;
1012	case 0x1A:
1013	pNode->node.name = "PORT-C";
1014	pNode->port.u32F1c_param = 0x90100141;
1015	pNode->node.au32F00_param[0xC] = RT_BIT(13)\|RT_BIT(12)\|RT_BIT(11)\|RT_BIT(10)\|RT_BIT(9)\|RT_BIT(8)\|RT_BIT(5)\|RT_BIT(4)\|RT_BIT(3)\|RT_BIT(2);
1016	goto port_init;
1017	break;
1018	case 0x1B:
1019	pNode->node.name = "PORT-E";
1020	pNode->port.u32F1c_param = 0x400000f0;
1021	pNode->node.au32F00_param[0xC] = RT_BIT(13)\|RT_BIT(12)\|RT_BIT(11)\|RT_BIT(10)\|RT_BIT(9)\|RT_BIT(8)\|RT_BIT(5)\|RT_BIT(4)\|RT_BIT(3)\|RT_BIT(2);
1022	port_init:
1023	pNode->node.au32F00_param[0x9] = 0x40018f;
1024	pNode->node.au32F00_param[0xD] = 0x270300;
1025	pNode->node.au32F00_param[0xE] = 0x5;
1026	/* N = 0~3 */
1027	pNode->node.au32F02_param[0] = RT_MAKE_U32_FROM_U8(0xC, 0xD, 0xE, 0xF);
1028	pNode->node.au32F02_param[1] = RT_MAKE_U32_FROM_U8(0xC, 0xD, 0xE, 0xF);
1029	pNode->node.au32F02_param[2] = RT_MAKE_U32_FROM_U8(0xC, 0xD, 0xE, 0xF);
1030	pNode->node.au32F02_param[3] = RT_MAKE_U32_FROM_U8(0xC, 0xD, 0xE, 0xF);
1031	/* N = 4~7 */
1032	pNode->node.au32F02_param[4] = RT_MAKE_U32_FROM_U8(0x26, 0, 0, 0);
1033	pNode->node.au32F02_param[5] = RT_MAKE_U32_FROM_U8(0x26, 0, 0, 0);
1034	pNode->node.au32F02_param[6] = RT_MAKE_U32_FROM_U8(0x26, 0, 0, 0);
1035	pNode->node.au32F02_param[7] = RT_MAKE_U32_FROM_U8(0x26, 0, 0, 0);
1036	break;
1037	/* ADCVols */
1038	case 0x26:
1039	pNode->node.name = "AdcVol-0";
1040	pNode->node.au32F00_param[0x9] = 0x20010f;
1041	pNode->node.au32F00_param[0xD] = 0x80000000;
1042	pNode->node.au32F00_param[0xE] = 0x2;
1043	pNode->node.au32F00_param[0x12] = 0x34040;
1044	pNode->node.au32F02_param[0] = RT_MAKE_U32_FROM_U8(0x25, 0xB, 0, 0);
1045	pNode->node.au32F02_param[1] = RT_MAKE_U32_FROM_U8(0x25, 0xB, 0, 0);
1046	pNode->node.au32F02_param[2] = RT_MAKE_U32_FROM_U8(0x25, 0xB, 0, 0);
1047	pNode->node.au32F02_param[3] = RT_MAKE_U32_FROM_U8(0x25, 0xB, 0, 0);
1048	break;
1049	case 0xF:
1050	pNode->node.name = "AdcVol-1";
1051	pNode->node.au32F00_param[0x9] = 0x20010f;
1052	pNode->node.au32F00_param[0xE] = 0x2;
1053	pNode->node.au32F00_param[0x12] = 0x34040;
1054	pNode->node.au32F02_param[0] = RT_MAKE_U32_FROM_U8(0x5, 0xB, 0, 0);
1055	pNode->node.au32F02_param[1] = RT_MAKE_U32_FROM_U8(0x5, 0xB, 0, 0);
1056	pNode->node.au32F02_param[2] = RT_MAKE_U32_FROM_U8(0x5, 0xB, 0, 0);
1057	pNode->node.au32F02_param[3] = RT_MAKE_U32_FROM_U8(0x5, 0xB, 0, 0);
1058	break;
1059	case 0xE:
1060	pNode->node.name = "AdcVol-2";
1061	pNode->node.au32F00_param[0x9] = 0x20010f;
1062	pNode->node.au32F00_param[0xE] = 0x2;
1063	pNode->node.au32F00_param[0xD] = 0x80000000;
1064	pNode->node.au32F00_param[0x12] = 0x34040;
1065	pNode->node.au32F02_param[0] = RT_MAKE_U32_FROM_U8(0x4, 0xB, 0, 0);
1066	pNode->node.au32F02_param[1] = RT_MAKE_U32_FROM_U8(0x4, 0xB, 0, 0);
1067	pNode->node.au32F02_param[2] = RT_MAKE_U32_FROM_U8(0x4, 0xB, 0, 0);
1068	pNode->node.au32F02_param[3] = RT_MAKE_U32_FROM_U8(0x4, 0xB, 0, 0);
1069	break;
1070	case 0xD:
1071	pNode->node.name = "AdcVol-3";
1072	pNode->node.au32F00_param[0x9] = 0x20010f;
1073	pNode->node.au32F00_param[0xE] = 0x2;
1074	pNode->node.au32F00_param[0xD] = 0x80000000;
1075	pNode->node.au32F00_param[0x12] = 0x34040;
1076	pNode->node.au32F02_param[0] = RT_MAKE_U32_FROM_U8(0x3, 0xB, 0, 0);
1077	pNode->node.au32F02_param[1] = RT_MAKE_U32_FROM_U8(0x3, 0xB, 0, 0);
1078	pNode->node.au32F02_param[2] = RT_MAKE_U32_FROM_U8(0x3, 0xB, 0, 0);
1079	pNode->node.au32F02_param[3] = RT_MAKE_U32_FROM_U8(0x3, 0xB, 0, 0);
1080	break;
1081	case 0xC:
1082	pNode->node.name = "AdcVol-4";
1083	pNode->node.au32F00_param[0x9] = 0x20010f;
1084	pNode->node.au32F00_param[0xE] = 0x2;
1085	pNode->node.au32F00_param[0xD] = 0x80000000;
1086	pNode->node.au32F00_param[0x12] = 0x34040;
1087	pNode->node.au32F02_param[0] = RT_MAKE_U32_FROM_U8(0x2, 0xB, 0, 0);
1088	pNode->node.au32F02_param[1] = RT_MAKE_U32_FROM_U8(0x2, 0xB, 0, 0);
1089	pNode->node.au32F02_param[2] = RT_MAKE_U32_FROM_U8(0x2, 0xB, 0, 0);
1090	pNode->node.au32F02_param[3] = RT_MAKE_U32_FROM_U8(0x2, 0xB, 0, 0);
1091	break;
1092	case 0xB:
1093	pNode->node.name = "AdcVol-5";
1094	pNode->node.au32F00_param[0x9] = 0x20010b;
1095	pNode->node.au32F00_param[0xD] = 0x80051f17;
1096	/* N = 0~3 */
1097	pNode->node.au32F02_param[0] = RT_MAKE_U32_FROM_U8(0x18, 0x19, 0x1A, 0x1B);
1098	pNode->node.au32F02_param[1] = RT_MAKE_U32_FROM_U8(0x18, 0x19, 0x1A, 0x1B);
1099	pNode->node.au32F02_param[2] = RT_MAKE_U32_FROM_U8(0x18, 0x19, 0x1A, 0x1B);
1100	pNode->node.au32F02_param[3] = RT_MAKE_U32_FROM_U8(0x18, 0x19, 0x1A, 0x1B);
1101	/* N = 4~7 */
1102	pNode->node.au32F02_param[4] = RT_MAKE_U32_FROM_U8(0x1C, 0x1D, 0x14, 0x15);
1103	pNode->node.au32F02_param[5] = RT_MAKE_U32_FROM_U8(0x1C, 0x1D, 0x14, 0x15);
1104	pNode->node.au32F02_param[6] = RT_MAKE_U32_FROM_U8(0x1C, 0x1D, 0x14, 0x15);
1105	pNode->node.au32F02_param[7] = RT_MAKE_U32_FROM_U8(0x1C, 0x1D, 0x14, 0x15);
1106	/* N = 8~11 */
1107	pNode->node.au32F02_param[8] = RT_MAKE_U32_FROM_U8(0x16, 0x17, 0, 0);
1108	pNode->node.au32F02_param[9] = RT_MAKE_U32_FROM_U8(0x16, 0x17, 0, 0);
1109	pNode->node.au32F02_param[10] = RT_MAKE_U32_FROM_U8(0x16, 0x17, 0, 0);
1110	pNode->node.au32F02_param[11] = RT_MAKE_U32_FROM_U8(0x16, 0x17, 0, 0);
1111	break;
1112	/* AdcMuxs */
1113	case 0x22:
1114	pNode->node.name = "AdcMux-0";
1115	pNode->node.au32F00_param[0x9] = 0x20010b;
1116	pNode->node.au32F00_param[0xD] = 0x80000000;
1117	pNode->node.au32F00_param[0xE] = 0xb;
1118	goto adc_mux_init;
1119	case 0x23:
1120	pNode->node.name = "AdcMux-1";
1121	pNode->node.au32F00_param[0x9] = 0x20010b;
1122	pNode->node.au32F00_param[0xD] = 0x80000000;
1123	pNode->node.au32F00_param[0xE] = 0xb;
1124	adc_mux_init:
1125	/* N = 0~3 */
1126	pNode->node.au32F02_param[0] = RT_MAKE_U32_FROM_U8(0x18, 0x19, 0x1A, 0x1B);
1127	pNode->node.au32F02_param[1] = RT_MAKE_U32_FROM_U8(0x18, 0x19, 0x1A, 0x1B);
1128	pNode->node.au32F02_param[2] = RT_MAKE_U32_FROM_U8(0x18, 0x19, 0x1A, 0x1B);
1129	pNode->node.au32F02_param[3] = RT_MAKE_U32_FROM_U8(0x18, 0x19, 0x1A, 0x1B);
1130	/* N = 4~7 */
1131	pNode->node.au32F02_param[4] = RT_MAKE_U32_FROM_U8(0x1C, 0x1D, 0x14, 0x15);
1132	pNode->node.au32F02_param[5] = RT_MAKE_U32_FROM_U8(0x1C, 0x1D, 0x14, 0x15);
1133	pNode->node.au32F02_param[6] = RT_MAKE_U32_FROM_U8(0x1C, 0x1D, 0x14, 0x15);
1134	pNode->node.au32F02_param[7] = RT_MAKE_U32_FROM_U8(0x1C, 0x1D, 0x14, 0x15);
1135	/* N = 8~11 */
1136	pNode->node.au32F02_param[8] = RT_MAKE_U32_FROM_U8(0x16, 0x17, 0xB, 0);
1137	pNode->node.au32F02_param[9] = RT_MAKE_U32_FROM_U8(0x16, 0x17, 0xB, 0);
1138	pNode->node.au32F02_param[10] = RT_MAKE_U32_FROM_U8(0x16, 0x17, 0xB, 0);
1139	pNode->node.au32F02_param[11] = RT_MAKE_U32_FROM_U8(0x16, 0x17, 0xB, 0);
1140	break;
1141	case 0x24:
1142	pNode->node.name = "AdcMux-2";
1143	pNode->node.au32F00_param[0x9] = 0x20010b;
1144	pNode->node.au32F00_param[0xD] = 0x80000000;
1145	pNode->node.au32F00_param[0xE] = 0xb;
1146	/* N = 0~3 */
1147	pNode->node.au32F02_param[0] = RT_MAKE_U32_FROM_U8(0x18, 0x19, 0x1A, 0x1B);
1148	pNode->node.au32F02_param[1] = RT_MAKE_U32_FROM_U8(0x18, 0x19, 0x1A, 0x1B);
1149	pNode->node.au32F02_param[2] = RT_MAKE_U32_FROM_U8(0x18, 0x19, 0x1A, 0x1B);
1150	pNode->node.au32F02_param[3] = RT_MAKE_U32_FROM_U8(0x18, 0x19, 0x1A, 0x1B);
1151	/* N = 4~7 */
1152	pNode->node.au32F02_param[4] = RT_MAKE_U32_FROM_U8(0x1C, 0x1D, 0x14, 0x15);
1153	pNode->node.au32F02_param[5] = RT_MAKE_U32_FROM_U8(0x1C, 0x1D, 0x14, 0x15);
1154	pNode->node.au32F02_param[6] = RT_MAKE_U32_FROM_U8(0x1C, 0x1D, 0x14, 0x15);
1155	pNode->node.au32F02_param[7] = RT_MAKE_U32_FROM_U8(0x1C, 0x1D, 0x14, 0x15);
1156	/* N = 8~11 */
1157	pNode->node.au32F02_param[8] = RT_MAKE_U32_FROM_U8(0x16, 0x17, 0xB, 0x12);
1158	pNode->node.au32F02_param[9] = RT_MAKE_U32_FROM_U8(0x16, 0x17, 0xB, 0x12);
1159	pNode->node.au32F02_param[10] = RT_MAKE_U32_FROM_U8(0x16, 0x17, 0xB, 0x12);
1160	pNode->node.au32F02_param[11] = RT_MAKE_U32_FROM_U8(0x16, 0x17, 0xB, 0x12);
1161	break;
1162	/* PCBEEP */
1163	case 0x1D:
1164	pNode->node.name = "PCBEEP";
1165	pNode->node.au32F00_param[0x9] = 0x400000;
1166	pNode->port.u32F1c_param = 0x400000f0;
1167	pNode->node.au32F00_param[0xC] = RT_BIT(5);
1168	break;
1169	/* CD */
1170	case 0x1C:
1171	pNode->node.name = "CD";
1172	pNode->node.au32F00_param[0x9] = 0x400001;
1173	pNode->port.u32F1c_param = 0x400000f0;
1174	pNode->node.au32F00_param[0xC] = RT_BIT(5);
1175	break;
1176	case 0x21:
1177	pNode->node.name = "VolumeKnob";
1178	pNode->node.au32F00_param[0x9] = (0x6 << 20)\|RT_BIT(7);
1179	break;
1180	default:
1181	AssertMsgFailed(("Unsupported Node"));
1182	}
1183	return VINF_SUCCESS;
1184	}
1185
1186
1187	/* generic */
1188
1189	#define DECLISNODEOFTYPE(type) \
1190	static inline int codecIs##type##Node(struct CODECState *pState, uint8_t cNode) \
1191	{ \
1192	Assert(pState->au8##type##s); \
1193	for(int i = 0; pState->au8##type##s[i] != 0; ++i) \
1194	if (pState->au8##type##s[i] == cNode) \
1195	return 1; \
1196	return 0; \
1197	}
1198	/* codecIsPortNode */
1199	DECLISNODEOFTYPE(Port)
1200	/* codecIsDacNode */
1201	DECLISNODEOFTYPE(Dac)
1202	/* codecIsAdcVolNode */
1203	DECLISNODEOFTYPE(AdcVol)
1204	/* codecIsAdcNode */
1205	DECLISNODEOFTYPE(Adc)
1206	/* codecIsAdcMuxNode */
1207	DECLISNODEOFTYPE(AdcMux)
1208	/* codecIsPcbeepNode */
1209	DECLISNODEOFTYPE(Pcbeep)
1210	/* codecIsSpdifOutNode */
1211	DECLISNODEOFTYPE(SpdifOut)
1212	/* codecIsSpdifInNode */
1213	DECLISNODEOFTYPE(SpdifIn)
1214	/* codecIsDigInPinNode */
1215	DECLISNODEOFTYPE(DigInPin)
1216	/* codecIsDigOutPinNode */
1217	DECLISNODEOFTYPE(DigOutPin)
1218	/* codecIsCdNode */
1219	DECLISNODEOFTYPE(Cd)
1220	/* codecIsVolKnobNode */
1221	DECLISNODEOFTYPE(VolKnob)
1222	/* codecIsReservedNode */
1223	DECLISNODEOFTYPE(Reserved)
1224
1225	static int codecToAudVolume(AMPLIFIER *pAmp, audmixerctl_t mt);
1226
1227	static inline void codecSetRegister(uint32_t *pu32Reg, uint32_t u32Cmd, uint8_t u8Offset, uint32_t mask)
1228	{
1229	Assert((pu32Reg && u8Offset < 32));
1230	*pu32Reg &= ~(mask << u8Offset);
1231	*pu32Reg \|= (u32Cmd & mask) << u8Offset;
1232	}
1233	static inline void codecSetRegisterU8(uint32_t *pu32Reg, uint32_t u32Cmd, uint8_t u8Offset)
1234	{
1235	codecSetRegister(pu32Reg, u32Cmd, u8Offset, CODEC_VERB_8BIT_DATA);
1236	}
1237
1238	static inline void codecSetRegisterU16(uint32_t *pu32Reg, uint32_t u32Cmd, uint8_t u8Offset)
1239	{
1240	codecSetRegister(pu32Reg, u32Cmd, u8Offset, CODEC_VERB_16BIT_DATA);
1241	}
1242
1243
1244	static int codecUnimplemented(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1245	{
1246	Log(("codecUnimplemented: cmd(raw:%x: cad:%x, d:%c, nid:%x, verb:%x)\n", cmd,
1247	CODEC_CAD(cmd), CODEC_DIRECT(cmd) ? 'N' : 'Y', CODEC_NID(cmd), CODEC_VERBDATA(cmd)));
1248	*pResp = 0;
1249	return VINF_SUCCESS;
1250	}
1251
1252	static int codecBreak(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1253	{
1254	int rc;
1255	rc = codecUnimplemented(pState, cmd, pResp);
1256	*pResp \|= CODEC_RESPONSE_UNSOLICITED;
1257	return rc;
1258	}
1259	/* B-- */
1260	static int codecGetAmplifier(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1261	{
1262	Assert((CODEC_CAD(cmd) == pState->id));
1263	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1264	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1265	{
1266	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1267	return VINF_SUCCESS;
1268	}
1269	*pResp = 0;
1270	/* HDA spec 7.3.3.7 Note A */
1271	/* @todo: if index out of range response should be 0 */
1272	uint8_t u8Index = CODEC_GET_AMP_DIRECTION(cmd) == AMPLIFIER_OUT? 0 : CODEC_GET_AMP_INDEX(cmd);
1273
1274	PCODECNODE pNode = &pState->pNodes[CODEC_NID(cmd)];
1275	if (codecIsDacNode(pState, CODEC_NID(cmd)))
1276	*pResp = AMPLIFIER_REGISTER(pNode->dac.B_params,
1277	CODEC_GET_AMP_DIRECTION(cmd),
1278	CODEC_GET_AMP_SIDE(cmd),
1279	u8Index);
1280	else if (codecIsAdcVolNode(pState, CODEC_NID(cmd)))
1281	*pResp = AMPLIFIER_REGISTER(pNode->adcvol.B_params,
1282	CODEC_GET_AMP_DIRECTION(cmd),
1283	CODEC_GET_AMP_SIDE(cmd),
1284	u8Index);
1285	else if (codecIsAdcMuxNode(pState, CODEC_NID(cmd)))
1286	*pResp = AMPLIFIER_REGISTER(pNode->adcmux.B_params,
1287	CODEC_GET_AMP_DIRECTION(cmd),
1288	CODEC_GET_AMP_SIDE(cmd),
1289	u8Index);
1290	else if (codecIsPcbeepNode(pState, CODEC_NID(cmd)))
1291	*pResp = AMPLIFIER_REGISTER(pNode->pcbeep.B_params,
1292	CODEC_GET_AMP_DIRECTION(cmd),
1293	CODEC_GET_AMP_SIDE(cmd),
1294	u8Index);
1295	else if (codecIsPortNode(pState, CODEC_NID(cmd)))
1296	*pResp = AMPLIFIER_REGISTER(pNode->port.B_params,
1297	CODEC_GET_AMP_DIRECTION(cmd),
1298	CODEC_GET_AMP_SIDE(cmd),
1299	u8Index);
1300	else if (codecIsAdcNode(pState, CODEC_NID(cmd)))
1301	*pResp = AMPLIFIER_REGISTER(pNode->adc.B_params,
1302	CODEC_GET_AMP_DIRECTION(cmd),
1303	CODEC_GET_AMP_SIDE(cmd),
1304	u8Index);
1305	else{
1306	AssertMsgReturn(0, ("access to fields of %x need to be implemented\n", CODEC_NID(cmd)), VINF_SUCCESS);
1307	}
1308	return VINF_SUCCESS;
1309	}
1310	/* 3-- */
1311	static int codecSetAmplifier(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1312	{
1313	AMPLIFIER *pAmplifier = NULL;
1314	bool fIsLeft = false;
1315	bool fIsRight = false;
1316	bool fIsOut = false;
1317	bool fIsIn = false;
1318	uint8_t u8Index = 0;
1319	Assert((CODEC_CAD(cmd) == pState->id));
1320	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1321	{
1322	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1323	return VINF_SUCCESS;
1324	}
1325	*pResp = 0;
1326	PCODECNODE pNode = &pState->pNodes[CODEC_NID(cmd)];
1327	if (codecIsDacNode(pState, CODEC_NID(cmd)))
1328	pAmplifier = &pNode->dac.B_params;
1329	else if (codecIsAdcVolNode(pState, CODEC_NID(cmd)))
1330	pAmplifier = &pNode->adcvol.B_params;
1331	else if (codecIsAdcMuxNode(pState, CODEC_NID(cmd)))
1332	pAmplifier = &pNode->adcmux.B_params;
1333	else if (codecIsPcbeepNode(pState, CODEC_NID(cmd)))
1334	pAmplifier = &pNode->pcbeep.B_params;
1335	else if (codecIsPortNode(pState, CODEC_NID(cmd)))
1336	pAmplifier = &pNode->port.B_params;
1337	else if (codecIsAdcNode(pState, CODEC_NID(cmd)))
1338	pAmplifier = &pNode->adc.B_params;
1339	Assert(pAmplifier);
1340	if (pAmplifier)
1341	{
1342	fIsOut = CODEC_SET_AMP_IS_OUT_DIRECTION(cmd);
1343	fIsIn = CODEC_SET_AMP_IS_IN_DIRECTION(cmd);
1344	fIsRight = CODEC_SET_AMP_IS_RIGHT_SIDE(cmd);
1345	fIsLeft = CODEC_SET_AMP_IS_LEFT_SIDE(cmd);
1346	u8Index = CODEC_SET_AMP_INDEX(cmd);
1347	if ( (!fIsLeft && !fIsRight)
1348	\|\| (!fIsOut && !fIsIn))
1349	return VINF_SUCCESS;
1350	if (fIsIn)
1351	{
1352	if (fIsLeft)
1353	codecSetRegisterU8(&AMPLIFIER_REGISTER(*pAmplifier, AMPLIFIER_IN, AMPLIFIER_LEFT, u8Index), cmd, 0);
1354	if (fIsRight)
1355	codecSetRegisterU8(&AMPLIFIER_REGISTER(*pAmplifier, AMPLIFIER_IN, AMPLIFIER_RIGHT, u8Index), cmd, 0);
1356	}
1357	if (fIsOut)
1358	{
1359	if (fIsLeft)
1360	codecSetRegisterU8(&AMPLIFIER_REGISTER(*pAmplifier, AMPLIFIER_OUT, AMPLIFIER_LEFT, u8Index), cmd, 0);
1361	if (fIsRight)
1362	codecSetRegisterU8(&AMPLIFIER_REGISTER(*pAmplifier, AMPLIFIER_OUT, AMPLIFIER_RIGHT, u8Index), cmd, 0);
1363	}
1364	if (CODEC_NID(cmd) == pState->u8DacLineOut)
1365	codecToAudVolume(pAmplifier, AUD_MIXER_VOLUME);
1366	if (CODEC_NID(cmd) == pState->u8AdcVolsLineIn) /* Microphone */
1367	codecToAudVolume(pAmplifier, AUD_MIXER_LINE_IN);
1368	}
1369	return VINF_SUCCESS;
1370	}
1371
1372	static int codecGetParameter(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1373	{
1374	Assert((CODEC_CAD(cmd) == pState->id));
1375	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1376	{
1377	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1378	return VINF_SUCCESS;
1379	}
1380	Assert(((cmd & CODEC_VERB_8BIT_DATA) < CODECNODE_F0_PARAM_LENGTH));
1381	if ((cmd & CODEC_VERB_8BIT_DATA) >= CODECNODE_F0_PARAM_LENGTH)
1382	{
1383	Log(("HDAcodec: invalid F00 parameter %d\n", (cmd & CODEC_VERB_8BIT_DATA)));
1384	return VINF_SUCCESS;
1385	}
1386	*pResp = 0;
1387	*pResp = pState->pNodes[CODEC_NID(cmd)].node.au32F00_param[cmd & CODEC_VERB_8BIT_DATA];
1388	return VINF_SUCCESS;
1389	}
1390
1391	/* F01 */
1392	static int codecGetConSelectCtrl(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1393	{
1394	Assert((CODEC_CAD(cmd) == pState->id));
1395	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1396	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1397	{
1398	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1399	return VINF_SUCCESS;
1400	}
1401	*pResp = 0;
1402	if (codecIsAdcMuxNode(pState, CODEC_NID(cmd)))
1403	*pResp = pState->pNodes[CODEC_NID(cmd)].adcmux.u32F01_param;
1404	else if (codecIsDigOutPinNode(pState, CODEC_NID(cmd)))
1405	*pResp = pState->pNodes[CODEC_NID(cmd)].digout.u32F01_param;
1406	else if (codecIsPortNode(pState, CODEC_NID(cmd)))
1407	*pResp = pState->pNodes[CODEC_NID(cmd)].port.u32F01_param;
1408	else if (codecIsAdcNode(pState, CODEC_NID(cmd)))
1409	*pResp = pState->pNodes[CODEC_NID(cmd)].adc.u32F01_param;
1410	else if (codecIsAdcVolNode(pState, CODEC_NID(cmd)))
1411	*pResp = pState->pNodes[CODEC_NID(cmd)].adcvol.u32F01_param;
1412	return VINF_SUCCESS;
1413	}
1414
1415	/* 701 */
1416	static int codecSetConSelectCtrl(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1417	{
1418	uint32_t *pu32Reg = NULL;
1419	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1420	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1421	{
1422	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1423	return VINF_SUCCESS;
1424	}
1425	*pResp = 0;
1426	if (codecIsAdcMuxNode(pState, CODEC_NID(cmd)))
1427	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].adcmux.u32F01_param;
1428	else if (codecIsDigOutPinNode(pState, CODEC_NID(cmd)))
1429	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].digout.u32F01_param;
1430	else if (codecIsPortNode(pState, CODEC_NID(cmd)))
1431	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].port.u32F01_param;
1432	else if (codecIsAdcNode(pState, CODEC_NID(cmd)))
1433	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].adc.u32F01_param;
1434	else if (codecIsAdcVolNode(pState, CODEC_NID(cmd)))
1435	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].adcvol.u32F01_param;
1436	Assert((pu32Reg));
1437	if (pu32Reg)
1438	codecSetRegisterU8(pu32Reg, cmd, 0);
1439	return VINF_SUCCESS;
1440	}
1441
1442	/* F07 */
1443	static int codecGetPinCtrl(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1444	{
1445	Assert((CODEC_CAD(cmd) == pState->id));
1446	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1447	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1448	{
1449	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1450	return VINF_SUCCESS;
1451	}
1452	*pResp = 0;
1453	if (codecIsPortNode(pState, CODEC_NID(cmd)))
1454	*pResp = pState->pNodes[CODEC_NID(cmd)].port.u32F07_param;
1455	else if (codecIsDigOutPinNode(pState, CODEC_NID(cmd)))
1456	*pResp = pState->pNodes[CODEC_NID(cmd)].digout.u32F07_param;
1457	else if (codecIsDigInPinNode(pState, CODEC_NID(cmd)))
1458	*pResp = pState->pNodes[CODEC_NID(cmd)].digin.u32F07_param;
1459	else if (codecIsCdNode(pState, CODEC_NID(cmd)))
1460	*pResp = pState->pNodes[CODEC_NID(cmd)].cdnode.u32F07_param;
1461	else if (codecIsPcbeepNode(pState, CODEC_NID(cmd)))
1462	*pResp = pState->pNodes[CODEC_NID(cmd)].pcbeep.u32F07_param;
1463	else if (codecIsReservedNode(pState, CODEC_NID(cmd)))
1464	*pResp = pState->pNodes[CODEC_NID(cmd)].reserved.u32F07_param;
1465	else
1466	AssertMsgFailed(("Unsupported"));
1467	return VINF_SUCCESS;
1468	}
1469
1470	/* 707 */
1471	static int codecSetPinCtrl(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1472	{
1473	Assert((CODEC_CAD(cmd) == pState->id));
1474	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1475	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1476	{
1477	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1478	return VINF_SUCCESS;
1479	}
1480	*pResp = 0;
1481	uint32_t *pu32Reg = NULL;
1482	if (codecIsPortNode(pState, CODEC_NID(cmd)))
1483	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].port.u32F07_param;
1484	else if (codecIsDigInPinNode(pState, CODEC_NID(cmd)))
1485	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].digin.u32F07_param;
1486	else if (codecIsDigOutPinNode(pState, CODEC_NID(cmd)))
1487	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].digout.u32F07_param;
1488	else if (codecIsCdNode(pState, CODEC_NID(cmd)))
1489	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].cdnode.u32F07_param;
1490	else if (codecIsPcbeepNode(pState, CODEC_NID(cmd)))
1491	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].pcbeep.u32F07_param;
1492	else if ( codecIsReservedNode(pState, CODEC_NID(cmd))
1493	&& CODEC_NID(cmd) == 0x1b
1494	&& pState->enmCodec == STAC9220_CODEC)
1495	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].reserved.u32F07_param;
1496	Assert((pu32Reg));
1497	if (pu32Reg)
1498	codecSetRegisterU8(pu32Reg, cmd, 0);
1499	return VINF_SUCCESS;
1500	}
1501
1502	/* F08 */
1503	static int codecGetUnsolicitedEnabled(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1504	{
1505	Assert((CODEC_CAD(cmd) == pState->id));
1506	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1507	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1508	{
1509	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1510	return VINF_SUCCESS;
1511	}
1512	*pResp = 0;
1513	if (codecIsPortNode(pState, CODEC_NID(cmd)))
1514	*pResp = pState->pNodes[CODEC_NID(cmd)].port.u32F08_param;
1515	else if (codecIsDigInPinNode(pState, CODEC_NID(cmd)))
1516	*pResp = pState->pNodes[CODEC_NID(cmd)].digin.u32F08_param;
1517	else if ((cmd) == 1 /* AFG */)
1518	*pResp = pState->pNodes[CODEC_NID(cmd)].afg.u32F08_param;
1519	else if (codecIsVolKnobNode(pState, CODEC_NID(cmd)))
1520	*pResp = pState->pNodes[CODEC_NID(cmd)].volumeKnob.u32F08_param;
1521	else if (codecIsDigOutPinNode(pState, CODEC_NID(cmd)))
1522	*pResp = pState->pNodes[CODEC_NID(cmd)].digout.u32F08_param;
1523	else if (codecIsDigInPinNode(pState, CODEC_NID(cmd)))
1524	*pResp = pState->pNodes[CODEC_NID(cmd)].digin.u32F08_param;
1525	else
1526	AssertMsgFailed(("unsupported operation %x on node: %x\n", CODEC_VERB_CMD8(cmd), CODEC_NID(cmd)));
1527	return VINF_SUCCESS;
1528	}
1529
1530	/* 708 */
1531	static int codecSetUnsolicitedEnabled(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1532	{
1533	Assert((CODEC_CAD(cmd) == pState->id));
1534	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1535	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1536	{
1537	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1538	return VINF_SUCCESS;
1539	}
1540	*pResp = 0;
1541	uint32_t *pu32Reg = NULL;
1542	if (codecIsPortNode(pState, CODEC_NID(cmd)))
1543	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].port.u32F08_param;
1544	else if (codecIsDigInPinNode(pState, CODEC_NID(cmd)))
1545	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].digin.u32F08_param;
1546	else if (CODEC_NID(cmd) == 1 /* AFG */)
1547	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].afg.u32F08_param;
1548	else if (codecIsVolKnobNode(pState, CODEC_NID(cmd)))
1549	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].volumeKnob.u32F08_param;
1550	else if (codecIsDigInPinNode(pState, CODEC_NID(cmd)))
1551	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].digin.u32F08_param;
1552	else if (codecIsDigOutPinNode(pState, CODEC_NID(cmd)))
1553	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].digout.u32F08_param;
1554	else
1555	AssertMsgFailed(("unsupported operation %x on node: %x\n", CODEC_VERB_CMD8(cmd), CODEC_NID(cmd)));
1556	Assert(pu32Reg);
1557	if(pu32Reg)
1558	codecSetRegisterU8(pu32Reg, cmd, 0);
1559	return VINF_SUCCESS;
1560	}
1561
1562	/* F09 */
1563	static int codecGetPinSense(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1564	{
1565	Assert((CODEC_CAD(cmd) == pState->id));
1566	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1567	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1568	{
1569	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1570	return VINF_SUCCESS;
1571	}
1572	*pResp = 0;
1573	if (codecIsPortNode(pState, CODEC_NID(cmd)))
1574	*pResp = pState->pNodes[CODEC_NID(cmd)].port.u32F09_param;
1575	else if (codecIsDigInPinNode(pState, CODEC_NID(cmd)))
1576	*pResp = pState->pNodes[CODEC_NID(cmd)].digin.u32F09_param;
1577	else
1578	AssertMsgFailed(("unsupported operation %x on node: %x\n", CODEC_VERB_CMD8(cmd), CODEC_NID(cmd)));
1579	return VINF_SUCCESS;
1580	}
1581
1582	/* 709 */
1583	static int codecSetPinSense(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1584	{
1585	Assert((CODEC_CAD(cmd) == pState->id));
1586	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1587	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1588	{
1589	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1590	return VINF_SUCCESS;
1591	}
1592	*pResp = 0;
1593	uint32_t *pu32Reg = NULL;
1594	if (codecIsPortNode(pState, CODEC_NID(cmd)))
1595	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].port.u32F09_param;
1596	else if (codecIsDigInPinNode(pState, CODEC_NID(cmd)))
1597	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].digin.u32F09_param;
1598	Assert(pu32Reg);
1599	if(pu32Reg)
1600	codecSetRegisterU8(pu32Reg, cmd, 0);
1601	return VINF_SUCCESS;
1602	}
1603
1604	static int codecGetConnectionListEntry(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1605	{
1606	Assert((CODEC_CAD(cmd) == pState->id));
1607	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1608	*pResp = 0;
1609	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1610	{
1611	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1612	return VINF_SUCCESS;
1613	}
1614	Assert((cmd & CODEC_VERB_8BIT_DATA) < CODECNODE_F02_PARAM_LENGTH);
1615	if ((cmd & CODEC_VERB_8BIT_DATA) >= CODECNODE_F02_PARAM_LENGTH)
1616	{
1617	Log(("HDAcodec: access to invalid F02 index %d\n", (cmd & CODEC_VERB_8BIT_DATA)));
1618	return VINF_SUCCESS;
1619	}
1620	*pResp = pState->pNodes[CODEC_NID(cmd)].node.au32F02_param[cmd & CODEC_VERB_8BIT_DATA];
1621	return VINF_SUCCESS;
1622	}
1623	/* F03 */
1624	static int codecGetProcessingState(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1625	{
1626	Assert((CODEC_CAD(cmd) == pState->id));
1627	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1628	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1629	{
1630	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1631	return VINF_SUCCESS;
1632	}
1633	*pResp = 0;
1634	if (codecIsAdcNode(pState, CODEC_NID(cmd)))
1635	*pResp = pState->pNodes[CODEC_NID(cmd)].adc.u32F03_param;
1636	return VINF_SUCCESS;
1637	}
1638
1639	/* 703 */
1640	static int codecSetProcessingState(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1641	{
1642	Assert((CODEC_CAD(cmd) == pState->id));
1643	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1644	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1645	{
1646	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1647	return VINF_SUCCESS;
1648	}
1649	*pResp = 0;
1650	if (codecIsAdcNode(pState, CODEC_NID(cmd)))
1651	{
1652	codecSetRegisterU8(&pState->pNodes[CODEC_NID(cmd)].adc.u32F03_param, cmd, 0);
1653	}
1654	return VINF_SUCCESS;
1655	}
1656
1657	/* F0D */
1658	static int codecGetDigitalConverter(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1659	{
1660	Assert((CODEC_CAD(cmd) == pState->id));
1661	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1662	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1663	{
1664	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1665	return VINF_SUCCESS;
1666	}
1667	*pResp = 0;
1668	if (codecIsSpdifOutNode(pState, CODEC_NID(cmd)))
1669	*pResp = pState->pNodes[CODEC_NID(cmd)].spdifout.u32F0d_param;
1670	else if (codecIsSpdifInNode(pState, CODEC_NID(cmd)))
1671	*pResp = pState->pNodes[CODEC_NID(cmd)].spdifin.u32F0d_param;
1672	return VINF_SUCCESS;
1673	}
1674
1675	static int codecSetDigitalConverter(struct CODECState pState, uint32_t cmd, uint8_t u8Offset, uint64_t pResp)
1676	{
1677	Assert((CODEC_CAD(cmd) == pState->id));
1678	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1679	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1680	{
1681	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1682	return VINF_SUCCESS;
1683	}
1684	*pResp = 0;
1685	if (codecIsSpdifOutNode(pState, CODEC_NID(cmd)))
1686	codecSetRegisterU8(&pState->pNodes[CODEC_NID(cmd)].spdifout.u32F0d_param, cmd, u8Offset);
1687	else if (codecIsSpdifInNode(pState, CODEC_NID(cmd)))
1688	codecSetRegisterU8(&pState->pNodes[CODEC_NID(cmd)].spdifin.u32F0d_param, cmd, u8Offset);
1689	return VINF_SUCCESS;
1690	}
1691
1692	/* 70D */
1693	static int codecSetDigitalConverter1(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1694	{
1695	return codecSetDigitalConverter(pState, cmd, 0, pResp);
1696	}
1697
1698	/* 70E */
1699	static int codecSetDigitalConverter2(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1700	{
1701	return codecSetDigitalConverter(pState, cmd, 8, pResp);
1702	}
1703
1704	/* F20 */
1705	static int codecGetSubId(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1706	{
1707	Assert((CODEC_CAD(cmd) == pState->id));
1708	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1709	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1710	{
1711	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1712	return VINF_SUCCESS;
1713	}
1714	*pResp = 0;
1715	if (CODEC_NID(cmd) == 1 /* AFG */)
1716	{
1717	*pResp = pState->pNodes[CODEC_NID(cmd)].afg.u32F20_param;
1718	}
1719	return VINF_SUCCESS;
1720	}
1721
1722	static int codecSetSubIdX(struct CODECState *pState, uint32_t cmd, uint8_t u8Offset)
1723	{
1724	Assert((CODEC_CAD(cmd) == pState->id));
1725	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1726	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1727	{
1728	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1729	return VINF_SUCCESS;
1730	}
1731	uint32_t *pu32Reg = NULL;
1732	if (CODEC_NID(cmd) == 0x1 /* AFG */)
1733	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].afg.u32F20_param;
1734	Assert((pu32Reg));
1735	if (pu32Reg)
1736	codecSetRegisterU8(pu32Reg, cmd, u8Offset);
1737	return VINF_SUCCESS;
1738	}
1739	/* 720 */
1740	static int codecSetSubId0 (struct CODECState pState, uint32_t cmd, uint64_t pResp)
1741	{
1742	*pResp = 0;
1743	return codecSetSubIdX(pState, cmd, 0);
1744	}
1745
1746	/* 721 */
1747	static int codecSetSubId1 (struct CODECState pState, uint32_t cmd, uint64_t pResp)
1748	{
1749	*pResp = 0;
1750	return codecSetSubIdX(pState, cmd, 8);
1751	}
1752	/* 722 */
1753	static int codecSetSubId2 (struct CODECState pState, uint32_t cmd, uint64_t pResp)
1754	{
1755	*pResp = 0;
1756	return codecSetSubIdX(pState, cmd, 16);
1757	}
1758	/* 723 */
1759	static int codecSetSubId3 (struct CODECState pState, uint32_t cmd, uint64_t pResp)
1760	{
1761	*pResp = 0;
1762	return codecSetSubIdX(pState, cmd, 24);
1763	}
1764
1765	static int codecReset(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1766	{
1767	Assert((CODEC_CAD(cmd) == pState->id));
1768	Assert(CODEC_NID(cmd) == 1 /* AFG */);
1769	if(CODEC_NID(cmd) == 1 /* AFG */)
1770	{
1771	uint8_t i;
1772	Log(("HDAcodec: enters reset\n"));
1773	Assert(pState->pfnCodecNodeReset);
1774	for (i = 0; i < pState->cTotalNodes; ++i)
1775	{
1776	pState->pfnCodecNodeReset(pState, i, &pState->pNodes[i]);
1777	}
1778	pState->fInReset = false;
1779	Log(("HDAcodec: exits reset\n"));
1780	}
1781	*pResp = 0;
1782	return VINF_SUCCESS;
1783	}
1784
1785	/* F05 */
1786	static int codecGetPowerState(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1787	{
1788	Assert((CODEC_CAD(cmd) == pState->id));
1789	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1790	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1791	{
1792	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1793	return VINF_SUCCESS;
1794	}
1795	*pResp = 0;
1796	if (CODEC_NID(cmd) == 1 /* AFG */)
1797	*pResp = pState->pNodes[CODEC_NID(cmd)].afg.u32F05_param;
1798	else if (codecIsDacNode(pState, CODEC_NID(cmd)))
1799	*pResp = pState->pNodes[CODEC_NID(cmd)].dac.u32F05_param;
1800	else if (codecIsDigInPinNode(pState, CODEC_NID(cmd)))
1801	*pResp = pState->pNodes[CODEC_NID(cmd)].digin.u32F05_param;
1802	else if (codecIsAdcNode(pState, CODEC_NID(cmd)))
1803	*pResp = pState->pNodes[CODEC_NID(cmd)].adc.u32F05_param;
1804	else if (codecIsSpdifOutNode(pState, CODEC_NID(cmd)))
1805	*pResp = pState->pNodes[CODEC_NID(cmd)].spdifout.u32F05_param;
1806	else if (codecIsSpdifInNode(pState, CODEC_NID(cmd)))
1807	*pResp = pState->pNodes[CODEC_NID(cmd)].spdifin.u32F05_param;
1808	else if (codecIsReservedNode(pState, CODEC_NID(cmd)))
1809	*pResp = pState->pNodes[CODEC_NID(cmd)].reserved.u32F05_param;
1810	return VINF_SUCCESS;
1811	}
1812
1813	/* 705 */
1814
1815	static inline void codecPropogatePowerState(uint32_t *pu32F05_param)
1816	{
1817	Assert(pu32F05_param);
1818	if (pu32F05_param)
1819	return;
1820	bool fReset = CODEC_F05_IS_RESET(*pu32F05_param);
1821	bool fStopOk = CODEC_F05_IS_STOPOK(*pu32F05_param);
1822	uint8_t u8SetPowerState = CODEC_F05_SET(*pu32F05_param);
1823	*pu32F05_param = CODEC_MAKE_F05(fReset, fStopOk, 0, u8SetPowerState, u8SetPowerState);
1824	}
1825
1826	static int codecSetPowerState(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1827	{
1828	Assert((CODEC_CAD(cmd) == pState->id));
1829	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1830	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1831	{
1832	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1833	return VINF_SUCCESS;
1834	}
1835	uint32_t *pu32Reg = NULL;
1836	*pResp = 0;
1837	if (CODEC_NID(cmd) == 1 /* AFG */)
1838	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].afg.u32F05_param;
1839	else if (codecIsDacNode(pState, CODEC_NID(cmd)))
1840	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].dac.u32F05_param;
1841	else if (codecIsDigInPinNode(pState, CODEC_NID(cmd)))
1842	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].digin.u32F05_param;
1843	else if (codecIsAdcNode(pState, CODEC_NID(cmd)))
1844	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].adc.u32F05_param;
1845	else if (codecIsSpdifOutNode(pState, CODEC_NID(cmd)))
1846	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].spdifout.u32F05_param;
1847	else if (codecIsSpdifInNode(pState, CODEC_NID(cmd)))
1848	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].spdifin.u32F05_param;
1849	else if (codecIsReservedNode(pState, CODEC_NID(cmd)))
1850	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].reserved.u32F05_param;
1851	Assert((pu32Reg));
1852	if (!pu32Reg)
1853	return VINF_SUCCESS;
1854
1855	bool fReset = CODEC_F05_IS_RESET(*pu32Reg);
1856	bool fStopOk = CODEC_F05_IS_STOPOK(*pu32Reg);
1857
1858	if (CODEC_NID(cmd) != 1 /* AFG */)
1859	{
1860	/*
1861	* We shouldn't propogate actual power state, which actual for AFG
1862	*/
1863	*pu32Reg = CODEC_MAKE_F05(fReset, fStopOk, 0,
1864	CODEC_F05_ACT(pState->pNodes[1].afg.u32F05_param),
1865	CODEC_F05_SET(cmd));
1866	}
1867
1868	/* Propagate next power state only if AFG is on or verb modifies AFG power state */
1869	if ( CODEC_NID(cmd) == 1 /* AFG */
1870	\|\| !CODEC_F05_ACT(pState->pNodes[1].afg.u32F05_param))
1871	{
1872	*pu32Reg = CODEC_MAKE_F05(fReset, fStopOk, 0, CODEC_F05_SET(cmd), CODEC_F05_SET(cmd));
1873	if ( CODEC_NID(cmd) == 1 /* AFG */
1874	&& (CODEC_F05_SET(cmd)) == CODEC_F05_D0)
1875	{
1876	/* now we're powered on AFG and may propogate power states on nodes */
1877	const uint8_t *pu8NodeIndex = &pState->au8Dacs[0];
1878	while (*(++pu8NodeIndex))
1879	codecPropogatePowerState(&pState->pNodes[*pu8NodeIndex].dac.u32F05_param);
1880
1881	pu8NodeIndex = &pState->au8Adcs[0];
1882	while (*(++pu8NodeIndex))
1883	codecPropogatePowerState(&pState->pNodes[*pu8NodeIndex].adc.u32F05_param);
1884
1885	pu8NodeIndex = &pState->au8DigInPins[0];
1886	while (*(++pu8NodeIndex))
1887	codecPropogatePowerState(&pState->pNodes[*pu8NodeIndex].digin.u32F05_param);
1888	}
1889	}
1890	return VINF_SUCCESS;
1891	}
1892
1893	static int codecGetStreamId(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1894	{
1895	Assert((CODEC_CAD(cmd) == pState->id));
1896	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1897	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1898	{
1899	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1900	return VINF_SUCCESS;
1901	}
1902	*pResp = 0;
1903	if (codecIsDacNode(pState, CODEC_NID(cmd)))
1904	*pResp = pState->pNodes[CODEC_NID(cmd)].dac.u32F06_param;
1905	else if (codecIsAdcNode(pState, CODEC_NID(cmd)))
1906	*pResp = pState->pNodes[CODEC_NID(cmd)].adc.u32F06_param;
1907	else if (codecIsSpdifInNode(pState, CODEC_NID(cmd)))
1908	*pResp = pState->pNodes[CODEC_NID(cmd)].spdifin.u32F06_param;
1909	else if (codecIsSpdifOutNode(pState, CODEC_NID(cmd)))
1910	*pResp = pState->pNodes[CODEC_NID(cmd)].spdifout.u32F06_param;
1911	else if (CODEC_NID(cmd) == 0x1A)
1912	*pResp = pState->pNodes[CODEC_NID(cmd)].reserved.u32F06_param;
1913	return VINF_SUCCESS;
1914	}
1915	static int codecSetStreamId(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1916	{
1917	Assert((CODEC_CAD(cmd) == pState->id));
1918	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1919	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1920	{
1921	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1922	return VINF_SUCCESS;
1923	}
1924	*pResp = 0;
1925	uint32_t *pu32addr = NULL;
1926	*pResp = 0;
1927	if (codecIsDacNode(pState, CODEC_NID(cmd)))
1928	pu32addr = &pState->pNodes[CODEC_NID(cmd)].dac.u32F06_param;
1929	else if (codecIsAdcNode(pState, CODEC_NID(cmd)))
1930	pu32addr = &pState->pNodes[CODEC_NID(cmd)].adc.u32F06_param;
1931	else if (codecIsSpdifOutNode(pState, CODEC_NID(cmd)))
1932	pu32addr = &pState->pNodes[CODEC_NID(cmd)].spdifout.u32F06_param;
1933	else if (codecIsSpdifInNode(pState, CODEC_NID(cmd)))
1934	pu32addr = &pState->pNodes[CODEC_NID(cmd)].spdifin.u32F06_param;
1935	else if (codecIsReservedNode(pState, CODEC_NID(cmd)))
1936	pu32addr = &pState->pNodes[CODEC_NID(cmd)].reserved.u32F06_param;
1937	Assert((pu32addr));
1938	if (pu32addr)
1939	codecSetRegisterU8(pu32addr, cmd, 0);
1940	return VINF_SUCCESS;
1941	}
1942
1943	static int codecGetConverterFormat(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1944	{
1945	Assert((CODEC_CAD(cmd) == pState->id));
1946	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1947	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1948	{
1949	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1950	return VINF_SUCCESS;
1951	}
1952	*pResp = 0;
1953	if (codecIsDacNode(pState, CODEC_NID(cmd)))
1954	*pResp = pState->pNodes[CODEC_NID(cmd)].dac.u32A_param;
1955	else if (codecIsAdcNode(pState, CODEC_NID(cmd)))
1956	*pResp = pState->pNodes[CODEC_NID(cmd)].adc.u32A_param;
1957	else if (codecIsSpdifOutNode(pState, CODEC_NID(cmd)))
1958	*pResp = pState->pNodes[CODEC_NID(cmd)].spdifout.u32A_param;
1959	else if (codecIsSpdifInNode(pState, CODEC_NID(cmd)))
1960	*pResp = pState->pNodes[CODEC_NID(cmd)].spdifin.u32A_param;
1961	return VINF_SUCCESS;
1962	}
1963
1964	static int codecSetConverterFormat(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1965	{
1966	Assert((CODEC_CAD(cmd) == pState->id));
1967	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1968	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1969	{
1970	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1971	return VINF_SUCCESS;
1972	}
1973	*pResp = 0;
1974	if (codecIsDacNode(pState, CODEC_NID(cmd)))
1975	codecSetRegisterU16(&pState->pNodes[CODEC_NID(cmd)].dac.u32A_param, cmd, 0);
1976	else if (codecIsAdcNode(pState, CODEC_NID(cmd)))
1977	codecSetRegisterU16(&pState->pNodes[CODEC_NID(cmd)].adc.u32A_param, cmd, 0);
1978	else if (codecIsSpdifOutNode(pState, CODEC_NID(cmd)))
1979	codecSetRegisterU16(&pState->pNodes[CODEC_NID(cmd)].spdifout.u32A_param, cmd, 0);
1980	else if (codecIsSpdifInNode(pState, CODEC_NID(cmd)))
1981	codecSetRegisterU16(&pState->pNodes[CODEC_NID(cmd)].spdifin.u32A_param, cmd, 0);
1982	return VINF_SUCCESS;
1983	}
1984
1985	/* F0C */
1986	static int codecGetEAPD_BTLEnabled(struct CODECState pState, uint32_t cmd, uint64_t pResp)
1987	{
1988	Assert((CODEC_CAD(cmd) == pState->id));
1989	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
1990	if (CODEC_NID(cmd) >= pState->cTotalNodes)
1991	{
1992	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
1993	return VINF_SUCCESS;
1994	}
1995	*pResp = 0;
1996	if (codecIsAdcVolNode(pState, CODEC_NID(cmd)))
1997	*pResp = pState->pNodes[CODEC_NID(cmd)].adcvol.u32F0c_param;
1998	else if (codecIsDacNode(pState, CODEC_NID(cmd)))
1999	*pResp = pState->pNodes[CODEC_NID(cmd)].dac.u32F0c_param;
2000	else if (codecIsDigInPinNode(pState, CODEC_NID(cmd)))
2001	*pResp = pState->pNodes[CODEC_NID(cmd)].digin.u32F0c_param;
2002	return VINF_SUCCESS;
2003	}
2004
2005	/* 70C */
2006	static int codecSetEAPD_BTLEnabled(struct CODECState pState, uint32_t cmd, uint64_t pResp)
2007	{
2008	Assert((CODEC_CAD(cmd) == pState->id));
2009	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
2010	if (CODEC_NID(cmd) >= pState->cTotalNodes)
2011	{
2012	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
2013	return VINF_SUCCESS;
2014	}
2015	*pResp = 0;
2016	uint32_t *pu32Reg = NULL;
2017	if (codecIsAdcVolNode(pState, CODEC_NID(cmd)))
2018	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].adcvol.u32F0c_param;
2019	else if (codecIsDacNode(pState, CODEC_NID(cmd)))
2020	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].dac.u32F0c_param;
2021	else if (codecIsDigInPinNode(pState, CODEC_NID(cmd)))
2022	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].digin.u32F0c_param;
2023	*pResp = 0;
2024	Assert((pu32Reg));
2025	if (pu32Reg)
2026	codecSetRegisterU8(pu32Reg, cmd, 0);
2027	return VINF_SUCCESS;
2028	}
2029
2030	/* F0F */
2031	static int codecGetVolumeKnobCtrl(struct CODECState pState, uint32_t cmd, uint64_t pResp)
2032	{
2033	Assert((CODEC_CAD(cmd) == pState->id));
2034	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
2035	if (CODEC_NID(cmd) >= pState->cTotalNodes)
2036	{
2037	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
2038	return VINF_SUCCESS;
2039	}
2040	*pResp = 0;
2041	if (codecIsVolKnobNode(pState, CODEC_NID(cmd)))
2042	*pResp = pState->pNodes[CODEC_NID(cmd)].volumeKnob.u32F0f_param;
2043	return VINF_SUCCESS;
2044	}
2045
2046	/* 70F */
2047	static int codecSetVolumeKnobCtrl(struct CODECState pState, uint32_t cmd, uint64_t pResp)
2048	{
2049	Assert((CODEC_CAD(cmd) == pState->id));
2050	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
2051	if (CODEC_NID(cmd) >= pState->cTotalNodes)
2052	{
2053	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
2054	return VINF_SUCCESS;
2055	}
2056	uint32_t *pu32Reg = NULL;
2057	*pResp = 0;
2058	if (codecIsVolKnobNode(pState, CODEC_NID(cmd)))
2059	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].volumeKnob.u32F0f_param;
2060	Assert((pu32Reg));
2061	if (pu32Reg)
2062	codecSetRegisterU8(pu32Reg, cmd, 0);
2063	return VINF_SUCCESS;
2064	}
2065
2066	/* F17 */
2067	static int codecGetGPIOUnsolisted (struct CODECState pState, uint32_t cmd, uint64_t pResp)
2068	{
2069	Assert((CODEC_CAD(cmd) == pState->id));
2070	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
2071	if (CODEC_NID(cmd) >= pState->cTotalNodes)
2072	{
2073	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
2074	return VINF_SUCCESS;
2075	}
2076	*pResp = 0;
2077	/* note: this is true for ALC885 */
2078	if (CODEC_NID(cmd) == 0x1 /* AFG */)
2079	*pResp = pState->pNodes[1].afg.u32F17_param;
2080	return VINF_SUCCESS;
2081	}
2082
2083	/* 717 */
2084	static int codecSetGPIOUnsolisted (struct CODECState pState, uint32_t cmd, uint64_t pResp)
2085	{
2086	Assert((CODEC_CAD(cmd) == pState->id));
2087	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
2088	if (CODEC_NID(cmd) >= pState->cTotalNodes)
2089	{
2090	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
2091	return VINF_SUCCESS;
2092	}
2093	uint32_t *pu32Reg = NULL;
2094	*pResp = 0;
2095	if (CODEC_NID(cmd) == 1 /* AFG */)
2096	pu32Reg = &pState->pNodes[1].afg.u32F17_param;
2097	Assert((pu32Reg));
2098	if (pu32Reg)
2099	codecSetRegisterU8(pu32Reg, cmd, 0);
2100	return VINF_SUCCESS;
2101	}
2102
2103	/* F1C */
2104	static int codecGetConfig (struct CODECState pState, uint32_t cmd, uint64_t pResp)
2105	{
2106	Assert((CODEC_CAD(cmd) == pState->id));
2107	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
2108	if (CODEC_NID(cmd) >= pState->cTotalNodes)
2109	{
2110	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
2111	return VINF_SUCCESS;
2112	}
2113	*pResp = 0;
2114	if (codecIsPortNode(pState, CODEC_NID(cmd)))
2115	*pResp = pState->pNodes[CODEC_NID(cmd)].port.u32F1c_param;
2116	else if (codecIsDigOutPinNode(pState, CODEC_NID(cmd)))
2117	*pResp = pState->pNodes[CODEC_NID(cmd)].digout.u32F1c_param;
2118	else if (codecIsDigInPinNode(pState, CODEC_NID(cmd)))
2119	*pResp = pState->pNodes[CODEC_NID(cmd)].digin.u32F1c_param;
2120	else if (codecIsPcbeepNode(pState, CODEC_NID(cmd)))
2121	*pResp = pState->pNodes[CODEC_NID(cmd)].pcbeep.u32F1c_param;
2122	else if (codecIsCdNode(pState, CODEC_NID(cmd)))
2123	*pResp = pState->pNodes[CODEC_NID(cmd)].cdnode.u32F1c_param;
2124	else if (codecIsReservedNode(pState, CODEC_NID(cmd)))
2125	*pResp = pState->pNodes[CODEC_NID(cmd)].reserved.u32F1c_param;
2126	return VINF_SUCCESS;
2127	}
2128	static int codecSetConfigX(struct CODECState *pState, uint32_t cmd, uint8_t u8Offset)
2129	{
2130	Assert((CODEC_CAD(cmd) == pState->id));
2131	Assert((CODEC_NID(cmd) < pState->cTotalNodes));
2132	if (CODEC_NID(cmd) >= pState->cTotalNodes)
2133	{
2134	Log(("HDAcodec: invalid node address %d\n", CODEC_NID(cmd)));
2135	return VINF_SUCCESS;
2136	}
2137	uint32_t *pu32Reg = NULL;
2138	if (codecIsPortNode(pState, CODEC_NID(cmd)))
2139	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].port.u32F1c_param;
2140	else if (codecIsDigInPinNode(pState, CODEC_NID(cmd)))
2141	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].digin.u32F1c_param;
2142	else if (codecIsDigOutPinNode(pState, CODEC_NID(cmd)))
2143	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].digout.u32F1c_param;
2144	else if (codecIsCdNode(pState, CODEC_NID(cmd)))
2145	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].cdnode.u32F1c_param;
2146	else if (codecIsPcbeepNode(pState, CODEC_NID(cmd)))
2147	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].pcbeep.u32F1c_param;
2148	else if (codecIsReservedNode(pState, CODEC_NID(cmd)))
2149	pu32Reg = &pState->pNodes[CODEC_NID(cmd)].reserved.u32F1c_param;
2150	Assert((pu32Reg));
2151	if (pu32Reg)
2152	codecSetRegisterU8(pu32Reg, cmd, u8Offset);
2153	return VINF_SUCCESS;
2154	}
2155	/* 71C */
2156	static int codecSetConfig0 (struct CODECState pState, uint32_t cmd, uint64_t pResp)
2157	{
2158	*pResp = 0;
2159	return codecSetConfigX(pState, cmd, 0);
2160	}
2161	/* 71D */
2162	static int codecSetConfig1 (struct CODECState pState, uint32_t cmd, uint64_t pResp)
2163	{
2164	*pResp = 0;
2165	return codecSetConfigX(pState, cmd, 8);
2166	}
2167	/* 71E */
2168	static int codecSetConfig2 (struct CODECState pState, uint32_t cmd, uint64_t pResp)
2169	{
2170	*pResp = 0;
2171	return codecSetConfigX(pState, cmd, 16);
2172	}
2173	/* 71E */
2174	static int codecSetConfig3 (struct CODECState pState, uint32_t cmd, uint64_t pResp)
2175	{
2176	*pResp = 0;
2177	return codecSetConfigX(pState, cmd, 24);
2178	}
2179
2180
2181	static int codecToAudVolume(AMPLIFIER *pAmp, audmixerctl_t mt)
2182	{
2183	uint32_t dir = AMPLIFIER_OUT;
2184	switch (mt)
2185	{
2186	case AUD_MIXER_VOLUME:
2187	case AUD_MIXER_PCM:
2188	dir = AMPLIFIER_OUT;
2189	break;
2190	case AUD_MIXER_LINE_IN:
2191	dir = AMPLIFIER_IN;
2192	break;
2193	}
2194	int mute = AMPLIFIER_REGISTER(*pAmp, dir, AMPLIFIER_LEFT, 0) & RT_BIT(7);
2195	mute \|= AMPLIFIER_REGISTER(*pAmp, dir, AMPLIFIER_RIGHT, 0) & RT_BIT(7);
2196	mute >>=7;
2197	mute &= 0x1;
2198	uint8_t lVol = AMPLIFIER_REGISTER(*pAmp, dir, AMPLIFIER_LEFT, 0) & 0x7f;
2199	uint8_t rVol = AMPLIFIER_REGISTER(*pAmp, dir, AMPLIFIER_RIGHT, 0) & 0x7f;
2200	AUD_set_volume(mt, &mute, &lVol, &rVol);
2201	return VINF_SUCCESS;
2202	}
2203
2204	static CODECVERB CODECVERBS[] =
2205	{
2206	/* verb \| verb mask \| callback */
2207	/* ----------- -------------------- ----------------------- */
2208	{0x000F0000, CODEC_VERB_8BIT_CMD , codecGetParameter },
2209	{0x000F0100, CODEC_VERB_8BIT_CMD , codecGetConSelectCtrl },
2210	{0x00070100, CODEC_VERB_8BIT_CMD , codecSetConSelectCtrl },
2211	{0x000F0600, CODEC_VERB_8BIT_CMD , codecGetStreamId },
2212	{0x00070600, CODEC_VERB_8BIT_CMD , codecSetStreamId },
2213	{0x000F0700, CODEC_VERB_8BIT_CMD , codecGetPinCtrl },
2214	{0x00070700, CODEC_VERB_8BIT_CMD , codecSetPinCtrl },
2215	{0x000F0800, CODEC_VERB_8BIT_CMD , codecGetUnsolicitedEnabled },
2216	{0x00070800, CODEC_VERB_8BIT_CMD , codecSetUnsolicitedEnabled },
2217	{0x000F0900, CODEC_VERB_8BIT_CMD , codecGetPinSense },
2218	{0x00070900, CODEC_VERB_8BIT_CMD , codecSetPinSense },
2219	{0x000F0200, CODEC_VERB_8BIT_CMD , codecGetConnectionListEntry },
2220	{0x000F0300, CODEC_VERB_8BIT_CMD , codecGetProcessingState },
2221	{0x00070300, CODEC_VERB_8BIT_CMD , codecSetProcessingState },
2222	{0x000F0D00, CODEC_VERB_8BIT_CMD , codecGetDigitalConverter },
2223	{0x00070D00, CODEC_VERB_8BIT_CMD , codecSetDigitalConverter1 },
2224	{0x00070E00, CODEC_VERB_8BIT_CMD , codecSetDigitalConverter2 },
2225	{0x000F2000, CODEC_VERB_8BIT_CMD , codecGetSubId },
2226	{0x00072000, CODEC_VERB_8BIT_CMD , codecSetSubId0 },
2227	{0x00072100, CODEC_VERB_8BIT_CMD , codecSetSubId1 },
2228	{0x00072200, CODEC_VERB_8BIT_CMD , codecSetSubId2 },
2229	{0x00072300, CODEC_VERB_8BIT_CMD , codecSetSubId3 },
2230	{0x0007FF00, CODEC_VERB_8BIT_CMD , codecReset },
2231	{0x000F0500, CODEC_VERB_8BIT_CMD , codecGetPowerState },
2232	{0x00070500, CODEC_VERB_8BIT_CMD , codecSetPowerState },
2233	{0x000F0C00, CODEC_VERB_8BIT_CMD , codecGetEAPD_BTLEnabled },
2234	{0x00070C00, CODEC_VERB_8BIT_CMD , codecSetEAPD_BTLEnabled },
2235	{0x000F0F00, CODEC_VERB_8BIT_CMD , codecGetVolumeKnobCtrl },
2236	{0x00070F00, CODEC_VERB_8BIT_CMD , codecSetVolumeKnobCtrl },
2237	{0x000F1700, CODEC_VERB_8BIT_CMD , codecGetGPIOUnsolisted },
2238	{0x00071700, CODEC_VERB_8BIT_CMD , codecSetGPIOUnsolisted },
2239	{0x000F1C00, CODEC_VERB_8BIT_CMD , codecGetConfig },
2240	{0x00071C00, CODEC_VERB_8BIT_CMD , codecSetConfig0 },
2241	{0x00071D00, CODEC_VERB_8BIT_CMD , codecSetConfig1 },
2242	{0x00071E00, CODEC_VERB_8BIT_CMD , codecSetConfig2 },
2243	{0x00071F00, CODEC_VERB_8BIT_CMD , codecSetConfig3 },
2244	{0x000A0000, CODEC_VERB_16BIT_CMD, codecGetConverterFormat },
2245	{0x00020000, CODEC_VERB_16BIT_CMD, codecSetConverterFormat },
2246	{0x000B0000, CODEC_VERB_16BIT_CMD, codecGetAmplifier },
2247	{0x00030000, CODEC_VERB_16BIT_CMD, codecSetAmplifier },
2248	};
2249
2250	static int codecLookup(CODECState *pState, uint32_t cmd, PPFNCODECVERBPROCESSOR pfn)
2251	{
2252	int rc = VINF_SUCCESS;
2253	Assert(CODEC_CAD(cmd) == pState->id);
2254	if (codecIsReservedNode(pState, CODEC_NID(cmd)))
2255	{
2256	LogRel(("HDAcodec: cmd %x was addressed to reserved node\n", cmd));
2257	}
2258	if ( CODEC_VERBDATA(cmd) == 0
2259	\|\| CODEC_NID(cmd) >= pState->cTotalNodes)
2260	{
2261	*pfn = codecUnimplemented;
2262	//** @todo r=michaln: There needs to be a counter to avoid log flooding (see e.g. DevRTC.cpp)
2263	LogRel(("HDAcodec: cmd %x was ignored\n", cmd));
2264	return VINF_SUCCESS;
2265	}
2266	for (int i = 0; i < pState->cVerbs; ++i)
2267	{
2268	if ((CODEC_VERBDATA(cmd) & pState->pVerbs[i].mask) == pState->pVerbs[i].verb)
2269	{
2270	*pfn = pState->pVerbs[i].pfn;
2271	return VINF_SUCCESS;
2272	}
2273	}
2274	*pfn = codecUnimplemented;
2275	LogRel(("HDAcodec: callback for %x wasn't found\n", CODEC_VERBDATA(cmd)));
2276	return rc;
2277	}
2278
2279	static void pi_callback (void *opaque, int avail)
2280	{
2281	CODECState pState = (CODECState )opaque;
2282	pState->pfnTransfer(pState, PI_INDEX, avail);
2283	}
2284
2285	static void po_callback (void *opaque, int avail)
2286	{
2287	CODECState pState = (CODECState )opaque;
2288	pState->pfnTransfer(pState, PO_INDEX, avail);
2289	}
2290
2291	static void mc_callback (void *opaque, int avail)
2292	{
2293	CODECState pState = (CODECState )opaque;
2294	pState->pfnTransfer(pState, MC_INDEX, avail);
2295	}
2296
2297	int codecConstruct(CODECState *pState, ENMCODEC enmCodec)
2298	{
2299	audsettings_t as;
2300	int rc;
2301	pState->pVerbs = (CODECVERB *)&CODECVERBS;
2302	pState->cVerbs = sizeof(CODECVERBS)/sizeof(CODECVERB);
2303	pState->pfnLookup = codecLookup;
2304	pState->enmCodec = enmCodec;
2305	switch (enmCodec)
2306	{
2307	case STAC9220_CODEC:
2308	rc = stac9220Construct(pState);
2309	AssertRC(rc);
2310	break;
2311	case ALC885_CODEC:
2312	rc = alc885Construct(pState);
2313	AssertRC(rc);
2314	break;
2315	default:
2316	AssertMsgFailed(("Unsupported Codec"));
2317	}
2318	/* common root node initializers */
2319	pState->pNodes[0].node.au32F00_param[0] = CODEC_MAKE_F00_00(pState->u16VendorId, pState->u16DeviceId);
2320	pState->pNodes[0].node.au32F00_param[4] = CODEC_MAKE_F00_04(0x1, 0x1);
2321	/* common AFG node initializers */
2322	pState->pNodes[1].node.au32F00_param[4] = CODEC_MAKE_F00_04(0x2, pState->cTotalNodes - 2);
2323	pState->pNodes[1].node.au32F00_param[5] = CODEC_MAKE_F00_05(CODEC_F00_05_UNSOL, CODEC_F00_05_AFG);
2324	pState->pNodes[1].afg.u32F20_param = CODEC_MAKE_F20(pState->u16VendorId, pState->u8BSKU, pState->u8AssemblyId);
2325
2326	//** @todo r=michaln: Was this meant to be 'HDA' or something like that? (AC'97 was on ICH0)
2327	AUD_register_card ("ICH0", &pState->card);
2328
2329	/* 44.1 kHz */
2330	as.freq = 44100;
2331	as.nchannels = 2;
2332	as.fmt = AUD_FMT_S16;
2333	as.endianness = 0;
2334	#define SETUP_AUDIO_FORMAT(pState, base, mult, div, name, as, in_callback, out_callback) \
2335	do{ \
2336	AUDIO_FORMAT_SELECTOR((pState), Out, (base), (mult), div) = AUD_open_out(&(pState)->card, \
2337	AUDIO_FORMAT_SELECTOR(pState, Out, (base), (mult), (div)), name ".out", (pState), (out_callback), &(as)); \
2338	if (!AUDIO_FORMAT_SELECTOR(pState, Out, (base), (mult), (div))) \
2339	LogRel (("HDAcodec: WARNING: Unable to open PCM OUT(%s)!\n", name ".out")); \
2340	AUDIO_FORMAT_SELECTOR(pState, In, (base), (mult), (div)) = AUD_open_in(&(pState)->card, \
2341	AUDIO_FORMAT_SELECTOR(pState, In, (base), (mult), (div)), name ".in", (pState), (in_callback), &(as)); \
2342	if (!AUDIO_FORMAT_SELECTOR(pState, In, (base), (mult), (div))) \
2343	LogRel (("HDAcodec: WARNING: Unable to open PCM IN(%s)!\n", name ".in")); \
2344	} while(0)
2345	#define IS_FORMAT_SUPPORTED_BY_HOST(pState, base, mult, div) (AUDIO_FORMAT_SELECTOR((pState), Out, (base), (mult), (div)) \
2346	&& AUDIO_FORMAT_SELECTOR((pState), In, (base), (mult), (div)))
2347
2348	pState->pNodes[1].node.au32F00_param[0xA] = CODEC_F00_0A_16_BIT;
2349	SETUP_AUDIO_FORMAT(pState, AFMT_HZ_44_1K, AFMT_MULT_X1, AFMT_DIV_X1, "hda44_1", as, pi_callback, po_callback);
2350	pState->pNodes[1].node.au32F00_param[0xA] \|= IS_FORMAT_SUPPORTED_BY_HOST(pState, AFMT_HZ_44_1K, AFMT_MULT_X1, AFMT_DIV_X1) ? CODEC_F00_0A_44_1KHZ : 0;
2351
2352	#ifdef VBOX_WITH_AUDIO_FLEXIBLE_FORMAT
2353	as.freq = 2; / 2 * 44.1kHz */
2354	SETUP_AUDIO_FORMAT(pState, AFMT_HZ_44_1K, AFMT_MULT_X2, AFMT_DIV_X1, "hda44_1_2x", as, pi_callback, po_callback);
2355	pState->pNodes[1].node.au32F00_param[0xA] \|= IS_FORMAT_SUPPORTED_BY_HOST(pState, AFMT_HZ_44_1K, AFMT_MULT_X2, AFMT_DIV_X1) ? CODEC_F00_0A_44_1KHZ_MULT_2X : 0;
2356
2357	as.freq = 2; / 4 * 44.1kHz */
2358	SETUP_AUDIO_FORMAT(pState, AFMT_HZ_44_1K, AFMT_MULT_X4, AFMT_DIV_X1, "hda44_1_4x", as, pi_callback, po_callback);
2359	pState->pNodes[1].node.au32F00_param[0xA] \|= IS_FORMAT_SUPPORTED_BY_HOST(pState, AFMT_HZ_44_1K, AFMT_MULT_X4, AFMT_DIV_X1) ? CODEC_F00_0A_44_1KHZ_MULT_4X : 0;
2360
2361	as.freq = 48000;
2362	SETUP_AUDIO_FORMAT(pState, AFMT_HZ_48K, AFMT_MULT_X1, AFMT_DIV_X1, "hda48", as, pi_callback, po_callback);
2363	pState->pNodes[1].node.au32F00_param[0xA] \|= IS_FORMAT_SUPPORTED_BY_HOST(pState, AFMT_HZ_48K, AFMT_MULT_X1, AFMT_DIV_X1) ? CODEC_F00_0A_48KHZ : 0;
2364
2365	# if 0
2366	as.freq = 2; / 2 * 48kHz */
2367	SETUP_AUDIO_FORMAT(pState, AFMT_HZ_48K, AFMT_MULT_X2, AFMT_DIV_X1, "hda48_2x", as, pi_callback, po_callback);
2368	pState->pNodes[1].node.au32F00_param[0xA] \|= IS_FORMAT_SUPPORTED_BY_HOST(pState, AFMT_HZ_48K, AFMT_MULT_X2, AFMT_DIV_X1) ? CODEC_F00_0A_48KHZ_MULT_2X : 0;
2369
2370	as.freq = 2; / 4 * 48kHz */
2371	SETUP_AUDIO_FORMAT(pState, AFMT_HZ_48K, AFMT_MULT_X4, AFMT_DIV_X1, "hda48_4x", as, pi_callback, po_callback);
2372	pState->pNodes[1].node.au32F00_param[0xA] \|= IS_FORMAT_SUPPORTED_BY_HOST(pState, AFMT_HZ_48K, AFMT_MULT_X4, AFMT_DIV_X1) ? CODEC_F00_0A_48KHZ_MULT_4X : 0;
2373	# endif
2374	#endif
2375	#undef SETUP_AUDIO_FORMAT
2376	#undef IS_FORMAT_SUPPORTED_BY_HOST
2377
2378	uint8_t i;
2379	Assert(pState->pNodes);
2380	Assert(pState->pfnCodecNodeReset);
2381	for (i = 0; i < pState->cTotalNodes; ++i)
2382	{
2383	pState->pfnCodecNodeReset(pState, i, &pState->pNodes[i]);
2384	}
2385
2386	codecToAudVolume(&pState->pNodes[pState->u8DacLineOut].dac.B_params, AUD_MIXER_VOLUME);
2387	codecToAudVolume(&pState->pNodes[pState->u8AdcVolsLineIn].adcvol.B_params, AUD_MIXER_LINE_IN);
2388
2389	return VINF_SUCCESS;
2390	}
2391	int codecDestruct(CODECState *pCodecState)
2392	{
2393	RTMemFree(pCodecState->pNodes);
2394	return VINF_SUCCESS;
2395	}
2396
2397	int codecSaveState(CODECState *pCodecState, PSSMHANDLE pSSMHandle)
2398	{
2399	SSMR3PutMem (pSSMHandle, pCodecState->pNodes, sizeof(CODECNODE) * pCodecState->cTotalNodes);
2400	return VINF_SUCCESS;
2401	}
2402
2403	int codecLoadState(CODECState *pCodecState, PSSMHANDLE pSSMHandle)
2404	{
2405	SSMR3GetMem (pSSMHandle, pCodecState->pNodes, sizeof(CODECNODE) * pCodecState->cTotalNodes);
2406	if (codecIsDacNode(pCodecState, pCodecState->u8DacLineOut))
2407	codecToAudVolume(&pCodecState->pNodes[pCodecState->u8DacLineOut].dac.B_params, AUD_MIXER_VOLUME);
2408	else if (codecIsSpdifOutNode(pCodecState, pCodecState->u8DacLineOut))
2409	codecToAudVolume(&pCodecState->pNodes[pCodecState->u8DacLineOut].spdifout.B_params, AUD_MIXER_VOLUME);
2410	codecToAudVolume(&pCodecState->pNodes[pCodecState->u8AdcVolsLineIn].adcvol.B_params, AUD_MIXER_LINE_IN);
2411	return VINF_SUCCESS;
2412	}

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source: vbox/trunk/src/VBox/Devices/Audio/DevCodec.cpp@ 33829

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