VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevHDA.cpp@ 65003

Last change on this file since 65003 was 65003, checked in by vboxsync, 8 years ago

Audio/DevHDA.cpp: VBOX_WITH_HDA_ASYNC_IO -> VBOX_WITH_AUDIO_HDA_ASYNC_IO, logging.
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1/* $Id: DevHDA.cpp 65003 2016-12-23 14:18:23Z vboxsync $ */
2/** @file
3 * DevHDA - VBox Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2016 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22
23/*********************************************************************************************************************************
24* Header Files *
25*********************************************************************************************************************************/
26#define LOG_GROUP LOG_GROUP_DEV_HDA
27#include <VBox/log.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/pdmaudioifs.h>
30#include <VBox/version.h>
31
32#include <iprt/assert.h>
33#include <iprt/asm.h>
34#include <iprt/asm-math.h>
35#include <iprt/file.h>
36#include <iprt/list.h>
37#ifdef IN_RING3
38# include <iprt/mem.h>
39# include <iprt/semaphore.h>
40# include <iprt/string.h>
41# include <iprt/uuid.h>
42#endif
43
44#include "VBoxDD.h"
45
46#include "AudioMixBuffer.h"
47#include "AudioMixer.h"
48#include "HDACodec.h"
49#include "DevHDACommon.h"
50#include "DrvAudio.h"
51
52
53/*********************************************************************************************************************************
54* Defined Constants And Macros *
55*********************************************************************************************************************************/
56//#define HDA_AS_PCI_EXPRESS
57#define VBOX_WITH_INTEL_HDA
58
59/*
60 * HDA_DEBUG_DUMP_PCM_DATA enables dumping the raw PCM data
61 * to a file on the host. Be sure to adjust HDA_DEBUG_DUMP_PCM_DATA_PATH
62 * to your needs before using this!
63 */
64//#define HDA_DEBUG_DUMP_PCM_DATA
65#ifdef HDA_DEBUG_DUMP_PCM_DATA
66# ifdef RT_OS_WINDOWS
67# define HDA_DEBUG_DUMP_PCM_DATA_PATH "c:\\temp\\"
68# else
69# define HDA_DEBUG_DUMP_PCM_DATA_PATH "/tmp/"
70# endif
71#endif
72
73#if defined(VBOX_WITH_HP_HDA)
74/* HP Pavilion dv4t-1300 */
75# define HDA_PCI_VENDOR_ID 0x103c
76# define HDA_PCI_DEVICE_ID 0x30f7
77#elif defined(VBOX_WITH_INTEL_HDA)
78/* Intel HDA controller */
79# define HDA_PCI_VENDOR_ID 0x8086
80# define HDA_PCI_DEVICE_ID 0x2668
81#elif defined(VBOX_WITH_NVIDIA_HDA)
82/* nVidia HDA controller */
83# define HDA_PCI_VENDOR_ID 0x10de
84# define HDA_PCI_DEVICE_ID 0x0ac0
85#else
86# error "Please specify your HDA device vendor/device IDs"
87#endif
88
89/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
90 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
91 * is read only except for bit 15 like the HDA spec states.
92 *
93 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
94 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
95#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
96
97/* Make sure that interleaving streams support is enabled if the 5.1 surround code is being used. */
98#if defined (VBOX_WITH_AUDIO_HDA_51_SURROUND) && !defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT)
99# define VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT
100#endif
101
102/** Default timer frequency (in Hz). */
103#define HDA_TIMER_HZ 100
104
105/**
106 * At the moment we support 4 input + 4 output streams max, which is 8 in total.
107 * Bidirectional streams are currently *not* supported.
108 *
109 * Note: When changing any of those values, be prepared for some saved state
110 * fixups / trouble!
111 */
112#define HDA_MAX_SDI 4
113#define HDA_MAX_SDO 4
114#define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
115AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
116
117/** Number of general registers. */
118#define HDA_NUM_GENERAL_REGS 34
119/** Number of total registers in the HDA's register map. */
120#define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */))
121/** Total number of stream tags (channels). Index 0 is reserved / invalid. */
122#define HDA_MAX_TAGS 16
123
124/**
125 * NB: Register values stored in memory (au32Regs[]) are indexed through
126 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
127 * register descriptors in g_aHdaRegMap[] are indexed through the
128 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
129 *
130 * The au32Regs[] layout is kept unchanged for saved state
131 * compatibility.
132 */
133
134/* Registers */
135#define HDA_REG_IND_NAME(x) HDA_REG_##x
136#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
137#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
138#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
139#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
140#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
141#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
142#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
143
144
145#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
146#define HDA_RMX_GCAP 0
147/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
148 * oss (15:12) - number of output streams supported
149 * iss (11:8) - number of input streams supported
150 * bss (7:3) - number of bidirectional streams supported
151 * bds (2:1) - number of serial data out (SDO) signals supported
152 * b64sup (0) - 64 bit addressing supported.
153 */
154#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
155 ( (((oss) & 0xF) << 12) \
156 | (((iss) & 0xF) << 8) \
157 | (((bss) & 0x1F) << 3) \
158 | (((bds) & 0x3) << 1) \
159 | ((b64sup) & 1))
160
161#define HDA_REG_VMIN 1 /* 0x02 */
162#define HDA_RMX_VMIN 1
163
164#define HDA_REG_VMAJ 2 /* 0x03 */
165#define HDA_RMX_VMAJ 2
166
167#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
168#define HDA_RMX_OUTPAY 3
169
170#define HDA_REG_INPAY 4 /* 0x06-0x07 */
171#define HDA_RMX_INPAY 4
172
173#define HDA_REG_GCTL 5 /* 0x08-0x0B */
174#define HDA_RMX_GCTL 5
175#define HDA_GCTL_RST_SHIFT 0
176#define HDA_GCTL_FSH_SHIFT 1
177#define HDA_GCTL_UR_SHIFT 8
178
179#define HDA_REG_WAKEEN 6 /* 0x0C */
180#define HDA_RMX_WAKEEN 6
181
182#define HDA_REG_STATESTS 7 /* 0x0E */
183#define HDA_RMX_STATESTS 7
184#define HDA_STATESTS_SCSF_MASK 0x7 /* State Change Status Flags (6.2.8). */
185
186#define HDA_REG_GSTS 8 /* 0x10-0x11*/
187#define HDA_RMX_GSTS 8
188#define HDA_GSTS_FSH_SHIFT 1
189
190#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
191#define HDA_RMX_OUTSTRMPAY 112
192
193#define HDA_REG_INSTRMPAY 10 /* 0x1a */
194#define HDA_RMX_INSTRMPAY 113
195
196#define HDA_REG_INTCTL 11 /* 0x20 */
197#define HDA_RMX_INTCTL 9
198#define HDA_INTCTL_GIE_SHIFT 31
199#define HDA_INTCTL_CIE_SHIFT 30
200#define HDA_INTCTL_S0_SHIFT 0
201#define HDA_INTCTL_S1_SHIFT 1
202#define HDA_INTCTL_S2_SHIFT 2
203#define HDA_INTCTL_S3_SHIFT 3
204#define HDA_INTCTL_S4_SHIFT 4
205#define HDA_INTCTL_S5_SHIFT 5
206#define HDA_INTCTL_S6_SHIFT 6
207#define HDA_INTCTL_S7_SHIFT 7
208#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
209#define HDA_INTCTL_GIE_MASK RT_BIT(31) /* Global Interrupt Enable (3.3.14). */
210
211#define HDA_REG_INTSTS 12 /* 0x24 */
212#define HDA_RMX_INTSTS 10
213#define HDA_INTSTS_GIS_SHIFT 31
214#define HDA_INTSTS_CIS_SHIFT 30
215#define HDA_INTSTS_S0_SHIFT 0
216#define HDA_INTSTS_S1_SHIFT 1
217#define HDA_INTSTS_S2_SHIFT 2
218#define HDA_INTSTS_S3_SHIFT 3
219#define HDA_INTSTS_S4_SHIFT 4
220#define HDA_INTSTS_S5_SHIFT 5
221#define HDA_INTSTS_S6_SHIFT 6
222#define HDA_INTSTS_S7_SHIFT 7
223#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
224
225#define HDA_REG_WALCLK 13 /* 0x30 */
226#define HDA_RMX_WALCLK /* Not defined! */
227
228/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
229 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
230 * the datasheet.
231 */
232#define HDA_REG_SSYNC 14 /* 0x38 */
233#define HDA_RMX_SSYNC 12
234
235#define HDA_REG_CORBLBASE 15 /* 0x40 */
236#define HDA_RMX_CORBLBASE 13
237
238#define HDA_REG_CORBUBASE 16 /* 0x44 */
239#define HDA_RMX_CORBUBASE 14
240
241#define HDA_REG_CORBWP 17 /* 0x48 */
242#define HDA_RMX_CORBWP 15
243
244#define HDA_REG_CORBRP 18 /* 0x4A */
245#define HDA_RMX_CORBRP 16
246#define HDA_CORBRP_RST_SHIFT 15
247#define HDA_CORBRP_WP_SHIFT 0
248#define HDA_CORBRP_WP_MASK 0xFF
249
250#define HDA_REG_CORBCTL 19 /* 0x4C */
251#define HDA_RMX_CORBCTL 17
252#define HDA_CORBCTL_DMA_SHIFT 1
253#define HDA_CORBCTL_CMEIE_SHIFT 0
254
255#define HDA_REG_CORBSTS 20 /* 0x4D */
256#define HDA_RMX_CORBSTS 18
257#define HDA_CORBSTS_CMEI_SHIFT 0
258
259#define HDA_REG_CORBSIZE 21 /* 0x4E */
260#define HDA_RMX_CORBSIZE 19
261#define HDA_CORBSIZE_SZ_CAP 0xF0
262#define HDA_CORBSIZE_SZ 0x3
263/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
264
265#define HDA_REG_RIRBLBASE 22 /* 0x50 */
266#define HDA_RMX_RIRBLBASE 20
267
268#define HDA_REG_RIRBUBASE 23 /* 0x54 */
269#define HDA_RMX_RIRBUBASE 21
270
271#define HDA_REG_RIRBWP 24 /* 0x58 */
272#define HDA_RMX_RIRBWP 22
273#define HDA_RIRBWP_RST_SHIFT 15
274#define HDA_RIRBWP_WP_MASK 0xFF
275
276#define HDA_REG_RINTCNT 25 /* 0x5A */
277#define HDA_RMX_RINTCNT 23
278#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
279
280#define HDA_REG_RIRBCTL 26 /* 0x5C */
281#define HDA_RMX_RIRBCTL 24
282#define HDA_RIRBCTL_RIC_SHIFT 0
283#define HDA_RIRBCTL_DMA_SHIFT 1
284#define HDA_ROI_DMA_SHIFT 2
285
286#define HDA_REG_RIRBSTS 27 /* 0x5D */
287#define HDA_RMX_RIRBSTS 25
288#define HDA_RIRBSTS_RINTFL_SHIFT 0
289#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
290
291#define HDA_REG_RIRBSIZE 28 /* 0x5E */
292#define HDA_RMX_RIRBSIZE 26
293#define HDA_RIRBSIZE_SZ_CAP 0xF0
294#define HDA_RIRBSIZE_SZ 0x3
295
296#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
297#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
298
299
300#define HDA_REG_IC 29 /* 0x60 */
301#define HDA_RMX_IC 27
302
303#define HDA_REG_IR 30 /* 0x64 */
304#define HDA_RMX_IR 28
305
306#define HDA_REG_IRS 31 /* 0x68 */
307#define HDA_RMX_IRS 29
308#define HDA_IRS_ICB_SHIFT 0
309#define HDA_IRS_IRV_SHIFT 1
310
311#define HDA_REG_DPLBASE 32 /* 0x70 */
312#define HDA_RMX_DPLBASE 30
313#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
314
315#define HDA_REG_DPUBASE 33 /* 0x74 */
316#define HDA_RMX_DPUBASE 31
317#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
318
319#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
320
321#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
322#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
323/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
324#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
325
326#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
327
328/** @todo Condense marcos! */
329
330#define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80 */
331#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
332#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
333#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
334#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
335#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
336#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
337#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
338#define HDA_RMX_SD0CTL 32
339#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
340#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
341#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
342#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
343#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
344#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
345#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
346
347#define SD(func, num) SD##num##func
348
349#define HDA_SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
350#define HDA_SDCTL_NUM(pThis, num) ((HDA_SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
351#define HDA_SDCTL_NUM_MASK 0xF
352#define HDA_SDCTL_NUM_SHIFT 20
353#define HDA_SDCTL_DIR_SHIFT 19
354#define HDA_SDCTL_TP_SHIFT 18
355#define HDA_SDCTL_STRIPE_MASK 0x3
356#define HDA_SDCTL_STRIPE_SHIFT 16
357#define HDA_SDCTL_DEIE_SHIFT 4
358#define HDA_SDCTL_FEIE_SHIFT 3
359#define HDA_SDCTL_ICE_SHIFT 2
360#define HDA_SDCTL_RUN_SHIFT 1
361#define HDA_SDCTL_SRST_SHIFT 0
362
363#define HDA_REG_SD0STS 35 /* 0x83 */
364#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
365#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
366#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
367#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
368#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
369#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
370#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
371#define HDA_RMX_SD0STS 33
372#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
373#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
374#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
375#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
376#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
377#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
378#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
379
380#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
381#define HDA_SDSTS_FIFORDY_SHIFT 5
382#define HDA_SDSTS_DE_SHIFT 4
383#define HDA_SDSTS_FE_SHIFT 3
384#define HDA_SDSTS_BCIS_SHIFT 2
385
386#define HDA_REG_SD0LPIB 36 /* 0x84 */
387#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
388#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
389#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
390#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
391#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
392#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
393#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
394#define HDA_RMX_SD0LPIB 34
395#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
396#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
397#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
398#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
399#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
400#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
401#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
402
403#define HDA_REG_SD0CBL 37 /* 0x88 */
404#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
405#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
406#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
407#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
408#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
409#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
410#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
411#define HDA_RMX_SD0CBL 35
412#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
413#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
414#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
415#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
416#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
417#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
418#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
419
420#define HDA_REG_SD0LVI 38 /* 0x8C */
421#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
422#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
423#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
424#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
425#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
426#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
427#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
428#define HDA_RMX_SD0LVI 36
429#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
430#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
431#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
432#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
433#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
434#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
435#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
436
437#define HDA_REG_SD0FIFOW 39 /* 0x8E */
438#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
439#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
440#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
441#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
442#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
443#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
444#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
445#define HDA_RMX_SD0FIFOW 37
446#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
447#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
448#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
449#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
450#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
451#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
452#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
453
454/*
455 * ICH6 datasheet defined limits for FIFOW values (18.2.38).
456 */
457#define HDA_SDFIFOW_8B 0x2
458#define HDA_SDFIFOW_16B 0x3
459#define HDA_SDFIFOW_32B 0x4
460
461#define HDA_REG_SD0FIFOS 40 /* 0x90 */
462#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
463#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
464#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
465#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
466#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
467#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
468#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
469#define HDA_RMX_SD0FIFOS 38
470#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
471#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
472#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
473#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
474#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
475#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
476#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
477
478/*
479 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
480 * formula: size - 1
481 * Other values not listed are not supported.
482 */
483/** Maximum FIFO size (in bytes). */
484#define HDA_FIFO_MAX 256
485
486#define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
487#define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
488
489#define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
490#define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
491#define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
492#define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
493#define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
494#define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
495#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
496
497#define HDA_REG_SD0FMT 41 /* 0x92 */
498#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
499#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
500#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
501#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
502#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
503#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
504#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
505#define HDA_RMX_SD0FMT 39
506#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
507#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
508#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
509#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
510#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
511#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
512#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
513
514#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
515#define HDA_SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
516#define HDA_SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
517#define HDA_SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
518
519#define HDA_REG_SD0BDPL 42 /* 0x98 */
520#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
521#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
522#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
523#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
524#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
525#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
526#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
527#define HDA_RMX_SD0BDPL 40
528#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
529#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
530#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
531#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
532#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
533#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
534#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
535
536#define HDA_REG_SD0BDPU 43 /* 0x9C */
537#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
538#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
539#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
540#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
541#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
542#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
543#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
544#define HDA_RMX_SD0BDPU 41
545#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
546#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
547#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
548#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
549#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
550#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
551#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
552
553#define HDA_BDLE_FLAG_IOC RT_BIT(0) /* Interrupt on completion (IOC). */
554
555#define HDA_CODEC_CAD_SHIFT 28
556/* Encodes the (required) LUN into a codec command. */
557#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
558
559
560
561/*********************************************************************************************************************************
562* Structures and Typedefs *
563*********************************************************************************************************************************/
564
565/**
566 * Internal state of a Buffer Descriptor List Entry (BDLE),
567 * needed to keep track of the data needed for the actual device
568 * emulation.
569 */
570typedef struct HDABDLESTATE
571{
572 /** Own index within the BDL (Buffer Descriptor List). */
573 uint32_t u32BDLIndex;
574 /** Number of bytes below the stream's FIFO watermark (SDFIFOW).
575 * Used to check if we need fill up the FIFO again. */
576 uint32_t cbBelowFIFOW;
577 /** Current offset in DMA buffer (in bytes).*/
578 uint32_t u32BufOff;
579 uint32_t Padding;
580} HDABDLESTATE, *PHDABDLESTATE;
581
582/**
583 * BDL description structure.
584 * Do not touch this, as this must match to the HDA specs.
585 */
586typedef struct HDABDLEDESC
587{
588 /** Starting address of the actual buffer. Must be 128-bit aligned. */
589 uint64_t u64BufAdr;
590 /** Size of the actual buffer (in bytes). */
591 uint32_t u32BufSize;
592 /** Bit 0: Interrupt on completion; the controller will generate
593 * an interrupt when the last byte of the buffer has been
594 * fetched by the DMA engine.
595 *
596 * Rest is reserved for further use and must be 0. */
597 uint32_t fFlags;
598} HDABDLEDESC, *PHDABDLEDESC;
599AssertCompileSize(HDABDLEDESC, 16); /* Always 16 byte. Also must be aligned on 128-byte boundary. */
600
601/**
602 * Buffer Descriptor List Entry (BDLE) (3.6.3).
603 */
604typedef struct HDABDLE
605{
606 /** The actual BDL description. */
607 HDABDLEDESC Desc;
608 /** Internal state of this BDLE.
609 * Not part of the actual BDLE registers. */
610 HDABDLESTATE State;
611} HDABDLE, *PHDABDLE;
612
613/**
614 * Structure for keeping an audio stream data mapping.
615 */
616typedef struct HDASTREAMMAPPING
617{
618 /** The stream's layout. */
619 PDMAUDIOSTREAMLAYOUT enmLayout;
620 /** Number of audio channels in this stream. */
621 uint8_t cChannels;
622 /** Array of audio channels. */
623 R3PTRTYPE(PPDMAUDIOSTREAMCHANNEL) paChannels;
624 /** Circular buffer holding for holding audio data for this mapping. */
625 R3PTRTYPE(PRTCIRCBUF) pCircBuf;
626} HDASTREAMMAPPING, *PHDASTREAMMAPPING;
627
628#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
629/**
630 * Structure keeping the HDA stream's state for asynchronous I/O.
631 */
632typedef struct HDASTREAMSTATEAIO
633{
634 /** Thread handle for the actual I/O thread. */
635 RTTHREAD Thread;
636 /** Event for letting the thread know there is some data to process. */
637 RTSEMEVENT Event;
638 /** Critical section for synchronizing access. */
639 RTCRITSECT CritSect;
640 /** Started indicator. */
641 volatile bool fStarted;
642 /** Shutdown indicator. */
643 volatile bool fShutdown;
644 uint32_t Padding1;
645} HDASTREAMSTATEAIO, *PHDASTREAMSTATEAIO;
646#endif
647
648/**
649 * Internal state of a HDA stream.
650 */
651typedef struct HDASTREAMSTATE
652{
653 /** Current BDLE to use. Wraps around to 0 if
654 * maximum (cBDLE) is reached. */
655 uint16_t uCurBDLE;
656 /** Flag indicating whether this stream currently is
657 * in reset mode and therefore not acccessible by the guest. */
658 volatile bool fInReset;
659 /** Unused, padding. */
660 uint32_t Padding0;
661 /** Critical section to serialize access. */
662 RTCRITSECT CritSect;
663#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
664 /** Asynchronous I/O state members. */
665 HDASTREAMSTATEAIO AIO;
666#endif
667 /** This stream's data mapping. */
668 HDASTREAMMAPPING Mapping;
669 /** Current BDLE (Buffer Descriptor List Entry). */
670 HDABDLE BDLE;
671 /** Circular buffer (FIFO) for holding DMA'ed data. */
672 R3PTRTYPE(PRTCIRCBUF) pCircBuf;
673} HDASTREAMSTATE, *PHDASTREAMSTATE;
674
675/**
676 * Structure defining an HDA mixer sink.
677 * Its purpose is to know which audio mixer sink is bound to
678 * which SDn (SDI/SDO) device stream.
679 *
680 * This is needed in order to handle interleaved streams
681 * (that is, multiple channels in one stream) or non-interleaved
682 * streams (each channel has a dedicated stream).
683 *
684 * This is only known to the actual device emulation level.
685 */
686typedef struct HDAMIXERSINK
687{
688 /** SDn ID this sink is assigned to. 0 if not assigned. */
689 uint8_t uSD;
690 /** Channel ID of SDn ID. Only valid if SDn ID is valid. */
691 uint8_t uChannel;
692 uint8_t Padding[3];
693 /** Pointer to the actual audio mixer sink. */
694 R3PTRTYPE(PAUDMIXSINK) pMixSink;
695} HDAMIXERSINK, *PHDAMIXERSINK;
696
697/**
698 * Structure for keeping a HDA stream (SDI / SDO).
699 *
700 * Note: This HDA stream has nothing to do with a regular audio stream handled
701 * by the audio connector or the audio mixer. This HDA stream is a serial data in/out
702 * stream (SDI/SDO) defined in hardware and can contain multiple audio streams
703 * in one single SDI/SDO (interleaving streams).
704 *
705 * How a specific SDI/SDO is mapped to our internal audio streams relies on the
706 * stream channel mappings.
707 *
708 * Contains only register values which do *not* change until a
709 * stream reset occurs.
710 */
711typedef struct HDASTREAM
712{
713 /** Stream descriptor number (SDn). */
714 uint8_t u8SD;
715 uint8_t Padding0[7];
716 /** DMA base address (SDnBDPU - SDnBDPL). */
717 uint64_t u64BDLBase;
718 /** Cyclic Buffer Length (SDnCBL).
719 * Represents the size of the ring buffer. */
720 uint32_t u32CBL;
721 /** Format (SDnFMT). */
722 uint16_t u16FMT;
723 /** FIFO Size (FIFOS).
724 * Maximum number of bytes that may have been DMA'd into
725 * memory but not yet transmitted on the link. */
726 uint16_t u16FIFOS;
727 /** FIFO Watermark. */
728 uint16_t u16FIFOW;
729 /** Last Valid Index (SDnLVI). */
730 uint16_t u16LVI;
731 uint16_t Padding1[2];
732 /** Pointer to HDA sink this stream is attached to. */
733 R3PTRTYPE(PHDAMIXERSINK) pMixSink;
734 /** Internal state of this stream. */
735 HDASTREAMSTATE State;
736} HDASTREAM, *PHDASTREAM;
737
738#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
739/**
740 * Structure for keeping a HDA stream thread context.
741 */
742typedef struct HDASTREAMTHREADCTX
743{
744 PHDASTATE pThis;
745 PHDASTREAM pStream;
746} HDASTREAMTHREADCTX, *PHDASTREAMTHREADCTX;
747#endif
748
749/**
750 * Structure for mapping a stream tag to an HDA stream.
751 */
752typedef struct HDATAG
753{
754 /** Own stream tag. */
755 uint8_t uTag;
756 uint8_t Padding[7];
757 /** Pointer to associated stream. */
758 R3PTRTYPE(PHDASTREAM) pStrm;
759} HDATAG, *PHDATAG;
760
761/**
762 * Structure defining a (host backend) driver stream.
763 * Each driver has its own instances of audio mixer streams, which then
764 * can go into the same (or even different) audio mixer sinks.
765 */
766typedef struct HDADRIVERSTREAM
767{
768 union
769 {
770 /** Desired playback destination (for an output stream). */
771 PDMAUDIOPLAYBACKDEST Dest;
772 /** Desired recording source (for an input stream). */
773 PDMAUDIORECSOURCE Source;
774 } DestSource;
775 uint8_t Padding1[4];
776 /** Associated mixer handle. */
777 R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
778} HDADRIVERSTREAM, *PHDADRIVERSTREAM;
779
780/**
781 * Struct for maintaining a host backend driver.
782 * This driver must be associated to one, and only one,
783 * HDA codec. The HDA controller does the actual multiplexing
784 * of HDA codec data to various host backend drivers then.
785 *
786 * This HDA device uses a timer in order to synchronize all
787 * read/write accesses across all attached LUNs / backends.
788 */
789typedef struct HDADRIVER
790{
791 /** Node for storing this driver in our device driver list of HDASTATE. */
792 RTLISTNODER3 Node;
793 /** Pointer to HDA controller (state). */
794 R3PTRTYPE(PHDASTATE) pHDAState;
795 /** Driver flags. */
796 PDMAUDIODRVFLAGS Flags;
797 uint8_t u32Padding0[2];
798 /** LUN to which this driver has been assigned. */
799 uint8_t uLUN;
800 /** Whether this driver is in an attached state or not. */
801 bool fAttached;
802 /** Pointer to attached driver base interface. */
803 R3PTRTYPE(PPDMIBASE) pDrvBase;
804 /** Audio connector interface to the underlying host backend. */
805 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
806 /** Mixer stream for line input. */
807 HDADRIVERSTREAM LineIn;
808#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
809 /** Mixer stream for mic input. */
810 HDADRIVERSTREAM MicIn;
811#endif
812 /** Mixer stream for front output. */
813 HDADRIVERSTREAM Front;
814#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
815 /** Mixer stream for center/LFE output. */
816 HDADRIVERSTREAM CenterLFE;
817 /** Mixer stream for rear output. */
818 HDADRIVERSTREAM Rear;
819#endif
820} HDADRIVER;
821
822/**
823 * ICH Intel HD Audio Controller state.
824 */
825typedef struct HDASTATE
826{
827 /** The PCI device structure. */
828 PDMPCIDEV PciDev;
829 /** R3 Pointer to the device instance. */
830 PPDMDEVINSR3 pDevInsR3;
831 /** R0 Pointer to the device instance. */
832 PPDMDEVINSR0 pDevInsR0;
833 /** R0 Pointer to the device instance. */
834 PPDMDEVINSRC pDevInsRC;
835 /** Padding for alignment. */
836 uint32_t u32Padding;
837 /** The base interface for LUN\#0. */
838 PDMIBASE IBase;
839 RTGCPHYS MMIOBaseAddr;
840 /** The HDA's register set. */
841 uint32_t au32Regs[HDA_NUM_REGS];
842 /** Internal stream states. */
843 HDASTREAM aStreams[HDA_MAX_STREAMS];
844 /** Mapping table between stream tags and stream states. */
845 HDATAG aTags[HDA_MAX_TAGS];
846 /** CORB buffer base address. */
847 uint64_t u64CORBBase;
848 /** RIRB buffer base address. */
849 uint64_t u64RIRBBase;
850 /** DMA base address.
851 * Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
852 uint64_t u64DPBase;
853 /** DMA position buffer enable bit. */
854 bool fDMAPosition;
855 /** Padding for alignment. */
856 uint8_t u8Padding0[7];
857 /** Pointer to CORB buffer. */
858 R3PTRTYPE(uint32_t *) pu32CorbBuf;
859 /** Size in bytes of CORB buffer. */
860 uint32_t cbCorbBuf;
861 /** Padding for alignment. */
862 uint32_t u32Padding1;
863 /** Pointer to RIRB buffer. */
864 R3PTRTYPE(uint64_t *) pu64RirbBuf;
865 /** Size in bytes of RIRB buffer. */
866 uint32_t cbRirbBuf;
867 /** Indicates if HDA controller is in reset mode. */
868 bool fInReset;
869 /** Flag whether the R0 part is enabled. */
870 bool fR0Enabled;
871 /** Flag whether the RC part is enabled. */
872 bool fRCEnabled;
873 /** Number of active (running) SDn streams. */
874 uint8_t cStreamsActive;
875#ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
876 /** The timer for pumping data thru the attached LUN drivers. */
877 PTMTIMERR3 pTimer;
878 /** Flag indicating whether the timer is active or not. */
879 bool fTimerActive;
880 uint8_t u8Padding1[7];
881 /** Timer ticks per Hz. */
882 uint64_t cTimerTicks;
883 /** Timestamp of the last timer callback (hdaTimer).
884 * Used to calculate the time actually elapsed between two timer callbacks. */
885 uint64_t uTimerTS;
886 uint64_t uTimerMS;
887#endif
888#ifdef VBOX_WITH_STATISTICS
889# ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
890 STAMPROFILE StatTimer;
891# endif
892 STAMPROFILE StatIn;
893 STAMPROFILE StatOut;
894 STAMCOUNTER StatBytesRead;
895 STAMCOUNTER StatBytesWritten;
896#endif
897 /** Pointer to HDA codec to use. */
898 R3PTRTYPE(PHDACODEC) pCodec;
899 /** List of associated LUN drivers (HDADRIVER). */
900 RTLISTANCHORR3 lstDrv;
901 /** The device' software mixer. */
902 R3PTRTYPE(PAUDIOMIXER) pMixer;
903 /** HDA sink for (front) output. */
904 HDAMIXERSINK SinkFront;
905#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
906 /** HDA sink for center / LFE output. */
907 HDAMIXERSINK SinkCenterLFE;
908 /** HDA sink for rear output. */
909 HDAMIXERSINK SinkRear;
910#endif
911 /** HDA mixer sink for line input. */
912 HDAMIXERSINK SinkLineIn;
913#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
914 /** Audio mixer sink for microphone input. */
915 HDAMIXERSINK SinkMicIn;
916#endif
917 uint64_t u64BaseTS;
918 /** Response Interrupt Count (RINTCNT). */
919 uint8_t u8RespIntCnt;
920 /** Padding for alignment. */
921 uint8_t au8Padding2[7];
922} HDASTATE;
923/** Pointer to the ICH Intel HD Audio Controller state. */
924typedef HDASTATE *PHDASTATE;
925
926#ifdef VBOX_WITH_AUDIO_HDA_CALLBACKS
927typedef struct HDACALLBACKCTX
928{
929 PHDASTATE pThis;
930 PHDADRIVER pDriver;
931} HDACALLBACKCTX, *PHDACALLBACKCTX;
932#endif
933
934
935/*********************************************************************************************************************************
936* Internal Functions *
937*********************************************************************************************************************************/
938#ifndef VBOX_DEVICE_STRUCT_TESTCASE
939#ifdef IN_RING3
940static FNPDMDEVRESET hdaReset;
941#endif
942
943/** @name Register read/write stubs.
944 * @{
945 */
946static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
947static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
948/** @} */
949
950/** @name Global register set read/write functions.
951 * @{
952 */
953static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
954static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
955static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
956static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
957static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
958static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
959static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
960static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
961static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
962static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
963static int hdaRegWriteINTCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
964static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
965static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
966static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
967/** @} */
968
969/** @name {IOB}SDn write functions.
970 * @{
971 */
972static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
973static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
974static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
975static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
976static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
977static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
978static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
979static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
980static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
981/** @} */
982
983/* Locking + logging. */
984#ifdef IN_RING3
985DECLINLINE(int) hdaRegWriteSDLock(PHDASTATE pThis, PHDASTREAM pStream, uint32_t iReg, uint32_t u32Value);
986DECLINLINE(void) hdaRegWriteSDUnlock(PHDASTREAM pStream);
987#endif
988
989/** @name Generic register read/write functions.
990 * @{
991 */
992static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
993static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
994static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
995#ifdef IN_RING3
996static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
997#endif
998static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
999static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
1000static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
1001static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
1002/** @} */
1003
1004/** @name Stream functions.
1005 * @{
1006 */
1007#ifdef IN_RING3
1008static void hdaStreamDestroy(PHDASTATE pThis, PHDASTREAM pStream);
1009static int hdaStreamDoDMA(PHDASTATE pThis, PHDASTREAM pStream, void *pvBuf, uint32_t cbBuf, uint32_t cbToProcess, uint32_t *pcbProcessed);
1010static int hdaStreamEnable(PHDASTATE pThis, PHDASTREAM pStream, bool fEnable);
1011static int hdaStreamUpdate(PHDASTATE pThis, PHDASTREAM pStream);
1012DECLINLINE(uint32_t) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStream, uint32_t u32LPIB);
1013#endif /* IN_RING3 */
1014/** @} */
1015
1016/** @name Async I/O stream functions.
1017 * @{
1018 */
1019#ifdef IN_RING3
1020# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1021static DECLCALLBACK(int) hdaStreamAsyncIOThread(RTTHREAD hThreadSelf, void *pvUser);
1022static int hdaStreamAsyncIONotify(PHDASTATE pThis, PHDASTREAM pStream);
1023static void hdaStreamAsyncIOLock(PHDASTREAM pStream);
1024static void hdaStreamAsyncIOUnlock(PHDASTREAM pStream);
1025# endif
1026#endif
1027/** @} */
1028
1029/** @name Stream mapping functions.
1030 * @{
1031 */
1032#ifdef IN_RING3
1033static int hdaStreamMapInit(PHDASTREAMMAPPING pMapping, PPDMAUDIOSTREAMCFG pCfg);
1034static void hdaStreamMapDestroy(PHDASTREAMMAPPING pMapping);
1035static void hdaStreamMapReset(PHDASTREAMMAPPING pMapping);
1036#endif /* IN_RING3 */
1037/** @} */
1038
1039/** @name HDA device functions.
1040 * @{
1041 */
1042#ifdef IN_RING3
1043static void hdaDoTransfers(PHDASTATE pThis);
1044#endif /* IN_RING3 */
1045static int hdaProcessInterrupt(PHDASTATE pThis);
1046/** @} */
1047
1048/** @name BDLE (Buffer Descriptor List Entry) functions.
1049 * @{
1050 */
1051#ifdef IN_RING3
1052static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry);
1053# ifdef LOG_ENABLED
1054static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BaseDMA, uint16_t cBDLE);
1055# endif
1056#endif /* IN_RING3 */
1057/** @} */
1058
1059/** @name Timer functions.
1060 * @{
1061 */
1062#if !defined(VBOX_WITH_AUDIO_HDA_CALLBACKS) && defined(IN_RING3)
1063static void hdaTimerMaybeStart(PHDASTATE pThis);
1064static void hdaTimerMaybeStop(PHDASTATE pThis);
1065#endif
1066/** @} */
1067
1068
1069/*********************************************************************************************************************************
1070* Global Variables *
1071*********************************************************************************************************************************/
1072
1073/** Offset of the SD0 register map. */
1074#define HDA_REG_DESC_SD0_BASE 0x80
1075
1076/** Turn a short global register name into an memory index and a stringized name. */
1077#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
1078
1079/** Turns a short stream register name into an memory index and a stringized name. */
1080#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
1081
1082/** Same as above for a register *not* stored in memory. */
1083#define HDA_REG_IDX_LOCAL(abbrev) 0, #abbrev
1084
1085/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
1086#define HDA_REG_MAP_STRM(offset, name) \
1087 /* offset size read mask write mask read callback write callback index + abbrev description */ \
1088 /* ------- ------- ---------- ---------- -------------- ----------------- ------------------------------ ----------- */ \
1089 /* Offset 0x80 (SD0) */ \
1090 { offset, 0x00003, 0x00FF001F, 0x00F0001F, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL) , #name " Stream Descriptor Control" }, \
1091 /* Offset 0x83 (SD0) */ \
1092 { offset + 0x3, 0x00001, 0x0000003C, 0x0000001C, hdaRegReadU8 , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS) , #name " Status" }, \
1093 /* Offset 0x84 (SD0) */ \
1094 { offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadLPIB, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
1095 /* Offset 0x88 (SD0) */ \
1096 { offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteSDCBL , HDA_REG_IDX_STRM(name, CBL) , #name " Cyclic Buffer Length" }, \
1097 /* Offset 0x8C (SD0) */ \
1098 { offset + 0xC, 0x00002, 0x0000FFFF, 0x0000FFFF, hdaRegReadU16, hdaRegWriteSDLVI , HDA_REG_IDX_STRM(name, LVI) , #name " Last Valid Index" }, \
1099 /* Reserved: FIFO Watermark. ** @todo Document this! */ \
1100 { offset + 0xE, 0x00002, 0x00000007, 0x00000007, hdaRegReadU16, hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
1101 /* Offset 0x90 (SD0) */ \
1102 { offset + 0x10, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16, hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
1103 /* Offset 0x92 (SD0) */ \
1104 { offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, hdaRegReadU16, hdaRegWriteSDFMT , HDA_REG_IDX_STRM(name, FMT) , #name " Stream Format" }, \
1105 /* Reserved: 0x94 - 0x98. */ \
1106 /* Offset 0x98 (SD0) */ \
1107 { offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32, hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
1108 /* Offset 0x9C (SD0) */ \
1109 { offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32, hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
1110
1111/** Defines a single audio stream register set (e.g. OSD0). */
1112#define HDA_REG_MAP_DEF_STREAM(index, name) \
1113 HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
1114
1115/* See 302349 p 6.2. */
1116static const struct HDAREGDESC
1117{
1118 /** Register offset in the register space. */
1119 uint32_t offset;
1120 /** Size in bytes. Registers of size > 4 are in fact tables. */
1121 uint32_t size;
1122 /** Readable bits. */
1123 uint32_t readable;
1124 /** Writable bits. */
1125 uint32_t writable;
1126 /** Read callback. */
1127 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
1128 /** Write callback. */
1129 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
1130 /** Index into the register storage array. */
1131 uint32_t mem_idx;
1132 /** Abbreviated name. */
1133 const char *abbrev;
1134 /** Descripton. */
1135 const char *desc;
1136} g_aHdaRegMap[HDA_NUM_REGS] =
1137
1138{
1139 /* offset size read mask write mask read callback write callback index + abbrev */
1140 /*------- ------- ---------- ---------- ----------------------- ---------------------- ---------------- */
1141 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(GCAP) }, /* Global Capabilities */
1142 { 0x00002, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMIN) }, /* Minor Version */
1143 { 0x00003, 0x00001, 0x000000FF, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMAJ) }, /* Major Version */
1144 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTPAY) }, /* Output Payload Capabilities */
1145 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INPAY) }, /* Input Payload Capabilities */
1146 { 0x00008, 0x00004, 0x00000103, 0x00000103, hdaRegReadU32 , hdaRegWriteGCTL , HDA_REG_IDX(GCTL) }, /* Global Control */
1147 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(WAKEEN) }, /* Wake Enable */
1148 { 0x0000e, 0x00002, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteSTATESTS , HDA_REG_IDX(STATESTS) }, /* State Change Status */
1149 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, hdaRegReadUnimpl , hdaRegWriteUnimpl , HDA_REG_IDX(GSTS) }, /* Global Status */
1150 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTSTRMPAY) }, /* Output Stream Payload Capability */
1151 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INSTRMPAY) }, /* Input Stream Payload Capability */
1152 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, hdaRegReadU32 , hdaRegWriteINTCTL , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */
1153 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */
1154 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, hdaRegReadWALCLK , hdaRegWriteUnimpl , HDA_REG_IDX_LOCAL(WALCLK) }, /* Wall Clock Counter */
1155 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */
1156 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
1157 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBUBASE) }, /* CORB Upper Base Address */
1158 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteCORBWP , HDA_REG_IDX(CORBWP) }, /* CORB Write Pointer */
1159 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, hdaRegReadU16 , hdaRegWriteCORBRP , HDA_REG_IDX(CORBRP) }, /* CORB Read Pointer */
1160 { 0x0004C, 0x00001, 0x00000003, 0x00000003, hdaRegReadU8 , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL) }, /* CORB Control */
1161 { 0x0004D, 0x00001, 0x00000001, 0x00000001, hdaRegReadU8 , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS) }, /* CORB Status */
1162 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(CORBSIZE) }, /* CORB Size */
1163 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBLBASE) }, /* RIRB Lower Base Address */
1164 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBUBASE) }, /* RIRB Upper Base Address */
1165 { 0x00058, 0x00002, 0x000000FF, 0x00008000, hdaRegReadU8 , hdaRegWriteRIRBWP , HDA_REG_IDX(RIRBWP) }, /* RIRB Write Pointer */
1166 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(RINTCNT) }, /* Response Interrupt Count */
1167 { 0x0005C, 0x00001, 0x00000007, 0x00000007, hdaRegReadU8 , hdaRegWriteU8 , HDA_REG_IDX(RIRBCTL) }, /* RIRB Control */
1168 { 0x0005D, 0x00001, 0x00000005, 0x00000005, hdaRegReadU8 , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS) }, /* RIRB Status */
1169 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(RIRBSIZE) }, /* RIRB Size */
1170 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(IC) }, /* Immediate Command */
1171 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(IR) }, /* Immediate Response */
1172 { 0x00068, 0x00002, 0x00000002, 0x00000002, hdaRegReadIRS , hdaRegWriteIRS , HDA_REG_IDX(IRS) }, /* Immediate Command Status */
1173 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPLBASE) }, /* DMA Position Lower Base */
1174 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPUBASE) }, /* DMA Position Upper Base */
1175 /* 4 Serial Data In (SDI). */
1176 HDA_REG_MAP_DEF_STREAM(0, SD0),
1177 HDA_REG_MAP_DEF_STREAM(1, SD1),
1178 HDA_REG_MAP_DEF_STREAM(2, SD2),
1179 HDA_REG_MAP_DEF_STREAM(3, SD3),
1180 /* 4 Serial Data Out (SDO). */
1181 HDA_REG_MAP_DEF_STREAM(4, SD4),
1182 HDA_REG_MAP_DEF_STREAM(5, SD5),
1183 HDA_REG_MAP_DEF_STREAM(6, SD6),
1184 HDA_REG_MAP_DEF_STREAM(7, SD7)
1185};
1186
1187/**
1188 * HDA register aliases (HDA spec 3.3.45).
1189 * @remarks Sorted by offReg.
1190 */
1191static const struct
1192{
1193 /** The alias register offset. */
1194 uint32_t offReg;
1195 /** The register index. */
1196 int idxAlias;
1197} g_aHdaRegAliases[] =
1198{
1199 { 0x2084, HDA_REG_SD0LPIB },
1200 { 0x20a4, HDA_REG_SD1LPIB },
1201 { 0x20c4, HDA_REG_SD2LPIB },
1202 { 0x20e4, HDA_REG_SD3LPIB },
1203 { 0x2104, HDA_REG_SD4LPIB },
1204 { 0x2124, HDA_REG_SD5LPIB },
1205 { 0x2144, HDA_REG_SD6LPIB },
1206 { 0x2164, HDA_REG_SD7LPIB },
1207};
1208
1209#ifdef IN_RING3
1210/** HDABDLEDESC field descriptors for the v6+ saved state. */
1211static SSMFIELD const g_aSSMBDLEDescFields6[] =
1212{
1213 SSMFIELD_ENTRY(HDABDLEDESC, u64BufAdr),
1214 SSMFIELD_ENTRY(HDABDLEDESC, u32BufSize),
1215 SSMFIELD_ENTRY(HDABDLEDESC, fFlags),
1216 SSMFIELD_ENTRY_TERM()
1217};
1218
1219/** HDABDLESTATE field descriptors for the v6+ saved state. */
1220static SSMFIELD const g_aSSMBDLEStateFields6[] =
1221{
1222 SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
1223 SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
1224 SSMFIELD_ENTRY_OLD(FIFO, 256),
1225 SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
1226 SSMFIELD_ENTRY_TERM()
1227};
1228
1229/** HDASTREAMSTATE field descriptors for the v6+ saved state. */
1230static SSMFIELD const g_aSSMStreamStateFields6[] =
1231{
1232 SSMFIELD_ENTRY_OLD(cBDLE, 2),
1233 SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
1234 SSMFIELD_ENTRY_OLD(fDoStop, 1),
1235 SSMFIELD_ENTRY_OLD(fActive, 1),
1236 SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
1237 SSMFIELD_ENTRY_TERM()
1238};
1239#endif
1240
1241/**
1242 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
1243 */
1244static uint32_t const g_afMasks[5] =
1245{
1246 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
1247};
1248
1249
1250#ifdef IN_RING3
1251/**
1252 * Retrieves the number of bytes of a FIFOW register.
1253 *
1254 * @return Number of bytes of a given FIFOW register.
1255 */
1256DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
1257{
1258 uint32_t cb;
1259 switch (u32RegFIFOW)
1260 {
1261 case HDA_SDFIFOW_8B: cb = 8; break;
1262 case HDA_SDFIFOW_16B: cb = 16; break;
1263 case HDA_SDFIFOW_32B: cb = 32; break;
1264 default: cb = 0; break;
1265 }
1266
1267 Assert(RT_IS_POWER_OF_TWO(cb));
1268 return cb;
1269}
1270
1271
1272DECLINLINE(uint32_t) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStream, uint32_t u32LPIB)
1273{
1274 AssertPtrReturn(pThis, 0);
1275 AssertPtrReturn(pStream, 0);
1276
1277 AssertMsg(u32LPIB <= pStream->u32CBL,
1278 ("[SD%RU8] New LPIB (%RU32) exceeds CBL (%RU32)\n", pStream->u8SD, u32LPIB, pStream->u32CBL));
1279
1280 u32LPIB = RT_MIN(u32LPIB, pStream->u32CBL);
1281
1282 LogFlowFunc(("[SD%RU8]: LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n",
1283 pStream->u8SD, u32LPIB, pThis->fDMAPosition));
1284
1285 /* Update LPIB in any case. */
1286 HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) = u32LPIB;
1287
1288 /* Do we need to tell the current DMA position? */
1289 if (pThis->fDMAPosition)
1290 {
1291 int rc2 = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
1292 (pThis->u64DPBase & DPBASE_ADDR_MASK) + (pStream->u8SD * 2 * sizeof(uint32_t)),
1293 (void *)&u32LPIB, sizeof(uint32_t));
1294 AssertRC(rc2);
1295 }
1296
1297 return u32LPIB;
1298}
1299
1300
1301/**
1302 * Fetches the next BDLE to use for a stream.
1303 *
1304 * @return IPRT status code.
1305 */
1306DECLINLINE(int) hdaStreamGetNextBDLE(PHDASTATE pThis, PHDASTREAM pStream, bool *pfWrapAround)
1307{
1308 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1309 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1310
1311 NOREF(pThis);
1312
1313 Assert(pStream->State.uCurBDLE < pStream->u16LVI + 1);
1314
1315 LogFlowFuncEnter();
1316
1317# ifdef LOG_ENABLED
1318 uint32_t const uOldBDLE = pStream->State.uCurBDLE;
1319# endif
1320
1321 PHDABDLE pBDLE = &pStream->State.BDLE;
1322 bool fWrapAround = false;
1323
1324 AssertMsg(pBDLE->State.u32BufOff == pBDLE->Desc.u32BufSize, ("BDLE not finished yet: %R[bdle]\n", pBDLE));
1325
1326 /*
1327 * Switch to the next BDLE entry and do a wrap around
1328 * if we reached the end of the Buffer Descriptor List (BDL).
1329 */
1330 pStream->State.uCurBDLE++;
1331 if (pStream->State.uCurBDLE == pStream->u16LVI + 1)
1332 {
1333 pStream->State.uCurBDLE = 0;
1334 fWrapAround = true;
1335 }
1336
1337 Assert(pStream->State.uCurBDLE < pStream->u16LVI + 1);
1338
1339 /* Fetch the next BDLE entry. */
1340 int rc = hdaBDLEFetch(pThis, pBDLE, pStream->u64BDLBase, pStream->State.uCurBDLE);
1341 if (RT_SUCCESS(rc))
1342 {
1343 LogFlowFunc(("[SD%RU8]: uOldBDLE=%RU16, uCurBDLE=%RU16, LVI=%RU32, rc=%Rrc, %R[bdle]\n",
1344 pStream->u8SD, uOldBDLE, pStream->State.uCurBDLE, pStream->u16LVI, rc, pBDLE));
1345
1346 if (pfWrapAround)
1347 *pfWrapAround = fWrapAround;
1348 }
1349
1350 return rc;
1351}
1352
1353
1354/**
1355 * Returns the HDA stream of specified stream descriptor number.
1356 *
1357 * @return Pointer to HDA stream, or NULL if none found.
1358 */
1359DECLINLINE(PHDASTREAM) hdaStreamFromSD(PHDASTATE pThis, uint8_t uSD)
1360{
1361 AssertPtrReturn(pThis, NULL);
1362 AssertReturn(uSD <= HDA_MAX_STREAMS, NULL);
1363
1364 if (uSD >= HDA_MAX_STREAMS)
1365 return NULL;
1366
1367 return &pThis->aStreams[uSD];
1368}
1369
1370
1371/**
1372 * Returns the HDA stream of specified HDA sink.
1373 *
1374 * @return Pointer to HDA stream, or NULL if none found.
1375 */
1376DECLINLINE(PHDASTREAM) hdaSinkGetStream(PHDASTATE pThis, PHDAMIXERSINK pSink)
1377{
1378 AssertPtrReturn(pThis, NULL);
1379 AssertPtrReturn(pSink, NULL);
1380
1381 /** @todo Do something with the channel mapping here? */
1382 return hdaStreamFromSD(pThis, pSink->uSD);
1383}
1384
1385
1386/**
1387 * Returns the audio direction of a specified stream descriptor.
1388 *
1389 * The register layout specifies that input streams (SDI) come first,
1390 * followed by the output streams (SDO). So every stream ID below HDA_MAX_SDI
1391 * is an input stream, whereas everything >= HDA_MAX_SDI is an output stream.
1392 *
1393 * Note: SDnFMT register does not provide that information, so we have to judge
1394 * for ourselves.
1395 *
1396 * @return Audio direction.
1397 */
1398DECLINLINE(PDMAUDIODIR) hdaGetDirFromSD(uint8_t uSD)
1399{
1400 AssertReturn(uSD <= HDA_MAX_STREAMS, PDMAUDIODIR_UNKNOWN);
1401
1402 if (uSD < HDA_MAX_SDI)
1403 return PDMAUDIODIR_IN;
1404
1405 return PDMAUDIODIR_OUT;
1406}
1407#endif /* IN_RING3 */
1408
1409
1410static void hdaUpdateINTSTS(PHDASTATE pThis)
1411{
1412 uint32_t intSts = 0;
1413
1414 if (/* Response Overrun Interrupt Status (ROIS) */
1415 HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1416 /* Response Interrupt */
1417 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1418 /* SDIN State Change Status Flags (SCSF) */
1419 || (HDA_REG(pThis, STATESTS) & HDA_STATESTS_SCSF_MASK))
1420 {
1421 intSts |= RT_BIT(30); /* Touch Controller Interrupt Status (CIS). */
1422 }
1423
1424#define HDA_MARK_STREAM(x) \
1425 if ( (INTCTL_SX(pThis, x)) \
1426 && ( (SDSTS(pThis, x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1427 || (SDSTS(pThis, x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1428 || (SDSTS(pThis, x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)) \
1429 ) \
1430 ) \
1431 { \
1432 Log3Func(("[SD%RU8] Marked\n", x)); \
1433 intSts |= RT_BIT(x); \
1434 }
1435
1436 HDA_MARK_STREAM(0);
1437 HDA_MARK_STREAM(1);
1438 HDA_MARK_STREAM(2);
1439 HDA_MARK_STREAM(3);
1440 HDA_MARK_STREAM(4);
1441 HDA_MARK_STREAM(5);
1442 HDA_MARK_STREAM(6);
1443 HDA_MARK_STREAM(7);
1444
1445#undef HDA_MARK_STREAM
1446
1447 if (intSts)
1448 intSts |= RT_BIT(31); /* Touch Global Interrupt Status (GIS). */
1449
1450 HDA_REG(pThis, INTSTS) = intSts;
1451
1452 Log3Func(("INTSTS=%x\n", intSts));
1453}
1454
1455static int hdaProcessInterrupt(PHDASTATE pThis)
1456{
1457 hdaUpdateINTSTS(pThis);
1458
1459 int iLevel = 0;
1460
1461 /* Global Interrupt Status (GIS) touched? */
1462 if (HDA_REG_FLAG_VALUE(pThis, INTSTS, GIS))
1463 iLevel = 1;
1464
1465 Log3Func(("INTCTL=%x, INTSTS=%x, Level=%d\n", HDA_REG(pThis, INTCTL), HDA_REG(pThis, INTSTS), iLevel));
1466
1467 /* Global Interrupt Enable (GIE) set? */
1468 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1469 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, iLevel);
1470
1471 return VINF_SUCCESS;
1472}
1473
1474/**
1475 * Looks up a register at the exact offset given by @a offReg.
1476 *
1477 * @returns Register index on success, -1 if not found.
1478 * @param offReg The register offset.
1479 */
1480static int hdaRegLookup(uint32_t offReg)
1481{
1482 /*
1483 * Aliases.
1484 */
1485 if (offReg >= g_aHdaRegAliases[0].offReg)
1486 {
1487 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1488 if (offReg == g_aHdaRegAliases[i].offReg)
1489 return g_aHdaRegAliases[i].idxAlias;
1490 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1491 return -1;
1492 }
1493
1494 /*
1495 * Binary search the
1496 */
1497 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1498 int idxLow = 0;
1499 for (;;)
1500 {
1501 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1502 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1503 {
1504 if (idxLow == idxMiddle)
1505 break;
1506 idxEnd = idxMiddle;
1507 }
1508 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1509 {
1510 idxLow = idxMiddle + 1;
1511 if (idxLow >= idxEnd)
1512 break;
1513 }
1514 else
1515 return idxMiddle;
1516 }
1517
1518#ifdef RT_STRICT
1519 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1520 Assert(g_aHdaRegMap[i].offset != offReg);
1521#endif
1522 return -1;
1523}
1524
1525/**
1526 * Looks up a register covering the offset given by @a offReg.
1527 *
1528 * @returns Register index on success, -1 if not found.
1529 * @param offReg The register offset.
1530 */
1531static int hdaRegLookupWithin(uint32_t offReg)
1532{
1533 /*
1534 * Aliases.
1535 */
1536 if (offReg >= g_aHdaRegAliases[0].offReg)
1537 {
1538 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1539 {
1540 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1541 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1542 return g_aHdaRegAliases[i].idxAlias;
1543 }
1544 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1545 return -1;
1546 }
1547
1548 /*
1549 * Binary search the register map.
1550 */
1551 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1552 int idxLow = 0;
1553 for (;;)
1554 {
1555 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1556 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1557 {
1558 if (idxLow == idxMiddle)
1559 break;
1560 idxEnd = idxMiddle;
1561 }
1562 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1563 {
1564 idxLow = idxMiddle + 1;
1565 if (idxLow >= idxEnd)
1566 break;
1567 }
1568 else
1569 return idxMiddle;
1570 }
1571
1572#ifdef RT_STRICT
1573 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1574 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1575#endif
1576 return -1;
1577}
1578
1579#ifdef IN_RING3
1580
1581static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1582{
1583 int rc = VINF_SUCCESS;
1584 if (fLocal)
1585 {
1586 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1587 Assert(pThis->u64CORBBase);
1588 AssertPtr(pThis->pu32CorbBuf);
1589 Assert(pThis->cbCorbBuf);
1590
1591 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1592 if (RT_FAILURE(rc))
1593 AssertRCReturn(rc, rc);
1594# ifdef DEBUG_CMD_BUFFER
1595 uint8_t i = 0;
1596 do
1597 {
1598 LogFunc(("CORB%02x: ", i));
1599 uint8_t j = 0;
1600 do
1601 {
1602 const char *pszPrefix;
1603 if ((i + j) == HDA_REG(pThis, CORBRP));
1604 pszPrefix = "[R]";
1605 else if ((i + j) == HDA_REG(pThis, CORBWP));
1606 pszPrefix = "[W]";
1607 else
1608 pszPrefix = " "; /* three spaces */
1609 LogFunc(("%s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
1610 j++;
1611 } while (j < 8);
1612 LogFunc(("\n"));
1613 i += 8;
1614 } while(i != 0);
1615# endif
1616 }
1617 else
1618 {
1619 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1620 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1621 if (RT_FAILURE(rc))
1622 AssertRCReturn(rc, rc);
1623# ifdef DEBUG_CMD_BUFFER
1624 uint8_t i = 0;
1625 do {
1626 LogFunc(("RIRB%02x: ", i));
1627 uint8_t j = 0;
1628 do {
1629 const char *prefix;
1630 if ((i + j) == HDA_REG(pThis, RIRBWP))
1631 prefix = "[W]";
1632 else
1633 prefix = " ";
1634 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1635 } while (++j < 8);
1636 LogFunc(("\n"));
1637 i += 8;
1638 } while (i != 0);
1639# endif
1640 }
1641 return rc;
1642}
1643
1644static int hdaCORBCmdProcess(PHDASTATE pThis)
1645{
1646 int rc = hdaCmdSync(pThis, true);
1647 if (RT_FAILURE(rc))
1648 AssertRCReturn(rc, rc);
1649
1650 uint8_t corbRp = HDA_REG(pThis, CORBRP);
1651 uint8_t corbWp = HDA_REG(pThis, CORBWP);
1652 uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
1653
1654 Assert((corbWp != corbRp));
1655 Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1656
1657 while (corbRp != corbWp)
1658 {
1659 uint64_t uResp;
1660 uint32_t uCmd = pThis->pu32CorbBuf[++corbRp];
1661
1662 int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(uCmd, 0 /* Codec index */), &uResp);
1663 if (RT_FAILURE(rc2))
1664 LogFunc(("Codec lookup failed with rc=%Rrc\n", rc2));
1665
1666 (rirbWp)++;
1667
1668 if ( (uResp & CODEC_RESPONSE_UNSOLICITED)
1669 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1670 {
1671 LogFunc(("Unexpected unsolicited response\n"));
1672 HDA_REG(pThis, CORBRP) = corbRp;
1673 return rc;
1674 }
1675
1676 pThis->pu64RirbBuf[rirbWp] = uResp;
1677
1678 pThis->u8RespIntCnt++;
1679 if (pThis->u8RespIntCnt == RINTCNT_N(pThis))
1680 break;
1681 }
1682
1683 HDA_REG(pThis, CORBRP) = corbRp;
1684 HDA_REG(pThis, RIRBWP) = rirbWp;
1685
1686 rc = hdaCmdSync(pThis, false);
1687
1688 Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1689
1690 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1691 {
1692 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1693
1694 pThis->u8RespIntCnt = 0;
1695 rc = hdaProcessInterrupt(pThis);
1696 }
1697
1698 if (RT_FAILURE(rc))
1699 AssertRCReturn(rc, rc);
1700 return rc;
1701}
1702
1703static int hdaStreamCreate(PHDASTATE pThis, PHDASTREAM pStream, uint8_t uSD)
1704{
1705 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1706 AssertReturn(uSD <= HDA_MAX_STREAMS, VERR_INVALID_PARAMETER);
1707
1708 int rc = RTCritSectInit(&pStream->State.CritSect);
1709 if (RT_SUCCESS(rc))
1710 {
1711 pStream->u8SD = uSD;
1712 pStream->pMixSink = NULL;
1713
1714 pStream->State.fInReset = false;
1715 }
1716
1717 if (RT_SUCCESS(rc))
1718 rc = RTCircBufCreate(&pStream->State.pCircBuf, _4K); /** @todo Make this configurable. */
1719
1720#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1721 /*
1722 * Create async I/O stuff.
1723 */
1724 PHDASTREAMSTATEAIO pAIO = &pStream->State.AIO;
1725
1726 pAIO->fShutdown = false;
1727
1728 if (RT_SUCCESS(rc))
1729 {
1730 rc = RTSemEventCreate(&pAIO->Event);
1731 if (RT_SUCCESS(rc))
1732 {
1733 rc = RTCritSectInit(&pAIO->CritSect);
1734 if (RT_SUCCESS(rc))
1735 {
1736 HDASTREAMTHREADCTX Ctx = { pThis, pStream };
1737
1738 char szThreadName[64];
1739 RTStrPrintf2(szThreadName, sizeof(szThreadName), "hdaAIO%RU8", pStream->u8SD);
1740
1741 /** @todo Create threads on demand? */
1742
1743 rc = RTThreadCreate(&pAIO->Thread, hdaStreamAsyncIOThread, &Ctx,
1744 0, RTTHREADTYPE_IO, RTTHREADFLAGS_WAITABLE, szThreadName);
1745 if (RT_SUCCESS(rc))
1746 rc = RTThreadUserWait(pAIO->Thread, 10 * 1000 /* 10s timeout */);
1747 }
1748 }
1749 }
1750#else
1751 RT_NOREF(pThis);
1752#endif
1753
1754 LogFlowFunc(("uSD=%RU8\n", uSD));
1755 return rc;
1756}
1757
1758static void hdaStreamDestroy(PHDASTATE pThis, PHDASTREAM pStream)
1759{
1760 AssertPtrReturnVoid(pStream);
1761
1762 LogFlowFunc(("[SD%RU8]: Destroying ...\n", pStream->u8SD));
1763
1764 hdaStreamMapDestroy(&pStream->State.Mapping);
1765
1766 int rc2 = RTCritSectDelete(&pStream->State.CritSect);
1767 AssertRC(rc2);
1768
1769 if (pStream->State.pCircBuf)
1770 {
1771 RTCircBufDestroy(pStream->State.pCircBuf);
1772 pStream->State.pCircBuf = NULL;
1773 }
1774
1775#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1776 /*
1777 * Destroy async I/O stuff.
1778 */
1779 PHDASTREAMSTATEAIO pAIO = &pStream->State.AIO;
1780
1781 if (ASMAtomicReadBool(&pAIO->fStarted))
1782 {
1783 ASMAtomicWriteBool(&pAIO->fShutdown, true);
1784
1785 rc2 = hdaStreamAsyncIONotify(pThis, pStream);
1786 AssertRC(rc2);
1787
1788 int rcThread;
1789 rc2 = RTThreadWait(pAIO->Thread, 30 * 1000 /* 30s timeout */, &rcThread);
1790 LogFunc(("Async I/O thread ended with %Rrc (%Rrc)\n", rc2, rcThread));
1791
1792 if (RT_SUCCESS(rc2))
1793 {
1794 rc2 = RTCritSectDelete(&pAIO->CritSect);
1795 AssertRC(rc2);
1796
1797 rc2 = RTSemEventDestroy(pAIO->Event);
1798 AssertRC(rc2);
1799
1800 pAIO->fStarted = false;
1801 pAIO->fShutdown = false;
1802 }
1803 }
1804#else
1805 RT_NOREF(pThis);
1806#endif
1807
1808 LogFlowFuncLeave();
1809}
1810
1811static int hdaStreamInit(PHDASTATE pThis, PHDASTREAM pStream, uint8_t u8SD)
1812{
1813 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1814 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1815
1816 pStream->u8SD = u8SD;
1817 pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
1818 HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
1819 pStream->u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
1820 pStream->u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
1821 pStream->u16FIFOS = HDA_STREAM_REG(pThis, FIFOS, pStream->u8SD) + 1;
1822
1823 RT_ZERO(pStream->State.BDLE);
1824 pStream->State.uCurBDLE = 0;
1825
1826 hdaStreamMapReset(&pStream->State.Mapping);
1827
1828 LogFlowFunc(("[SD%RU8]: DMA @ 0x%x (%RU32 bytes), LVI=%RU16, FIFOS=%RU16\n",
1829 pStream->u8SD, pStream->u64BDLBase, pStream->u32CBL, pStream->u16LVI, pStream->u16FIFOS));
1830
1831# ifdef DEBUG
1832 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
1833 HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
1834 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
1835 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
1836
1837 LogFlowFunc(("\t-> DMA @ 0x%x, LVI=%RU16, CBL=%RU32\n", u64BaseDMA, u16LVI, u32CBL));
1838
1839 hdaBDLEDumpAll(pThis, u64BaseDMA, u16LVI + 1);
1840# endif
1841
1842 return VINF_SUCCESS;
1843}
1844
1845static void hdaStreamReset(PHDASTATE pThis, PHDASTREAM pStream)
1846{
1847 AssertPtrReturnVoid(pThis);
1848 AssertPtrReturnVoid(pStream);
1849
1850 const uint8_t uSD = pStream->u8SD;
1851
1852# ifdef VBOX_STRICT
1853 AssertReleaseMsg(!RT_BOOL(HDA_STREAM_REG(pThis, CTL, uSD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
1854 ("[SD%RU8] Cannot reset stream while in running state\n", uSD));
1855# endif
1856
1857 LogFunc(("[SD%RU8]: Reset\n", uSD));
1858
1859 /*
1860 * Set reset state.
1861 */
1862 Assert(ASMAtomicReadBool(&pStream->State.fInReset) == false); /* No nested calls. */
1863 ASMAtomicXchgBool(&pStream->State.fInReset, true);
1864
1865 /*
1866 * First, reset the internal stream state.
1867 */
1868 RT_ZERO(pStream->State.BDLE);
1869 pStream->State.uCurBDLE = 0;
1870
1871 if (pStream->State.pCircBuf)
1872 RTCircBufReset(pStream->State.pCircBuf);
1873
1874 /*
1875 * Second, initialize the registers.
1876 */
1877 HDA_STREAM_REG(pThis, STS, uSD) = HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1878 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1879 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
1880 HDA_STREAM_REG(pThis, CTL, uSD) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1881 /*
1882 * ICH6 defines default values (120 bytes for input and 192 bytes for output descriptors) of FIFO size. 18.2.39.
1883 * BUT: Windows guests seem to read the FIFOS but define a DMA region which does not fit to that FIFO size
1884 * (e.g. 1792 bytes DMA region vs. 192 bytes FIFOS).
1885 * This will lead to crackling and corrupted sound -- so define a 256 bytes FIOS for output streams here per default.
1886 */
1887 HDA_STREAM_REG(pThis, FIFOS, uSD) = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? HDA_SDIFIFO_120B : HDA_SDOFIFO_256B;
1888 /* See 18.2.38: Always defaults to 0x4 (32 bytes). */
1889 HDA_STREAM_REG(pThis, FIFOW, uSD) = HDA_SDFIFOW_32B;
1890 HDA_STREAM_REG(pThis, LPIB, uSD) = 0;
1891 HDA_STREAM_REG(pThis, CBL, uSD) = 0;
1892 HDA_STREAM_REG(pThis, LVI, uSD) = 0;
1893 HDA_STREAM_REG(pThis, FMT, uSD) = HDA_SDFMT_MAKE(HDA_SDFMT_TYPE_PCM, HDA_SDFMT_BASE_44KHZ,
1894 HDA_SDFMT_MULT_1X, HDA_SDFMT_DIV_1X, HDA_SDFMT_16_BIT,
1895 HDA_SDFMT_CHAN_STEREO);
1896 HDA_STREAM_REG(pThis, BDPU, uSD) = 0;
1897 HDA_STREAM_REG(pThis, BDPL, uSD) = 0;
1898
1899 int rc2 = hdaStreamInit(pThis, pStream, uSD);
1900 AssertRC(rc2);
1901
1902 /* Exit reset state. */
1903 ASMAtomicXchgBool(&pStream->State.fInReset, false);
1904}
1905
1906static int hdaStreamEnable(PHDASTATE pThis, PHDASTREAM pStream, bool fEnable)
1907{
1908 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1909 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1910
1911 LogFlowFunc(("[SD%RU8]: fEnable=%RTbool, pMixSink=%p\n", pStream->u8SD, fEnable, pStream->pMixSink));
1912
1913 int rc = VINF_SUCCESS;
1914
1915#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1916 hdaStreamAsyncIOLock(pStream);
1917#endif
1918
1919 if (pStream->pMixSink) /* Stream attached to a sink? */
1920 {
1921 AUDMIXSINKCMD enmCmd = fEnable
1922 ? AUDMIXSINKCMD_ENABLE : AUDMIXSINKCMD_DISABLE;
1923
1924 /* First, enable or disable the stream and the stream's sink, if any. */
1925 if (pStream->pMixSink->pMixSink)
1926 rc = AudioMixerSinkCtl(pStream->pMixSink->pMixSink, enmCmd);
1927 }
1928 else
1929 rc = VINF_SUCCESS;
1930
1931#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1932 hdaStreamAsyncIOUnlock(pStream);
1933#endif
1934
1935 if (RT_FAILURE(rc))
1936 {
1937 LogFunc(("Failed with rc=%Rrc\n", rc));
1938 return rc;
1939 }
1940
1941 /* Second, see if we need to start or stop the timer. */
1942 if (!fEnable)
1943 {
1944# ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
1945 hdaTimerMaybeStop(pThis);
1946# endif
1947 }
1948 else
1949 {
1950# ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
1951 hdaTimerMaybeStart(pThis);
1952# endif
1953 }
1954
1955 LogFlowFunc(("u8Strm=%RU8, fEnable=%RTbool, cStreamsActive=%RU8\n", pStream->u8SD, fEnable, pThis->cStreamsActive));
1956 return VINF_SUCCESS;
1957}
1958
1959static void hdaStreamAssignToSink(PHDASTREAM pStream, PHDAMIXERSINK pMixSink)
1960{
1961 AssertPtrReturnVoid(pStream);
1962
1963 int rc2 = RTCritSectEnter(&pStream->State.CritSect);
1964 if (RT_SUCCESS(rc2))
1965 {
1966 pStream->pMixSink = pMixSink;
1967
1968 rc2 = RTCritSectLeave(&pStream->State.CritSect);
1969 AssertRC(rc2);
1970 }
1971}
1972
1973# if defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_AUDIO_HDA_51_SURROUND)
1974static int hdaStreamChannelExtract(PPDMAUDIOSTREAMCHANNEL pChan, const void *pvBuf, size_t cbBuf)
1975{
1976 AssertPtrReturn(pChan, VERR_INVALID_POINTER);
1977 AssertPtrReturn(pvBuf, VERR_INVALID_POINTER);
1978 AssertReturn(cbBuf, VERR_INVALID_PARAMETER);
1979
1980 AssertRelease(pChan->cbOff <= cbBuf);
1981
1982 const uint8_t *pu8Buf = (const uint8_t *)pvBuf;
1983
1984 size_t cbSrc = cbBuf - pChan->cbOff;
1985 const uint8_t *pvSrc = &pu8Buf[pChan->cbOff];
1986
1987 size_t cbDst;
1988 uint8_t *pvDst;
1989 RTCircBufAcquireWriteBlock(pChan->Data.pCircBuf, cbBuf, (void **)&pvDst, &cbDst);
1990
1991 cbSrc = RT_MIN(cbSrc, cbDst);
1992
1993 while (cbSrc)
1994 {
1995 AssertBreak(cbDst >= cbSrc);
1996
1997 /* Enough data for at least one next frame? */
1998 if (cbSrc < pChan->cbFrame)
1999 break;
2000
2001 memcpy(pvDst, pvSrc, pChan->cbFrame);
2002
2003 /* Advance to next channel frame in stream. */
2004 pvSrc += pChan->cbStep;
2005 Assert(cbSrc >= pChan->cbStep);
2006 cbSrc -= pChan->cbStep;
2007
2008 /* Advance destination by one frame. */
2009 pvDst += pChan->cbFrame;
2010 Assert(cbDst >= pChan->cbFrame);
2011 cbDst -= pChan->cbFrame;
2012
2013 /* Adjust offset. */
2014 pChan->cbOff += pChan->cbFrame;
2015 }
2016
2017 RTCircBufReleaseWriteBlock(pChan->Data.pCircBuf, cbDst);
2018
2019 return VINF_SUCCESS;
2020}
2021# endif /* defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_AUDIO_HDA_51_SURROUND) */
2022
2023# if 0 /** @todo hdaStreamChannelAdvance is unused */
2024static int hdaStreamChannelAdvance(PPDMAUDIOSTREAMCHANNEL pChan, size_t cbAdv)
2025{
2026 AssertPtrReturn(pChan, VERR_INVALID_POINTER);
2027
2028 if (!cbAdv)
2029 return VINF_SUCCESS;
2030
2031 return VINF_SUCCESS;
2032}
2033# endif
2034
2035static int hdaStreamChannelDataInit(PPDMAUDIOSTREAMCHANNELDATA pChanData, uint32_t fFlags)
2036{
2037 int rc = RTCircBufCreate(&pChanData->pCircBuf, 256); /** @todo Make this configurable? */
2038 if (RT_SUCCESS(rc))
2039 {
2040 pChanData->fFlags = fFlags;
2041 }
2042
2043 return rc;
2044}
2045
2046/**
2047 * Frees a stream channel data block again.
2048 *
2049 * @param pChanData Pointer to channel data to free.
2050 */
2051static void hdaStreamChannelDataDestroy(PPDMAUDIOSTREAMCHANNELDATA pChanData)
2052{
2053 if (!pChanData)
2054 return;
2055
2056 if (pChanData->pCircBuf)
2057 {
2058 RTCircBufDestroy(pChanData->pCircBuf);
2059 pChanData->pCircBuf = NULL;
2060 }
2061
2062 pChanData->fFlags = PDMAUDIOSTREAMCHANNELDATA_FLAG_NONE;
2063}
2064
2065# if defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_AUDIO_HDA_51_SURROUND)
2066
2067static int hdaStreamChannelAcquireData(PPDMAUDIOSTREAMCHANNELDATA pChanData, void *pvData, size_t *pcbData)
2068{
2069 AssertPtrReturn(pChanData, VERR_INVALID_POINTER);
2070 AssertPtrReturn(pvData, VERR_INVALID_POINTER);
2071 AssertPtrReturn(pcbData, VERR_INVALID_POINTER);
2072
2073 RTCircBufAcquireReadBlock(pChanData->pCircBuf, 256 /** @todo Make this configurarble? */, &pvData, &pChanData->cbAcq);
2074
2075 *pcbData = pChanData->cbAcq;
2076 return VINF_SUCCESS;
2077}
2078
2079static int hdaStreamChannelReleaseData(PPDMAUDIOSTREAMCHANNELDATA pChanData)
2080{
2081 AssertPtrReturn(pChanData, VERR_INVALID_POINTER);
2082 RTCircBufReleaseReadBlock(pChanData->pCircBuf, pChanData->cbAcq);
2083
2084 return VINF_SUCCESS;
2085}
2086
2087# endif /* defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_AUDIO_HDA_51_SURROUND) */
2088
2089# if 0 /* currently unused */
2090static int hdaStreamWaitForStateChange(PHDASTREAM pStream, RTMSINTERVAL msTimeout)
2091{
2092 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
2093
2094 LogFlowFunc(("[SD%RU8]: msTimeout=%RU32\n", pStream->u8SD, msTimeout));
2095 return RTSemEventWait(pStream->State.hStateChangedEvent, msTimeout);
2096}
2097# endif /* currently unused */
2098
2099#endif /* IN_RING3 */
2100
2101/* Register access handlers. */
2102
2103static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2104{
2105 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg);
2106 *pu32Value = 0;
2107 return VINF_SUCCESS;
2108}
2109
2110static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2111{
2112 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2113 return VINF_SUCCESS;
2114}
2115
2116/* U8 */
2117static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2118{
2119 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
2120 return hdaRegReadU32(pThis, iReg, pu32Value);
2121}
2122
2123static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2124{
2125 Assert((u32Value & 0xffffff00) == 0);
2126 return hdaRegWriteU32(pThis, iReg, u32Value);
2127}
2128
2129/* U16 */
2130static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2131{
2132 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
2133 return hdaRegReadU32(pThis, iReg, pu32Value);
2134}
2135
2136static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2137{
2138 Assert((u32Value & 0xffff0000) == 0);
2139 return hdaRegWriteU32(pThis, iReg, u32Value);
2140}
2141
2142/* U24 */
2143static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2144{
2145 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
2146 return hdaRegReadU32(pThis, iReg, pu32Value);
2147}
2148
2149#ifdef IN_RING3
2150static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2151{
2152 Assert((u32Value & 0xff000000) == 0);
2153 return hdaRegWriteU32(pThis, iReg, u32Value);
2154}
2155#endif
2156
2157/* U32 */
2158static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2159{
2160 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2161
2162 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
2163 return VINF_SUCCESS;
2164}
2165
2166static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2167{
2168 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2169
2170 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
2171 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
2172 return VINF_SUCCESS;
2173}
2174
2175static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2176{
2177 RT_NOREF_PV(iReg);
2178
2179 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
2180 {
2181 /* Set the CRST bit to indicate that we're leaving reset mode. */
2182 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
2183
2184 if (pThis->fInReset)
2185 {
2186 LogFunc(("Guest leaving HDA reset\n"));
2187 pThis->fInReset = false;
2188 }
2189 }
2190 else
2191 {
2192#ifdef IN_RING3
2193 /* Enter reset state. */
2194 LogFunc(("Guest entering HDA reset with DMA(RIRB:%s, CORB:%s)\n",
2195 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
2196 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
2197
2198 /* Clear the CRST bit to indicate that we're in reset state. */
2199 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
2200 pThis->fInReset = true;
2201
2202 hdaReset(pThis->CTX_SUFF(pDevIns));
2203#else
2204 return VINF_IOM_R3_MMIO_WRITE;
2205#endif
2206 }
2207
2208 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
2209 {
2210 /* Flush: GSTS:1 set, see 6.2.6. */
2211 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* Set the flush state. */
2212 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
2213 }
2214 return VINF_SUCCESS;
2215}
2216
2217static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2218{
2219 uint32_t v = HDA_REG_IND(pThis, iReg);
2220 uint32_t nv = u32Value & HDA_STATESTS_SCSF_MASK;
2221
2222 HDA_REG(pThis, STATESTS) &= ~(v & nv); /* Write of 1 clears corresponding bit. */
2223
2224 return hdaProcessInterrupt(pThis);
2225}
2226
2227static int hdaRegWriteINTCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2228{
2229 RT_NOREF(iReg);
2230
2231 int rc;
2232
2233 HDA_REG(pThis, INTCTL) = u32Value;
2234
2235 /* Global Interrupt Enable (GIE) set? */
2236 if (u32Value & HDA_INTCTL_GIE_MASK)
2237 {
2238 rc = hdaProcessInterrupt(pThis);
2239 }
2240 else
2241 {
2242 /** @todo Clear INTSTS's individual stream status bits as well? */
2243
2244 /* Make sure to lower interrupt line, as Global Interrupt Enable (GIE) is disabled. */
2245 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 0 /* iLevel */);
2246
2247 rc = VINF_SUCCESS;
2248 }
2249
2250 return rc;
2251}
2252
2253static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2254{
2255 const uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
2256 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, u8Strm);
2257#ifdef LOG_ENABLED
2258 const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
2259 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32\n", u8Strm, u32LPIB, u32CBL));
2260#endif
2261
2262 *pu32Value = u32LPIB;
2263 return VINF_SUCCESS;
2264}
2265
2266static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2267{
2268 RT_NOREF_PV(iReg);
2269
2270 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
2271 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
2272 - pThis->u64BaseTS, 24, 1000);
2273 LogFlowFunc(("%RU32\n", *pu32Value));
2274 return VINF_SUCCESS;
2275}
2276
2277static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2278{
2279 RT_NOREF_PV(iReg);
2280
2281 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
2282 {
2283 HDA_REG(pThis, CORBRP) = 0;
2284 }
2285#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
2286 else
2287 return hdaRegWriteU8(pThis, iReg, u32Value);
2288#endif
2289 return VINF_SUCCESS;
2290}
2291
2292static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2293{
2294#ifdef IN_RING3
2295 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
2296 AssertRC(rc);
2297 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2298 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
2299 {
2300 return hdaCORBCmdProcess(pThis);
2301 }
2302 return rc;
2303#else
2304 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2305 return VINF_IOM_R3_MMIO_WRITE;
2306#endif
2307}
2308
2309static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2310{
2311 RT_NOREF_PV(iReg);
2312
2313 uint32_t v = HDA_REG(pThis, CORBSTS);
2314 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
2315 return VINF_SUCCESS;
2316}
2317
2318static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2319{
2320#ifdef IN_RING3
2321 int rc;
2322 rc = hdaRegWriteU16(pThis, iReg, u32Value);
2323 if (RT_FAILURE(rc))
2324 AssertRCReturn(rc, rc);
2325 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
2326 return VINF_SUCCESS;
2327 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
2328 return VINF_SUCCESS;
2329 rc = hdaCORBCmdProcess(pThis);
2330 return rc;
2331#else /* !IN_RING3 */
2332 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2333 return VINF_IOM_R3_MMIO_WRITE;
2334#endif /* IN_RING3 */
2335}
2336
2337static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2338{
2339#ifdef IN_RING3
2340 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2341 return VINF_SUCCESS;
2342
2343 PHDASTREAM pStream = hdaStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, CBL, iReg));
2344 if (!pStream)
2345 {
2346 LogFunc(("[SD%RU8]: Warning: Changing SDCBL on non-attached stream (0x%x)\n", HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
2347 return hdaRegWriteU32(pThis, iReg, u32Value);
2348 }
2349
2350 int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2351 AssertRC(rc2);
2352
2353 pStream->u32CBL = u32Value;
2354
2355 /* Reset BDLE state. */
2356 RT_ZERO(pStream->State.BDLE);
2357 pStream->State.uCurBDLE = 0;
2358
2359 rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2360 AssertRC(rc2);
2361
2362 LogFlowFunc(("[SD%RU8]: CBL=%RU32\n", pStream->u8SD, u32Value));
2363 hdaRegWriteSDUnlock(pStream);
2364
2365 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2366#else /* !IN_RING3 */
2367 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2368 return VINF_IOM_R3_MMIO_WRITE;
2369#endif /* IN_RING3 */
2370}
2371
2372static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2373{
2374#ifdef IN_RING3
2375 /*
2376 * Some guests write too much (that is, 32-bit with the top 8 bit being junk)
2377 * instead of 24-bit required for SDCTL. So just mask this here to be safe.
2378 */
2379 u32Value = (u32Value & 0x00ffffff);
2380
2381 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2382 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2383
2384 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
2385 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
2386
2387 /* Get the stream descriptor. */
2388 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
2389
2390 LogFunc(("[SD%RU8]: fRun=%RTbool, fInRun=%RTbool, fReset=%RTbool, fInReset=%RTbool, %R[sdctl]\n",
2391 uSD, fRun, fInRun, fReset, fInReset, u32Value));
2392
2393 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2394 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2395
2396 /*
2397 * Extract the stream tag the guest wants to use for this specific
2398 * stream descriptor (SDn). This only can happen if the stream is in a non-running
2399 * state, so we're doing the lookup and assignment here.
2400 *
2401 * So depending on the guest OS, SD3 can use stream tag 4, for example.
2402 */
2403 uint8_t uTag = (u32Value >> HDA_SDCTL_NUM_SHIFT) & HDA_SDCTL_NUM_MASK;
2404 if (uTag > HDA_MAX_TAGS)
2405 {
2406 LogFunc(("[SD%RU8]: Warning: Invalid stream tag %RU8 specified!\n", uSD, uTag));
2407 return hdaRegWriteU24(pThis, iReg, u32Value);
2408 }
2409
2410 PHDATAG pTag = &pThis->aTags[uTag];
2411 AssertPtr(pTag);
2412
2413 LogFunc(("[SD%RU8]: Using stream tag=%RU8\n", uSD, uTag));
2414
2415 /* Assign new values. */
2416 pTag->uTag = uTag;
2417 pTag->pStrm = hdaStreamFromSD(pThis, uSD);
2418
2419 PHDASTREAM pStream = pTag->pStrm;
2420 AssertPtr(pStream);
2421
2422 /* Note: Do not use hdaRegWriteSDLock() here, as SDnCTL might change the RUN bit. */
2423 int rc2 = RTCritSectEnter(&pStream->State.CritSect);
2424 AssertRC(rc2);
2425
2426 if (fInReset)
2427 {
2428 Assert(!fReset);
2429 Assert(!fInRun && !fRun);
2430
2431 /* Report that we're done resetting this stream by clearing SRST. */
2432 HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST);
2433
2434 LogFunc(("[SD%RU8]: Guest initiated exit of stream reset\n", uSD));
2435 }
2436 else if (fReset)
2437 {
2438 /* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
2439 Assert(!fInRun && !fRun);
2440
2441 LogFunc(("[SD%RU8]: Guest initiated enter to stream reset\n", pStream->u8SD));
2442
2443 hdaStreamReset(pThis, pStream);
2444 }
2445 else
2446 {
2447 /*
2448 * We enter here to change DMA states only.
2449 */
2450 if (fInRun != fRun)
2451 {
2452 Assert(!fReset && !fInReset);
2453 LogFunc(("[SD%RU8]: State changed (fRun=%RTbool)\n", pStream->u8SD, fRun));
2454
2455 hdaStreamEnable(pThis, pStream, fRun /* fEnable */);
2456
2457 if (fRun)
2458 {
2459 /* (Re-)Fetch the current BDLE entry. */
2460 rc2 = hdaBDLEFetch(pThis, &pStream->State.BDLE, pStream->u64BDLBase, pStream->State.uCurBDLE);
2461 AssertRC(rc2);
2462 }
2463 }
2464 }
2465
2466 rc2 = hdaRegWriteU24(pThis, iReg, u32Value);
2467 AssertRC(rc2);
2468
2469 /* Make sure to handle interrupts here as well. */
2470 hdaProcessInterrupt(pThis);
2471
2472 hdaRegWriteSDUnlock(pStream);
2473 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2474#else /* !IN_RING3 */
2475 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2476 return VINF_IOM_R3_MMIO_WRITE;
2477#endif /* IN_RING3 */
2478}
2479
2480static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2481{
2482 uint32_t v = HDA_REG_IND(pThis, iReg);
2483
2484 /* Clear (zero) FIFOE, DESE and BCIS bits when writing 1 to it (6.2.33). */
2485 HDA_REG_IND(pThis, iReg) &= ~(u32Value & v);
2486
2487 LogFunc(("SDSTS 0x%x -> 0x%x\n", v, HDA_REG_IND(pThis, iReg)));
2488
2489 hdaProcessInterrupt(pThis);
2490 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2491}
2492
2493static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2494{
2495#ifdef IN_RING3
2496 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2497 return VINF_SUCCESS;
2498
2499 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, LVI, iReg);
2500
2501 PHDASTREAM pStream = hdaStreamFromSD(pThis, uSD);
2502 if (!pStream)
2503 {
2504 AssertMsgFailed(("[SD%RU8]: Warning: Changing SDLVI on non-attached stream (0x%x)\n", uSD, u32Value));
2505 return hdaRegWriteU16(pThis, iReg, u32Value);
2506 }
2507
2508 int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2509 if (RT_SUCCESS(rc2))
2510 {
2511 /** @todo Validate LVI. */
2512 pStream->u16LVI = u32Value;
2513 LogFunc(("[SD%RU8]: Updating LVI to %RU32\n", uSD, pStream->u16LVI));
2514
2515 /* Reset BDLE state. */
2516 RT_ZERO(pStream->State.BDLE);
2517 pStream->State.uCurBDLE = 0;
2518
2519 rc2 = hdaRegWriteU16(pThis, iReg, u32Value);
2520 AssertRC(rc2);
2521
2522 hdaRegWriteSDUnlock(pStream);
2523 }
2524 else
2525 LogRel(("HDA: Warning: Guest tried to write LVI to running stream #%RU8, ignoring\n", uSD));
2526
2527 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2528
2529#else /* !IN_RING3 */
2530 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2531 return VINF_IOM_R3_MMIO_WRITE;
2532#endif /* IN_RING3 */
2533}
2534
2535static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2536{
2537#ifdef IN_RING3
2538 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg);
2539
2540 if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_IN) /* FIFOW for input streams only. */
2541 {
2542 LogRel(("HDA: Warning: Guest tried to write read-only FIFOW to output stream #%RU8, ignoring\n", uSD));
2543 return VINF_SUCCESS;
2544 }
2545
2546 PHDASTREAM pStream = hdaStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg));
2547 if (!pStream)
2548 {
2549 AssertMsgFailed(("[SD%RU8]: Warning: Changing FIFOW on non-attached stream (0x%x)\n", uSD, u32Value));
2550 return hdaRegWriteU16(pThis, iReg, u32Value);
2551 }
2552
2553 int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2554 if (RT_SUCCESS(rc2))
2555 {
2556 uint32_t u32FIFOW = 0;
2557
2558 switch (u32Value)
2559 {
2560 case HDA_SDFIFOW_8B:
2561 case HDA_SDFIFOW_16B:
2562 case HDA_SDFIFOW_32B:
2563 u32FIFOW = u32Value;
2564 break;
2565 default:
2566 LogRel(("HDA: Warning: Guest tried write unsupported FIFOW (0x%x) to stream #%RU8, defaulting to 32 bytes\n",
2567 u32Value, uSD));
2568 AssertFailed();
2569 u32FIFOW = HDA_SDFIFOW_32B;
2570 break;
2571 }
2572
2573 if (u32FIFOW)
2574 {
2575 pStream->u16FIFOW = hdaSDFIFOWToBytes(u32FIFOW);
2576 LogFunc(("[SD%RU8]: Updating FIFOW to %RU32 bytes\n", uSD, pStream->u16FIFOW));
2577
2578 rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOW);
2579 AssertRC(rc2);
2580 }
2581
2582 hdaRegWriteSDUnlock(pStream);
2583 }
2584 else
2585 LogRel(("HDA: Warning: Guest tried to write FIFOW to running stream #%RU8, ignoring\n", uSD));
2586
2587 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2588#else /* !IN_RING3 */
2589 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2590 return VINF_IOM_R3_MMIO_WRITE;
2591#endif /* IN_RING3 */
2592}
2593
2594/**
2595 * @note This method could be called for changing value on Output Streams only (ICH6 datasheet 18.2.39).
2596 */
2597static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2598{
2599#ifdef IN_RING3
2600 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOS, iReg);
2601
2602 if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_OUT) /* FIFOS for output streams only. */
2603 {
2604 LogRel(("HDA: Warning: Guest tried to write read-only FIFOS to input stream #%RU8, ignoring\n", uSD));
2605 return VINF_SUCCESS;
2606 }
2607
2608 PHDASTREAM pStream = hdaStreamFromSD(pThis, uSD);
2609 if (!pStream)
2610 {
2611 AssertMsgFailed(("[SD%RU8]: Warning: Changing FIFOS on non-attached stream (0x%x)\n", uSD, u32Value));
2612 return hdaRegWriteU16(pThis, iReg, u32Value);
2613 }
2614
2615 int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2616 if (RT_SUCCESS(rc2))
2617 {
2618 uint32_t u32FIFOS = 0;
2619
2620 switch(u32Value)
2621 {
2622 case HDA_SDOFIFO_16B:
2623 case HDA_SDOFIFO_32B:
2624 case HDA_SDOFIFO_64B:
2625 case HDA_SDOFIFO_128B:
2626 case HDA_SDOFIFO_192B:
2627 case HDA_SDOFIFO_256B:
2628 u32FIFOS = u32Value;
2629 break;
2630
2631 default:
2632 LogRel(("HDA: Warning: Guest tried write unsupported FIFOS (0x%x) to stream #%RU8, defaulting to 192 bytes\n",
2633 u32Value, uSD));
2634 AssertFailed();
2635 u32FIFOS = HDA_SDOFIFO_192B;
2636 break;
2637 }
2638
2639 if (u32FIFOS)
2640 {
2641 pStream->u16FIFOS = u32FIFOS + 1;
2642 LogFunc(("[SD%RU8]: Updating FIFOS to %RU32 bytes\n", uSD, pStream->u16FIFOS));
2643
2644 rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOS);
2645 AssertRC(rc2);
2646 }
2647
2648 hdaRegWriteSDUnlock(pStream);
2649 }
2650 else
2651 LogRel(("HDA: Warning: Guest tried to write FIFOS to running stream #%RU8, ignoring\n", uSD));
2652
2653 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2654#else /* !IN_RING3 */
2655 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2656 return VINF_IOM_R3_MMIO_WRITE;
2657#endif /* IN_RING3 */
2658}
2659
2660#ifdef IN_RING3
2661static int hdaSDFMTToStrmCfg(uint32_t u32SDFMT, PPDMAUDIOSTREAMCFG pStrmCfg)
2662{
2663 AssertPtrReturn(pStrmCfg, VERR_INVALID_POINTER);
2664
2665# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
2666
2667 int rc = VINF_SUCCESS;
2668
2669 uint32_t u32Hz = EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BASE_RATE_MASK, HDA_SDFMT_BASE_RATE_SHIFT)
2670 ? 44100 : 48000;
2671 uint32_t u32HzMult = 1;
2672 uint32_t u32HzDiv = 1;
2673
2674 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
2675 {
2676 case 0: u32HzMult = 1; break;
2677 case 1: u32HzMult = 2; break;
2678 case 2: u32HzMult = 3; break;
2679 case 3: u32HzMult = 4; break;
2680 default:
2681 LogFunc(("Unsupported multiplier %x\n",
2682 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
2683 rc = VERR_NOT_SUPPORTED;
2684 break;
2685 }
2686 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
2687 {
2688 case 0: u32HzDiv = 1; break;
2689 case 1: u32HzDiv = 2; break;
2690 case 2: u32HzDiv = 3; break;
2691 case 3: u32HzDiv = 4; break;
2692 case 4: u32HzDiv = 5; break;
2693 case 5: u32HzDiv = 6; break;
2694 case 6: u32HzDiv = 7; break;
2695 case 7: u32HzDiv = 8; break;
2696 default:
2697 LogFunc(("Unsupported divisor %x\n",
2698 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
2699 rc = VERR_NOT_SUPPORTED;
2700 break;
2701 }
2702
2703 PDMAUDIOFMT enmFmt;
2704 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
2705 {
2706 case 0:
2707 enmFmt = PDMAUDIOFMT_S8;
2708 break;
2709 case 1:
2710 enmFmt = PDMAUDIOFMT_S16;
2711 break;
2712 case 4:
2713 enmFmt = PDMAUDIOFMT_S32;
2714 break;
2715 default:
2716 AssertMsgFailed(("Unsupported bits per sample %x\n",
2717 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
2718 enmFmt = PDMAUDIOFMT_INVALID;
2719 rc = VERR_NOT_SUPPORTED;
2720 break;
2721 }
2722
2723 if (RT_SUCCESS(rc))
2724 {
2725 pStrmCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
2726 pStrmCfg->cChannels = (u32SDFMT & 0xf) + 1;
2727 pStrmCfg->enmFormat = enmFmt;
2728 pStrmCfg->enmEndianness = PDMAUDIOHOSTENDIANNESS;
2729 }
2730
2731# undef EXTRACT_VALUE
2732 return rc;
2733}
2734
2735static int hdaAddStreamOut(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
2736{
2737 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2738 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2739
2740 AssertReturn(pCfg->enmDir == PDMAUDIODIR_OUT, VERR_INVALID_PARAMETER);
2741
2742 LogFlowFunc(("Stream=%s\n", pCfg->szName));
2743
2744 int rc = VINF_SUCCESS;
2745
2746 bool fUseFront = true; /* Always use front out by default. */
2747#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2748 bool fUseRear;
2749 bool fUseCenter;
2750 bool fUseLFE;
2751
2752 fUseRear = fUseCenter = fUseLFE = false;
2753
2754 /*
2755 * Use commonly used setups for speaker configurations.
2756 */
2757
2758 /** @todo Make the following configurable through mixer API and/or CFGM? */
2759 switch (pCfg->cChannels)
2760 {
2761 case 3: /* 2.1: Front (Stereo) + LFE. */
2762 {
2763 fUseLFE = true;
2764 break;
2765 }
2766
2767 case 4: /* Quadrophonic: Front (Stereo) + Rear (Stereo). */
2768 {
2769 fUseRear = true;
2770 break;
2771 }
2772
2773 case 5: /* 4.1: Front (Stereo) + Rear (Stereo) + LFE. */
2774 {
2775 fUseRear = true;
2776 fUseLFE = true;
2777 break;
2778 }
2779
2780 case 6: /* 5.1: Front (Stereo) + Rear (Stereo) + Center/LFE. */
2781 {
2782 fUseRear = true;
2783 fUseCenter = true;
2784 fUseLFE = true;
2785 break;
2786 }
2787
2788 default: /* Unknown; fall back to 2 front channels (stereo). */
2789 {
2790 rc = VERR_NOT_SUPPORTED;
2791 break;
2792 }
2793 }
2794#else /* !VBOX_WITH_AUDIO_HDA_51_SURROUND */
2795 /* Only support mono or stereo channels. */
2796 if ( pCfg->cChannels != 1 /* Mono */
2797 && pCfg->cChannels != 2 /* Stereo */)
2798 {
2799 rc = VERR_NOT_SUPPORTED;
2800 }
2801#endif
2802
2803 if (rc == VERR_NOT_SUPPORTED)
2804 {
2805 LogRel(("HDA: Unsupported channel count (%RU8), falling back to stereo channels\n", pCfg->cChannels));
2806 pCfg->cChannels = 2;
2807
2808 rc = VINF_SUCCESS;
2809 }
2810
2811 do
2812 {
2813 if (RT_FAILURE(rc))
2814 break;
2815
2816 if (fUseFront)
2817 {
2818 RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Front");
2819 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_FRONT;
2820 pCfg->cChannels = 2;
2821
2822 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT);
2823 if (RT_SUCCESS(rc))
2824 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT, pCfg);
2825 }
2826
2827#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2828 if ( RT_SUCCESS(rc)
2829 && (fUseCenter || fUseLFE))
2830 {
2831 RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Center/LFE");
2832 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_CENTER_LFE;
2833 pCfg->cChannels = (fUseCenter && fUseLFE) ? 2 : 1;
2834
2835 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE);
2836 if (RT_SUCCESS(rc))
2837 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE, pCfg);
2838 }
2839
2840 if ( RT_SUCCESS(rc)
2841 && fUseRear)
2842 {
2843 RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Rear");
2844 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_REAR;
2845 pCfg->cChannels = 2;
2846
2847 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR);
2848 if (RT_SUCCESS(rc))
2849 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR, pCfg);
2850 }
2851#endif /* VBOX_WITH_AUDIO_HDA_51_SURROUND */
2852
2853 } while (0);
2854
2855 LogFlowFuncLeaveRC(rc);
2856 return rc;
2857}
2858
2859static int hdaAddStreamIn(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
2860{
2861 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2862 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2863
2864 AssertReturn(pCfg->enmDir == PDMAUDIODIR_IN, VERR_INVALID_PARAMETER);
2865
2866 LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Source));
2867
2868 int rc;
2869
2870 switch (pCfg->DestSource.Source)
2871 {
2872 case PDMAUDIORECSOURCE_LINE:
2873 {
2874 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN);
2875 if (RT_SUCCESS(rc))
2876 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN, pCfg);
2877 break;
2878 }
2879#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2880 case PDMAUDIORECSOURCE_MIC:
2881 {
2882 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN);
2883 if (RT_SUCCESS(rc))
2884 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN, pCfg);
2885 break;
2886 }
2887#endif
2888 default:
2889 rc = VERR_NOT_SUPPORTED;
2890 break;
2891 }
2892
2893 LogFlowFuncLeaveRC(rc);
2894 return rc;
2895}
2896#endif /* IN_RING3 */
2897
2898static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2899{
2900#ifdef IN_RING3
2901 PDMAUDIOSTREAMCFG strmCfg;
2902 RT_ZERO(strmCfg);
2903
2904 int rc = hdaSDFMTToStrmCfg(u32Value, &strmCfg);
2905 if (RT_FAILURE(rc))
2906 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2907
2908 PHDASTREAM pStream = hdaStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FMT, iReg));
2909 if (!pStream)
2910 {
2911 LogFunc(("[SD%RU8]: Warning: Changing SDFMT on non-attached stream (0x%x)\n",
2912 HDA_SD_NUM_FROM_REG(pThis, FMT, iReg), u32Value));
2913 return hdaRegWriteU16(pThis, iReg, u32Value);
2914 }
2915
2916 int rcSem = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
2917 AssertRC(rcSem);
2918
2919 LogFunc(("[SD%RU8]: Hz=%RU32, Channels=%RU8, enmFmt=%RU32\n",
2920 pStream->u8SD, strmCfg.uHz, strmCfg.cChannels, strmCfg.enmFormat));
2921
2922 /* Set audio direction. */
2923 strmCfg.enmDir = hdaGetDirFromSD(pStream->u8SD);
2924 switch (strmCfg.enmDir)
2925 {
2926 case PDMAUDIODIR_IN:
2927# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2928# error "Implement me!"
2929# else
2930 strmCfg.DestSource.Source = PDMAUDIORECSOURCE_LINE;
2931 RTStrCopy(strmCfg.szName, sizeof(strmCfg.szName), "Line In");
2932# endif
2933 break;
2934
2935 case PDMAUDIODIR_OUT:
2936 /* Destination(s) will be set in hdaAddStreamOut(),
2937 * based on the channels / stream layout. */
2938 break;
2939
2940 default:
2941 rc = VERR_NOT_SUPPORTED;
2942 break;
2943 }
2944
2945 /*
2946 * Initialize the stream mapping in any case, regardless if
2947 * we support surround audio or not. This is needed to handle
2948 * the supported channels within a single audio stream, e.g. mono/stereo.
2949 *
2950 * In other words, the stream mapping *always* knowns the real
2951 * number of channels in a single audio stream.
2952 */
2953 if (RT_SUCCESS(rc))
2954 {
2955 rc = hdaStreamMapInit(&pStream->State.Mapping, &strmCfg);
2956 AssertRC(rc);
2957 }
2958
2959 if (RT_SUCCESS(rc))
2960 {
2961 PHDADRIVER pDrv;
2962 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2963 {
2964 int rc2;
2965 switch (strmCfg.enmDir)
2966 {
2967 case PDMAUDIODIR_OUT:
2968 rc2 = hdaAddStreamOut(pThis, &strmCfg);
2969 break;
2970
2971 case PDMAUDIODIR_IN:
2972 rc2 = hdaAddStreamIn(pThis, &strmCfg);
2973 break;
2974
2975 default:
2976 rc2 = VERR_NOT_SUPPORTED;
2977 AssertFailed();
2978 break;
2979 }
2980
2981 if ( RT_FAILURE(rc2)
2982 && (pDrv->Flags & PDMAUDIODRVFLAGS_PRIMARY)) /* We only care about primary drivers here, the rest may fail. */
2983 {
2984 if (RT_SUCCESS(rc))
2985 rc = rc2;
2986 /* Keep going. */
2987 }
2988 }
2989
2990 /* If (re-)opening the stream by the codec above failed, don't write the new
2991 * format to the register so that the guest is aware it didn't work. */
2992 if (RT_SUCCESS(rc))
2993 {
2994 rc = hdaRegWriteU16(pThis, iReg, u32Value);
2995 AssertRC(rc);
2996 }
2997 else
2998 LogFunc(("[SD%RU8]: (Re-)Opening stream failed with rc=%Rrc\n", pStream->u8SD, rc));
2999 }
3000
3001 if (RT_SUCCESS(rcSem))
3002 hdaRegWriteSDUnlock(pStream);
3003
3004 return VINF_SUCCESS; /* Never return failure. */
3005#else /* !IN_RING3 */
3006 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
3007 return VINF_IOM_R3_MMIO_WRITE;
3008#endif
3009}
3010
3011/* Note: Will be called for both, BDPL and BDPU, registers. */
3012DECLINLINE(int) hdaRegWriteSDBDPX(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value, uint8_t u8Strm)
3013{
3014#ifdef IN_RING3
3015 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
3016 return VINF_SUCCESS;
3017
3018 PHDASTREAM pStream = hdaStreamFromSD(pThis, u8Strm);
3019 if (!pStream)
3020 {
3021 LogFunc(("[SD%RU8]: Warning: Changing SDBPL/SDBPU on non-attached stream (0x%x)\n", HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
3022 return hdaRegWriteU32(pThis, iReg, u32Value);
3023 }
3024
3025 int rc2 = hdaRegWriteSDLock(pThis, pStream, iReg, u32Value);
3026 AssertRC(rc2);
3027
3028 rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
3029 AssertRC(rc2);
3030
3031 /* Update BDL base. */
3032 pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, u8Strm),
3033 HDA_STREAM_REG(pThis, BDPU, u8Strm));
3034 /* Reset BDLE state. */
3035 RT_ZERO(pStream->State.BDLE);
3036 pStream->State.uCurBDLE = 0;
3037
3038 LogFlowFunc(("[SD%RU8]: BDLBase=0x%x\n", pStream->u8SD, pStream->u64BDLBase));
3039 hdaRegWriteSDUnlock(pStream);
3040
3041 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
3042#else /* !IN_RING3 */
3043 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value); RT_NOREF_PV(u8Strm);
3044 return VINF_IOM_R3_MMIO_WRITE;
3045#endif /* IN_RING3 */
3046}
3047
3048static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3049{
3050 return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPL, iReg));
3051}
3052
3053static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3054{
3055 return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPU, iReg));
3056}
3057
3058#ifdef IN_RING3
3059/**
3060 * XXX
3061 *
3062 * @return VBox status code. ALL THE CALLERS IGNORES THIS. DUH.
3063 *
3064 * @param pThis Pointer to HDA state.
3065 * @param iReg Register to write (logging only).
3066 * @param u32Value Value to write (logging only).
3067 */
3068DECLINLINE(int) hdaRegWriteSDLock(PHDASTATE pThis, PHDASTREAM pStream, uint32_t iReg, uint32_t u32Value)
3069{
3070 RT_NOREF(pThis, iReg, u32Value);
3071 AssertPtr(pThis); /* don't bother returning errors */
3072 AssertPtr(pStream);
3073
3074# ifdef VBOX_STRICT
3075 /* Check if the SD's RUN bit is set. */
3076 uint32_t u32SDCTL = HDA_STREAM_REG(pThis, CTL, pStream->u8SD);
3077 bool fIsRunning = RT_BOOL(u32SDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
3078 if (fIsRunning)
3079 {
3080 LogFunc(("[SD%RU8]: Warning: Cannot write to register 0x%x (0x%x) when RUN bit is set (%R[sdctl])\n",
3081 pStream->u8SD, iReg, u32Value, u32SDCTL));
3082# ifdef DEBUG_andy
3083 AssertFailed();
3084# endif
3085 return VERR_ACCESS_DENIED;
3086 }
3087# endif
3088
3089 return RTCritSectEnter(&pStream->State.CritSect);
3090}
3091
3092DECLINLINE(void) hdaRegWriteSDUnlock(PHDASTREAM pStream)
3093{
3094 AssertPtrReturnVoid(pStream);
3095
3096 int rc2 = RTCritSectLeave(&pStream->State.CritSect);
3097 AssertRC(rc2);
3098}
3099#endif /* IN_RING3 */
3100
3101static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
3102{
3103 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
3104 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
3105 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
3106 {
3107 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
3108 }
3109
3110 return hdaRegReadU32(pThis, iReg, pu32Value);
3111}
3112
3113static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3114{
3115 RT_NOREF_PV(iReg);
3116
3117 /*
3118 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
3119 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
3120 */
3121 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
3122 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
3123 {
3124#ifdef IN_RING3
3125 uint32_t uCmd = HDA_REG(pThis, IC);
3126
3127 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
3128 {
3129 /*
3130 * 3.4.3: Defines behavior of immediate Command status register.
3131 */
3132 LogRel(("HDA: Guest attempted process immediate verb (%x) with active CORB\n", uCmd));
3133 return VINF_SUCCESS;
3134 }
3135
3136 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
3137
3138 uint64_t uResp;
3139 int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec,
3140 HDA_CODEC_CMD(uCmd, 0 /* LUN */), &uResp);
3141 if (RT_FAILURE(rc2))
3142 LogFunc(("Codec lookup failed with rc2=%Rrc\n", rc2));
3143
3144 HDA_REG(pThis, IR) = (uint32_t)uResp; /** @todo r=andy Do we need a 64-bit response? */
3145 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
3146 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
3147 return VINF_SUCCESS;
3148#else /* !IN_RING3 */
3149 return VINF_IOM_R3_MMIO_WRITE;
3150#endif /* !IN_RING3 */
3151 }
3152
3153 /*
3154 * Once the guest read the response, it should clean the IRV bit of the IRS register.
3155 */
3156 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
3157 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
3158 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
3159 return VINF_SUCCESS;
3160}
3161
3162static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3163{
3164 RT_NOREF_PV(iReg);
3165
3166 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
3167 HDA_REG(pThis, RIRBWP) = 0;
3168
3169 /* The remaining bits are O, see 6.2.22. */
3170 return VINF_SUCCESS;
3171}
3172
3173static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3174{
3175 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
3176 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
3177 if (RT_FAILURE(rc))
3178 AssertRCReturn(rc, rc);
3179
3180 switch(iReg)
3181 {
3182 case HDA_REG_CORBLBASE:
3183 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
3184 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
3185 break;
3186 case HDA_REG_CORBUBASE:
3187 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
3188 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3189 break;
3190 case HDA_REG_RIRBLBASE:
3191 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
3192 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
3193 break;
3194 case HDA_REG_RIRBUBASE:
3195 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
3196 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3197 break;
3198 case HDA_REG_DPLBASE:
3199 {
3200 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
3201 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
3202
3203 /* Also make sure to handle the DMA position enable bit. */
3204 pThis->fDMAPosition = RT_BOOL(pThis->u64DPBase & RT_BIT_64(0));
3205 LogRel2(("HDA: %s DMA position buffer\n", pThis->fDMAPosition ? "Enabled" : "Disabled"));
3206 break;
3207 }
3208 case HDA_REG_DPUBASE:
3209 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
3210 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3211 break;
3212 default:
3213 AssertMsgFailed(("Invalid index\n"));
3214 break;
3215 }
3216
3217 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
3218 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
3219 return rc;
3220}
3221
3222static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3223{
3224 RT_NOREF_PV(iReg);
3225
3226 uint8_t v = HDA_REG(pThis, RIRBSTS);
3227 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
3228
3229 return hdaProcessInterrupt(pThis);
3230}
3231
3232#ifdef IN_RING3
3233#ifdef LOG_ENABLED
3234static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BDLBase, uint16_t cBDLE)
3235{
3236 LogFlowFunc(("BDLEs @ 0x%x (%RU16):\n", u64BDLBase, cBDLE));
3237 if (!u64BDLBase)
3238 return;
3239
3240 uint32_t cbBDLE = 0;
3241 for (uint16_t i = 0; i < cBDLE; i++)
3242 {
3243 HDABDLEDESC bd;
3244 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BDLBase + i * sizeof(HDABDLEDESC), &bd, sizeof(bd));
3245
3246 LogFunc(("\t#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
3247 i, bd.u64BufAdr, bd.u32BufSize, bd.fFlags & HDA_BDLE_FLAG_IOC));
3248
3249 cbBDLE += bd.u32BufSize;
3250 }
3251
3252 LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
3253
3254 if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
3255 return;
3256
3257 LogFlowFunc(("DMA counters:\n"));
3258
3259 for (int i = 0; i < cBDLE; i++)
3260 {
3261 uint32_t uDMACnt;
3262 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
3263 &uDMACnt, sizeof(uDMACnt));
3264
3265 LogFlowFunc(("\t#%03d DMA @ 0x%x\n", i , uDMACnt));
3266 }
3267}
3268#endif
3269
3270/**
3271 * Fetches a Bundle Descriptor List Entry (BDLE) from the DMA engine.
3272 *
3273 * @param pThis Pointer to HDA state.
3274 * @param pBDLE Where to store the fetched result.
3275 * @param u64BaseDMA Address base of DMA engine to use.
3276 * @param u16Entry BDLE entry to fetch.
3277 */
3278static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry)
3279{
3280 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3281 AssertPtrReturn(pBDLE, VERR_INVALID_POINTER);
3282 AssertReturn(u64BaseDMA, VERR_INVALID_PARAMETER);
3283
3284 if (!u64BaseDMA)
3285 {
3286 LogRel2(("HDA: Unable to fetch BDLE #%RU16 - no base DMA address set (yet)\n", u16Entry));
3287 return VERR_NOT_FOUND;
3288 }
3289 /** @todo Compare u16Entry with LVI. */
3290
3291 int rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + u16Entry * sizeof(HDABDLEDESC),
3292 &pBDLE->Desc, sizeof(pBDLE->Desc));
3293 if (RT_FAILURE(rc))
3294 return rc;
3295
3296 /* Set internal state. */
3297 pBDLE->State.u32BufOff = 0;
3298 pBDLE->State.u32BDLIndex = u16Entry;
3299
3300 return VINF_SUCCESS;
3301}
3302
3303/**
3304 * Returns the number of outstanding stream data bytes which need to be processed
3305 * by the DMA engine assigned to this stream.
3306 *
3307 * @return Number of bytes for the DMA engine to process.
3308 */
3309DECLINLINE(uint32_t) hdaStreamGetTransferSize(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbMax)
3310{
3311 AssertPtrReturn(pThis, 0);
3312 AssertPtrReturn(pStream, 0);
3313 AssertReturn (cbMax, 0);
3314
3315 PHDABDLE pBDLE = &pStream->State.BDLE;
3316
3317 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3318 Assert(u32LPIB <= pStream->u32CBL);
3319
3320 /* Do we have space left in the CBL at all? */
3321 uint32_t cbData = pStream->u32CBL - u32LPIB;
3322
3323 /* Limit to the available free space of the current BDLE. */
3324 cbData = RT_MIN(cbData, pBDLE->Desc.u32BufSize - pBDLE->State.u32BufOff);
3325
3326 /* Make sure we only transfer as many bytes as requested. */
3327 cbData = RT_MIN(cbData, cbMax);
3328
3329 if (pBDLE->State.cbBelowFIFOW)
3330 {
3331 /* Are we not going to reach (or exceed) the FIFO watermark yet with the data to copy?
3332 * No need to read data from DMA then. */
3333 if (cbData > pBDLE->State.cbBelowFIFOW)
3334 {
3335 /* Subtract the amount of bytes that still would fit in the stream's FIFO
3336 * and therefore do not need to be processed by DMA. */
3337 cbData -= pBDLE->State.cbBelowFIFOW;
3338 }
3339 }
3340
3341 AssertMsg((cbData % 2 == 0), ("Transfer size invalid: %RU32\n", cbData));
3342
3343 Log3Func(("[SD%RU8]: CBL=%RU32, LPIB=%RU32, FIFOS=%RU16, cbData=%RU32, %R[bdle]\n", pStream->u8SD,
3344 pStream->u32CBL, HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), pStream->u16FIFOS,
3345 cbData, pBDLE));
3346
3347 return cbData;
3348}
3349
3350DECLINLINE(void) hdaBDLEUpdate(PHDABDLE pBDLE, uint32_t cbData, uint32_t cbProcessed)
3351{
3352 AssertPtrReturnVoid(pBDLE);
3353
3354 if (!cbData || !cbProcessed)
3355 return;
3356
3357 Assert(pBDLE->Desc.u32BufSize >= cbProcessed);
3358
3359 /* Fewer than cbBelowFIFOW bytes were copied.
3360 * Probably we need to move the buffer, but it is rather hard to imagine a situation
3361 * where it might happen. */
3362 AssertMsg((cbProcessed == pBDLE->State.cbBelowFIFOW + cbData), /* we assume that we write the entire buffer including unreported bytes */
3363 ("cbProcessed=%RU32 != pBDLE->State.cbBelowFIFOW=%RU32 + cbData=%RU32\n",
3364 cbProcessed, pBDLE->State.cbBelowFIFOW, cbData));
3365
3366#if 0
3367 if ( pBDLE->State.cbBelowFIFOW
3368 && pBDLE->State.cbBelowFIFOW <= cbWritten)
3369 {
3370 LogFlowFunc(("BDLE(cbUnderFifoW:%RU32, off:%RU32, size:%RU32)\n",
3371 pBDLE->State.cbBelowFIFOW, pBDLE->State.u32BufOff, pBDLE->Desc.u32BufSize));
3372 }
3373#endif
3374
3375 pBDLE->State.cbBelowFIFOW -= RT_MIN(pBDLE->State.cbBelowFIFOW, cbProcessed);
3376 Assert(pBDLE->State.cbBelowFIFOW == 0);
3377
3378 /* We always increment the position of DMA buffer counter because we're always reading
3379 * into an intermediate buffer. */
3380 Assert(pBDLE->Desc.u32BufSize >= (pBDLE->State.u32BufOff + cbProcessed));
3381 pBDLE->State.u32BufOff += cbProcessed;
3382
3383 LogFlowFunc(("cbData=%RU32, cbProcessed=%RU32, %R[bdle]\n", cbData, cbProcessed, pBDLE));
3384}
3385
3386#ifdef IN_RING3
3387/**
3388 * Initializes a stream mapping structure according to the given stream configuration.
3389 *
3390 * @return IPRT status code.
3391 * @param pMapping Pointer to mapping to initialize.
3392 * @param pCfg Pointer to stream configuration to use.
3393 */
3394static int hdaStreamMapInit(PHDASTREAMMAPPING pMapping, PPDMAUDIOSTREAMCFG pCfg)
3395{
3396 AssertPtrReturn(pMapping, VERR_INVALID_POINTER);
3397 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3398
3399 AssertReturn(pCfg->cChannels, VERR_INVALID_PARAMETER);
3400
3401 hdaStreamMapReset(pMapping);
3402
3403 pMapping->paChannels = (PPDMAUDIOSTREAMCHANNEL)RTMemAlloc(sizeof(PDMAUDIOSTREAMCHANNEL) * pCfg->cChannels);
3404 if (!pMapping->paChannels)
3405 return VERR_NO_MEMORY;
3406
3407 PDMAUDIOPCMPROPS Props;
3408 int rc = DrvAudioHlpStreamCfgToProps(pCfg, &Props);
3409 if (RT_FAILURE(rc))
3410 return rc;
3411
3412 Assert(RT_IS_POWER_OF_TWO(Props.cBits));
3413
3414 /** @todo We assume all channels in a stream have the same format. */
3415 PPDMAUDIOSTREAMCHANNEL pChan = pMapping->paChannels;
3416 for (uint8_t i = 0; i < pCfg->cChannels; i++)
3417 {
3418 pChan->uChannel = i;
3419 pChan->cbStep = (Props.cBits / 2);
3420 pChan->cbFrame = pChan->cbStep * pCfg->cChannels;
3421 pChan->cbFirst = i * pChan->cbStep;
3422 pChan->cbOff = pChan->cbFirst;
3423
3424 int rc2 = hdaStreamChannelDataInit(&pChan->Data, PDMAUDIOSTREAMCHANNELDATA_FLAG_NONE);
3425 if (RT_SUCCESS(rc))
3426 rc = rc2;
3427
3428 if (RT_FAILURE(rc))
3429 break;
3430
3431 pChan++;
3432 }
3433
3434 if ( RT_SUCCESS(rc)
3435 /* Create circular buffer if not created yet. */
3436 && !pMapping->pCircBuf)
3437 {
3438 rc = RTCircBufCreate(&pMapping->pCircBuf, _4K); /** @todo Make size configurable? */
3439 }
3440
3441 if (RT_SUCCESS(rc))
3442 {
3443 pMapping->cChannels = pCfg->cChannels;
3444#ifdef VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT
3445 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_INTERLEAVED;
3446#else
3447 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
3448#endif
3449 }
3450
3451 return rc;
3452}
3453
3454/**
3455 * Destroys a given stream mapping.
3456 *
3457 * @param pMapping Pointer to mapping to destroy.
3458 */
3459static void hdaStreamMapDestroy(PHDASTREAMMAPPING pMapping)
3460{
3461 hdaStreamMapReset(pMapping);
3462
3463 if (pMapping->pCircBuf)
3464 {
3465 RTCircBufDestroy(pMapping->pCircBuf);
3466 pMapping->pCircBuf = NULL;
3467 }
3468}
3469
3470/**
3471 * Resets a given stream mapping.
3472 *
3473 * @param pMapping Pointer to mapping to reset.
3474 */
3475static void hdaStreamMapReset(PHDASTREAMMAPPING pMapping)
3476{
3477 AssertPtrReturnVoid(pMapping);
3478
3479 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_UNKNOWN;
3480
3481 if (pMapping->cChannels)
3482 {
3483 for (uint8_t i = 0; i < pMapping->cChannels; i++)
3484 hdaStreamChannelDataDestroy(&pMapping->paChannels[i].Data);
3485
3486 AssertPtr(pMapping->paChannels);
3487 RTMemFree(pMapping->paChannels);
3488 pMapping->paChannels = NULL;
3489
3490 pMapping->cChannels = 0;
3491 }
3492}
3493#endif /* IN_RING3 */
3494
3495DECLINLINE(bool) hdaStreamNeedsNextBDLE(PHDASTATE pThis, PHDASTREAM pStream)
3496{
3497 AssertPtrReturn(pThis, false);
3498 AssertPtrReturn(pStream, false);
3499
3500 PHDABDLE pBDLE = &pStream->State.BDLE;
3501 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3502
3503 /* Did we reach the CBL (Cyclic Buffer List) limit? */
3504 bool fCBLLimitReached = u32LPIB >= pStream->u32CBL;
3505
3506 /* Do we need to use the next BDLE entry? Either because we reached
3507 * the CBL limit or our internal DMA buffer is full. */
3508 bool fNeedsNextBDLE = ( fCBLLimitReached
3509 || (pBDLE->State.u32BufOff >= pBDLE->Desc.u32BufSize));
3510
3511 Assert(u32LPIB <= pStream->u32CBL);
3512 Assert(pBDLE->State.u32BufOff <= pBDLE->Desc.u32BufSize);
3513
3514 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32, fCBLLimitReached=%RTbool, fNeedsNextBDLE=%RTbool, %R[bdle]\n",
3515 pStream->u8SD, u32LPIB, pStream->u32CBL, fCBLLimitReached, fNeedsNextBDLE, pBDLE));
3516
3517 return fNeedsNextBDLE;
3518}
3519
3520DECLINLINE(void) hdaStreamTransferUpdate(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbInc)
3521{
3522 AssertPtrReturnVoid(pThis);
3523 AssertPtrReturnVoid(pStream);
3524
3525 if (!cbInc) /* Nothing to do? Bail out early. */
3526 return;
3527
3528 /*
3529 * If we're below the FIFO watermark (SDFIFOW), it's expected that HDA
3530 * doesn't fetch anything via DMA, so just update LPIB.
3531 * (ICH6 datasheet 18.2.38).
3532 */
3533 PHDABDLE pBDLE = &pStream->State.BDLE;
3534 if (pBDLE->State.cbBelowFIFOW == 0) /* Did we hit (or exceed) the watermark? */
3535 {
3536 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) + cbInc;
3537
3538 Log3Func(("[SD%RU8]: LPIB: %RU32 -> %RU32, CBL=%RU32\n",
3539 pStream->u8SD, HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), u32LPIB, pStream->u32CBL));
3540
3541 hdaStreamUpdateLPIB(pThis, pStream, u32LPIB);
3542 }
3543}
3544
3545static bool hdaBDLEIsComplete(PHDABDLE pBDLE, bool *pfInterrupt)
3546{
3547 AssertPtrReturn(pBDLE, true);
3548
3549 bool fInterrupt = false;
3550 bool fIsComplete = false;
3551
3552 /* Check if the current BDLE entry is complete (full). */
3553 if (pBDLE->State.u32BufOff >= pBDLE->Desc.u32BufSize)
3554 {
3555 Assert(pBDLE->State.u32BufOff <= pBDLE->Desc.u32BufSize);
3556
3557 if (/* IOC (Interrupt On Completion) bit set? */
3558 pBDLE->Desc.fFlags & HDA_BDLE_FLAG_IOC
3559 /* All data put into the DMA FIFO? */
3560 && pBDLE->State.cbBelowFIFOW == 0
3561 )
3562 {
3563 fInterrupt = true;
3564 }
3565
3566 fIsComplete = true;
3567 }
3568
3569 if (pfInterrupt)
3570 *pfInterrupt = fInterrupt;
3571
3572 LogFlowFunc(("%R[bdle] fIsComplete=%RTbool, fInterrupt=%RTbool\n", pBDLE, fIsComplete, fInterrupt));
3573
3574 return fIsComplete;
3575}
3576
3577/**
3578 * Retrieves a corresponding sink for a given mixer control.
3579 * Returns NULL if no sink is found.
3580 *
3581 * @return PHDAMIXERSINK
3582 * @param pThis HDA state.
3583 * @param enmMixerCtl Mixer control to get the corresponding sink for.
3584 */
3585static PHDAMIXERSINK hdaMixerControlToSink(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
3586{
3587 PHDAMIXERSINK pSink;
3588
3589 switch (enmMixerCtl)
3590 {
3591 case PDMAUDIOMIXERCTL_VOLUME_MASTER:
3592 /* Fall through is intentional. */
3593 case PDMAUDIOMIXERCTL_FRONT:
3594 pSink = &pThis->SinkFront;
3595 break;
3596#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3597 case PDMAUDIOMIXERCTL_CENTER_LFE:
3598 pSink = &pThis->SinkCenterLFE;
3599 break;
3600 case PDMAUDIOMIXERCTL_REAR:
3601 pSink = &pThis->SinkRear;
3602 break;
3603#endif
3604 case PDMAUDIOMIXERCTL_LINE_IN:
3605 pSink = &pThis->SinkLineIn;
3606 break;
3607#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3608 case PDMAUDIOMIXERCTL_MIC_IN:
3609 pSink = &pThis->SinkMicIn;
3610 break;
3611#endif
3612 default:
3613 pSink = NULL;
3614 AssertMsgFailed(("Unhandled mixer control\n"));
3615 break;
3616 }
3617
3618 return pSink;
3619}
3620
3621static DECLCALLBACK(int) hdaMixerAddStream(PHDASTATE pThis, PHDAMIXERSINK pSink, PPDMAUDIOSTREAMCFG pCfg)
3622{
3623 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3624 AssertPtrReturn(pSink, VERR_INVALID_POINTER);
3625 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3626
3627 LogFunc(("Sink=%s, Stream=%s\n", pSink->pMixSink->pszName, pCfg->szName));
3628
3629 /* Update the sink's format. */
3630 PDMAUDIOPCMPROPS PCMProps;
3631 int rc = DrvAudioHlpStreamCfgToProps(pCfg, &PCMProps);
3632 if (RT_SUCCESS(rc))
3633 rc = AudioMixerSinkSetFormat(pSink->pMixSink, &PCMProps);
3634
3635 if (RT_FAILURE(rc))
3636 return rc;
3637
3638 PHDADRIVER pDrv;
3639 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3640 {
3641 int rc2 = VINF_SUCCESS;
3642 PHDADRIVERSTREAM pDrvStream = NULL;
3643
3644 PPDMAUDIOSTREAMCFG pStreamCfg = (PPDMAUDIOSTREAMCFG)RTMemDup(pCfg, sizeof(PDMAUDIOSTREAMCFG));
3645 if (!pStreamCfg)
3646 {
3647 rc = VERR_NO_MEMORY;
3648 break;
3649 }
3650
3651 /* Include the driver's LUN in the stream name for easier identification. */
3652 RTStrPrintf(pStreamCfg->szName, RT_ELEMENTS(pStreamCfg->szName), "[LUN#%RU8] %s", pDrv->uLUN, pCfg->szName);
3653
3654 if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
3655 {
3656 LogFunc(("enmRecSource=%d\n", pStreamCfg->DestSource.Source));
3657
3658 switch (pStreamCfg->DestSource.Source)
3659 {
3660 case PDMAUDIORECSOURCE_LINE:
3661 pDrvStream = &pDrv->LineIn;
3662 break;
3663#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3664 case PDMAUDIORECSOURCE_MIC:
3665 pDrvStream = &pDrv->MicIn;
3666 break;
3667#endif
3668 default:
3669 rc2 = VERR_NOT_SUPPORTED;
3670 break;
3671 }
3672 }
3673 else if (pStreamCfg->enmDir == PDMAUDIODIR_OUT)
3674 {
3675 LogFunc(("enmPlaybackDest=%d\n", pStreamCfg->DestSource.Dest));
3676
3677 switch (pStreamCfg->DestSource.Dest)
3678 {
3679 case PDMAUDIOPLAYBACKDEST_FRONT:
3680 pDrvStream = &pDrv->Front;
3681 break;
3682#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3683 case PDMAUDIOPLAYBACKDEST_CENTER_LFE:
3684 pDrvStream = &pDrv->CenterLFE;
3685 break;
3686 case PDMAUDIOPLAYBACKDEST_REAR:
3687 pDrvStream = &pDrv->Rear;
3688 break;
3689#endif
3690 default:
3691 rc2 = VERR_NOT_SUPPORTED;
3692 break;
3693 }
3694 }
3695 else
3696 rc2 = VERR_NOT_SUPPORTED;
3697
3698 if (RT_SUCCESS(rc2))
3699 {
3700 AssertPtr(pDrvStream);
3701
3702 AudioMixerSinkRemoveStream(pSink->pMixSink, pDrvStream->pMixStrm);
3703
3704 AudioMixerStreamDestroy(pDrvStream->pMixStrm);
3705 pDrvStream->pMixStrm = NULL;
3706
3707 PAUDMIXSTREAM pMixStrm;
3708 rc2 = AudioMixerSinkCreateStream(pSink->pMixSink, pDrv->pConnector, pStreamCfg, 0 /* fFlags */, &pMixStrm);
3709 if (RT_SUCCESS(rc2))
3710 {
3711 rc2 = AudioMixerSinkAddStream(pSink->pMixSink, pMixStrm);
3712 LogFlowFunc(("LUN#%RU8: Added \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName , rc2));
3713 }
3714
3715 if (RT_SUCCESS(rc2))
3716 pDrvStream->pMixStrm = pMixStrm;
3717 }
3718
3719 if (RT_SUCCESS(rc))
3720 rc = rc2;
3721
3722 if (pStreamCfg)
3723 {
3724 RTMemFree(pStreamCfg);
3725 pStreamCfg = NULL;
3726 }
3727 }
3728
3729 LogFlowFuncLeaveRC(rc);
3730 return rc;
3731}
3732
3733/**
3734 * Adds a new audio stream to a specific mixer control.
3735 * Depending on the mixer control the stream then gets assigned to one of the internal
3736 * mixer sinks, which in turn then handle the mixing of all connected streams to that sink.
3737 *
3738 * @return IPRT status code.
3739 * @param pThis HDA state.
3740 * @param enmMixerCtl Mixer control to assign new stream to.
3741 * @param pCfg Stream configuration for the new stream.
3742 */
3743static DECLCALLBACK(int) hdaMixerAddStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOSTREAMCFG pCfg)
3744{
3745 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3746 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3747
3748 int rc;
3749
3750 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3751 if (pSink)
3752 {
3753 rc = hdaMixerAddStream(pThis, pSink, pCfg);
3754
3755 AssertPtr(pSink->pMixSink);
3756 LogFlowFunc(("Sink=%s, enmMixerCtl=%d\n", pSink->pMixSink->pszName, enmMixerCtl));
3757 }
3758 else
3759 rc = VERR_NOT_FOUND;
3760
3761 LogFlowFuncLeaveRC(rc);
3762 return rc;
3763}
3764
3765/**
3766 * Removes a specified mixer control from the HDA's mixer.
3767 *
3768 * @return IPRT status code.
3769 * @param pThis HDA state.
3770 * @param enmMixerCtl Mixer control to remove.
3771 */
3772static DECLCALLBACK(int) hdaMixerRemoveStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
3773{
3774 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3775
3776 int rc;
3777
3778 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3779 if (pSink)
3780 {
3781 PHDADRIVER pDrv;
3782 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3783 {
3784 PAUDMIXSTREAM pMixStream = NULL;
3785 switch (enmMixerCtl)
3786 {
3787 /*
3788 * Input.
3789 */
3790 case PDMAUDIOMIXERCTL_LINE_IN:
3791 pMixStream = pDrv->LineIn.pMixStrm;
3792 pDrv->LineIn.pMixStrm = NULL;
3793 break;
3794#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3795 case PDMAUDIOMIXERCTL_MIC_IN:
3796 pMixStream = pDrv->MicIn.pMixStrm;
3797 pDrv->MicIn.pMixStrm = NULL;
3798 break;
3799#endif
3800 /*
3801 * Output.
3802 */
3803 case PDMAUDIOMIXERCTL_FRONT:
3804 pMixStream = pDrv->Front.pMixStrm;
3805 pDrv->Front.pMixStrm = NULL;
3806 break;
3807#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3808 case PDMAUDIOMIXERCTL_CENTER_LFE:
3809 pMixStream = pDrv->CenterLFE.pMixStrm;
3810 pDrv->CenterLFE.pMixStrm = NULL;
3811 break;
3812 case PDMAUDIOMIXERCTL_REAR:
3813 pMixStream = pDrv->Rear.pMixStrm;
3814 pDrv->Rear.pMixStrm = NULL;
3815 break;
3816#endif
3817 default:
3818 AssertMsgFailed(("Mixer control %d not implemented\n", enmMixerCtl));
3819 break;
3820 }
3821
3822 if (pMixStream)
3823 {
3824 AudioMixerSinkRemoveStream(pSink->pMixSink, pMixStream);
3825 AudioMixerStreamDestroy(pMixStream);
3826
3827 pMixStream = NULL;
3828 }
3829 }
3830
3831 AudioMixerSinkRemoveAllStreams(pSink->pMixSink);
3832 rc = VINF_SUCCESS;
3833 }
3834 else
3835 rc = VERR_NOT_FOUND;
3836
3837 LogFlowFunc(("enmMixerCtl=%d, rc=%Rrc\n", enmMixerCtl, rc));
3838 return rc;
3839}
3840
3841/**
3842 * Sets a SDn stream number and channel to a particular mixer control.
3843 *
3844 * @returns IPRT status code.
3845 * @param pThis HDA State.
3846 * @param enmMixerCtl Mixer control to set SD stream number and channel for.
3847 * @param uSD SD stream number (number + 1) to set. Set to 0 for unassign.
3848 * @param uChannel Channel to set. Only valid if a valid SD stream number is specified.
3849 */
3850static DECLCALLBACK(int) hdaMixerSetStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, uint8_t uSD, uint8_t uChannel)
3851{
3852 LogFlowFunc(("enmMixerCtl=%RU32, uSD=%RU8, uChannel=%RU8\n", enmMixerCtl, uSD, uChannel));
3853
3854 if (uSD == 0) /* Stream number 0 is reserved. */
3855 {
3856 LogFlowFunc(("Invalid SDn (%RU8) number for mixer control %d, ignoring\n", uSD, enmMixerCtl));
3857 return VINF_SUCCESS;
3858 }
3859 /* uChannel is optional. */
3860
3861 /* SDn0 starts as 1. */
3862 Assert(uSD);
3863 uSD--;
3864
3865 int rc;
3866
3867 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3868 if (pSink)
3869 {
3870 if ( (uSD < HDA_MAX_SDI)
3871 && AudioMixerSinkGetDir(pSink->pMixSink) == AUDMIXSINKDIR_OUTPUT)
3872 {
3873 uSD += HDA_MAX_SDI;
3874 }
3875
3876 LogFlowFunc(("%s: Setting to stream ID=%RU8, channel=%RU8, enmMixerCtl=%RU32\n",
3877 pSink->pMixSink->pszName, uSD, uChannel, enmMixerCtl));
3878
3879 Assert(uSD < HDA_MAX_STREAMS);
3880
3881 PHDASTREAM pStream = hdaStreamFromSD(pThis, uSD);
3882 if (pStream)
3883 {
3884 pSink->uSD = uSD;
3885 pSink->uChannel = uChannel;
3886
3887 /* Make sure that the stream also has this sink set. */
3888 hdaStreamAssignToSink(pStream, pSink);
3889
3890 rc = VINF_SUCCESS;
3891 }
3892 else
3893 {
3894 LogRel(("HDA: Guest wanted to assign invalid stream ID=%RU8 (channel %RU8) to mixer control %RU32, skipping\n",
3895 uSD, uChannel, enmMixerCtl));
3896 rc = VERR_INVALID_PARAMETER;
3897 }
3898 }
3899 else
3900 rc = VERR_NOT_FOUND;
3901
3902 LogFlowFuncLeaveRC(rc);
3903 return rc;
3904}
3905
3906/**
3907 * Sets the volume of a specified mixer control.
3908 *
3909 * @return IPRT status code.
3910 * @param pThis HDA State.
3911 * @param enmMixerCtl Mixer control to set volume for.
3912 * @param pVol Pointer to volume data to set.
3913 */
3914static DECLCALLBACK(int) hdaMixerSetVolume(PHDASTATE pThis,
3915 PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOVOLUME pVol)
3916{
3917 int rc;
3918
3919 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3920 if (pSink)
3921 {
3922 /* Set the volume.
3923 * We assume that the codec already converted it to the correct range. */
3924 rc = AudioMixerSinkSetVolume(pSink->pMixSink, pVol);
3925 }
3926 else
3927 rc = VERR_NOT_FOUND;
3928
3929 LogFlowFuncLeaveRC(rc);
3930 return rc;
3931}
3932
3933#ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
3934static void hdaTimerMaybeStart(PHDASTATE pThis)
3935{
3936 LogFlowFuncEnter();
3937
3938 if (!pThis->pTimer)
3939 return;
3940
3941 pThis->cStreamsActive++;
3942
3943 /* Only start the timer at the first active stream. */
3944 if (pThis->cStreamsActive == 1)
3945 {
3946 LogRel2(("HDA: Starting transfers\n"));
3947
3948 /* Set timer flag. */
3949 ASMAtomicXchgBool(&pThis->fTimerActive, true);
3950
3951 /* Update current time timestamp. */
3952 pThis->uTimerTS = TMTimerGet(pThis->pTimer);
3953
3954 /* Start transfers. */
3955 hdaDoTransfers(pThis);
3956 }
3957}
3958
3959static void hdaTimerStop(PHDASTATE pThis)
3960{
3961 LogFlowFuncEnter();
3962
3963 /* Set timer flag. */
3964 ASMAtomicXchgBool(&pThis->fTimerActive, false);
3965}
3966
3967static void hdaTimerMaybeStop(PHDASTATE pThis)
3968{
3969 LogFlowFuncEnter();
3970
3971 if (!pThis->pTimer)
3972 return;
3973
3974 if (pThis->cStreamsActive) /* Disable can be called mupltiple times. */
3975 pThis->cStreamsActive--;
3976
3977 if (pThis->cStreamsActive == 0)
3978 hdaTimerStop(pThis);
3979}
3980
3981static void hdaDoTransfers(PHDASTATE pThis)
3982{
3983 AssertPtrReturnVoid(pThis);
3984
3985 STAM_PROFILE_START(&pThis->StatTimer, a);
3986
3987 uint64_t cTicksNow = TMTimerGet(pThis->pTimer);
3988
3989 Log4Func(("Timer enter\n"));
3990
3991 /* Update current time timestamp. */
3992 pThis->uTimerTS = cTicksNow;
3993
3994 /* Flag indicating whether to kick the timer again for a
3995 * new data processing round. */
3996 bool fKickTimer = false;
3997
3998 PHDASTREAM pStreamLineIn = hdaSinkGetStream(pThis, &pThis->SinkLineIn);
3999#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
4000 PHDASTREAM pStreamMicIn = hdaSinkGetStream(pThis, &pThis->SinkMicIn);
4001#endif
4002 PHDASTREAM pStreamFront = hdaSinkGetStream(pThis, &pThis->SinkFront);
4003#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
4004 /** @todo See note below. */
4005#endif
4006
4007 hdaStreamUpdate(pThis, pStreamLineIn);
4008#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
4009 hdaStreamUpdate(pThis, pStreamMicIn);
4010#endif
4011 hdaStreamUpdate(pThis, pStreamFront);
4012
4013
4014#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
4015 int rc2 = AudioMixerSinkUpdate(pThis->SinkCenterLFE.pMixSink);
4016 AssertRC(rc2);
4017
4018 rc2 = AudioMixerSinkUpdate(pThis->SinkRear.pMixSink);
4019 AssertRC(rc2);
4020 /** @todo Check for stream interleaving and only call hdaStreamDoDMA() if required! */
4021
4022 /*
4023 * Only call hdaTransfer if CenterLFE and/or Rear are on different SDs,
4024 * otherwise we have to use the interleaved streams support for getting the data
4025 * out of the Front sink (depending on the mapping layout).
4026 */
4027#endif
4028
4029 /* Do we need to kick the timer again? */
4030 if ( AudioMixerSinkIsActive(pThis->SinkFront.pMixSink)
4031#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
4032 || AudioMixerSinkIsActive(pThis->SinkCenterLFE.pMixSink)
4033 || AudioMixerSinkIsActive(pThis->SinkRear.pMixSink)
4034#endif
4035 || AudioMixerSinkIsActive(pThis->SinkLineIn.pMixSink)
4036#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
4037 || AudioMixerSinkIsActive(pThis->SinkMicIn.pMixSink)
4038#endif
4039 )
4040 {
4041 fKickTimer = true;
4042 }
4043
4044 pThis->uTimerMS = RTTimeMilliTS();
4045
4046 if ( ASMAtomicReadBool(&pThis->fTimerActive)
4047 || fKickTimer)
4048 {
4049 /* Kick the timer again. */
4050 uint64_t cTicks = pThis->cTimerTicks;
4051 /** @todo adjust cTicks down by now much cbOutMin represents. */
4052 TMTimerSet(pThis->pTimer, cTicksNow + cTicks);
4053 }
4054 else
4055 LogRel2(("HDA: Stopping transfers\n"));
4056
4057 STAM_PROFILE_STOP(&pThis->StatTimer, a);
4058}
4059
4060static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
4061{
4062 RT_NOREF(pDevIns, pTimer);
4063
4064 PHDASTATE pThis = (PHDASTATE)pvUser;
4065 Assert(pThis == PDMINS_2_DATA(pDevIns, PHDASTATE));
4066 AssertPtr(pThis);
4067
4068 hdaDoTransfers(pThis);
4069}
4070
4071#else /* VBOX_WITH_AUDIO_HDA_CALLBACKS */
4072
4073static DECLCALLBACK(int) hdaCallbackInput(PDMAUDIOCBTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
4074{
4075 Assert(enmType == PDMAUDIOCALLBACKTYPE_INPUT);
4076 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
4077 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
4078 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
4079 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
4080
4081 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
4082 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
4083
4084 PPDMAUDIOCBDATA_DATA_INPUT pData = (PPDMAUDIOCBDATA_DATA_INPUT)pvUser;
4085 AssertReturn(cbUser == sizeof(PDMAUDIOCBDATA_DATA_INPUT), VERR_INVALID_PARAMETER);
4086
4087 return hdaStreamDoDMA(pCtx->pThis, PI_INDEX, UINT32_MAX, &pData->cbOutRead);
4088}
4089
4090static DECLCALLBACK(int) hdaCallbackOutput(PDMAUDIOCBTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
4091{
4092 Assert(enmType == PDMAUDIOCALLBACKTYPE_OUTPUT);
4093 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
4094 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
4095 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
4096 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
4097
4098 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
4099 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
4100
4101 PPDMAUDIOCBDATA_DATA_OUTPUT pData = (PPDMAUDIOCBDATA_DATA_OUTPUT)pvUser;
4102 AssertReturn(cbUser == sizeof(PDMAUDIOCBDATA_DATA_OUTPUT), VERR_INVALID_PARAMETER);
4103
4104 PHDASTATE pThis = pCtx->pThis;
4105
4106 int rc = hdaStreamDoDMA(pCtx->pThis, PO_INDEX, UINT32_MAX, &pData->cbOutWritten);
4107 if ( RT_SUCCESS(rc)
4108 && pData->cbOutWritten)
4109 {
4110 PHDADRIVER pDrv;
4111 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
4112 {
4113 uint32_t cSamplesPlayed;
4114 int rc2 = pDrv->pConnector->pfnPlay(pDrv->pConnector, &cSamplesPlayed);
4115 LogFlowFunc(("LUN#%RU8: cSamplesPlayed=%RU32, rc=%Rrc\n", pDrv->uLUN, cSamplesPlayed, rc2));
4116 }
4117 }
4118}
4119#endif /* VBOX_WITH_AUDIO_HDA_CALLBACKS */
4120
4121#ifdef DEBUG_andy
4122# define HDA_DEBUG_DMA
4123#endif
4124
4125/**
4126 * Does a single DMA transfer for a specific HDA stream (SDI/SDO).
4127 * This either can be a read or write operation, depending on the HDA stream.
4128 *
4129 * @returns IPRT status code.
4130 * @param pThis HDA state.
4131 * @param pStream HDA stream to do the DMA transfer for.
4132 * @param pvBuf Pointer to buffer data to write data to / read data from.
4133 * @param cbBuf Size of buffer (in bytes).
4134 * @param cbToProcess Size (in bytes) to transfer (read/write).
4135 * @param pcbProcessed Size (in bytes) transferred (read/written). Optional.
4136 */
4137static int hdaStreamDoDMA(PHDASTATE pThis, PHDASTREAM pStream, void *pvBuf, uint32_t cbBuf,
4138 uint32_t cbToProcess, uint32_t *pcbProcessed)
4139{
4140 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
4141 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
4142 AssertPtrReturn(pvBuf, VERR_INVALID_POINTER);
4143 AssertReturn(cbBuf >= cbToProcess, VERR_INVALID_PARAMETER);
4144 /* pcbProcessed is optional. */
4145
4146 if (ASMAtomicReadBool(&pThis->fInReset)) /* HDA controller in reset mode? Bail out. */
4147 {
4148 if (pcbProcessed)
4149 *pcbProcessed = 0;
4150 return VINF_SUCCESS;
4151 }
4152
4153 bool fProceed = true;
4154
4155 Log3Func(("[SD%RU8] %R[sdsts] cbToProcess=%RU32\n",
4156 pStream->u8SD, HDA_STREAM_REG(pThis, STS, pStream->u8SD), cbToProcess));
4157
4158 /* Is the stream not in a running state currently? */
4159 if (!(HDA_STREAM_REG(pThis, CTL, pStream->u8SD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)))
4160 fProceed = false;
4161 /* Is the BCIS (Buffer Completion Interrupt Status) flag set? Then we have to wait and skip. */
4162 else if ((HDA_STREAM_REG(pThis, STS, pStream->u8SD) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
4163 fProceed = false;
4164
4165 if (!fProceed)
4166 {
4167#ifdef HDA_DEBUG_DMA
4168 Log3Func(("[SD%RU8] DMA: Skip\n", pStream->u8SD));
4169#endif
4170 if (pcbProcessed)
4171 *pcbProcessed = 0;
4172 return VINF_SUCCESS;
4173 }
4174
4175 int rc = VINF_SUCCESS;
4176
4177#ifdef HDA_DEBUG_DMA
4178 Log3Func(("[SD%RU8] DMA: Start\n", pStream->u8SD));
4179#endif
4180
4181 /* Sanity checks. */
4182 Assert(pStream->u8SD <= HDA_MAX_STREAMS);
4183 Assert(pStream->u64BDLBase);
4184 Assert(pStream->u32CBL);
4185
4186 /* State sanity checks. */
4187 Assert(pStream->State.fInReset == false);
4188 Assert(HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) <= pStream->u32CBL);
4189
4190 bool fSendInterrupt = false;
4191
4192 /* Only do one FIFO size at a time. */
4193 uint32_t cbLeft = RT_MIN(pStream->u16FIFOS, RT_MIN(cbToProcess, cbBuf));
4194 uint32_t cbTotal = 0;
4195 uint32_t cbChunk = 0;
4196 uint32_t cbChunkProcessed = 0;
4197
4198#ifdef HDA_DEBUG_DMA
4199 LogFunc(("[SD%RU8] DMA: cbToProcess=%RU32, cbLeft=%RU32\n", pStream->u8SD, cbToProcess, cbLeft));
4200#endif
4201
4202 /* Get the maximum number of BDL entries. */
4203 uint16_t cBDLE = pStream->u16LVI + 1;
4204
4205 while ( cbLeft
4206 && cBDLE--)
4207 {
4208 cbChunk = hdaStreamGetTransferSize(pThis, pStream, cbLeft);
4209 cbChunkProcessed = 0;
4210
4211 PHDABDLE pBDLE = &pStream->State.BDLE;
4212
4213 if (cbChunk)
4214 {
4215 if (hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_OUT) /* Output (SDO). */
4216 {
4217 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
4218 pBDLE->Desc.u64BufAdr + pBDLE->State.u32BufOff,
4219 (uint8_t *)pvBuf + cbTotal, cbChunk);
4220 }
4221 else /* Input (SDI). */
4222 {
4223 PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns),
4224 pBDLE->Desc.u64BufAdr + pBDLE->State.u32BufOff,
4225 (uint8_t *)pvBuf + cbTotal, cbChunk);
4226 }
4227
4228#ifdef HDA_DEBUG_DUMP_PCM_DATA
4229 RTFILE fh;
4230 RTFileOpen(&fh,
4231 hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_OUT
4232 ? HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaDMARead.pcm" : HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaDMAWrite.pcm",
4233 RTFILE_O_OPEN_CREATE | RTFILE_O_APPEND | RTFILE_O_WRITE | RTFILE_O_DENY_NONE);
4234 RTFileWrite(fh, (uint8_t *)pvBuf + cbTotal, cbChunk, NULL);
4235 RTFileClose(fh);
4236#endif
4237 }
4238
4239 cbChunkProcessed = cbChunk;
4240
4241 hdaBDLEUpdate(pBDLE, cbChunkProcessed, cbChunkProcessed);
4242
4243 LogFunc(("[SD%RU8] DMA: Entry %RU32 Pos %RU32/%RU32 Chunk %RU32\n",
4244 pStream->u8SD, pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->Desc.u32BufSize, cbChunk));
4245
4246 Assert(cbLeft >= cbChunkProcessed);
4247 cbLeft -= cbChunkProcessed;
4248 cbTotal += cbChunkProcessed;
4249 Assert(cbTotal <= cbToProcess);
4250
4251 hdaStreamTransferUpdate(pThis, pStream, cbChunkProcessed);
4252
4253#ifdef HDA_DEBUG_DMA
4254 LogFunc(("[SD%RU8] DMA: LPIB %RU32 Pos %RU32 Left %RU32\n",
4255 pStream->u8SD, HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), cbTotal, cbLeft));
4256#endif
4257 bool fNeedsInterrupt = false;
4258 bool fBDLEIsComplete = hdaBDLEIsComplete(pBDLE, &fNeedsInterrupt);
4259
4260 if (fNeedsInterrupt)
4261 fSendInterrupt = true;
4262
4263 if (fBDLEIsComplete)
4264 {
4265 /* Do we need to fetch the next Buffer Descriptor Entry (BDLE)? */
4266 if (hdaStreamNeedsNextBDLE(pThis, pStream))
4267 {
4268 bool fWrapAround;
4269 rc = hdaStreamGetNextBDLE(pThis, pStream, &fWrapAround);
4270 if ( RT_SUCCESS(rc)
4271 && fWrapAround)
4272 {
4273 hdaStreamUpdateLPIB(pThis, pStream, 0);
4274 }
4275 }
4276 }
4277
4278 if (RT_FAILURE(rc))
4279 break;
4280 }
4281
4282 Log3Func(("[SD%RU8]: cbLeft=%RU32, rc=%Rrc\n", pStream->u8SD, cbLeft, rc));
4283
4284 if (fSendInterrupt)
4285 {
4286#ifdef HDA_DEBUG_DMA
4287 Log3Func(("[SD%RU8] DMA: Interrupt\n", pStream->u8SD));
4288#endif
4289 /**
4290 * Set the BCIS (Buffer Completion Interrupt Status) flag as the
4291 * last byte of data for the current descriptor has been fetched
4292 * from memory and put into the DMA FIFO.
4293 *
4294 * Speech synthesis works fine on Mac Guest if this bit isn't set
4295 * but in general sound quality gets worse.
4296 *
4297 * This must be set in *any* case.
4298 */
4299 HDA_STREAM_REG(pThis, STS, pStream->u8SD) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
4300 Log3Func(("[SD%RU8]: BCIS set\n", pStream->u8SD));
4301
4302 hdaProcessInterrupt(pThis);
4303 }
4304
4305 if (RT_SUCCESS(rc))
4306 {
4307 if (pcbProcessed)
4308 *pcbProcessed = cbTotal;
4309 }
4310
4311#ifdef HDA_DEBUG_DMA
4312 Log3Func(("[SD%RU8] DMA: End\n", pStream->u8SD));
4313#endif
4314
4315 return rc;
4316}
4317
4318/**
4319 * Writes audio data from a mixer sink into an HDA stream's DMA buffer.
4320 *
4321 * @returns IPRT status code.
4322 * @param pThis HDA state.
4323 * @param pStream HDA stream to write to.
4324 * @param cbToWrite Number of bytes to write.
4325 * @param pcbWritten Number of bytes written. Optional.
4326 */
4327static int hdaStreamWrite(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToWrite, uint32_t *pcbWritten)
4328{
4329 RT_NOREF(pThis);
4330 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
4331 AssertReturn(cbToWrite, VERR_INVALID_PARAMETER);
4332 /* pcbWritten is optional. */
4333
4334 PHDAMIXERSINK pSink = pStream->pMixSink;
4335 if (!pSink)
4336 {
4337 AssertMsgFailed(("[SD%RU8]: Can't write to a stream with no sink attached\n", pStream->u8SD));
4338
4339 if (pcbWritten)
4340 *pcbWritten = 0;
4341 return VINF_SUCCESS;
4342 }
4343
4344 PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
4345 AssertPtr(pCircBuf);
4346
4347 void *pvDst;
4348 size_t cbDst;
4349
4350 uint32_t cbWritten = 0;
4351
4352 RTCircBufAcquireWriteBlock(pCircBuf, cbToWrite, &pvDst, &cbDst);
4353
4354 if (cbDst)
4355 {
4356 int rc2 = AudioMixerSinkRead(pSink->pMixSink, AUDMIXOP_COPY, pvDst, (uint32_t)cbDst, &cbWritten);
4357 AssertRC(rc2);
4358
4359 Assert(cbDst >= cbWritten);
4360 Log2Func(("[SD%RU8]: %zu/%zu bytes written\n", pStream->u8SD, cbWritten, cbDst));
4361
4362#ifdef HDA_DEBUG_DUMP_PCM_DATA
4363 RTFILE fh;
4364 RTFileOpen(&fh, HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaStreamWrite.pcm",
4365 RTFILE_O_OPEN_CREATE | RTFILE_O_APPEND | RTFILE_O_WRITE | RTFILE_O_DENY_NONE);
4366 RTFileWrite(fh, pvDst, cbWritten, NULL);
4367 RTFileClose(fh);
4368#endif
4369 }
4370
4371 RTCircBufReleaseWriteBlock(pCircBuf, cbWritten);
4372
4373 if (pcbWritten)
4374 *pcbWritten = cbWritten;
4375
4376 return VINF_SUCCESS;
4377}
4378
4379/**
4380 * Reads audio data from an HDA stream's DMA buffer and writes into a specified mixer sink.
4381 *
4382 * @returns IPRT status code.
4383 * @param pThis HDA state.
4384 * @param pStream HDA stream to read audio data from.
4385 * @param cbToRead Number of bytes to read.
4386 * @param pcbRead Number of bytes read. Optional.
4387 */
4388static int hdaStreamRead(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToRead, uint32_t *pcbRead)
4389{
4390 RT_NOREF(pThis);
4391 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
4392 AssertReturn(cbToRead, VERR_INVALID_PARAMETER);
4393 /* pcbWritten is optional. */
4394
4395 PHDAMIXERSINK pSink = pStream->pMixSink;
4396 if (!pSink)
4397 {
4398 AssertMsgFailed(("[SD%RU8]: Can't read from a stream with no sink attached\n", pStream->u8SD));
4399
4400 if (pcbRead)
4401 *pcbRead = 0;
4402 return VINF_SUCCESS;
4403 }
4404
4405 PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
4406 AssertPtr(pCircBuf);
4407
4408 void *pvSrc;
4409 size_t cbSrc;
4410
4411 uint32_t cbRead = 0;
4412
4413 RTCircBufAcquireReadBlock(pCircBuf, cbToRead, &pvSrc, &cbSrc);
4414
4415 if (cbSrc)
4416 {
4417 Log2Func(("[SD%RU8]: Reading %zu bytes ...\n", pStream->u8SD, cbSrc));
4418
4419#ifdef HDA_DEBUG_DUMP_PCM_DATA
4420 RTFILE fh;
4421 RTFileOpen(&fh, HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaStreamRead.pcm",
4422 RTFILE_O_OPEN_CREATE | RTFILE_O_APPEND | RTFILE_O_WRITE | RTFILE_O_DENY_NONE);
4423 RTFileWrite(fh, pvSrc, cbSrc, NULL);
4424 RTFileClose(fh);
4425#endif
4426 int rc2 = AudioMixerSinkWrite(pSink->pMixSink, AUDMIXOP_COPY, pvSrc, (uint32_t)cbSrc, &cbRead);
4427 AssertRC(rc2);
4428
4429 Assert(cbSrc >= cbRead);
4430 Log2Func(("[SD%RU8]: %zu/%zu bytes read\n", pStream->u8SD, cbRead, cbSrc));
4431 }
4432
4433 RTCircBufReleaseReadBlock(pCircBuf, cbRead);
4434
4435 if (pcbRead)
4436 *pcbRead = cbRead;
4437
4438 return VINF_SUCCESS;
4439}
4440
4441#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
4442/**
4443 * Asynchronous I/O thread for a HDA stream.
4444 * This will do the heavy lifting work for us as soon as it's getting notified by another thread.
4445 *
4446 * @returns IPRT status code.
4447 * @param hThreadSelf Thread handle.
4448 * @param pvUser User argument. Must be of type PHDASTREAMTHREADCTX.
4449 */
4450static DECLCALLBACK(int) hdaStreamAsyncIOThread(RTTHREAD hThreadSelf, void *pvUser)
4451{
4452 PHDASTREAMTHREADCTX pCtx = (PHDASTREAMTHREADCTX)pvUser;
4453 AssertPtr(pCtx);
4454
4455 PHDASTATE pThis = pCtx->pThis;
4456 AssertPtr(pThis);
4457
4458 PHDASTREAM pStream = pCtx->pStream;
4459 AssertPtr(pStream);
4460
4461 PHDASTREAMSTATEAIO pAIO = &pCtx->pStream->State.AIO;
4462
4463 PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
4464 AssertPtr(pCircBuf);
4465
4466 ASMAtomicXchgBool(&pAIO->fStarted, true);
4467
4468 RTThreadUserSignal(hThreadSelf);
4469
4470 LogFunc(("[SD%RU8]: Started\n", pStream->u8SD));
4471
4472 for (;;)
4473 {
4474 int rc2 = RTSemEventWait(pAIO->Event, RT_INDEFINITE_WAIT);
4475 if (RT_FAILURE(rc2))
4476 break;
4477
4478 if (ASMAtomicReadBool(&pAIO->fShutdown))
4479 break;
4480
4481 PHDAMIXERSINK pSink = pStream->pMixSink;
4482
4483 rc2 = RTCritSectEnter(&pAIO->CritSect);
4484 if (RT_SUCCESS(rc2))
4485 {
4486 uint32_t cbToProcess;
4487 uint32_t cbProcessed = 0;
4488
4489 if (hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_OUT) /* Output (SDO). */
4490 {
4491 cbToProcess = RTCircBufUsed(pCircBuf);
4492 if (cbToProcess)
4493 rc2 = hdaStreamRead(pThis, pStream, cbToProcess, &cbProcessed);
4494 }
4495 else /* Input (SDI). */
4496 {
4497 cbToProcess = RTCircBufFree(pCircBuf);
4498 if (cbToProcess)
4499 rc2 = hdaStreamWrite(pThis, pStream, cbToProcess, &cbProcessed);
4500 }
4501
4502 if ( pSink
4503 && RT_SUCCESS(rc2))
4504 {
4505 rc2 = AudioMixerSinkUpdate(pSink->pMixSink);
4506 }
4507
4508 int rc3 = RTCritSectLeave(&pAIO->CritSect);
4509 AssertRC(rc3);
4510 }
4511
4512 AssertRC(rc2);
4513 }
4514
4515 LogFunc(("[SD%RU8]: Ended\n", pStream->u8SD));
4516
4517 return VINF_SUCCESS;
4518}
4519
4520/**
4521 * Lets the stream's async I/O thread know that there is some data to process.
4522 *
4523 * @returns IPRT status code.
4524 * @param pThis HDA state.
4525 * @param pStream HDA stream to notify async I/O thread for.
4526 */
4527static int hdaStreamAsyncIONotify(PHDASTATE pThis, PHDASTREAM pStream)
4528{
4529 RT_NOREF(pThis);
4530 return RTSemEventSignal(pStream->State.AIO.Event);
4531}
4532
4533static void hdaStreamAsyncIOLock(PHDASTREAM pStream)
4534{
4535 PHDASTREAMSTATEAIO pAIO = &pStream->State.AIO;
4536
4537 int rc2 = RTCritSectEnter(&pAIO->CritSect);
4538 AssertRC(rc2);
4539}
4540
4541static void hdaStreamAsyncIOUnlock(PHDASTREAM pStream)
4542{
4543 PHDASTREAMSTATEAIO pAIO = &pStream->State.AIO;
4544
4545 int rc2 = RTCritSectLeave(&pAIO->CritSect);
4546 AssertRC(rc2);
4547}
4548#endif /* VBOX_WITH_AUDIO_HDA_ASYNC_IO */
4549
4550/**
4551 * Updates a HDA stream according to its usage (input / output).
4552 *
4553 * For an SDO (output) stream this means reading DMA data from the device to
4554 * the connected audio sink(s).
4555 *
4556 * For an SDI (input) stream this is reading audio data from the connected
4557 * audio sink(s) and writing it as DMA data to the device.
4558 *
4559 * @returns IPRT status code.
4560 * @param pThis HDA state.
4561 * @param pStream HDA stream to update.
4562 */
4563static int hdaStreamUpdate(PHDASTATE pThis, PHDASTREAM pStream)
4564{
4565 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
4566 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
4567
4568 PHDAMIXERSINK pSink = pStream->pMixSink;
4569 AssertPtr(pSink);
4570
4571 PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
4572 AssertPtr(pCircBuf);
4573
4574 if (!AudioMixerSinkIsActive(pSink->pMixSink))
4575 return VINF_SUCCESS;
4576
4577 Log2Func(("[SD%RU8]\n", pStream->u8SD));
4578
4579 int rc = VINF_SUCCESS;
4580
4581 bool fDone = false;
4582
4583 while (!fDone)
4584 {
4585 int rc2;
4586
4587 if (hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_OUT) /* Output (SDO). */
4588 {
4589 STAM_PROFILE_START(&pThis->StatOut, a);
4590
4591 /*
4592 * Read from DMA.
4593 */
4594
4595 uint8_t abFIFO[HDA_FIFO_MAX + 1];
4596 uint32_t cbProcessed = 0;
4597
4598 /* Do one DMA transfer with FIFOS size at a time. */
4599 rc2 = hdaStreamDoDMA(pThis, pStream, abFIFO, sizeof(abFIFO), (uint32_t)pStream->u16FIFOS /* cbToProcess */,
4600 &cbProcessed);
4601 AssertRC(rc2);
4602
4603 if (cbProcessed)
4604 {
4605 void *pvDst;
4606 size_t cbDst;
4607
4608 Assert(pStream->u16FIFOS);
4609 RTCircBufAcquireWriteBlock(pCircBuf, cbProcessed, &pvDst, &cbDst);
4610
4611 if (cbDst)
4612 {
4613 Assert(cbDst == cbProcessed);
4614 memcpy(pvDst, abFIFO, cbDst);
4615 }
4616
4617 RTCircBufReleaseWriteBlock(pCircBuf, cbDst);
4618 }
4619
4620 /*
4621 * Process backends.
4622 */
4623
4624 uint32_t cbUsed = (uint32_t)RTCircBufUsed(pCircBuf);
4625 if (cbUsed)
4626 {
4627#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
4628 /* Let the asynchronous thread know that there is some new data to process. */
4629 hdaStreamAsyncIONotify(pThis, pStream);
4630#else
4631 rc2 = hdaStreamRead(pThis, pStream, cbUsed, NULL /* pcbRead */);
4632 AssertRC(rc2);
4633#endif
4634 }
4635
4636#ifndef VBOX_WITH_AUDIO_HDA_ASYNC_IO
4637 rc2 = AudioMixerSinkUpdate(pSink->pMixSink);
4638 AssertRC(rc2);
4639#endif
4640 if (!cbProcessed)
4641 fDone = true;
4642
4643 STAM_PROFILE_STOP(&pThis->StatOut, a);
4644 }
4645 else if (hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN) /* Input (SDI). */
4646 {
4647 STAM_PROFILE_START(&pThis->StatIn, a);
4648
4649 /*
4650 * Process backends.
4651 */
4652
4653#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
4654 /* Let the asynchronous thread know that there is some new data to process. */
4655 hdaStreamAsyncIONotify(pThis, pStream);
4656#else
4657 rc2 = AudioMixerSinkUpdate(pSink->pMixSink);
4658 AssertRC(rc2);
4659
4660 rc2 = hdaStreamWrite(pThis, pStream, pStream->u16FIFOS, NULL /* pcbWritten */);
4661 AssertRC(rc2);
4662#endif
4663 /*
4664 * Write to DMA.
4665 */
4666
4667 void *pvSrc;
4668 size_t cbSrc;
4669
4670 RTCircBufAcquireReadBlock(pCircBuf, pStream->u16FIFOS, &pvSrc, &cbSrc);
4671
4672 uint32_t cbProcessed = 0;
4673
4674 if (cbSrc)
4675 {
4676 /* Do one DMA transfer with FIFOS size at a time. */
4677 rc2 = hdaStreamDoDMA(pThis, pStream, pvSrc, (uint32_t)cbSrc, (uint32_t)cbSrc /* cbToProcess */, &cbProcessed);
4678 AssertRC(rc2);
4679 }
4680
4681 RTCircBufReleaseReadBlock(pCircBuf, cbProcessed);
4682
4683 if (!cbProcessed)
4684 fDone = true;
4685
4686 STAM_PROFILE_STOP(&pThis->StatIn, a);
4687 }
4688 else
4689 AssertFailed();
4690 }
4691
4692 return rc;
4693}
4694#endif /* IN_RING3 */
4695
4696/* MMIO callbacks */
4697
4698/**
4699 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
4700 *
4701 * @note During implementation, we discovered so-called "forgotten" or "hole"
4702 * registers whose description is not listed in the RPM, datasheet, or
4703 * spec.
4704 */
4705PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
4706{
4707 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4708 int rc;
4709 RT_NOREF_PV(pvUser);
4710
4711 /*
4712 * Look up and log.
4713 */
4714 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
4715 int idxRegDsc = hdaRegLookup(offReg); /* Register descriptor index. */
4716#ifdef LOG_ENABLED
4717 unsigned const cbLog = cb;
4718 uint32_t offRegLog = offReg;
4719#endif
4720
4721 Log3Func(("offReg=%#x cb=%#x\n", offReg, cb));
4722 Assert(cb == 4); Assert((offReg & 3) == 0);
4723
4724 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
4725 LogFunc(("Access to registers except GCTL is blocked while reset\n"));
4726
4727 if (idxRegDsc == -1)
4728 LogRel(("HDA: Invalid read access @0x%x (bytes=%u)\n", offReg, cb));
4729
4730 if (idxRegDsc != -1)
4731 {
4732 /* ASSUMES gapless DWORD at end of map. */
4733 if (g_aHdaRegMap[idxRegDsc].size == 4)
4734 {
4735 /*
4736 * Straight forward DWORD access.
4737 */
4738 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
4739 Log3Func(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
4740 }
4741 else
4742 {
4743 /*
4744 * Multi register read (unless there are trailing gaps).
4745 * ASSUMES that only DWORD reads have sideeffects.
4746 */
4747 uint32_t u32Value = 0;
4748 unsigned cbLeft = 4;
4749 do
4750 {
4751 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
4752 uint32_t u32Tmp = 0;
4753
4754 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
4755 Log3Func(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
4756 if (rc != VINF_SUCCESS)
4757 break;
4758 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
4759
4760 cbLeft -= cbReg;
4761 offReg += cbReg;
4762 idxRegDsc++;
4763 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
4764
4765 if (rc == VINF_SUCCESS)
4766 *(uint32_t *)pv = u32Value;
4767 else
4768 Assert(!IOM_SUCCESS(rc));
4769 }
4770 }
4771 else
4772 {
4773 rc = VINF_IOM_MMIO_UNUSED_FF;
4774 Log3Func(("\tHole at %x is accessed for read\n", offReg));
4775 }
4776
4777 /*
4778 * Log the outcome.
4779 */
4780#ifdef LOG_ENABLED
4781 if (cbLog == 4)
4782 Log3Func(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
4783 else if (cbLog == 2)
4784 Log3Func(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
4785 else if (cbLog == 1)
4786 Log3Func(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
4787#endif
4788 return rc;
4789}
4790
4791
4792DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
4793{
4794 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
4795 {
4796 LogRel2(("HDA: Warning: Access to register 0x%x is blocked while reset\n", idxRegDsc));
4797 return VINF_SUCCESS;
4798 }
4799
4800#ifdef LOG_ENABLED
4801 uint32_t const idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4802 uint32_t const u32CurValue = pThis->au32Regs[idxRegMem];
4803#endif
4804 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
4805 Log3Func(("Written value %#x to %s[%d byte]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
4806 g_aHdaRegMap[idxRegDsc].size, u32CurValue, pThis->au32Regs[idxRegMem], pszLog));
4807 RT_NOREF1(pszLog);
4808 return rc;
4809}
4810
4811
4812/**
4813 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
4814 */
4815PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
4816{
4817 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4818 int rc;
4819 RT_NOREF_PV(pvUser);
4820
4821 /*
4822 * The behavior of accesses that aren't aligned on natural boundraries is
4823 * undefined. Just reject them outright.
4824 */
4825 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
4826 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
4827 if (GCPhysAddr & (cb - 1))
4828 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
4829
4830 /*
4831 * Look up and log the access.
4832 */
4833 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
4834 int idxRegDsc = hdaRegLookup(offReg);
4835 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
4836 uint64_t u64Value;
4837 if (cb == 4) u64Value = *(uint32_t const *)pv;
4838 else if (cb == 2) u64Value = *(uint16_t const *)pv;
4839 else if (cb == 1) u64Value = *(uint8_t const *)pv;
4840 else if (cb == 8) u64Value = *(uint64_t const *)pv;
4841 else
4842 {
4843 u64Value = 0; /* shut up gcc. */
4844 AssertReleaseMsgFailed(("%u\n", cb));
4845 }
4846
4847#ifdef LOG_ENABLED
4848 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
4849 if (idxRegDsc == -1)
4850 Log3Func(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
4851 else if (cb == 4)
4852 Log3Func(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4853 else if (cb == 2)
4854 Log3Func(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4855 else if (cb == 1)
4856 Log3Func(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4857
4858 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
4859 Log3Func(("\tsize=%RU32 != cb=%u!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
4860#endif
4861
4862 /*
4863 * Try for a direct hit first.
4864 */
4865 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
4866 {
4867 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
4868 Log3Func(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
4869 }
4870 /*
4871 * Partial or multiple register access, loop thru the requested memory.
4872 */
4873 else
4874 {
4875 /*
4876 * If it's an access beyond the start of the register, shift the input
4877 * value and fill in missing bits. Natural alignment rules means we
4878 * will only see 1 or 2 byte accesses of this kind, so no risk of
4879 * shifting out input values.
4880 */
4881 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(offReg)) != -1)
4882 {
4883 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
4884 offReg -= cbBefore;
4885 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4886 u64Value <<= cbBefore * 8;
4887 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
4888 Log3Func(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
4889 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
4890 }
4891
4892 /* Loop thru the write area, it may cover multiple registers. */
4893 rc = VINF_SUCCESS;
4894 for (;;)
4895 {
4896 uint32_t cbReg;
4897 if (idxRegDsc != -1)
4898 {
4899 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4900 cbReg = g_aHdaRegMap[idxRegDsc].size;
4901 if (cb < cbReg)
4902 {
4903 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
4904 Log3Func(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
4905 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
4906 }
4907#ifdef LOG_ENABLED
4908 uint32_t uLogOldVal = pThis->au32Regs[idxRegMem];
4909#endif
4910 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
4911 Log3Func(("\t%#x -> %#x\n", uLogOldVal, pThis->au32Regs[idxRegMem]));
4912 }
4913 else
4914 {
4915 LogRel(("HDA: Invalid write access @0x%x\n", offReg));
4916 cbReg = 1;
4917 }
4918 if (rc != VINF_SUCCESS)
4919 break;
4920 if (cbReg >= cb)
4921 break;
4922
4923 /* Advance. */
4924 offReg += cbReg;
4925 cb -= cbReg;
4926 u64Value >>= cbReg * 8;
4927 if (idxRegDsc == -1)
4928 idxRegDsc = hdaRegLookup(offReg);
4929 else
4930 {
4931 idxRegDsc++;
4932 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
4933 || g_aHdaRegMap[idxRegDsc].offset != offReg)
4934 {
4935 idxRegDsc = -1;
4936 }
4937 }
4938 }
4939 }
4940
4941 return rc;
4942}
4943
4944
4945/* PCI callback. */
4946
4947#ifdef IN_RING3
4948/**
4949 * @callback_method_impl{FNPCIIOREGIONMAP}
4950 */
4951static DECLCALLBACK(int) hdaPciIoRegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
4952 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
4953{
4954 RT_NOREF(iRegion, enmType);
4955 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
4956
4957 /*
4958 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
4959 *
4960 * Let IOM talk DWORDs when reading, saves a lot of complications. On
4961 * writing though, we have to do it all ourselves because of sideeffects.
4962 */
4963 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
4964 int rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
4965 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_PASSTHRU,
4966 hdaMMIOWrite, hdaMMIORead, "HDA");
4967 if (RT_FAILURE(rc))
4968 return rc;
4969
4970 if (pThis->fR0Enabled)
4971 {
4972 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
4973 "hdaMMIOWrite", "hdaMMIORead");
4974 if (RT_FAILURE(rc))
4975 return rc;
4976 }
4977
4978 if (pThis->fRCEnabled)
4979 {
4980 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
4981 "hdaMMIOWrite", "hdaMMIORead");
4982 if (RT_FAILURE(rc))
4983 return rc;
4984 }
4985
4986 pThis->MMIOBaseAddr = GCPhysAddress;
4987 return VINF_SUCCESS;
4988}
4989
4990
4991/* Saved state callbacks. */
4992
4993static int hdaSaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStrm)
4994{
4995 RT_NOREF(pDevIns);
4996#ifdef DEBUG
4997 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4998#endif
4999 LogFlowFunc(("[SD%RU8]\n", pStrm->u8SD));
5000
5001 /* Save stream ID. */
5002 int rc = SSMR3PutU8(pSSM, pStrm->u8SD);
5003 AssertRCReturn(rc, rc);
5004 Assert(pStrm->u8SD <= HDA_MAX_STREAMS);
5005
5006 rc = SSMR3PutStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE), 0 /*fFlags*/, g_aSSMStreamStateFields6, NULL);
5007 AssertRCReturn(rc, rc);
5008
5009#ifdef DEBUG /* Sanity checks. */
5010 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStrm->u8SD),
5011 HDA_STREAM_REG(pThis, BDPU, pStrm->u8SD));
5012 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStrm->u8SD);
5013 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStrm->u8SD);
5014
5015 hdaBDLEDumpAll(pThis, u64BaseDMA, u16LVI + 1);
5016
5017 Assert(u64BaseDMA == pStrm->u64BDLBase);
5018 Assert(u16LVI == pStrm->u16LVI);
5019 Assert(u32CBL == pStrm->u32CBL);
5020#endif
5021
5022 rc = SSMR3PutStructEx(pSSM, &pStrm->State.BDLE.Desc, sizeof(HDABDLEDESC),
5023 0 /*fFlags*/, g_aSSMBDLEDescFields6, NULL);
5024 AssertRCReturn(rc, rc);
5025
5026 rc = SSMR3PutStructEx(pSSM, &pStrm->State.BDLE.State, sizeof(HDABDLESTATE),
5027 0 /*fFlags*/, g_aSSMBDLEStateFields6, NULL);
5028 AssertRCReturn(rc, rc);
5029
5030#ifdef DEBUG /* Sanity checks. */
5031 PHDABDLE pBDLE = &pStrm->State.BDLE;
5032 if (u64BaseDMA)
5033 {
5034 Assert(pStrm->State.uCurBDLE <= u16LVI + 1);
5035
5036 HDABDLE curBDLE;
5037 rc = hdaBDLEFetch(pThis, &curBDLE, u64BaseDMA, pStrm->State.uCurBDLE);
5038 AssertRC(rc);
5039
5040 Assert(curBDLE.Desc.u32BufSize == pBDLE->Desc.u32BufSize);
5041 Assert(curBDLE.Desc.u64BufAdr == pBDLE->Desc.u64BufAdr);
5042 Assert(curBDLE.Desc.fFlags == pBDLE->Desc.fFlags);
5043 }
5044 else
5045 {
5046 Assert(pBDLE->Desc.u64BufAdr == 0);
5047 Assert(pBDLE->Desc.u32BufSize == 0);
5048 }
5049#endif
5050 return rc;
5051}
5052
5053/**
5054 * @callback_method_impl{FNSSMDEVSAVEEXEC}
5055 */
5056static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5057{
5058 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5059
5060 /* Save Codec nodes states. */
5061 hdaCodecSaveState(pThis->pCodec, pSSM);
5062
5063 /* Save MMIO registers. */
5064 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
5065 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
5066
5067 /* Save number of streams. */
5068 SSMR3PutU32(pSSM, HDA_MAX_STREAMS);
5069
5070 /* Save stream states. */
5071 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5072 {
5073 int rc = hdaSaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
5074 AssertRCReturn(rc, rc);
5075 }
5076
5077 return VINF_SUCCESS;
5078}
5079
5080
5081/**
5082 * @callback_method_impl{FNSSMDEVLOADEXEC}
5083 */
5084static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5085{
5086 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5087
5088 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
5089
5090 LogRel2(("hdaLoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
5091
5092 /*
5093 * Load Codec nodes states.
5094 */
5095 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
5096 if (RT_FAILURE(rc))
5097 {
5098 LogRel(("HDA: Failed loading codec state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
5099 return rc;
5100 }
5101
5102 /*
5103 * Load MMIO registers.
5104 */
5105 uint32_t cRegs;
5106 switch (uVersion)
5107 {
5108 case HDA_SSM_VERSION_1:
5109 /* Starting with r71199, we would save 112 instead of 113
5110 registers due to some code cleanups. This only affected trunk
5111 builds in the 4.1 development period. */
5112 cRegs = 113;
5113 if (SSMR3HandleRevision(pSSM) >= 71199)
5114 {
5115 uint32_t uVer = SSMR3HandleVersion(pSSM);
5116 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
5117 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
5118 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
5119 cRegs = 112;
5120 }
5121 break;
5122
5123 case HDA_SSM_VERSION_2:
5124 case HDA_SSM_VERSION_3:
5125 cRegs = 112;
5126 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= 112);
5127 break;
5128
5129 /* Since version 4 we store the register count to stay flexible. */
5130 case HDA_SSM_VERSION_4:
5131 case HDA_SSM_VERSION_5:
5132 case HDA_SSM_VERSION:
5133 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
5134 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
5135 LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
5136 break;
5137
5138 default:
5139 LogRel(("HDA: Unsupported / too new saved state version (%RU32)\n", uVersion));
5140 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
5141 }
5142
5143 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
5144 {
5145 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
5146 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
5147 }
5148 else
5149 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
5150
5151 /*
5152 * Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
5153 * *every* BDLE state, whereas it only needs to be stored
5154 * *once* for every stream. Most of the BDLE state we can
5155 * get out of the registers anyway, so just ignore those values.
5156 *
5157 * Also, only the current BDLE was saved, regardless whether
5158 * there were more than one (and there are at least two entries,
5159 * according to the spec).
5160 */
5161#define HDA_SSM_LOAD_BDLE_STATE_PRE_V5(v, x) \
5162 { \
5163 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */ \
5164 AssertRCReturn(rc, rc); \
5165 rc = SSMR3GetU64(pSSM, &x.Desc.u64BufAdr); /* u64BdleCviAddr */ \
5166 AssertRCReturn(rc, rc); \
5167 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleMaxCvi */ \
5168 AssertRCReturn(rc, rc); \
5169 rc = SSMR3GetU32(pSSM, &x.State.u32BDLIndex); /* u32BdleCvi */ \
5170 AssertRCReturn(rc, rc); \
5171 rc = SSMR3GetU32(pSSM, &x.Desc.u32BufSize); /* u32BdleCviLen */ \
5172 AssertRCReturn(rc, rc); \
5173 rc = SSMR3GetU32(pSSM, &x.State.u32BufOff); /* u32BdleCviPos */ \
5174 AssertRCReturn(rc, rc); \
5175 bool fIOC; \
5176 rc = SSMR3GetBool(pSSM, &fIOC); /* fBdleCviIoc */ \
5177 AssertRCReturn(rc, rc); \
5178 x.Desc.fFlags = fIOC ? HDA_BDLE_FLAG_IOC : 0; \
5179 rc = SSMR3GetU32(pSSM, &x.State.cbBelowFIFOW); /* cbUnderFifoW */ \
5180 AssertRCReturn(rc, rc); \
5181 rc = SSMR3Skip(pSSM, sizeof(uint8_t) * 256); /* FIFO */ \
5182 AssertRCReturn(rc, rc); \
5183 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */ \
5184 AssertRCReturn(rc, rc); \
5185 } \
5186
5187 /*
5188 * Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
5189 */
5190 switch (uVersion)
5191 {
5192 case HDA_SSM_VERSION_1:
5193 case HDA_SSM_VERSION_2:
5194 case HDA_SSM_VERSION_3:
5195 case HDA_SSM_VERSION_4:
5196 {
5197 /* Only load the internal states.
5198 * The rest will be initialized from the saved registers later. */
5199
5200 /* Note 1: Only the *current* BDLE for a stream was saved! */
5201 /* Note 2: The stream's saving order is/was fixed, so don't touch! */
5202
5203 /* Output */
5204 PHDASTREAM pStream = &pThis->aStreams[4];
5205 rc = hdaStreamInit(pThis, pStream, 4 /* Stream descriptor, hardcoded */);
5206 if (RT_FAILURE(rc))
5207 break;
5208 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
5209 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
5210
5211 /* Microphone-In */
5212 pStream = &pThis->aStreams[2];
5213 rc = hdaStreamInit(pThis, pStream, 2 /* Stream descriptor, hardcoded */);
5214 if (RT_FAILURE(rc))
5215 break;
5216 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
5217 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
5218
5219 /* Line-In */
5220 pStream = &pThis->aStreams[0];
5221 rc = hdaStreamInit(pThis, pStream, 0 /* Stream descriptor, hardcoded */);
5222 if (RT_FAILURE(rc))
5223 break;
5224 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
5225 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
5226 break;
5227 }
5228
5229 /* Since v5 we support flexible stream and BDLE counts. */
5230 case HDA_SSM_VERSION_5:
5231 case HDA_SSM_VERSION:
5232 {
5233 uint32_t cStreams;
5234 rc = SSMR3GetU32(pSSM, &cStreams);
5235 if (RT_FAILURE(rc))
5236 break;
5237
5238 LogRel2(("hdaLoadExec: cStreams=%RU32\n", cStreams));
5239
5240 /* Load stream states. */
5241 for (uint32_t i = 0; i < cStreams; i++)
5242 {
5243 uint8_t uSD;
5244 rc = SSMR3GetU8(pSSM, &uSD);
5245 if (RT_FAILURE(rc))
5246 break;
5247
5248 PHDASTREAM pStrm = hdaStreamFromSD(pThis, uSD);
5249 HDASTREAM StreamDummy;
5250
5251 if (!pStrm)
5252 {
5253 RT_ZERO(StreamDummy);
5254 pStrm = &StreamDummy;
5255 LogRel2(("HDA: Warning: Stream ID=%RU32 not supported, skipping to load ...\n", uSD));
5256 break;
5257 }
5258
5259 rc = hdaStreamInit(pThis, pStrm, uSD);
5260 if (RT_FAILURE(rc))
5261 {
5262 LogRel(("HDA: Stream #%RU32: Initialization of stream %RU8 failed, rc=%Rrc\n", i, uSD, rc));
5263 break;
5264 }
5265
5266 if (uVersion == HDA_SSM_VERSION_5)
5267 {
5268 /* Get the current BDLE entry and skip the rest. */
5269 uint16_t cBDLE;
5270
5271 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
5272 AssertRC(rc);
5273 rc = SSMR3GetU16(pSSM, &cBDLE); /* cBDLE */
5274 AssertRC(rc);
5275 rc = SSMR3GetU16(pSSM, &pStrm->State.uCurBDLE); /* uCurBDLE */
5276 AssertRC(rc);
5277 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
5278 AssertRC(rc);
5279
5280 uint32_t u32BDLEIndex;
5281 for (uint16_t a = 0; a < cBDLE; a++)
5282 {
5283 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
5284 AssertRC(rc);
5285 rc = SSMR3GetU32(pSSM, &u32BDLEIndex); /* u32BDLIndex */
5286 AssertRC(rc);
5287
5288 /* Does the current BDLE index match the current BDLE to process? */
5289 if (u32BDLEIndex == pStrm->State.uCurBDLE)
5290 {
5291 rc = SSMR3GetU32(pSSM, &pStrm->State.BDLE.State.cbBelowFIFOW); /* cbBelowFIFOW */
5292 AssertRC(rc);
5293 rc = SSMR3Skip(pSSM, sizeof(uint8_t) * 256); /* FIFO, deprecated */
5294 AssertRC(rc);
5295 rc = SSMR3GetU32(pSSM, &pStrm->State.BDLE.State.u32BufOff); /* u32BufOff */
5296 AssertRC(rc);
5297 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
5298 AssertRC(rc);
5299 }
5300 else /* Skip not current BDLEs. */
5301 {
5302 rc = SSMR3Skip(pSSM, sizeof(uint32_t) /* cbBelowFIFOW */
5303 + sizeof(uint8_t) * 256 /* FIFO, deprecated */
5304 + sizeof(uint32_t) /* u32BufOff */
5305 + sizeof(uint32_t)); /* End marker */
5306 AssertRC(rc);
5307 }
5308 }
5309 }
5310 else
5311 {
5312 rc = SSMR3GetStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE),
5313 0 /* fFlags */, g_aSSMStreamStateFields6, NULL);
5314 if (RT_FAILURE(rc))
5315 break;
5316
5317 rc = SSMR3GetStructEx(pSSM, &pStrm->State.BDLE.Desc, sizeof(HDABDLEDESC),
5318 0 /* fFlags */, g_aSSMBDLEDescFields6, NULL);
5319 if (RT_FAILURE(rc))
5320 break;
5321
5322 rc = SSMR3GetStructEx(pSSM, &pStrm->State.BDLE.State, sizeof(HDABDLESTATE),
5323 0 /* fFlags */, g_aSSMBDLEStateFields6, NULL);
5324 if (RT_FAILURE(rc))
5325 break;
5326 }
5327 }
5328 break;
5329 }
5330
5331 default:
5332 AssertReleaseFailed(); /* Never reached. */
5333 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
5334 }
5335
5336#undef HDA_SSM_LOAD_BDLE_STATE_PRE_V5
5337
5338 if (RT_SUCCESS(rc))
5339 {
5340 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
5341 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
5342 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
5343
5344 /* Also make sure to update the DMA position bit if this was enabled when saving the state. */
5345 pThis->fDMAPosition = RT_BOOL(pThis->u64DPBase & RT_BIT_64(0));
5346 }
5347
5348 if (RT_SUCCESS(rc))
5349 {
5350 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5351 {
5352 PHDASTREAM pStream = hdaStreamFromSD(pThis, i);
5353 if (pStream)
5354 {
5355 hdaStreamEnable(pThis, pStream, false /* fEnable */);
5356
5357 bool fActive = RT_BOOL(HDA_STREAM_REG(pThis, CTL, i) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
5358 if (fActive)
5359 {
5360 int rc2 = hdaStreamEnable(pThis, pStream, true /* fEnable */);
5361 AssertRC(rc2);
5362 }
5363 }
5364 }
5365 }
5366
5367 if (RT_FAILURE(rc))
5368 LogRel(("HDA: Failed loading device state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
5369
5370 LogFlowFuncLeaveRC(rc);
5371 return rc;
5372}
5373
5374#ifdef DEBUG
5375/* Debug and log type formatters. */
5376
5377/**
5378 * @callback_method_impl{FNRTSTRFORMATTYPE}
5379 */
5380static DECLCALLBACK(size_t) hdaDbgFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5381 const char *pszType, void const *pvValue,
5382 int cchWidth, int cchPrecision, unsigned fFlags,
5383 void *pvUser)
5384{
5385 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5386 PHDABDLE pBDLE = (PHDABDLE)pvValue;
5387 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5388 "BDLE(idx:%RU32, off:%RU32, fifow:%RU32, IOC:%RTbool, DMA[%RU32 bytes @ 0x%x])",
5389 pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW,
5390 pBDLE->Desc.fFlags & HDA_BDLE_FLAG_IOC, pBDLE->Desc.u32BufSize, pBDLE->Desc.u64BufAdr);
5391}
5392
5393/**
5394 * @callback_method_impl{FNRTSTRFORMATTYPE}
5395 */
5396static DECLCALLBACK(size_t) hdaDbgFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5397 const char *pszType, void const *pvValue,
5398 int cchWidth, int cchPrecision, unsigned fFlags,
5399 void *pvUser)
5400{
5401 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5402 uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
5403 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5404 "SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
5405 uSDCTL,
5406 (uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)) ? "OUT" : "IN",
5407 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
5408 (uSDCTL & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
5409 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
5410 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, FEIE)),
5411 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
5412 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
5413 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
5414}
5415
5416/**
5417 * @callback_method_impl{FNRTSTRFORMATTYPE}
5418 */
5419static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5420 const char *pszType, void const *pvValue,
5421 int cchWidth, int cchPrecision, unsigned fFlags,
5422 void *pvUser)
5423{
5424 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5425 uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
5426 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, uSDFIFOS ? uSDFIFOS + 1 : 0);
5427}
5428
5429/**
5430 * @callback_method_impl{FNRTSTRFORMATTYPE}
5431 */
5432static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5433 const char *pszType, void const *pvValue,
5434 int cchWidth, int cchPrecision, unsigned fFlags,
5435 void *pvUser)
5436{
5437 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5438 uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
5439 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
5440}
5441
5442/**
5443 * @callback_method_impl{FNRTSTRFORMATTYPE}
5444 */
5445static DECLCALLBACK(size_t) hdaDbgFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5446 const char *pszType, void const *pvValue,
5447 int cchWidth, int cchPrecision, unsigned fFlags,
5448 void *pvUser)
5449{
5450 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5451 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
5452 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5453 "SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
5454 uSdSts,
5455 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
5456 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
5457 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
5458 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
5459}
5460
5461static int hdaDbgLookupRegByName(const char *pszArgs)
5462{
5463 int iReg = 0;
5464 for (; iReg < HDA_NUM_REGS; ++iReg)
5465 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
5466 return iReg;
5467 return -1;
5468}
5469
5470
5471static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
5472{
5473 Assert( pThis
5474 && iHdaIndex >= 0
5475 && iHdaIndex < HDA_NUM_REGS);
5476 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
5477}
5478
5479/**
5480 * @callback_method_impl{FNDBGFHANDLERDEV}
5481 */
5482static DECLCALLBACK(void) hdaDbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5483{
5484 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5485 int iHdaRegisterIndex = hdaDbgLookupRegByName(pszArgs);
5486 if (iHdaRegisterIndex != -1)
5487 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
5488 else
5489 {
5490 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NUM_REGS; ++iHdaRegisterIndex)
5491 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
5492 }
5493}
5494
5495static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
5496{
5497 Assert( pThis
5498 && iIdx >= 0
5499 && iIdx < HDA_MAX_STREAMS);
5500
5501 const PHDASTREAM pStrm = &pThis->aStreams[iIdx];
5502
5503 pHlp->pfnPrintf(pHlp, "Stream #%d:\n", iIdx);
5504 pHlp->pfnPrintf(pHlp, "\tSD%dCTL : %R[sdctl]\n", iIdx, HDA_STREAM_REG(pThis, CTL, iIdx));
5505 pHlp->pfnPrintf(pHlp, "\tSD%dCTS : %R[sdsts]\n", iIdx, HDA_STREAM_REG(pThis, STS, iIdx));
5506 pHlp->pfnPrintf(pHlp, "\tSD%dFIFOS: %R[sdfifos]\n", iIdx, HDA_STREAM_REG(pThis, FIFOS, iIdx));
5507 pHlp->pfnPrintf(pHlp, "\tSD%dFIFOW: %R[sdfifow]\n", iIdx, HDA_STREAM_REG(pThis, FIFOW, iIdx));
5508 pHlp->pfnPrintf(pHlp, "\tBDLE : %R[bdle]\n", &pStrm->State.BDLE);
5509}
5510
5511static void hdaDbgPrintBDLE(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
5512{
5513 Assert( pThis
5514 && iIdx >= 0
5515 && iIdx < HDA_MAX_STREAMS);
5516
5517 const PHDASTREAM pStrm = &pThis->aStreams[iIdx];
5518 const PHDABDLE pBDLE = &pStrm->State.BDLE;
5519
5520 pHlp->pfnPrintf(pHlp, "Stream #%d BDLE:\n", iIdx);
5521
5522 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, iIdx),
5523 HDA_STREAM_REG(pThis, BDPU, iIdx));
5524 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, iIdx);
5525 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, iIdx);
5526
5527 if (!u64BaseDMA)
5528 return;
5529
5530 pHlp->pfnPrintf(pHlp, "\tCurrent: %R[bdle]\n\n", pBDLE);
5531
5532 pHlp->pfnPrintf(pHlp, "\tMemory:\n");
5533
5534 uint32_t cbBDLE = 0;
5535 for (uint16_t i = 0; i < u16LVI + 1; i++)
5536 {
5537 HDABDLEDESC bd;
5538 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i * sizeof(HDABDLEDESC), &bd, sizeof(bd));
5539
5540 pHlp->pfnPrintf(pHlp, "\t\t%s #%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
5541 pBDLE->State.u32BDLIndex == i ? "*" : " ", i, bd.u64BufAdr, bd.u32BufSize, bd.fFlags & HDA_BDLE_FLAG_IOC);
5542
5543 cbBDLE += bd.u32BufSize;
5544 }
5545
5546 pHlp->pfnPrintf(pHlp, "Total: %RU32 bytes\n", cbBDLE);
5547
5548 if (cbBDLE != u32CBL)
5549 pHlp->pfnPrintf(pHlp, "Warning: %RU32 bytes does not match CBL (%RU32)!\n", cbBDLE, u32CBL);
5550
5551 pHlp->pfnPrintf(pHlp, "DMA counters (base @ 0x%llx):\n", u64BaseDMA);
5552 if (!u64BaseDMA) /* No DMA base given? Bail out. */
5553 {
5554 pHlp->pfnPrintf(pHlp, "\tNo counters found\n");
5555 return;
5556 }
5557
5558 for (int i = 0; i < u16LVI + 1; i++)
5559 {
5560 uint32_t uDMACnt;
5561 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
5562 &uDMACnt, sizeof(uDMACnt));
5563
5564 pHlp->pfnPrintf(pHlp, "\t#%03d DMA @ 0x%x\n", i , uDMACnt);
5565 }
5566}
5567
5568static int hdaDbgLookupStrmIdx(PHDASTATE pThis, const char *pszArgs)
5569{
5570 RT_NOREF(pThis, pszArgs);
5571 /** @todo Add args parsing. */
5572 return -1;
5573}
5574
5575/**
5576 * @callback_method_impl{FNDBGFHANDLERDEV}
5577 */
5578static DECLCALLBACK(void) hdaDbgInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5579{
5580 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5581 int iHdaStreamdex = hdaDbgLookupStrmIdx(pThis, pszArgs);
5582 if (iHdaStreamdex != -1)
5583 hdaDbgPrintStream(pThis, pHlp, iHdaStreamdex);
5584 else
5585 for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
5586 hdaDbgPrintStream(pThis, pHlp, iHdaStreamdex);
5587}
5588
5589/**
5590 * @callback_method_impl{FNDBGFHANDLERDEV}
5591 */
5592static DECLCALLBACK(void) hdaDbgInfoBDLE(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5593{
5594 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5595 int iHdaStreamdex = hdaDbgLookupStrmIdx(pThis, pszArgs);
5596 if (iHdaStreamdex != -1)
5597 hdaDbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
5598 else
5599 for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
5600 hdaDbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
5601}
5602
5603/**
5604 * @callback_method_impl{FNDBGFHANDLERDEV}
5605 */
5606static DECLCALLBACK(void) hdaDbgInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5607{
5608 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5609
5610 if (pThis->pCodec->pfnDbgListNodes)
5611 pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
5612 else
5613 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
5614}
5615
5616/**
5617 * @callback_method_impl{FNDBGFHANDLERDEV}
5618 */
5619static DECLCALLBACK(void) hdaDbgInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5620{
5621 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5622
5623 if (pThis->pCodec->pfnDbgSelector)
5624 pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
5625 else
5626 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
5627}
5628
5629/**
5630 * @callback_method_impl{FNDBGFHANDLERDEV}
5631 */
5632static DECLCALLBACK(void) hdaDbgInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5633{
5634 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5635
5636 if (pThis->pMixer)
5637 AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
5638 else
5639 pHlp->pfnPrintf(pHlp, "Mixer not available\n");
5640}
5641#endif /* DEBUG */
5642
5643/* PDMIBASE */
5644
5645/**
5646 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
5647 */
5648static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
5649{
5650 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
5651 Assert(&pThis->IBase == pInterface);
5652
5653 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
5654 return NULL;
5655}
5656
5657
5658/* PDMDEVREG */
5659
5660/**
5661 * Reset notification.
5662 *
5663 * @returns VBox status code.
5664 * @param pDevIns The device instance data.
5665 *
5666 * @remark The original sources didn't install a reset handler, but it seems to
5667 * make sense to me so we'll do it.
5668 */
5669static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
5670{
5671 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5672
5673 LogFlowFuncEnter();
5674
5675# ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
5676 /*
5677 * Stop the timer, if any.
5678 */
5679 hdaTimerStop(pThis);
5680
5681 pThis->cStreamsActive = 0;
5682# endif
5683
5684 /* See 6.2.1. */
5685 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(HDA_MAX_SDO /* Ouput streams */,
5686 HDA_MAX_SDI /* Input streams */,
5687 0 /* Bidirectional output streams */,
5688 0 /* Serial data out signals */,
5689 1 /* 64-bit */);
5690 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
5691 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
5692 /* Announce the full 60 words output payload. */
5693 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
5694 /* Announce the full 29 words input payload. */
5695 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
5696 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
5697 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
5698 HDA_REG(pThis, CORBRP) = 0x0;
5699 HDA_REG(pThis, RIRBWP) = 0x0;
5700
5701 /*
5702 * Stop any audio currently playing and/or recording.
5703 */
5704 if (pThis->SinkFront.pMixSink)
5705 AudioMixerSinkReset(pThis->SinkFront.pMixSink);
5706# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5707 if (pThis->SinkMicIn.pMixSink)
5708 AudioMixerSinkReset(pThis->SinkMicIn.pMixSink);
5709# endif
5710 if (pThis->SinkLineIn.pMixSink)
5711 AudioMixerSinkReset(pThis->SinkLineIn.pMixSink);
5712# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
5713 if (pThis->SinkCenterLFE.pMixSink)
5714 AudioMixerSinkReset(pThis->SinkCenterLFE.pMixSink);
5715 if (pThis->SinkRear.pMixSink)
5716 AudioMixerSinkReset(pThis->SinkRear.pMixSink);
5717# endif
5718
5719 /*
5720 * Reset the codec.
5721 */
5722 if ( pThis->pCodec
5723 && pThis->pCodec->pfnReset)
5724 {
5725 pThis->pCodec->pfnReset(pThis->pCodec);
5726 }
5727
5728 /*
5729 * Set some sensible defaults for which HDA sinks
5730 * are connected to which stream number.
5731 *
5732 * We use SD0 for input and SD4 for output by default.
5733 * These stream numbers can be changed by the guest dynamically lateron.
5734 */
5735#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5736 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_MIC_IN , 1 /* SD0 */, 0 /* Channel */);
5737#endif
5738 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_LINE_IN , 1 /* SD0 */, 0 /* Channel */);
5739
5740 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_FRONT , 5 /* SD4 */, 0 /* Channel */);
5741#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
5742 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_CENTER_LFE, 5 /* SD4 */, 0 /* Channel */);
5743 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_REAR , 5 /* SD4 */, 0 /* Channel */);
5744#endif
5745
5746 pThis->cbCorbBuf = 256 * sizeof(uint32_t); /** @todo Use a define here. */
5747
5748 if (pThis->pu32CorbBuf)
5749 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
5750 else
5751 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
5752
5753 pThis->cbRirbBuf = 256 * sizeof(uint64_t); /** @todo Use a define here. */
5754 if (pThis->pu64RirbBuf)
5755 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
5756 else
5757 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
5758
5759 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
5760
5761 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5762 {
5763 /* Remove the RUN bit from SDnCTL in case the stream was in a running state before. */
5764 HDA_STREAM_REG(pThis, CTL, i) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN);
5765 hdaStreamReset(pThis, &pThis->aStreams[i]);
5766 }
5767
5768 /* Clear stream tags <-> objects mapping table. */
5769 RT_ZERO(pThis->aTags);
5770
5771 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
5772 HDA_REG(pThis, STATESTS) = 0x1;
5773
5774 LogFlowFuncLeave();
5775 LogRel(("HDA: Reset\n"));
5776}
5777
5778/**
5779 * @interface_method_impl{PDMDEVREG,pfnDestruct}
5780 */
5781static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
5782{
5783 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5784
5785 PHDADRIVER pDrv;
5786 while (!RTListIsEmpty(&pThis->lstDrv))
5787 {
5788 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
5789
5790 RTListNodeRemove(&pDrv->Node);
5791 RTMemFree(pDrv);
5792 }
5793
5794 if (pThis->pCodec)
5795 {
5796 hdaCodecDestruct(pThis->pCodec);
5797
5798 RTMemFree(pThis->pCodec);
5799 pThis->pCodec = NULL;
5800 }
5801
5802 RTMemFree(pThis->pu32CorbBuf);
5803 pThis->pu32CorbBuf = NULL;
5804
5805 RTMemFree(pThis->pu64RirbBuf);
5806 pThis->pu64RirbBuf = NULL;
5807
5808 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5809 hdaStreamDestroy(pThis, &pThis->aStreams[i]);
5810
5811 return VINF_SUCCESS;
5812}
5813
5814
5815/**
5816 * Attach command, internal version.
5817 *
5818 * This is called to let the device attach to a driver for a specified LUN
5819 * during runtime. This is not called during VM construction, the device
5820 * constructor has to attach to all the available drivers.
5821 *
5822 * @returns VBox status code.
5823 * @param pDevIns The device instance.
5824 * @param pDrv Driver to (re-)use for (re-)attaching to.
5825 * If NULL is specified, a new driver will be created and appended
5826 * to the driver list.
5827 * @param uLUN The logical unit which is being detached.
5828 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5829 */
5830static int hdaAttachInternal(PPDMDEVINS pDevIns, PHDADRIVER pDrv, unsigned uLUN, uint32_t fFlags)
5831{
5832 RT_NOREF(fFlags);
5833 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5834
5835 /*
5836 * Attach driver.
5837 */
5838 char *pszDesc = NULL;
5839 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
5840 AssertReleaseMsgReturn(pszDesc,
5841 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
5842 VERR_NO_MEMORY);
5843
5844 PPDMIBASE pDrvBase;
5845 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
5846 &pThis->IBase, &pDrvBase, pszDesc);
5847 if (RT_SUCCESS(rc))
5848 {
5849 if (pDrv == NULL)
5850 pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
5851 if (pDrv)
5852 {
5853 pDrv->pDrvBase = pDrvBase;
5854 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
5855 AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
5856 pDrv->pHDAState = pThis;
5857 pDrv->uLUN = uLUN;
5858
5859 /*
5860 * For now we always set the driver at LUN 0 as our primary
5861 * host backend. This might change in the future.
5862 */
5863 if (pDrv->uLUN == 0)
5864 pDrv->Flags |= PDMAUDIODRVFLAGS_PRIMARY;
5865
5866 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
5867
5868 /* Attach to driver list if not attached yet. */
5869 if (!pDrv->fAttached)
5870 {
5871 RTListAppend(&pThis->lstDrv, &pDrv->Node);
5872 pDrv->fAttached = true;
5873 }
5874 }
5875 else
5876 rc = VERR_NO_MEMORY;
5877 }
5878 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5879 LogFunc(("No attached driver for LUN #%u\n", uLUN));
5880
5881 if (RT_FAILURE(rc))
5882 {
5883 /* Only free this string on failure;
5884 * must remain valid for the live of the driver instance. */
5885 RTStrFree(pszDesc);
5886 }
5887
5888 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
5889 return rc;
5890}
5891
5892/**
5893 * Attach command.
5894 *
5895 * This is called to let the device attach to a driver for a specified LUN
5896 * during runtime. This is not called during VM construction, the device
5897 * constructor has to attach to all the available drivers.
5898 *
5899 * @returns VBox status code.
5900 * @param pDevIns The device instance.
5901 * @param uLUN The logical unit which is being detached.
5902 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5903 */
5904static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
5905{
5906 return hdaAttachInternal(pDevIns, NULL /* pDrv */, uLUN, fFlags);
5907}
5908
5909static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
5910{
5911 RT_NOREF(pDevIns, uLUN, fFlags);
5912 LogFunc(("iLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
5913}
5914
5915/**
5916 * Powers off the device.
5917 *
5918 * @param pDevIns Device instance to power off.
5919 */
5920static DECLCALLBACK(void) hdaPowerOff(PPDMDEVINS pDevIns)
5921{
5922 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5923
5924 LogRel2(("HDA: Powering off ...\n"));
5925
5926 /* Ditto goes for the codec, which in turn uses the mixer. */
5927 hdaCodecPowerOff(pThis->pCodec);
5928
5929 /**
5930 * Note: Destroy the mixer while powering off and *not* in hdaDestruct,
5931 * giving the mixer the chance to release any references held to
5932 * PDM audio streams it maintains.
5933 */
5934 if (pThis->pMixer)
5935 {
5936 AudioMixerDestroy(pThis->pMixer);
5937 pThis->pMixer = NULL;
5938 }
5939}
5940
5941/**
5942 * Re-attaches a new driver to the device's driver chain.
5943 *
5944 * @returns VBox status code.
5945 * @param pThis Device instance to re-attach driver to.
5946 * @param pDrv Driver instance used for attaching to.
5947 * If NULL is specified, a new driver will be created and appended
5948 * to the driver list.
5949 * @param uLUN The logical unit which is being re-detached.
5950 * @param pszDriver Driver name.
5951 */
5952static int hdaReattach(PHDASTATE pThis, PHDADRIVER pDrv, uint8_t uLUN, const char *pszDriver)
5953{
5954 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
5955 AssertPtrReturn(pszDriver, VERR_INVALID_POINTER);
5956
5957 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
5958 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
5959 PCFGMNODE pDev0 = CFGMR3GetChild(pRoot, "Devices/hda/0/");
5960
5961 /* Remove LUN branch. */
5962 CFGMR3RemoveNode(CFGMR3GetChildF(pDev0, "LUN#%u/", uLUN));
5963
5964 if (pDrv)
5965 {
5966 /* Re-use a driver instance => detach the driver before. */
5967 int rc = PDMDevHlpDriverDetach(pThis->pDevInsR3, PDMIBASE_2_PDMDRV(pDrv->pDrvBase), 0 /* fFlags */);
5968 if (RT_FAILURE(rc))
5969 return rc;
5970 }
5971
5972#define RC_CHECK() if (RT_FAILURE(rc)) { AssertReleaseRC(rc); break; }
5973
5974 int rc = VINF_SUCCESS;
5975 do
5976 {
5977 PCFGMNODE pLunL0;
5978 rc = CFGMR3InsertNodeF(pDev0, &pLunL0, "LUN#%u/", uLUN); RC_CHECK();
5979 rc = CFGMR3InsertString(pLunL0, "Driver", "AUDIO"); RC_CHECK();
5980 rc = CFGMR3InsertNode(pLunL0, "Config/", NULL); RC_CHECK();
5981
5982 PCFGMNODE pLunL1, pLunL2;
5983 rc = CFGMR3InsertNode (pLunL0, "AttachedDriver/", &pLunL1); RC_CHECK();
5984 rc = CFGMR3InsertNode (pLunL1, "Config/", &pLunL2); RC_CHECK();
5985 rc = CFGMR3InsertString(pLunL1, "Driver", pszDriver); RC_CHECK();
5986
5987 rc = CFGMR3InsertString(pLunL2, "AudioDriver", pszDriver); RC_CHECK();
5988
5989 } while (0);
5990
5991 if (RT_SUCCESS(rc))
5992 rc = hdaAttachInternal(pThis->pDevInsR3, pDrv, uLUN, 0 /* fFlags */);
5993
5994 LogFunc(("pThis=%p, uLUN=%u, pszDriver=%s, rc=%Rrc\n", pThis, uLUN, pszDriver, rc));
5995
5996#undef RC_CHECK
5997
5998 return rc;
5999}
6000
6001/**
6002 * @interface_method_impl{PDMDEVREG,pfnConstruct}
6003 */
6004static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
6005{
6006 RT_NOREF(iInstance);
6007 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
6008 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
6009 Assert(iInstance == 0);
6010
6011 /*
6012 * Validations.
6013 */
6014 if (!CFGMR3AreValuesValid(pCfg, "R0Enabled\0"
6015 "RCEnabled\0"
6016 "TimerHz\0"))
6017 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
6018 N_ ("Invalid configuration for the Intel HDA device"));
6019
6020 int rc = CFGMR3QueryBoolDef(pCfg, "RCEnabled", &pThis->fRCEnabled, false);
6021 if (RT_FAILURE(rc))
6022 return PDMDEV_SET_ERROR(pDevIns, rc,
6023 N_("HDA configuration error: failed to read RCEnabled as boolean"));
6024 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, false);
6025 if (RT_FAILURE(rc))
6026 return PDMDEV_SET_ERROR(pDevIns, rc,
6027 N_("HDA configuration error: failed to read R0Enabled as boolean"));
6028#ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
6029 uint16_t uTimerHz;
6030 rc = CFGMR3QueryU16Def(pCfg, "TimerHz", &uTimerHz, HDA_TIMER_HZ /* Default value, if not set. */);
6031 if (RT_FAILURE(rc))
6032 return PDMDEV_SET_ERROR(pDevIns, rc,
6033 N_("HDA configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
6034#endif
6035
6036 /*
6037 * Initialize data (most of it anyway).
6038 */
6039 pThis->pDevInsR3 = pDevIns;
6040 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
6041 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
6042 /* IBase */
6043 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
6044
6045 /* PCI Device */
6046 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
6047 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
6048
6049 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
6050 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
6051 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
6052 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
6053 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
6054 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
6055 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
6056 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
6057 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
6058 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
6059 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
6060
6061#if defined(HDA_AS_PCI_EXPRESS)
6062 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
6063#elif defined(VBOX_WITH_MSI_DEVICES)
6064 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
6065#else
6066 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
6067#endif
6068
6069 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
6070 /// of these values needs to be properly documented!
6071 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
6072 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
6073
6074 /* Power Management */
6075 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
6076 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
6077 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
6078
6079#ifdef HDA_AS_PCI_EXPRESS
6080 /* PCI Express */
6081 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
6082 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
6083 /* Device flags */
6084 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
6085 /* version */ 0x1 |
6086 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
6087 /* MSI */ (100) << 9 );
6088 /* Device capabilities */
6089 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
6090 /* Device control */
6091 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
6092 /* Device status */
6093 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
6094 /* Link caps */
6095 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
6096 /* Link control */
6097 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
6098 /* Link status */
6099 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
6100 /* Slot capabilities */
6101 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
6102 /* Slot control */
6103 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
6104 /* Slot status */
6105 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
6106 /* Root control */
6107 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
6108 /* Root capabilities */
6109 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
6110 /* Root status */
6111 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
6112 /* Device capabilities 2 */
6113 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
6114 /* Device control 2 */
6115 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
6116 /* Link control 2 */
6117 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
6118 /* Slot control 2 */
6119 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
6120#endif
6121
6122 /*
6123 * Register the PCI device.
6124 */
6125 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
6126 if (RT_FAILURE(rc))
6127 return rc;
6128
6129 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
6130 if (RT_FAILURE(rc))
6131 return rc;
6132
6133#ifdef VBOX_WITH_MSI_DEVICES
6134 PDMMSIREG MsiReg;
6135 RT_ZERO(MsiReg);
6136 MsiReg.cMsiVectors = 1;
6137 MsiReg.iMsiCapOffset = 0x60;
6138 MsiReg.iMsiNextOffset = 0x50;
6139 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
6140 if (RT_FAILURE(rc))
6141 {
6142 /* That's OK, we can work without MSI */
6143 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
6144 }
6145#endif
6146
6147 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
6148 if (RT_FAILURE(rc))
6149 return rc;
6150
6151 RTListInit(&pThis->lstDrv);
6152
6153#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
6154 LogRel(("HDA: Asynchronous I/O enabled\n"));
6155#endif
6156
6157 uint8_t uLUN;
6158 for (uLUN = 0; uLUN < UINT8_MAX; ++uLUN)
6159 {
6160 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
6161 rc = hdaAttachInternal(pDevIns, NULL /* pDrv */, uLUN, 0 /* fFlags */);
6162 if (RT_FAILURE(rc))
6163 {
6164 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
6165 rc = VINF_SUCCESS;
6166 else if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
6167 {
6168 hdaReattach(pThis, NULL /* pDrv */, uLUN, "NullAudio");
6169 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
6170 N_("Host audio backend initialization has failed. Selecting the NULL audio backend "
6171 "with the consequence that no sound is audible"));
6172 /* Attaching to the NULL audio backend will never fail. */
6173 rc = VINF_SUCCESS;
6174 }
6175 break;
6176 }
6177 }
6178
6179 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
6180
6181 if (RT_SUCCESS(rc))
6182 {
6183 rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
6184 if (RT_SUCCESS(rc))
6185 {
6186 /*
6187 * Add mixer output sinks.
6188 */
6189#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
6190 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Front",
6191 AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
6192 AssertRC(rc);
6193 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Center / Subwoofer",
6194 AUDMIXSINKDIR_OUTPUT, &pThis->SinkCenterLFE.pMixSink);
6195 AssertRC(rc);
6196 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Rear",
6197 AUDMIXSINKDIR_OUTPUT, &pThis->SinkRear.pMixSink);
6198 AssertRC(rc);
6199#else
6200 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] PCM Output",
6201 AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
6202 AssertRC(rc);
6203#endif
6204 /*
6205 * Add mixer input sinks.
6206 */
6207 rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Line In",
6208 AUDMIXSINKDIR_INPUT, &pThis->SinkLineIn.pMixSink);
6209 AssertRC(rc);
6210#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
6211 rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Microphone In",
6212 AUDMIXSINKDIR_INPUT, &pThis->SinkMicIn.pMixSink);
6213 AssertRC(rc);
6214#endif
6215 /* There is no master volume control. Set the master to max. */
6216 PDMAUDIOVOLUME vol = { false, 255, 255 };
6217 rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
6218 AssertRC(rc);
6219 }
6220 }
6221
6222 if (RT_SUCCESS(rc))
6223 {
6224 /* Construct codec. */
6225 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
6226 if (!pThis->pCodec)
6227 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
6228
6229 /* Set codec callbacks to this controller. */
6230 pThis->pCodec->pfnCbMixerAddStream = hdaMixerAddStream;
6231 pThis->pCodec->pfnCbMixerRemoveStream = hdaMixerRemoveStream;
6232 pThis->pCodec->pfnCbMixerSetStream = hdaMixerSetStream;
6233 pThis->pCodec->pfnCbMixerSetVolume = hdaMixerSetVolume;
6234
6235 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
6236
6237 /* Construct the codec. */
6238 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfg);
6239 if (RT_FAILURE(rc))
6240 AssertRCReturn(rc, rc);
6241
6242 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
6243 verb F20 should provide device/codec recognition. */
6244 Assert(pThis->pCodec->u16VendorId);
6245 Assert(pThis->pCodec->u16DeviceId);
6246 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
6247 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
6248 }
6249
6250 if (RT_SUCCESS(rc))
6251 {
6252 /*
6253 * Create all hardware streams.
6254 */
6255 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
6256 {
6257 rc = hdaStreamCreate(pThis, &pThis->aStreams[i], i /* uSD */);
6258 AssertRC(rc);
6259 }
6260
6261#ifdef VBOX_WITH_AUDIO_HDA_ONETIME_INIT
6262 /*
6263 * Initialize the driver chain.
6264 */
6265 PHDADRIVER pDrv;
6266 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
6267 {
6268 /*
6269 * Only primary drivers are critical for the VM to run. Everything else
6270 * might not worth showing an own error message box in the GUI.
6271 */
6272 if (!(pDrv->Flags & PDMAUDIODRVFLAGS_PRIMARY))
6273 continue;
6274
6275 PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
6276 AssertPtr(pCon);
6277
6278 bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
6279# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
6280 bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
6281# endif
6282 bool fValidOut = AudioMixerStreamIsValid(pDrv->Front.pMixStrm);
6283# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
6284 /** @todo Anything to do here? */
6285# endif
6286
6287 if ( !fValidLineIn
6288# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
6289 && !fValidMicIn
6290# endif
6291 && !fValidOut)
6292 {
6293 LogRel(("HDA: Falling back to NULL backend (no sound audible)\n"));
6294
6295 hdaReset(pDevIns);
6296 hdaReattach(pThis, pDrv, pDrv->uLUN, "NullAudio");
6297
6298 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
6299 N_("No audio devices could be opened. Selecting the NULL audio backend "
6300 "with the consequence that no sound is audible"));
6301 }
6302 else
6303 {
6304 bool fWarn = false;
6305
6306 PDMAUDIOBACKENDCFG backendCfg;
6307 int rc2 = pCon->pfnGetConfig(pCon, &backendCfg);
6308 if (RT_SUCCESS(rc2))
6309 {
6310 if (backendCfg.cMaxStreamsIn)
6311 {
6312# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
6313 /* If the audio backend supports two or more input streams at once,
6314 * warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
6315 if (backendCfg.cMaxStreamsIn >= 2)
6316 fWarn = !fValidLineIn || !fValidMicIn;
6317 /* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
6318 * *not* ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
6319 * One of the two simply is not in use then. */
6320 else if (backendCfg.cMaxStreamsIn == 1)
6321 fWarn = !fValidLineIn && !fValidMicIn;
6322 /* Don't warn if our backend is not able of supporting any input streams at all. */
6323# else /* !VBOX_WITH_AUDIO_HDA_MIC_IN */
6324 /* We only have line-in as input source. */
6325 fWarn = !fValidLineIn;
6326# endif /* VBOX_WITH_AUDIO_HDA_MIC_IN */
6327 }
6328
6329 if ( !fWarn
6330 && backendCfg.cMaxStreamsOut)
6331 {
6332 fWarn = !fValidOut;
6333 }
6334 }
6335 else
6336 {
6337 LogRel(("HDA: Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
6338 fWarn = true;
6339 }
6340
6341 if (fWarn)
6342 {
6343 char szMissingStreams[255];
6344 size_t len = 0;
6345 if (!fValidLineIn)
6346 {
6347 LogRel(("HDA: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
6348 len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
6349 }
6350# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
6351 if (!fValidMicIn)
6352 {
6353 LogRel(("HDA: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
6354 len += RTStrPrintf(szMissingStreams + len,
6355 sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
6356 }
6357# endif /* VBOX_WITH_AUDIO_HDA_MIC_IN */
6358 if (!fValidOut)
6359 {
6360 LogRel(("HDA: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
6361 len += RTStrPrintf(szMissingStreams + len,
6362 sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
6363 }
6364
6365 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
6366 N_("Some HDA audio streams (%s) could not be opened. Guest applications generating audio "
6367 "output or depending on audio input may hang. Make sure your host audio device "
6368 "is working properly. Check the logfile for error messages of the audio "
6369 "subsystem"), szMissingStreams);
6370 }
6371 }
6372 }
6373#endif /* VBOX_WITH_AUDIO_HDA_ONETIME_INIT */
6374 }
6375
6376 if (RT_SUCCESS(rc))
6377 {
6378 hdaReset(pDevIns);
6379
6380 /*
6381 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
6382 * hdaReset shouldn't affects these registers.
6383 */
6384 HDA_REG(pThis, WAKEEN) = 0x0;
6385 HDA_REG(pThis, STATESTS) = 0x0;
6386
6387#ifdef DEBUG
6388 /*
6389 * Debug and string formatter types.
6390 */
6391 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaDbgInfo);
6392 PDMDevHlpDBGFInfoRegister(pDevIns, "hdabdle", "HDA stream BDLE info. (hdabdle [stream number])", hdaDbgInfoBDLE);
6393 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaDbgInfoStream);
6394 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaDbgInfoCodecNodes);
6395 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaDbgInfoCodecSelector);
6396 PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaDbgInfoMixer);
6397
6398 rc = RTStrFormatTypeRegister("bdle", hdaDbgFmtBDLE, NULL);
6399 AssertRC(rc);
6400 rc = RTStrFormatTypeRegister("sdctl", hdaDbgFmtSDCTL, NULL);
6401 AssertRC(rc);
6402 rc = RTStrFormatTypeRegister("sdsts", hdaDbgFmtSDSTS, NULL);
6403 AssertRC(rc);
6404 rc = RTStrFormatTypeRegister("sdfifos", hdaDbgFmtSDFIFOS, NULL);
6405 AssertRC(rc);
6406 rc = RTStrFormatTypeRegister("sdfifow", hdaDbgFmtSDFIFOW, NULL);
6407 AssertRC(rc);
6408#endif /* DEBUG */
6409
6410 /*
6411 * Some debug assertions.
6412 */
6413 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
6414 {
6415 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
6416 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
6417
6418 /* binary search order. */
6419 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
6420 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6421 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
6422
6423 /* alignment. */
6424 AssertReleaseMsg( pReg->size == 1
6425 || (pReg->size == 2 && (pReg->offset & 1) == 0)
6426 || (pReg->size == 3 && (pReg->offset & 3) == 0)
6427 || (pReg->size == 4 && (pReg->offset & 3) == 0),
6428 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6429
6430 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
6431 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
6432 if (pReg->offset & 3)
6433 {
6434 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
6435 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6436 if (pPrevReg)
6437 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
6438 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6439 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
6440 }
6441#if 0
6442 if ((pReg->offset + pReg->size) & 3)
6443 {
6444 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6445 if (pNextReg)
6446 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
6447 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6448 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
6449 }
6450#endif
6451 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
6452 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
6453 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6454 }
6455 }
6456
6457# ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
6458 if (RT_SUCCESS(rc))
6459 {
6460 /* Create the emulation timer. */
6461 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
6462 TMTIMER_FLAGS_NO_CRIT_SECT, "DevHDA", &pThis->pTimer);
6463 AssertRCReturn(rc, rc);
6464
6465 if (RT_SUCCESS(rc))
6466 {
6467 pThis->cTimerTicks = TMTimerGetFreq(pThis->pTimer) / uTimerHz;
6468 pThis->uTimerTS = TMTimerGet(pThis->pTimer);
6469 LogFunc(("Timer ticks=%RU64 (%RU16 Hz)\n", pThis->cTimerTicks, uTimerHz));
6470 }
6471 }
6472# else
6473 if (RT_SUCCESS(rc))
6474 {
6475 PHDADRIVER pDrv;
6476 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
6477 {
6478 /* Only register primary driver.
6479 * The device emulation does the output multiplexing then. */
6480 if (pDrv->Flags != PDMAUDIODRVFLAGS_PRIMARY)
6481 continue;
6482
6483 PDMAUDIOCALLBACK AudioCallbacks[2];
6484
6485 HDACALLBACKCTX Ctx = { pThis, pDrv };
6486
6487 AudioCallbacks[0].enmType = PDMAUDIOCALLBACKTYPE_INPUT;
6488 AudioCallbacks[0].pfnCallback = hdaCallbackInput;
6489 AudioCallbacks[0].pvCtx = &Ctx;
6490 AudioCallbacks[0].cbCtx = sizeof(HDACALLBACKCTX);
6491
6492 AudioCallbacks[1].enmType = PDMAUDIOCALLBACKTYPE_OUTPUT;
6493 AudioCallbacks[1].pfnCallback = hdaCallbackOutput;
6494 AudioCallbacks[1].pvCtx = &Ctx;
6495 AudioCallbacks[1].cbCtx = sizeof(HDACALLBACKCTX);
6496
6497 rc = pDrv->pConnector->pfnRegisterCallbacks(pDrv->pConnector, AudioCallbacks, RT_ELEMENTS(AudioCallbacks));
6498 if (RT_FAILURE(rc))
6499 break;
6500 }
6501 }
6502# endif
6503
6504# ifdef VBOX_WITH_STATISTICS
6505 if (RT_SUCCESS(rc))
6506 {
6507 /*
6508 * Register statistics.
6509 */
6510# ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
6511 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
6512# endif
6513 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIn, STAMTYPE_PROFILE, "/Devices/HDA/Input", STAMUNIT_TICKS_PER_CALL, "Profiling input.");
6514 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatOut, STAMTYPE_PROFILE, "/Devices/HDA/Output", STAMUNIT_TICKS_PER_CALL, "Profiling output.");
6515 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
6516 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
6517 }
6518# endif
6519
6520#ifdef HDA_DEBUG_DUMP_PCM_DATA
6521 RTFileDelete(HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaDMARead.pcm");
6522 RTFileDelete(HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaDMAWrite.pcm");
6523 RTFileDelete(HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaStreamRead.pcm");
6524 RTFileDelete(HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaStreamWrite.pcm");
6525#endif
6526
6527 LogFlowFuncLeaveRC(rc);
6528 return rc;
6529}
6530
6531/**
6532 * The device registration structure.
6533 */
6534const PDMDEVREG g_DeviceHDA =
6535{
6536 /* u32Version */
6537 PDM_DEVREG_VERSION,
6538 /* szName */
6539 "hda",
6540 /* szRCMod */
6541 "VBoxDDRC.rc",
6542 /* szR0Mod */
6543 "VBoxDDR0.r0",
6544 /* pszDescription */
6545 "Intel HD Audio Controller",
6546 /* fFlags */
6547 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
6548 /* fClass */
6549 PDM_DEVREG_CLASS_AUDIO,
6550 /* cMaxInstances */
6551 1,
6552 /* cbInstance */
6553 sizeof(HDASTATE),
6554 /* pfnConstruct */
6555 hdaConstruct,
6556 /* pfnDestruct */
6557 hdaDestruct,
6558 /* pfnRelocate */
6559 NULL,
6560 /* pfnMemSetup */
6561 NULL,
6562 /* pfnPowerOn */
6563 NULL,
6564 /* pfnReset */
6565 hdaReset,
6566 /* pfnSuspend */
6567 NULL,
6568 /* pfnResume */
6569 NULL,
6570 /* pfnAttach */
6571 hdaAttach,
6572 /* pfnDetach */
6573 hdaDetach,
6574 /* pfnQueryInterface. */
6575 NULL,
6576 /* pfnInitComplete */
6577 NULL,
6578 /* pfnPowerOff */
6579 hdaPowerOff,
6580 /* pfnSoftReset */
6581 NULL,
6582 /* u32VersionEnd */
6583 PDM_DEVREG_VERSION
6584};
6585
6586#endif /* IN_RING3 */
6587#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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