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source: vbox/trunk/src/VBox/Devices/Audio/DevHDA.cpp@ 65070

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1/* $Id: DevHDA.cpp 65070 2017-01-03 11:34:35Z vboxsync $ */
2/** @file
3 * DevHDA - VBox Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2016 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22
23/*********************************************************************************************************************************
24* Header Files *
25*********************************************************************************************************************************/
26#define LOG_GROUP LOG_GROUP_DEV_HDA
27#include <VBox/log.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/pdmaudioifs.h>
30#include <VBox/version.h>
31
32#include <iprt/assert.h>
33#include <iprt/asm.h>
34#include <iprt/asm-math.h>
35#include <iprt/file.h>
36#include <iprt/list.h>
37#ifdef IN_RING3
38# include <iprt/mem.h>
39# include <iprt/semaphore.h>
40# include <iprt/string.h>
41# include <iprt/uuid.h>
42#endif
43
44#include "VBoxDD.h"
45
46#include "AudioMixBuffer.h"
47#include "AudioMixer.h"
48#include "HDACodec.h"
49#include "DevHDACommon.h"
50#include "DrvAudio.h"
51
52
53/*********************************************************************************************************************************
54* Defined Constants And Macros *
55*********************************************************************************************************************************/
56//#define HDA_AS_PCI_EXPRESS
57#define VBOX_WITH_INTEL_HDA
58
59/*
60 * HDA_DEBUG_DUMP_PCM_DATA enables dumping the raw PCM data
61 * to a file on the host. Be sure to adjust HDA_DEBUG_DUMP_PCM_DATA_PATH
62 * to your needs before using this!
63 */
64//#define HDA_DEBUG_DUMP_PCM_DATA
65#ifdef HDA_DEBUG_DUMP_PCM_DATA
66# ifdef RT_OS_WINDOWS
67# define HDA_DEBUG_DUMP_PCM_DATA_PATH "c:\\temp\\"
68# else
69# define HDA_DEBUG_DUMP_PCM_DATA_PATH "/tmp/"
70# endif
71#endif
72
73#if defined(VBOX_WITH_HP_HDA)
74/* HP Pavilion dv4t-1300 */
75# define HDA_PCI_VENDOR_ID 0x103c
76# define HDA_PCI_DEVICE_ID 0x30f7
77#elif defined(VBOX_WITH_INTEL_HDA)
78/* Intel HDA controller */
79# define HDA_PCI_VENDOR_ID 0x8086
80# define HDA_PCI_DEVICE_ID 0x2668
81#elif defined(VBOX_WITH_NVIDIA_HDA)
82/* nVidia HDA controller */
83# define HDA_PCI_VENDOR_ID 0x10de
84# define HDA_PCI_DEVICE_ID 0x0ac0
85#else
86# error "Please specify your HDA device vendor/device IDs"
87#endif
88
89/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
90 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
91 * is read only except for bit 15 like the HDA spec states.
92 *
93 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
94 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
95#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
96
97/* Make sure that interleaving streams support is enabled if the 5.1 surround code is being used. */
98#if defined (VBOX_WITH_AUDIO_HDA_51_SURROUND) && !defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT)
99# define VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT
100#endif
101
102/** Default timer frequency (in Hz). */
103#define HDA_TIMER_HZ 100
104
105/**
106 * At the moment we support 4 input + 4 output streams max, which is 8 in total.
107 * Bidirectional streams are currently *not* supported.
108 *
109 * Note: When changing any of those values, be prepared for some saved state
110 * fixups / trouble!
111 */
112#define HDA_MAX_SDI 4
113#define HDA_MAX_SDO 4
114#define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
115AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
116
117/** Number of general registers. */
118#define HDA_NUM_GENERAL_REGS 34
119/** Number of total registers in the HDA's register map. */
120#define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */))
121/** Total number of stream tags (channels). Index 0 is reserved / invalid. */
122#define HDA_MAX_TAGS 16
123
124/**
125 * NB: Register values stored in memory (au32Regs[]) are indexed through
126 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
127 * register descriptors in g_aHdaRegMap[] are indexed through the
128 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
129 *
130 * The au32Regs[] layout is kept unchanged for saved state
131 * compatibility.
132 */
133
134/* Registers */
135#define HDA_REG_IND_NAME(x) HDA_REG_##x
136#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
137#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
138#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
139#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
140#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
141#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
142#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
143
144
145#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
146#define HDA_RMX_GCAP 0
147/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
148 * oss (15:12) - number of output streams supported
149 * iss (11:8) - number of input streams supported
150 * bss (7:3) - number of bidirectional streams supported
151 * bds (2:1) - number of serial data out (SDO) signals supported
152 * b64sup (0) - 64 bit addressing supported.
153 */
154#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
155 ( (((oss) & 0xF) << 12) \
156 | (((iss) & 0xF) << 8) \
157 | (((bss) & 0x1F) << 3) \
158 | (((bds) & 0x3) << 1) \
159 | ((b64sup) & 1))
160
161#define HDA_REG_VMIN 1 /* 0x02 */
162#define HDA_RMX_VMIN 1
163
164#define HDA_REG_VMAJ 2 /* 0x03 */
165#define HDA_RMX_VMAJ 2
166
167#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
168#define HDA_RMX_OUTPAY 3
169
170#define HDA_REG_INPAY 4 /* 0x06-0x07 */
171#define HDA_RMX_INPAY 4
172
173#define HDA_REG_GCTL 5 /* 0x08-0x0B */
174#define HDA_RMX_GCTL 5
175#define HDA_GCTL_RST_SHIFT 0
176#define HDA_GCTL_FSH_SHIFT 1
177#define HDA_GCTL_UR_SHIFT 8
178
179#define HDA_REG_WAKEEN 6 /* 0x0C */
180#define HDA_RMX_WAKEEN 6
181
182#define HDA_REG_STATESTS 7 /* 0x0E */
183#define HDA_RMX_STATESTS 7
184#define HDA_STATESTS_SCSF_MASK 0x7 /* State Change Status Flags (6.2.8). */
185
186#define HDA_REG_GSTS 8 /* 0x10-0x11*/
187#define HDA_RMX_GSTS 8
188#define HDA_GSTS_FSH_SHIFT 1
189
190#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
191#define HDA_RMX_OUTSTRMPAY 112
192
193#define HDA_REG_INSTRMPAY 10 /* 0x1a */
194#define HDA_RMX_INSTRMPAY 113
195
196#define HDA_REG_INTCTL 11 /* 0x20 */
197#define HDA_RMX_INTCTL 9
198#define HDA_INTCTL_GIE_SHIFT 31
199#define HDA_INTCTL_CIE_SHIFT 30
200#define HDA_INTCTL_S0_SHIFT 0
201#define HDA_INTCTL_S1_SHIFT 1
202#define HDA_INTCTL_S2_SHIFT 2
203#define HDA_INTCTL_S3_SHIFT 3
204#define HDA_INTCTL_S4_SHIFT 4
205#define HDA_INTCTL_S5_SHIFT 5
206#define HDA_INTCTL_S6_SHIFT 6
207#define HDA_INTCTL_S7_SHIFT 7
208#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
209#define HDA_INTCTL_GIE_MASK RT_BIT(31) /* Global Interrupt Enable (3.3.14). */
210
211#define HDA_REG_INTSTS 12 /* 0x24 */
212#define HDA_RMX_INTSTS 10
213#define HDA_INTSTS_GIS_SHIFT 31
214#define HDA_INTSTS_CIS_SHIFT 30
215#define HDA_INTSTS_S0_SHIFT 0
216#define HDA_INTSTS_S1_SHIFT 1
217#define HDA_INTSTS_S2_SHIFT 2
218#define HDA_INTSTS_S3_SHIFT 3
219#define HDA_INTSTS_S4_SHIFT 4
220#define HDA_INTSTS_S5_SHIFT 5
221#define HDA_INTSTS_S6_SHIFT 6
222#define HDA_INTSTS_S7_SHIFT 7
223#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
224
225#define HDA_REG_WALCLK 13 /* 0x30 */
226#define HDA_RMX_WALCLK /* Not defined! */
227
228/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
229 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
230 * the datasheet.
231 */
232#define HDA_REG_SSYNC 14 /* 0x38 */
233#define HDA_RMX_SSYNC 12
234
235#define HDA_REG_CORBLBASE 15 /* 0x40 */
236#define HDA_RMX_CORBLBASE 13
237
238#define HDA_REG_CORBUBASE 16 /* 0x44 */
239#define HDA_RMX_CORBUBASE 14
240
241#define HDA_REG_CORBWP 17 /* 0x48 */
242#define HDA_RMX_CORBWP 15
243
244#define HDA_REG_CORBRP 18 /* 0x4A */
245#define HDA_RMX_CORBRP 16
246#define HDA_CORBRP_RST_SHIFT 15
247#define HDA_CORBRP_WP_SHIFT 0
248#define HDA_CORBRP_WP_MASK 0xFF
249
250#define HDA_REG_CORBCTL 19 /* 0x4C */
251#define HDA_RMX_CORBCTL 17
252#define HDA_CORBCTL_DMA_SHIFT 1
253#define HDA_CORBCTL_CMEIE_SHIFT 0
254
255#define HDA_REG_CORBSTS 20 /* 0x4D */
256#define HDA_RMX_CORBSTS 18
257#define HDA_CORBSTS_CMEI_SHIFT 0
258
259#define HDA_REG_CORBSIZE 21 /* 0x4E */
260#define HDA_RMX_CORBSIZE 19
261#define HDA_CORBSIZE_SZ_CAP 0xF0
262#define HDA_CORBSIZE_SZ 0x3
263/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
264
265#define HDA_REG_RIRBLBASE 22 /* 0x50 */
266#define HDA_RMX_RIRBLBASE 20
267
268#define HDA_REG_RIRBUBASE 23 /* 0x54 */
269#define HDA_RMX_RIRBUBASE 21
270
271#define HDA_REG_RIRBWP 24 /* 0x58 */
272#define HDA_RMX_RIRBWP 22
273#define HDA_RIRBWP_RST_SHIFT 15
274#define HDA_RIRBWP_WP_MASK 0xFF
275
276#define HDA_REG_RINTCNT 25 /* 0x5A */
277#define HDA_RMX_RINTCNT 23
278#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
279
280#define HDA_REG_RIRBCTL 26 /* 0x5C */
281#define HDA_RMX_RIRBCTL 24
282#define HDA_RIRBCTL_RIC_SHIFT 0
283#define HDA_RIRBCTL_DMA_SHIFT 1
284#define HDA_ROI_DMA_SHIFT 2
285
286#define HDA_REG_RIRBSTS 27 /* 0x5D */
287#define HDA_RMX_RIRBSTS 25
288#define HDA_RIRBSTS_RINTFL_SHIFT 0
289#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
290
291#define HDA_REG_RIRBSIZE 28 /* 0x5E */
292#define HDA_RMX_RIRBSIZE 26
293#define HDA_RIRBSIZE_SZ_CAP 0xF0
294#define HDA_RIRBSIZE_SZ 0x3
295
296#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
297#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
298
299
300#define HDA_REG_IC 29 /* 0x60 */
301#define HDA_RMX_IC 27
302
303#define HDA_REG_IR 30 /* 0x64 */
304#define HDA_RMX_IR 28
305
306#define HDA_REG_IRS 31 /* 0x68 */
307#define HDA_RMX_IRS 29
308#define HDA_IRS_ICB_SHIFT 0
309#define HDA_IRS_IRV_SHIFT 1
310
311#define HDA_REG_DPLBASE 32 /* 0x70 */
312#define HDA_RMX_DPLBASE 30
313#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
314
315#define HDA_REG_DPUBASE 33 /* 0x74 */
316#define HDA_RMX_DPUBASE 31
317#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
318
319#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
320
321#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
322#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
323/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
324#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
325
326#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
327
328/** @todo Condense marcos! */
329
330#define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80 */
331#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
332#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
333#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
334#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
335#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
336#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
337#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
338#define HDA_RMX_SD0CTL 32
339#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
340#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
341#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
342#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
343#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
344#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
345#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
346
347#define SD(func, num) SD##num##func
348
349#define HDA_SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
350#define HDA_SDCTL_NUM(pThis, num) ((HDA_SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
351#define HDA_SDCTL_NUM_MASK 0xF
352#define HDA_SDCTL_NUM_SHIFT 20
353#define HDA_SDCTL_DIR_SHIFT 19
354#define HDA_SDCTL_TP_SHIFT 18
355#define HDA_SDCTL_STRIPE_MASK 0x3
356#define HDA_SDCTL_STRIPE_SHIFT 16
357#define HDA_SDCTL_DEIE_SHIFT 4
358#define HDA_SDCTL_FEIE_SHIFT 3
359#define HDA_SDCTL_ICE_SHIFT 2
360#define HDA_SDCTL_RUN_SHIFT 1
361#define HDA_SDCTL_SRST_SHIFT 0
362
363#define HDA_REG_SD0STS 35 /* 0x83 */
364#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
365#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
366#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
367#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
368#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
369#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
370#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
371#define HDA_RMX_SD0STS 33
372#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
373#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
374#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
375#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
376#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
377#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
378#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
379
380#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
381#define HDA_SDSTS_FIFORDY_SHIFT 5
382#define HDA_SDSTS_DE_SHIFT 4
383#define HDA_SDSTS_FE_SHIFT 3
384#define HDA_SDSTS_BCIS_SHIFT 2
385
386#define HDA_REG_SD0LPIB 36 /* 0x84 */
387#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
388#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
389#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
390#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
391#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
392#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
393#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
394#define HDA_RMX_SD0LPIB 34
395#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
396#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
397#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
398#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
399#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
400#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
401#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
402
403#define HDA_REG_SD0CBL 37 /* 0x88 */
404#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
405#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
406#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
407#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
408#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
409#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
410#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
411#define HDA_RMX_SD0CBL 35
412#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
413#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
414#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
415#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
416#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
417#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
418#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
419
420#define HDA_REG_SD0LVI 38 /* 0x8C */
421#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
422#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
423#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
424#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
425#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
426#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
427#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
428#define HDA_RMX_SD0LVI 36
429#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
430#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
431#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
432#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
433#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
434#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
435#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
436
437#define HDA_REG_SD0FIFOW 39 /* 0x8E */
438#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
439#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
440#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
441#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
442#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
443#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
444#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
445#define HDA_RMX_SD0FIFOW 37
446#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
447#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
448#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
449#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
450#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
451#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
452#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
453
454/*
455 * ICH6 datasheet defined limits for FIFOW values (18.2.38).
456 */
457#define HDA_SDFIFOW_8B 0x2
458#define HDA_SDFIFOW_16B 0x3
459#define HDA_SDFIFOW_32B 0x4
460
461#define HDA_REG_SD0FIFOS 40 /* 0x90 */
462#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
463#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
464#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
465#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
466#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
467#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
468#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
469#define HDA_RMX_SD0FIFOS 38
470#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
471#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
472#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
473#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
474#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
475#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
476#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
477
478/*
479 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
480 * formula: size - 1
481 * Other values not listed are not supported.
482 */
483/** Maximum FIFO size (in bytes). */
484#define HDA_FIFO_MAX 256
485
486#define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
487#define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
488
489#define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
490#define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
491#define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
492#define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
493#define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
494#define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
495#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
496
497#define HDA_REG_SD0FMT 41 /* 0x92 */
498#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
499#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
500#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
501#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
502#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
503#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
504#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
505#define HDA_RMX_SD0FMT 39
506#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
507#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
508#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
509#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
510#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
511#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
512#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
513
514#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
515#define HDA_SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
516#define HDA_SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
517#define HDA_SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
518
519#define HDA_REG_SD0BDPL 42 /* 0x98 */
520#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
521#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
522#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
523#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
524#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
525#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
526#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
527#define HDA_RMX_SD0BDPL 40
528#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
529#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
530#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
531#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
532#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
533#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
534#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
535
536#define HDA_REG_SD0BDPU 43 /* 0x9C */
537#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
538#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
539#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
540#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
541#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
542#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
543#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
544#define HDA_RMX_SD0BDPU 41
545#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
546#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
547#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
548#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
549#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
550#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
551#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
552
553#define HDA_BDLE_FLAG_IOC RT_BIT(0) /* Interrupt on completion (IOC). */
554
555#define HDA_CODEC_CAD_SHIFT 28
556/* Encodes the (required) LUN into a codec command. */
557#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
558
559
560
561/*********************************************************************************************************************************
562* Structures and Typedefs *
563*********************************************************************************************************************************/
564
565/**
566 * Internal state of a Buffer Descriptor List Entry (BDLE),
567 * needed to keep track of the data needed for the actual device
568 * emulation.
569 */
570typedef struct HDABDLESTATE
571{
572 /** Own index within the BDL (Buffer Descriptor List). */
573 uint32_t u32BDLIndex;
574 /** Number of bytes below the stream's FIFO watermark (SDFIFOW).
575 * Used to check if we need fill up the FIFO again. */
576 uint32_t cbBelowFIFOW;
577 /** Current offset in DMA buffer (in bytes).*/
578 uint32_t u32BufOff;
579 uint32_t Padding;
580} HDABDLESTATE, *PHDABDLESTATE;
581
582/**
583 * BDL description structure.
584 * Do not touch this, as this must match to the HDA specs.
585 */
586typedef struct HDABDLEDESC
587{
588 /** Starting address of the actual buffer. Must be 128-bit aligned. */
589 uint64_t u64BufAdr;
590 /** Size of the actual buffer (in bytes). */
591 uint32_t u32BufSize;
592 /** Bit 0: Interrupt on completion; the controller will generate
593 * an interrupt when the last byte of the buffer has been
594 * fetched by the DMA engine.
595 *
596 * Rest is reserved for further use and must be 0. */
597 uint32_t fFlags;
598} HDABDLEDESC, *PHDABDLEDESC;
599AssertCompileSize(HDABDLEDESC, 16); /* Always 16 byte. Also must be aligned on 128-byte boundary. */
600
601/**
602 * Buffer Descriptor List Entry (BDLE) (3.6.3).
603 */
604typedef struct HDABDLE
605{
606 /** The actual BDL description. */
607 HDABDLEDESC Desc;
608 /** Internal state of this BDLE.
609 * Not part of the actual BDLE registers. */
610 HDABDLESTATE State;
611} HDABDLE, *PHDABDLE;
612
613/**
614 * Structure for keeping an audio stream data mapping.
615 */
616typedef struct HDASTREAMMAPPING
617{
618 /** The stream's layout. */
619 PDMAUDIOSTREAMLAYOUT enmLayout;
620 /** Number of audio channels in this stream. */
621 uint8_t cChannels;
622 /** Array of audio channels. */
623 R3PTRTYPE(PPDMAUDIOSTREAMCHANNEL) paChannels;
624 /** Circular buffer holding for holding audio data for this mapping. */
625 R3PTRTYPE(PRTCIRCBUF) pCircBuf;
626} HDASTREAMMAPPING, *PHDASTREAMMAPPING;
627
628#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
629/**
630 * Structure keeping the HDA stream's state for asynchronous I/O.
631 */
632typedef struct HDASTREAMSTATEAIO
633{
634 /** Thread handle for the actual I/O thread. */
635 RTTHREAD Thread;
636 /** Event for letting the thread know there is some data to process. */
637 RTSEMEVENT Event;
638 /** Critical section for synchronizing access. */
639 RTCRITSECT CritSect;
640 /** Started indicator. */
641 volatile bool fStarted;
642 /** Shutdown indicator. */
643 volatile bool fShutdown;
644 uint32_t Padding1;
645} HDASTREAMSTATEAIO, *PHDASTREAMSTATEAIO;
646#endif
647
648/**
649 * Internal state of a HDA stream.
650 */
651typedef struct HDASTREAMSTATE
652{
653 /** Current BDLE to use. Wraps around to 0 if
654 * maximum (cBDLE) is reached. */
655 uint16_t uCurBDLE;
656 /** Flag indicating whether this stream currently is
657 * in reset mode and therefore not acccessible by the guest. */
658 volatile bool fInReset;
659 /** Unused, padding. */
660 uint32_t Padding0;
661 /** Critical section to serialize access. */
662 RTCRITSECT CritSect;
663#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
664 /** Asynchronous I/O state members. */
665 HDASTREAMSTATEAIO AIO;
666#endif
667 /** This stream's data mapping. */
668 HDASTREAMMAPPING Mapping;
669 /** Current BDLE (Buffer Descriptor List Entry). */
670 HDABDLE BDLE;
671 /** Circular buffer (FIFO) for holding DMA'ed data. */
672 R3PTRTYPE(PRTCIRCBUF) pCircBuf;
673} HDASTREAMSTATE, *PHDASTREAMSTATE;
674
675/**
676 * Structure defining an HDA mixer sink.
677 * Its purpose is to know which audio mixer sink is bound to
678 * which SDn (SDI/SDO) device stream.
679 *
680 * This is needed in order to handle interleaved streams
681 * (that is, multiple channels in one stream) or non-interleaved
682 * streams (each channel has a dedicated stream).
683 *
684 * This is only known to the actual device emulation level.
685 */
686typedef struct HDAMIXERSINK
687{
688 /** SDn ID this sink is assigned to. 0 if not assigned. */
689 uint8_t uSD;
690 /** Channel ID of SDn ID. Only valid if SDn ID is valid. */
691 uint8_t uChannel;
692 uint8_t Padding[3];
693 /** Pointer to the actual audio mixer sink. */
694 R3PTRTYPE(PAUDMIXSINK) pMixSink;
695} HDAMIXERSINK, *PHDAMIXERSINK;
696
697/**
698 * Structure for keeping a HDA stream (SDI / SDO).
699 *
700 * Note: This HDA stream has nothing to do with a regular audio stream handled
701 * by the audio connector or the audio mixer. This HDA stream is a serial data in/out
702 * stream (SDI/SDO) defined in hardware and can contain multiple audio streams
703 * in one single SDI/SDO (interleaving streams).
704 *
705 * How a specific SDI/SDO is mapped to our internal audio streams relies on the
706 * stream channel mappings.
707 *
708 * Contains only register values which do *not* change until a
709 * stream reset occurs.
710 */
711typedef struct HDASTREAM
712{
713 /** Stream descriptor number (SDn). */
714 uint8_t u8SD;
715 uint8_t Padding0[7];
716 /** DMA base address (SDnBDPU - SDnBDPL). */
717 uint64_t u64BDLBase;
718 /** Cyclic Buffer Length (SDnCBL).
719 * Represents the size of the ring buffer. */
720 uint32_t u32CBL;
721 /** Format (SDnFMT). */
722 uint16_t u16FMT;
723 /** FIFO Size (FIFOS).
724 * Maximum number of bytes that may have been DMA'd into
725 * memory but not yet transmitted on the link. */
726 uint16_t u16FIFOS;
727 /** FIFO Watermark. */
728 uint16_t u16FIFOW;
729 /** Last Valid Index (SDnLVI). */
730 uint16_t u16LVI;
731 uint16_t Padding1[2];
732 /** Pointer to HDA sink this stream is attached to. */
733 R3PTRTYPE(PHDAMIXERSINK) pMixSink;
734 /** Internal state of this stream. */
735 HDASTREAMSTATE State;
736} HDASTREAM, *PHDASTREAM;
737
738#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
739/**
740 * Structure for keeping a HDA stream thread context.
741 */
742typedef struct HDASTREAMTHREADCTX
743{
744 PHDASTATE pThis;
745 PHDASTREAM pStream;
746} HDASTREAMTHREADCTX, *PHDASTREAMTHREADCTX;
747#endif
748
749/**
750 * Structure for mapping a stream tag to an HDA stream.
751 */
752typedef struct HDATAG
753{
754 /** Own stream tag. */
755 uint8_t uTag;
756 uint8_t Padding[7];
757 /** Pointer to associated stream. */
758 R3PTRTYPE(PHDASTREAM) pStrm;
759} HDATAG, *PHDATAG;
760
761/**
762 * Structure defining a (host backend) driver stream.
763 * Each driver has its own instances of audio mixer streams, which then
764 * can go into the same (or even different) audio mixer sinks.
765 */
766typedef struct HDADRIVERSTREAM
767{
768 union
769 {
770 /** Desired playback destination (for an output stream). */
771 PDMAUDIOPLAYBACKDEST Dest;
772 /** Desired recording source (for an input stream). */
773 PDMAUDIORECSOURCE Source;
774 } DestSource;
775 uint8_t Padding1[4];
776 /** Associated mixer handle. */
777 R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
778} HDADRIVERSTREAM, *PHDADRIVERSTREAM;
779
780/**
781 * Struct for maintaining a host backend driver.
782 * This driver must be associated to one, and only one,
783 * HDA codec. The HDA controller does the actual multiplexing
784 * of HDA codec data to various host backend drivers then.
785 *
786 * This HDA device uses a timer in order to synchronize all
787 * read/write accesses across all attached LUNs / backends.
788 */
789typedef struct HDADRIVER
790{
791 /** Node for storing this driver in our device driver list of HDASTATE. */
792 RTLISTNODER3 Node;
793 /** Pointer to HDA controller (state). */
794 R3PTRTYPE(PHDASTATE) pHDAState;
795 /** Driver flags. */
796 PDMAUDIODRVFLAGS Flags;
797 uint8_t u32Padding0[2];
798 /** LUN to which this driver has been assigned. */
799 uint8_t uLUN;
800 /** Whether this driver is in an attached state or not. */
801 bool fAttached;
802 /** Pointer to attached driver base interface. */
803 R3PTRTYPE(PPDMIBASE) pDrvBase;
804 /** Audio connector interface to the underlying host backend. */
805 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
806 /** Mixer stream for line input. */
807 HDADRIVERSTREAM LineIn;
808#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
809 /** Mixer stream for mic input. */
810 HDADRIVERSTREAM MicIn;
811#endif
812 /** Mixer stream for front output. */
813 HDADRIVERSTREAM Front;
814#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
815 /** Mixer stream for center/LFE output. */
816 HDADRIVERSTREAM CenterLFE;
817 /** Mixer stream for rear output. */
818 HDADRIVERSTREAM Rear;
819#endif
820} HDADRIVER;
821
822/**
823 * ICH Intel HD Audio Controller state.
824 */
825typedef struct HDASTATE
826{
827 /** The PCI device structure. */
828 PDMPCIDEV PciDev;
829 /** R3 Pointer to the device instance. */
830 PPDMDEVINSR3 pDevInsR3;
831 /** R0 Pointer to the device instance. */
832 PPDMDEVINSR0 pDevInsR0;
833 /** R0 Pointer to the device instance. */
834 PPDMDEVINSRC pDevInsRC;
835 /** Padding for alignment. */
836 uint32_t u32Padding;
837 /** The base interface for LUN\#0. */
838 PDMIBASE IBase;
839 RTGCPHYS MMIOBaseAddr;
840 /** The HDA's register set. */
841 uint32_t au32Regs[HDA_NUM_REGS];
842 /** Internal stream states. */
843 HDASTREAM aStreams[HDA_MAX_STREAMS];
844 /** Mapping table between stream tags and stream states. */
845 HDATAG aTags[HDA_MAX_TAGS];
846 /** CORB buffer base address. */
847 uint64_t u64CORBBase;
848 /** RIRB buffer base address. */
849 uint64_t u64RIRBBase;
850 /** DMA base address.
851 * Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
852 uint64_t u64DPBase;
853 /** DMA position buffer enable bit. */
854 bool fDMAPosition;
855 /** Padding for alignment. */
856 uint8_t u8Padding0[7];
857 /** Pointer to CORB buffer. */
858 R3PTRTYPE(uint32_t *) pu32CorbBuf;
859 /** Size in bytes of CORB buffer. */
860 uint32_t cbCorbBuf;
861 /** Padding for alignment. */
862 uint32_t u32Padding1;
863 /** Pointer to RIRB buffer. */
864 R3PTRTYPE(uint64_t *) pu64RirbBuf;
865 /** Size in bytes of RIRB buffer. */
866 uint32_t cbRirbBuf;
867 /** Indicates if HDA controller is in reset mode. */
868 bool fInReset;
869 /** Flag whether the R0 part is enabled. */
870 bool fR0Enabled;
871 /** Flag whether the RC part is enabled. */
872 bool fRCEnabled;
873 /** Number of active (running) SDn streams. */
874 uint8_t cStreamsActive;
875#ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
876 /** The timer for pumping data thru the attached LUN drivers. */
877 PTMTIMERR3 pTimer;
878 /** Flag indicating whether the timer is active or not. */
879 bool fTimerActive;
880 uint8_t u8Padding1[7];
881 /** Timer ticks per Hz. */
882 uint64_t cTimerTicks;
883 /** Timestamp of the last timer callback (hdaTimer).
884 * Used to calculate the time actually elapsed between two timer callbacks. */
885 uint64_t uTimerTS;
886 uint64_t uTimerMS;
887#endif
888#ifdef VBOX_WITH_STATISTICS
889# ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
890 STAMPROFILE StatTimer;
891# endif
892 STAMPROFILE StatIn;
893 STAMPROFILE StatOut;
894 STAMCOUNTER StatBytesRead;
895 STAMCOUNTER StatBytesWritten;
896#endif
897 /** Pointer to HDA codec to use. */
898 R3PTRTYPE(PHDACODEC) pCodec;
899 /** List of associated LUN drivers (HDADRIVER). */
900 RTLISTANCHORR3 lstDrv;
901 /** The device' software mixer. */
902 R3PTRTYPE(PAUDIOMIXER) pMixer;
903 /** HDA sink for (front) output. */
904 HDAMIXERSINK SinkFront;
905#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
906 /** HDA sink for center / LFE output. */
907 HDAMIXERSINK SinkCenterLFE;
908 /** HDA sink for rear output. */
909 HDAMIXERSINK SinkRear;
910#endif
911 /** HDA mixer sink for line input. */
912 HDAMIXERSINK SinkLineIn;
913#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
914 /** Audio mixer sink for microphone input. */
915 HDAMIXERSINK SinkMicIn;
916#endif
917 uint64_t u64BaseTS;
918 /** Response Interrupt Count (RINTCNT). */
919 uint8_t u8RespIntCnt;
920 /** Padding for alignment. */
921 uint8_t au8Padding2[7];
922} HDASTATE;
923/** Pointer to the ICH Intel HD Audio Controller state. */
924typedef HDASTATE *PHDASTATE;
925
926#ifdef VBOX_WITH_AUDIO_HDA_CALLBACKS
927typedef struct HDACALLBACKCTX
928{
929 PHDASTATE pThis;
930 PHDADRIVER pDriver;
931} HDACALLBACKCTX, *PHDACALLBACKCTX;
932#endif
933
934
935/*********************************************************************************************************************************
936* Internal Functions *
937*********************************************************************************************************************************/
938#ifndef VBOX_DEVICE_STRUCT_TESTCASE
939#ifdef IN_RING3
940static FNPDMDEVRESET hdaReset;
941#endif
942
943/** @name Register read/write stubs.
944 * @{
945 */
946static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
947static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
948/** @} */
949
950/** @name Global register set read/write functions.
951 * @{
952 */
953static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
954static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
955static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
956static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
957static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
958static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
959static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
960static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
961static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
962static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
963static int hdaRegWriteINTCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
964static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
965static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
966static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
967/** @} */
968
969/** @name {IOB}SDn write functions.
970 * @{
971 */
972static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
973static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
974static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
975static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
976static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
977static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
978static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
979static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
980static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
981/** @} */
982
983/** @name Generic register read/write functions.
984 * @{
985 */
986static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
987static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
988static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
989#ifdef IN_RING3
990static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
991#endif
992static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
993static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
994static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
995static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
996/** @} */
997
998/** @name Stream functions.
999 * @{
1000 */
1001#ifdef IN_RING3
1002static void hdaStreamDestroy(PHDASTATE pThis, PHDASTREAM pStream);
1003static int hdaStreamDoDMA(PHDASTATE pThis, PHDASTREAM pStream, void *pvBuf, uint32_t cbBuf, uint32_t cbToProcess, uint32_t *pcbProcessed);
1004static int hdaStreamEnable(PHDASTATE pThis, PHDASTREAM pStream, bool fEnable);
1005static int hdaStreamUpdate(PHDASTATE pThis, PHDASTREAM pStream);
1006DECLINLINE(uint32_t) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStream, uint32_t u32LPIB);
1007#endif /* IN_RING3 */
1008/** @} */
1009
1010/** @name Async I/O stream functions.
1011 * @{
1012 */
1013#ifdef IN_RING3
1014# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1015static DECLCALLBACK(int) hdaStreamAsyncIOThread(RTTHREAD hThreadSelf, void *pvUser);
1016static int hdaStreamAsyncIOCreate(PHDASTATE pThis, PHDASTREAM pStream);
1017static int hdaStreamAsyncIODestroy(PHDASTATE pThis, PHDASTREAM pStream);
1018static int hdaStreamAsyncIONotify(PHDASTATE pThis, PHDASTREAM pStream);
1019static void hdaStreamAsyncIOLock(PHDASTREAM pStream);
1020static void hdaStreamAsyncIOUnlock(PHDASTREAM pStream);
1021# endif
1022#endif
1023/** @} */
1024
1025/** @name Stream mapping functions.
1026 * @{
1027 */
1028#ifdef IN_RING3
1029static int hdaStreamMapInit(PHDASTREAMMAPPING pMapping, PPDMAUDIOSTREAMCFG pCfg);
1030static void hdaStreamMapDestroy(PHDASTREAMMAPPING pMapping);
1031static void hdaStreamMapReset(PHDASTREAMMAPPING pMapping);
1032#endif /* IN_RING3 */
1033/** @} */
1034
1035/** @name HDA device functions.
1036 * @{
1037 */
1038#ifdef IN_RING3
1039static void hdaDoTransfers(PHDASTATE pThis);
1040#endif /* IN_RING3 */
1041static int hdaProcessInterrupt(PHDASTATE pThis);
1042/** @} */
1043
1044/** @name BDLE (Buffer Descriptor List Entry) functions.
1045 * @{
1046 */
1047#ifdef IN_RING3
1048static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry);
1049# ifdef LOG_ENABLED
1050static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BaseDMA, uint16_t cBDLE);
1051# endif
1052#endif /* IN_RING3 */
1053/** @} */
1054
1055/** @name Timer functions.
1056 * @{
1057 */
1058#if !defined(VBOX_WITH_AUDIO_HDA_CALLBACKS) && defined(IN_RING3)
1059static void hdaTimerMaybeStart(PHDASTATE pThis);
1060static void hdaTimerMaybeStop(PHDASTATE pThis);
1061static void hdaTimerMain(PHDASTATE pThis);
1062#endif
1063/** @} */
1064
1065
1066/*********************************************************************************************************************************
1067* Global Variables *
1068*********************************************************************************************************************************/
1069
1070/** Offset of the SD0 register map. */
1071#define HDA_REG_DESC_SD0_BASE 0x80
1072
1073/** Turn a short global register name into an memory index and a stringized name. */
1074#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
1075
1076/** Turns a short stream register name into an memory index and a stringized name. */
1077#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
1078
1079/** Same as above for a register *not* stored in memory. */
1080#define HDA_REG_IDX_LOCAL(abbrev) 0, #abbrev
1081
1082/** No register description (RD) flags defined. */
1083#define HDA_RD_FLAG_NONE UINT32_C(0)
1084/** Writes to SD are allowed while RUN bit is set. */
1085#define HDA_RD_FLAG_SD_WRITE_RUN RT_BIT(0)
1086
1087/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
1088#define HDA_REG_MAP_STRM(offset, name) \
1089 /* offset size read mask write mask flags read callback write callback index + abbrev description */ \
1090 /* ------- ------- ---------- ---------- ------------------------- -------------- ----------------- ----------------------------- ----------- */ \
1091 /* Offset 0x80 (SD0) */ \
1092 { offset, 0x00003, 0x00FF001F, 0x00F0001F, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL) , #name " Stream Descriptor Control" }, \
1093 /* Offset 0x83 (SD0) */ \
1094 { offset + 0x3, 0x00001, 0x0000003C, 0x0000001C, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU8 , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS) , #name " Status" }, \
1095 /* Offset 0x84 (SD0) */ \
1096 { offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadLPIB, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
1097 /* Offset 0x88 (SD0) */ \
1098 { offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDCBL , HDA_REG_IDX_STRM(name, CBL) , #name " Cyclic Buffer Length" }, \
1099 /* Offset 0x8C (SD0) */ \
1100 { offset + 0xC, 0x00002, 0x0000FFFF, 0x0000FFFF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDLVI , HDA_REG_IDX_STRM(name, LVI) , #name " Last Valid Index" }, \
1101 /* Reserved: FIFO Watermark. ** @todo Document this! */ \
1102 { offset + 0xE, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
1103 /* Offset 0x90 (SD0) */ \
1104 { offset + 0x10, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
1105 /* Offset 0x92 (SD0) */ \
1106 { offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFMT , HDA_REG_IDX_STRM(name, FMT) , #name " Stream Format" }, \
1107 /* Reserved: 0x94 - 0x98. */ \
1108 /* Offset 0x98 (SD0) */ \
1109 { offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
1110 /* Offset 0x9C (SD0) */ \
1111 { offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
1112
1113/** Defines a single audio stream register set (e.g. OSD0). */
1114#define HDA_REG_MAP_DEF_STREAM(index, name) \
1115 HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
1116
1117/* See 302349 p 6.2. */
1118static const struct HDAREGDESC
1119{
1120 /** Register offset in the register space. */
1121 uint32_t offset;
1122 /** Size in bytes. Registers of size > 4 are in fact tables. */
1123 uint32_t size;
1124 /** Readable bits. */
1125 uint32_t readable;
1126 /** Writable bits. */
1127 uint32_t writable;
1128 /** Register descriptor (RD) flags of type HDA_RD_FLAG_.
1129 * These are used to specify the handling (read/write)
1130 * policy of the register. */
1131 uint32_t fFlags;
1132 /** Read callback. */
1133 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
1134 /** Write callback. */
1135 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
1136 /** Index into the register storage array. */
1137 uint32_t mem_idx;
1138 /** Abbreviated name. */
1139 const char *abbrev;
1140 /** Descripton. */
1141 const char *desc;
1142} g_aHdaRegMap[HDA_NUM_REGS] =
1143
1144{
1145 /* offset size read mask write mask flags read callback write callback index + abbrev */
1146 /*------- ------- ---------- ---------- ----------------- ---------------- ------------------- ------------------------ */
1147 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(GCAP) }, /* Global Capabilities */
1148 { 0x00002, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMIN) }, /* Minor Version */
1149 { 0x00003, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMAJ) }, /* Major Version */
1150 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTPAY) }, /* Output Payload Capabilities */
1151 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INPAY) }, /* Input Payload Capabilities */
1152 { 0x00008, 0x00004, 0x00000103, 0x00000103, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteGCTL , HDA_REG_IDX(GCTL) }, /* Global Control */
1153 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(WAKEEN) }, /* Wake Enable */
1154 { 0x0000e, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteSTATESTS, HDA_REG_IDX(STATESTS) }, /* State Change Status */
1155 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadUnimpl, hdaRegWriteUnimpl , HDA_REG_IDX(GSTS) }, /* Global Status */
1156 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTSTRMPAY) }, /* Output Stream Payload Capability */
1157 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INSTRMPAY) }, /* Input Stream Payload Capability */
1158 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteINTCTL , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */
1159 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */
1160 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadWALCLK, hdaRegWriteUnimpl , HDA_REG_IDX_LOCAL(WALCLK) }, /* Wall Clock Counter */
1161 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */
1162 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
1163 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBUBASE) }, /* CORB Upper Base Address */
1164 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteCORBWP , HDA_REG_IDX(CORBWP) }, /* CORB Write Pointer */
1165 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteCORBRP , HDA_REG_IDX(CORBRP) }, /* CORB Read Pointer */
1166 { 0x0004C, 0x00001, 0x00000003, 0x00000003, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL) }, /* CORB Control */
1167 { 0x0004D, 0x00001, 0x00000001, 0x00000001, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS) }, /* CORB Status */
1168 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(CORBSIZE) }, /* CORB Size */
1169 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBLBASE) }, /* RIRB Lower Base Address */
1170 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBUBASE) }, /* RIRB Upper Base Address */
1171 { 0x00058, 0x00002, 0x000000FF, 0x00008000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteRIRBWP , HDA_REG_IDX(RIRBWP) }, /* RIRB Write Pointer */
1172 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(RINTCNT) }, /* Response Interrupt Count */
1173 { 0x0005C, 0x00001, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteU8 , HDA_REG_IDX(RIRBCTL) }, /* RIRB Control */
1174 { 0x0005D, 0x00001, 0x00000005, 0x00000005, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS) }, /* RIRB Status */
1175 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(RIRBSIZE) }, /* RIRB Size */
1176 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(IC) }, /* Immediate Command */
1177 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(IR) }, /* Immediate Response */
1178 { 0x00068, 0x00002, 0x00000002, 0x00000002, HDA_RD_FLAG_NONE, hdaRegReadIRS , hdaRegWriteIRS , HDA_REG_IDX(IRS) }, /* Immediate Command Status */
1179 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPLBASE) }, /* DMA Position Lower Base */
1180 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPUBASE) }, /* DMA Position Upper Base */
1181 /* 4 Serial Data In (SDI). */
1182 HDA_REG_MAP_DEF_STREAM(0, SD0),
1183 HDA_REG_MAP_DEF_STREAM(1, SD1),
1184 HDA_REG_MAP_DEF_STREAM(2, SD2),
1185 HDA_REG_MAP_DEF_STREAM(3, SD3),
1186 /* 4 Serial Data Out (SDO). */
1187 HDA_REG_MAP_DEF_STREAM(4, SD4),
1188 HDA_REG_MAP_DEF_STREAM(5, SD5),
1189 HDA_REG_MAP_DEF_STREAM(6, SD6),
1190 HDA_REG_MAP_DEF_STREAM(7, SD7)
1191};
1192
1193/**
1194 * HDA register aliases (HDA spec 3.3.45).
1195 * @remarks Sorted by offReg.
1196 */
1197static const struct
1198{
1199 /** The alias register offset. */
1200 uint32_t offReg;
1201 /** The register index. */
1202 int idxAlias;
1203} g_aHdaRegAliases[] =
1204{
1205 { 0x2084, HDA_REG_SD0LPIB },
1206 { 0x20a4, HDA_REG_SD1LPIB },
1207 { 0x20c4, HDA_REG_SD2LPIB },
1208 { 0x20e4, HDA_REG_SD3LPIB },
1209 { 0x2104, HDA_REG_SD4LPIB },
1210 { 0x2124, HDA_REG_SD5LPIB },
1211 { 0x2144, HDA_REG_SD6LPIB },
1212 { 0x2164, HDA_REG_SD7LPIB },
1213};
1214
1215#ifdef IN_RING3
1216/** HDABDLEDESC field descriptors for the v6+ saved state. */
1217static SSMFIELD const g_aSSMBDLEDescFields6[] =
1218{
1219 SSMFIELD_ENTRY(HDABDLEDESC, u64BufAdr),
1220 SSMFIELD_ENTRY(HDABDLEDESC, u32BufSize),
1221 SSMFIELD_ENTRY(HDABDLEDESC, fFlags),
1222 SSMFIELD_ENTRY_TERM()
1223};
1224
1225/** HDABDLESTATE field descriptors for the v6+ saved state. */
1226static SSMFIELD const g_aSSMBDLEStateFields6[] =
1227{
1228 SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
1229 SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
1230 SSMFIELD_ENTRY_OLD(FIFO, 256),
1231 SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
1232 SSMFIELD_ENTRY_TERM()
1233};
1234
1235/** HDASTREAMSTATE field descriptors for the v6+ saved state. */
1236static SSMFIELD const g_aSSMStreamStateFields6[] =
1237{
1238 SSMFIELD_ENTRY_OLD(cBDLE, 2),
1239 SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
1240 SSMFIELD_ENTRY_OLD(fDoStop, 1),
1241 SSMFIELD_ENTRY_OLD(fActive, 1),
1242 SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
1243 SSMFIELD_ENTRY_TERM()
1244};
1245#endif
1246
1247/**
1248 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
1249 */
1250static uint32_t const g_afMasks[5] =
1251{
1252 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
1253};
1254
1255
1256#ifdef IN_RING3
1257/**
1258 * Retrieves the number of bytes of a FIFOW register.
1259 *
1260 * @return Number of bytes of a given FIFOW register.
1261 */
1262DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
1263{
1264 uint32_t cb;
1265 switch (u32RegFIFOW)
1266 {
1267 case HDA_SDFIFOW_8B: cb = 8; break;
1268 case HDA_SDFIFOW_16B: cb = 16; break;
1269 case HDA_SDFIFOW_32B: cb = 32; break;
1270 default: cb = 0; break;
1271 }
1272
1273 Assert(RT_IS_POWER_OF_TWO(cb));
1274 return cb;
1275}
1276
1277
1278DECLINLINE(uint32_t) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStream, uint32_t u32LPIB)
1279{
1280 AssertPtrReturn(pThis, 0);
1281 AssertPtrReturn(pStream, 0);
1282
1283 AssertMsg(u32LPIB <= pStream->u32CBL,
1284 ("[SD%RU8] New LPIB (%RU32) exceeds CBL (%RU32)\n", pStream->u8SD, u32LPIB, pStream->u32CBL));
1285
1286 u32LPIB = RT_MIN(u32LPIB, pStream->u32CBL);
1287
1288 LogFlowFunc(("[SD%RU8]: LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n",
1289 pStream->u8SD, u32LPIB, pThis->fDMAPosition));
1290
1291 /* Update LPIB in any case. */
1292 HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) = u32LPIB;
1293
1294 /* Do we need to tell the current DMA position? */
1295 if (pThis->fDMAPosition)
1296 {
1297 int rc2 = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
1298 (pThis->u64DPBase & DPBASE_ADDR_MASK) + (pStream->u8SD * 2 * sizeof(uint32_t)),
1299 (void *)&u32LPIB, sizeof(uint32_t));
1300 AssertRC(rc2);
1301 }
1302
1303 return u32LPIB;
1304}
1305
1306
1307/**
1308 * Fetches the next BDLE to use for a stream.
1309 *
1310 * @return IPRT status code.
1311 */
1312DECLINLINE(int) hdaStreamGetNextBDLE(PHDASTATE pThis, PHDASTREAM pStream, bool *pfWrapAround)
1313{
1314 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1315 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1316
1317 NOREF(pThis);
1318
1319 Assert(pStream->State.uCurBDLE < pStream->u16LVI + 1);
1320
1321 LogFlowFuncEnter();
1322
1323# ifdef LOG_ENABLED
1324 uint32_t const uOldBDLE = pStream->State.uCurBDLE;
1325# endif
1326
1327 PHDABDLE pBDLE = &pStream->State.BDLE;
1328 bool fWrapAround = false;
1329
1330 AssertMsg(pBDLE->State.u32BufOff == pBDLE->Desc.u32BufSize, ("BDLE not finished yet: %R[bdle]\n", pBDLE));
1331
1332 /*
1333 * Switch to the next BDLE entry and do a wrap around
1334 * if we reached the end of the Buffer Descriptor List (BDL).
1335 */
1336 pStream->State.uCurBDLE++;
1337 if (pStream->State.uCurBDLE == pStream->u16LVI + 1)
1338 {
1339 pStream->State.uCurBDLE = 0;
1340 fWrapAround = true;
1341 }
1342
1343 Assert(pStream->State.uCurBDLE < pStream->u16LVI + 1);
1344
1345 /* Fetch the next BDLE entry. */
1346 int rc = hdaBDLEFetch(pThis, pBDLE, pStream->u64BDLBase, pStream->State.uCurBDLE);
1347 if (RT_SUCCESS(rc))
1348 {
1349 LogFlowFunc(("[SD%RU8]: uOldBDLE=%RU16, uCurBDLE=%RU16, LVI=%RU32, rc=%Rrc, %R[bdle]\n",
1350 pStream->u8SD, uOldBDLE, pStream->State.uCurBDLE, pStream->u16LVI, rc, pBDLE));
1351
1352 if (pfWrapAround)
1353 *pfWrapAround = fWrapAround;
1354 }
1355
1356 return rc;
1357}
1358
1359
1360/**
1361 * Returns the HDA stream of specified stream descriptor number.
1362 *
1363 * @return Pointer to HDA stream, or NULL if none found.
1364 */
1365DECLINLINE(PHDASTREAM) hdaStreamGetFromSD(PHDASTATE pThis, uint8_t uSD)
1366{
1367 AssertPtrReturn(pThis, NULL);
1368 AssertReturn(uSD <= HDA_MAX_STREAMS, NULL);
1369
1370 if (uSD >= HDA_MAX_STREAMS)
1371 {
1372 AssertMsgFailed(("Invalid / non-handled SD%RU8\n", uSD));
1373 return NULL;
1374 }
1375
1376 return &pThis->aStreams[uSD];
1377}
1378
1379
1380/**
1381 * Returns the HDA stream of specified HDA sink.
1382 *
1383 * @return Pointer to HDA stream, or NULL if none found.
1384 */
1385DECLINLINE(PHDASTREAM) hdaSinkGetStream(PHDASTATE pThis, PHDAMIXERSINK pSink)
1386{
1387 AssertPtrReturn(pThis, NULL);
1388 AssertPtrReturn(pSink, NULL);
1389
1390 /** @todo Do something with the channel mapping here? */
1391 return hdaStreamGetFromSD(pThis, pSink->uSD);
1392}
1393
1394
1395/**
1396 * Returns the audio direction of a specified stream descriptor.
1397 *
1398 * The register layout specifies that input streams (SDI) come first,
1399 * followed by the output streams (SDO). So every stream ID below HDA_MAX_SDI
1400 * is an input stream, whereas everything >= HDA_MAX_SDI is an output stream.
1401 *
1402 * Note: SDnFMT register does not provide that information, so we have to judge
1403 * for ourselves.
1404 *
1405 * @return Audio direction.
1406 */
1407DECLINLINE(PDMAUDIODIR) hdaGetDirFromSD(uint8_t uSD)
1408{
1409 AssertReturn(uSD <= HDA_MAX_STREAMS, PDMAUDIODIR_UNKNOWN);
1410
1411 if (uSD < HDA_MAX_SDI)
1412 return PDMAUDIODIR_IN;
1413
1414 return PDMAUDIODIR_OUT;
1415}
1416#endif /* IN_RING3 */
1417
1418
1419static void hdaUpdateINTSTS(PHDASTATE pThis)
1420{
1421 uint32_t intSts = 0;
1422
1423 if (/* Response Overrun Interrupt Status (ROIS) */
1424 HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1425 /* Response Interrupt */
1426 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1427 /* SDIN State Change Status Flags (SCSF) */
1428 || (HDA_REG(pThis, STATESTS) & HDA_STATESTS_SCSF_MASK))
1429 {
1430 intSts |= RT_BIT(30); /* Touch Controller Interrupt Status (CIS). */
1431 }
1432
1433#define HDA_MARK_STREAM(x) \
1434 if ( (INTCTL_SX(pThis, x)) \
1435 && ( (SDSTS(pThis, x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1436 || (SDSTS(pThis, x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1437 || (SDSTS(pThis, x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)) \
1438 ) \
1439 ) \
1440 { \
1441 Log3Func(("[SD%RU8] Marked\n", x)); \
1442 intSts |= RT_BIT(x); \
1443 }
1444
1445 HDA_MARK_STREAM(0);
1446 HDA_MARK_STREAM(1);
1447 HDA_MARK_STREAM(2);
1448 HDA_MARK_STREAM(3);
1449 HDA_MARK_STREAM(4);
1450 HDA_MARK_STREAM(5);
1451 HDA_MARK_STREAM(6);
1452 HDA_MARK_STREAM(7);
1453
1454#undef HDA_MARK_STREAM
1455
1456 if (intSts)
1457 intSts |= RT_BIT(31); /* Touch Global Interrupt Status (GIS). */
1458
1459 HDA_REG(pThis, INTSTS) = intSts;
1460
1461 Log3Func(("INTSTS=%x\n", intSts));
1462}
1463
1464static int hdaProcessInterrupt(PHDASTATE pThis)
1465{
1466 hdaUpdateINTSTS(pThis);
1467
1468 int iLevel = 0;
1469
1470 /* Global Interrupt Status (GIS) touched? */
1471 if (HDA_REG_FLAG_VALUE(pThis, INTSTS, GIS))
1472 iLevel = 1;
1473
1474 Log3Func(("INTCTL=%x, INTSTS=%x, Level=%d\n", HDA_REG(pThis, INTCTL), HDA_REG(pThis, INTSTS), iLevel));
1475
1476 /* Global Interrupt Enable (GIE) set? */
1477 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1478 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, iLevel);
1479
1480 return VINF_SUCCESS;
1481}
1482
1483/**
1484 * Looks up a register at the exact offset given by @a offReg.
1485 *
1486 * @returns Register index on success, -1 if not found.
1487 * @param offReg The register offset.
1488 */
1489static int hdaRegLookup(uint32_t offReg)
1490{
1491 /*
1492 * Aliases.
1493 */
1494 if (offReg >= g_aHdaRegAliases[0].offReg)
1495 {
1496 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1497 if (offReg == g_aHdaRegAliases[i].offReg)
1498 return g_aHdaRegAliases[i].idxAlias;
1499 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1500 return -1;
1501 }
1502
1503 /*
1504 * Binary search the
1505 */
1506 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1507 int idxLow = 0;
1508 for (;;)
1509 {
1510 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1511 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1512 {
1513 if (idxLow == idxMiddle)
1514 break;
1515 idxEnd = idxMiddle;
1516 }
1517 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1518 {
1519 idxLow = idxMiddle + 1;
1520 if (idxLow >= idxEnd)
1521 break;
1522 }
1523 else
1524 return idxMiddle;
1525 }
1526
1527#ifdef RT_STRICT
1528 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1529 Assert(g_aHdaRegMap[i].offset != offReg);
1530#endif
1531 return -1;
1532}
1533
1534/**
1535 * Looks up a register covering the offset given by @a offReg.
1536 *
1537 * @returns Register index on success, -1 if not found.
1538 * @param offReg The register offset.
1539 */
1540static int hdaRegLookupWithin(uint32_t offReg)
1541{
1542 /*
1543 * Aliases.
1544 */
1545 if (offReg >= g_aHdaRegAliases[0].offReg)
1546 {
1547 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1548 {
1549 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1550 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1551 return g_aHdaRegAliases[i].idxAlias;
1552 }
1553 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1554 return -1;
1555 }
1556
1557 /*
1558 * Binary search the register map.
1559 */
1560 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1561 int idxLow = 0;
1562 for (;;)
1563 {
1564 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1565 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1566 {
1567 if (idxLow == idxMiddle)
1568 break;
1569 idxEnd = idxMiddle;
1570 }
1571 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1572 {
1573 idxLow = idxMiddle + 1;
1574 if (idxLow >= idxEnd)
1575 break;
1576 }
1577 else
1578 return idxMiddle;
1579 }
1580
1581#ifdef RT_STRICT
1582 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1583 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1584#endif
1585 return -1;
1586}
1587
1588#ifdef IN_RING3
1589
1590static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1591{
1592 int rc = VINF_SUCCESS;
1593 if (fLocal)
1594 {
1595 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1596 Assert(pThis->u64CORBBase);
1597 AssertPtr(pThis->pu32CorbBuf);
1598 Assert(pThis->cbCorbBuf);
1599
1600 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1601 if (RT_FAILURE(rc))
1602 AssertRCReturn(rc, rc);
1603# ifdef DEBUG_CMD_BUFFER
1604 uint8_t i = 0;
1605 do
1606 {
1607 LogFunc(("CORB%02x: ", i));
1608 uint8_t j = 0;
1609 do
1610 {
1611 const char *pszPrefix;
1612 if ((i + j) == HDA_REG(pThis, CORBRP));
1613 pszPrefix = "[R]";
1614 else if ((i + j) == HDA_REG(pThis, CORBWP));
1615 pszPrefix = "[W]";
1616 else
1617 pszPrefix = " "; /* three spaces */
1618 LogFunc(("%s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
1619 j++;
1620 } while (j < 8);
1621 LogFunc(("\n"));
1622 i += 8;
1623 } while(i != 0);
1624# endif
1625 }
1626 else
1627 {
1628 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1629 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1630 if (RT_FAILURE(rc))
1631 AssertRCReturn(rc, rc);
1632# ifdef DEBUG_CMD_BUFFER
1633 uint8_t i = 0;
1634 do {
1635 LogFunc(("RIRB%02x: ", i));
1636 uint8_t j = 0;
1637 do {
1638 const char *prefix;
1639 if ((i + j) == HDA_REG(pThis, RIRBWP))
1640 prefix = "[W]";
1641 else
1642 prefix = " ";
1643 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1644 } while (++j < 8);
1645 LogFunc(("\n"));
1646 i += 8;
1647 } while (i != 0);
1648# endif
1649 }
1650 return rc;
1651}
1652
1653static int hdaCORBCmdProcess(PHDASTATE pThis)
1654{
1655 int rc = hdaCmdSync(pThis, true);
1656 if (RT_FAILURE(rc))
1657 AssertRCReturn(rc, rc);
1658
1659 uint8_t corbRp = HDA_REG(pThis, CORBRP);
1660 uint8_t corbWp = HDA_REG(pThis, CORBWP);
1661 uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
1662
1663 Assert((corbWp != corbRp));
1664 Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1665
1666 while (corbRp != corbWp)
1667 {
1668 uint64_t uResp;
1669 uint32_t uCmd = pThis->pu32CorbBuf[++corbRp];
1670
1671 int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(uCmd, 0 /* Codec index */), &uResp);
1672 if (RT_FAILURE(rc2))
1673 LogFunc(("Codec lookup failed with rc=%Rrc\n", rc2));
1674
1675 (rirbWp)++;
1676
1677 if ( (uResp & CODEC_RESPONSE_UNSOLICITED)
1678 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1679 {
1680 LogFunc(("Unexpected unsolicited response\n"));
1681 HDA_REG(pThis, CORBRP) = corbRp;
1682 return rc;
1683 }
1684
1685 pThis->pu64RirbBuf[rirbWp] = uResp;
1686
1687 pThis->u8RespIntCnt++;
1688 if (pThis->u8RespIntCnt == RINTCNT_N(pThis))
1689 break;
1690 }
1691
1692 HDA_REG(pThis, CORBRP) = corbRp;
1693 HDA_REG(pThis, RIRBWP) = rirbWp;
1694
1695 rc = hdaCmdSync(pThis, false);
1696
1697 Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1698
1699 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1700 {
1701 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1702
1703 pThis->u8RespIntCnt = 0;
1704 rc = hdaProcessInterrupt(pThis);
1705 }
1706
1707 if (RT_FAILURE(rc))
1708 AssertRCReturn(rc, rc);
1709 return rc;
1710}
1711
1712static int hdaStreamCreate(PHDASTATE pThis, PHDASTREAM pStream, uint8_t uSD)
1713{
1714 RT_NOREF(pThis);
1715 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1716 AssertReturn(uSD <= HDA_MAX_STREAMS, VERR_INVALID_PARAMETER);
1717
1718 int rc = RTCritSectInit(&pStream->State.CritSect);
1719 if (RT_SUCCESS(rc))
1720 {
1721 pStream->u8SD = uSD;
1722 pStream->pMixSink = NULL;
1723
1724 pStream->State.fInReset = false;
1725 }
1726
1727 if (RT_SUCCESS(rc))
1728 rc = RTCircBufCreate(&pStream->State.pCircBuf, _4K); /** @todo Make this configurable. */
1729
1730 LogFlowFunc(("uSD=%RU8\n", uSD));
1731 return rc;
1732}
1733
1734static void hdaStreamDestroy(PHDASTATE pThis, PHDASTREAM pStream)
1735{
1736 AssertPtrReturnVoid(pStream);
1737
1738 LogFlowFunc(("[SD%RU8]: Destroying ...\n", pStream->u8SD));
1739
1740 hdaStreamMapDestroy(&pStream->State.Mapping);
1741
1742 int rc2;
1743
1744#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1745 rc2 = hdaStreamAsyncIODestroy(pThis, pStream);
1746 AssertRC(rc2);
1747#else
1748 RT_NOREF(pThis);
1749#endif
1750
1751 rc2 = RTCritSectDelete(&pStream->State.CritSect);
1752 AssertRC(rc2);
1753
1754 if (pStream->State.pCircBuf)
1755 {
1756 RTCircBufDestroy(pStream->State.pCircBuf);
1757 pStream->State.pCircBuf = NULL;
1758 }
1759
1760 LogFlowFuncLeave();
1761}
1762
1763static int hdaStreamInit(PHDASTATE pThis, PHDASTREAM pStream, uint8_t u8SD)
1764{
1765 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1766 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1767
1768 pStream->u8SD = u8SD;
1769 pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
1770 HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
1771 pStream->u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
1772 pStream->u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
1773 pStream->u16FIFOS = HDA_STREAM_REG(pThis, FIFOS, pStream->u8SD) + 1;
1774
1775 RT_ZERO(pStream->State.BDLE);
1776 pStream->State.uCurBDLE = 0;
1777
1778 hdaStreamMapReset(&pStream->State.Mapping);
1779
1780 LogFlowFunc(("[SD%RU8]: DMA @ 0x%x (%RU32 bytes), LVI=%RU16, FIFOS=%RU16\n",
1781 pStream->u8SD, pStream->u64BDLBase, pStream->u32CBL, pStream->u16LVI, pStream->u16FIFOS));
1782
1783# ifdef DEBUG
1784 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
1785 HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
1786 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
1787 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
1788
1789 LogFlowFunc(("\t-> DMA @ 0x%x, LVI=%RU16, CBL=%RU32\n", u64BaseDMA, u16LVI, u32CBL));
1790
1791 hdaBDLEDumpAll(pThis, u64BaseDMA, u16LVI + 1);
1792# endif
1793
1794 return VINF_SUCCESS;
1795}
1796
1797static void hdaStreamReset(PHDASTATE pThis, PHDASTREAM pStream)
1798{
1799 AssertPtrReturnVoid(pThis);
1800 AssertPtrReturnVoid(pStream);
1801
1802 const uint8_t uSD = pStream->u8SD;
1803
1804# ifdef VBOX_STRICT
1805 AssertReleaseMsg(!RT_BOOL(HDA_STREAM_REG(pThis, CTL, uSD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
1806 ("[SD%RU8] Cannot reset stream while in running state\n", uSD));
1807# endif
1808
1809 LogFunc(("[SD%RU8]: Reset\n", uSD));
1810
1811 int rc2;
1812#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1813 /*
1814 * Make sure to destroy the async I/O thread for this stream on reset, as we
1815 * can't be sure that the same stream is being used in the next cycle
1816 * (and therefore would leave unused threads around).
1817 */
1818 rc2 = hdaStreamAsyncIODestroy(pThis, pStream);
1819 AssertRC(rc2);
1820#endif
1821
1822 /*
1823 * First, reset the internal stream state.
1824 */
1825 RT_ZERO(pStream->State.BDLE);
1826 pStream->State.uCurBDLE = 0;
1827
1828 if (pStream->State.pCircBuf)
1829 RTCircBufReset(pStream->State.pCircBuf);
1830
1831 /*
1832 * Second, initialize the registers.
1833 */
1834 HDA_STREAM_REG(pThis, STS, uSD) = HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1835 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1836 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
1837 HDA_STREAM_REG(pThis, CTL, uSD) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1838 /*
1839 * ICH6 defines default values (120 bytes for input and 192 bytes for output descriptors) of FIFO size. 18.2.39.
1840 * BUT: Windows guests seem to read the FIFOS but define a DMA region which does not fit to that FIFO size
1841 * (e.g. 1792 bytes DMA region vs. 192 bytes FIFOS).
1842 * This will lead to crackling and corrupted sound -- so define a 256 bytes FIOS for output streams here per default.
1843 */
1844 HDA_STREAM_REG(pThis, FIFOS, uSD) = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? HDA_SDIFIFO_120B : HDA_SDOFIFO_256B;
1845 /* See 18.2.38: Always defaults to 0x4 (32 bytes). */
1846 HDA_STREAM_REG(pThis, FIFOW, uSD) = HDA_SDFIFOW_32B;
1847 HDA_STREAM_REG(pThis, LPIB, uSD) = 0;
1848 HDA_STREAM_REG(pThis, CBL, uSD) = 0;
1849 HDA_STREAM_REG(pThis, LVI, uSD) = 0;
1850 HDA_STREAM_REG(pThis, FMT, uSD) = HDA_SDFMT_MAKE(HDA_SDFMT_TYPE_PCM, HDA_SDFMT_BASE_44KHZ,
1851 HDA_SDFMT_MULT_1X, HDA_SDFMT_DIV_1X, HDA_SDFMT_16_BIT,
1852 HDA_SDFMT_CHAN_STEREO);
1853 HDA_STREAM_REG(pThis, BDPU, uSD) = 0;
1854 HDA_STREAM_REG(pThis, BDPL, uSD) = 0;
1855
1856 rc2 = hdaStreamInit(pThis, pStream, uSD);
1857 AssertRC(rc2);
1858}
1859
1860static int hdaStreamEnable(PHDASTATE pThis, PHDASTREAM pStream, bool fEnable)
1861{
1862 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1863 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1864
1865 LogFlowFunc(("[SD%RU8]: fEnable=%RTbool, pMixSink=%p\n", pStream->u8SD, fEnable, pStream->pMixSink));
1866
1867 int rc = VINF_SUCCESS;
1868
1869#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1870 hdaStreamAsyncIOLock(pStream);
1871#endif
1872
1873 if (pStream->pMixSink) /* Stream attached to a sink? */
1874 {
1875 AUDMIXSINKCMD enmCmd = fEnable
1876 ? AUDMIXSINKCMD_ENABLE : AUDMIXSINKCMD_DISABLE;
1877
1878 /* First, enable or disable the stream and the stream's sink, if any. */
1879 if (pStream->pMixSink->pMixSink)
1880 rc = AudioMixerSinkCtl(pStream->pMixSink->pMixSink, enmCmd);
1881 }
1882 else
1883 rc = VINF_SUCCESS;
1884
1885#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1886 hdaStreamAsyncIOUnlock(pStream);
1887#endif
1888
1889 if (RT_FAILURE(rc))
1890 {
1891 LogFunc(("Failed with rc=%Rrc\n", rc));
1892 return rc;
1893 }
1894
1895 /* Second, see if we need to start or stop the timer. */
1896 if (!fEnable)
1897 {
1898# ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
1899 hdaTimerMaybeStop(pThis);
1900# endif
1901 }
1902 else
1903 {
1904# ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
1905 hdaTimerMaybeStart(pThis);
1906# endif
1907 }
1908
1909 LogFlowFunc(("u8Strm=%RU8, fEnable=%RTbool, cStreamsActive=%RU8\n", pStream->u8SD, fEnable, pThis->cStreamsActive));
1910 return VINF_SUCCESS;
1911}
1912
1913static void hdaStreamAssignToSink(PHDASTREAM pStream, PHDAMIXERSINK pMixSink)
1914{
1915 AssertPtrReturnVoid(pStream);
1916
1917 int rc2 = RTCritSectEnter(&pStream->State.CritSect);
1918 if (RT_SUCCESS(rc2))
1919 {
1920 pStream->pMixSink = pMixSink;
1921
1922 rc2 = RTCritSectLeave(&pStream->State.CritSect);
1923 AssertRC(rc2);
1924 }
1925}
1926
1927# if defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_AUDIO_HDA_51_SURROUND)
1928static int hdaStreamChannelExtract(PPDMAUDIOSTREAMCHANNEL pChan, const void *pvBuf, size_t cbBuf)
1929{
1930 AssertPtrReturn(pChan, VERR_INVALID_POINTER);
1931 AssertPtrReturn(pvBuf, VERR_INVALID_POINTER);
1932 AssertReturn(cbBuf, VERR_INVALID_PARAMETER);
1933
1934 AssertRelease(pChan->cbOff <= cbBuf);
1935
1936 const uint8_t *pu8Buf = (const uint8_t *)pvBuf;
1937
1938 size_t cbSrc = cbBuf - pChan->cbOff;
1939 const uint8_t *pvSrc = &pu8Buf[pChan->cbOff];
1940
1941 size_t cbDst;
1942 uint8_t *pvDst;
1943 RTCircBufAcquireWriteBlock(pChan->Data.pCircBuf, cbBuf, (void **)&pvDst, &cbDst);
1944
1945 cbSrc = RT_MIN(cbSrc, cbDst);
1946
1947 while (cbSrc)
1948 {
1949 AssertBreak(cbDst >= cbSrc);
1950
1951 /* Enough data for at least one next frame? */
1952 if (cbSrc < pChan->cbFrame)
1953 break;
1954
1955 memcpy(pvDst, pvSrc, pChan->cbFrame);
1956
1957 /* Advance to next channel frame in stream. */
1958 pvSrc += pChan->cbStep;
1959 Assert(cbSrc >= pChan->cbStep);
1960 cbSrc -= pChan->cbStep;
1961
1962 /* Advance destination by one frame. */
1963 pvDst += pChan->cbFrame;
1964 Assert(cbDst >= pChan->cbFrame);
1965 cbDst -= pChan->cbFrame;
1966
1967 /* Adjust offset. */
1968 pChan->cbOff += pChan->cbFrame;
1969 }
1970
1971 RTCircBufReleaseWriteBlock(pChan->Data.pCircBuf, cbDst);
1972
1973 return VINF_SUCCESS;
1974}
1975# endif /* defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_AUDIO_HDA_51_SURROUND) */
1976
1977# if 0 /** @todo hdaStreamChannelAdvance is unused */
1978static int hdaStreamChannelAdvance(PPDMAUDIOSTREAMCHANNEL pChan, size_t cbAdv)
1979{
1980 AssertPtrReturn(pChan, VERR_INVALID_POINTER);
1981
1982 if (!cbAdv)
1983 return VINF_SUCCESS;
1984
1985 return VINF_SUCCESS;
1986}
1987# endif
1988
1989static int hdaStreamChannelDataInit(PPDMAUDIOSTREAMCHANNELDATA pChanData, uint32_t fFlags)
1990{
1991 int rc = RTCircBufCreate(&pChanData->pCircBuf, 256); /** @todo Make this configurable? */
1992 if (RT_SUCCESS(rc))
1993 {
1994 pChanData->fFlags = fFlags;
1995 }
1996
1997 return rc;
1998}
1999
2000/**
2001 * Frees a stream channel data block again.
2002 *
2003 * @param pChanData Pointer to channel data to free.
2004 */
2005static void hdaStreamChannelDataDestroy(PPDMAUDIOSTREAMCHANNELDATA pChanData)
2006{
2007 if (!pChanData)
2008 return;
2009
2010 if (pChanData->pCircBuf)
2011 {
2012 RTCircBufDestroy(pChanData->pCircBuf);
2013 pChanData->pCircBuf = NULL;
2014 }
2015
2016 pChanData->fFlags = PDMAUDIOSTREAMCHANNELDATA_FLAG_NONE;
2017}
2018
2019# if defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_AUDIO_HDA_51_SURROUND)
2020
2021static int hdaStreamChannelAcquireData(PPDMAUDIOSTREAMCHANNELDATA pChanData, void *pvData, size_t *pcbData)
2022{
2023 AssertPtrReturn(pChanData, VERR_INVALID_POINTER);
2024 AssertPtrReturn(pvData, VERR_INVALID_POINTER);
2025 AssertPtrReturn(pcbData, VERR_INVALID_POINTER);
2026
2027 RTCircBufAcquireReadBlock(pChanData->pCircBuf, 256 /** @todo Make this configurarble? */, &pvData, &pChanData->cbAcq);
2028
2029 *pcbData = pChanData->cbAcq;
2030 return VINF_SUCCESS;
2031}
2032
2033static int hdaStreamChannelReleaseData(PPDMAUDIOSTREAMCHANNELDATA pChanData)
2034{
2035 AssertPtrReturn(pChanData, VERR_INVALID_POINTER);
2036 RTCircBufReleaseReadBlock(pChanData->pCircBuf, pChanData->cbAcq);
2037
2038 return VINF_SUCCESS;
2039}
2040
2041# endif /* defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_AUDIO_HDA_51_SURROUND) */
2042
2043# if 0 /* currently unused */
2044static int hdaStreamWaitForStateChange(PHDASTREAM pStream, RTMSINTERVAL msTimeout)
2045{
2046 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
2047
2048 LogFlowFunc(("[SD%RU8]: msTimeout=%RU32\n", pStream->u8SD, msTimeout));
2049 return RTSemEventWait(pStream->State.hStateChangedEvent, msTimeout);
2050}
2051# endif /* currently unused */
2052
2053#endif /* IN_RING3 */
2054
2055/* Register access handlers. */
2056
2057static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2058{
2059 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg);
2060 *pu32Value = 0;
2061 return VINF_SUCCESS;
2062}
2063
2064static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2065{
2066 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2067 return VINF_SUCCESS;
2068}
2069
2070/* U8 */
2071static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2072{
2073 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
2074 return hdaRegReadU32(pThis, iReg, pu32Value);
2075}
2076
2077static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2078{
2079 Assert((u32Value & 0xffffff00) == 0);
2080 return hdaRegWriteU32(pThis, iReg, u32Value);
2081}
2082
2083/* U16 */
2084static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2085{
2086 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
2087 return hdaRegReadU32(pThis, iReg, pu32Value);
2088}
2089
2090static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2091{
2092 Assert((u32Value & 0xffff0000) == 0);
2093 return hdaRegWriteU32(pThis, iReg, u32Value);
2094}
2095
2096/* U24 */
2097static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2098{
2099 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
2100 return hdaRegReadU32(pThis, iReg, pu32Value);
2101}
2102
2103#ifdef IN_RING3
2104static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2105{
2106 Assert((u32Value & 0xff000000) == 0);
2107 return hdaRegWriteU32(pThis, iReg, u32Value);
2108}
2109#endif
2110
2111/* U32 */
2112static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2113{
2114 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2115
2116 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
2117 return VINF_SUCCESS;
2118}
2119
2120static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2121{
2122 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2123
2124 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
2125 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
2126 return VINF_SUCCESS;
2127}
2128
2129static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2130{
2131 RT_NOREF_PV(iReg);
2132
2133 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
2134 {
2135 /* Set the CRST bit to indicate that we're leaving reset mode. */
2136 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
2137
2138 if (pThis->fInReset)
2139 {
2140 LogFunc(("Guest leaving HDA reset\n"));
2141 pThis->fInReset = false;
2142 }
2143 }
2144 else
2145 {
2146#ifdef IN_RING3
2147 /* Enter reset state. */
2148 LogFunc(("Guest entering HDA reset with DMA(RIRB:%s, CORB:%s)\n",
2149 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
2150 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
2151
2152 /* Clear the CRST bit to indicate that we're in reset state. */
2153 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
2154 pThis->fInReset = true;
2155
2156 hdaReset(pThis->CTX_SUFF(pDevIns));
2157#else
2158 return VINF_IOM_R3_MMIO_WRITE;
2159#endif
2160 }
2161
2162 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
2163 {
2164 /* Flush: GSTS:1 set, see 6.2.6. */
2165 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* Set the flush state. */
2166 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
2167 }
2168 return VINF_SUCCESS;
2169}
2170
2171static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2172{
2173 uint32_t v = HDA_REG_IND(pThis, iReg);
2174 uint32_t nv = u32Value & HDA_STATESTS_SCSF_MASK;
2175
2176 HDA_REG(pThis, STATESTS) &= ~(v & nv); /* Write of 1 clears corresponding bit. */
2177
2178 return hdaProcessInterrupt(pThis);
2179}
2180
2181static int hdaRegWriteINTCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2182{
2183 RT_NOREF(iReg);
2184
2185 int rc;
2186
2187 HDA_REG(pThis, INTCTL) = u32Value;
2188
2189 /* Global Interrupt Enable (GIE) set? */
2190 if (u32Value & HDA_INTCTL_GIE_MASK)
2191 {
2192 rc = hdaProcessInterrupt(pThis);
2193 }
2194 else
2195 {
2196 /** @todo Clear INTSTS's individual stream status bits as well? */
2197
2198 /* Make sure to lower interrupt line, as Global Interrupt Enable (GIE) is disabled. */
2199 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 0 /* iLevel */);
2200
2201 rc = VINF_SUCCESS;
2202 }
2203
2204 return rc;
2205}
2206
2207static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2208{
2209 const uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
2210 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, u8Strm);
2211#ifdef LOG_ENABLED
2212 const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
2213 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32\n", u8Strm, u32LPIB, u32CBL));
2214#endif
2215
2216 *pu32Value = u32LPIB;
2217 return VINF_SUCCESS;
2218}
2219
2220static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2221{
2222 RT_NOREF_PV(iReg);
2223
2224 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
2225 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
2226 - pThis->u64BaseTS, 24, 1000);
2227 LogFlowFunc(("%RU32\n", *pu32Value));
2228 return VINF_SUCCESS;
2229}
2230
2231static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2232{
2233 RT_NOREF_PV(iReg);
2234
2235 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
2236 {
2237 HDA_REG(pThis, CORBRP) = 0;
2238 }
2239#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
2240 else
2241 return hdaRegWriteU8(pThis, iReg, u32Value);
2242#endif
2243 return VINF_SUCCESS;
2244}
2245
2246static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2247{
2248#ifdef IN_RING3
2249 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
2250 AssertRC(rc);
2251 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2252 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
2253 {
2254 return hdaCORBCmdProcess(pThis);
2255 }
2256 return rc;
2257#else
2258 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2259 return VINF_IOM_R3_MMIO_WRITE;
2260#endif
2261}
2262
2263static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2264{
2265 RT_NOREF_PV(iReg);
2266
2267 uint32_t v = HDA_REG(pThis, CORBSTS);
2268 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
2269 return VINF_SUCCESS;
2270}
2271
2272static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2273{
2274#ifdef IN_RING3
2275 int rc;
2276 rc = hdaRegWriteU16(pThis, iReg, u32Value);
2277 if (RT_FAILURE(rc))
2278 AssertRCReturn(rc, rc);
2279 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
2280 return VINF_SUCCESS;
2281 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
2282 return VINF_SUCCESS;
2283 rc = hdaCORBCmdProcess(pThis);
2284 return rc;
2285#else /* !IN_RING3 */
2286 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2287 return VINF_IOM_R3_MMIO_WRITE;
2288#endif /* IN_RING3 */
2289}
2290
2291static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2292{
2293#ifdef IN_RING3
2294 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2295 return VINF_SUCCESS;
2296
2297 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, CBL, iReg));
2298 if (!pStream)
2299 {
2300 LogFunc(("[SD%RU8]: Warning: Changing SDCBL on non-attached stream (0x%x)\n",
2301 HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
2302 return hdaRegWriteU32(pThis, iReg, u32Value);
2303 }
2304
2305 pStream->u32CBL = u32Value;
2306
2307 /* Reset BDLE state. */
2308 RT_ZERO(pStream->State.BDLE);
2309 pStream->State.uCurBDLE = 0;
2310
2311 int rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2312 AssertRC(rc2);
2313
2314 LogFlowFunc(("[SD%RU8]: CBL=%RU32\n", pStream->u8SD, u32Value));
2315
2316 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2317#else /* !IN_RING3 */
2318 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2319 return VINF_IOM_R3_MMIO_WRITE;
2320#endif /* IN_RING3 */
2321}
2322
2323static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2324{
2325#ifdef IN_RING3
2326 /*
2327 * Some guests write too much (that is, 32-bit with the top 8 bit being junk)
2328 * instead of 24-bit required for SDCTL. So just mask this here to be safe.
2329 */
2330 u32Value = (u32Value & 0x00ffffff);
2331
2332 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2333 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2334
2335 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
2336 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
2337
2338 /* Get the stream descriptor. */
2339 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
2340
2341 LogFunc(("[SD%RU8]: fRun=%RTbool, fInRun=%RTbool, fReset=%RTbool, fInReset=%RTbool, %R[sdctl]\n",
2342 uSD, fRun, fInRun, fReset, fInReset, u32Value));
2343
2344 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2345 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2346
2347 /*
2348 * Extract the stream tag the guest wants to use for this specific
2349 * stream descriptor (SDn). This only can happen if the stream is in a non-running
2350 * state, so we're doing the lookup and assignment here.
2351 *
2352 * So depending on the guest OS, SD3 can use stream tag 4, for example.
2353 */
2354 uint8_t uTag = (u32Value >> HDA_SDCTL_NUM_SHIFT) & HDA_SDCTL_NUM_MASK;
2355 if (uTag > HDA_MAX_TAGS)
2356 {
2357 LogFunc(("[SD%RU8]: Warning: Invalid stream tag %RU8 specified!\n", uSD, uTag));
2358 return hdaRegWriteU24(pThis, iReg, u32Value);
2359 }
2360
2361 PHDATAG pTag = &pThis->aTags[uTag];
2362 AssertPtr(pTag);
2363
2364 LogFunc(("[SD%RU8]: Using stream tag=%RU8\n", uSD, uTag));
2365
2366 /* Assign new values. */
2367 pTag->uTag = uTag;
2368 pTag->pStrm = hdaStreamGetFromSD(pThis, uSD);
2369
2370 PHDASTREAM pStream = pTag->pStrm;
2371 AssertPtr(pStream);
2372
2373 /* Note: Do not use hdaRegWriteSDLock() here, as SDnCTL might change the RUN bit. */
2374 int rc2 = RTCritSectEnter(&pStream->State.CritSect);
2375 AssertRC(rc2);
2376
2377 if (fInReset)
2378 {
2379 Assert(!fReset);
2380 Assert(!fInRun && !fRun);
2381
2382 /* Exit reset state. */
2383 ASMAtomicXchgBool(&pStream->State.fInReset, false);
2384
2385 /* Report that we're done resetting this stream by clearing SRST. */
2386 HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST);
2387
2388 LogFunc(("[SD%RU8]: Reset exit\n", uSD));
2389 }
2390 else if (fReset)
2391 {
2392 /* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
2393 Assert(!fInRun && !fRun);
2394
2395 LogFunc(("[SD%RU8]: Reset enter\n", pStream->u8SD));
2396
2397 /* Enter reset state. */
2398 Assert(ASMAtomicReadBool(&pStream->State.fInReset) == false); /* No nested calls. */
2399 ASMAtomicXchgBool(&pStream->State.fInReset, true);
2400
2401 hdaStreamReset(pThis, pStream);
2402 }
2403 else
2404 {
2405 /*
2406 * We enter here to change DMA states only.
2407 */
2408 if (fInRun != fRun)
2409 {
2410 Assert(!fReset && !fInReset);
2411 LogFunc(("[SD%RU8]: State changed (fRun=%RTbool)\n", pStream->u8SD, fRun));
2412
2413 if (fRun)
2414 {
2415 /* Make sure to first fetch the current BDLE before enabling the stream below. */
2416 rc2 = hdaBDLEFetch(pThis, &pStream->State.BDLE, pStream->u64BDLBase, pStream->State.uCurBDLE);
2417 AssertRC(rc2);
2418 }
2419
2420 hdaStreamEnable(pThis, pStream, fRun /* fEnable */);
2421 }
2422 }
2423
2424 rc2 = hdaRegWriteU24(pThis, iReg, u32Value);
2425 AssertRC(rc2);
2426
2427 /* Make sure to handle interrupts here as well. */
2428 hdaProcessInterrupt(pThis);
2429
2430 rc2 = RTCritSectLeave(&pStream->State.CritSect);
2431 AssertRC(rc2);
2432
2433 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2434#else /* !IN_RING3 */
2435 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2436 return VINF_IOM_R3_MMIO_WRITE;
2437#endif /* IN_RING3 */
2438}
2439
2440static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2441{
2442 uint32_t v = HDA_REG_IND(pThis, iReg);
2443
2444 /* Clear (zero) FIFOE, DESE and BCIS bits when writing 1 to it (6.2.33). */
2445 HDA_REG_IND(pThis, iReg) &= ~(u32Value & v);
2446
2447 LogFunc(("SDSTS 0x%x -> 0x%x\n", v, HDA_REG_IND(pThis, iReg)));
2448
2449 hdaProcessInterrupt(pThis);
2450 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2451}
2452
2453static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2454{
2455#ifdef IN_RING3
2456 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2457 return VINF_SUCCESS;
2458
2459 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, LVI, iReg);
2460
2461 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, uSD);
2462 if (!pStream)
2463 {
2464 AssertMsgFailed(("[SD%RU8]: Warning: Changing SDLVI on non-attached stream (0x%x)\n", uSD, u32Value));
2465 return hdaRegWriteU16(pThis, iReg, u32Value);
2466 }
2467
2468 /** @todo Validate LVI. */
2469 pStream->u16LVI = u32Value;
2470 LogFunc(("[SD%RU8]: Updating LVI to %RU16\n", uSD, pStream->u16LVI));
2471
2472 /* Reset BDLE state. */
2473 RT_ZERO(pStream->State.BDLE);
2474 pStream->State.uCurBDLE = 0;
2475
2476 int rc2 = hdaRegWriteU16(pThis, iReg, u32Value);
2477 AssertRC(rc2);
2478
2479 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2480#else /* !IN_RING3 */
2481 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2482 return VINF_IOM_R3_MMIO_WRITE;
2483#endif /* IN_RING3 */
2484}
2485
2486static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2487{
2488#ifdef IN_RING3
2489 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg);
2490
2491 if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_IN) /* FIFOW for input streams only. */
2492 {
2493 LogRel(("HDA: Warning: Guest tried to write read-only FIFOW to output stream #%RU8, ignoring\n", uSD));
2494 return VINF_SUCCESS;
2495 }
2496
2497 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg));
2498 if (!pStream)
2499 {
2500 AssertMsgFailed(("[SD%RU8]: Warning: Changing FIFOW on non-attached stream (0x%x)\n", uSD, u32Value));
2501 return hdaRegWriteU16(pThis, iReg, u32Value);
2502 }
2503
2504 uint32_t u32FIFOW = 0;
2505
2506 switch (u32Value)
2507 {
2508 case HDA_SDFIFOW_8B:
2509 case HDA_SDFIFOW_16B:
2510 case HDA_SDFIFOW_32B:
2511 u32FIFOW = u32Value;
2512 break;
2513 default:
2514 LogRel(("HDA: Warning: Guest tried write unsupported FIFOW (0x%x) to stream #%RU8, defaulting to 32 bytes\n",
2515 u32Value, uSD));
2516 AssertFailed();
2517 u32FIFOW = HDA_SDFIFOW_32B;
2518 break;
2519 }
2520
2521 if (u32FIFOW)
2522 {
2523 pStream->u16FIFOW = hdaSDFIFOWToBytes(u32FIFOW);
2524 LogFunc(("[SD%RU8]: Updating FIFOW to %RU32 bytes\n", uSD, pStream->u16FIFOW));
2525
2526 int rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOW);
2527 AssertRC(rc2);
2528 }
2529
2530 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2531#else /* !IN_RING3 */
2532 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2533 return VINF_IOM_R3_MMIO_WRITE;
2534#endif /* IN_RING3 */
2535}
2536
2537/**
2538 * @note This method could be called for changing value on Output Streams only (ICH6 datasheet 18.2.39).
2539 */
2540static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2541{
2542#ifdef IN_RING3
2543 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOS, iReg);
2544
2545 if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_OUT) /* FIFOS for output streams only. */
2546 {
2547 LogRel(("HDA: Warning: Guest tried to write read-only FIFOS to input stream #%RU8, ignoring\n", uSD));
2548 return VINF_SUCCESS;
2549 }
2550
2551 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, uSD);
2552 if (!pStream)
2553 {
2554 AssertMsgFailed(("[SD%RU8]: Warning: Changing FIFOS on non-attached stream (0x%x)\n", uSD, u32Value));
2555 return hdaRegWriteU16(pThis, iReg, u32Value);
2556 }
2557
2558 uint32_t u32FIFOS = 0;
2559
2560 switch(u32Value)
2561 {
2562 case HDA_SDOFIFO_16B:
2563 case HDA_SDOFIFO_32B:
2564 case HDA_SDOFIFO_64B:
2565 case HDA_SDOFIFO_128B:
2566 case HDA_SDOFIFO_192B:
2567 case HDA_SDOFIFO_256B:
2568 u32FIFOS = u32Value;
2569 break;
2570
2571 default:
2572 LogRel(("HDA: Warning: Guest tried write unsupported FIFOS (0x%x) to stream #%RU8, defaulting to 192 bytes\n",
2573 u32Value, uSD));
2574 AssertFailed();
2575 u32FIFOS = HDA_SDOFIFO_192B;
2576 break;
2577 }
2578
2579 if (u32FIFOS)
2580 {
2581 pStream->u16FIFOS = u32FIFOS + 1;
2582 LogFunc(("[SD%RU8]: Updating FIFOS to %RU32 bytes\n", uSD, pStream->u16FIFOS));
2583
2584 int rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOS);
2585 AssertRC(rc2);
2586 }
2587
2588 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2589#else /* !IN_RING3 */
2590 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2591 return VINF_IOM_R3_MMIO_WRITE;
2592#endif /* IN_RING3 */
2593}
2594
2595#ifdef IN_RING3
2596static int hdaSDFMTToStrmCfg(uint32_t u32SDFMT, PPDMAUDIOSTREAMCFG pStrmCfg)
2597{
2598 AssertPtrReturn(pStrmCfg, VERR_INVALID_POINTER);
2599
2600# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
2601
2602 int rc = VINF_SUCCESS;
2603
2604 uint32_t u32Hz = EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BASE_RATE_MASK, HDA_SDFMT_BASE_RATE_SHIFT)
2605 ? 44100 : 48000;
2606 uint32_t u32HzMult = 1;
2607 uint32_t u32HzDiv = 1;
2608
2609 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
2610 {
2611 case 0: u32HzMult = 1; break;
2612 case 1: u32HzMult = 2; break;
2613 case 2: u32HzMult = 3; break;
2614 case 3: u32HzMult = 4; break;
2615 default:
2616 LogFunc(("Unsupported multiplier %x\n",
2617 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
2618 rc = VERR_NOT_SUPPORTED;
2619 break;
2620 }
2621 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
2622 {
2623 case 0: u32HzDiv = 1; break;
2624 case 1: u32HzDiv = 2; break;
2625 case 2: u32HzDiv = 3; break;
2626 case 3: u32HzDiv = 4; break;
2627 case 4: u32HzDiv = 5; break;
2628 case 5: u32HzDiv = 6; break;
2629 case 6: u32HzDiv = 7; break;
2630 case 7: u32HzDiv = 8; break;
2631 default:
2632 LogFunc(("Unsupported divisor %x\n",
2633 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
2634 rc = VERR_NOT_SUPPORTED;
2635 break;
2636 }
2637
2638 PDMAUDIOFMT enmFmt;
2639 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
2640 {
2641 case 0:
2642 enmFmt = PDMAUDIOFMT_S8;
2643 break;
2644 case 1:
2645 enmFmt = PDMAUDIOFMT_S16;
2646 break;
2647 case 4:
2648 enmFmt = PDMAUDIOFMT_S32;
2649 break;
2650 default:
2651 AssertMsgFailed(("Unsupported bits per sample %x\n",
2652 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
2653 enmFmt = PDMAUDIOFMT_INVALID;
2654 rc = VERR_NOT_SUPPORTED;
2655 break;
2656 }
2657
2658 if (RT_SUCCESS(rc))
2659 {
2660 pStrmCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
2661 pStrmCfg->cChannels = (u32SDFMT & 0xf) + 1;
2662 pStrmCfg->enmFormat = enmFmt;
2663 pStrmCfg->enmEndianness = PDMAUDIOHOSTENDIANNESS;
2664 }
2665
2666# undef EXTRACT_VALUE
2667 return rc;
2668}
2669
2670static int hdaAddStreamOut(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
2671{
2672 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2673 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2674
2675 AssertReturn(pCfg->enmDir == PDMAUDIODIR_OUT, VERR_INVALID_PARAMETER);
2676
2677 LogFlowFunc(("Stream=%s\n", pCfg->szName));
2678
2679 int rc = VINF_SUCCESS;
2680
2681 bool fUseFront = true; /* Always use front out by default. */
2682#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2683 bool fUseRear;
2684 bool fUseCenter;
2685 bool fUseLFE;
2686
2687 fUseRear = fUseCenter = fUseLFE = false;
2688
2689 /*
2690 * Use commonly used setups for speaker configurations.
2691 */
2692
2693 /** @todo Make the following configurable through mixer API and/or CFGM? */
2694 switch (pCfg->cChannels)
2695 {
2696 case 3: /* 2.1: Front (Stereo) + LFE. */
2697 {
2698 fUseLFE = true;
2699 break;
2700 }
2701
2702 case 4: /* Quadrophonic: Front (Stereo) + Rear (Stereo). */
2703 {
2704 fUseRear = true;
2705 break;
2706 }
2707
2708 case 5: /* 4.1: Front (Stereo) + Rear (Stereo) + LFE. */
2709 {
2710 fUseRear = true;
2711 fUseLFE = true;
2712 break;
2713 }
2714
2715 case 6: /* 5.1: Front (Stereo) + Rear (Stereo) + Center/LFE. */
2716 {
2717 fUseRear = true;
2718 fUseCenter = true;
2719 fUseLFE = true;
2720 break;
2721 }
2722
2723 default: /* Unknown; fall back to 2 front channels (stereo). */
2724 {
2725 rc = VERR_NOT_SUPPORTED;
2726 break;
2727 }
2728 }
2729#else /* !VBOX_WITH_AUDIO_HDA_51_SURROUND */
2730 /* Only support mono or stereo channels. */
2731 if ( pCfg->cChannels != 1 /* Mono */
2732 && pCfg->cChannels != 2 /* Stereo */)
2733 {
2734 rc = VERR_NOT_SUPPORTED;
2735 }
2736#endif
2737
2738 if (rc == VERR_NOT_SUPPORTED)
2739 {
2740 LogRel(("HDA: Unsupported channel count (%RU8), falling back to stereo channels\n", pCfg->cChannels));
2741 pCfg->cChannels = 2;
2742
2743 rc = VINF_SUCCESS;
2744 }
2745
2746 do
2747 {
2748 if (RT_FAILURE(rc))
2749 break;
2750
2751 if (fUseFront)
2752 {
2753 RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Front");
2754 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_FRONT;
2755 pCfg->cChannels = 2;
2756
2757 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT);
2758 if (RT_SUCCESS(rc))
2759 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT, pCfg);
2760 }
2761
2762#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2763 if ( RT_SUCCESS(rc)
2764 && (fUseCenter || fUseLFE))
2765 {
2766 RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Center/LFE");
2767 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_CENTER_LFE;
2768 pCfg->cChannels = (fUseCenter && fUseLFE) ? 2 : 1;
2769
2770 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE);
2771 if (RT_SUCCESS(rc))
2772 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE, pCfg);
2773 }
2774
2775 if ( RT_SUCCESS(rc)
2776 && fUseRear)
2777 {
2778 RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Rear");
2779 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_REAR;
2780 pCfg->cChannels = 2;
2781
2782 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR);
2783 if (RT_SUCCESS(rc))
2784 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR, pCfg);
2785 }
2786#endif /* VBOX_WITH_AUDIO_HDA_51_SURROUND */
2787
2788 } while (0);
2789
2790 LogFlowFuncLeaveRC(rc);
2791 return rc;
2792}
2793
2794static int hdaAddStreamIn(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
2795{
2796 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2797 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2798
2799 AssertReturn(pCfg->enmDir == PDMAUDIODIR_IN, VERR_INVALID_PARAMETER);
2800
2801 LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Source));
2802
2803 int rc;
2804
2805 switch (pCfg->DestSource.Source)
2806 {
2807 case PDMAUDIORECSOURCE_LINE:
2808 {
2809 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN);
2810 if (RT_SUCCESS(rc))
2811 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN, pCfg);
2812 break;
2813 }
2814#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2815 case PDMAUDIORECSOURCE_MIC:
2816 {
2817 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN);
2818 if (RT_SUCCESS(rc))
2819 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN, pCfg);
2820 break;
2821 }
2822#endif
2823 default:
2824 rc = VERR_NOT_SUPPORTED;
2825 break;
2826 }
2827
2828 LogFlowFuncLeaveRC(rc);
2829 return rc;
2830}
2831#endif /* IN_RING3 */
2832
2833static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2834{
2835#ifdef IN_RING3
2836 PDMAUDIOSTREAMCFG strmCfg;
2837 RT_ZERO(strmCfg);
2838
2839 int rc = hdaSDFMTToStrmCfg(u32Value, &strmCfg);
2840 if (RT_FAILURE(rc))
2841 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2842
2843 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FMT, iReg));
2844 if (!pStream)
2845 {
2846 LogFunc(("[SD%RU8]: Warning: Changing SDFMT on non-attached stream (0x%x)\n",
2847 HDA_SD_NUM_FROM_REG(pThis, FMT, iReg), u32Value));
2848 return hdaRegWriteU16(pThis, iReg, u32Value);
2849 }
2850
2851 LogFunc(("[SD%RU8]: Hz=%RU32, Channels=%RU8, enmFmt=%RU32\n",
2852 pStream->u8SD, strmCfg.uHz, strmCfg.cChannels, strmCfg.enmFormat));
2853
2854 /* Set audio direction. */
2855 strmCfg.enmDir = hdaGetDirFromSD(pStream->u8SD);
2856 switch (strmCfg.enmDir)
2857 {
2858 case PDMAUDIODIR_IN:
2859# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2860# error "Implement me!"
2861# else
2862 strmCfg.DestSource.Source = PDMAUDIORECSOURCE_LINE;
2863 RTStrCopy(strmCfg.szName, sizeof(strmCfg.szName), "Line In");
2864# endif
2865 break;
2866
2867 case PDMAUDIODIR_OUT:
2868 /* Destination(s) will be set in hdaAddStreamOut(),
2869 * based on the channels / stream layout. */
2870 break;
2871
2872 default:
2873 rc = VERR_NOT_SUPPORTED;
2874 break;
2875 }
2876
2877#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2878 if (RT_SUCCESS(rc))
2879 {
2880 rc = hdaStreamAsyncIOCreate(pThis, pStream);
2881 AssertRC(rc);
2882 }
2883#endif
2884
2885 /*
2886 * Initialize the stream mapping in any case, regardless if
2887 * we support surround audio or not. This is needed to handle
2888 * the supported channels within a single audio stream, e.g. mono/stereo.
2889 *
2890 * In other words, the stream mapping *always* knowns the real
2891 * number of channels in a single audio stream.
2892 */
2893 if (RT_SUCCESS(rc))
2894 {
2895 rc = hdaStreamMapInit(&pStream->State.Mapping, &strmCfg);
2896 AssertRC(rc);
2897 }
2898
2899 if (RT_SUCCESS(rc))
2900 {
2901 PHDADRIVER pDrv;
2902 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2903 {
2904 int rc2;
2905 switch (strmCfg.enmDir)
2906 {
2907 case PDMAUDIODIR_OUT:
2908 rc2 = hdaAddStreamOut(pThis, &strmCfg);
2909 break;
2910
2911 case PDMAUDIODIR_IN:
2912 rc2 = hdaAddStreamIn(pThis, &strmCfg);
2913 break;
2914
2915 default:
2916 rc2 = VERR_NOT_SUPPORTED;
2917 AssertFailed();
2918 break;
2919 }
2920
2921 if ( RT_FAILURE(rc2)
2922 && (pDrv->Flags & PDMAUDIODRVFLAGS_PRIMARY)) /* We only care about primary drivers here, the rest may fail. */
2923 {
2924 if (RT_SUCCESS(rc))
2925 rc = rc2;
2926 /* Keep going. */
2927 }
2928 }
2929
2930 /* If (re-)opening the stream by the codec above failed, don't write the new
2931 * format to the register so that the guest is aware it didn't work. */
2932 if (RT_SUCCESS(rc))
2933 {
2934 rc = hdaRegWriteU16(pThis, iReg, u32Value);
2935 AssertRC(rc);
2936 }
2937 else
2938 LogFunc(("[SD%RU8]: (Re-)Opening stream failed with rc=%Rrc\n", pStream->u8SD, rc));
2939 }
2940
2941 return VINF_SUCCESS; /* Never return failure. */
2942#else /* !IN_RING3 */
2943 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2944 return VINF_IOM_R3_MMIO_WRITE;
2945#endif
2946}
2947
2948/* Note: Will be called for both, BDPL and BDPU, registers. */
2949DECLINLINE(int) hdaRegWriteSDBDPX(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value, uint8_t uSD)
2950{
2951#ifdef IN_RING3
2952 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2953 return VINF_SUCCESS;
2954
2955 int rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2956 AssertRC(rc2);
2957
2958 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, uSD);
2959 if (!pStream)
2960 return VINF_SUCCESS;
2961
2962 /* Update BDL base. */
2963 pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, uSD),
2964 HDA_STREAM_REG(pThis, BDPU, uSD));
2965 AssertMsg(pStream->u64BDLBase, ("BDL base invalid\n"));
2966
2967 /* Reset BDLE state. */
2968 RT_ZERO(pStream->State.BDLE);
2969 pStream->State.uCurBDLE = 0;
2970
2971 LogFlowFunc(("[SD%RU8]: BDLBase=0x%x\n", pStream->u8SD, pStream->u64BDLBase));
2972
2973 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2974#else /* !IN_RING3 */
2975 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value); RT_NOREF_PV(uSD);
2976 return VINF_IOM_R3_MMIO_WRITE;
2977#endif /* IN_RING3 */
2978}
2979
2980static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2981{
2982 return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPL, iReg));
2983}
2984
2985static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2986{
2987 return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPU, iReg));
2988}
2989
2990static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2991{
2992 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
2993 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2994 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
2995 {
2996 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
2997 }
2998
2999 return hdaRegReadU32(pThis, iReg, pu32Value);
3000}
3001
3002static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3003{
3004 RT_NOREF_PV(iReg);
3005
3006 /*
3007 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
3008 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
3009 */
3010 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
3011 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
3012 {
3013#ifdef IN_RING3
3014 uint32_t uCmd = HDA_REG(pThis, IC);
3015
3016 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
3017 {
3018 /*
3019 * 3.4.3: Defines behavior of immediate Command status register.
3020 */
3021 LogRel(("HDA: Guest attempted process immediate verb (%x) with active CORB\n", uCmd));
3022 return VINF_SUCCESS;
3023 }
3024
3025 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
3026
3027 uint64_t uResp;
3028 int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec,
3029 HDA_CODEC_CMD(uCmd, 0 /* LUN */), &uResp);
3030 if (RT_FAILURE(rc2))
3031 LogFunc(("Codec lookup failed with rc2=%Rrc\n", rc2));
3032
3033 HDA_REG(pThis, IR) = (uint32_t)uResp; /** @todo r=andy Do we need a 64-bit response? */
3034 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
3035 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
3036 return VINF_SUCCESS;
3037#else /* !IN_RING3 */
3038 return VINF_IOM_R3_MMIO_WRITE;
3039#endif /* !IN_RING3 */
3040 }
3041
3042 /*
3043 * Once the guest read the response, it should clean the IRV bit of the IRS register.
3044 */
3045 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
3046 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
3047 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
3048 return VINF_SUCCESS;
3049}
3050
3051static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3052{
3053 RT_NOREF_PV(iReg);
3054
3055 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
3056 HDA_REG(pThis, RIRBWP) = 0;
3057
3058 /* The remaining bits are O, see 6.2.22. */
3059 return VINF_SUCCESS;
3060}
3061
3062static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3063{
3064 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
3065 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
3066 if (RT_FAILURE(rc))
3067 AssertRCReturn(rc, rc);
3068
3069 switch(iReg)
3070 {
3071 case HDA_REG_CORBLBASE:
3072 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
3073 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
3074 break;
3075 case HDA_REG_CORBUBASE:
3076 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
3077 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3078 break;
3079 case HDA_REG_RIRBLBASE:
3080 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
3081 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
3082 break;
3083 case HDA_REG_RIRBUBASE:
3084 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
3085 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3086 break;
3087 case HDA_REG_DPLBASE:
3088 {
3089 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
3090 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
3091
3092 /* Also make sure to handle the DMA position enable bit. */
3093 pThis->fDMAPosition = RT_BOOL(pThis->u64DPBase & RT_BIT_64(0));
3094 LogRel2(("HDA: %s DMA position buffer\n", pThis->fDMAPosition ? "Enabled" : "Disabled"));
3095 break;
3096 }
3097 case HDA_REG_DPUBASE:
3098 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
3099 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3100 break;
3101 default:
3102 AssertMsgFailed(("Invalid index\n"));
3103 break;
3104 }
3105
3106 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
3107 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
3108 return rc;
3109}
3110
3111static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3112{
3113 RT_NOREF_PV(iReg);
3114
3115 uint8_t v = HDA_REG(pThis, RIRBSTS);
3116 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
3117
3118 return hdaProcessInterrupt(pThis);
3119}
3120
3121#ifdef IN_RING3
3122#ifdef LOG_ENABLED
3123static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BDLBase, uint16_t cBDLE)
3124{
3125 LogFlowFunc(("BDLEs @ 0x%x (%RU16):\n", u64BDLBase, cBDLE));
3126 if (!u64BDLBase)
3127 return;
3128
3129 uint32_t cbBDLE = 0;
3130 for (uint16_t i = 0; i < cBDLE; i++)
3131 {
3132 HDABDLEDESC bd;
3133 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BDLBase + i * sizeof(HDABDLEDESC), &bd, sizeof(bd));
3134
3135 LogFunc(("\t#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
3136 i, bd.u64BufAdr, bd.u32BufSize, bd.fFlags & HDA_BDLE_FLAG_IOC));
3137
3138 cbBDLE += bd.u32BufSize;
3139 }
3140
3141 LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
3142
3143 if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
3144 return;
3145
3146 LogFlowFunc(("DMA counters:\n"));
3147
3148 for (int i = 0; i < cBDLE; i++)
3149 {
3150 uint32_t uDMACnt;
3151 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
3152 &uDMACnt, sizeof(uDMACnt));
3153
3154 LogFlowFunc(("\t#%03d DMA @ 0x%x\n", i , uDMACnt));
3155 }
3156}
3157#endif
3158
3159/**
3160 * Fetches a Bundle Descriptor List Entry (BDLE) from the DMA engine.
3161 *
3162 * @param pThis Pointer to HDA state.
3163 * @param pBDLE Where to store the fetched result.
3164 * @param u64BaseDMA Address base of DMA engine to use.
3165 * @param u16Entry BDLE entry to fetch.
3166 */
3167static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry)
3168{
3169 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3170 AssertPtrReturn(pBDLE, VERR_INVALID_POINTER);
3171 AssertReturn(u64BaseDMA, VERR_INVALID_PARAMETER);
3172
3173 if (!u64BaseDMA)
3174 {
3175 LogRel2(("HDA: Unable to fetch BDLE #%RU16 - no base DMA address set (yet)\n", u16Entry));
3176 return VERR_NOT_FOUND;
3177 }
3178 /** @todo Compare u16Entry with LVI. */
3179
3180 int rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + u16Entry * sizeof(HDABDLEDESC),
3181 &pBDLE->Desc, sizeof(pBDLE->Desc));
3182 if (RT_FAILURE(rc))
3183 return rc;
3184
3185 /* Set internal state. */
3186 pBDLE->State.u32BufOff = 0;
3187 pBDLE->State.u32BDLIndex = u16Entry;
3188
3189 return VINF_SUCCESS;
3190}
3191
3192/**
3193 * Returns the number of outstanding stream data bytes which need to be processed
3194 * by the DMA engine assigned to this stream.
3195 *
3196 * @return Number of bytes for the DMA engine to process.
3197 */
3198DECLINLINE(uint32_t) hdaStreamGetTransferSize(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbMax)
3199{
3200 AssertPtrReturn(pThis, 0);
3201 AssertPtrReturn(pStream, 0);
3202 AssertReturn (cbMax, 0);
3203
3204 PHDABDLE pBDLE = &pStream->State.BDLE;
3205
3206 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3207 Assert(u32LPIB <= pStream->u32CBL);
3208
3209 /* Do we have space left in the CBL at all? */
3210 uint32_t cbData = pStream->u32CBL - u32LPIB;
3211
3212 /* Limit to the available free space of the current BDLE. */
3213 cbData = RT_MIN(cbData, pBDLE->Desc.u32BufSize - pBDLE->State.u32BufOff);
3214
3215 /* Make sure we only transfer as many bytes as requested. */
3216 cbData = RT_MIN(cbData, cbMax);
3217
3218 if (pBDLE->State.cbBelowFIFOW)
3219 {
3220 /* Are we not going to reach (or exceed) the FIFO watermark yet with the data to copy?
3221 * No need to read data from DMA then. */
3222 if (cbData > pBDLE->State.cbBelowFIFOW)
3223 {
3224 /* Subtract the amount of bytes that still would fit in the stream's FIFO
3225 * and therefore do not need to be processed by DMA. */
3226 cbData -= pBDLE->State.cbBelowFIFOW;
3227 }
3228 }
3229
3230 AssertMsg((cbData % 2 == 0), ("Transfer size invalid: %RU32\n", cbData));
3231
3232 Log3Func(("[SD%RU8]: CBL=%RU32, LPIB=%RU32, FIFOS=%RU16, cbData=%RU32, %R[bdle]\n", pStream->u8SD,
3233 pStream->u32CBL, HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), pStream->u16FIFOS,
3234 cbData, pBDLE));
3235
3236 return cbData;
3237}
3238
3239DECLINLINE(void) hdaBDLEUpdate(PHDABDLE pBDLE, uint32_t cbData, uint32_t cbProcessed)
3240{
3241 AssertPtrReturnVoid(pBDLE);
3242
3243 if (!cbData || !cbProcessed)
3244 return;
3245
3246 Assert(pBDLE->Desc.u32BufSize >= cbProcessed);
3247
3248 /* Fewer than cbBelowFIFOW bytes were copied.
3249 * Probably we need to move the buffer, but it is rather hard to imagine a situation
3250 * where it might happen. */
3251 AssertMsg((cbProcessed == pBDLE->State.cbBelowFIFOW + cbData), /* we assume that we write the entire buffer including unreported bytes */
3252 ("cbProcessed=%RU32 != pBDLE->State.cbBelowFIFOW=%RU32 + cbData=%RU32\n",
3253 cbProcessed, pBDLE->State.cbBelowFIFOW, cbData));
3254
3255#if 0
3256 if ( pBDLE->State.cbBelowFIFOW
3257 && pBDLE->State.cbBelowFIFOW <= cbWritten)
3258 {
3259 LogFlowFunc(("BDLE(cbUnderFifoW:%RU32, off:%RU32, size:%RU32)\n",
3260 pBDLE->State.cbBelowFIFOW, pBDLE->State.u32BufOff, pBDLE->Desc.u32BufSize));
3261 }
3262#endif
3263
3264 pBDLE->State.cbBelowFIFOW -= RT_MIN(pBDLE->State.cbBelowFIFOW, cbProcessed);
3265 Assert(pBDLE->State.cbBelowFIFOW == 0);
3266
3267 /* We always increment the position of DMA buffer counter because we're always reading
3268 * into an intermediate buffer. */
3269 Assert(pBDLE->Desc.u32BufSize >= (pBDLE->State.u32BufOff + cbProcessed));
3270 pBDLE->State.u32BufOff += cbProcessed;
3271
3272 LogFlowFunc(("cbData=%RU32, cbProcessed=%RU32, %R[bdle]\n", cbData, cbProcessed, pBDLE));
3273}
3274
3275#ifdef IN_RING3
3276/**
3277 * Initializes a stream mapping structure according to the given stream configuration.
3278 *
3279 * @return IPRT status code.
3280 * @param pMapping Pointer to mapping to initialize.
3281 * @param pCfg Pointer to stream configuration to use.
3282 */
3283static int hdaStreamMapInit(PHDASTREAMMAPPING pMapping, PPDMAUDIOSTREAMCFG pCfg)
3284{
3285 AssertPtrReturn(pMapping, VERR_INVALID_POINTER);
3286 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3287
3288 AssertReturn(pCfg->cChannels, VERR_INVALID_PARAMETER);
3289
3290 hdaStreamMapReset(pMapping);
3291
3292 pMapping->paChannels = (PPDMAUDIOSTREAMCHANNEL)RTMemAlloc(sizeof(PDMAUDIOSTREAMCHANNEL) * pCfg->cChannels);
3293 if (!pMapping->paChannels)
3294 return VERR_NO_MEMORY;
3295
3296 PDMAUDIOPCMPROPS Props;
3297 int rc = DrvAudioHlpStreamCfgToProps(pCfg, &Props);
3298 if (RT_FAILURE(rc))
3299 return rc;
3300
3301 Assert(RT_IS_POWER_OF_TWO(Props.cBits));
3302
3303 /** @todo We assume all channels in a stream have the same format. */
3304 PPDMAUDIOSTREAMCHANNEL pChan = pMapping->paChannels;
3305 for (uint8_t i = 0; i < pCfg->cChannels; i++)
3306 {
3307 pChan->uChannel = i;
3308 pChan->cbStep = (Props.cBits / 2);
3309 pChan->cbFrame = pChan->cbStep * pCfg->cChannels;
3310 pChan->cbFirst = i * pChan->cbStep;
3311 pChan->cbOff = pChan->cbFirst;
3312
3313 int rc2 = hdaStreamChannelDataInit(&pChan->Data, PDMAUDIOSTREAMCHANNELDATA_FLAG_NONE);
3314 if (RT_SUCCESS(rc))
3315 rc = rc2;
3316
3317 if (RT_FAILURE(rc))
3318 break;
3319
3320 pChan++;
3321 }
3322
3323 if ( RT_SUCCESS(rc)
3324 /* Create circular buffer if not created yet. */
3325 && !pMapping->pCircBuf)
3326 {
3327 rc = RTCircBufCreate(&pMapping->pCircBuf, _4K); /** @todo Make size configurable? */
3328 }
3329
3330 if (RT_SUCCESS(rc))
3331 {
3332 pMapping->cChannels = pCfg->cChannels;
3333#ifdef VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT
3334 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_INTERLEAVED;
3335#else
3336 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
3337#endif
3338 }
3339
3340 return rc;
3341}
3342
3343/**
3344 * Destroys a given stream mapping.
3345 *
3346 * @param pMapping Pointer to mapping to destroy.
3347 */
3348static void hdaStreamMapDestroy(PHDASTREAMMAPPING pMapping)
3349{
3350 hdaStreamMapReset(pMapping);
3351
3352 if (pMapping->pCircBuf)
3353 {
3354 RTCircBufDestroy(pMapping->pCircBuf);
3355 pMapping->pCircBuf = NULL;
3356 }
3357}
3358
3359/**
3360 * Resets a given stream mapping.
3361 *
3362 * @param pMapping Pointer to mapping to reset.
3363 */
3364static void hdaStreamMapReset(PHDASTREAMMAPPING pMapping)
3365{
3366 AssertPtrReturnVoid(pMapping);
3367
3368 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_UNKNOWN;
3369
3370 if (pMapping->cChannels)
3371 {
3372 for (uint8_t i = 0; i < pMapping->cChannels; i++)
3373 hdaStreamChannelDataDestroy(&pMapping->paChannels[i].Data);
3374
3375 AssertPtr(pMapping->paChannels);
3376 RTMemFree(pMapping->paChannels);
3377 pMapping->paChannels = NULL;
3378
3379 pMapping->cChannels = 0;
3380 }
3381}
3382#endif /* IN_RING3 */
3383
3384DECLINLINE(bool) hdaStreamNeedsNextBDLE(PHDASTATE pThis, PHDASTREAM pStream)
3385{
3386 AssertPtrReturn(pThis, false);
3387 AssertPtrReturn(pStream, false);
3388
3389 PHDABDLE pBDLE = &pStream->State.BDLE;
3390 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3391
3392 /* Did we reach the CBL (Cyclic Buffer List) limit? */
3393 bool fCBLLimitReached = u32LPIB >= pStream->u32CBL;
3394
3395 /* Do we need to use the next BDLE entry? Either because we reached
3396 * the CBL limit or our internal DMA buffer is full. */
3397 bool fNeedsNextBDLE = ( fCBLLimitReached
3398 || (pBDLE->State.u32BufOff >= pBDLE->Desc.u32BufSize));
3399
3400 Assert(u32LPIB <= pStream->u32CBL);
3401 Assert(pBDLE->State.u32BufOff <= pBDLE->Desc.u32BufSize);
3402
3403 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32, fCBLLimitReached=%RTbool, fNeedsNextBDLE=%RTbool, %R[bdle]\n",
3404 pStream->u8SD, u32LPIB, pStream->u32CBL, fCBLLimitReached, fNeedsNextBDLE, pBDLE));
3405
3406 return fNeedsNextBDLE;
3407}
3408
3409DECLINLINE(void) hdaStreamTransferUpdate(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbInc)
3410{
3411 AssertPtrReturnVoid(pThis);
3412 AssertPtrReturnVoid(pStream);
3413
3414 if (!cbInc) /* Nothing to do? Bail out early. */
3415 return;
3416
3417 /*
3418 * If we're below the FIFO watermark (SDFIFOW), it's expected that HDA
3419 * doesn't fetch anything via DMA, so just update LPIB.
3420 * (ICH6 datasheet 18.2.38).
3421 */
3422 PHDABDLE pBDLE = &pStream->State.BDLE;
3423 if (pBDLE->State.cbBelowFIFOW == 0) /* Did we hit (or exceed) the watermark? */
3424 {
3425 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) + cbInc;
3426
3427 Log3Func(("[SD%RU8]: LPIB: %RU32 -> %RU32, CBL=%RU32\n",
3428 pStream->u8SD, HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), u32LPIB, pStream->u32CBL));
3429
3430 hdaStreamUpdateLPIB(pThis, pStream, u32LPIB);
3431 }
3432}
3433
3434static bool hdaBDLEIsComplete(PHDABDLE pBDLE, bool *pfInterrupt)
3435{
3436 AssertPtrReturn(pBDLE, true);
3437
3438 bool fInterrupt = false;
3439 bool fIsComplete = false;
3440
3441 /* Check if the current BDLE entry is complete (full). */
3442 if (pBDLE->State.u32BufOff >= pBDLE->Desc.u32BufSize)
3443 {
3444 Assert(pBDLE->State.u32BufOff <= pBDLE->Desc.u32BufSize);
3445
3446 if (/* IOC (Interrupt On Completion) bit set? */
3447 pBDLE->Desc.fFlags & HDA_BDLE_FLAG_IOC
3448 /* All data put into the DMA FIFO? */
3449 && pBDLE->State.cbBelowFIFOW == 0
3450 )
3451 {
3452 fInterrupt = true;
3453 }
3454
3455 fIsComplete = true;
3456 }
3457
3458 if (pfInterrupt)
3459 *pfInterrupt = fInterrupt;
3460
3461 LogFlowFunc(("%R[bdle] fIsComplete=%RTbool, fInterrupt=%RTbool\n", pBDLE, fIsComplete, fInterrupt));
3462
3463 return fIsComplete;
3464}
3465
3466/**
3467 * Retrieves a corresponding sink for a given mixer control.
3468 * Returns NULL if no sink is found.
3469 *
3470 * @return PHDAMIXERSINK
3471 * @param pThis HDA state.
3472 * @param enmMixerCtl Mixer control to get the corresponding sink for.
3473 */
3474static PHDAMIXERSINK hdaMixerControlToSink(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
3475{
3476 PHDAMIXERSINK pSink;
3477
3478 switch (enmMixerCtl)
3479 {
3480 case PDMAUDIOMIXERCTL_VOLUME_MASTER:
3481 /* Fall through is intentional. */
3482 case PDMAUDIOMIXERCTL_FRONT:
3483 pSink = &pThis->SinkFront;
3484 break;
3485#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3486 case PDMAUDIOMIXERCTL_CENTER_LFE:
3487 pSink = &pThis->SinkCenterLFE;
3488 break;
3489 case PDMAUDIOMIXERCTL_REAR:
3490 pSink = &pThis->SinkRear;
3491 break;
3492#endif
3493 case PDMAUDIOMIXERCTL_LINE_IN:
3494 pSink = &pThis->SinkLineIn;
3495 break;
3496#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3497 case PDMAUDIOMIXERCTL_MIC_IN:
3498 pSink = &pThis->SinkMicIn;
3499 break;
3500#endif
3501 default:
3502 pSink = NULL;
3503 AssertMsgFailed(("Unhandled mixer control\n"));
3504 break;
3505 }
3506
3507 return pSink;
3508}
3509
3510static DECLCALLBACK(int) hdaMixerAddStream(PHDASTATE pThis, PHDAMIXERSINK pSink, PPDMAUDIOSTREAMCFG pCfg)
3511{
3512 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3513 AssertPtrReturn(pSink, VERR_INVALID_POINTER);
3514 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3515
3516 LogFunc(("Sink=%s, Stream=%s\n", pSink->pMixSink->pszName, pCfg->szName));
3517
3518 /* Update the sink's format. */
3519 PDMAUDIOPCMPROPS PCMProps;
3520 int rc = DrvAudioHlpStreamCfgToProps(pCfg, &PCMProps);
3521 if (RT_SUCCESS(rc))
3522 rc = AudioMixerSinkSetFormat(pSink->pMixSink, &PCMProps);
3523
3524 if (RT_FAILURE(rc))
3525 return rc;
3526
3527 PHDADRIVER pDrv;
3528 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3529 {
3530 int rc2 = VINF_SUCCESS;
3531 PHDADRIVERSTREAM pDrvStream = NULL;
3532
3533 PPDMAUDIOSTREAMCFG pStreamCfg = (PPDMAUDIOSTREAMCFG)RTMemDup(pCfg, sizeof(PDMAUDIOSTREAMCFG));
3534 if (!pStreamCfg)
3535 {
3536 rc = VERR_NO_MEMORY;
3537 break;
3538 }
3539
3540 /* Include the driver's LUN in the stream name for easier identification. */
3541 RTStrPrintf(pStreamCfg->szName, RT_ELEMENTS(pStreamCfg->szName), "[LUN#%RU8] %s", pDrv->uLUN, pCfg->szName);
3542
3543 if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
3544 {
3545 LogFunc(("enmRecSource=%d\n", pStreamCfg->DestSource.Source));
3546
3547 switch (pStreamCfg->DestSource.Source)
3548 {
3549 case PDMAUDIORECSOURCE_LINE:
3550 pDrvStream = &pDrv->LineIn;
3551 break;
3552#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3553 case PDMAUDIORECSOURCE_MIC:
3554 pDrvStream = &pDrv->MicIn;
3555 break;
3556#endif
3557 default:
3558 rc2 = VERR_NOT_SUPPORTED;
3559 break;
3560 }
3561 }
3562 else if (pStreamCfg->enmDir == PDMAUDIODIR_OUT)
3563 {
3564 LogFunc(("enmPlaybackDest=%d\n", pStreamCfg->DestSource.Dest));
3565
3566 switch (pStreamCfg->DestSource.Dest)
3567 {
3568 case PDMAUDIOPLAYBACKDEST_FRONT:
3569 pDrvStream = &pDrv->Front;
3570 break;
3571#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3572 case PDMAUDIOPLAYBACKDEST_CENTER_LFE:
3573 pDrvStream = &pDrv->CenterLFE;
3574 break;
3575 case PDMAUDIOPLAYBACKDEST_REAR:
3576 pDrvStream = &pDrv->Rear;
3577 break;
3578#endif
3579 default:
3580 rc2 = VERR_NOT_SUPPORTED;
3581 break;
3582 }
3583 }
3584 else
3585 rc2 = VERR_NOT_SUPPORTED;
3586
3587 if (RT_SUCCESS(rc2))
3588 {
3589 AssertPtr(pDrvStream);
3590
3591 AudioMixerSinkRemoveStream(pSink->pMixSink, pDrvStream->pMixStrm);
3592
3593 AudioMixerStreamDestroy(pDrvStream->pMixStrm);
3594 pDrvStream->pMixStrm = NULL;
3595
3596 PAUDMIXSTREAM pMixStrm;
3597 rc2 = AudioMixerSinkCreateStream(pSink->pMixSink, pDrv->pConnector, pStreamCfg, 0 /* fFlags */, &pMixStrm);
3598 if (RT_SUCCESS(rc2))
3599 {
3600 rc2 = AudioMixerSinkAddStream(pSink->pMixSink, pMixStrm);
3601 LogFlowFunc(("LUN#%RU8: Added \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName , rc2));
3602 }
3603
3604 if (RT_SUCCESS(rc2))
3605 pDrvStream->pMixStrm = pMixStrm;
3606 }
3607
3608 if (RT_SUCCESS(rc))
3609 rc = rc2;
3610
3611 if (pStreamCfg)
3612 {
3613 RTMemFree(pStreamCfg);
3614 pStreamCfg = NULL;
3615 }
3616 }
3617
3618 LogFlowFuncLeaveRC(rc);
3619 return rc;
3620}
3621
3622/**
3623 * Adds a new audio stream to a specific mixer control.
3624 * Depending on the mixer control the stream then gets assigned to one of the internal
3625 * mixer sinks, which in turn then handle the mixing of all connected streams to that sink.
3626 *
3627 * @return IPRT status code.
3628 * @param pThis HDA state.
3629 * @param enmMixerCtl Mixer control to assign new stream to.
3630 * @param pCfg Stream configuration for the new stream.
3631 */
3632static DECLCALLBACK(int) hdaMixerAddStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOSTREAMCFG pCfg)
3633{
3634 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3635 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3636
3637 int rc;
3638
3639 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3640 if (pSink)
3641 {
3642 rc = hdaMixerAddStream(pThis, pSink, pCfg);
3643
3644 AssertPtr(pSink->pMixSink);
3645 LogFlowFunc(("Sink=%s, enmMixerCtl=%d\n", pSink->pMixSink->pszName, enmMixerCtl));
3646 }
3647 else
3648 rc = VERR_NOT_FOUND;
3649
3650 LogFlowFuncLeaveRC(rc);
3651 return rc;
3652}
3653
3654/**
3655 * Removes a specified mixer control from the HDA's mixer.
3656 *
3657 * @return IPRT status code.
3658 * @param pThis HDA state.
3659 * @param enmMixerCtl Mixer control to remove.
3660 */
3661static DECLCALLBACK(int) hdaMixerRemoveStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
3662{
3663 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3664
3665 int rc;
3666
3667 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3668 if (pSink)
3669 {
3670 PHDADRIVER pDrv;
3671 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3672 {
3673 PAUDMIXSTREAM pMixStream = NULL;
3674 switch (enmMixerCtl)
3675 {
3676 /*
3677 * Input.
3678 */
3679 case PDMAUDIOMIXERCTL_LINE_IN:
3680 pMixStream = pDrv->LineIn.pMixStrm;
3681 pDrv->LineIn.pMixStrm = NULL;
3682 break;
3683#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3684 case PDMAUDIOMIXERCTL_MIC_IN:
3685 pMixStream = pDrv->MicIn.pMixStrm;
3686 pDrv->MicIn.pMixStrm = NULL;
3687 break;
3688#endif
3689 /*
3690 * Output.
3691 */
3692 case PDMAUDIOMIXERCTL_FRONT:
3693 pMixStream = pDrv->Front.pMixStrm;
3694 pDrv->Front.pMixStrm = NULL;
3695 break;
3696#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3697 case PDMAUDIOMIXERCTL_CENTER_LFE:
3698 pMixStream = pDrv->CenterLFE.pMixStrm;
3699 pDrv->CenterLFE.pMixStrm = NULL;
3700 break;
3701 case PDMAUDIOMIXERCTL_REAR:
3702 pMixStream = pDrv->Rear.pMixStrm;
3703 pDrv->Rear.pMixStrm = NULL;
3704 break;
3705#endif
3706 default:
3707 AssertMsgFailed(("Mixer control %d not implemented\n", enmMixerCtl));
3708 break;
3709 }
3710
3711 if (pMixStream)
3712 {
3713 AudioMixerSinkRemoveStream(pSink->pMixSink, pMixStream);
3714 AudioMixerStreamDestroy(pMixStream);
3715
3716 pMixStream = NULL;
3717 }
3718 }
3719
3720 AudioMixerSinkRemoveAllStreams(pSink->pMixSink);
3721 rc = VINF_SUCCESS;
3722 }
3723 else
3724 rc = VERR_NOT_FOUND;
3725
3726 LogFlowFunc(("enmMixerCtl=%d, rc=%Rrc\n", enmMixerCtl, rc));
3727 return rc;
3728}
3729
3730/**
3731 * Sets a SDn stream number and channel to a particular mixer control.
3732 *
3733 * @returns IPRT status code.
3734 * @param pThis HDA State.
3735 * @param enmMixerCtl Mixer control to set SD stream number and channel for.
3736 * @param uSD SD stream number (number + 1) to set. Set to 0 for unassign.
3737 * @param uChannel Channel to set. Only valid if a valid SD stream number is specified.
3738 */
3739static DECLCALLBACK(int) hdaMixerSetStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, uint8_t uSD, uint8_t uChannel)
3740{
3741 LogFlowFunc(("enmMixerCtl=%RU32, uSD=%RU8, uChannel=%RU8\n", enmMixerCtl, uSD, uChannel));
3742
3743 if (uSD == 0) /* Stream number 0 is reserved. */
3744 {
3745 LogFlowFunc(("Invalid SDn (%RU8) number for mixer control %d, ignoring\n", uSD, enmMixerCtl));
3746 return VINF_SUCCESS;
3747 }
3748 /* uChannel is optional. */
3749
3750 /* SDn0 starts as 1. */
3751 Assert(uSD);
3752 uSD--;
3753
3754 int rc;
3755
3756 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3757 if (pSink)
3758 {
3759 if ( (uSD < HDA_MAX_SDI)
3760 && AudioMixerSinkGetDir(pSink->pMixSink) == AUDMIXSINKDIR_OUTPUT)
3761 {
3762 uSD += HDA_MAX_SDI;
3763 }
3764
3765 LogFlowFunc(("%s: Setting to stream ID=%RU8, channel=%RU8, enmMixerCtl=%RU32\n",
3766 pSink->pMixSink->pszName, uSD, uChannel, enmMixerCtl));
3767
3768 Assert(uSD < HDA_MAX_STREAMS);
3769
3770 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, uSD);
3771 if (pStream)
3772 {
3773 pSink->uSD = uSD;
3774 pSink->uChannel = uChannel;
3775
3776 /* Make sure that the stream also has this sink set. */
3777 hdaStreamAssignToSink(pStream, pSink);
3778
3779 rc = VINF_SUCCESS;
3780 }
3781 else
3782 {
3783 LogRel(("HDA: Guest wanted to assign invalid stream ID=%RU8 (channel %RU8) to mixer control %RU32, skipping\n",
3784 uSD, uChannel, enmMixerCtl));
3785 rc = VERR_INVALID_PARAMETER;
3786 }
3787 }
3788 else
3789 rc = VERR_NOT_FOUND;
3790
3791 LogFlowFuncLeaveRC(rc);
3792 return rc;
3793}
3794
3795/**
3796 * Sets the volume of a specified mixer control.
3797 *
3798 * @return IPRT status code.
3799 * @param pThis HDA State.
3800 * @param enmMixerCtl Mixer control to set volume for.
3801 * @param pVol Pointer to volume data to set.
3802 */
3803static DECLCALLBACK(int) hdaMixerSetVolume(PHDASTATE pThis,
3804 PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOVOLUME pVol)
3805{
3806 int rc;
3807
3808 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3809 if (pSink)
3810 {
3811 /* Set the volume.
3812 * We assume that the codec already converted it to the correct range. */
3813 rc = AudioMixerSinkSetVolume(pSink->pMixSink, pVol);
3814 }
3815 else
3816 rc = VERR_NOT_FOUND;
3817
3818 LogFlowFuncLeaveRC(rc);
3819 return rc;
3820}
3821
3822#ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
3823/**
3824 * Starts the internal audio device timer (if not started yet).
3825 *
3826 * @param pThis HDA state.
3827 */
3828static void hdaTimerMaybeStart(PHDASTATE pThis)
3829{
3830 LogFlowFuncEnter();
3831
3832 if (!pThis->pTimer)
3833 return;
3834
3835 pThis->cStreamsActive++;
3836
3837 /* Only start the timer at the first active stream. */
3838 if (pThis->cStreamsActive == 1)
3839 {
3840 LogRel2(("HDA: Starting transfers\n"));
3841
3842 /* Set timer flag. */
3843 ASMAtomicXchgBool(&pThis->fTimerActive, true);
3844
3845 /* Update current time timestamp. */
3846 pThis->uTimerTS = TMTimerGet(pThis->pTimer);
3847
3848 /* Start transfers. */
3849 hdaTimerMain(pThis);
3850 }
3851}
3852
3853/**
3854 * Stops the internal audio device timer (if not stopped yet).
3855 *
3856 * @param pThis HDA state.
3857 */
3858static void hdaTimerStop(PHDASTATE pThis)
3859{
3860 LogFlowFuncEnter();
3861
3862 /* Set timer flag. */
3863 ASMAtomicXchgBool(&pThis->fTimerActive, false);
3864}
3865
3866static void hdaTimerMaybeStop(PHDASTATE pThis)
3867{
3868 LogFlowFuncEnter();
3869
3870 if (!pThis->pTimer)
3871 return;
3872
3873 if (pThis->cStreamsActive) /* Disable can be called mupltiple times. */
3874 pThis->cStreamsActive--;
3875
3876 if (pThis->cStreamsActive == 0)
3877 hdaTimerStop(pThis);
3878}
3879
3880/**
3881 * Main routine for the device timer.
3882 *
3883 * @returns IPRT status code.
3884 * @param pThis HDA state.
3885 */
3886static void hdaTimerMain(PHDASTATE pThis)
3887{
3888 AssertPtrReturnVoid(pThis);
3889
3890 STAM_PROFILE_START(&pThis->StatTimer, a);
3891
3892 uint64_t cTicksNow = TMTimerGet(pThis->pTimer);
3893
3894 Log4Func(("Timer enter\n"));
3895
3896 /* Update current time timestamp. */
3897 pThis->uTimerTS = cTicksNow;
3898
3899 /* Flag indicating whether to kick the timer again for a
3900 * new data processing round. */
3901 bool fKickTimer = false;
3902
3903 hdaDoTransfers(pThis);
3904
3905 /* Do we need to kick the timer again? */
3906 if ( AudioMixerSinkIsActive(pThis->SinkFront.pMixSink)
3907#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3908 || AudioMixerSinkIsActive(pThis->SinkCenterLFE.pMixSink)
3909 || AudioMixerSinkIsActive(pThis->SinkRear.pMixSink)
3910#endif
3911 || AudioMixerSinkIsActive(pThis->SinkLineIn.pMixSink)
3912#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3913 || AudioMixerSinkIsActive(pThis->SinkMicIn.pMixSink)
3914#endif
3915 )
3916 {
3917 fKickTimer = true;
3918 }
3919
3920 pThis->uTimerMS = RTTimeMilliTS();
3921
3922 if ( ASMAtomicReadBool(&pThis->fTimerActive)
3923 || fKickTimer)
3924 {
3925 /* Kick the timer again. */
3926 uint64_t cTicks = pThis->cTimerTicks;
3927 /** @todo adjust cTicks down by now much cbOutMin represents. */
3928 TMTimerSet(pThis->pTimer, cTicksNow + cTicks);
3929 }
3930 else
3931 LogRel2(("HDA: Stopping transfers\n"));
3932
3933 STAM_PROFILE_STOP(&pThis->StatTimer, a);
3934}
3935
3936/**
3937 * Timer callback which handles the audio data transfers on a periodic basis.
3938 *
3939 * @param pDevIns Device instance.
3940 * @param pTimer Timer which was used when calling this.
3941 * @param pvUser User argument as PHDASTATE.
3942 */
3943static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3944{
3945 RT_NOREF(pDevIns, pTimer);
3946
3947 PHDASTATE pThis = (PHDASTATE)pvUser;
3948 Assert(pThis == PDMINS_2_DATA(pDevIns, PHDASTATE));
3949 AssertPtr(pThis);
3950
3951 hdaTimerMain(pThis);
3952}
3953
3954#else /* VBOX_WITH_AUDIO_HDA_CALLBACKS */
3955
3956static DECLCALLBACK(int) hdaCallbackInput(PDMAUDIOCBTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
3957{
3958 Assert(enmType == PDMAUDIOCALLBACKTYPE_INPUT);
3959 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
3960 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
3961 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
3962 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
3963
3964 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
3965 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
3966
3967 PPDMAUDIOCBDATA_DATA_INPUT pData = (PPDMAUDIOCBDATA_DATA_INPUT)pvUser;
3968 AssertReturn(cbUser == sizeof(PDMAUDIOCBDATA_DATA_INPUT), VERR_INVALID_PARAMETER);
3969
3970 return hdaStreamDoDMA(pCtx->pThis, PI_INDEX, UINT32_MAX, &pData->cbOutRead);
3971}
3972
3973static DECLCALLBACK(int) hdaCallbackOutput(PDMAUDIOCBTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
3974{
3975 Assert(enmType == PDMAUDIOCALLBACKTYPE_OUTPUT);
3976 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
3977 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
3978 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
3979 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
3980
3981 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
3982 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
3983
3984 PPDMAUDIOCBDATA_DATA_OUTPUT pData = (PPDMAUDIOCBDATA_DATA_OUTPUT)pvUser;
3985 AssertReturn(cbUser == sizeof(PDMAUDIOCBDATA_DATA_OUTPUT), VERR_INVALID_PARAMETER);
3986
3987 PHDASTATE pThis = pCtx->pThis;
3988
3989 int rc = hdaStreamDoDMA(pCtx->pThis, PO_INDEX, UINT32_MAX, &pData->cbOutWritten);
3990 if ( RT_SUCCESS(rc)
3991 && pData->cbOutWritten)
3992 {
3993 PHDADRIVER pDrv;
3994 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3995 {
3996 uint32_t cSamplesPlayed;
3997 int rc2 = pDrv->pConnector->pfnPlay(pDrv->pConnector, &cSamplesPlayed);
3998 LogFlowFunc(("LUN#%RU8: cSamplesPlayed=%RU32, rc=%Rrc\n", pDrv->uLUN, cSamplesPlayed, rc2));
3999 }
4000 }
4001}
4002#endif /* VBOX_WITH_AUDIO_HDA_CALLBACKS */
4003
4004/**
4005 * Main routine to perform the actual audio data transfers from the HDA streams
4006 * to the backend(s) and vice versa.
4007 *
4008 * @param pThis HDA state.
4009 */
4010static void hdaDoTransfers(PHDASTATE pThis)
4011{
4012 PHDASTREAM pStreamLineIn = hdaSinkGetStream(pThis, &pThis->SinkLineIn);
4013#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
4014 PHDASTREAM pStreamMicIn = hdaSinkGetStream(pThis, &pThis->SinkMicIn);
4015#endif
4016 PHDASTREAM pStreamFront = hdaSinkGetStream(pThis, &pThis->SinkFront);
4017#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
4018 /** @todo See note below. */
4019#endif
4020
4021 hdaStreamUpdate(pThis, pStreamLineIn);
4022#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
4023 hdaStreamUpdate(pThis, pStreamMicIn);
4024#endif
4025 hdaStreamUpdate(pThis, pStreamFront);
4026
4027
4028#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
4029 int rc2 = AudioMixerSinkUpdate(pThis->SinkCenterLFE.pMixSink);
4030 AssertRC(rc2);
4031
4032 rc2 = AudioMixerSinkUpdate(pThis->SinkRear.pMixSink);
4033 AssertRC(rc2);
4034 /** @todo Check for stream interleaving and only call hdaStreamDoDMA() if required! */
4035
4036 /*
4037 * Only call hdaTransfer if CenterLFE and/or Rear are on different SDs,
4038 * otherwise we have to use the interleaved streams support for getting the data
4039 * out of the Front sink (depending on the mapping layout).
4040 */
4041#endif
4042}
4043
4044#ifdef DEBUG_andy
4045# define HDA_DEBUG_DMA
4046#endif
4047
4048/**
4049 * Does a single DMA transfer for a specific HDA stream (SDI/SDO).
4050 * This either can be a read or write operation, depending on the HDA stream.
4051 *
4052 * @returns IPRT status code.
4053 * @param pThis HDA state.
4054 * @param pStream HDA stream to do the DMA transfer for.
4055 * @param pvBuf Pointer to buffer data to write data to / read data from.
4056 * @param cbBuf Size of buffer (in bytes).
4057 * @param cbToProcess Size (in bytes) to transfer (read/write).
4058 * @param pcbProcessed Size (in bytes) transferred (read/written). Optional.
4059 */
4060static int hdaStreamDoDMA(PHDASTATE pThis, PHDASTREAM pStream, void *pvBuf, uint32_t cbBuf,
4061 uint32_t cbToProcess, uint32_t *pcbProcessed)
4062{
4063 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
4064 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
4065 AssertPtrReturn(pvBuf, VERR_INVALID_POINTER);
4066 AssertReturn(cbBuf >= cbToProcess, VERR_INVALID_PARAMETER);
4067 /* pcbProcessed is optional. */
4068
4069 if (ASMAtomicReadBool(&pThis->fInReset)) /* HDA controller in reset mode? Bail out. */
4070 {
4071 if (pcbProcessed)
4072 *pcbProcessed = 0;
4073 return VINF_SUCCESS;
4074 }
4075
4076 bool fProceed = true;
4077
4078 Log3Func(("[SD%RU8] %R[sdsts] cbToProcess=%RU32\n",
4079 pStream->u8SD, HDA_STREAM_REG(pThis, STS, pStream->u8SD), cbToProcess));
4080
4081 /* Is the stream not in a running state currently? */
4082 if (!(HDA_STREAM_REG(pThis, CTL, pStream->u8SD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)))
4083 fProceed = false;
4084 /* Is the BCIS (Buffer Completion Interrupt Status) flag set? Then we have to wait and skip. */
4085 else if ((HDA_STREAM_REG(pThis, STS, pStream->u8SD) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
4086 fProceed = false;
4087
4088 if (!fProceed)
4089 {
4090#ifdef HDA_DEBUG_DMA
4091 Log3Func(("[SD%RU8] DMA: Skip\n", pStream->u8SD));
4092#endif
4093 if (pcbProcessed)
4094 *pcbProcessed = 0;
4095 return VINF_SUCCESS;
4096 }
4097
4098 int rc = VINF_SUCCESS;
4099
4100#ifdef HDA_DEBUG_DMA
4101 Log3Func(("[SD%RU8] DMA: Start\n", pStream->u8SD));
4102#endif
4103
4104 /* Sanity checks. */
4105 Assert(pStream->u8SD <= HDA_MAX_STREAMS);
4106 Assert(pStream->u64BDLBase);
4107 Assert(pStream->u32CBL);
4108
4109 /* State sanity checks. */
4110 Assert(pStream->State.fInReset == false);
4111 Assert(HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) <= pStream->u32CBL);
4112
4113 bool fSendInterrupt = false;
4114
4115 /* Only do one FIFO size at a time. */
4116 uint32_t cbLeft = RT_MIN(pStream->u16FIFOS, RT_MIN(cbToProcess, cbBuf));
4117 uint32_t cbTotal = 0;
4118 uint32_t cbChunk = 0;
4119 uint32_t cbChunkProcessed = 0;
4120
4121#ifdef HDA_DEBUG_DMA
4122 LogFunc(("[SD%RU8] DMA: cbToProcess=%RU32, cbLeft=%RU32\n", pStream->u8SD, cbToProcess, cbLeft));
4123#endif
4124
4125 /* Get the maximum number of BDL entries. */
4126 uint16_t cBDLE = pStream->u16LVI + 1;
4127
4128 while ( cbLeft
4129 && cBDLE--)
4130 {
4131 cbChunk = hdaStreamGetTransferSize(pThis, pStream, cbLeft);
4132 cbChunkProcessed = 0;
4133
4134 PHDABDLE pBDLE = &pStream->State.BDLE;
4135
4136 if (cbChunk)
4137 {
4138 if (hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_OUT) /* Output (SDO). */
4139 {
4140 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
4141 pBDLE->Desc.u64BufAdr + pBDLE->State.u32BufOff,
4142 (uint8_t *)pvBuf + cbTotal, cbChunk);
4143 }
4144 else /* Input (SDI). */
4145 {
4146 PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns),
4147 pBDLE->Desc.u64BufAdr + pBDLE->State.u32BufOff,
4148 (uint8_t *)pvBuf + cbTotal, cbChunk);
4149 }
4150
4151#ifdef HDA_DEBUG_DUMP_PCM_DATA
4152 RTFILE fh;
4153 RTFileOpen(&fh,
4154 hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_OUT
4155 ? HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaDMARead.pcm" : HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaDMAWrite.pcm",
4156 RTFILE_O_OPEN_CREATE | RTFILE_O_APPEND | RTFILE_O_WRITE | RTFILE_O_DENY_NONE);
4157 RTFileWrite(fh, (uint8_t *)pvBuf + cbTotal, cbChunk, NULL);
4158 RTFileClose(fh);
4159#endif
4160 }
4161
4162 cbChunkProcessed = cbChunk;
4163
4164 hdaBDLEUpdate(pBDLE, cbChunkProcessed, cbChunkProcessed);
4165
4166 LogFunc(("[SD%RU8] DMA: Entry %RU32 Pos %RU32/%RU32 Chunk %RU32\n",
4167 pStream->u8SD, pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->Desc.u32BufSize, cbChunk));
4168
4169 Assert(cbLeft >= cbChunkProcessed);
4170 cbLeft -= cbChunkProcessed;
4171 cbTotal += cbChunkProcessed;
4172 Assert(cbTotal <= cbToProcess);
4173
4174 hdaStreamTransferUpdate(pThis, pStream, cbChunkProcessed);
4175
4176#ifdef HDA_DEBUG_DMA
4177 LogFunc(("[SD%RU8] DMA: LPIB %RU32 Pos %RU32 Left %RU32\n",
4178 pStream->u8SD, HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), cbTotal, cbLeft));
4179#endif
4180 bool fNeedsInterrupt = false;
4181 bool fBDLEIsComplete = hdaBDLEIsComplete(pBDLE, &fNeedsInterrupt);
4182
4183 if (fNeedsInterrupt)
4184 fSendInterrupt = true;
4185
4186 if (fBDLEIsComplete)
4187 {
4188 /* Do we need to fetch the next Buffer Descriptor Entry (BDLE)? */
4189 if (hdaStreamNeedsNextBDLE(pThis, pStream))
4190 {
4191 bool fWrapAround;
4192 rc = hdaStreamGetNextBDLE(pThis, pStream, &fWrapAround);
4193 if ( RT_SUCCESS(rc)
4194 && fWrapAround)
4195 {
4196 hdaStreamUpdateLPIB(pThis, pStream, 0);
4197 }
4198 }
4199 }
4200
4201 if (RT_FAILURE(rc))
4202 break;
4203 }
4204
4205 Log3Func(("[SD%RU8]: cbLeft=%RU32, rc=%Rrc\n", pStream->u8SD, cbLeft, rc));
4206
4207 if (fSendInterrupt)
4208 {
4209#ifdef HDA_DEBUG_DMA
4210 Log3Func(("[SD%RU8] DMA: Interrupt\n", pStream->u8SD));
4211#endif
4212 /**
4213 * Set the BCIS (Buffer Completion Interrupt Status) flag as the
4214 * last byte of data for the current descriptor has been fetched
4215 * from memory and put into the DMA FIFO.
4216 *
4217 * Speech synthesis works fine on Mac Guest if this bit isn't set
4218 * but in general sound quality gets worse.
4219 *
4220 * This must be set in *any* case.
4221 */
4222 HDA_STREAM_REG(pThis, STS, pStream->u8SD) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
4223 Log3Func(("[SD%RU8]: BCIS set\n", pStream->u8SD));
4224
4225 hdaProcessInterrupt(pThis);
4226 }
4227
4228 if (RT_SUCCESS(rc))
4229 {
4230 if (pcbProcessed)
4231 *pcbProcessed = cbTotal;
4232 }
4233
4234#ifdef HDA_DEBUG_DMA
4235 Log3Func(("[SD%RU8] DMA: End\n", pStream->u8SD));
4236#endif
4237
4238 return rc;
4239}
4240
4241/**
4242 * Writes audio data from a mixer sink into an HDA stream's DMA buffer.
4243 *
4244 * @returns IPRT status code.
4245 * @param pThis HDA state.
4246 * @param pStream HDA stream to write to.
4247 * @param cbToWrite Number of bytes to write.
4248 * @param pcbWritten Number of bytes written. Optional.
4249 */
4250static int hdaStreamWrite(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToWrite, uint32_t *pcbWritten)
4251{
4252 RT_NOREF(pThis);
4253 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
4254 AssertReturn(cbToWrite, VERR_INVALID_PARAMETER);
4255 /* pcbWritten is optional. */
4256
4257 PHDAMIXERSINK pSink = pStream->pMixSink;
4258 if (!pSink)
4259 {
4260 AssertMsgFailed(("[SD%RU8]: Can't write to a stream with no sink attached\n", pStream->u8SD));
4261
4262 if (pcbWritten)
4263 *pcbWritten = 0;
4264 return VINF_SUCCESS;
4265 }
4266
4267 PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
4268 AssertPtr(pCircBuf);
4269
4270 void *pvDst;
4271 size_t cbDst;
4272
4273 uint32_t cbWritten = 0;
4274
4275 RTCircBufAcquireWriteBlock(pCircBuf, cbToWrite, &pvDst, &cbDst);
4276
4277 if (cbDst)
4278 {
4279 int rc2 = AudioMixerSinkRead(pSink->pMixSink, AUDMIXOP_COPY, pvDst, (uint32_t)cbDst, &cbWritten);
4280 AssertRC(rc2);
4281
4282 Assert(cbDst >= cbWritten);
4283 Log2Func(("[SD%RU8]: %zu/%zu bytes written\n", pStream->u8SD, cbWritten, cbDst));
4284
4285#ifdef HDA_DEBUG_DUMP_PCM_DATA
4286 RTFILE fh;
4287 RTFileOpen(&fh, HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaStreamWrite.pcm",
4288 RTFILE_O_OPEN_CREATE | RTFILE_O_APPEND | RTFILE_O_WRITE | RTFILE_O_DENY_NONE);
4289 RTFileWrite(fh, pvDst, cbWritten, NULL);
4290 RTFileClose(fh);
4291#endif
4292 }
4293
4294 RTCircBufReleaseWriteBlock(pCircBuf, cbWritten);
4295
4296 if (pcbWritten)
4297 *pcbWritten = cbWritten;
4298
4299 return VINF_SUCCESS;
4300}
4301
4302/**
4303 * Reads audio data from an HDA stream's DMA buffer and writes into a specified mixer sink.
4304 *
4305 * @returns IPRT status code.
4306 * @param pThis HDA state.
4307 * @param pStream HDA stream to read audio data from.
4308 * @param cbToRead Number of bytes to read.
4309 * @param pcbRead Number of bytes read. Optional.
4310 */
4311static int hdaStreamRead(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToRead, uint32_t *pcbRead)
4312{
4313 RT_NOREF(pThis);
4314 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
4315 AssertReturn(cbToRead, VERR_INVALID_PARAMETER);
4316 /* pcbWritten is optional. */
4317
4318 PHDAMIXERSINK pSink = pStream->pMixSink;
4319 if (!pSink)
4320 {
4321 AssertMsgFailed(("[SD%RU8]: Can't read from a stream with no sink attached\n", pStream->u8SD));
4322
4323 if (pcbRead)
4324 *pcbRead = 0;
4325 return VINF_SUCCESS;
4326 }
4327
4328 PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
4329 AssertPtr(pCircBuf);
4330
4331 void *pvSrc;
4332 size_t cbSrc;
4333
4334 uint32_t cbRead = 0;
4335
4336 RTCircBufAcquireReadBlock(pCircBuf, cbToRead, &pvSrc, &cbSrc);
4337
4338 if (cbSrc)
4339 {
4340 Log2Func(("[SD%RU8]: Reading %zu bytes ...\n", pStream->u8SD, cbSrc));
4341
4342#ifdef HDA_DEBUG_DUMP_PCM_DATA
4343 RTFILE fh;
4344 RTFileOpen(&fh, HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaStreamRead.pcm",
4345 RTFILE_O_OPEN_CREATE | RTFILE_O_APPEND | RTFILE_O_WRITE | RTFILE_O_DENY_NONE);
4346 RTFileWrite(fh, pvSrc, cbSrc, NULL);
4347 RTFileClose(fh);
4348#endif
4349 int rc2 = AudioMixerSinkWrite(pSink->pMixSink, AUDMIXOP_COPY, pvSrc, (uint32_t)cbSrc, &cbRead);
4350 AssertRC(rc2);
4351
4352 Assert(cbSrc >= cbRead);
4353 Log2Func(("[SD%RU8]: %zu/%zu bytes read\n", pStream->u8SD, cbRead, cbSrc));
4354 }
4355
4356 RTCircBufReleaseReadBlock(pCircBuf, cbRead);
4357
4358 if (pcbRead)
4359 *pcbRead = cbRead;
4360
4361 return VINF_SUCCESS;
4362}
4363
4364#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
4365/**
4366 * Asynchronous I/O thread for a HDA stream.
4367 * This will do the heavy lifting work for us as soon as it's getting notified by another thread.
4368 *
4369 * @returns IPRT status code.
4370 * @param hThreadSelf Thread handle.
4371 * @param pvUser User argument. Must be of type PHDASTREAMTHREADCTX.
4372 */
4373static DECLCALLBACK(int) hdaStreamAsyncIOThread(RTTHREAD hThreadSelf, void *pvUser)
4374{
4375 PHDASTREAMTHREADCTX pCtx = (PHDASTREAMTHREADCTX)pvUser;
4376 AssertPtr(pCtx);
4377
4378 PHDASTATE pThis = pCtx->pThis;
4379 AssertPtr(pThis);
4380
4381 PHDASTREAM pStream = pCtx->pStream;
4382 AssertPtr(pStream);
4383
4384 PHDASTREAMSTATEAIO pAIO = &pCtx->pStream->State.AIO;
4385
4386 PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
4387 AssertPtr(pCircBuf);
4388
4389 ASMAtomicXchgBool(&pAIO->fStarted, true);
4390
4391 RTThreadUserSignal(hThreadSelf);
4392
4393 LogFunc(("[SD%RU8]: Started\n", pStream->u8SD));
4394
4395 for (;;)
4396 {
4397 int rc2 = RTSemEventWait(pAIO->Event, RT_INDEFINITE_WAIT);
4398 if (RT_FAILURE(rc2))
4399 break;
4400
4401 if (ASMAtomicReadBool(&pAIO->fShutdown))
4402 break;
4403
4404 PHDAMIXERSINK pSink = pStream->pMixSink;
4405
4406 rc2 = RTCritSectEnter(&pAIO->CritSect);
4407 if (RT_SUCCESS(rc2))
4408 {
4409 uint32_t cbToProcess;
4410 uint32_t cbProcessed = 0;
4411
4412 if (hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_OUT) /* Output (SDO). */
4413 {
4414 cbToProcess = RTCircBufUsed(pCircBuf);
4415 if (cbToProcess)
4416 rc2 = hdaStreamRead(pThis, pStream, cbToProcess, &cbProcessed);
4417 }
4418 else /* Input (SDI). */
4419 {
4420 cbToProcess = RTCircBufFree(pCircBuf);
4421 if (cbToProcess)
4422 rc2 = hdaStreamWrite(pThis, pStream, cbToProcess, &cbProcessed);
4423 }
4424
4425 if ( pSink
4426 && RT_SUCCESS(rc2))
4427 {
4428 rc2 = AudioMixerSinkUpdate(pSink->pMixSink);
4429 }
4430
4431 int rc3 = RTCritSectLeave(&pAIO->CritSect);
4432 AssertRC(rc3);
4433 }
4434
4435 AssertRC(rc2);
4436 }
4437
4438 LogFunc(("[SD%RU8]: Ended\n", pStream->u8SD));
4439
4440 return VINF_SUCCESS;
4441}
4442
4443/**
4444 * Creates the async I/O thread for a specific HDA audio stream.
4445 *
4446 * @returns IPRT status code.
4447 * @param pThis HDA state.
4448 * @param pStream HDA audio stream to create the async I/O thread for.
4449 */
4450static int hdaStreamAsyncIOCreate(PHDASTATE pThis, PHDASTREAM pStream)
4451{
4452 PHDASTREAMSTATEAIO pAIO = &pStream->State.AIO;
4453
4454 int rc;
4455
4456 if (!ASMAtomicReadBool(&pAIO->fStarted))
4457 {
4458 pAIO->fShutdown = false;
4459
4460 rc = RTSemEventCreate(&pAIO->Event);
4461 if (RT_SUCCESS(rc))
4462 {
4463 rc = RTCritSectInit(&pAIO->CritSect);
4464 if (RT_SUCCESS(rc))
4465 {
4466 HDASTREAMTHREADCTX Ctx = { pThis, pStream };
4467
4468 char szThreadName[64];
4469 RTStrPrintf2(szThreadName, sizeof(szThreadName), "hdaAIO%RU8", pStream->u8SD);
4470
4471 rc = RTThreadCreate(&pAIO->Thread, hdaStreamAsyncIOThread, &Ctx,
4472 0, RTTHREADTYPE_IO, RTTHREADFLAGS_WAITABLE, szThreadName);
4473 if (RT_SUCCESS(rc))
4474 rc = RTThreadUserWait(pAIO->Thread, 10 * 1000 /* 10s timeout */);
4475 }
4476 }
4477 }
4478 else
4479 rc = VINF_SUCCESS;
4480
4481 LogFunc(("[SD%RU8]: Returning %Rrc\n", pStream->u8SD, rc));
4482 return rc;
4483}
4484
4485/**
4486 * Destroys the async I/O thread of a specific HDA audio stream.
4487 *
4488 * @returns IPRT status code.
4489 * @param pThis HDA state.
4490 * @param pStream HDA audio stream to destroy the async I/O thread for.
4491 */
4492static int hdaStreamAsyncIODestroy(PHDASTATE pThis, PHDASTREAM pStream)
4493{
4494 PHDASTREAMSTATEAIO pAIO = &pStream->State.AIO;
4495
4496 if (!ASMAtomicReadBool(&pAIO->fStarted))
4497 return VINF_SUCCESS;
4498
4499 ASMAtomicWriteBool(&pAIO->fShutdown, true);
4500
4501 int rc = hdaStreamAsyncIONotify(pThis, pStream);
4502 AssertRC(rc);
4503
4504 int rcThread;
4505 rc = RTThreadWait(pAIO->Thread, 30 * 1000 /* 30s timeout */, &rcThread);
4506 LogFunc(("Async I/O thread ended with %Rrc (%Rrc)\n", rc, rcThread));
4507
4508 if (RT_SUCCESS(rc))
4509 {
4510 rc = RTCritSectDelete(&pAIO->CritSect);
4511 AssertRC(rc);
4512
4513 rc = RTSemEventDestroy(pAIO->Event);
4514 AssertRC(rc);
4515
4516 pAIO->fStarted = false;
4517 pAIO->fShutdown = false;
4518 }
4519
4520 LogFunc(("[SD%RU8]: Returning %Rrc\n", pStream->u8SD, rc));
4521 return rc;
4522}
4523
4524/**
4525 * Lets the stream's async I/O thread know that there is some data to process.
4526 *
4527 * @returns IPRT status code.
4528 * @param pThis HDA state.
4529 * @param pStream HDA stream to notify async I/O thread for.
4530 */
4531static int hdaStreamAsyncIONotify(PHDASTATE pThis, PHDASTREAM pStream)
4532{
4533 RT_NOREF(pThis);
4534 return RTSemEventSignal(pStream->State.AIO.Event);
4535}
4536
4537/**
4538 * Locks the async I/O thread of a specific HDA audio stream.
4539 *
4540 * @param pStream HDA stream to lock async I/O thread for.
4541 */
4542static void hdaStreamAsyncIOLock(PHDASTREAM pStream)
4543{
4544 PHDASTREAMSTATEAIO pAIO = &pStream->State.AIO;
4545
4546 if (!ASMAtomicReadBool(&pAIO->fStarted))
4547 return;
4548
4549 int rc2 = RTCritSectEnter(&pAIO->CritSect);
4550 AssertRC(rc2);
4551}
4552
4553/**
4554 * Unlocks the async I/O thread of a specific HDA audio stream.
4555 *
4556 * @param pStream HDA stream to unlock async I/O thread for.
4557 */
4558static void hdaStreamAsyncIOUnlock(PHDASTREAM pStream)
4559{
4560 PHDASTREAMSTATEAIO pAIO = &pStream->State.AIO;
4561
4562 if (!ASMAtomicReadBool(&pAIO->fStarted))
4563 return;
4564
4565 int rc2 = RTCritSectLeave(&pAIO->CritSect);
4566 AssertRC(rc2);
4567}
4568#endif /* VBOX_WITH_AUDIO_HDA_ASYNC_IO */
4569
4570/**
4571 * Updates a HDA stream according to its usage (input / output).
4572 *
4573 * For an SDO (output) stream this means reading DMA data from the device to
4574 * the connected audio sink(s).
4575 *
4576 * For an SDI (input) stream this is reading audio data from the connected
4577 * audio sink(s) and writing it as DMA data to the device.
4578 *
4579 * @returns IPRT status code.
4580 * @param pThis HDA state.
4581 * @param pStream HDA stream to update.
4582 */
4583static int hdaStreamUpdate(PHDASTATE pThis, PHDASTREAM pStream)
4584{
4585 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
4586 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
4587
4588 PHDAMIXERSINK pSink = pStream->pMixSink;
4589 AssertPtr(pSink);
4590
4591 PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
4592 AssertPtr(pCircBuf);
4593
4594 if (!AudioMixerSinkIsActive(pSink->pMixSink))
4595 return VINF_SUCCESS;
4596
4597 Log2Func(("[SD%RU8]\n", pStream->u8SD));
4598
4599 int rc = VINF_SUCCESS;
4600
4601 bool fDone = false;
4602 uint8_t cTransfers = 0;
4603
4604 while (!fDone)
4605 {
4606 int rc2;
4607 uint32_t cbDMA = 0;
4608
4609 if (hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_OUT) /* Output (SDO). */
4610 {
4611 STAM_PROFILE_START(&pThis->StatOut, a);
4612
4613 /*
4614 * Read from DMA.
4615 */
4616
4617 uint8_t abFIFO[HDA_FIFO_MAX + 1];
4618 size_t offFIFO = 0;
4619
4620 /* Do one DMA transfer with FIFOS size at a time. */
4621 rc2 = hdaStreamDoDMA(pThis, pStream, abFIFO, sizeof(abFIFO), (uint32_t)pStream->u16FIFOS /* cbToProcess */, &cbDMA);
4622 AssertRC(rc2);
4623
4624 uint32_t cbDMALeft = cbDMA;
4625
4626 while ( cbDMALeft
4627 && RTCircBufFree(pCircBuf))
4628 {
4629 void *pvDst;
4630 size_t cbDst;
4631
4632 RTCircBufAcquireWriteBlock(pCircBuf, cbDMALeft, &pvDst, &cbDst);
4633
4634 if (cbDst)
4635 {
4636 memcpy(pvDst, abFIFO + offFIFO, cbDst);
4637
4638 offFIFO += cbDst;
4639 Assert(offFIFO <= sizeof(abFIFO));
4640 }
4641
4642 RTCircBufReleaseWriteBlock(pCircBuf, cbDst);
4643
4644 Assert(cbDst <= cbDMALeft);
4645 cbDMALeft -= (uint32_t)cbDst;
4646 }
4647
4648#ifdef DEBUG_andy
4649 AssertMsg(cbDMALeft == 0, ("%RU32 bytes of DMA data left, CircBuf=%zu/%zu\n",
4650 cbDMALeft, RTCircBufUsed(pCircBuf), RTCircBufSize(pCircBuf)));
4651#endif
4652 /*
4653 * Process backends.
4654 */
4655
4656 uint32_t cbUsed = (uint32_t)RTCircBufUsed(pCircBuf);
4657 if (cbUsed)
4658 {
4659#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
4660 /* Let the asynchronous thread know that there is some new data to process. */
4661 hdaStreamAsyncIONotify(pThis, pStream);
4662#else
4663 /* Read audio data from the HDA stream and write to the backends. */
4664 rc2 = hdaStreamRead(pThis, pStream, cbUsed, NULL /* pcbRead */);
4665 AssertRC(rc2);
4666#endif
4667 }
4668
4669 /* All DMA transfers done for now? */
4670 if ( !cbDMA
4671#ifndef VBOX_WITH_AUDIO_AC97_ASYNC_IO
4672 /* All data read *and* processed for now? */
4673 && RTCircBufUsed(pCircBuf) == 0
4674#endif
4675 )
4676 {
4677 fDone = true;
4678 }
4679
4680#ifndef VBOX_WITH_AUDIO_HDA_ASYNC_IO
4681 rc2 = AudioMixerSinkUpdate(pSink->pMixSink);
4682 AssertRC(rc2);
4683#endif
4684 STAM_PROFILE_STOP(&pThis->StatOut, a);
4685 }
4686 else if (hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN) /* Input (SDI). */
4687 {
4688 STAM_PROFILE_START(&pThis->StatIn, a);
4689
4690 /*
4691 * Process backends.
4692 */
4693
4694#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
4695 /* Let the asynchronous thread know that there is some new data to process. */
4696 hdaStreamAsyncIONotify(pThis, pStream);
4697#else
4698 rc2 = AudioMixerSinkUpdate(pSink->pMixSink);
4699 AssertRC(rc2);
4700
4701 /* Write read data from the backend to the HDA stream. */
4702 rc2 = hdaStreamWrite(pThis, pStream, pStream->u16FIFOS, NULL /* pcbWritten */);
4703 AssertRC(rc2);
4704#endif
4705 /*
4706 * Write to DMA.
4707 */
4708
4709 void *pvSrc;
4710 size_t cbSrc;
4711
4712 RTCircBufAcquireReadBlock(pCircBuf, pStream->u16FIFOS, &pvSrc, &cbSrc);
4713
4714 if (cbSrc)
4715 {
4716 /* Do one DMA transfer with FIFOS size at a time. */
4717 rc2 = hdaStreamDoDMA(pThis, pStream, pvSrc, (uint32_t)cbSrc, (uint32_t)cbSrc /* cbToProcess */, &cbDMA);
4718 AssertRC(rc2);
4719 }
4720
4721 RTCircBufReleaseReadBlock(pCircBuf, cbDMA);
4722
4723 /* All DMA transfers done for now? */
4724 if (!cbDMA)
4725 fDone = true;
4726
4727 STAM_PROFILE_STOP(&pThis->StatIn, a);
4728 }
4729 else
4730 AssertFailed();
4731
4732 if (++cTransfers > 32) /* Failsafe counter. */
4733 fDone = true;
4734
4735 } /* while !fDone */
4736
4737 return rc;
4738}
4739#endif /* IN_RING3 */
4740
4741/* MMIO callbacks */
4742
4743/**
4744 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
4745 *
4746 * @note During implementation, we discovered so-called "forgotten" or "hole"
4747 * registers whose description is not listed in the RPM, datasheet, or
4748 * spec.
4749 */
4750PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
4751{
4752 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4753 int rc;
4754 RT_NOREF_PV(pvUser);
4755
4756 /*
4757 * Look up and log.
4758 */
4759 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
4760 int idxRegDsc = hdaRegLookup(offReg); /* Register descriptor index. */
4761#ifdef LOG_ENABLED
4762 unsigned const cbLog = cb;
4763 uint32_t offRegLog = offReg;
4764#endif
4765
4766 Log3Func(("offReg=%#x cb=%#x\n", offReg, cb));
4767 Assert(cb == 4); Assert((offReg & 3) == 0);
4768
4769 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
4770 LogFunc(("Access to registers except GCTL is blocked while reset\n"));
4771
4772 if (idxRegDsc == -1)
4773 LogRel(("HDA: Invalid read access @0x%x (bytes=%u)\n", offReg, cb));
4774
4775 if (idxRegDsc != -1)
4776 {
4777 /* ASSUMES gapless DWORD at end of map. */
4778 if (g_aHdaRegMap[idxRegDsc].size == 4)
4779 {
4780 /*
4781 * Straight forward DWORD access.
4782 */
4783 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
4784 Log3Func(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
4785 }
4786 else
4787 {
4788 /*
4789 * Multi register read (unless there are trailing gaps).
4790 * ASSUMES that only DWORD reads have sideeffects.
4791 */
4792 uint32_t u32Value = 0;
4793 unsigned cbLeft = 4;
4794 do
4795 {
4796 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
4797 uint32_t u32Tmp = 0;
4798
4799 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
4800 Log3Func(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
4801 if (rc != VINF_SUCCESS)
4802 break;
4803 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
4804
4805 cbLeft -= cbReg;
4806 offReg += cbReg;
4807 idxRegDsc++;
4808 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
4809
4810 if (rc == VINF_SUCCESS)
4811 *(uint32_t *)pv = u32Value;
4812 else
4813 Assert(!IOM_SUCCESS(rc));
4814 }
4815 }
4816 else
4817 {
4818 rc = VINF_IOM_MMIO_UNUSED_FF;
4819 Log3Func(("\tHole at %x is accessed for read\n", offReg));
4820 }
4821
4822 /*
4823 * Log the outcome.
4824 */
4825#ifdef LOG_ENABLED
4826 if (cbLog == 4)
4827 Log3Func(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
4828 else if (cbLog == 2)
4829 Log3Func(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
4830 else if (cbLog == 1)
4831 Log3Func(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
4832#endif
4833 return rc;
4834}
4835
4836
4837DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
4838{
4839 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
4840 {
4841 Log(("hdaWriteReg: Warning: Access to %s is blocked while controller is in reset mode\n", g_aHdaRegMap[idxRegDsc].abbrev));
4842 LogRel2(("HDA: Warning: Access to register %s is blocked while controller is in reset mode\n",
4843 g_aHdaRegMap[idxRegDsc].abbrev));
4844 return VINF_SUCCESS;
4845 }
4846
4847 /*
4848 * Handle RD (register description) flags.
4849 */
4850
4851 /* For SDI / SDO: Check if writes to those registers are allowed while SDCTL's RUN bit is set. */
4852 if (idxRegDsc >= HDA_NUM_GENERAL_REGS)
4853 {
4854 const uint32_t uSDCTL = HDA_STREAM_REG(pThis, CTL, HDA_SD_NUM_FROM_REG(pThis, CTL, idxRegDsc));
4855
4856 /*
4857 * Some OSes (like Win 10 AU) violate the spec by writing stuff to registers which are not supposed to be be touched
4858 * while SDCTL's RUN bit is set. So just ignore those values.
4859 */
4860
4861 /* Is the RUN bit currently set? */
4862 if ( RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
4863 /* Are writes to the register denied if RUN bit is set? */
4864 && !(g_aHdaRegMap[idxRegDsc].fFlags & HDA_RD_FLAG_SD_WRITE_RUN))
4865 {
4866 Log(("hdaWriteReg: Warning: Access to %s is blocked! %R[sdctl]\n", g_aHdaRegMap[idxRegDsc].abbrev, uSDCTL));
4867 LogRel2(("HDA: Warning: Access to register %s is blocked while the stream's RUN bit is set\n",
4868 g_aHdaRegMap[idxRegDsc].abbrev));
4869 return VINF_SUCCESS;
4870 }
4871 }
4872
4873#ifdef LOG_ENABLED
4874 uint32_t const idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4875 uint32_t const u32OldValue = pThis->au32Regs[idxRegMem];
4876#endif
4877 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
4878 Log3Func(("Written value %#x to %s[%d byte]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
4879 g_aHdaRegMap[idxRegDsc].size, u32OldValue, pThis->au32Regs[idxRegMem], pszLog));
4880 RT_NOREF(pszLog);
4881 return rc;
4882}
4883
4884
4885/**
4886 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
4887 */
4888PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
4889{
4890 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4891 int rc;
4892 RT_NOREF_PV(pvUser);
4893
4894 /*
4895 * The behavior of accesses that aren't aligned on natural boundraries is
4896 * undefined. Just reject them outright.
4897 */
4898 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
4899 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
4900 if (GCPhysAddr & (cb - 1))
4901 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
4902
4903 /*
4904 * Look up and log the access.
4905 */
4906 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
4907 int idxRegDsc = hdaRegLookup(offReg);
4908 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
4909 uint64_t u64Value;
4910 if (cb == 4) u64Value = *(uint32_t const *)pv;
4911 else if (cb == 2) u64Value = *(uint16_t const *)pv;
4912 else if (cb == 1) u64Value = *(uint8_t const *)pv;
4913 else if (cb == 8) u64Value = *(uint64_t const *)pv;
4914 else
4915 {
4916 u64Value = 0; /* shut up gcc. */
4917 AssertReleaseMsgFailed(("%u\n", cb));
4918 }
4919
4920#ifdef LOG_ENABLED
4921 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
4922 if (idxRegDsc == -1)
4923 Log3Func(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
4924 else if (cb == 4)
4925 Log3Func(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4926 else if (cb == 2)
4927 Log3Func(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4928 else if (cb == 1)
4929 Log3Func(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4930
4931 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
4932 Log3Func(("\tsize=%RU32 != cb=%u!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
4933#endif
4934
4935 /*
4936 * Try for a direct hit first.
4937 */
4938 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
4939 {
4940 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
4941 Log3Func(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
4942 }
4943 /*
4944 * Partial or multiple register access, loop thru the requested memory.
4945 */
4946 else
4947 {
4948 /*
4949 * If it's an access beyond the start of the register, shift the input
4950 * value and fill in missing bits. Natural alignment rules means we
4951 * will only see 1 or 2 byte accesses of this kind, so no risk of
4952 * shifting out input values.
4953 */
4954 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(offReg)) != -1)
4955 {
4956 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
4957 offReg -= cbBefore;
4958 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4959 u64Value <<= cbBefore * 8;
4960 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
4961 Log3Func(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
4962 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
4963 }
4964
4965 /* Loop thru the write area, it may cover multiple registers. */
4966 rc = VINF_SUCCESS;
4967 for (;;)
4968 {
4969 uint32_t cbReg;
4970 if (idxRegDsc != -1)
4971 {
4972 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4973 cbReg = g_aHdaRegMap[idxRegDsc].size;
4974 if (cb < cbReg)
4975 {
4976 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
4977 Log3Func(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
4978 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
4979 }
4980#ifdef LOG_ENABLED
4981 uint32_t uLogOldVal = pThis->au32Regs[idxRegMem];
4982#endif
4983 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
4984 Log3Func(("\t%#x -> %#x\n", uLogOldVal, pThis->au32Regs[idxRegMem]));
4985 }
4986 else
4987 {
4988 LogRel(("HDA: Invalid write access @0x%x\n", offReg));
4989 cbReg = 1;
4990 }
4991 if (rc != VINF_SUCCESS)
4992 break;
4993 if (cbReg >= cb)
4994 break;
4995
4996 /* Advance. */
4997 offReg += cbReg;
4998 cb -= cbReg;
4999 u64Value >>= cbReg * 8;
5000 if (idxRegDsc == -1)
5001 idxRegDsc = hdaRegLookup(offReg);
5002 else
5003 {
5004 idxRegDsc++;
5005 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
5006 || g_aHdaRegMap[idxRegDsc].offset != offReg)
5007 {
5008 idxRegDsc = -1;
5009 }
5010 }
5011 }
5012 }
5013
5014 return rc;
5015}
5016
5017
5018/* PCI callback. */
5019
5020#ifdef IN_RING3
5021/**
5022 * @callback_method_impl{FNPCIIOREGIONMAP}
5023 */
5024static DECLCALLBACK(int) hdaPciIoRegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5025 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5026{
5027 RT_NOREF(iRegion, enmType);
5028 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
5029
5030 /*
5031 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
5032 *
5033 * Let IOM talk DWORDs when reading, saves a lot of complications. On
5034 * writing though, we have to do it all ourselves because of sideeffects.
5035 */
5036 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
5037 int rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
5038 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_PASSTHRU,
5039 hdaMMIOWrite, hdaMMIORead, "HDA");
5040 if (RT_FAILURE(rc))
5041 return rc;
5042
5043 if (pThis->fR0Enabled)
5044 {
5045 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
5046 "hdaMMIOWrite", "hdaMMIORead");
5047 if (RT_FAILURE(rc))
5048 return rc;
5049 }
5050
5051 if (pThis->fRCEnabled)
5052 {
5053 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
5054 "hdaMMIOWrite", "hdaMMIORead");
5055 if (RT_FAILURE(rc))
5056 return rc;
5057 }
5058
5059 pThis->MMIOBaseAddr = GCPhysAddress;
5060 return VINF_SUCCESS;
5061}
5062
5063
5064/* Saved state callbacks. */
5065
5066static int hdaSaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStrm)
5067{
5068 RT_NOREF(pDevIns);
5069#ifdef DEBUG
5070 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5071#endif
5072 LogFlowFunc(("[SD%RU8]\n", pStrm->u8SD));
5073
5074 /* Save stream ID. */
5075 int rc = SSMR3PutU8(pSSM, pStrm->u8SD);
5076 AssertRCReturn(rc, rc);
5077 Assert(pStrm->u8SD <= HDA_MAX_STREAMS);
5078
5079 rc = SSMR3PutStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE), 0 /*fFlags*/, g_aSSMStreamStateFields6, NULL);
5080 AssertRCReturn(rc, rc);
5081
5082#ifdef DEBUG /* Sanity checks. */
5083 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStrm->u8SD),
5084 HDA_STREAM_REG(pThis, BDPU, pStrm->u8SD));
5085 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStrm->u8SD);
5086 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStrm->u8SD);
5087
5088 hdaBDLEDumpAll(pThis, u64BaseDMA, u16LVI + 1);
5089
5090 Assert(u64BaseDMA == pStrm->u64BDLBase);
5091 Assert(u16LVI == pStrm->u16LVI);
5092 Assert(u32CBL == pStrm->u32CBL);
5093#endif
5094
5095 rc = SSMR3PutStructEx(pSSM, &pStrm->State.BDLE.Desc, sizeof(HDABDLEDESC),
5096 0 /*fFlags*/, g_aSSMBDLEDescFields6, NULL);
5097 AssertRCReturn(rc, rc);
5098
5099 rc = SSMR3PutStructEx(pSSM, &pStrm->State.BDLE.State, sizeof(HDABDLESTATE),
5100 0 /*fFlags*/, g_aSSMBDLEStateFields6, NULL);
5101 AssertRCReturn(rc, rc);
5102
5103#ifdef DEBUG /* Sanity checks. */
5104 PHDABDLE pBDLE = &pStrm->State.BDLE;
5105 if (u64BaseDMA)
5106 {
5107 Assert(pStrm->State.uCurBDLE <= u16LVI + 1);
5108
5109 HDABDLE curBDLE;
5110 rc = hdaBDLEFetch(pThis, &curBDLE, u64BaseDMA, pStrm->State.uCurBDLE);
5111 AssertRC(rc);
5112
5113 Assert(curBDLE.Desc.u32BufSize == pBDLE->Desc.u32BufSize);
5114 Assert(curBDLE.Desc.u64BufAdr == pBDLE->Desc.u64BufAdr);
5115 Assert(curBDLE.Desc.fFlags == pBDLE->Desc.fFlags);
5116 }
5117 else
5118 {
5119 Assert(pBDLE->Desc.u64BufAdr == 0);
5120 Assert(pBDLE->Desc.u32BufSize == 0);
5121 }
5122#endif
5123 return rc;
5124}
5125
5126/**
5127 * @callback_method_impl{FNSSMDEVSAVEEXEC}
5128 */
5129static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5130{
5131 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5132
5133 /* Save Codec nodes states. */
5134 hdaCodecSaveState(pThis->pCodec, pSSM);
5135
5136 /* Save MMIO registers. */
5137 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
5138 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
5139
5140 /* Save number of streams. */
5141 SSMR3PutU32(pSSM, HDA_MAX_STREAMS);
5142
5143 /* Save stream states. */
5144 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5145 {
5146 int rc = hdaSaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
5147 AssertRCReturn(rc, rc);
5148 }
5149
5150 return VINF_SUCCESS;
5151}
5152
5153
5154/**
5155 * @callback_method_impl{FNSSMDEVLOADEXEC}
5156 */
5157static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5158{
5159 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5160
5161 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
5162
5163 LogRel2(("hdaLoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
5164
5165 /*
5166 * Load Codec nodes states.
5167 */
5168 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
5169 if (RT_FAILURE(rc))
5170 {
5171 LogRel(("HDA: Failed loading codec state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
5172 return rc;
5173 }
5174
5175 /*
5176 * Load MMIO registers.
5177 */
5178 uint32_t cRegs;
5179 switch (uVersion)
5180 {
5181 case HDA_SSM_VERSION_1:
5182 /* Starting with r71199, we would save 112 instead of 113
5183 registers due to some code cleanups. This only affected trunk
5184 builds in the 4.1 development period. */
5185 cRegs = 113;
5186 if (SSMR3HandleRevision(pSSM) >= 71199)
5187 {
5188 uint32_t uVer = SSMR3HandleVersion(pSSM);
5189 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
5190 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
5191 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
5192 cRegs = 112;
5193 }
5194 break;
5195
5196 case HDA_SSM_VERSION_2:
5197 case HDA_SSM_VERSION_3:
5198 cRegs = 112;
5199 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= 112);
5200 break;
5201
5202 /* Since version 4 we store the register count to stay flexible. */
5203 case HDA_SSM_VERSION_4:
5204 case HDA_SSM_VERSION_5:
5205 case HDA_SSM_VERSION:
5206 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
5207 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
5208 LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
5209 break;
5210
5211 default:
5212 LogRel(("HDA: Unsupported / too new saved state version (%RU32)\n", uVersion));
5213 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
5214 }
5215
5216 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
5217 {
5218 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
5219 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
5220 }
5221 else
5222 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
5223
5224 /*
5225 * Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
5226 * *every* BDLE state, whereas it only needs to be stored
5227 * *once* for every stream. Most of the BDLE state we can
5228 * get out of the registers anyway, so just ignore those values.
5229 *
5230 * Also, only the current BDLE was saved, regardless whether
5231 * there were more than one (and there are at least two entries,
5232 * according to the spec).
5233 */
5234#define HDA_SSM_LOAD_BDLE_STATE_PRE_V5(v, x) \
5235 { \
5236 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */ \
5237 AssertRCReturn(rc, rc); \
5238 rc = SSMR3GetU64(pSSM, &x.Desc.u64BufAdr); /* u64BdleCviAddr */ \
5239 AssertRCReturn(rc, rc); \
5240 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleMaxCvi */ \
5241 AssertRCReturn(rc, rc); \
5242 rc = SSMR3GetU32(pSSM, &x.State.u32BDLIndex); /* u32BdleCvi */ \
5243 AssertRCReturn(rc, rc); \
5244 rc = SSMR3GetU32(pSSM, &x.Desc.u32BufSize); /* u32BdleCviLen */ \
5245 AssertRCReturn(rc, rc); \
5246 rc = SSMR3GetU32(pSSM, &x.State.u32BufOff); /* u32BdleCviPos */ \
5247 AssertRCReturn(rc, rc); \
5248 bool fIOC; \
5249 rc = SSMR3GetBool(pSSM, &fIOC); /* fBdleCviIoc */ \
5250 AssertRCReturn(rc, rc); \
5251 x.Desc.fFlags = fIOC ? HDA_BDLE_FLAG_IOC : 0; \
5252 rc = SSMR3GetU32(pSSM, &x.State.cbBelowFIFOW); /* cbUnderFifoW */ \
5253 AssertRCReturn(rc, rc); \
5254 rc = SSMR3Skip(pSSM, sizeof(uint8_t) * 256); /* FIFO */ \
5255 AssertRCReturn(rc, rc); \
5256 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */ \
5257 AssertRCReturn(rc, rc); \
5258 } \
5259
5260 /*
5261 * Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
5262 */
5263 switch (uVersion)
5264 {
5265 case HDA_SSM_VERSION_1:
5266 case HDA_SSM_VERSION_2:
5267 case HDA_SSM_VERSION_3:
5268 case HDA_SSM_VERSION_4:
5269 {
5270 /* Only load the internal states.
5271 * The rest will be initialized from the saved registers later. */
5272
5273 /* Note 1: Only the *current* BDLE for a stream was saved! */
5274 /* Note 2: The stream's saving order is/was fixed, so don't touch! */
5275
5276 /* Output */
5277 PHDASTREAM pStream = &pThis->aStreams[4];
5278 rc = hdaStreamInit(pThis, pStream, 4 /* Stream descriptor, hardcoded */);
5279 if (RT_FAILURE(rc))
5280 break;
5281 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
5282 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
5283
5284 /* Microphone-In */
5285 pStream = &pThis->aStreams[2];
5286 rc = hdaStreamInit(pThis, pStream, 2 /* Stream descriptor, hardcoded */);
5287 if (RT_FAILURE(rc))
5288 break;
5289 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
5290 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
5291
5292 /* Line-In */
5293 pStream = &pThis->aStreams[0];
5294 rc = hdaStreamInit(pThis, pStream, 0 /* Stream descriptor, hardcoded */);
5295 if (RT_FAILURE(rc))
5296 break;
5297 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
5298 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
5299 break;
5300 }
5301
5302 /* Since v5 we support flexible stream and BDLE counts. */
5303 case HDA_SSM_VERSION_5:
5304 case HDA_SSM_VERSION:
5305 {
5306 uint32_t cStreams;
5307 rc = SSMR3GetU32(pSSM, &cStreams);
5308 if (RT_FAILURE(rc))
5309 break;
5310
5311 LogRel2(("hdaLoadExec: cStreams=%RU32\n", cStreams));
5312
5313 /* Load stream states. */
5314 for (uint32_t i = 0; i < cStreams; i++)
5315 {
5316 uint8_t uSD;
5317 rc = SSMR3GetU8(pSSM, &uSD);
5318 if (RT_FAILURE(rc))
5319 break;
5320
5321 PHDASTREAM pStrm = hdaStreamGetFromSD(pThis, uSD);
5322 HDASTREAM StreamDummy;
5323
5324 if (!pStrm)
5325 {
5326 RT_ZERO(StreamDummy);
5327 pStrm = &StreamDummy;
5328 LogRel2(("HDA: Warning: Stream ID=%RU32 not supported, skipping to load ...\n", uSD));
5329 break;
5330 }
5331
5332 rc = hdaStreamInit(pThis, pStrm, uSD);
5333 if (RT_FAILURE(rc))
5334 {
5335 LogRel(("HDA: Stream #%RU32: Initialization of stream %RU8 failed, rc=%Rrc\n", i, uSD, rc));
5336 break;
5337 }
5338
5339 if (uVersion == HDA_SSM_VERSION_5)
5340 {
5341 /* Get the current BDLE entry and skip the rest. */
5342 uint16_t cBDLE;
5343
5344 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
5345 AssertRC(rc);
5346 rc = SSMR3GetU16(pSSM, &cBDLE); /* cBDLE */
5347 AssertRC(rc);
5348 rc = SSMR3GetU16(pSSM, &pStrm->State.uCurBDLE); /* uCurBDLE */
5349 AssertRC(rc);
5350 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
5351 AssertRC(rc);
5352
5353 uint32_t u32BDLEIndex;
5354 for (uint16_t a = 0; a < cBDLE; a++)
5355 {
5356 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
5357 AssertRC(rc);
5358 rc = SSMR3GetU32(pSSM, &u32BDLEIndex); /* u32BDLIndex */
5359 AssertRC(rc);
5360
5361 /* Does the current BDLE index match the current BDLE to process? */
5362 if (u32BDLEIndex == pStrm->State.uCurBDLE)
5363 {
5364 rc = SSMR3GetU32(pSSM, &pStrm->State.BDLE.State.cbBelowFIFOW); /* cbBelowFIFOW */
5365 AssertRC(rc);
5366 rc = SSMR3Skip(pSSM, sizeof(uint8_t) * 256); /* FIFO, deprecated */
5367 AssertRC(rc);
5368 rc = SSMR3GetU32(pSSM, &pStrm->State.BDLE.State.u32BufOff); /* u32BufOff */
5369 AssertRC(rc);
5370 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
5371 AssertRC(rc);
5372 }
5373 else /* Skip not current BDLEs. */
5374 {
5375 rc = SSMR3Skip(pSSM, sizeof(uint32_t) /* cbBelowFIFOW */
5376 + sizeof(uint8_t) * 256 /* FIFO, deprecated */
5377 + sizeof(uint32_t) /* u32BufOff */
5378 + sizeof(uint32_t)); /* End marker */
5379 AssertRC(rc);
5380 }
5381 }
5382 }
5383 else
5384 {
5385 rc = SSMR3GetStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE),
5386 0 /* fFlags */, g_aSSMStreamStateFields6, NULL);
5387 if (RT_FAILURE(rc))
5388 break;
5389
5390 rc = SSMR3GetStructEx(pSSM, &pStrm->State.BDLE.Desc, sizeof(HDABDLEDESC),
5391 0 /* fFlags */, g_aSSMBDLEDescFields6, NULL);
5392 if (RT_FAILURE(rc))
5393 break;
5394
5395 rc = SSMR3GetStructEx(pSSM, &pStrm->State.BDLE.State, sizeof(HDABDLESTATE),
5396 0 /* fFlags */, g_aSSMBDLEStateFields6, NULL);
5397 if (RT_FAILURE(rc))
5398 break;
5399 }
5400 }
5401 break;
5402 }
5403
5404 default:
5405 AssertReleaseFailed(); /* Never reached. */
5406 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
5407 }
5408
5409#undef HDA_SSM_LOAD_BDLE_STATE_PRE_V5
5410
5411 if (RT_SUCCESS(rc))
5412 {
5413 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
5414 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
5415 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
5416
5417 /* Also make sure to update the DMA position bit if this was enabled when saving the state. */
5418 pThis->fDMAPosition = RT_BOOL(pThis->u64DPBase & RT_BIT_64(0));
5419 }
5420
5421 if (RT_SUCCESS(rc))
5422 {
5423 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5424 {
5425 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, i);
5426 if (pStream)
5427 {
5428 hdaStreamEnable(pThis, pStream, false /* fEnable */);
5429
5430 bool fActive = RT_BOOL(HDA_STREAM_REG(pThis, CTL, i) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
5431 if (fActive)
5432 {
5433 int rc2 = hdaStreamEnable(pThis, pStream, true /* fEnable */);
5434 AssertRC(rc2);
5435 }
5436 }
5437 }
5438 }
5439
5440 if (RT_FAILURE(rc))
5441 LogRel(("HDA: Failed loading device state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
5442
5443 LogFlowFuncLeaveRC(rc);
5444 return rc;
5445}
5446
5447#ifdef DEBUG
5448/* Debug and log type formatters. */
5449
5450/**
5451 * @callback_method_impl{FNRTSTRFORMATTYPE}
5452 */
5453static DECLCALLBACK(size_t) hdaDbgFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5454 const char *pszType, void const *pvValue,
5455 int cchWidth, int cchPrecision, unsigned fFlags,
5456 void *pvUser)
5457{
5458 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5459 PHDABDLE pBDLE = (PHDABDLE)pvValue;
5460 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5461 "BDLE(idx:%RU32, off:%RU32, fifow:%RU32, IOC:%RTbool, DMA[%RU32 bytes @ 0x%x])",
5462 pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW,
5463 pBDLE->Desc.fFlags & HDA_BDLE_FLAG_IOC, pBDLE->Desc.u32BufSize, pBDLE->Desc.u64BufAdr);
5464}
5465
5466/**
5467 * @callback_method_impl{FNRTSTRFORMATTYPE}
5468 */
5469static DECLCALLBACK(size_t) hdaDbgFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5470 const char *pszType, void const *pvValue,
5471 int cchWidth, int cchPrecision, unsigned fFlags,
5472 void *pvUser)
5473{
5474 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5475 uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
5476 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5477 "SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
5478 uSDCTL,
5479 (uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)) ? "OUT" : "IN",
5480 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
5481 (uSDCTL & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
5482 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
5483 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, FEIE)),
5484 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
5485 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
5486 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
5487}
5488
5489/**
5490 * @callback_method_impl{FNRTSTRFORMATTYPE}
5491 */
5492static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5493 const char *pszType, void const *pvValue,
5494 int cchWidth, int cchPrecision, unsigned fFlags,
5495 void *pvUser)
5496{
5497 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5498 uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
5499 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, uSDFIFOS ? uSDFIFOS + 1 : 0);
5500}
5501
5502/**
5503 * @callback_method_impl{FNRTSTRFORMATTYPE}
5504 */
5505static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5506 const char *pszType, void const *pvValue,
5507 int cchWidth, int cchPrecision, unsigned fFlags,
5508 void *pvUser)
5509{
5510 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5511 uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
5512 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
5513}
5514
5515/**
5516 * @callback_method_impl{FNRTSTRFORMATTYPE}
5517 */
5518static DECLCALLBACK(size_t) hdaDbgFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5519 const char *pszType, void const *pvValue,
5520 int cchWidth, int cchPrecision, unsigned fFlags,
5521 void *pvUser)
5522{
5523 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5524 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
5525 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5526 "SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
5527 uSdSts,
5528 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
5529 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
5530 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
5531 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
5532}
5533
5534static int hdaDbgLookupRegByName(const char *pszArgs)
5535{
5536 int iReg = 0;
5537 for (; iReg < HDA_NUM_REGS; ++iReg)
5538 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
5539 return iReg;
5540 return -1;
5541}
5542
5543
5544static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
5545{
5546 Assert( pThis
5547 && iHdaIndex >= 0
5548 && iHdaIndex < HDA_NUM_REGS);
5549 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
5550}
5551
5552/**
5553 * @callback_method_impl{FNDBGFHANDLERDEV}
5554 */
5555static DECLCALLBACK(void) hdaDbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5556{
5557 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5558 int iHdaRegisterIndex = hdaDbgLookupRegByName(pszArgs);
5559 if (iHdaRegisterIndex != -1)
5560 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
5561 else
5562 {
5563 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NUM_REGS; ++iHdaRegisterIndex)
5564 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
5565 }
5566}
5567
5568static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
5569{
5570 Assert( pThis
5571 && iIdx >= 0
5572 && iIdx < HDA_MAX_STREAMS);
5573
5574 const PHDASTREAM pStrm = &pThis->aStreams[iIdx];
5575
5576 pHlp->pfnPrintf(pHlp, "Stream #%d:\n", iIdx);
5577 pHlp->pfnPrintf(pHlp, "\tSD%dCTL : %R[sdctl]\n", iIdx, HDA_STREAM_REG(pThis, CTL, iIdx));
5578 pHlp->pfnPrintf(pHlp, "\tSD%dCTS : %R[sdsts]\n", iIdx, HDA_STREAM_REG(pThis, STS, iIdx));
5579 pHlp->pfnPrintf(pHlp, "\tSD%dFIFOS: %R[sdfifos]\n", iIdx, HDA_STREAM_REG(pThis, FIFOS, iIdx));
5580 pHlp->pfnPrintf(pHlp, "\tSD%dFIFOW: %R[sdfifow]\n", iIdx, HDA_STREAM_REG(pThis, FIFOW, iIdx));
5581 pHlp->pfnPrintf(pHlp, "\tBDLE : %R[bdle]\n", &pStrm->State.BDLE);
5582}
5583
5584static void hdaDbgPrintBDLE(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
5585{
5586 Assert( pThis
5587 && iIdx >= 0
5588 && iIdx < HDA_MAX_STREAMS);
5589
5590 const PHDASTREAM pStrm = &pThis->aStreams[iIdx];
5591 const PHDABDLE pBDLE = &pStrm->State.BDLE;
5592
5593 pHlp->pfnPrintf(pHlp, "Stream #%d BDLE:\n", iIdx);
5594
5595 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, iIdx),
5596 HDA_STREAM_REG(pThis, BDPU, iIdx));
5597 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, iIdx);
5598 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, iIdx);
5599
5600 if (!u64BaseDMA)
5601 return;
5602
5603 pHlp->pfnPrintf(pHlp, "\tCurrent: %R[bdle]\n\n", pBDLE);
5604
5605 pHlp->pfnPrintf(pHlp, "\tMemory:\n");
5606
5607 uint32_t cbBDLE = 0;
5608 for (uint16_t i = 0; i < u16LVI + 1; i++)
5609 {
5610 HDABDLEDESC bd;
5611 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i * sizeof(HDABDLEDESC), &bd, sizeof(bd));
5612
5613 pHlp->pfnPrintf(pHlp, "\t\t%s #%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
5614 pBDLE->State.u32BDLIndex == i ? "*" : " ", i, bd.u64BufAdr, bd.u32BufSize, bd.fFlags & HDA_BDLE_FLAG_IOC);
5615
5616 cbBDLE += bd.u32BufSize;
5617 }
5618
5619 pHlp->pfnPrintf(pHlp, "Total: %RU32 bytes\n", cbBDLE);
5620
5621 if (cbBDLE != u32CBL)
5622 pHlp->pfnPrintf(pHlp, "Warning: %RU32 bytes does not match CBL (%RU32)!\n", cbBDLE, u32CBL);
5623
5624 pHlp->pfnPrintf(pHlp, "DMA counters (base @ 0x%llx):\n", u64BaseDMA);
5625 if (!u64BaseDMA) /* No DMA base given? Bail out. */
5626 {
5627 pHlp->pfnPrintf(pHlp, "\tNo counters found\n");
5628 return;
5629 }
5630
5631 for (int i = 0; i < u16LVI + 1; i++)
5632 {
5633 uint32_t uDMACnt;
5634 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
5635 &uDMACnt, sizeof(uDMACnt));
5636
5637 pHlp->pfnPrintf(pHlp, "\t#%03d DMA @ 0x%x\n", i , uDMACnt);
5638 }
5639}
5640
5641static int hdaDbgLookupStrmIdx(PHDASTATE pThis, const char *pszArgs)
5642{
5643 RT_NOREF(pThis, pszArgs);
5644 /** @todo Add args parsing. */
5645 return -1;
5646}
5647
5648/**
5649 * @callback_method_impl{FNDBGFHANDLERDEV}
5650 */
5651static DECLCALLBACK(void) hdaDbgInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5652{
5653 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5654 int iHdaStreamdex = hdaDbgLookupStrmIdx(pThis, pszArgs);
5655 if (iHdaStreamdex != -1)
5656 hdaDbgPrintStream(pThis, pHlp, iHdaStreamdex);
5657 else
5658 for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
5659 hdaDbgPrintStream(pThis, pHlp, iHdaStreamdex);
5660}
5661
5662/**
5663 * @callback_method_impl{FNDBGFHANDLERDEV}
5664 */
5665static DECLCALLBACK(void) hdaDbgInfoBDLE(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5666{
5667 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5668 int iHdaStreamdex = hdaDbgLookupStrmIdx(pThis, pszArgs);
5669 if (iHdaStreamdex != -1)
5670 hdaDbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
5671 else
5672 for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
5673 hdaDbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
5674}
5675
5676/**
5677 * @callback_method_impl{FNDBGFHANDLERDEV}
5678 */
5679static DECLCALLBACK(void) hdaDbgInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5680{
5681 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5682
5683 if (pThis->pCodec->pfnDbgListNodes)
5684 pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
5685 else
5686 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
5687}
5688
5689/**
5690 * @callback_method_impl{FNDBGFHANDLERDEV}
5691 */
5692static DECLCALLBACK(void) hdaDbgInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5693{
5694 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5695
5696 if (pThis->pCodec->pfnDbgSelector)
5697 pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
5698 else
5699 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
5700}
5701
5702/**
5703 * @callback_method_impl{FNDBGFHANDLERDEV}
5704 */
5705static DECLCALLBACK(void) hdaDbgInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5706{
5707 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5708
5709 if (pThis->pMixer)
5710 AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
5711 else
5712 pHlp->pfnPrintf(pHlp, "Mixer not available\n");
5713}
5714#endif /* DEBUG */
5715
5716/* PDMIBASE */
5717
5718/**
5719 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
5720 */
5721static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
5722{
5723 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
5724 Assert(&pThis->IBase == pInterface);
5725
5726 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
5727 return NULL;
5728}
5729
5730
5731/* PDMDEVREG */
5732
5733/**
5734 * Reset notification.
5735 *
5736 * @returns VBox status code.
5737 * @param pDevIns The device instance data.
5738 *
5739 * @remark The original sources didn't install a reset handler, but it seems to
5740 * make sense to me so we'll do it.
5741 */
5742static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
5743{
5744 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5745
5746 LogFlowFuncEnter();
5747
5748# ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
5749 /*
5750 * Stop the timer, if any.
5751 */
5752 hdaTimerStop(pThis);
5753
5754 pThis->cStreamsActive = 0;
5755# endif
5756
5757 /* See 6.2.1. */
5758 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(HDA_MAX_SDO /* Ouput streams */,
5759 HDA_MAX_SDI /* Input streams */,
5760 0 /* Bidirectional output streams */,
5761 0 /* Serial data out signals */,
5762 1 /* 64-bit */);
5763 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
5764 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
5765 /* Announce the full 60 words output payload. */
5766 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
5767 /* Announce the full 29 words input payload. */
5768 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
5769 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
5770 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
5771 HDA_REG(pThis, CORBRP) = 0x0;
5772 HDA_REG(pThis, RIRBWP) = 0x0;
5773
5774 /*
5775 * Stop any audio currently playing and/or recording.
5776 */
5777 if (pThis->SinkFront.pMixSink)
5778 AudioMixerSinkReset(pThis->SinkFront.pMixSink);
5779# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5780 if (pThis->SinkMicIn.pMixSink)
5781 AudioMixerSinkReset(pThis->SinkMicIn.pMixSink);
5782# endif
5783 if (pThis->SinkLineIn.pMixSink)
5784 AudioMixerSinkReset(pThis->SinkLineIn.pMixSink);
5785# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
5786 if (pThis->SinkCenterLFE.pMixSink)
5787 AudioMixerSinkReset(pThis->SinkCenterLFE.pMixSink);
5788 if (pThis->SinkRear.pMixSink)
5789 AudioMixerSinkReset(pThis->SinkRear.pMixSink);
5790# endif
5791
5792 /*
5793 * Reset the codec.
5794 */
5795 if ( pThis->pCodec
5796 && pThis->pCodec->pfnReset)
5797 {
5798 pThis->pCodec->pfnReset(pThis->pCodec);
5799 }
5800
5801 /*
5802 * Set some sensible defaults for which HDA sinks
5803 * are connected to which stream number.
5804 *
5805 * We use SD0 for input and SD4 for output by default.
5806 * These stream numbers can be changed by the guest dynamically lateron.
5807 */
5808#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5809 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_MIC_IN , 1 /* SD0 */, 0 /* Channel */);
5810#endif
5811 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_LINE_IN , 1 /* SD0 */, 0 /* Channel */);
5812
5813 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_FRONT , 5 /* SD4 */, 0 /* Channel */);
5814#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
5815 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_CENTER_LFE, 5 /* SD4 */, 0 /* Channel */);
5816 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_REAR , 5 /* SD4 */, 0 /* Channel */);
5817#endif
5818
5819 pThis->cbCorbBuf = 256 * sizeof(uint32_t); /** @todo Use a define here. */
5820
5821 if (pThis->pu32CorbBuf)
5822 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
5823 else
5824 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
5825
5826 pThis->cbRirbBuf = 256 * sizeof(uint64_t); /** @todo Use a define here. */
5827 if (pThis->pu64RirbBuf)
5828 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
5829 else
5830 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
5831
5832 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
5833
5834 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5835 {
5836 /* Remove the RUN bit from SDnCTL in case the stream was in a running state before. */
5837 HDA_STREAM_REG(pThis, CTL, i) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN);
5838 hdaStreamReset(pThis, &pThis->aStreams[i]);
5839 }
5840
5841 /* Clear stream tags <-> objects mapping table. */
5842 RT_ZERO(pThis->aTags);
5843
5844 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
5845 HDA_REG(pThis, STATESTS) = 0x1;
5846
5847 LogFlowFuncLeave();
5848 LogRel(("HDA: Reset\n"));
5849}
5850
5851/**
5852 * @interface_method_impl{PDMDEVREG,pfnDestruct}
5853 */
5854static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
5855{
5856 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5857
5858 PHDADRIVER pDrv;
5859 while (!RTListIsEmpty(&pThis->lstDrv))
5860 {
5861 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
5862
5863 RTListNodeRemove(&pDrv->Node);
5864 RTMemFree(pDrv);
5865 }
5866
5867 if (pThis->pCodec)
5868 {
5869 hdaCodecDestruct(pThis->pCodec);
5870
5871 RTMemFree(pThis->pCodec);
5872 pThis->pCodec = NULL;
5873 }
5874
5875 RTMemFree(pThis->pu32CorbBuf);
5876 pThis->pu32CorbBuf = NULL;
5877
5878 RTMemFree(pThis->pu64RirbBuf);
5879 pThis->pu64RirbBuf = NULL;
5880
5881 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5882 hdaStreamDestroy(pThis, &pThis->aStreams[i]);
5883
5884 return VINF_SUCCESS;
5885}
5886
5887
5888/**
5889 * Attach command, internal version.
5890 *
5891 * This is called to let the device attach to a driver for a specified LUN
5892 * during runtime. This is not called during VM construction, the device
5893 * constructor has to attach to all the available drivers.
5894 *
5895 * @returns VBox status code.
5896 * @param pDevIns The device instance.
5897 * @param pDrv Driver to (re-)use for (re-)attaching to.
5898 * If NULL is specified, a new driver will be created and appended
5899 * to the driver list.
5900 * @param uLUN The logical unit which is being detached.
5901 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5902 */
5903static int hdaAttachInternal(PPDMDEVINS pDevIns, PHDADRIVER pDrv, unsigned uLUN, uint32_t fFlags)
5904{
5905 RT_NOREF(fFlags);
5906 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5907
5908 /*
5909 * Attach driver.
5910 */
5911 char *pszDesc = NULL;
5912 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
5913 AssertReleaseMsgReturn(pszDesc,
5914 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
5915 VERR_NO_MEMORY);
5916
5917 PPDMIBASE pDrvBase;
5918 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
5919 &pThis->IBase, &pDrvBase, pszDesc);
5920 if (RT_SUCCESS(rc))
5921 {
5922 if (pDrv == NULL)
5923 pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
5924 if (pDrv)
5925 {
5926 pDrv->pDrvBase = pDrvBase;
5927 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
5928 AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
5929 pDrv->pHDAState = pThis;
5930 pDrv->uLUN = uLUN;
5931
5932 /*
5933 * For now we always set the driver at LUN 0 as our primary
5934 * host backend. This might change in the future.
5935 */
5936 if (pDrv->uLUN == 0)
5937 pDrv->Flags |= PDMAUDIODRVFLAGS_PRIMARY;
5938
5939 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
5940
5941 /* Attach to driver list if not attached yet. */
5942 if (!pDrv->fAttached)
5943 {
5944 RTListAppend(&pThis->lstDrv, &pDrv->Node);
5945 pDrv->fAttached = true;
5946 }
5947 }
5948 else
5949 rc = VERR_NO_MEMORY;
5950 }
5951 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5952 LogFunc(("No attached driver for LUN #%u\n", uLUN));
5953
5954 if (RT_FAILURE(rc))
5955 {
5956 /* Only free this string on failure;
5957 * must remain valid for the live of the driver instance. */
5958 RTStrFree(pszDesc);
5959 }
5960
5961 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
5962 return rc;
5963}
5964
5965/**
5966 * Attach command.
5967 *
5968 * This is called to let the device attach to a driver for a specified LUN
5969 * during runtime. This is not called during VM construction, the device
5970 * constructor has to attach to all the available drivers.
5971 *
5972 * @returns VBox status code.
5973 * @param pDevIns The device instance.
5974 * @param uLUN The logical unit which is being detached.
5975 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5976 */
5977static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
5978{
5979 return hdaAttachInternal(pDevIns, NULL /* pDrv */, uLUN, fFlags);
5980}
5981
5982static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
5983{
5984 RT_NOREF(pDevIns, uLUN, fFlags);
5985 LogFunc(("iLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
5986}
5987
5988/**
5989 * Powers off the device.
5990 *
5991 * @param pDevIns Device instance to power off.
5992 */
5993static DECLCALLBACK(void) hdaPowerOff(PPDMDEVINS pDevIns)
5994{
5995 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5996
5997 LogRel2(("HDA: Powering off ...\n"));
5998
5999 /* Ditto goes for the codec, which in turn uses the mixer. */
6000 hdaCodecPowerOff(pThis->pCodec);
6001
6002 /**
6003 * Note: Destroy the mixer while powering off and *not* in hdaDestruct,
6004 * giving the mixer the chance to release any references held to
6005 * PDM audio streams it maintains.
6006 */
6007 if (pThis->pMixer)
6008 {
6009 AudioMixerDestroy(pThis->pMixer);
6010 pThis->pMixer = NULL;
6011 }
6012}
6013
6014/**
6015 * Re-attaches a new driver to the device's driver chain.
6016 *
6017 * @returns VBox status code.
6018 * @param pThis Device instance to re-attach driver to.
6019 * @param pDrv Driver instance used for attaching to.
6020 * If NULL is specified, a new driver will be created and appended
6021 * to the driver list.
6022 * @param uLUN The logical unit which is being re-detached.
6023 * @param pszDriver Driver name.
6024 */
6025static int hdaReattach(PHDASTATE pThis, PHDADRIVER pDrv, uint8_t uLUN, const char *pszDriver)
6026{
6027 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
6028 AssertPtrReturn(pszDriver, VERR_INVALID_POINTER);
6029
6030 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
6031 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
6032 PCFGMNODE pDev0 = CFGMR3GetChild(pRoot, "Devices/hda/0/");
6033
6034 /* Remove LUN branch. */
6035 CFGMR3RemoveNode(CFGMR3GetChildF(pDev0, "LUN#%u/", uLUN));
6036
6037 if (pDrv)
6038 {
6039 /* Re-use a driver instance => detach the driver before. */
6040 int rc = PDMDevHlpDriverDetach(pThis->pDevInsR3, PDMIBASE_2_PDMDRV(pDrv->pDrvBase), 0 /* fFlags */);
6041 if (RT_FAILURE(rc))
6042 return rc;
6043 }
6044
6045#define RC_CHECK() if (RT_FAILURE(rc)) { AssertReleaseRC(rc); break; }
6046
6047 int rc = VINF_SUCCESS;
6048 do
6049 {
6050 PCFGMNODE pLunL0;
6051 rc = CFGMR3InsertNodeF(pDev0, &pLunL0, "LUN#%u/", uLUN); RC_CHECK();
6052 rc = CFGMR3InsertString(pLunL0, "Driver", "AUDIO"); RC_CHECK();
6053 rc = CFGMR3InsertNode(pLunL0, "Config/", NULL); RC_CHECK();
6054
6055 PCFGMNODE pLunL1, pLunL2;
6056 rc = CFGMR3InsertNode (pLunL0, "AttachedDriver/", &pLunL1); RC_CHECK();
6057 rc = CFGMR3InsertNode (pLunL1, "Config/", &pLunL2); RC_CHECK();
6058 rc = CFGMR3InsertString(pLunL1, "Driver", pszDriver); RC_CHECK();
6059
6060 rc = CFGMR3InsertString(pLunL2, "AudioDriver", pszDriver); RC_CHECK();
6061
6062 } while (0);
6063
6064 if (RT_SUCCESS(rc))
6065 rc = hdaAttachInternal(pThis->pDevInsR3, pDrv, uLUN, 0 /* fFlags */);
6066
6067 LogFunc(("pThis=%p, uLUN=%u, pszDriver=%s, rc=%Rrc\n", pThis, uLUN, pszDriver, rc));
6068
6069#undef RC_CHECK
6070
6071 return rc;
6072}
6073
6074/**
6075 * @interface_method_impl{PDMDEVREG,pfnConstruct}
6076 */
6077static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
6078{
6079 RT_NOREF(iInstance);
6080 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
6081 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
6082 Assert(iInstance == 0);
6083
6084 /*
6085 * Validations.
6086 */
6087 if (!CFGMR3AreValuesValid(pCfg, "R0Enabled\0"
6088 "RCEnabled\0"
6089 "TimerHz\0"))
6090 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
6091 N_ ("Invalid configuration for the Intel HDA device"));
6092
6093 int rc = CFGMR3QueryBoolDef(pCfg, "RCEnabled", &pThis->fRCEnabled, false);
6094 if (RT_FAILURE(rc))
6095 return PDMDEV_SET_ERROR(pDevIns, rc,
6096 N_("HDA configuration error: failed to read RCEnabled as boolean"));
6097 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, false);
6098 if (RT_FAILURE(rc))
6099 return PDMDEV_SET_ERROR(pDevIns, rc,
6100 N_("HDA configuration error: failed to read R0Enabled as boolean"));
6101#ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
6102 uint16_t uTimerHz;
6103 rc = CFGMR3QueryU16Def(pCfg, "TimerHz", &uTimerHz, HDA_TIMER_HZ /* Default value, if not set. */);
6104 if (RT_FAILURE(rc))
6105 return PDMDEV_SET_ERROR(pDevIns, rc,
6106 N_("HDA configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
6107#endif
6108
6109 /*
6110 * Initialize data (most of it anyway).
6111 */
6112 pThis->pDevInsR3 = pDevIns;
6113 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
6114 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
6115 /* IBase */
6116 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
6117
6118 /* PCI Device */
6119 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
6120 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
6121
6122 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
6123 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
6124 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
6125 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
6126 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
6127 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
6128 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
6129 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
6130 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
6131 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
6132 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
6133
6134#if defined(HDA_AS_PCI_EXPRESS)
6135 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
6136#elif defined(VBOX_WITH_MSI_DEVICES)
6137 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
6138#else
6139 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
6140#endif
6141
6142 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
6143 /// of these values needs to be properly documented!
6144 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
6145 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
6146
6147 /* Power Management */
6148 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
6149 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
6150 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
6151
6152#ifdef HDA_AS_PCI_EXPRESS
6153 /* PCI Express */
6154 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
6155 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
6156 /* Device flags */
6157 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
6158 /* version */ 0x1 |
6159 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
6160 /* MSI */ (100) << 9 );
6161 /* Device capabilities */
6162 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
6163 /* Device control */
6164 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
6165 /* Device status */
6166 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
6167 /* Link caps */
6168 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
6169 /* Link control */
6170 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
6171 /* Link status */
6172 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
6173 /* Slot capabilities */
6174 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
6175 /* Slot control */
6176 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
6177 /* Slot status */
6178 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
6179 /* Root control */
6180 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
6181 /* Root capabilities */
6182 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
6183 /* Root status */
6184 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
6185 /* Device capabilities 2 */
6186 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
6187 /* Device control 2 */
6188 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
6189 /* Link control 2 */
6190 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
6191 /* Slot control 2 */
6192 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
6193#endif
6194
6195 /*
6196 * Register the PCI device.
6197 */
6198 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
6199 if (RT_FAILURE(rc))
6200 return rc;
6201
6202 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
6203 if (RT_FAILURE(rc))
6204 return rc;
6205
6206#ifdef VBOX_WITH_MSI_DEVICES
6207 PDMMSIREG MsiReg;
6208 RT_ZERO(MsiReg);
6209 MsiReg.cMsiVectors = 1;
6210 MsiReg.iMsiCapOffset = 0x60;
6211 MsiReg.iMsiNextOffset = 0x50;
6212 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
6213 if (RT_FAILURE(rc))
6214 {
6215 /* That's OK, we can work without MSI */
6216 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
6217 }
6218#endif
6219
6220 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
6221 if (RT_FAILURE(rc))
6222 return rc;
6223
6224 RTListInit(&pThis->lstDrv);
6225
6226#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
6227 LogRel(("HDA: Asynchronous I/O enabled\n"));
6228#endif
6229
6230 uint8_t uLUN;
6231 for (uLUN = 0; uLUN < UINT8_MAX; ++uLUN)
6232 {
6233 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
6234 rc = hdaAttachInternal(pDevIns, NULL /* pDrv */, uLUN, 0 /* fFlags */);
6235 if (RT_FAILURE(rc))
6236 {
6237 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
6238 rc = VINF_SUCCESS;
6239 else if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
6240 {
6241 hdaReattach(pThis, NULL /* pDrv */, uLUN, "NullAudio");
6242 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
6243 N_("Host audio backend initialization has failed. Selecting the NULL audio backend "
6244 "with the consequence that no sound is audible"));
6245 /* Attaching to the NULL audio backend will never fail. */
6246 rc = VINF_SUCCESS;
6247 }
6248 break;
6249 }
6250 }
6251
6252 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
6253
6254 if (RT_SUCCESS(rc))
6255 {
6256 rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
6257 if (RT_SUCCESS(rc))
6258 {
6259 /*
6260 * Add mixer output sinks.
6261 */
6262#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
6263 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Front",
6264 AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
6265 AssertRC(rc);
6266 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Center / Subwoofer",
6267 AUDMIXSINKDIR_OUTPUT, &pThis->SinkCenterLFE.pMixSink);
6268 AssertRC(rc);
6269 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Rear",
6270 AUDMIXSINKDIR_OUTPUT, &pThis->SinkRear.pMixSink);
6271 AssertRC(rc);
6272#else
6273 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] PCM Output",
6274 AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
6275 AssertRC(rc);
6276#endif
6277 /*
6278 * Add mixer input sinks.
6279 */
6280 rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Line In",
6281 AUDMIXSINKDIR_INPUT, &pThis->SinkLineIn.pMixSink);
6282 AssertRC(rc);
6283#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
6284 rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Microphone In",
6285 AUDMIXSINKDIR_INPUT, &pThis->SinkMicIn.pMixSink);
6286 AssertRC(rc);
6287#endif
6288 /* There is no master volume control. Set the master to max. */
6289 PDMAUDIOVOLUME vol = { false, 255, 255 };
6290 rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
6291 AssertRC(rc);
6292 }
6293 }
6294
6295 if (RT_SUCCESS(rc))
6296 {
6297 /* Construct codec. */
6298 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
6299 if (!pThis->pCodec)
6300 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
6301
6302 /* Set codec callbacks to this controller. */
6303 pThis->pCodec->pfnCbMixerAddStream = hdaMixerAddStream;
6304 pThis->pCodec->pfnCbMixerRemoveStream = hdaMixerRemoveStream;
6305 pThis->pCodec->pfnCbMixerSetStream = hdaMixerSetStream;
6306 pThis->pCodec->pfnCbMixerSetVolume = hdaMixerSetVolume;
6307
6308 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
6309
6310 /* Construct the codec. */
6311 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfg);
6312 if (RT_FAILURE(rc))
6313 AssertRCReturn(rc, rc);
6314
6315 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
6316 verb F20 should provide device/codec recognition. */
6317 Assert(pThis->pCodec->u16VendorId);
6318 Assert(pThis->pCodec->u16DeviceId);
6319 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
6320 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
6321 }
6322
6323 if (RT_SUCCESS(rc))
6324 {
6325 /*
6326 * Create all hardware streams.
6327 */
6328 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
6329 {
6330 rc = hdaStreamCreate(pThis, &pThis->aStreams[i], i /* uSD */);
6331 AssertRC(rc);
6332 }
6333
6334#ifdef VBOX_WITH_AUDIO_HDA_ONETIME_INIT
6335 /*
6336 * Initialize the driver chain.
6337 */
6338 PHDADRIVER pDrv;
6339 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
6340 {
6341 /*
6342 * Only primary drivers are critical for the VM to run. Everything else
6343 * might not worth showing an own error message box in the GUI.
6344 */
6345 if (!(pDrv->Flags & PDMAUDIODRVFLAGS_PRIMARY))
6346 continue;
6347
6348 PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
6349 AssertPtr(pCon);
6350
6351 bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
6352# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
6353 bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
6354# endif
6355 bool fValidOut = AudioMixerStreamIsValid(pDrv->Front.pMixStrm);
6356# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
6357 /** @todo Anything to do here? */
6358# endif
6359
6360 if ( !fValidLineIn
6361# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
6362 && !fValidMicIn
6363# endif
6364 && !fValidOut)
6365 {
6366 LogRel(("HDA: Falling back to NULL backend (no sound audible)\n"));
6367
6368 hdaReset(pDevIns);
6369 hdaReattach(pThis, pDrv, pDrv->uLUN, "NullAudio");
6370
6371 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
6372 N_("No audio devices could be opened. Selecting the NULL audio backend "
6373 "with the consequence that no sound is audible"));
6374 }
6375 else
6376 {
6377 bool fWarn = false;
6378
6379 PDMAUDIOBACKENDCFG backendCfg;
6380 int rc2 = pCon->pfnGetConfig(pCon, &backendCfg);
6381 if (RT_SUCCESS(rc2))
6382 {
6383 if (backendCfg.cMaxStreamsIn)
6384 {
6385# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
6386 /* If the audio backend supports two or more input streams at once,
6387 * warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
6388 if (backendCfg.cMaxStreamsIn >= 2)
6389 fWarn = !fValidLineIn || !fValidMicIn;
6390 /* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
6391 * *not* ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
6392 * One of the two simply is not in use then. */
6393 else if (backendCfg.cMaxStreamsIn == 1)
6394 fWarn = !fValidLineIn && !fValidMicIn;
6395 /* Don't warn if our backend is not able of supporting any input streams at all. */
6396# else /* !VBOX_WITH_AUDIO_HDA_MIC_IN */
6397 /* We only have line-in as input source. */
6398 fWarn = !fValidLineIn;
6399# endif /* VBOX_WITH_AUDIO_HDA_MIC_IN */
6400 }
6401
6402 if ( !fWarn
6403 && backendCfg.cMaxStreamsOut)
6404 {
6405 fWarn = !fValidOut;
6406 }
6407 }
6408 else
6409 {
6410 LogRel(("HDA: Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
6411 fWarn = true;
6412 }
6413
6414 if (fWarn)
6415 {
6416 char szMissingStreams[255];
6417 size_t len = 0;
6418 if (!fValidLineIn)
6419 {
6420 LogRel(("HDA: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
6421 len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
6422 }
6423# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
6424 if (!fValidMicIn)
6425 {
6426 LogRel(("HDA: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
6427 len += RTStrPrintf(szMissingStreams + len,
6428 sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
6429 }
6430# endif /* VBOX_WITH_AUDIO_HDA_MIC_IN */
6431 if (!fValidOut)
6432 {
6433 LogRel(("HDA: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
6434 len += RTStrPrintf(szMissingStreams + len,
6435 sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
6436 }
6437
6438 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
6439 N_("Some HDA audio streams (%s) could not be opened. Guest applications generating audio "
6440 "output or depending on audio input may hang. Make sure your host audio device "
6441 "is working properly. Check the logfile for error messages of the audio "
6442 "subsystem"), szMissingStreams);
6443 }
6444 }
6445 }
6446#endif /* VBOX_WITH_AUDIO_HDA_ONETIME_INIT */
6447 }
6448
6449 if (RT_SUCCESS(rc))
6450 {
6451 hdaReset(pDevIns);
6452
6453 /*
6454 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
6455 * hdaReset shouldn't affects these registers.
6456 */
6457 HDA_REG(pThis, WAKEEN) = 0x0;
6458 HDA_REG(pThis, STATESTS) = 0x0;
6459
6460#ifdef DEBUG
6461 /*
6462 * Debug and string formatter types.
6463 */
6464 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaDbgInfo);
6465 PDMDevHlpDBGFInfoRegister(pDevIns, "hdabdle", "HDA stream BDLE info. (hdabdle [stream number])", hdaDbgInfoBDLE);
6466 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaDbgInfoStream);
6467 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaDbgInfoCodecNodes);
6468 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaDbgInfoCodecSelector);
6469 PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaDbgInfoMixer);
6470
6471 rc = RTStrFormatTypeRegister("bdle", hdaDbgFmtBDLE, NULL);
6472 AssertRC(rc);
6473 rc = RTStrFormatTypeRegister("sdctl", hdaDbgFmtSDCTL, NULL);
6474 AssertRC(rc);
6475 rc = RTStrFormatTypeRegister("sdsts", hdaDbgFmtSDSTS, NULL);
6476 AssertRC(rc);
6477 rc = RTStrFormatTypeRegister("sdfifos", hdaDbgFmtSDFIFOS, NULL);
6478 AssertRC(rc);
6479 rc = RTStrFormatTypeRegister("sdfifow", hdaDbgFmtSDFIFOW, NULL);
6480 AssertRC(rc);
6481#endif /* DEBUG */
6482
6483 /*
6484 * Some debug assertions.
6485 */
6486 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
6487 {
6488 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
6489 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
6490
6491 /* binary search order. */
6492 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
6493 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6494 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
6495
6496 /* alignment. */
6497 AssertReleaseMsg( pReg->size == 1
6498 || (pReg->size == 2 && (pReg->offset & 1) == 0)
6499 || (pReg->size == 3 && (pReg->offset & 3) == 0)
6500 || (pReg->size == 4 && (pReg->offset & 3) == 0),
6501 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6502
6503 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
6504 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
6505 if (pReg->offset & 3)
6506 {
6507 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
6508 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6509 if (pPrevReg)
6510 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
6511 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6512 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
6513 }
6514#if 0
6515 if ((pReg->offset + pReg->size) & 3)
6516 {
6517 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6518 if (pNextReg)
6519 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
6520 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6521 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
6522 }
6523#endif
6524 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
6525 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
6526 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6527 }
6528 }
6529
6530# ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
6531 if (RT_SUCCESS(rc))
6532 {
6533 /* Create the emulation timer. */
6534 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
6535 TMTIMER_FLAGS_NO_CRIT_SECT, "DevHDA", &pThis->pTimer);
6536 AssertRCReturn(rc, rc);
6537
6538 if (RT_SUCCESS(rc))
6539 {
6540 pThis->cTimerTicks = TMTimerGetFreq(pThis->pTimer) / uTimerHz;
6541 pThis->uTimerTS = TMTimerGet(pThis->pTimer);
6542 LogFunc(("Timer ticks=%RU64 (%RU16 Hz)\n", pThis->cTimerTicks, uTimerHz));
6543 }
6544 }
6545# else
6546 if (RT_SUCCESS(rc))
6547 {
6548 PHDADRIVER pDrv;
6549 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
6550 {
6551 /* Only register primary driver.
6552 * The device emulation does the output multiplexing then. */
6553 if (pDrv->Flags != PDMAUDIODRVFLAGS_PRIMARY)
6554 continue;
6555
6556 PDMAUDIOCALLBACK AudioCallbacks[2];
6557
6558 HDACALLBACKCTX Ctx = { pThis, pDrv };
6559
6560 AudioCallbacks[0].enmType = PDMAUDIOCALLBACKTYPE_INPUT;
6561 AudioCallbacks[0].pfnCallback = hdaCallbackInput;
6562 AudioCallbacks[0].pvCtx = &Ctx;
6563 AudioCallbacks[0].cbCtx = sizeof(HDACALLBACKCTX);
6564
6565 AudioCallbacks[1].enmType = PDMAUDIOCALLBACKTYPE_OUTPUT;
6566 AudioCallbacks[1].pfnCallback = hdaCallbackOutput;
6567 AudioCallbacks[1].pvCtx = &Ctx;
6568 AudioCallbacks[1].cbCtx = sizeof(HDACALLBACKCTX);
6569
6570 rc = pDrv->pConnector->pfnRegisterCallbacks(pDrv->pConnector, AudioCallbacks, RT_ELEMENTS(AudioCallbacks));
6571 if (RT_FAILURE(rc))
6572 break;
6573 }
6574 }
6575# endif
6576
6577# ifdef VBOX_WITH_STATISTICS
6578 if (RT_SUCCESS(rc))
6579 {
6580 /*
6581 * Register statistics.
6582 */
6583# ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
6584 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
6585# endif
6586 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIn, STAMTYPE_PROFILE, "/Devices/HDA/Input", STAMUNIT_TICKS_PER_CALL, "Profiling input.");
6587 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatOut, STAMTYPE_PROFILE, "/Devices/HDA/Output", STAMUNIT_TICKS_PER_CALL, "Profiling output.");
6588 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
6589 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
6590 }
6591# endif
6592
6593#ifdef HDA_DEBUG_DUMP_PCM_DATA
6594 RTFileDelete(HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaDMARead.pcm");
6595 RTFileDelete(HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaDMAWrite.pcm");
6596 RTFileDelete(HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaStreamRead.pcm");
6597 RTFileDelete(HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaStreamWrite.pcm");
6598#endif
6599
6600 LogFlowFuncLeaveRC(rc);
6601 return rc;
6602}
6603
6604/**
6605 * The device registration structure.
6606 */
6607const PDMDEVREG g_DeviceHDA =
6608{
6609 /* u32Version */
6610 PDM_DEVREG_VERSION,
6611 /* szName */
6612 "hda",
6613 /* szRCMod */
6614 "VBoxDDRC.rc",
6615 /* szR0Mod */
6616 "VBoxDDR0.r0",
6617 /* pszDescription */
6618 "Intel HD Audio Controller",
6619 /* fFlags */
6620 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
6621 /* fClass */
6622 PDM_DEVREG_CLASS_AUDIO,
6623 /* cMaxInstances */
6624 1,
6625 /* cbInstance */
6626 sizeof(HDASTATE),
6627 /* pfnConstruct */
6628 hdaConstruct,
6629 /* pfnDestruct */
6630 hdaDestruct,
6631 /* pfnRelocate */
6632 NULL,
6633 /* pfnMemSetup */
6634 NULL,
6635 /* pfnPowerOn */
6636 NULL,
6637 /* pfnReset */
6638 hdaReset,
6639 /* pfnSuspend */
6640 NULL,
6641 /* pfnResume */
6642 NULL,
6643 /* pfnAttach */
6644 hdaAttach,
6645 /* pfnDetach */
6646 hdaDetach,
6647 /* pfnQueryInterface. */
6648 NULL,
6649 /* pfnInitComplete */
6650 NULL,
6651 /* pfnPowerOff */
6652 hdaPowerOff,
6653 /* pfnSoftReset */
6654 NULL,
6655 /* u32VersionEnd */
6656 PDM_DEVREG_VERSION
6657};
6658
6659#endif /* IN_RING3 */
6660#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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