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source: vbox/trunk/src/VBox/Devices/Audio/DevHDA.cpp@ 65458

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1/* $Id: DevHDA.cpp 65152 2017-01-05 13:08:28Z vboxsync $ */
2/** @file
3 * DevHDA - VBox Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2016 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22
23/*********************************************************************************************************************************
24* Header Files *
25*********************************************************************************************************************************/
26#define LOG_GROUP LOG_GROUP_DEV_HDA
27#include <VBox/log.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/pdmaudioifs.h>
30#include <VBox/version.h>
31
32#include <iprt/assert.h>
33#include <iprt/asm.h>
34#include <iprt/asm-math.h>
35#include <iprt/file.h>
36#include <iprt/list.h>
37#ifdef IN_RING3
38# include <iprt/mem.h>
39# include <iprt/semaphore.h>
40# include <iprt/string.h>
41# include <iprt/uuid.h>
42#endif
43
44#include "VBoxDD.h"
45
46#include "AudioMixBuffer.h"
47#include "AudioMixer.h"
48#include "HDACodec.h"
49#include "DevHDACommon.h"
50#include "DrvAudio.h"
51
52
53/*********************************************************************************************************************************
54* Defined Constants And Macros *
55*********************************************************************************************************************************/
56//#define HDA_AS_PCI_EXPRESS
57#define VBOX_WITH_INTEL_HDA
58
59/*
60 * HDA_DEBUG_DUMP_PCM_DATA enables dumping the raw PCM data
61 * to a file on the host. Be sure to adjust HDA_DEBUG_DUMP_PCM_DATA_PATH
62 * to your needs before using this!
63 */
64//#define HDA_DEBUG_DUMP_PCM_DATA
65#ifdef HDA_DEBUG_DUMP_PCM_DATA
66# ifdef RT_OS_WINDOWS
67# define HDA_DEBUG_DUMP_PCM_DATA_PATH "c:\\temp\\"
68# else
69# define HDA_DEBUG_DUMP_PCM_DATA_PATH "/tmp/"
70# endif
71#endif
72
73#if defined(VBOX_WITH_HP_HDA)
74/* HP Pavilion dv4t-1300 */
75# define HDA_PCI_VENDOR_ID 0x103c
76# define HDA_PCI_DEVICE_ID 0x30f7
77#elif defined(VBOX_WITH_INTEL_HDA)
78/* Intel HDA controller */
79# define HDA_PCI_VENDOR_ID 0x8086
80# define HDA_PCI_DEVICE_ID 0x2668
81#elif defined(VBOX_WITH_NVIDIA_HDA)
82/* nVidia HDA controller */
83# define HDA_PCI_VENDOR_ID 0x10de
84# define HDA_PCI_DEVICE_ID 0x0ac0
85#else
86# error "Please specify your HDA device vendor/device IDs"
87#endif
88
89/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
90 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
91 * is read only except for bit 15 like the HDA spec states.
92 *
93 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
94 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
95#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
96
97/* Make sure that interleaving streams support is enabled if the 5.1 surround code is being used. */
98#if defined (VBOX_WITH_AUDIO_HDA_51_SURROUND) && !defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT)
99# define VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT
100#endif
101
102/** Default timer frequency (in Hz). */
103#define HDA_TIMER_HZ 100
104
105/**
106 * At the moment we support 4 input + 4 output streams max, which is 8 in total.
107 * Bidirectional streams are currently *not* supported.
108 *
109 * Note: When changing any of those values, be prepared for some saved state
110 * fixups / trouble!
111 */
112#define HDA_MAX_SDI 4
113#define HDA_MAX_SDO 4
114#define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
115AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
116
117/** Number of general registers. */
118#define HDA_NUM_GENERAL_REGS 34
119/** Number of total registers in the HDA's register map. */
120#define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */))
121/** Total number of stream tags (channels). Index 0 is reserved / invalid. */
122#define HDA_MAX_TAGS 16
123
124/**
125 * NB: Register values stored in memory (au32Regs[]) are indexed through
126 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
127 * register descriptors in g_aHdaRegMap[] are indexed through the
128 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
129 *
130 * The au32Regs[] layout is kept unchanged for saved state
131 * compatibility.
132 */
133
134/* Registers */
135#define HDA_REG_IND_NAME(x) HDA_REG_##x
136#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
137#define HDA_REG_FIELD_MASK(reg, x) HDA_##reg##_##x##_MASK
138#define HDA_REG_FIELD_FLAG_MASK(reg, x) RT_BIT(HDA_##reg##_##x##_SHIFT)
139#define HDA_REG_FIELD_SHIFT(reg, x) HDA_##reg##_##x##_SHIFT
140#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
141#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
142#define HDA_REG_FLAG_VALUE(pThis, reg, val) (HDA_REG((pThis),reg) & (((HDA_REG_FIELD_FLAG_MASK(reg, val)))))
143
144
145#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
146#define HDA_RMX_GCAP 0
147/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
148 * oss (15:12) - number of output streams supported
149 * iss (11:8) - number of input streams supported
150 * bss (7:3) - number of bidirectional streams supported
151 * bds (2:1) - number of serial data out (SDO) signals supported
152 * b64sup (0) - 64 bit addressing supported.
153 */
154#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
155 ( (((oss) & 0xF) << 12) \
156 | (((iss) & 0xF) << 8) \
157 | (((bss) & 0x1F) << 3) \
158 | (((bds) & 0x3) << 1) \
159 | ((b64sup) & 1))
160
161#define HDA_REG_VMIN 1 /* 0x02 */
162#define HDA_RMX_VMIN 1
163
164#define HDA_REG_VMAJ 2 /* 0x03 */
165#define HDA_RMX_VMAJ 2
166
167#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
168#define HDA_RMX_OUTPAY 3
169
170#define HDA_REG_INPAY 4 /* 0x06-0x07 */
171#define HDA_RMX_INPAY 4
172
173#define HDA_REG_GCTL 5 /* 0x08-0x0B */
174#define HDA_RMX_GCTL 5
175#define HDA_GCTL_RST_SHIFT 0
176#define HDA_GCTL_FSH_SHIFT 1
177#define HDA_GCTL_UR_SHIFT 8
178
179#define HDA_REG_WAKEEN 6 /* 0x0C */
180#define HDA_RMX_WAKEEN 6
181
182#define HDA_REG_STATESTS 7 /* 0x0E */
183#define HDA_RMX_STATESTS 7
184#define HDA_STATESTS_SCSF_MASK 0x7 /* State Change Status Flags (6.2.8). */
185
186#define HDA_REG_GSTS 8 /* 0x10-0x11*/
187#define HDA_RMX_GSTS 8
188#define HDA_GSTS_FSH_SHIFT 1
189
190#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
191#define HDA_RMX_OUTSTRMPAY 112
192
193#define HDA_REG_INSTRMPAY 10 /* 0x1a */
194#define HDA_RMX_INSTRMPAY 113
195
196#define HDA_REG_INTCTL 11 /* 0x20 */
197#define HDA_RMX_INTCTL 9
198#define HDA_INTCTL_GIE_SHIFT 31
199#define HDA_INTCTL_CIE_SHIFT 30
200#define HDA_INTCTL_S0_SHIFT 0
201#define HDA_INTCTL_S1_SHIFT 1
202#define HDA_INTCTL_S2_SHIFT 2
203#define HDA_INTCTL_S3_SHIFT 3
204#define HDA_INTCTL_S4_SHIFT 4
205#define HDA_INTCTL_S5_SHIFT 5
206#define HDA_INTCTL_S6_SHIFT 6
207#define HDA_INTCTL_S7_SHIFT 7
208#define INTCTL_SX(pThis, X) (HDA_REG_FLAG_VALUE((pThis), INTCTL, S##X))
209#define HDA_INTCTL_GIE_MASK RT_BIT(31) /* Global Interrupt Enable (3.3.14). */
210
211#define HDA_REG_INTSTS 12 /* 0x24 */
212#define HDA_RMX_INTSTS 10
213#define HDA_INTSTS_GIS_SHIFT 31
214#define HDA_INTSTS_CIS_SHIFT 30
215#define HDA_INTSTS_S0_SHIFT 0
216#define HDA_INTSTS_S1_SHIFT 1
217#define HDA_INTSTS_S2_SHIFT 2
218#define HDA_INTSTS_S3_SHIFT 3
219#define HDA_INTSTS_S4_SHIFT 4
220#define HDA_INTSTS_S5_SHIFT 5
221#define HDA_INTSTS_S6_SHIFT 6
222#define HDA_INTSTS_S7_SHIFT 7
223#define HDA_INTSTS_S_MASK(num) RT_BIT(HDA_REG_FIELD_SHIFT(S##num))
224
225#define HDA_REG_WALCLK 13 /* 0x30 */
226#define HDA_RMX_WALCLK /* Not defined! */
227
228/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
229 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
230 * the datasheet.
231 */
232#define HDA_REG_SSYNC 14 /* 0x38 */
233#define HDA_RMX_SSYNC 12
234
235#define HDA_REG_CORBLBASE 15 /* 0x40 */
236#define HDA_RMX_CORBLBASE 13
237
238#define HDA_REG_CORBUBASE 16 /* 0x44 */
239#define HDA_RMX_CORBUBASE 14
240
241#define HDA_REG_CORBWP 17 /* 0x48 */
242#define HDA_RMX_CORBWP 15
243
244#define HDA_REG_CORBRP 18 /* 0x4A */
245#define HDA_RMX_CORBRP 16
246#define HDA_CORBRP_RST_SHIFT 15
247#define HDA_CORBRP_WP_SHIFT 0
248#define HDA_CORBRP_WP_MASK 0xFF
249
250#define HDA_REG_CORBCTL 19 /* 0x4C */
251#define HDA_RMX_CORBCTL 17
252#define HDA_CORBCTL_DMA_SHIFT 1
253#define HDA_CORBCTL_CMEIE_SHIFT 0
254
255#define HDA_REG_CORBSTS 20 /* 0x4D */
256#define HDA_RMX_CORBSTS 18
257#define HDA_CORBSTS_CMEI_SHIFT 0
258
259#define HDA_REG_CORBSIZE 21 /* 0x4E */
260#define HDA_RMX_CORBSIZE 19
261#define HDA_CORBSIZE_SZ_CAP 0xF0
262#define HDA_CORBSIZE_SZ 0x3
263/* till ich 10 sizes of CORB and RIRB are hardcoded to 256 in real hw */
264
265#define HDA_REG_RIRBLBASE 22 /* 0x50 */
266#define HDA_RMX_RIRBLBASE 20
267
268#define HDA_REG_RIRBUBASE 23 /* 0x54 */
269#define HDA_RMX_RIRBUBASE 21
270
271#define HDA_REG_RIRBWP 24 /* 0x58 */
272#define HDA_RMX_RIRBWP 22
273#define HDA_RIRBWP_RST_SHIFT 15
274#define HDA_RIRBWP_WP_MASK 0xFF
275
276#define HDA_REG_RINTCNT 25 /* 0x5A */
277#define HDA_RMX_RINTCNT 23
278#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
279
280#define HDA_REG_RIRBCTL 26 /* 0x5C */
281#define HDA_RMX_RIRBCTL 24
282#define HDA_RIRBCTL_RIC_SHIFT 0
283#define HDA_RIRBCTL_DMA_SHIFT 1
284#define HDA_ROI_DMA_SHIFT 2
285
286#define HDA_REG_RIRBSTS 27 /* 0x5D */
287#define HDA_RMX_RIRBSTS 25
288#define HDA_RIRBSTS_RINTFL_SHIFT 0
289#define HDA_RIRBSTS_RIRBOIS_SHIFT 2
290
291#define HDA_REG_RIRBSIZE 28 /* 0x5E */
292#define HDA_RMX_RIRBSIZE 26
293#define HDA_RIRBSIZE_SZ_CAP 0xF0
294#define HDA_RIRBSIZE_SZ 0x3
295
296#define RIRBSIZE_SZ(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ)
297#define RIRBSIZE_SZ_CAP(pThis) (HDA_REG(pThis, HDA_REG_RIRBSIZE) & HDA_RIRBSIZE_SZ_CAP)
298
299
300#define HDA_REG_IC 29 /* 0x60 */
301#define HDA_RMX_IC 27
302
303#define HDA_REG_IR 30 /* 0x64 */
304#define HDA_RMX_IR 28
305
306#define HDA_REG_IRS 31 /* 0x68 */
307#define HDA_RMX_IRS 29
308#define HDA_IRS_ICB_SHIFT 0
309#define HDA_IRS_IRV_SHIFT 1
310
311#define HDA_REG_DPLBASE 32 /* 0x70 */
312#define HDA_RMX_DPLBASE 30
313#define DPLBASE(pThis) (HDA_REG((pThis), DPLBASE))
314
315#define HDA_REG_DPUBASE 33 /* 0x74 */
316#define HDA_RMX_DPUBASE 31
317#define DPUBASE(pThis) (HDA_REG((pThis), DPUBASE))
318
319#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
320
321#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
322#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
323/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
324#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
325
326#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
327
328/** @todo Condense marcos! */
329
330#define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80 */
331#define HDA_REG_SD1CTL (HDA_STREAM_REG_DEF(CTL, 0) + 10) /* 0xA0 */
332#define HDA_REG_SD2CTL (HDA_STREAM_REG_DEF(CTL, 0) + 20) /* 0xC0 */
333#define HDA_REG_SD3CTL (HDA_STREAM_REG_DEF(CTL, 0) + 30) /* 0xE0 */
334#define HDA_REG_SD4CTL (HDA_STREAM_REG_DEF(CTL, 0) + 40) /* 0x100 */
335#define HDA_REG_SD5CTL (HDA_STREAM_REG_DEF(CTL, 0) + 50) /* 0x120 */
336#define HDA_REG_SD6CTL (HDA_STREAM_REG_DEF(CTL, 0) + 60) /* 0x140 */
337#define HDA_REG_SD7CTL (HDA_STREAM_REG_DEF(CTL, 0) + 70) /* 0x160 */
338#define HDA_RMX_SD0CTL 32
339#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
340#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
341#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
342#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
343#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
344#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
345#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
346
347#define SD(func, num) SD##num##func
348
349#define HDA_SDCTL(pThis, num) HDA_REG((pThis), SD(CTL, num))
350#define HDA_SDCTL_NUM(pThis, num) ((HDA_SDCTL((pThis), num) & HDA_REG_FIELD_MASK(SDCTL,NUM)) >> HDA_REG_FIELD_SHIFT(SDCTL, NUM))
351#define HDA_SDCTL_NUM_MASK 0xF
352#define HDA_SDCTL_NUM_SHIFT 20
353#define HDA_SDCTL_DIR_SHIFT 19
354#define HDA_SDCTL_TP_SHIFT 18
355#define HDA_SDCTL_STRIPE_MASK 0x3
356#define HDA_SDCTL_STRIPE_SHIFT 16
357#define HDA_SDCTL_DEIE_SHIFT 4
358#define HDA_SDCTL_FEIE_SHIFT 3
359#define HDA_SDCTL_ICE_SHIFT 2
360#define HDA_SDCTL_RUN_SHIFT 1
361#define HDA_SDCTL_SRST_SHIFT 0
362
363#define HDA_REG_SD0STS 35 /* 0x83 */
364#define HDA_REG_SD1STS (HDA_STREAM_REG_DEF(STS, 0) + 10) /* 0xA3 */
365#define HDA_REG_SD2STS (HDA_STREAM_REG_DEF(STS, 0) + 20) /* 0xC3 */
366#define HDA_REG_SD3STS (HDA_STREAM_REG_DEF(STS, 0) + 30) /* 0xE3 */
367#define HDA_REG_SD4STS (HDA_STREAM_REG_DEF(STS, 0) + 40) /* 0x103 */
368#define HDA_REG_SD5STS (HDA_STREAM_REG_DEF(STS, 0) + 50) /* 0x123 */
369#define HDA_REG_SD6STS (HDA_STREAM_REG_DEF(STS, 0) + 60) /* 0x143 */
370#define HDA_REG_SD7STS (HDA_STREAM_REG_DEF(STS, 0) + 70) /* 0x163 */
371#define HDA_RMX_SD0STS 33
372#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
373#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
374#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
375#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
376#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
377#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
378#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
379
380#define SDSTS(pThis, num) HDA_REG((pThis), SD(STS, num))
381#define HDA_SDSTS_FIFORDY_SHIFT 5
382#define HDA_SDSTS_DE_SHIFT 4
383#define HDA_SDSTS_FE_SHIFT 3
384#define HDA_SDSTS_BCIS_SHIFT 2
385
386#define HDA_REG_SD0LPIB 36 /* 0x84 */
387#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
388#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
389#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
390#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
391#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
392#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
393#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
394#define HDA_RMX_SD0LPIB 34
395#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
396#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
397#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
398#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
399#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
400#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
401#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
402
403#define HDA_REG_SD0CBL 37 /* 0x88 */
404#define HDA_REG_SD1CBL (HDA_STREAM_REG_DEF(CBL, 0) + 10) /* 0xA8 */
405#define HDA_REG_SD2CBL (HDA_STREAM_REG_DEF(CBL, 0) + 20) /* 0xC8 */
406#define HDA_REG_SD3CBL (HDA_STREAM_REG_DEF(CBL, 0) + 30) /* 0xE8 */
407#define HDA_REG_SD4CBL (HDA_STREAM_REG_DEF(CBL, 0) + 40) /* 0x108 */
408#define HDA_REG_SD5CBL (HDA_STREAM_REG_DEF(CBL, 0) + 50) /* 0x128 */
409#define HDA_REG_SD6CBL (HDA_STREAM_REG_DEF(CBL, 0) + 60) /* 0x148 */
410#define HDA_REG_SD7CBL (HDA_STREAM_REG_DEF(CBL, 0) + 70) /* 0x168 */
411#define HDA_RMX_SD0CBL 35
412#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
413#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
414#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
415#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
416#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
417#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
418#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
419
420#define HDA_REG_SD0LVI 38 /* 0x8C */
421#define HDA_REG_SD1LVI (HDA_STREAM_REG_DEF(LVI, 0) + 10) /* 0xAC */
422#define HDA_REG_SD2LVI (HDA_STREAM_REG_DEF(LVI, 0) + 20) /* 0xCC */
423#define HDA_REG_SD3LVI (HDA_STREAM_REG_DEF(LVI, 0) + 30) /* 0xEC */
424#define HDA_REG_SD4LVI (HDA_STREAM_REG_DEF(LVI, 0) + 40) /* 0x10C */
425#define HDA_REG_SD5LVI (HDA_STREAM_REG_DEF(LVI, 0) + 50) /* 0x12C */
426#define HDA_REG_SD6LVI (HDA_STREAM_REG_DEF(LVI, 0) + 60) /* 0x14C */
427#define HDA_REG_SD7LVI (HDA_STREAM_REG_DEF(LVI, 0) + 70) /* 0x16C */
428#define HDA_RMX_SD0LVI 36
429#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
430#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
431#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
432#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
433#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
434#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
435#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
436
437#define HDA_REG_SD0FIFOW 39 /* 0x8E */
438#define HDA_REG_SD1FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 10) /* 0xAE */
439#define HDA_REG_SD2FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 20) /* 0xCE */
440#define HDA_REG_SD3FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 30) /* 0xEE */
441#define HDA_REG_SD4FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 40) /* 0x10E */
442#define HDA_REG_SD5FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 50) /* 0x12E */
443#define HDA_REG_SD6FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 60) /* 0x14E */
444#define HDA_REG_SD7FIFOW (HDA_STREAM_REG_DEF(FIFOW, 0) + 70) /* 0x16E */
445#define HDA_RMX_SD0FIFOW 37
446#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
447#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
448#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
449#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
450#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
451#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
452#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
453
454/*
455 * ICH6 datasheet defined limits for FIFOW values (18.2.38).
456 */
457#define HDA_SDFIFOW_8B 0x2
458#define HDA_SDFIFOW_16B 0x3
459#define HDA_SDFIFOW_32B 0x4
460
461#define HDA_REG_SD0FIFOS 40 /* 0x90 */
462#define HDA_REG_SD1FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 10) /* 0xB0 */
463#define HDA_REG_SD2FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 20) /* 0xD0 */
464#define HDA_REG_SD3FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 30) /* 0xF0 */
465#define HDA_REG_SD4FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 40) /* 0x110 */
466#define HDA_REG_SD5FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 50) /* 0x130 */
467#define HDA_REG_SD6FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 60) /* 0x150 */
468#define HDA_REG_SD7FIFOS (HDA_STREAM_REG_DEF(FIFOS, 0) + 70) /* 0x170 */
469#define HDA_RMX_SD0FIFOS 38
470#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
471#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
472#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
473#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
474#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
475#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
476#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
477
478/*
479 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
480 * formula: size - 1
481 * Other values not listed are not supported.
482 */
483/** Maximum FIFO size (in bytes). */
484#define HDA_FIFO_MAX 256
485
486#define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
487#define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
488
489#define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
490#define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
491#define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
492#define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
493#define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
494#define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
495#define SDFIFOS(pThis, num) HDA_REG((pThis), SD(FIFOS, num))
496
497#define HDA_REG_SD0FMT 41 /* 0x92 */
498#define HDA_REG_SD1FMT (HDA_STREAM_REG_DEF(FMT, 0) + 10) /* 0xB2 */
499#define HDA_REG_SD2FMT (HDA_STREAM_REG_DEF(FMT, 0) + 20) /* 0xD2 */
500#define HDA_REG_SD3FMT (HDA_STREAM_REG_DEF(FMT, 0) + 30) /* 0xF2 */
501#define HDA_REG_SD4FMT (HDA_STREAM_REG_DEF(FMT, 0) + 40) /* 0x112 */
502#define HDA_REG_SD5FMT (HDA_STREAM_REG_DEF(FMT, 0) + 50) /* 0x132 */
503#define HDA_REG_SD6FMT (HDA_STREAM_REG_DEF(FMT, 0) + 60) /* 0x152 */
504#define HDA_REG_SD7FMT (HDA_STREAM_REG_DEF(FMT, 0) + 70) /* 0x172 */
505#define HDA_RMX_SD0FMT 39
506#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
507#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
508#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
509#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
510#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
511#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
512#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
513
514#define SDFMT(pThis, num) (HDA_REG((pThis), SD(FMT, num)))
515#define HDA_SDFMT_BASE_RATE(pThis, num) ((SDFMT(pThis, num) & HDA_REG_FIELD_FLAG_MASK(SDFMT, BASE_RATE)) >> HDA_REG_FIELD_SHIFT(SDFMT, BASE_RATE))
516#define HDA_SDFMT_MULT(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,MULT)) >> HDA_REG_FIELD_SHIFT(SDFMT, MULT))
517#define HDA_SDFMT_DIV(pThis, num) ((SDFMT((pThis), num) & HDA_REG_FIELD_MASK(SDFMT,DIV)) >> HDA_REG_FIELD_SHIFT(SDFMT, DIV))
518
519#define HDA_REG_SD0BDPL 42 /* 0x98 */
520#define HDA_REG_SD1BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 10) /* 0xB8 */
521#define HDA_REG_SD2BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 20) /* 0xD8 */
522#define HDA_REG_SD3BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 30) /* 0xF8 */
523#define HDA_REG_SD4BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 40) /* 0x118 */
524#define HDA_REG_SD5BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 50) /* 0x138 */
525#define HDA_REG_SD6BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 60) /* 0x158 */
526#define HDA_REG_SD7BDPL (HDA_STREAM_REG_DEF(BDPL, 0) + 70) /* 0x178 */
527#define HDA_RMX_SD0BDPL 40
528#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
529#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
530#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
531#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
532#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
533#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
534#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
535
536#define HDA_REG_SD0BDPU 43 /* 0x9C */
537#define HDA_REG_SD1BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 10) /* 0xBC */
538#define HDA_REG_SD2BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 20) /* 0xDC */
539#define HDA_REG_SD3BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 30) /* 0xFC */
540#define HDA_REG_SD4BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 40) /* 0x11C */
541#define HDA_REG_SD5BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 50) /* 0x13C */
542#define HDA_REG_SD6BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 60) /* 0x15C */
543#define HDA_REG_SD7BDPU (HDA_STREAM_REG_DEF(BDPU, 0) + 70) /* 0x17C */
544#define HDA_RMX_SD0BDPU 41
545#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
546#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
547#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
548#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
549#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
550#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
551#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
552
553#define HDA_BDLE_FLAG_IOC RT_BIT(0) /* Interrupt on completion (IOC). */
554
555#define HDA_CODEC_CAD_SHIFT 28
556/* Encodes the (required) LUN into a codec command. */
557#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
558
559
560
561/*********************************************************************************************************************************
562* Structures and Typedefs *
563*********************************************************************************************************************************/
564
565/**
566 * Internal state of a Buffer Descriptor List Entry (BDLE),
567 * needed to keep track of the data needed for the actual device
568 * emulation.
569 */
570typedef struct HDABDLESTATE
571{
572 /** Own index within the BDL (Buffer Descriptor List). */
573 uint32_t u32BDLIndex;
574 /** Number of bytes below the stream's FIFO watermark (SDFIFOW).
575 * Used to check if we need fill up the FIFO again. */
576 uint32_t cbBelowFIFOW;
577 /** Current offset in DMA buffer (in bytes).*/
578 uint32_t u32BufOff;
579 uint32_t Padding;
580} HDABDLESTATE, *PHDABDLESTATE;
581
582/**
583 * BDL description structure.
584 * Do not touch this, as this must match to the HDA specs.
585 */
586typedef struct HDABDLEDESC
587{
588 /** Starting address of the actual buffer. Must be 128-bit aligned. */
589 uint64_t u64BufAdr;
590 /** Size of the actual buffer (in bytes). */
591 uint32_t u32BufSize;
592 /** Bit 0: Interrupt on completion; the controller will generate
593 * an interrupt when the last byte of the buffer has been
594 * fetched by the DMA engine.
595 *
596 * Rest is reserved for further use and must be 0. */
597 uint32_t fFlags;
598} HDABDLEDESC, *PHDABDLEDESC;
599AssertCompileSize(HDABDLEDESC, 16); /* Always 16 byte. Also must be aligned on 128-byte boundary. */
600
601/**
602 * Buffer Descriptor List Entry (BDLE) (3.6.3).
603 */
604typedef struct HDABDLE
605{
606 /** The actual BDL description. */
607 HDABDLEDESC Desc;
608 /** Internal state of this BDLE.
609 * Not part of the actual BDLE registers. */
610 HDABDLESTATE State;
611} HDABDLE, *PHDABDLE;
612
613/**
614 * Structure for keeping an audio stream data mapping.
615 */
616typedef struct HDASTREAMMAPPING
617{
618 /** The stream's layout. */
619 PDMAUDIOSTREAMLAYOUT enmLayout;
620 /** Number of audio channels in this stream. */
621 uint8_t cChannels;
622 /** Array of audio channels. */
623 R3PTRTYPE(PPDMAUDIOSTREAMCHANNEL) paChannels;
624 /** Circular buffer holding for holding audio data for this mapping. */
625 R3PTRTYPE(PRTCIRCBUF) pCircBuf;
626} HDASTREAMMAPPING, *PHDASTREAMMAPPING;
627
628#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
629/**
630 * Structure keeping the HDA stream's state for asynchronous I/O.
631 */
632typedef struct HDASTREAMSTATEAIO
633{
634 /** Thread handle for the actual I/O thread. */
635 RTTHREAD Thread;
636 /** Event for letting the thread know there is some data to process. */
637 RTSEMEVENT Event;
638 /** Critical section for synchronizing access. */
639 RTCRITSECT CritSect;
640 /** Started indicator. */
641 volatile bool fStarted;
642 /** Shutdown indicator. */
643 volatile bool fShutdown;
644 /** Whether the thread should do any data processing or not. */
645 volatile bool fEnabled;
646 uint32_t Padding1;
647} HDASTREAMSTATEAIO, *PHDASTREAMSTATEAIO;
648#endif
649
650/**
651 * Internal state of a HDA stream.
652 */
653typedef struct HDASTREAMSTATE
654{
655 /** Current BDLE to use. Wraps around to 0 if
656 * maximum (cBDLE) is reached. */
657 uint16_t uCurBDLE;
658 /** Flag indicating whether this stream currently is
659 * in reset mode and therefore not acccessible by the guest. */
660 volatile bool fInReset;
661 /** Unused, padding. */
662 uint32_t Padding0;
663 /** Critical section to serialize access. */
664 RTCRITSECT CritSect;
665#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
666 /** Asynchronous I/O state members. */
667 HDASTREAMSTATEAIO AIO;
668#endif
669 /** This stream's data mapping. */
670 HDASTREAMMAPPING Mapping;
671 /** Current BDLE (Buffer Descriptor List Entry). */
672 HDABDLE BDLE;
673 /** Circular buffer (FIFO) for holding DMA'ed data. */
674 R3PTRTYPE(PRTCIRCBUF) pCircBuf;
675} HDASTREAMSTATE, *PHDASTREAMSTATE;
676
677/**
678 * Structure defining an HDA mixer sink.
679 * Its purpose is to know which audio mixer sink is bound to
680 * which SDn (SDI/SDO) device stream.
681 *
682 * This is needed in order to handle interleaved streams
683 * (that is, multiple channels in one stream) or non-interleaved
684 * streams (each channel has a dedicated stream).
685 *
686 * This is only known to the actual device emulation level.
687 */
688typedef struct HDAMIXERSINK
689{
690 /** SDn ID this sink is assigned to. 0 if not assigned. */
691 uint8_t uSD;
692 /** Channel ID of SDn ID. Only valid if SDn ID is valid. */
693 uint8_t uChannel;
694 uint8_t Padding[3];
695 /** Pointer to the actual audio mixer sink. */
696 R3PTRTYPE(PAUDMIXSINK) pMixSink;
697} HDAMIXERSINK, *PHDAMIXERSINK;
698
699/**
700 * Structure for keeping a HDA stream (SDI / SDO).
701 *
702 * Note: This HDA stream has nothing to do with a regular audio stream handled
703 * by the audio connector or the audio mixer. This HDA stream is a serial data in/out
704 * stream (SDI/SDO) defined in hardware and can contain multiple audio streams
705 * in one single SDI/SDO (interleaving streams).
706 *
707 * How a specific SDI/SDO is mapped to our internal audio streams relies on the
708 * stream channel mappings.
709 *
710 * Contains only register values which do *not* change until a
711 * stream reset occurs.
712 */
713typedef struct HDASTREAM
714{
715 /** Stream descriptor number (SDn). */
716 uint8_t u8SD;
717 uint8_t Padding0[7];
718 /** DMA base address (SDnBDPU - SDnBDPL). */
719 uint64_t u64BDLBase;
720 /** Cyclic Buffer Length (SDnCBL).
721 * Represents the size of the ring buffer. */
722 uint32_t u32CBL;
723 /** Format (SDnFMT). */
724 uint16_t u16FMT;
725 /** FIFO Size (FIFOS).
726 * Maximum number of bytes that may have been DMA'd into
727 * memory but not yet transmitted on the link. */
728 uint16_t u16FIFOS;
729 /** FIFO Watermark. */
730 uint16_t u16FIFOW;
731 /** Last Valid Index (SDnLVI). */
732 uint16_t u16LVI;
733 uint16_t Padding1[2];
734 /** Pointer to HDA sink this stream is attached to. */
735 R3PTRTYPE(PHDAMIXERSINK) pMixSink;
736 /** Internal state of this stream. */
737 HDASTREAMSTATE State;
738} HDASTREAM, *PHDASTREAM;
739
740#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
741/**
742 * Structure for keeping a HDA stream thread context.
743 */
744typedef struct HDASTREAMTHREADCTX
745{
746 PHDASTATE pThis;
747 PHDASTREAM pStream;
748} HDASTREAMTHREADCTX, *PHDASTREAMTHREADCTX;
749#endif
750
751/**
752 * Structure for mapping a stream tag to an HDA stream.
753 */
754typedef struct HDATAG
755{
756 /** Own stream tag. */
757 uint8_t uTag;
758 uint8_t Padding[7];
759 /** Pointer to associated stream. */
760 R3PTRTYPE(PHDASTREAM) pStrm;
761} HDATAG, *PHDATAG;
762
763/**
764 * Structure defining a (host backend) driver stream.
765 * Each driver has its own instances of audio mixer streams, which then
766 * can go into the same (or even different) audio mixer sinks.
767 */
768typedef struct HDADRIVERSTREAM
769{
770 union
771 {
772 /** Desired playback destination (for an output stream). */
773 PDMAUDIOPLAYBACKDEST Dest;
774 /** Desired recording source (for an input stream). */
775 PDMAUDIORECSOURCE Source;
776 } DestSource;
777 uint8_t Padding1[4];
778 /** Associated mixer handle. */
779 R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
780} HDADRIVERSTREAM, *PHDADRIVERSTREAM;
781
782/**
783 * Struct for maintaining a host backend driver.
784 * This driver must be associated to one, and only one,
785 * HDA codec. The HDA controller does the actual multiplexing
786 * of HDA codec data to various host backend drivers then.
787 *
788 * This HDA device uses a timer in order to synchronize all
789 * read/write accesses across all attached LUNs / backends.
790 */
791typedef struct HDADRIVER
792{
793 /** Node for storing this driver in our device driver list of HDASTATE. */
794 RTLISTNODER3 Node;
795 /** Pointer to HDA controller (state). */
796 R3PTRTYPE(PHDASTATE) pHDAState;
797 /** Driver flags. */
798 PDMAUDIODRVFLAGS Flags;
799 uint8_t u32Padding0[2];
800 /** LUN to which this driver has been assigned. */
801 uint8_t uLUN;
802 /** Whether this driver is in an attached state or not. */
803 bool fAttached;
804 /** Pointer to attached driver base interface. */
805 R3PTRTYPE(PPDMIBASE) pDrvBase;
806 /** Audio connector interface to the underlying host backend. */
807 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
808 /** Mixer stream for line input. */
809 HDADRIVERSTREAM LineIn;
810#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
811 /** Mixer stream for mic input. */
812 HDADRIVERSTREAM MicIn;
813#endif
814 /** Mixer stream for front output. */
815 HDADRIVERSTREAM Front;
816#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
817 /** Mixer stream for center/LFE output. */
818 HDADRIVERSTREAM CenterLFE;
819 /** Mixer stream for rear output. */
820 HDADRIVERSTREAM Rear;
821#endif
822} HDADRIVER;
823
824/**
825 * ICH Intel HD Audio Controller state.
826 */
827typedef struct HDASTATE
828{
829 /** The PCI device structure. */
830 PDMPCIDEV PciDev;
831 /** R3 Pointer to the device instance. */
832 PPDMDEVINSR3 pDevInsR3;
833 /** R0 Pointer to the device instance. */
834 PPDMDEVINSR0 pDevInsR0;
835 /** R0 Pointer to the device instance. */
836 PPDMDEVINSRC pDevInsRC;
837 /** Padding for alignment. */
838 uint32_t u32Padding;
839 /** The base interface for LUN\#0. */
840 PDMIBASE IBase;
841 RTGCPHYS MMIOBaseAddr;
842 /** The HDA's register set. */
843 uint32_t au32Regs[HDA_NUM_REGS];
844 /** Internal stream states. */
845 HDASTREAM aStreams[HDA_MAX_STREAMS];
846 /** Mapping table between stream tags and stream states. */
847 HDATAG aTags[HDA_MAX_TAGS];
848 /** CORB buffer base address. */
849 uint64_t u64CORBBase;
850 /** RIRB buffer base address. */
851 uint64_t u64RIRBBase;
852 /** DMA base address.
853 * Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
854 uint64_t u64DPBase;
855 /** DMA position buffer enable bit. */
856 bool fDMAPosition;
857 /** Padding for alignment. */
858 uint8_t u8Padding0[7];
859 /** Pointer to CORB buffer. */
860 R3PTRTYPE(uint32_t *) pu32CorbBuf;
861 /** Size in bytes of CORB buffer. */
862 uint32_t cbCorbBuf;
863 /** Padding for alignment. */
864 uint32_t u32Padding1;
865 /** Pointer to RIRB buffer. */
866 R3PTRTYPE(uint64_t *) pu64RirbBuf;
867 /** Size in bytes of RIRB buffer. */
868 uint32_t cbRirbBuf;
869 /** Indicates if HDA controller is in reset mode. */
870 bool fInReset;
871 /** Flag whether the R0 part is enabled. */
872 bool fR0Enabled;
873 /** Flag whether the RC part is enabled. */
874 bool fRCEnabled;
875 /** Number of active (running) SDn streams. */
876 uint8_t cStreamsActive;
877#ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
878 /** The timer for pumping data thru the attached LUN drivers. */
879 PTMTIMERR3 pTimer;
880 /** Flag indicating whether the timer is active or not. */
881 bool fTimerActive;
882 uint8_t u8Padding1[7];
883 /** Timer ticks per Hz. */
884 uint64_t cTimerTicks;
885 /** Timestamp of the last timer callback (hdaTimer).
886 * Used to calculate the time actually elapsed between two timer callbacks. */
887 uint64_t uTimerTS;
888 uint64_t uTimerMS;
889#endif
890#ifdef VBOX_WITH_STATISTICS
891# ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
892 STAMPROFILE StatTimer;
893# endif
894 STAMPROFILE StatIn;
895 STAMPROFILE StatOut;
896 STAMCOUNTER StatBytesRead;
897 STAMCOUNTER StatBytesWritten;
898#endif
899 /** Pointer to HDA codec to use. */
900 R3PTRTYPE(PHDACODEC) pCodec;
901 /** List of associated LUN drivers (HDADRIVER). */
902 RTLISTANCHORR3 lstDrv;
903 /** The device' software mixer. */
904 R3PTRTYPE(PAUDIOMIXER) pMixer;
905 /** HDA sink for (front) output. */
906 HDAMIXERSINK SinkFront;
907#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
908 /** HDA sink for center / LFE output. */
909 HDAMIXERSINK SinkCenterLFE;
910 /** HDA sink for rear output. */
911 HDAMIXERSINK SinkRear;
912#endif
913 /** HDA mixer sink for line input. */
914 HDAMIXERSINK SinkLineIn;
915#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
916 /** Audio mixer sink for microphone input. */
917 HDAMIXERSINK SinkMicIn;
918#endif
919 uint64_t u64BaseTS;
920 /** Response Interrupt Count (RINTCNT). */
921 uint8_t u8RespIntCnt;
922 /** Padding for alignment. */
923 uint8_t au8Padding2[7];
924} HDASTATE;
925/** Pointer to the ICH Intel HD Audio Controller state. */
926typedef HDASTATE *PHDASTATE;
927
928#ifdef VBOX_WITH_AUDIO_HDA_CALLBACKS
929typedef struct HDACALLBACKCTX
930{
931 PHDASTATE pThis;
932 PHDADRIVER pDriver;
933} HDACALLBACKCTX, *PHDACALLBACKCTX;
934#endif
935
936
937/*********************************************************************************************************************************
938* Internal Functions *
939*********************************************************************************************************************************/
940#ifndef VBOX_DEVICE_STRUCT_TESTCASE
941#ifdef IN_RING3
942static FNPDMDEVRESET hdaReset;
943#endif
944
945/** @name Register read/write stubs.
946 * @{
947 */
948static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
949static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
950/** @} */
951
952/** @name Global register set read/write functions.
953 * @{
954 */
955static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
956static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
957static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
958static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
959static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
960static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
961static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
962static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
963static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
964static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
965static int hdaRegWriteINTCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
966static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
967static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
968static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
969/** @} */
970
971/** @name {IOB}SDn write functions.
972 * @{
973 */
974static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
975static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
976static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
977static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
978static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
979static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
980static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
981static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
982static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
983/** @} */
984
985/** @name Generic register read/write functions.
986 * @{
987 */
988static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
989static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
990static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
991#ifdef IN_RING3
992static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
993#endif
994static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
995static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
996static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
997static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
998/** @} */
999
1000/** @name Stream functions.
1001 * @{
1002 */
1003#ifdef IN_RING3
1004static void hdaStreamDestroy(PHDASTATE pThis, PHDASTREAM pStream);
1005static int hdaStreamDoDMA(PHDASTATE pThis, PHDASTREAM pStream, void *pvBuf, uint32_t cbBuf, uint32_t cbToProcess, uint32_t *pcbProcessed);
1006static int hdaStreamEnable(PHDASTATE pThis, PHDASTREAM pStream, bool fEnable);
1007static int hdaStreamUpdate(PHDASTATE pThis, PHDASTREAM pStream);
1008DECLINLINE(uint32_t) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStream, uint32_t u32LPIB);
1009static void hdaStreamLock(PHDASTREAM pStream);
1010static void hdaStreamUnlock(PHDASTREAM pStream);
1011#endif /* IN_RING3 */
1012/** @} */
1013
1014/** @name Async I/O stream functions.
1015 * @{
1016 */
1017#ifdef IN_RING3
1018# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1019static DECLCALLBACK(int) hdaStreamAsyncIOThread(RTTHREAD hThreadSelf, void *pvUser);
1020static int hdaStreamAsyncIOCreate(PHDASTATE pThis, PHDASTREAM pStream);
1021static int hdaStreamAsyncIODestroy(PHDASTATE pThis, PHDASTREAM pStream);
1022static int hdaStreamAsyncIONotify(PHDASTATE pThis, PHDASTREAM pStream);
1023static void hdaStreamAsyncIOLock(PHDASTREAM pStream);
1024static void hdaStreamAsyncIOUnlock(PHDASTREAM pStream);
1025static void hdaStreamAsyncIOEnable(PHDASTREAM pStream, bool fEnable);
1026# endif
1027#endif
1028/** @} */
1029
1030/** @name Stream mapping functions.
1031 * @{
1032 */
1033#ifdef IN_RING3
1034static int hdaStreamMapInit(PHDASTREAMMAPPING pMapping, PPDMAUDIOSTREAMCFG pCfg);
1035static void hdaStreamMapDestroy(PHDASTREAMMAPPING pMapping);
1036static void hdaStreamMapReset(PHDASTREAMMAPPING pMapping);
1037#endif /* IN_RING3 */
1038/** @} */
1039
1040/** @name HDA device functions.
1041 * @{
1042 */
1043#ifdef IN_RING3
1044static void hdaDoTransfers(PHDASTATE pThis);
1045#endif /* IN_RING3 */
1046static int hdaProcessInterrupt(PHDASTATE pThis);
1047/** @} */
1048
1049/** @name BDLE (Buffer Descriptor List Entry) functions.
1050 * @{
1051 */
1052#ifdef IN_RING3
1053static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry);
1054# ifdef LOG_ENABLED
1055static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BaseDMA, uint16_t cBDLE);
1056# endif
1057#endif /* IN_RING3 */
1058/** @} */
1059
1060/** @name Timer functions.
1061 * @{
1062 */
1063#if !defined(VBOX_WITH_AUDIO_HDA_CALLBACKS) && defined(IN_RING3)
1064static void hdaTimerMaybeStart(PHDASTATE pThis);
1065static void hdaTimerMaybeStop(PHDASTATE pThis);
1066static void hdaTimerMain(PHDASTATE pThis);
1067#endif
1068/** @} */
1069
1070
1071/*********************************************************************************************************************************
1072* Global Variables *
1073*********************************************************************************************************************************/
1074
1075/** Offset of the SD0 register map. */
1076#define HDA_REG_DESC_SD0_BASE 0x80
1077
1078/** Turn a short global register name into an memory index and a stringized name. */
1079#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
1080
1081/** Turns a short stream register name into an memory index and a stringized name. */
1082#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
1083
1084/** Same as above for a register *not* stored in memory. */
1085#define HDA_REG_IDX_LOCAL(abbrev) 0, #abbrev
1086
1087/** No register description (RD) flags defined. */
1088#define HDA_RD_FLAG_NONE UINT32_C(0)
1089/** Writes to SD are allowed while RUN bit is set. */
1090#define HDA_RD_FLAG_SD_WRITE_RUN RT_BIT(0)
1091
1092/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
1093#define HDA_REG_MAP_STRM(offset, name) \
1094 /* offset size read mask write mask flags read callback write callback index + abbrev description */ \
1095 /* ------- ------- ---------- ---------- ------------------------- -------------- ----------------- ----------------------------- ----------- */ \
1096 /* Offset 0x80 (SD0) */ \
1097 { offset, 0x00003, 0x00FF001F, 0x00F0001F, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL) , #name " Stream Descriptor Control" }, \
1098 /* Offset 0x83 (SD0) */ \
1099 { offset + 0x3, 0x00001, 0x0000003C, 0x0000001C, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU8 , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS) , #name " Status" }, \
1100 /* Offset 0x84 (SD0) */ \
1101 { offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadLPIB, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
1102 /* Offset 0x88 (SD0) */ \
1103 { offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDCBL , HDA_REG_IDX_STRM(name, CBL) , #name " Cyclic Buffer Length" }, \
1104 /* Offset 0x8C (SD0) */ \
1105 { offset + 0xC, 0x00002, 0x0000FFFF, 0x0000FFFF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDLVI , HDA_REG_IDX_STRM(name, LVI) , #name " Last Valid Index" }, \
1106 /* Reserved: FIFO Watermark. ** @todo Document this! */ \
1107 { offset + 0xE, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
1108 /* Offset 0x90 (SD0) */ \
1109 { offset + 0x10, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
1110 /* Offset 0x92 (SD0) */ \
1111 { offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFMT , HDA_REG_IDX_STRM(name, FMT) , #name " Stream Format" }, \
1112 /* Reserved: 0x94 - 0x98. */ \
1113 /* Offset 0x98 (SD0) */ \
1114 { offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
1115 /* Offset 0x9C (SD0) */ \
1116 { offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
1117
1118/** Defines a single audio stream register set (e.g. OSD0). */
1119#define HDA_REG_MAP_DEF_STREAM(index, name) \
1120 HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
1121
1122/* See 302349 p 6.2. */
1123static const struct HDAREGDESC
1124{
1125 /** Register offset in the register space. */
1126 uint32_t offset;
1127 /** Size in bytes. Registers of size > 4 are in fact tables. */
1128 uint32_t size;
1129 /** Readable bits. */
1130 uint32_t readable;
1131 /** Writable bits. */
1132 uint32_t writable;
1133 /** Register descriptor (RD) flags of type HDA_RD_FLAG_.
1134 * These are used to specify the handling (read/write)
1135 * policy of the register. */
1136 uint32_t fFlags;
1137 /** Read callback. */
1138 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
1139 /** Write callback. */
1140 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
1141 /** Index into the register storage array. */
1142 uint32_t mem_idx;
1143 /** Abbreviated name. */
1144 const char *abbrev;
1145 /** Descripton. */
1146 const char *desc;
1147} g_aHdaRegMap[HDA_NUM_REGS] =
1148
1149{
1150 /* offset size read mask write mask flags read callback write callback index + abbrev */
1151 /*------- ------- ---------- ---------- ----------------- ---------------- ------------------- ------------------------ */
1152 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(GCAP) }, /* Global Capabilities */
1153 { 0x00002, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMIN) }, /* Minor Version */
1154 { 0x00003, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMAJ) }, /* Major Version */
1155 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTPAY) }, /* Output Payload Capabilities */
1156 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INPAY) }, /* Input Payload Capabilities */
1157 { 0x00008, 0x00004, 0x00000103, 0x00000103, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteGCTL , HDA_REG_IDX(GCTL) }, /* Global Control */
1158 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(WAKEEN) }, /* Wake Enable */
1159 { 0x0000e, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteSTATESTS, HDA_REG_IDX(STATESTS) }, /* State Change Status */
1160 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadUnimpl, hdaRegWriteUnimpl , HDA_REG_IDX(GSTS) }, /* Global Status */
1161 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTSTRMPAY) }, /* Output Stream Payload Capability */
1162 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INSTRMPAY) }, /* Input Stream Payload Capability */
1163 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteINTCTL , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */
1164 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */
1165 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadWALCLK, hdaRegWriteUnimpl , HDA_REG_IDX_LOCAL(WALCLK) }, /* Wall Clock Counter */
1166 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */
1167 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
1168 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBUBASE) }, /* CORB Upper Base Address */
1169 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteCORBWP , HDA_REG_IDX(CORBWP) }, /* CORB Write Pointer */
1170 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteCORBRP , HDA_REG_IDX(CORBRP) }, /* CORB Read Pointer */
1171 { 0x0004C, 0x00001, 0x00000003, 0x00000003, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL) }, /* CORB Control */
1172 { 0x0004D, 0x00001, 0x00000001, 0x00000001, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS) }, /* CORB Status */
1173 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(CORBSIZE) }, /* CORB Size */
1174 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBLBASE) }, /* RIRB Lower Base Address */
1175 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBUBASE) }, /* RIRB Upper Base Address */
1176 { 0x00058, 0x00002, 0x000000FF, 0x00008000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteRIRBWP , HDA_REG_IDX(RIRBWP) }, /* RIRB Write Pointer */
1177 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(RINTCNT) }, /* Response Interrupt Count */
1178 { 0x0005C, 0x00001, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteU8 , HDA_REG_IDX(RIRBCTL) }, /* RIRB Control */
1179 { 0x0005D, 0x00001, 0x00000005, 0x00000005, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS) }, /* RIRB Status */
1180 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(RIRBSIZE) }, /* RIRB Size */
1181 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(IC) }, /* Immediate Command */
1182 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(IR) }, /* Immediate Response */
1183 { 0x00068, 0x00002, 0x00000002, 0x00000002, HDA_RD_FLAG_NONE, hdaRegReadIRS , hdaRegWriteIRS , HDA_REG_IDX(IRS) }, /* Immediate Command Status */
1184 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPLBASE) }, /* DMA Position Lower Base */
1185 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPUBASE) }, /* DMA Position Upper Base */
1186 /* 4 Serial Data In (SDI). */
1187 HDA_REG_MAP_DEF_STREAM(0, SD0),
1188 HDA_REG_MAP_DEF_STREAM(1, SD1),
1189 HDA_REG_MAP_DEF_STREAM(2, SD2),
1190 HDA_REG_MAP_DEF_STREAM(3, SD3),
1191 /* 4 Serial Data Out (SDO). */
1192 HDA_REG_MAP_DEF_STREAM(4, SD4),
1193 HDA_REG_MAP_DEF_STREAM(5, SD5),
1194 HDA_REG_MAP_DEF_STREAM(6, SD6),
1195 HDA_REG_MAP_DEF_STREAM(7, SD7)
1196};
1197
1198/**
1199 * HDA register aliases (HDA spec 3.3.45).
1200 * @remarks Sorted by offReg.
1201 */
1202static const struct
1203{
1204 /** The alias register offset. */
1205 uint32_t offReg;
1206 /** The register index. */
1207 int idxAlias;
1208} g_aHdaRegAliases[] =
1209{
1210 { 0x2084, HDA_REG_SD0LPIB },
1211 { 0x20a4, HDA_REG_SD1LPIB },
1212 { 0x20c4, HDA_REG_SD2LPIB },
1213 { 0x20e4, HDA_REG_SD3LPIB },
1214 { 0x2104, HDA_REG_SD4LPIB },
1215 { 0x2124, HDA_REG_SD5LPIB },
1216 { 0x2144, HDA_REG_SD6LPIB },
1217 { 0x2164, HDA_REG_SD7LPIB },
1218};
1219
1220#ifdef IN_RING3
1221/** HDABDLEDESC field descriptors for the v6+ saved state. */
1222static SSMFIELD const g_aSSMBDLEDescFields6[] =
1223{
1224 SSMFIELD_ENTRY(HDABDLEDESC, u64BufAdr),
1225 SSMFIELD_ENTRY(HDABDLEDESC, u32BufSize),
1226 SSMFIELD_ENTRY(HDABDLEDESC, fFlags),
1227 SSMFIELD_ENTRY_TERM()
1228};
1229
1230/** HDABDLESTATE field descriptors for the v6+ saved state. */
1231static SSMFIELD const g_aSSMBDLEStateFields6[] =
1232{
1233 SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
1234 SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
1235 SSMFIELD_ENTRY_OLD(FIFO, 256),
1236 SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
1237 SSMFIELD_ENTRY_TERM()
1238};
1239
1240/** HDASTREAMSTATE field descriptors for the v6+ saved state. */
1241static SSMFIELD const g_aSSMStreamStateFields6[] =
1242{
1243 SSMFIELD_ENTRY_OLD(cBDLE, 2),
1244 SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
1245 SSMFIELD_ENTRY_OLD(fDoStop, 1),
1246 SSMFIELD_ENTRY_OLD(fActive, 1),
1247 SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
1248 SSMFIELD_ENTRY_TERM()
1249};
1250#endif
1251
1252/**
1253 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
1254 */
1255static uint32_t const g_afMasks[5] =
1256{
1257 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
1258};
1259
1260
1261#ifdef IN_RING3
1262/**
1263 * Retrieves the number of bytes of a FIFOW register.
1264 *
1265 * @return Number of bytes of a given FIFOW register.
1266 */
1267DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
1268{
1269 uint32_t cb;
1270 switch (u32RegFIFOW)
1271 {
1272 case HDA_SDFIFOW_8B: cb = 8; break;
1273 case HDA_SDFIFOW_16B: cb = 16; break;
1274 case HDA_SDFIFOW_32B: cb = 32; break;
1275 default: cb = 0; break;
1276 }
1277
1278 Assert(RT_IS_POWER_OF_TWO(cb));
1279 return cb;
1280}
1281
1282
1283DECLINLINE(uint32_t) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStream, uint32_t u32LPIB)
1284{
1285 AssertPtrReturn(pThis, 0);
1286 AssertPtrReturn(pStream, 0);
1287
1288 AssertMsg(u32LPIB <= pStream->u32CBL,
1289 ("[SD%RU8] New LPIB (%RU32) exceeds CBL (%RU32)\n", pStream->u8SD, u32LPIB, pStream->u32CBL));
1290
1291 u32LPIB = RT_MIN(u32LPIB, pStream->u32CBL);
1292
1293 LogFlowFunc(("[SD%RU8]: LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n",
1294 pStream->u8SD, u32LPIB, pThis->fDMAPosition));
1295
1296 /* Update LPIB in any case. */
1297 HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) = u32LPIB;
1298
1299 /* Do we need to tell the current DMA position? */
1300 if (pThis->fDMAPosition)
1301 {
1302 int rc2 = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
1303 (pThis->u64DPBase & DPBASE_ADDR_MASK) + (pStream->u8SD * 2 * sizeof(uint32_t)),
1304 (void *)&u32LPIB, sizeof(uint32_t));
1305 AssertRC(rc2);
1306 }
1307
1308 return u32LPIB;
1309}
1310
1311
1312/**
1313 * Locks an HDA stream for serialized access.
1314 *
1315 * @returns IPRT status code.
1316 * @param pStream HDA stream to lock.
1317 */
1318static void hdaStreamLock(PHDASTREAM pStream)
1319{
1320 AssertPtrReturnVoid(pStream);
1321 int rc2 = RTCritSectEnter(&pStream->State.CritSect);
1322 AssertRC(rc2);
1323}
1324
1325
1326/**
1327 * Unlocks a formerly locked HDA stream.
1328 *
1329 * @returns IPRT status code.
1330 * @param pStream HDA stream to unlock.
1331 */
1332static void hdaStreamUnlock(PHDASTREAM pStream)
1333{
1334 AssertPtrReturnVoid(pStream);
1335 int rc2 = RTCritSectLeave(&pStream->State.CritSect);
1336 AssertRC(rc2);
1337}
1338
1339
1340/**
1341 * Fetches the next BDLE to use for a stream.
1342 *
1343 * @return IPRT status code.
1344 */
1345DECLINLINE(int) hdaStreamGetNextBDLE(PHDASTATE pThis, PHDASTREAM pStream, bool *pfWrapAround)
1346{
1347 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1348 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1349
1350 NOREF(pThis);
1351
1352 Assert(pStream->State.uCurBDLE < pStream->u16LVI + 1);
1353
1354 LogFlowFuncEnter();
1355
1356# ifdef LOG_ENABLED
1357 uint32_t const uOldBDLE = pStream->State.uCurBDLE;
1358# endif
1359
1360 PHDABDLE pBDLE = &pStream->State.BDLE;
1361 bool fWrapAround = false;
1362
1363 AssertMsg(pBDLE->State.u32BufOff == pBDLE->Desc.u32BufSize, ("BDLE not finished yet: %R[bdle]\n", pBDLE));
1364
1365 /*
1366 * Switch to the next BDLE entry and do a wrap around
1367 * if we reached the end of the Buffer Descriptor List (BDL).
1368 */
1369 pStream->State.uCurBDLE++;
1370 if (pStream->State.uCurBDLE == pStream->u16LVI + 1)
1371 {
1372 pStream->State.uCurBDLE = 0;
1373 fWrapAround = true;
1374 }
1375
1376 Assert(pStream->State.uCurBDLE < pStream->u16LVI + 1);
1377
1378 /* Fetch the next BDLE entry. */
1379 int rc = hdaBDLEFetch(pThis, pBDLE, pStream->u64BDLBase, pStream->State.uCurBDLE);
1380 if (RT_SUCCESS(rc))
1381 {
1382 LogFlowFunc(("[SD%RU8]: uOldBDLE=%RU16, uCurBDLE=%RU16, LVI=%RU32, rc=%Rrc, %R[bdle]\n",
1383 pStream->u8SD, uOldBDLE, pStream->State.uCurBDLE, pStream->u16LVI, rc, pBDLE));
1384
1385 if (pfWrapAround)
1386 *pfWrapAround = fWrapAround;
1387 }
1388
1389 return rc;
1390}
1391
1392
1393/**
1394 * Returns the HDA stream of specified stream descriptor number.
1395 *
1396 * @return Pointer to HDA stream, or NULL if none found.
1397 */
1398DECLINLINE(PHDASTREAM) hdaStreamGetFromSD(PHDASTATE pThis, uint8_t uSD)
1399{
1400 AssertPtrReturn(pThis, NULL);
1401 AssertReturn(uSD <= HDA_MAX_STREAMS, NULL);
1402
1403 if (uSD >= HDA_MAX_STREAMS)
1404 {
1405 AssertMsgFailed(("Invalid / non-handled SD%RU8\n", uSD));
1406 return NULL;
1407 }
1408
1409 return &pThis->aStreams[uSD];
1410}
1411
1412
1413/**
1414 * Returns the HDA stream of specified HDA sink.
1415 *
1416 * @return Pointer to HDA stream, or NULL if none found.
1417 */
1418DECLINLINE(PHDASTREAM) hdaSinkGetStream(PHDASTATE pThis, PHDAMIXERSINK pSink)
1419{
1420 AssertPtrReturn(pThis, NULL);
1421 AssertPtrReturn(pSink, NULL);
1422
1423 /** @todo Do something with the channel mapping here? */
1424 return hdaStreamGetFromSD(pThis, pSink->uSD);
1425}
1426
1427
1428/**
1429 * Returns the audio direction of a specified stream descriptor.
1430 *
1431 * The register layout specifies that input streams (SDI) come first,
1432 * followed by the output streams (SDO). So every stream ID below HDA_MAX_SDI
1433 * is an input stream, whereas everything >= HDA_MAX_SDI is an output stream.
1434 *
1435 * Note: SDnFMT register does not provide that information, so we have to judge
1436 * for ourselves.
1437 *
1438 * @return Audio direction.
1439 */
1440DECLINLINE(PDMAUDIODIR) hdaGetDirFromSD(uint8_t uSD)
1441{
1442 AssertReturn(uSD <= HDA_MAX_STREAMS, PDMAUDIODIR_UNKNOWN);
1443
1444 if (uSD < HDA_MAX_SDI)
1445 return PDMAUDIODIR_IN;
1446
1447 return PDMAUDIODIR_OUT;
1448}
1449#endif /* IN_RING3 */
1450
1451
1452static void hdaUpdateINTSTS(PHDASTATE pThis)
1453{
1454 uint32_t intSts = 0;
1455
1456 if (/* Response Overrun Interrupt Status (ROIS) */
1457 HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RIRBOIS)
1458 /* Response Interrupt */
1459 || HDA_REG_FLAG_VALUE(pThis, RIRBSTS, RINTFL)
1460 /* SDIN State Change Status Flags (SCSF) */
1461 || (HDA_REG(pThis, STATESTS) & HDA_STATESTS_SCSF_MASK))
1462 {
1463 intSts |= RT_BIT(30); /* Touch Controller Interrupt Status (CIS). */
1464 }
1465
1466#define HDA_MARK_STREAM(x) \
1467 if ( (INTCTL_SX(pThis, x)) \
1468 && ( (SDSTS(pThis, x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)) \
1469 || (SDSTS(pThis, x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)) \
1470 || (SDSTS(pThis, x) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)) \
1471 ) \
1472 ) \
1473 { \
1474 Log3Func(("[SD%RU8] Marked\n", x)); \
1475 intSts |= RT_BIT(x); \
1476 }
1477
1478 HDA_MARK_STREAM(0);
1479 HDA_MARK_STREAM(1);
1480 HDA_MARK_STREAM(2);
1481 HDA_MARK_STREAM(3);
1482 HDA_MARK_STREAM(4);
1483 HDA_MARK_STREAM(5);
1484 HDA_MARK_STREAM(6);
1485 HDA_MARK_STREAM(7);
1486
1487#undef HDA_MARK_STREAM
1488
1489 if (intSts)
1490 intSts |= RT_BIT(31); /* Touch Global Interrupt Status (GIS). */
1491
1492 HDA_REG(pThis, INTSTS) = intSts;
1493
1494 Log3Func(("INTSTS=%x\n", intSts));
1495}
1496
1497static int hdaProcessInterrupt(PHDASTATE pThis)
1498{
1499 hdaUpdateINTSTS(pThis);
1500
1501 int iLevel = 0;
1502
1503 /* Global Interrupt Status (GIS) touched? */
1504 if (HDA_REG_FLAG_VALUE(pThis, INTSTS, GIS))
1505 iLevel = 1;
1506
1507 Log3Func(("INTCTL=%x, INTSTS=%x, Level=%d\n", HDA_REG(pThis, INTCTL), HDA_REG(pThis, INTSTS), iLevel));
1508
1509 /* Global Interrupt Enable (GIE) set? */
1510 if (HDA_REG_FLAG_VALUE(pThis, INTCTL, GIE))
1511 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, iLevel);
1512
1513 return VINF_SUCCESS;
1514}
1515
1516/**
1517 * Looks up a register at the exact offset given by @a offReg.
1518 *
1519 * @returns Register index on success, -1 if not found.
1520 * @param offReg The register offset.
1521 */
1522static int hdaRegLookup(uint32_t offReg)
1523{
1524 /*
1525 * Aliases.
1526 */
1527 if (offReg >= g_aHdaRegAliases[0].offReg)
1528 {
1529 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1530 if (offReg == g_aHdaRegAliases[i].offReg)
1531 return g_aHdaRegAliases[i].idxAlias;
1532 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1533 return -1;
1534 }
1535
1536 /*
1537 * Binary search the
1538 */
1539 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1540 int idxLow = 0;
1541 for (;;)
1542 {
1543 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1544 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1545 {
1546 if (idxLow == idxMiddle)
1547 break;
1548 idxEnd = idxMiddle;
1549 }
1550 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1551 {
1552 idxLow = idxMiddle + 1;
1553 if (idxLow >= idxEnd)
1554 break;
1555 }
1556 else
1557 return idxMiddle;
1558 }
1559
1560#ifdef RT_STRICT
1561 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1562 Assert(g_aHdaRegMap[i].offset != offReg);
1563#endif
1564 return -1;
1565}
1566
1567/**
1568 * Looks up a register covering the offset given by @a offReg.
1569 *
1570 * @returns Register index on success, -1 if not found.
1571 * @param offReg The register offset.
1572 */
1573static int hdaRegLookupWithin(uint32_t offReg)
1574{
1575 /*
1576 * Aliases.
1577 */
1578 if (offReg >= g_aHdaRegAliases[0].offReg)
1579 {
1580 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1581 {
1582 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1583 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1584 return g_aHdaRegAliases[i].idxAlias;
1585 }
1586 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1587 return -1;
1588 }
1589
1590 /*
1591 * Binary search the register map.
1592 */
1593 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1594 int idxLow = 0;
1595 for (;;)
1596 {
1597 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1598 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1599 {
1600 if (idxLow == idxMiddle)
1601 break;
1602 idxEnd = idxMiddle;
1603 }
1604 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1605 {
1606 idxLow = idxMiddle + 1;
1607 if (idxLow >= idxEnd)
1608 break;
1609 }
1610 else
1611 return idxMiddle;
1612 }
1613
1614#ifdef RT_STRICT
1615 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1616 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1617#endif
1618 return -1;
1619}
1620
1621#ifdef IN_RING3
1622
1623static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1624{
1625 int rc = VINF_SUCCESS;
1626 if (fLocal)
1627 {
1628 Assert((HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA)));
1629 Assert(pThis->u64CORBBase);
1630 AssertPtr(pThis->pu32CorbBuf);
1631 Assert(pThis->cbCorbBuf);
1632
1633 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1634 if (RT_FAILURE(rc))
1635 AssertRCReturn(rc, rc);
1636# ifdef DEBUG_CMD_BUFFER
1637 uint8_t i = 0;
1638 do
1639 {
1640 LogFunc(("CORB%02x: ", i));
1641 uint8_t j = 0;
1642 do
1643 {
1644 const char *pszPrefix;
1645 if ((i + j) == HDA_REG(pThis, CORBRP));
1646 pszPrefix = "[R]";
1647 else if ((i + j) == HDA_REG(pThis, CORBWP));
1648 pszPrefix = "[W]";
1649 else
1650 pszPrefix = " "; /* three spaces */
1651 LogFunc(("%s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
1652 j++;
1653 } while (j < 8);
1654 LogFunc(("\n"));
1655 i += 8;
1656 } while(i != 0);
1657# endif
1658 }
1659 else
1660 {
1661 Assert((HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA)));
1662 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1663 if (RT_FAILURE(rc))
1664 AssertRCReturn(rc, rc);
1665# ifdef DEBUG_CMD_BUFFER
1666 uint8_t i = 0;
1667 do {
1668 LogFunc(("RIRB%02x: ", i));
1669 uint8_t j = 0;
1670 do {
1671 const char *prefix;
1672 if ((i + j) == HDA_REG(pThis, RIRBWP))
1673 prefix = "[W]";
1674 else
1675 prefix = " ";
1676 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1677 } while (++j < 8);
1678 LogFunc(("\n"));
1679 i += 8;
1680 } while (i != 0);
1681# endif
1682 }
1683 return rc;
1684}
1685
1686static int hdaCORBCmdProcess(PHDASTATE pThis)
1687{
1688 int rc = hdaCmdSync(pThis, true);
1689 if (RT_FAILURE(rc))
1690 AssertRCReturn(rc, rc);
1691
1692 uint8_t corbRp = HDA_REG(pThis, CORBRP);
1693 uint8_t corbWp = HDA_REG(pThis, CORBWP);
1694 uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
1695
1696 Assert((corbWp != corbRp));
1697 Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1698
1699 while (corbRp != corbWp)
1700 {
1701 uint64_t uResp;
1702 uint32_t uCmd = pThis->pu32CorbBuf[++corbRp];
1703
1704 int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(uCmd, 0 /* Codec index */), &uResp);
1705 if (RT_FAILURE(rc2))
1706 LogFunc(("Codec lookup failed with rc=%Rrc\n", rc2));
1707
1708 (rirbWp)++;
1709
1710 if ( (uResp & CODEC_RESPONSE_UNSOLICITED)
1711 && !HDA_REG_FLAG_VALUE(pThis, GCTL, UR))
1712 {
1713 LogFunc(("Unexpected unsolicited response\n"));
1714 HDA_REG(pThis, CORBRP) = corbRp;
1715 return rc;
1716 }
1717
1718 pThis->pu64RirbBuf[rirbWp] = uResp;
1719
1720 pThis->u8RespIntCnt++;
1721 if (pThis->u8RespIntCnt == RINTCNT_N(pThis))
1722 break;
1723 }
1724
1725 HDA_REG(pThis, CORBRP) = corbRp;
1726 HDA_REG(pThis, RIRBWP) = rirbWp;
1727
1728 rc = hdaCmdSync(pThis, false);
1729
1730 Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1731
1732 if (HDA_REG_FLAG_VALUE(pThis, RIRBCTL, RIC))
1733 {
1734 HDA_REG(pThis, RIRBSTS) |= HDA_REG_FIELD_FLAG_MASK(RIRBSTS,RINTFL);
1735
1736 pThis->u8RespIntCnt = 0;
1737 rc = hdaProcessInterrupt(pThis);
1738 }
1739
1740 if (RT_FAILURE(rc))
1741 AssertRCReturn(rc, rc);
1742 return rc;
1743}
1744
1745static int hdaStreamCreate(PHDASTATE pThis, PHDASTREAM pStream, uint8_t uSD)
1746{
1747 RT_NOREF(pThis);
1748 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1749 AssertReturn(uSD <= HDA_MAX_STREAMS, VERR_INVALID_PARAMETER);
1750
1751 int rc = RTCritSectInit(&pStream->State.CritSect);
1752 if (RT_SUCCESS(rc))
1753 {
1754 pStream->u8SD = uSD;
1755 pStream->pMixSink = NULL;
1756
1757 pStream->State.fInReset = false;
1758 }
1759
1760 if (RT_SUCCESS(rc))
1761 rc = RTCircBufCreate(&pStream->State.pCircBuf, _4K); /** @todo Make this configurable. */
1762
1763 LogFlowFunc(("uSD=%RU8\n", uSD));
1764 return rc;
1765}
1766
1767static void hdaStreamDestroy(PHDASTATE pThis, PHDASTREAM pStream)
1768{
1769 AssertPtrReturnVoid(pStream);
1770
1771 LogFlowFunc(("[SD%RU8]: Destroying ...\n", pStream->u8SD));
1772
1773 hdaStreamMapDestroy(&pStream->State.Mapping);
1774
1775 int rc2;
1776
1777#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1778 rc2 = hdaStreamAsyncIODestroy(pThis, pStream);
1779 AssertRC(rc2);
1780#else
1781 RT_NOREF(pThis);
1782#endif
1783
1784 rc2 = RTCritSectDelete(&pStream->State.CritSect);
1785 AssertRC(rc2);
1786
1787 if (pStream->State.pCircBuf)
1788 {
1789 RTCircBufDestroy(pStream->State.pCircBuf);
1790 pStream->State.pCircBuf = NULL;
1791 }
1792
1793 LogFlowFuncLeave();
1794}
1795
1796static int hdaStreamInit(PHDASTATE pThis, PHDASTREAM pStream, uint8_t u8SD)
1797{
1798 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1799 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1800
1801 pStream->u8SD = u8SD;
1802 pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
1803 HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
1804 pStream->u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
1805 pStream->u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
1806 pStream->u16FIFOS = HDA_STREAM_REG(pThis, FIFOS, pStream->u8SD) + 1;
1807
1808 RT_ZERO(pStream->State.BDLE);
1809 pStream->State.uCurBDLE = 0;
1810
1811 hdaStreamMapReset(&pStream->State.Mapping);
1812
1813 LogFlowFunc(("[SD%RU8]: DMA @ 0x%x (%RU32 bytes), LVI=%RU16, FIFOS=%RU16\n",
1814 pStream->u8SD, pStream->u64BDLBase, pStream->u32CBL, pStream->u16LVI, pStream->u16FIFOS));
1815
1816# ifdef DEBUG
1817 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
1818 HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
1819 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
1820 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
1821
1822 LogFlowFunc(("\t-> DMA @ 0x%x, LVI=%RU16, CBL=%RU32\n", u64BaseDMA, u16LVI, u32CBL));
1823
1824 hdaBDLEDumpAll(pThis, u64BaseDMA, u16LVI + 1);
1825# endif
1826
1827 return VINF_SUCCESS;
1828}
1829
1830/**
1831 * Resets an HDA stream.
1832 *
1833 * @param pThis HDA state.
1834 * @param pStream HDA stream to reset.
1835 */
1836static void hdaStreamReset(PHDASTATE pThis, PHDASTREAM pStream)
1837{
1838 AssertPtrReturnVoid(pThis);
1839 AssertPtrReturnVoid(pStream);
1840
1841 const uint8_t uSD = pStream->u8SD;
1842
1843# ifdef VBOX_STRICT
1844 AssertReleaseMsg(!RT_BOOL(HDA_STREAM_REG(pThis, CTL, uSD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
1845 ("[SD%RU8] Cannot reset stream while in running state\n", uSD));
1846# endif
1847
1848 LogFunc(("[SD%RU8]: Reset\n", uSD));
1849
1850 /*
1851 * First, reset the internal stream state.
1852 */
1853 RT_ZERO(pStream->State.BDLE);
1854 pStream->State.uCurBDLE = 0;
1855
1856 if (pStream->State.pCircBuf)
1857 RTCircBufReset(pStream->State.pCircBuf);
1858
1859 /*
1860 * Second, initialize the registers.
1861 */
1862 HDA_STREAM_REG(pThis, STS, uSD) = HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY);
1863 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1864 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
1865 HDA_STREAM_REG(pThis, CTL, uSD) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
1866 /*
1867 * ICH6 defines default values (120 bytes for input and 192 bytes for output descriptors) of FIFO size. 18.2.39.
1868 * BUT: Windows guests seem to read the FIFOS but define a DMA region which does not fit to that FIFO size
1869 * (e.g. 1792 bytes DMA region vs. 192 bytes FIFOS).
1870 * This will lead to crackling and corrupted sound -- so define a 256 bytes FIOS for output streams here per default.
1871 */
1872 HDA_STREAM_REG(pThis, FIFOS, uSD) = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? HDA_SDIFIFO_120B : HDA_SDOFIFO_256B;
1873 /* See 18.2.38: Always defaults to 0x4 (32 bytes). */
1874 HDA_STREAM_REG(pThis, FIFOW, uSD) = HDA_SDFIFOW_32B;
1875 HDA_STREAM_REG(pThis, LPIB, uSD) = 0;
1876 HDA_STREAM_REG(pThis, CBL, uSD) = 0;
1877 HDA_STREAM_REG(pThis, LVI, uSD) = 0;
1878 HDA_STREAM_REG(pThis, FMT, uSD) = HDA_SDFMT_MAKE(HDA_SDFMT_TYPE_PCM, HDA_SDFMT_BASE_44KHZ,
1879 HDA_SDFMT_MULT_1X, HDA_SDFMT_DIV_1X, HDA_SDFMT_16_BIT,
1880 HDA_SDFMT_CHAN_STEREO);
1881 HDA_STREAM_REG(pThis, BDPU, uSD) = 0;
1882 HDA_STREAM_REG(pThis, BDPL, uSD) = 0;
1883
1884 int rc2 = hdaStreamInit(pThis, pStream, uSD);
1885 AssertRC(rc2);
1886}
1887
1888/**
1889 * Enables or disables an HDA audio stream.
1890 *
1891 * @returns IPRT status code.
1892 * @param pThis HDA state.
1893 * @param pStream HDA stream to enable or disable.
1894 * @param fEnable Whether to enable or disble the stream.
1895 */
1896static int hdaStreamEnable(PHDASTATE pThis, PHDASTREAM pStream, bool fEnable)
1897{
1898 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1899 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1900
1901 LogFunc(("[SD%RU8]: fEnable=%RTbool, pMixSink=%p\n", pStream->u8SD, fEnable, pStream->pMixSink));
1902
1903 int rc = VINF_SUCCESS;
1904
1905 hdaStreamLock(pStream);
1906
1907#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1908 hdaStreamAsyncIOLock(pStream);
1909 hdaStreamAsyncIOEnable(pStream, fEnable);
1910#endif
1911
1912 if (pStream->pMixSink) /* Stream attached to a sink? */
1913 {
1914 AUDMIXSINKCMD enmCmd = fEnable
1915 ? AUDMIXSINKCMD_ENABLE : AUDMIXSINKCMD_DISABLE;
1916
1917 /* First, enable or disable the stream and the stream's sink, if any. */
1918 if (pStream->pMixSink->pMixSink)
1919 rc = AudioMixerSinkCtl(pStream->pMixSink->pMixSink, enmCmd);
1920 }
1921
1922#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1923 hdaStreamAsyncIOUnlock(pStream);
1924#endif
1925
1926 /* Make sure to leave the lock before (eventually) starting the timer. */
1927 hdaStreamUnlock(pStream);
1928
1929#ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
1930 /* Second, see if we need to start or stop the timer. */
1931 if (!fEnable)
1932 hdaTimerMaybeStop(pThis);
1933 else
1934 hdaTimerMaybeStart(pThis);
1935#endif
1936
1937 LogFunc(("[SD%RU8]: cStreamsActive=%RU8, rc=%Rrc\n", pStream->u8SD, pThis->cStreamsActive, rc));
1938 return rc;
1939}
1940
1941# if defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_AUDIO_HDA_51_SURROUND)
1942static int hdaStreamChannelExtract(PPDMAUDIOSTREAMCHANNEL pChan, const void *pvBuf, size_t cbBuf)
1943{
1944 AssertPtrReturn(pChan, VERR_INVALID_POINTER);
1945 AssertPtrReturn(pvBuf, VERR_INVALID_POINTER);
1946 AssertReturn(cbBuf, VERR_INVALID_PARAMETER);
1947
1948 AssertRelease(pChan->cbOff <= cbBuf);
1949
1950 const uint8_t *pu8Buf = (const uint8_t *)pvBuf;
1951
1952 size_t cbSrc = cbBuf - pChan->cbOff;
1953 const uint8_t *pvSrc = &pu8Buf[pChan->cbOff];
1954
1955 size_t cbDst;
1956 uint8_t *pvDst;
1957 RTCircBufAcquireWriteBlock(pChan->Data.pCircBuf, cbBuf, (void **)&pvDst, &cbDst);
1958
1959 cbSrc = RT_MIN(cbSrc, cbDst);
1960
1961 while (cbSrc)
1962 {
1963 AssertBreak(cbDst >= cbSrc);
1964
1965 /* Enough data for at least one next frame? */
1966 if (cbSrc < pChan->cbFrame)
1967 break;
1968
1969 memcpy(pvDst, pvSrc, pChan->cbFrame);
1970
1971 /* Advance to next channel frame in stream. */
1972 pvSrc += pChan->cbStep;
1973 Assert(cbSrc >= pChan->cbStep);
1974 cbSrc -= pChan->cbStep;
1975
1976 /* Advance destination by one frame. */
1977 pvDst += pChan->cbFrame;
1978 Assert(cbDst >= pChan->cbFrame);
1979 cbDst -= pChan->cbFrame;
1980
1981 /* Adjust offset. */
1982 pChan->cbOff += pChan->cbFrame;
1983 }
1984
1985 RTCircBufReleaseWriteBlock(pChan->Data.pCircBuf, cbDst);
1986
1987 return VINF_SUCCESS;
1988}
1989# endif /* defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_AUDIO_HDA_51_SURROUND) */
1990
1991# if 0 /** @todo hdaStreamChannelAdvance is unused */
1992static int hdaStreamChannelAdvance(PPDMAUDIOSTREAMCHANNEL pChan, size_t cbAdv)
1993{
1994 AssertPtrReturn(pChan, VERR_INVALID_POINTER);
1995
1996 if (!cbAdv)
1997 return VINF_SUCCESS;
1998
1999 return VINF_SUCCESS;
2000}
2001# endif
2002
2003static int hdaStreamChannelDataInit(PPDMAUDIOSTREAMCHANNELDATA pChanData, uint32_t fFlags)
2004{
2005 int rc = RTCircBufCreate(&pChanData->pCircBuf, 256); /** @todo Make this configurable? */
2006 if (RT_SUCCESS(rc))
2007 {
2008 pChanData->fFlags = fFlags;
2009 }
2010
2011 return rc;
2012}
2013
2014/**
2015 * Frees a stream channel data block again.
2016 *
2017 * @param pChanData Pointer to channel data to free.
2018 */
2019static void hdaStreamChannelDataDestroy(PPDMAUDIOSTREAMCHANNELDATA pChanData)
2020{
2021 if (!pChanData)
2022 return;
2023
2024 if (pChanData->pCircBuf)
2025 {
2026 RTCircBufDestroy(pChanData->pCircBuf);
2027 pChanData->pCircBuf = NULL;
2028 }
2029
2030 pChanData->fFlags = PDMAUDIOSTREAMCHANNELDATA_FLAG_NONE;
2031}
2032
2033# if defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_AUDIO_HDA_51_SURROUND)
2034
2035static int hdaStreamChannelAcquireData(PPDMAUDIOSTREAMCHANNELDATA pChanData, void *pvData, size_t *pcbData)
2036{
2037 AssertPtrReturn(pChanData, VERR_INVALID_POINTER);
2038 AssertPtrReturn(pvData, VERR_INVALID_POINTER);
2039 AssertPtrReturn(pcbData, VERR_INVALID_POINTER);
2040
2041 RTCircBufAcquireReadBlock(pChanData->pCircBuf, 256 /** @todo Make this configurarble? */, &pvData, &pChanData->cbAcq);
2042
2043 *pcbData = pChanData->cbAcq;
2044 return VINF_SUCCESS;
2045}
2046
2047static int hdaStreamChannelReleaseData(PPDMAUDIOSTREAMCHANNELDATA pChanData)
2048{
2049 AssertPtrReturn(pChanData, VERR_INVALID_POINTER);
2050 RTCircBufReleaseReadBlock(pChanData->pCircBuf, pChanData->cbAcq);
2051
2052 return VINF_SUCCESS;
2053}
2054
2055# endif /* defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_AUDIO_HDA_51_SURROUND) */
2056
2057# if 0 /* currently unused */
2058static int hdaStreamWaitForStateChange(PHDASTREAM pStream, RTMSINTERVAL msTimeout)
2059{
2060 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
2061
2062 LogFlowFunc(("[SD%RU8]: msTimeout=%RU32\n", pStream->u8SD, msTimeout));
2063 return RTSemEventWait(pStream->State.hStateChangedEvent, msTimeout);
2064}
2065# endif /* currently unused */
2066
2067#endif /* IN_RING3 */
2068
2069/* Register access handlers. */
2070
2071static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2072{
2073 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg);
2074 *pu32Value = 0;
2075 return VINF_SUCCESS;
2076}
2077
2078static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2079{
2080 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2081 return VINF_SUCCESS;
2082}
2083
2084/* U8 */
2085static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2086{
2087 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
2088 return hdaRegReadU32(pThis, iReg, pu32Value);
2089}
2090
2091static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2092{
2093 Assert((u32Value & 0xffffff00) == 0);
2094 return hdaRegWriteU32(pThis, iReg, u32Value);
2095}
2096
2097/* U16 */
2098static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2099{
2100 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
2101 return hdaRegReadU32(pThis, iReg, pu32Value);
2102}
2103
2104static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2105{
2106 Assert((u32Value & 0xffff0000) == 0);
2107 return hdaRegWriteU32(pThis, iReg, u32Value);
2108}
2109
2110/* U24 */
2111static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2112{
2113 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
2114 return hdaRegReadU32(pThis, iReg, pu32Value);
2115}
2116
2117#ifdef IN_RING3
2118static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2119{
2120 Assert((u32Value & 0xff000000) == 0);
2121 return hdaRegWriteU32(pThis, iReg, u32Value);
2122}
2123#endif
2124
2125/* U32 */
2126static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2127{
2128 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2129
2130 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
2131 return VINF_SUCCESS;
2132}
2133
2134static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2135{
2136 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2137
2138 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
2139 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
2140 return VINF_SUCCESS;
2141}
2142
2143static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2144{
2145 RT_NOREF_PV(iReg);
2146
2147 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, RST))
2148 {
2149 /* Set the CRST bit to indicate that we're leaving reset mode. */
2150 HDA_REG(pThis, GCTL) |= HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
2151
2152 if (pThis->fInReset)
2153 {
2154 LogFunc(("Guest leaving HDA reset\n"));
2155 pThis->fInReset = false;
2156 }
2157 }
2158 else
2159 {
2160#ifdef IN_RING3
2161 /* Enter reset state. */
2162 LogFunc(("Guest entering HDA reset with DMA(RIRB:%s, CORB:%s)\n",
2163 HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) ? "on" : "off",
2164 HDA_REG_FLAG_VALUE(pThis, RIRBCTL, DMA) ? "on" : "off"));
2165
2166 /* Clear the CRST bit to indicate that we're in reset state. */
2167 HDA_REG(pThis, GCTL) &= ~HDA_REG_FIELD_FLAG_MASK(GCTL, RST);
2168 pThis->fInReset = true;
2169
2170 hdaReset(pThis->CTX_SUFF(pDevIns));
2171#else
2172 return VINF_IOM_R3_MMIO_WRITE;
2173#endif
2174 }
2175
2176 if (u32Value & HDA_REG_FIELD_FLAG_MASK(GCTL, FSH))
2177 {
2178 /* Flush: GSTS:1 set, see 6.2.6. */
2179 HDA_REG(pThis, GSTS) |= HDA_REG_FIELD_FLAG_MASK(GSTS, FSH); /* Set the flush state. */
2180 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
2181 }
2182 return VINF_SUCCESS;
2183}
2184
2185static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2186{
2187 uint32_t v = HDA_REG_IND(pThis, iReg);
2188 uint32_t nv = u32Value & HDA_STATESTS_SCSF_MASK;
2189
2190 HDA_REG(pThis, STATESTS) &= ~(v & nv); /* Write of 1 clears corresponding bit. */
2191
2192 return hdaProcessInterrupt(pThis);
2193}
2194
2195static int hdaRegWriteINTCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2196{
2197 RT_NOREF(iReg);
2198
2199 int rc;
2200
2201 HDA_REG(pThis, INTCTL) = u32Value;
2202
2203 /* Global Interrupt Enable (GIE) set? */
2204 if (u32Value & HDA_INTCTL_GIE_MASK)
2205 {
2206 rc = hdaProcessInterrupt(pThis);
2207 }
2208 else
2209 {
2210 /** @todo Clear INTSTS's individual stream status bits as well? */
2211
2212 /* Make sure to lower interrupt line, as Global Interrupt Enable (GIE) is disabled. */
2213 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 0 /* iLevel */);
2214
2215 rc = VINF_SUCCESS;
2216 }
2217
2218 return rc;
2219}
2220
2221static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2222{
2223 const uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
2224 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, u8Strm);
2225#ifdef LOG_ENABLED
2226 const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
2227 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32\n", u8Strm, u32LPIB, u32CBL));
2228#endif
2229
2230 *pu32Value = u32LPIB;
2231 return VINF_SUCCESS;
2232}
2233
2234static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2235{
2236 RT_NOREF_PV(iReg);
2237
2238 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
2239 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
2240 - pThis->u64BaseTS, 24, 1000);
2241 LogFlowFunc(("%RU32\n", *pu32Value));
2242 return VINF_SUCCESS;
2243}
2244
2245static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2246{
2247 RT_NOREF_PV(iReg);
2248
2249 if (u32Value & HDA_REG_FIELD_FLAG_MASK(CORBRP, RST))
2250 {
2251 HDA_REG(pThis, CORBRP) = 0;
2252 }
2253#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
2254 else
2255 return hdaRegWriteU8(pThis, iReg, u32Value);
2256#endif
2257 return VINF_SUCCESS;
2258}
2259
2260static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2261{
2262#ifdef IN_RING3
2263 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
2264 AssertRC(rc);
2265 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2266 && HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA) != 0)
2267 {
2268 return hdaCORBCmdProcess(pThis);
2269 }
2270 return rc;
2271#else
2272 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2273 return VINF_IOM_R3_MMIO_WRITE;
2274#endif
2275}
2276
2277static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2278{
2279 RT_NOREF_PV(iReg);
2280
2281 uint32_t v = HDA_REG(pThis, CORBSTS);
2282 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
2283 return VINF_SUCCESS;
2284}
2285
2286static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2287{
2288#ifdef IN_RING3
2289 int rc;
2290 rc = hdaRegWriteU16(pThis, iReg, u32Value);
2291 if (RT_FAILURE(rc))
2292 AssertRCReturn(rc, rc);
2293 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
2294 return VINF_SUCCESS;
2295 if (!HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
2296 return VINF_SUCCESS;
2297 rc = hdaCORBCmdProcess(pThis);
2298 return rc;
2299#else /* !IN_RING3 */
2300 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2301 return VINF_IOM_R3_MMIO_WRITE;
2302#endif /* IN_RING3 */
2303}
2304
2305static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2306{
2307#ifdef IN_RING3
2308 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2309 return VINF_SUCCESS;
2310
2311 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, CBL, iReg));
2312 if (!pStream)
2313 {
2314 LogFunc(("[SD%RU8]: Warning: Changing SDCBL on non-attached stream (0x%x)\n",
2315 HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
2316 return hdaRegWriteU32(pThis, iReg, u32Value);
2317 }
2318
2319 pStream->u32CBL = u32Value;
2320
2321 /* Reset BDLE state. */
2322 RT_ZERO(pStream->State.BDLE);
2323 pStream->State.uCurBDLE = 0;
2324
2325 int rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2326 AssertRC(rc2);
2327
2328 LogFlowFunc(("[SD%RU8]: CBL=%RU32\n", pStream->u8SD, u32Value));
2329
2330 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2331#else /* !IN_RING3 */
2332 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2333 return VINF_IOM_R3_MMIO_WRITE;
2334#endif /* IN_RING3 */
2335}
2336
2337static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2338{
2339#ifdef IN_RING3
2340 /*
2341 * Some guests write too much (that is, 32-bit with the top 8 bit being junk)
2342 * instead of 24-bit required for SDCTL. So just mask this here to be safe.
2343 */
2344 u32Value = (u32Value & 0x00ffffff);
2345
2346 bool fRun = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2347 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
2348
2349 bool fReset = RT_BOOL(u32Value & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
2350 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST));
2351
2352 /* Get the stream descriptor. */
2353 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
2354
2355 LogFunc(("[SD%RU8]: fRun=%RTbool, fInRun=%RTbool, fReset=%RTbool, fInReset=%RTbool, %R[sdctl]\n",
2356 uSD, fRun, fInRun, fReset, fInReset, u32Value));
2357
2358 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2359 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2360
2361 /*
2362 * Extract the stream tag the guest wants to use for this specific
2363 * stream descriptor (SDn). This only can happen if the stream is in a non-running
2364 * state, so we're doing the lookup and assignment here.
2365 *
2366 * So depending on the guest OS, SD3 can use stream tag 4, for example.
2367 */
2368 uint8_t uTag = (u32Value >> HDA_SDCTL_NUM_SHIFT) & HDA_SDCTL_NUM_MASK;
2369 if (uTag > HDA_MAX_TAGS)
2370 {
2371 LogFunc(("[SD%RU8]: Warning: Invalid stream tag %RU8 specified!\n", uSD, uTag));
2372 return hdaRegWriteU24(pThis, iReg, u32Value);
2373 }
2374
2375 PHDATAG pTag = &pThis->aTags[uTag];
2376 AssertPtr(pTag);
2377
2378 LogFunc(("[SD%RU8]: Using stream tag=%RU8\n", uSD, uTag));
2379
2380 /* Assign new values. */
2381 pTag->uTag = uTag;
2382 pTag->pStrm = hdaStreamGetFromSD(pThis, uSD);
2383
2384 PHDASTREAM pStream = pTag->pStrm;
2385 AssertPtr(pStream);
2386
2387 if (fInReset)
2388 {
2389 Assert(!fReset);
2390 Assert(!fInRun && !fRun);
2391
2392 /* Exit reset state. */
2393 ASMAtomicXchgBool(&pStream->State.fInReset, false);
2394
2395 /* Report that we're done resetting this stream by clearing SRST. */
2396 HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST);
2397
2398 LogFunc(("[SD%RU8]: Reset exit\n", uSD));
2399 }
2400 else if (fReset)
2401 {
2402 /* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
2403 Assert(!fInRun && !fRun);
2404
2405 LogFunc(("[SD%RU8]: Reset enter\n", pStream->u8SD));
2406
2407 /* Enter reset state. */
2408 Assert(ASMAtomicReadBool(&pStream->State.fInReset) == false); /* No nested calls. */
2409 ASMAtomicXchgBool(&pStream->State.fInReset, true);
2410
2411 hdaStreamLock(pStream);
2412
2413 hdaStreamReset(pThis, pStream);
2414
2415 hdaStreamUnlock(pStream);
2416 }
2417 else
2418 {
2419 /*
2420 * We enter here to change DMA states only.
2421 */
2422 if (fInRun != fRun)
2423 {
2424 Assert(!fReset && !fInReset);
2425 LogFunc(("[SD%RU8]: State changed (fRun=%RTbool)\n", pStream->u8SD, fRun));
2426
2427 if (fRun)
2428 {
2429 /* Make sure to first fetch the current BDLE before enabling the stream below. */
2430 int rc2 = hdaBDLEFetch(pThis, &pStream->State.BDLE, pStream->u64BDLBase, pStream->State.uCurBDLE);
2431 AssertRC(rc2);
2432 }
2433
2434 hdaStreamEnable(pThis, pStream, fRun /* fEnable */);
2435 }
2436 }
2437
2438 int rc2 = hdaRegWriteU24(pThis, iReg, u32Value);
2439 AssertRC(rc2);
2440
2441 /* Make sure to handle interrupts here as well. */
2442 hdaProcessInterrupt(pThis);
2443
2444 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2445#else /* !IN_RING3 */
2446 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2447 return VINF_IOM_R3_MMIO_WRITE;
2448#endif /* IN_RING3 */
2449}
2450
2451static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2452{
2453 uint32_t v = HDA_REG_IND(pThis, iReg);
2454
2455 /* Clear (zero) FIFOE, DESE and BCIS bits when writing 1 to it (6.2.33). */
2456 HDA_REG_IND(pThis, iReg) &= ~(u32Value & v);
2457
2458 LogFunc(("SDSTS 0x%x -> 0x%x\n", v, HDA_REG_IND(pThis, iReg)));
2459
2460 hdaProcessInterrupt(pThis);
2461 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2462}
2463
2464static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2465{
2466#ifdef IN_RING3
2467 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2468 return VINF_SUCCESS;
2469
2470 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, LVI, iReg);
2471
2472 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, uSD);
2473 if (!pStream)
2474 {
2475 AssertMsgFailed(("[SD%RU8]: Warning: Changing SDLVI on non-attached stream (0x%x)\n", uSD, u32Value));
2476 return hdaRegWriteU16(pThis, iReg, u32Value);
2477 }
2478
2479 /** @todo Validate LVI. */
2480 pStream->u16LVI = u32Value;
2481 LogFunc(("[SD%RU8]: Updating LVI to %RU16\n", uSD, pStream->u16LVI));
2482
2483 /* Reset BDLE state. */
2484 RT_ZERO(pStream->State.BDLE);
2485 pStream->State.uCurBDLE = 0;
2486
2487 int rc2 = hdaRegWriteU16(pThis, iReg, u32Value);
2488 AssertRC(rc2);
2489
2490 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2491#else /* !IN_RING3 */
2492 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2493 return VINF_IOM_R3_MMIO_WRITE;
2494#endif /* IN_RING3 */
2495}
2496
2497static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2498{
2499#ifdef IN_RING3
2500 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg);
2501
2502 if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_IN) /* FIFOW for input streams only. */
2503 {
2504 LogRel(("HDA: Warning: Guest tried to write read-only FIFOW to output stream #%RU8, ignoring\n", uSD));
2505 return VINF_SUCCESS;
2506 }
2507
2508 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg));
2509 if (!pStream)
2510 {
2511 AssertMsgFailed(("[SD%RU8]: Warning: Changing FIFOW on non-attached stream (0x%x)\n", uSD, u32Value));
2512 return hdaRegWriteU16(pThis, iReg, u32Value);
2513 }
2514
2515 uint32_t u32FIFOW = 0;
2516
2517 switch (u32Value)
2518 {
2519 case HDA_SDFIFOW_8B:
2520 case HDA_SDFIFOW_16B:
2521 case HDA_SDFIFOW_32B:
2522 u32FIFOW = u32Value;
2523 break;
2524 default:
2525 LogRel(("HDA: Warning: Guest tried write unsupported FIFOW (0x%x) to stream #%RU8, defaulting to 32 bytes\n",
2526 u32Value, uSD));
2527 AssertFailed();
2528 u32FIFOW = HDA_SDFIFOW_32B;
2529 break;
2530 }
2531
2532 if (u32FIFOW)
2533 {
2534 pStream->u16FIFOW = hdaSDFIFOWToBytes(u32FIFOW);
2535 LogFunc(("[SD%RU8]: Updating FIFOW to %RU32 bytes\n", uSD, pStream->u16FIFOW));
2536
2537 int rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOW);
2538 AssertRC(rc2);
2539 }
2540
2541 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2542#else /* !IN_RING3 */
2543 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2544 return VINF_IOM_R3_MMIO_WRITE;
2545#endif /* IN_RING3 */
2546}
2547
2548/**
2549 * @note This method could be called for changing value on Output Streams only (ICH6 datasheet 18.2.39).
2550 */
2551static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2552{
2553#ifdef IN_RING3
2554 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOS, iReg);
2555
2556 if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_OUT) /* FIFOS for output streams only. */
2557 {
2558 LogRel(("HDA: Warning: Guest tried to write read-only FIFOS to input stream #%RU8, ignoring\n", uSD));
2559 return VINF_SUCCESS;
2560 }
2561
2562 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, uSD);
2563 if (!pStream)
2564 {
2565 AssertMsgFailed(("[SD%RU8]: Warning: Changing FIFOS on non-attached stream (0x%x)\n", uSD, u32Value));
2566 return hdaRegWriteU16(pThis, iReg, u32Value);
2567 }
2568
2569 uint32_t u32FIFOS = 0;
2570
2571 switch(u32Value)
2572 {
2573 case HDA_SDOFIFO_16B:
2574 case HDA_SDOFIFO_32B:
2575 case HDA_SDOFIFO_64B:
2576 case HDA_SDOFIFO_128B:
2577 case HDA_SDOFIFO_192B:
2578 case HDA_SDOFIFO_256B:
2579 u32FIFOS = u32Value;
2580 break;
2581
2582 default:
2583 LogRel(("HDA: Warning: Guest tried write unsupported FIFOS (0x%x) to stream #%RU8, defaulting to 192 bytes\n",
2584 u32Value, uSD));
2585 AssertFailed();
2586 u32FIFOS = HDA_SDOFIFO_192B;
2587 break;
2588 }
2589
2590 if (u32FIFOS)
2591 {
2592 pStream->u16FIFOS = u32FIFOS + 1;
2593 LogFunc(("[SD%RU8]: Updating FIFOS to %RU32 bytes\n", uSD, pStream->u16FIFOS));
2594
2595 int rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOS);
2596 AssertRC(rc2);
2597 }
2598
2599 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2600#else /* !IN_RING3 */
2601 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2602 return VINF_IOM_R3_MMIO_WRITE;
2603#endif /* IN_RING3 */
2604}
2605
2606#ifdef IN_RING3
2607static int hdaSDFMTToStrmCfg(uint32_t u32SDFMT, PPDMAUDIOSTREAMCFG pStrmCfg)
2608{
2609 AssertPtrReturn(pStrmCfg, VERR_INVALID_POINTER);
2610
2611# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
2612
2613 int rc = VINF_SUCCESS;
2614
2615 uint32_t u32Hz = EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BASE_RATE_MASK, HDA_SDFMT_BASE_RATE_SHIFT)
2616 ? 44100 : 48000;
2617 uint32_t u32HzMult = 1;
2618 uint32_t u32HzDiv = 1;
2619
2620 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
2621 {
2622 case 0: u32HzMult = 1; break;
2623 case 1: u32HzMult = 2; break;
2624 case 2: u32HzMult = 3; break;
2625 case 3: u32HzMult = 4; break;
2626 default:
2627 LogFunc(("Unsupported multiplier %x\n",
2628 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
2629 rc = VERR_NOT_SUPPORTED;
2630 break;
2631 }
2632 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
2633 {
2634 case 0: u32HzDiv = 1; break;
2635 case 1: u32HzDiv = 2; break;
2636 case 2: u32HzDiv = 3; break;
2637 case 3: u32HzDiv = 4; break;
2638 case 4: u32HzDiv = 5; break;
2639 case 5: u32HzDiv = 6; break;
2640 case 6: u32HzDiv = 7; break;
2641 case 7: u32HzDiv = 8; break;
2642 default:
2643 LogFunc(("Unsupported divisor %x\n",
2644 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
2645 rc = VERR_NOT_SUPPORTED;
2646 break;
2647 }
2648
2649 PDMAUDIOFMT enmFmt;
2650 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
2651 {
2652 case 0:
2653 enmFmt = PDMAUDIOFMT_S8;
2654 break;
2655 case 1:
2656 enmFmt = PDMAUDIOFMT_S16;
2657 break;
2658 case 4:
2659 enmFmt = PDMAUDIOFMT_S32;
2660 break;
2661 default:
2662 AssertMsgFailed(("Unsupported bits per sample %x\n",
2663 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
2664 enmFmt = PDMAUDIOFMT_INVALID;
2665 rc = VERR_NOT_SUPPORTED;
2666 break;
2667 }
2668
2669 if (RT_SUCCESS(rc))
2670 {
2671 pStrmCfg->uHz = u32Hz * u32HzMult / u32HzDiv;
2672 pStrmCfg->cChannels = (u32SDFMT & 0xf) + 1;
2673 pStrmCfg->enmFormat = enmFmt;
2674 pStrmCfg->enmEndianness = PDMAUDIOHOSTENDIANNESS;
2675 }
2676
2677# undef EXTRACT_VALUE
2678 return rc;
2679}
2680
2681static int hdaAddStreamOut(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
2682{
2683 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2684 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2685
2686 AssertReturn(pCfg->enmDir == PDMAUDIODIR_OUT, VERR_INVALID_PARAMETER);
2687
2688 LogFlowFunc(("Stream=%s\n", pCfg->szName));
2689
2690 int rc = VINF_SUCCESS;
2691
2692 bool fUseFront = true; /* Always use front out by default. */
2693#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2694 bool fUseRear;
2695 bool fUseCenter;
2696 bool fUseLFE;
2697
2698 fUseRear = fUseCenter = fUseLFE = false;
2699
2700 /*
2701 * Use commonly used setups for speaker configurations.
2702 */
2703
2704 /** @todo Make the following configurable through mixer API and/or CFGM? */
2705 switch (pCfg->cChannels)
2706 {
2707 case 3: /* 2.1: Front (Stereo) + LFE. */
2708 {
2709 fUseLFE = true;
2710 break;
2711 }
2712
2713 case 4: /* Quadrophonic: Front (Stereo) + Rear (Stereo). */
2714 {
2715 fUseRear = true;
2716 break;
2717 }
2718
2719 case 5: /* 4.1: Front (Stereo) + Rear (Stereo) + LFE. */
2720 {
2721 fUseRear = true;
2722 fUseLFE = true;
2723 break;
2724 }
2725
2726 case 6: /* 5.1: Front (Stereo) + Rear (Stereo) + Center/LFE. */
2727 {
2728 fUseRear = true;
2729 fUseCenter = true;
2730 fUseLFE = true;
2731 break;
2732 }
2733
2734 default: /* Unknown; fall back to 2 front channels (stereo). */
2735 {
2736 rc = VERR_NOT_SUPPORTED;
2737 break;
2738 }
2739 }
2740#else /* !VBOX_WITH_AUDIO_HDA_51_SURROUND */
2741 /* Only support mono or stereo channels. */
2742 if ( pCfg->cChannels != 1 /* Mono */
2743 && pCfg->cChannels != 2 /* Stereo */)
2744 {
2745 rc = VERR_NOT_SUPPORTED;
2746 }
2747#endif
2748
2749 if (rc == VERR_NOT_SUPPORTED)
2750 {
2751 LogRel(("HDA: Unsupported channel count (%RU8), falling back to stereo channels\n", pCfg->cChannels));
2752 pCfg->cChannels = 2;
2753
2754 rc = VINF_SUCCESS;
2755 }
2756
2757 do
2758 {
2759 if (RT_FAILURE(rc))
2760 break;
2761
2762 if (fUseFront)
2763 {
2764 RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Front");
2765 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_FRONT;
2766 pCfg->cChannels = 2;
2767
2768 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT);
2769 if (RT_SUCCESS(rc))
2770 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT, pCfg);
2771 }
2772
2773#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2774 if ( RT_SUCCESS(rc)
2775 && (fUseCenter || fUseLFE))
2776 {
2777 RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Center/LFE");
2778 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_CENTER_LFE;
2779 pCfg->cChannels = (fUseCenter && fUseLFE) ? 2 : 1;
2780
2781 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE);
2782 if (RT_SUCCESS(rc))
2783 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE, pCfg);
2784 }
2785
2786 if ( RT_SUCCESS(rc)
2787 && fUseRear)
2788 {
2789 RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Rear");
2790 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_REAR;
2791 pCfg->cChannels = 2;
2792
2793 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR);
2794 if (RT_SUCCESS(rc))
2795 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR, pCfg);
2796 }
2797#endif /* VBOX_WITH_AUDIO_HDA_51_SURROUND */
2798
2799 } while (0);
2800
2801 LogFlowFuncLeaveRC(rc);
2802 return rc;
2803}
2804
2805static int hdaAddStreamIn(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
2806{
2807 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2808 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2809
2810 AssertReturn(pCfg->enmDir == PDMAUDIODIR_IN, VERR_INVALID_PARAMETER);
2811
2812 LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Source));
2813
2814 int rc;
2815
2816 switch (pCfg->DestSource.Source)
2817 {
2818 case PDMAUDIORECSOURCE_LINE:
2819 {
2820 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN);
2821 if (RT_SUCCESS(rc))
2822 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN, pCfg);
2823 break;
2824 }
2825#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2826 case PDMAUDIORECSOURCE_MIC:
2827 {
2828 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN);
2829 if (RT_SUCCESS(rc))
2830 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN, pCfg);
2831 break;
2832 }
2833#endif
2834 default:
2835 rc = VERR_NOT_SUPPORTED;
2836 break;
2837 }
2838
2839 LogFlowFuncLeaveRC(rc);
2840 return rc;
2841}
2842#endif /* IN_RING3 */
2843
2844static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2845{
2846#ifdef IN_RING3
2847 PDMAUDIOSTREAMCFG strmCfg;
2848 RT_ZERO(strmCfg);
2849
2850 int rc = hdaSDFMTToStrmCfg(u32Value, &strmCfg);
2851 if (RT_FAILURE(rc))
2852 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2853
2854 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FMT, iReg));
2855 if (!pStream)
2856 {
2857 LogFunc(("[SD%RU8]: Warning: Changing SDFMT on non-attached stream (0x%x)\n",
2858 HDA_SD_NUM_FROM_REG(pThis, FMT, iReg), u32Value));
2859 return hdaRegWriteU16(pThis, iReg, u32Value);
2860 }
2861
2862 LogFunc(("[SD%RU8]: Hz=%RU32, Channels=%RU8, enmFmt=%RU32\n",
2863 pStream->u8SD, strmCfg.uHz, strmCfg.cChannels, strmCfg.enmFormat));
2864
2865 /* Set audio direction. */
2866 strmCfg.enmDir = hdaGetDirFromSD(pStream->u8SD);
2867 switch (strmCfg.enmDir)
2868 {
2869 case PDMAUDIODIR_IN:
2870# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2871# error "Implement me!"
2872# else
2873 strmCfg.DestSource.Source = PDMAUDIORECSOURCE_LINE;
2874 RTStrCopy(strmCfg.szName, sizeof(strmCfg.szName), "Line In");
2875# endif
2876 break;
2877
2878 case PDMAUDIODIR_OUT:
2879 /* Destination(s) will be set in hdaAddStreamOut(),
2880 * based on the channels / stream layout. */
2881 break;
2882
2883 default:
2884 rc = VERR_NOT_SUPPORTED;
2885 break;
2886 }
2887
2888#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2889 if (RT_SUCCESS(rc))
2890 {
2891 rc = hdaStreamAsyncIOCreate(pThis, pStream);
2892 AssertRC(rc);
2893 }
2894#endif
2895
2896 /*
2897 * Initialize the stream mapping in any case, regardless if
2898 * we support surround audio or not. This is needed to handle
2899 * the supported channels within a single audio stream, e.g. mono/stereo.
2900 *
2901 * In other words, the stream mapping *always* knowns the real
2902 * number of channels in a single audio stream.
2903 */
2904 if (RT_SUCCESS(rc))
2905 {
2906 rc = hdaStreamMapInit(&pStream->State.Mapping, &strmCfg);
2907 AssertRC(rc);
2908 }
2909
2910 if (RT_SUCCESS(rc))
2911 {
2912 PHDADRIVER pDrv;
2913 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2914 {
2915 int rc2;
2916 switch (strmCfg.enmDir)
2917 {
2918 case PDMAUDIODIR_OUT:
2919 rc2 = hdaAddStreamOut(pThis, &strmCfg);
2920 break;
2921
2922 case PDMAUDIODIR_IN:
2923 rc2 = hdaAddStreamIn(pThis, &strmCfg);
2924 break;
2925
2926 default:
2927 rc2 = VERR_NOT_SUPPORTED;
2928 AssertFailed();
2929 break;
2930 }
2931
2932 if ( RT_FAILURE(rc2)
2933 && (pDrv->Flags & PDMAUDIODRVFLAGS_PRIMARY)) /* We only care about primary drivers here, the rest may fail. */
2934 {
2935 if (RT_SUCCESS(rc))
2936 rc = rc2;
2937 /* Keep going. */
2938 }
2939 }
2940
2941 /* If (re-)opening the stream by the codec above failed, don't write the new
2942 * format to the register so that the guest is aware it didn't work. */
2943 if (RT_SUCCESS(rc))
2944 {
2945 rc = hdaRegWriteU16(pThis, iReg, u32Value);
2946 AssertRC(rc);
2947 }
2948 else
2949 LogFunc(("[SD%RU8]: (Re-)Opening stream failed with rc=%Rrc\n", pStream->u8SD, rc));
2950 }
2951
2952 return VINF_SUCCESS; /* Never return failure. */
2953#else /* !IN_RING3 */
2954 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2955 return VINF_IOM_R3_MMIO_WRITE;
2956#endif
2957}
2958
2959/* Note: Will be called for both, BDPL and BDPU, registers. */
2960DECLINLINE(int) hdaRegWriteSDBDPX(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value, uint8_t uSD)
2961{
2962#ifdef IN_RING3
2963 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2964 return VINF_SUCCESS;
2965
2966 int rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2967 AssertRC(rc2);
2968
2969 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, uSD);
2970 if (!pStream)
2971 return VINF_SUCCESS;
2972
2973 /* Update BDL base. */
2974 pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, uSD),
2975 HDA_STREAM_REG(pThis, BDPU, uSD));
2976 AssertMsg(pStream->u64BDLBase, ("BDL base invalid\n"));
2977
2978 /* Reset BDLE state. */
2979 RT_ZERO(pStream->State.BDLE);
2980 pStream->State.uCurBDLE = 0;
2981
2982 LogFlowFunc(("[SD%RU8]: BDLBase=0x%x\n", pStream->u8SD, pStream->u64BDLBase));
2983
2984 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2985#else /* !IN_RING3 */
2986 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value); RT_NOREF_PV(uSD);
2987 return VINF_IOM_R3_MMIO_WRITE;
2988#endif /* IN_RING3 */
2989}
2990
2991static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2992{
2993 return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPL, iReg));
2994}
2995
2996static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2997{
2998 return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPU, iReg));
2999}
3000
3001static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
3002{
3003 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
3004 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
3005 || HDA_REG_FLAG_VALUE(pThis, CORBCTL, DMA))
3006 {
3007 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
3008 }
3009
3010 return hdaRegReadU32(pThis, iReg, pu32Value);
3011}
3012
3013static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3014{
3015 RT_NOREF_PV(iReg);
3016
3017 /*
3018 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
3019 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
3020 */
3021 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, ICB)
3022 && !HDA_REG_FLAG_VALUE(pThis, IRS, ICB))
3023 {
3024#ifdef IN_RING3
3025 uint32_t uCmd = HDA_REG(pThis, IC);
3026
3027 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
3028 {
3029 /*
3030 * 3.4.3: Defines behavior of immediate Command status register.
3031 */
3032 LogRel(("HDA: Guest attempted process immediate verb (%x) with active CORB\n", uCmd));
3033 return VINF_SUCCESS;
3034 }
3035
3036 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy */
3037
3038 uint64_t uResp;
3039 int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec,
3040 HDA_CODEC_CMD(uCmd, 0 /* LUN */), &uResp);
3041 if (RT_FAILURE(rc2))
3042 LogFunc(("Codec lookup failed with rc2=%Rrc\n", rc2));
3043
3044 HDA_REG(pThis, IR) = (uint32_t)uResp; /** @todo r=andy Do we need a 64-bit response? */
3045 HDA_REG(pThis, IRS) = HDA_REG_FIELD_FLAG_MASK(IRS, IRV); /* result is ready */
3046 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, ICB); /* busy is clear */
3047 return VINF_SUCCESS;
3048#else /* !IN_RING3 */
3049 return VINF_IOM_R3_MMIO_WRITE;
3050#endif /* !IN_RING3 */
3051 }
3052
3053 /*
3054 * Once the guest read the response, it should clean the IRV bit of the IRS register.
3055 */
3056 if ( u32Value & HDA_REG_FIELD_FLAG_MASK(IRS, IRV)
3057 && HDA_REG_FLAG_VALUE(pThis, IRS, IRV))
3058 HDA_REG(pThis, IRS) &= ~HDA_REG_FIELD_FLAG_MASK(IRS, IRV);
3059 return VINF_SUCCESS;
3060}
3061
3062static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3063{
3064 RT_NOREF_PV(iReg);
3065
3066 if (u32Value & HDA_REG_FIELD_FLAG_MASK(RIRBWP, RST))
3067 HDA_REG(pThis, RIRBWP) = 0;
3068
3069 /* The remaining bits are O, see 6.2.22. */
3070 return VINF_SUCCESS;
3071}
3072
3073static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3074{
3075 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
3076 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
3077 if (RT_FAILURE(rc))
3078 AssertRCReturn(rc, rc);
3079
3080 switch(iReg)
3081 {
3082 case HDA_REG_CORBLBASE:
3083 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
3084 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
3085 break;
3086 case HDA_REG_CORBUBASE:
3087 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
3088 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3089 break;
3090 case HDA_REG_RIRBLBASE:
3091 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
3092 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
3093 break;
3094 case HDA_REG_RIRBUBASE:
3095 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
3096 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3097 break;
3098 case HDA_REG_DPLBASE:
3099 {
3100 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
3101 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
3102
3103 /* Also make sure to handle the DMA position enable bit. */
3104 pThis->fDMAPosition = RT_BOOL(pThis->u64DPBase & RT_BIT_64(0));
3105 LogRel2(("HDA: %s DMA position buffer\n", pThis->fDMAPosition ? "Enabled" : "Disabled"));
3106 break;
3107 }
3108 case HDA_REG_DPUBASE:
3109 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
3110 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
3111 break;
3112 default:
3113 AssertMsgFailed(("Invalid index\n"));
3114 break;
3115 }
3116
3117 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
3118 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
3119 return rc;
3120}
3121
3122static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3123{
3124 RT_NOREF_PV(iReg);
3125
3126 uint8_t v = HDA_REG(pThis, RIRBSTS);
3127 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
3128
3129 return hdaProcessInterrupt(pThis);
3130}
3131
3132#ifdef IN_RING3
3133#ifdef LOG_ENABLED
3134static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BDLBase, uint16_t cBDLE)
3135{
3136 LogFlowFunc(("BDLEs @ 0x%x (%RU16):\n", u64BDLBase, cBDLE));
3137 if (!u64BDLBase)
3138 return;
3139
3140 uint32_t cbBDLE = 0;
3141 for (uint16_t i = 0; i < cBDLE; i++)
3142 {
3143 HDABDLEDESC bd;
3144 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BDLBase + i * sizeof(HDABDLEDESC), &bd, sizeof(bd));
3145
3146 LogFunc(("\t#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
3147 i, bd.u64BufAdr, bd.u32BufSize, bd.fFlags & HDA_BDLE_FLAG_IOC));
3148
3149 cbBDLE += bd.u32BufSize;
3150 }
3151
3152 LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
3153
3154 if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
3155 return;
3156
3157 LogFlowFunc(("DMA counters:\n"));
3158
3159 for (int i = 0; i < cBDLE; i++)
3160 {
3161 uint32_t uDMACnt;
3162 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
3163 &uDMACnt, sizeof(uDMACnt));
3164
3165 LogFlowFunc(("\t#%03d DMA @ 0x%x\n", i , uDMACnt));
3166 }
3167}
3168#endif
3169
3170/**
3171 * Fetches a Bundle Descriptor List Entry (BDLE) from the DMA engine.
3172 *
3173 * @param pThis Pointer to HDA state.
3174 * @param pBDLE Where to store the fetched result.
3175 * @param u64BaseDMA Address base of DMA engine to use.
3176 * @param u16Entry BDLE entry to fetch.
3177 */
3178static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry)
3179{
3180 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3181 AssertPtrReturn(pBDLE, VERR_INVALID_POINTER);
3182 AssertReturn(u64BaseDMA, VERR_INVALID_PARAMETER);
3183
3184 if (!u64BaseDMA)
3185 {
3186 LogRel2(("HDA: Unable to fetch BDLE #%RU16 - no base DMA address set (yet)\n", u16Entry));
3187 return VERR_NOT_FOUND;
3188 }
3189 /** @todo Compare u16Entry with LVI. */
3190
3191 int rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + u16Entry * sizeof(HDABDLEDESC),
3192 &pBDLE->Desc, sizeof(pBDLE->Desc));
3193 if (RT_FAILURE(rc))
3194 return rc;
3195
3196 /* Set internal state. */
3197 pBDLE->State.u32BufOff = 0;
3198 pBDLE->State.u32BDLIndex = u16Entry;
3199
3200 return VINF_SUCCESS;
3201}
3202
3203/**
3204 * Returns the number of outstanding stream data bytes which need to be processed
3205 * by the DMA engine assigned to this stream.
3206 *
3207 * @return Number of bytes for the DMA engine to process.
3208 */
3209DECLINLINE(uint32_t) hdaStreamGetTransferSize(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbMax)
3210{
3211 AssertPtrReturn(pThis, 0);
3212 AssertPtrReturn(pStream, 0);
3213 AssertReturn (cbMax, 0);
3214
3215 PHDABDLE pBDLE = &pStream->State.BDLE;
3216
3217 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3218 Assert(u32LPIB <= pStream->u32CBL);
3219
3220 /* Do we have space left in the CBL at all? */
3221 uint32_t cbData = pStream->u32CBL - u32LPIB;
3222
3223 /* Limit to the available free space of the current BDLE. */
3224 cbData = RT_MIN(cbData, pBDLE->Desc.u32BufSize - pBDLE->State.u32BufOff);
3225
3226 /* Make sure we only transfer as many bytes as requested. */
3227 cbData = RT_MIN(cbData, cbMax);
3228
3229 if (pBDLE->State.cbBelowFIFOW)
3230 {
3231 /* Are we not going to reach (or exceed) the FIFO watermark yet with the data to copy?
3232 * No need to read data from DMA then. */
3233 if (cbData > pBDLE->State.cbBelowFIFOW)
3234 {
3235 /* Subtract the amount of bytes that still would fit in the stream's FIFO
3236 * and therefore do not need to be processed by DMA. */
3237 cbData -= pBDLE->State.cbBelowFIFOW;
3238 }
3239 }
3240
3241 AssertMsg((cbData % 2 == 0), ("Transfer size invalid: %RU32\n", cbData));
3242
3243 Log3Func(("[SD%RU8]: CBL=%RU32, LPIB=%RU32, FIFOS=%RU16, cbData=%RU32, %R[bdle]\n", pStream->u8SD,
3244 pStream->u32CBL, HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), pStream->u16FIFOS,
3245 cbData, pBDLE));
3246
3247 return cbData;
3248}
3249
3250DECLINLINE(void) hdaBDLEUpdate(PHDABDLE pBDLE, uint32_t cbData, uint32_t cbProcessed)
3251{
3252 AssertPtrReturnVoid(pBDLE);
3253
3254 if (!cbData || !cbProcessed)
3255 return;
3256
3257 Assert(pBDLE->Desc.u32BufSize >= cbProcessed);
3258
3259 /* Fewer than cbBelowFIFOW bytes were copied.
3260 * Probably we need to move the buffer, but it is rather hard to imagine a situation
3261 * where it might happen. */
3262 AssertMsg((cbProcessed == pBDLE->State.cbBelowFIFOW + cbData), /* we assume that we write the entire buffer including unreported bytes */
3263 ("cbProcessed=%RU32 != pBDLE->State.cbBelowFIFOW=%RU32 + cbData=%RU32\n",
3264 cbProcessed, pBDLE->State.cbBelowFIFOW, cbData));
3265
3266#if 0
3267 if ( pBDLE->State.cbBelowFIFOW
3268 && pBDLE->State.cbBelowFIFOW <= cbWritten)
3269 {
3270 LogFlowFunc(("BDLE(cbUnderFifoW:%RU32, off:%RU32, size:%RU32)\n",
3271 pBDLE->State.cbBelowFIFOW, pBDLE->State.u32BufOff, pBDLE->Desc.u32BufSize));
3272 }
3273#endif
3274
3275 pBDLE->State.cbBelowFIFOW -= RT_MIN(pBDLE->State.cbBelowFIFOW, cbProcessed);
3276 Assert(pBDLE->State.cbBelowFIFOW == 0);
3277
3278 /* We always increment the position of DMA buffer counter because we're always reading
3279 * into an intermediate buffer. */
3280 Assert(pBDLE->Desc.u32BufSize >= (pBDLE->State.u32BufOff + cbProcessed));
3281 pBDLE->State.u32BufOff += cbProcessed;
3282
3283 LogFlowFunc(("cbData=%RU32, cbProcessed=%RU32, %R[bdle]\n", cbData, cbProcessed, pBDLE));
3284}
3285
3286#ifdef IN_RING3
3287/**
3288 * Initializes a stream mapping structure according to the given stream configuration.
3289 *
3290 * @return IPRT status code.
3291 * @param pMapping Pointer to mapping to initialize.
3292 * @param pCfg Pointer to stream configuration to use.
3293 */
3294static int hdaStreamMapInit(PHDASTREAMMAPPING pMapping, PPDMAUDIOSTREAMCFG pCfg)
3295{
3296 AssertPtrReturn(pMapping, VERR_INVALID_POINTER);
3297 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3298
3299 AssertReturn(pCfg->cChannels, VERR_INVALID_PARAMETER);
3300
3301 hdaStreamMapReset(pMapping);
3302
3303 pMapping->paChannels = (PPDMAUDIOSTREAMCHANNEL)RTMemAlloc(sizeof(PDMAUDIOSTREAMCHANNEL) * pCfg->cChannels);
3304 if (!pMapping->paChannels)
3305 return VERR_NO_MEMORY;
3306
3307 PDMAUDIOPCMPROPS Props;
3308 int rc = DrvAudioHlpStreamCfgToProps(pCfg, &Props);
3309 if (RT_FAILURE(rc))
3310 return rc;
3311
3312 Assert(RT_IS_POWER_OF_TWO(Props.cBits));
3313
3314 /** @todo We assume all channels in a stream have the same format. */
3315 PPDMAUDIOSTREAMCHANNEL pChan = pMapping->paChannels;
3316 for (uint8_t i = 0; i < pCfg->cChannels; i++)
3317 {
3318 pChan->uChannel = i;
3319 pChan->cbStep = (Props.cBits / 2);
3320 pChan->cbFrame = pChan->cbStep * pCfg->cChannels;
3321 pChan->cbFirst = i * pChan->cbStep;
3322 pChan->cbOff = pChan->cbFirst;
3323
3324 int rc2 = hdaStreamChannelDataInit(&pChan->Data, PDMAUDIOSTREAMCHANNELDATA_FLAG_NONE);
3325 if (RT_SUCCESS(rc))
3326 rc = rc2;
3327
3328 if (RT_FAILURE(rc))
3329 break;
3330
3331 pChan++;
3332 }
3333
3334 if ( RT_SUCCESS(rc)
3335 /* Create circular buffer if not created yet. */
3336 && !pMapping->pCircBuf)
3337 {
3338 rc = RTCircBufCreate(&pMapping->pCircBuf, _4K); /** @todo Make size configurable? */
3339 }
3340
3341 if (RT_SUCCESS(rc))
3342 {
3343 pMapping->cChannels = pCfg->cChannels;
3344#ifdef VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT
3345 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_INTERLEAVED;
3346#else
3347 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
3348#endif
3349 }
3350
3351 return rc;
3352}
3353
3354/**
3355 * Destroys a given stream mapping.
3356 *
3357 * @param pMapping Pointer to mapping to destroy.
3358 */
3359static void hdaStreamMapDestroy(PHDASTREAMMAPPING pMapping)
3360{
3361 hdaStreamMapReset(pMapping);
3362
3363 if (pMapping->pCircBuf)
3364 {
3365 RTCircBufDestroy(pMapping->pCircBuf);
3366 pMapping->pCircBuf = NULL;
3367 }
3368}
3369
3370/**
3371 * Resets a given stream mapping.
3372 *
3373 * @param pMapping Pointer to mapping to reset.
3374 */
3375static void hdaStreamMapReset(PHDASTREAMMAPPING pMapping)
3376{
3377 AssertPtrReturnVoid(pMapping);
3378
3379 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_UNKNOWN;
3380
3381 if (pMapping->cChannels)
3382 {
3383 for (uint8_t i = 0; i < pMapping->cChannels; i++)
3384 hdaStreamChannelDataDestroy(&pMapping->paChannels[i].Data);
3385
3386 AssertPtr(pMapping->paChannels);
3387 RTMemFree(pMapping->paChannels);
3388 pMapping->paChannels = NULL;
3389
3390 pMapping->cChannels = 0;
3391 }
3392}
3393#endif /* IN_RING3 */
3394
3395DECLINLINE(bool) hdaStreamNeedsNextBDLE(PHDASTATE pThis, PHDASTREAM pStream)
3396{
3397 AssertPtrReturn(pThis, false);
3398 AssertPtrReturn(pStream, false);
3399
3400 PHDABDLE pBDLE = &pStream->State.BDLE;
3401 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3402
3403 /* Did we reach the CBL (Cyclic Buffer List) limit? */
3404 bool fCBLLimitReached = u32LPIB >= pStream->u32CBL;
3405
3406 /* Do we need to use the next BDLE entry? Either because we reached
3407 * the CBL limit or our internal DMA buffer is full. */
3408 bool fNeedsNextBDLE = ( fCBLLimitReached
3409 || (pBDLE->State.u32BufOff >= pBDLE->Desc.u32BufSize));
3410
3411 Assert(u32LPIB <= pStream->u32CBL);
3412 Assert(pBDLE->State.u32BufOff <= pBDLE->Desc.u32BufSize);
3413
3414 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32, fCBLLimitReached=%RTbool, fNeedsNextBDLE=%RTbool, %R[bdle]\n",
3415 pStream->u8SD, u32LPIB, pStream->u32CBL, fCBLLimitReached, fNeedsNextBDLE, pBDLE));
3416
3417 return fNeedsNextBDLE;
3418}
3419
3420DECLINLINE(void) hdaStreamTransferUpdate(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbInc)
3421{
3422 AssertPtrReturnVoid(pThis);
3423 AssertPtrReturnVoid(pStream);
3424
3425 if (!cbInc) /* Nothing to do? Bail out early. */
3426 return;
3427
3428 /*
3429 * If we're below the FIFO watermark (SDFIFOW), it's expected that HDA
3430 * doesn't fetch anything via DMA, so just update LPIB.
3431 * (ICH6 datasheet 18.2.38).
3432 */
3433 PHDABDLE pBDLE = &pStream->State.BDLE;
3434 if (pBDLE->State.cbBelowFIFOW == 0) /* Did we hit (or exceed) the watermark? */
3435 {
3436 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) + cbInc;
3437
3438 Log3Func(("[SD%RU8]: LPIB: %RU32 -> %RU32, CBL=%RU32\n",
3439 pStream->u8SD, HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), u32LPIB, pStream->u32CBL));
3440
3441 hdaStreamUpdateLPIB(pThis, pStream, u32LPIB);
3442 }
3443}
3444
3445static bool hdaBDLEIsComplete(PHDABDLE pBDLE, bool *pfInterrupt)
3446{
3447 AssertPtrReturn(pBDLE, true);
3448
3449 bool fInterrupt = false;
3450 bool fIsComplete = false;
3451
3452 /* Check if the current BDLE entry is complete (full). */
3453 if (pBDLE->State.u32BufOff >= pBDLE->Desc.u32BufSize)
3454 {
3455 Assert(pBDLE->State.u32BufOff <= pBDLE->Desc.u32BufSize);
3456
3457 if (/* IOC (Interrupt On Completion) bit set? */
3458 pBDLE->Desc.fFlags & HDA_BDLE_FLAG_IOC
3459 /* All data put into the DMA FIFO? */
3460 && pBDLE->State.cbBelowFIFOW == 0
3461 )
3462 {
3463 fInterrupt = true;
3464 }
3465
3466 fIsComplete = true;
3467 }
3468
3469 if (pfInterrupt)
3470 *pfInterrupt = fInterrupt;
3471
3472 LogFlowFunc(("%R[bdle] fIsComplete=%RTbool, fInterrupt=%RTbool\n", pBDLE, fIsComplete, fInterrupt));
3473
3474 return fIsComplete;
3475}
3476
3477/**
3478 * Retrieves a corresponding sink for a given mixer control.
3479 * Returns NULL if no sink is found.
3480 *
3481 * @return PHDAMIXERSINK
3482 * @param pThis HDA state.
3483 * @param enmMixerCtl Mixer control to get the corresponding sink for.
3484 */
3485static PHDAMIXERSINK hdaMixerControlToSink(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
3486{
3487 PHDAMIXERSINK pSink;
3488
3489 switch (enmMixerCtl)
3490 {
3491 case PDMAUDIOMIXERCTL_VOLUME_MASTER:
3492 /* Fall through is intentional. */
3493 case PDMAUDIOMIXERCTL_FRONT:
3494 pSink = &pThis->SinkFront;
3495 break;
3496#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3497 case PDMAUDIOMIXERCTL_CENTER_LFE:
3498 pSink = &pThis->SinkCenterLFE;
3499 break;
3500 case PDMAUDIOMIXERCTL_REAR:
3501 pSink = &pThis->SinkRear;
3502 break;
3503#endif
3504 case PDMAUDIOMIXERCTL_LINE_IN:
3505 pSink = &pThis->SinkLineIn;
3506 break;
3507#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3508 case PDMAUDIOMIXERCTL_MIC_IN:
3509 pSink = &pThis->SinkMicIn;
3510 break;
3511#endif
3512 default:
3513 pSink = NULL;
3514 AssertMsgFailed(("Unhandled mixer control\n"));
3515 break;
3516 }
3517
3518 return pSink;
3519}
3520
3521static DECLCALLBACK(int) hdaMixerAddStream(PHDASTATE pThis, PHDAMIXERSINK pSink, PPDMAUDIOSTREAMCFG pCfg)
3522{
3523 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3524 AssertPtrReturn(pSink, VERR_INVALID_POINTER);
3525 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3526
3527 LogFunc(("Sink=%s, Stream=%s\n", pSink->pMixSink->pszName, pCfg->szName));
3528
3529 /* Update the sink's format. */
3530 PDMAUDIOPCMPROPS PCMProps;
3531 int rc = DrvAudioHlpStreamCfgToProps(pCfg, &PCMProps);
3532 if (RT_SUCCESS(rc))
3533 rc = AudioMixerSinkSetFormat(pSink->pMixSink, &PCMProps);
3534
3535 if (RT_FAILURE(rc))
3536 return rc;
3537
3538 PHDADRIVER pDrv;
3539 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3540 {
3541 int rc2 = VINF_SUCCESS;
3542 PHDADRIVERSTREAM pDrvStream = NULL;
3543
3544 PPDMAUDIOSTREAMCFG pStreamCfg = (PPDMAUDIOSTREAMCFG)RTMemDup(pCfg, sizeof(PDMAUDIOSTREAMCFG));
3545 if (!pStreamCfg)
3546 {
3547 rc = VERR_NO_MEMORY;
3548 break;
3549 }
3550
3551 /* Include the driver's LUN in the stream name for easier identification. */
3552 RTStrPrintf(pStreamCfg->szName, RT_ELEMENTS(pStreamCfg->szName), "[LUN#%RU8] %s", pDrv->uLUN, pCfg->szName);
3553
3554 if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
3555 {
3556 LogFunc(("enmRecSource=%d\n", pStreamCfg->DestSource.Source));
3557
3558 switch (pStreamCfg->DestSource.Source)
3559 {
3560 case PDMAUDIORECSOURCE_LINE:
3561 pDrvStream = &pDrv->LineIn;
3562 break;
3563#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3564 case PDMAUDIORECSOURCE_MIC:
3565 pDrvStream = &pDrv->MicIn;
3566 break;
3567#endif
3568 default:
3569 rc2 = VERR_NOT_SUPPORTED;
3570 break;
3571 }
3572 }
3573 else if (pStreamCfg->enmDir == PDMAUDIODIR_OUT)
3574 {
3575 LogFunc(("enmPlaybackDest=%d\n", pStreamCfg->DestSource.Dest));
3576
3577 switch (pStreamCfg->DestSource.Dest)
3578 {
3579 case PDMAUDIOPLAYBACKDEST_FRONT:
3580 pDrvStream = &pDrv->Front;
3581 break;
3582#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3583 case PDMAUDIOPLAYBACKDEST_CENTER_LFE:
3584 pDrvStream = &pDrv->CenterLFE;
3585 break;
3586 case PDMAUDIOPLAYBACKDEST_REAR:
3587 pDrvStream = &pDrv->Rear;
3588 break;
3589#endif
3590 default:
3591 rc2 = VERR_NOT_SUPPORTED;
3592 break;
3593 }
3594 }
3595 else
3596 rc2 = VERR_NOT_SUPPORTED;
3597
3598 if (RT_SUCCESS(rc2))
3599 {
3600 AssertPtr(pDrvStream);
3601
3602 AudioMixerSinkRemoveStream(pSink->pMixSink, pDrvStream->pMixStrm);
3603
3604 AudioMixerStreamDestroy(pDrvStream->pMixStrm);
3605 pDrvStream->pMixStrm = NULL;
3606
3607 PAUDMIXSTREAM pMixStrm;
3608 rc2 = AudioMixerSinkCreateStream(pSink->pMixSink, pDrv->pConnector, pStreamCfg, 0 /* fFlags */, &pMixStrm);
3609 if (RT_SUCCESS(rc2))
3610 {
3611 rc2 = AudioMixerSinkAddStream(pSink->pMixSink, pMixStrm);
3612 LogFlowFunc(("LUN#%RU8: Added \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName , rc2));
3613 }
3614
3615 if (RT_SUCCESS(rc2))
3616 pDrvStream->pMixStrm = pMixStrm;
3617 }
3618
3619 if (RT_SUCCESS(rc))
3620 rc = rc2;
3621
3622 if (pStreamCfg)
3623 {
3624 RTMemFree(pStreamCfg);
3625 pStreamCfg = NULL;
3626 }
3627 }
3628
3629 LogFlowFuncLeaveRC(rc);
3630 return rc;
3631}
3632
3633/**
3634 * Adds a new audio stream to a specific mixer control.
3635 * Depending on the mixer control the stream then gets assigned to one of the internal
3636 * mixer sinks, which in turn then handle the mixing of all connected streams to that sink.
3637 *
3638 * @return IPRT status code.
3639 * @param pThis HDA state.
3640 * @param enmMixerCtl Mixer control to assign new stream to.
3641 * @param pCfg Stream configuration for the new stream.
3642 */
3643static DECLCALLBACK(int) hdaMixerAddStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOSTREAMCFG pCfg)
3644{
3645 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3646 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3647
3648 int rc;
3649
3650 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3651 if (pSink)
3652 {
3653 rc = hdaMixerAddStream(pThis, pSink, pCfg);
3654
3655 AssertPtr(pSink->pMixSink);
3656 LogFlowFunc(("Sink=%s, enmMixerCtl=%d\n", pSink->pMixSink->pszName, enmMixerCtl));
3657 }
3658 else
3659 rc = VERR_NOT_FOUND;
3660
3661 LogFlowFuncLeaveRC(rc);
3662 return rc;
3663}
3664
3665/**
3666 * Removes a specified mixer control from the HDA's mixer.
3667 *
3668 * @return IPRT status code.
3669 * @param pThis HDA state.
3670 * @param enmMixerCtl Mixer control to remove.
3671 *
3672 * @remarks Can be called as a callback by the HDA codec.
3673 */
3674static DECLCALLBACK(int) hdaMixerRemoveStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
3675{
3676 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3677
3678 int rc;
3679
3680 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3681 if (pSink)
3682 {
3683 PHDADRIVER pDrv;
3684 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3685 {
3686 PAUDMIXSTREAM pMixStream = NULL;
3687 switch (enmMixerCtl)
3688 {
3689 /*
3690 * Input.
3691 */
3692 case PDMAUDIOMIXERCTL_LINE_IN:
3693 pMixStream = pDrv->LineIn.pMixStrm;
3694 pDrv->LineIn.pMixStrm = NULL;
3695 break;
3696#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3697 case PDMAUDIOMIXERCTL_MIC_IN:
3698 pMixStream = pDrv->MicIn.pMixStrm;
3699 pDrv->MicIn.pMixStrm = NULL;
3700 break;
3701#endif
3702 /*
3703 * Output.
3704 */
3705 case PDMAUDIOMIXERCTL_FRONT:
3706 pMixStream = pDrv->Front.pMixStrm;
3707 pDrv->Front.pMixStrm = NULL;
3708 break;
3709#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3710 case PDMAUDIOMIXERCTL_CENTER_LFE:
3711 pMixStream = pDrv->CenterLFE.pMixStrm;
3712 pDrv->CenterLFE.pMixStrm = NULL;
3713 break;
3714 case PDMAUDIOMIXERCTL_REAR:
3715 pMixStream = pDrv->Rear.pMixStrm;
3716 pDrv->Rear.pMixStrm = NULL;
3717 break;
3718#endif
3719 default:
3720 AssertMsgFailed(("Mixer control %d not implemented\n", enmMixerCtl));
3721 break;
3722 }
3723
3724 if (pMixStream)
3725 {
3726 AudioMixerSinkRemoveStream(pSink->pMixSink, pMixStream);
3727 AudioMixerStreamDestroy(pMixStream);
3728
3729 pMixStream = NULL;
3730 }
3731 }
3732
3733 AudioMixerSinkRemoveAllStreams(pSink->pMixSink);
3734 rc = VINF_SUCCESS;
3735 }
3736 else
3737 rc = VERR_NOT_FOUND;
3738
3739 LogFlowFunc(("enmMixerCtl=%d, rc=%Rrc\n", enmMixerCtl, rc));
3740 return rc;
3741}
3742
3743/**
3744 * Sets a SDn stream number and channel to a particular mixer control.
3745 *
3746 * @returns IPRT status code.
3747 * @param pThis HDA State.
3748 * @param enmMixerCtl Mixer control to set SD stream number and channel for.
3749 * @param uSD SD stream number (number + 1) to set. Set to 0 for unassign.
3750 * @param uChannel Channel to set. Only valid if a valid SD stream number is specified.
3751 *
3752 * @remarks Can be called as a callback by the HDA codec.
3753 */
3754static DECLCALLBACK(int) hdaMixerSetStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, uint8_t uSD, uint8_t uChannel)
3755{
3756 LogFlowFunc(("enmMixerCtl=%RU32, uSD=%RU8, uChannel=%RU8\n", enmMixerCtl, uSD, uChannel));
3757
3758 if (uSD == 0) /* Stream number 0 is reserved. */
3759 {
3760 LogFlowFunc(("Invalid SDn (%RU8) number for mixer control %d, ignoring\n", uSD, enmMixerCtl));
3761 return VINF_SUCCESS;
3762 }
3763 /* uChannel is optional. */
3764
3765 /* SDn0 starts as 1. */
3766 Assert(uSD);
3767 uSD--;
3768
3769 int rc;
3770
3771 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3772 if (pSink)
3773 {
3774 if ( (uSD < HDA_MAX_SDI)
3775 && AudioMixerSinkGetDir(pSink->pMixSink) == AUDMIXSINKDIR_OUTPUT)
3776 {
3777 uSD += HDA_MAX_SDI;
3778 }
3779
3780 LogFlowFunc(("%s: Setting to stream ID=%RU8, channel=%RU8, enmMixerCtl=%RU32\n",
3781 pSink->pMixSink->pszName, uSD, uChannel, enmMixerCtl));
3782
3783 Assert(uSD < HDA_MAX_STREAMS);
3784
3785 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, uSD);
3786 if (pStream)
3787 {
3788 hdaStreamLock(pStream);
3789
3790 pSink->uSD = uSD;
3791 pSink->uChannel = uChannel;
3792 pStream->pMixSink = pSink;
3793
3794 hdaStreamUnlock(pStream);
3795
3796 rc = VINF_SUCCESS;
3797 }
3798 else
3799 {
3800 LogRel(("HDA: Guest wanted to assign invalid stream ID=%RU8 (channel %RU8) to mixer control %RU32, skipping\n",
3801 uSD, uChannel, enmMixerCtl));
3802 rc = VERR_INVALID_PARAMETER;
3803 }
3804 }
3805 else
3806 rc = VERR_NOT_FOUND;
3807
3808 LogFlowFuncLeaveRC(rc);
3809 return rc;
3810}
3811
3812/**
3813 * Sets the volume of a specified mixer control.
3814 *
3815 * @return IPRT status code.
3816 * @param pThis HDA State.
3817 * @param enmMixerCtl Mixer control to set volume for.
3818 * @param pVol Pointer to volume data to set.
3819 *
3820 * @remarks Can be called as a callback by the HDA codec.
3821 */
3822static DECLCALLBACK(int) hdaMixerSetVolume(PHDASTATE pThis,
3823 PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOVOLUME pVol)
3824{
3825 int rc;
3826
3827 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3828 if (pSink)
3829 {
3830 /* Set the volume.
3831 * We assume that the codec already converted it to the correct range. */
3832 rc = AudioMixerSinkSetVolume(pSink->pMixSink, pVol);
3833 }
3834 else
3835 rc = VERR_NOT_FOUND;
3836
3837 LogFlowFuncLeaveRC(rc);
3838 return rc;
3839}
3840
3841#ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
3842/**
3843 * Starts the internal audio device timer (if not started yet).
3844 *
3845 * @param pThis HDA state.
3846 */
3847static void hdaTimerMaybeStart(PHDASTATE pThis)
3848{
3849 LogFlowFuncEnter();
3850
3851 if (!pThis->pTimer)
3852 return;
3853
3854 pThis->cStreamsActive++;
3855
3856 /* Only start the timer at the first active stream. */
3857 if (pThis->cStreamsActive == 1)
3858 {
3859 LogRel2(("HDA: Starting transfers\n"));
3860
3861 /* Set timer flag. */
3862 ASMAtomicXchgBool(&pThis->fTimerActive, true);
3863
3864 /* Update current time timestamp. */
3865 pThis->uTimerTS = TMTimerGet(pThis->pTimer);
3866
3867 /* Start transfers. */
3868 hdaTimerMain(pThis);
3869 }
3870}
3871
3872/**
3873 * Stops the internal audio device timer.
3874 *
3875 * @param pThis HDA state.
3876 */
3877static void hdaTimerStop(PHDASTATE pThis)
3878{
3879 LogFlowFuncEnter();
3880
3881 /* Set timer flag. */
3882 ASMAtomicXchgBool(&pThis->fTimerActive, false);
3883}
3884
3885/**
3886 * Decreases the active HDA streams count by one and
3887 * then checks if the internal audio device timer can be
3888 * stopped.
3889 *
3890 * @param pThis HDA state.
3891 */
3892static void hdaTimerMaybeStop(PHDASTATE pThis)
3893{
3894 LogFlowFuncEnter();
3895
3896 if (!pThis->pTimer)
3897 return;
3898
3899 if (pThis->cStreamsActive) /* Disable can be called mupltiple times. */
3900 {
3901 pThis->cStreamsActive--;
3902
3903 if (pThis->cStreamsActive == 0)
3904 hdaTimerStop(pThis);
3905 }
3906}
3907
3908/**
3909 * Main routine for the device timer.
3910 *
3911 * @returns IPRT status code.
3912 * @param pThis HDA state.
3913 */
3914static void hdaTimerMain(PHDASTATE pThis)
3915{
3916 AssertPtrReturnVoid(pThis);
3917
3918 STAM_PROFILE_START(&pThis->StatTimer, a);
3919
3920 uint64_t cTicksNow = TMTimerGet(pThis->pTimer);
3921
3922 /* Update current time timestamp. */
3923 pThis->uTimerTS = cTicksNow;
3924
3925 /* Flag indicating whether to kick the timer again for a
3926 * new data processing round. */
3927 bool fKickTimer = false;
3928
3929 hdaDoTransfers(pThis);
3930
3931 /* Do we need to kick the timer again? */
3932 if ( AudioMixerSinkIsActive(pThis->SinkFront.pMixSink)
3933#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3934 || AudioMixerSinkIsActive(pThis->SinkCenterLFE.pMixSink)
3935 || AudioMixerSinkIsActive(pThis->SinkRear.pMixSink)
3936#endif
3937 || AudioMixerSinkIsActive(pThis->SinkLineIn.pMixSink)
3938#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3939 || AudioMixerSinkIsActive(pThis->SinkMicIn.pMixSink)
3940#endif
3941 )
3942 {
3943 fKickTimer = true;
3944 }
3945
3946 pThis->uTimerMS = RTTimeMilliTS();
3947
3948 if ( ASMAtomicReadBool(&pThis->fTimerActive)
3949 || fKickTimer)
3950 {
3951 /* Kick the timer again. */
3952 uint64_t cTicks = pThis->cTimerTicks;
3953 /** @todo adjust cTicks down by now much cbOutMin represents. */
3954 TMTimerSet(pThis->pTimer, cTicksNow + cTicks);
3955 }
3956 else
3957 LogRel2(("HDA: Stopping transfers\n"));
3958
3959 STAM_PROFILE_STOP(&pThis->StatTimer, a);
3960}
3961
3962/**
3963 * Timer callback which handles the audio data transfers on a periodic basis.
3964 *
3965 * @param pDevIns Device instance.
3966 * @param pTimer Timer which was used when calling this.
3967 * @param pvUser User argument as PHDASTATE.
3968 */
3969static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3970{
3971 RT_NOREF(pDevIns, pTimer);
3972
3973 PHDASTATE pThis = (PHDASTATE)pvUser;
3974 Assert(pThis == PDMINS_2_DATA(pDevIns, PHDASTATE));
3975 AssertPtr(pThis);
3976
3977 hdaTimerMain(pThis);
3978}
3979
3980#else /* VBOX_WITH_AUDIO_HDA_CALLBACKS */
3981
3982static DECLCALLBACK(int) hdaCallbackInput(PDMAUDIOCBTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
3983{
3984 Assert(enmType == PDMAUDIOCALLBACKTYPE_INPUT);
3985 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
3986 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
3987 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
3988 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
3989
3990 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
3991 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
3992
3993 PPDMAUDIOCBDATA_DATA_INPUT pData = (PPDMAUDIOCBDATA_DATA_INPUT)pvUser;
3994 AssertReturn(cbUser == sizeof(PDMAUDIOCBDATA_DATA_INPUT), VERR_INVALID_PARAMETER);
3995
3996 return hdaStreamDoDMA(pCtx->pThis, PI_INDEX, UINT32_MAX, &pData->cbOutRead);
3997}
3998
3999static DECLCALLBACK(int) hdaCallbackOutput(PDMAUDIOCBTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
4000{
4001 Assert(enmType == PDMAUDIOCALLBACKTYPE_OUTPUT);
4002 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
4003 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
4004 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
4005 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
4006
4007 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
4008 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
4009
4010 PPDMAUDIOCBDATA_DATA_OUTPUT pData = (PPDMAUDIOCBDATA_DATA_OUTPUT)pvUser;
4011 AssertReturn(cbUser == sizeof(PDMAUDIOCBDATA_DATA_OUTPUT), VERR_INVALID_PARAMETER);
4012
4013 PHDASTATE pThis = pCtx->pThis;
4014
4015 int rc = hdaStreamDoDMA(pCtx->pThis, PO_INDEX, UINT32_MAX, &pData->cbOutWritten);
4016 if ( RT_SUCCESS(rc)
4017 && pData->cbOutWritten)
4018 {
4019 PHDADRIVER pDrv;
4020 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
4021 {
4022 uint32_t cSamplesPlayed;
4023 int rc2 = pDrv->pConnector->pfnPlay(pDrv->pConnector, &cSamplesPlayed);
4024 LogFlowFunc(("LUN#%RU8: cSamplesPlayed=%RU32, rc=%Rrc\n", pDrv->uLUN, cSamplesPlayed, rc2));
4025 }
4026 }
4027}
4028#endif /* VBOX_WITH_AUDIO_HDA_CALLBACKS */
4029
4030/**
4031 * Main routine to perform the actual audio data transfers from the HDA streams
4032 * to the backend(s) and vice versa.
4033 *
4034 * @param pThis HDA state.
4035 */
4036static void hdaDoTransfers(PHDASTATE pThis)
4037{
4038 PHDASTREAM pStreamLineIn = hdaSinkGetStream(pThis, &pThis->SinkLineIn);
4039#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
4040 PHDASTREAM pStreamMicIn = hdaSinkGetStream(pThis, &pThis->SinkMicIn);
4041#endif
4042 PHDASTREAM pStreamFront = hdaSinkGetStream(pThis, &pThis->SinkFront);
4043#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
4044 /** @todo See note below. */
4045#endif
4046
4047 hdaStreamUpdate(pThis, pStreamLineIn);
4048#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
4049 hdaStreamUpdate(pThis, pStreamMicIn);
4050#endif
4051 hdaStreamUpdate(pThis, pStreamFront);
4052
4053
4054#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
4055 int rc2 = AudioMixerSinkUpdate(pThis->SinkCenterLFE.pMixSink);
4056 AssertRC(rc2);
4057
4058 rc2 = AudioMixerSinkUpdate(pThis->SinkRear.pMixSink);
4059 AssertRC(rc2);
4060 /** @todo Check for stream interleaving and only call hdaStreamDoDMA() if required! */
4061
4062 /*
4063 * Only call hdaTransfer if CenterLFE and/or Rear are on different SDs,
4064 * otherwise we have to use the interleaved streams support for getting the data
4065 * out of the Front sink (depending on the mapping layout).
4066 */
4067#endif
4068}
4069
4070#ifdef DEBUG_andy
4071# define HDA_DEBUG_DMA
4072#endif
4073
4074/**
4075 * Does a single DMA transfer for a specific HDA stream (SDI/SDO).
4076 * This either can be a read or write operation, depending on the HDA stream.
4077 *
4078 * @returns IPRT status code.
4079 * @param pThis HDA state.
4080 * @param pStream HDA stream to do the DMA transfer for.
4081 * @param pvBuf Pointer to buffer data to write data to / read data from.
4082 * @param cbBuf Size of buffer (in bytes).
4083 * @param cbToProcess Size (in bytes) to transfer (read/write).
4084 * @param pcbProcessed Size (in bytes) transferred (read/written). Optional.
4085 */
4086static int hdaStreamDoDMA(PHDASTATE pThis, PHDASTREAM pStream, void *pvBuf, uint32_t cbBuf,
4087 uint32_t cbToProcess, uint32_t *pcbProcessed)
4088{
4089 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
4090 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
4091 AssertPtrReturn(pvBuf, VERR_INVALID_POINTER);
4092 AssertReturn(cbBuf >= cbToProcess, VERR_INVALID_PARAMETER);
4093 /* pcbProcessed is optional. */
4094
4095 if (ASMAtomicReadBool(&pThis->fInReset)) /* HDA controller in reset mode? Bail out. */
4096 {
4097 if (pcbProcessed)
4098 *pcbProcessed = 0;
4099 return VINF_SUCCESS;
4100 }
4101
4102 bool fProceed = true;
4103
4104 Log3Func(("[SD%RU8] %R[sdsts] cbToProcess=%RU32\n",
4105 pStream->u8SD, HDA_STREAM_REG(pThis, STS, pStream->u8SD), cbToProcess));
4106
4107 /* Is the stream not in a running state currently? */
4108 if (!(HDA_STREAM_REG(pThis, CTL, pStream->u8SD) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)))
4109 fProceed = false;
4110 /* Is the BCIS (Buffer Completion Interrupt Status) flag set? Then we have to wait and skip. */
4111 else if ((HDA_STREAM_REG(pThis, STS, pStream->u8SD) & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)))
4112 fProceed = false;
4113
4114 if (!fProceed)
4115 {
4116#ifdef HDA_DEBUG_DMA
4117 Log3Func(("[SD%RU8] DMA: Skip\n", pStream->u8SD));
4118#endif
4119 if (pcbProcessed)
4120 *pcbProcessed = 0;
4121 return VINF_SUCCESS;
4122 }
4123
4124 int rc = VINF_SUCCESS;
4125
4126#ifdef HDA_DEBUG_DMA
4127 Log3Func(("[SD%RU8] DMA: Start\n", pStream->u8SD));
4128#endif
4129
4130 /* Sanity checks. */
4131 Assert(pStream->u8SD <= HDA_MAX_STREAMS);
4132 Assert(pStream->u64BDLBase);
4133 Assert(pStream->u32CBL);
4134
4135 /* State sanity checks. */
4136 Assert(pStream->State.fInReset == false);
4137 Assert(HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) <= pStream->u32CBL);
4138
4139 bool fSendInterrupt = false;
4140
4141 /* Only do one FIFO size at a time. */
4142 uint32_t cbLeft = RT_MIN(pStream->u16FIFOS, RT_MIN(cbToProcess, cbBuf));
4143 uint32_t cbTotal = 0;
4144 uint32_t cbChunk = 0;
4145 uint32_t cbChunkProcessed = 0;
4146
4147#ifdef HDA_DEBUG_DMA
4148 LogFunc(("[SD%RU8] DMA: cbToProcess=%RU32, cbLeft=%RU32\n", pStream->u8SD, cbToProcess, cbLeft));
4149#endif
4150
4151 /* Get the maximum number of BDL entries. */
4152 uint16_t cBDLE = pStream->u16LVI + 1;
4153
4154 while ( cbLeft
4155 && cBDLE--)
4156 {
4157 cbChunk = hdaStreamGetTransferSize(pThis, pStream, cbLeft);
4158 cbChunkProcessed = 0;
4159
4160 PHDABDLE pBDLE = &pStream->State.BDLE;
4161
4162 if (cbChunk)
4163 {
4164 if (hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_OUT) /* Output (SDO). */
4165 {
4166 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
4167 pBDLE->Desc.u64BufAdr + pBDLE->State.u32BufOff,
4168 (uint8_t *)pvBuf + cbTotal, cbChunk);
4169 }
4170 else /* Input (SDI). */
4171 {
4172 PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns),
4173 pBDLE->Desc.u64BufAdr + pBDLE->State.u32BufOff,
4174 (uint8_t *)pvBuf + cbTotal, cbChunk);
4175 }
4176
4177#ifdef HDA_DEBUG_DUMP_PCM_DATA
4178 RTFILE fh;
4179 RTFileOpen(&fh,
4180 hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_OUT
4181 ? HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaDMARead.pcm" : HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaDMAWrite.pcm",
4182 RTFILE_O_OPEN_CREATE | RTFILE_O_APPEND | RTFILE_O_WRITE | RTFILE_O_DENY_NONE);
4183 RTFileWrite(fh, (uint8_t *)pvBuf + cbTotal, cbChunk, NULL);
4184 RTFileClose(fh);
4185#endif
4186 }
4187
4188 cbChunkProcessed = cbChunk;
4189
4190 hdaBDLEUpdate(pBDLE, cbChunkProcessed, cbChunkProcessed);
4191
4192 LogFunc(("[SD%RU8] DMA: Entry %RU32 Pos %RU32/%RU32 Chunk %RU32\n",
4193 pStream->u8SD, pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->Desc.u32BufSize, cbChunk));
4194
4195 Assert(cbLeft >= cbChunkProcessed);
4196 cbLeft -= cbChunkProcessed;
4197 cbTotal += cbChunkProcessed;
4198 Assert(cbTotal <= cbToProcess);
4199
4200 hdaStreamTransferUpdate(pThis, pStream, cbChunkProcessed);
4201
4202#ifdef HDA_DEBUG_DMA
4203 LogFunc(("[SD%RU8] DMA: LPIB %RU32 Pos %RU32 Left %RU32\n",
4204 pStream->u8SD, HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), cbTotal, cbLeft));
4205#endif
4206 bool fNeedsInterrupt = false;
4207 bool fBDLEIsComplete = hdaBDLEIsComplete(pBDLE, &fNeedsInterrupt);
4208
4209 if (fNeedsInterrupt)
4210 fSendInterrupt = true;
4211
4212 if (fBDLEIsComplete)
4213 {
4214 /* Do we need to fetch the next Buffer Descriptor Entry (BDLE)? */
4215 if (hdaStreamNeedsNextBDLE(pThis, pStream))
4216 {
4217 bool fWrapAround;
4218 rc = hdaStreamGetNextBDLE(pThis, pStream, &fWrapAround);
4219 if ( RT_SUCCESS(rc)
4220 && fWrapAround)
4221 {
4222 hdaStreamUpdateLPIB(pThis, pStream, 0);
4223 }
4224 }
4225 }
4226
4227 if (RT_FAILURE(rc))
4228 break;
4229 }
4230
4231 Log3Func(("[SD%RU8]: cbLeft=%RU32, rc=%Rrc\n", pStream->u8SD, cbLeft, rc));
4232
4233 if (fSendInterrupt)
4234 {
4235#ifdef HDA_DEBUG_DMA
4236 Log3Func(("[SD%RU8] DMA: Interrupt\n", pStream->u8SD));
4237#endif
4238 /**
4239 * Set the BCIS (Buffer Completion Interrupt Status) flag as the
4240 * last byte of data for the current descriptor has been fetched
4241 * from memory and put into the DMA FIFO.
4242 *
4243 * Speech synthesis works fine on Mac Guest if this bit isn't set
4244 * but in general sound quality gets worse.
4245 *
4246 * This must be set in *any* case.
4247 */
4248 HDA_STREAM_REG(pThis, STS, pStream->u8SD) |= HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS);
4249 Log3Func(("[SD%RU8]: BCIS set\n", pStream->u8SD));
4250
4251 hdaProcessInterrupt(pThis);
4252 }
4253
4254 if (RT_SUCCESS(rc))
4255 {
4256 if (pcbProcessed)
4257 *pcbProcessed = cbTotal;
4258 }
4259
4260#ifdef HDA_DEBUG_DMA
4261 Log3Func(("[SD%RU8] DMA: End\n", pStream->u8SD));
4262#endif
4263
4264 return rc;
4265}
4266
4267/**
4268 * Writes audio data from a mixer sink into an HDA stream's DMA buffer.
4269 *
4270 * @returns IPRT status code.
4271 * @param pThis HDA state.
4272 * @param pStream HDA stream to write to.
4273 * @param cbToWrite Number of bytes to write.
4274 * @param pcbWritten Number of bytes written. Optional.
4275 */
4276static int hdaStreamWrite(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToWrite, uint32_t *pcbWritten)
4277{
4278 RT_NOREF(pThis);
4279 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
4280 AssertReturn(cbToWrite, VERR_INVALID_PARAMETER);
4281 /* pcbWritten is optional. */
4282
4283 PHDAMIXERSINK pSink = pStream->pMixSink;
4284 if (!pSink)
4285 {
4286 AssertMsgFailed(("[SD%RU8]: Can't write to a stream with no sink attached\n", pStream->u8SD));
4287
4288 if (pcbWritten)
4289 *pcbWritten = 0;
4290 return VINF_SUCCESS;
4291 }
4292
4293 PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
4294 AssertPtr(pCircBuf);
4295
4296 void *pvDst;
4297 size_t cbDst;
4298
4299 uint32_t cbWritten = 0;
4300
4301 RTCircBufAcquireWriteBlock(pCircBuf, cbToWrite, &pvDst, &cbDst);
4302
4303 if (cbDst)
4304 {
4305 int rc2 = AudioMixerSinkRead(pSink->pMixSink, AUDMIXOP_COPY, pvDst, (uint32_t)cbDst, &cbWritten);
4306 AssertRC(rc2);
4307
4308 Assert(cbDst >= cbWritten);
4309 Log2Func(("[SD%RU8]: %zu/%zu bytes written\n", pStream->u8SD, cbWritten, cbDst));
4310
4311#ifdef HDA_DEBUG_DUMP_PCM_DATA
4312 RTFILE fh;
4313 RTFileOpen(&fh, HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaStreamWrite.pcm",
4314 RTFILE_O_OPEN_CREATE | RTFILE_O_APPEND | RTFILE_O_WRITE | RTFILE_O_DENY_NONE);
4315 RTFileWrite(fh, pvDst, cbWritten, NULL);
4316 RTFileClose(fh);
4317#endif
4318 }
4319
4320 RTCircBufReleaseWriteBlock(pCircBuf, cbWritten);
4321
4322 if (pcbWritten)
4323 *pcbWritten = cbWritten;
4324
4325 return VINF_SUCCESS;
4326}
4327
4328/**
4329 * Reads audio data from an HDA stream's DMA buffer and writes into a specified mixer sink.
4330 *
4331 * @returns IPRT status code.
4332 * @param pThis HDA state.
4333 * @param pStream HDA stream to read audio data from.
4334 * @param cbToRead Number of bytes to read.
4335 * @param pcbRead Number of bytes read. Optional.
4336 */
4337static int hdaStreamRead(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToRead, uint32_t *pcbRead)
4338{
4339 RT_NOREF(pThis);
4340 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
4341 AssertReturn(cbToRead, VERR_INVALID_PARAMETER);
4342 /* pcbWritten is optional. */
4343
4344 PHDAMIXERSINK pSink = pStream->pMixSink;
4345 if (!pSink)
4346 {
4347 AssertMsgFailed(("[SD%RU8]: Can't read from a stream with no sink attached\n", pStream->u8SD));
4348
4349 if (pcbRead)
4350 *pcbRead = 0;
4351 return VINF_SUCCESS;
4352 }
4353
4354 PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
4355 AssertPtr(pCircBuf);
4356
4357 void *pvSrc;
4358 size_t cbSrc;
4359
4360 uint32_t cbRead = 0;
4361
4362 RTCircBufAcquireReadBlock(pCircBuf, cbToRead, &pvSrc, &cbSrc);
4363
4364 if (cbSrc)
4365 {
4366 Log2Func(("[SD%RU8]: Reading %zu bytes ...\n", pStream->u8SD, cbSrc));
4367
4368#ifdef HDA_DEBUG_DUMP_PCM_DATA
4369 RTFILE fh;
4370 RTFileOpen(&fh, HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaStreamRead.pcm",
4371 RTFILE_O_OPEN_CREATE | RTFILE_O_APPEND | RTFILE_O_WRITE | RTFILE_O_DENY_NONE);
4372 RTFileWrite(fh, pvSrc, cbSrc, NULL);
4373 RTFileClose(fh);
4374#endif
4375 int rc2 = AudioMixerSinkWrite(pSink->pMixSink, AUDMIXOP_COPY, pvSrc, (uint32_t)cbSrc, &cbRead);
4376 AssertRC(rc2);
4377
4378 Assert(cbSrc >= cbRead);
4379 Log2Func(("[SD%RU8]: %zu/%zu bytes read\n", pStream->u8SD, cbRead, cbSrc));
4380 }
4381
4382 RTCircBufReleaseReadBlock(pCircBuf, cbRead);
4383
4384 if (pcbRead)
4385 *pcbRead = cbRead;
4386
4387 return VINF_SUCCESS;
4388}
4389
4390#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
4391/**
4392 * Asynchronous I/O thread for a HDA stream.
4393 * This will do the heavy lifting work for us as soon as it's getting notified by another thread.
4394 *
4395 * @returns IPRT status code.
4396 * @param hThreadSelf Thread handle.
4397 * @param pvUser User argument. Must be of type PHDASTREAMTHREADCTX.
4398 */
4399static DECLCALLBACK(int) hdaStreamAsyncIOThread(RTTHREAD hThreadSelf, void *pvUser)
4400{
4401 PHDASTREAMTHREADCTX pCtx = (PHDASTREAMTHREADCTX)pvUser;
4402 AssertPtr(pCtx);
4403
4404 PHDASTATE pThis = pCtx->pThis;
4405 AssertPtr(pThis);
4406
4407 PHDASTREAM pStream = pCtx->pStream;
4408 AssertPtr(pStream);
4409
4410 PHDASTREAMSTATEAIO pAIO = &pCtx->pStream->State.AIO;
4411
4412 PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
4413 AssertPtr(pCircBuf);
4414
4415 ASMAtomicXchgBool(&pAIO->fStarted, true);
4416
4417 RTThreadUserSignal(hThreadSelf);
4418
4419 LogFunc(("[SD%RU8]: Started\n", pStream->u8SD));
4420
4421 for (;;)
4422 {
4423 int rc2 = RTSemEventWait(pAIO->Event, RT_INDEFINITE_WAIT);
4424 if (RT_FAILURE(rc2))
4425 break;
4426
4427 if (ASMAtomicReadBool(&pAIO->fShutdown))
4428 break;
4429
4430 PHDAMIXERSINK pSink = pStream->pMixSink;
4431
4432 rc2 = RTCritSectEnter(&pAIO->CritSect);
4433 if (RT_SUCCESS(rc2))
4434 {
4435 if (!pAIO->fEnabled)
4436 {
4437 RTCritSectLeave(&pAIO->CritSect);
4438 continue;
4439 }
4440
4441 uint32_t cbToProcess;
4442 uint32_t cbProcessed = 0;
4443
4444 if (hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_OUT) /* Output (SDO). */
4445 {
4446 cbToProcess = (uint32_t)RTCircBufUsed(pCircBuf);
4447 if (cbToProcess)
4448 rc2 = hdaStreamRead(pThis, pStream, cbToProcess, &cbProcessed);
4449 }
4450 else /* Input (SDI). */
4451 {
4452 cbToProcess = (uint32_t)RTCircBufFree(pCircBuf);
4453 if (cbToProcess)
4454 rc2 = hdaStreamWrite(pThis, pStream, cbToProcess, &cbProcessed);
4455 }
4456
4457 if ( pSink
4458 && RT_SUCCESS(rc2))
4459 {
4460 rc2 = AudioMixerSinkUpdate(pSink->pMixSink);
4461 }
4462
4463 int rc3 = RTCritSectLeave(&pAIO->CritSect);
4464 AssertRC(rc3);
4465 }
4466
4467 AssertRC(rc2);
4468 }
4469
4470 LogFunc(("[SD%RU8]: Ended\n", pStream->u8SD));
4471
4472 ASMAtomicXchgBool(&pAIO->fStarted, false);
4473
4474 return VINF_SUCCESS;
4475}
4476
4477/**
4478 * Creates the async I/O thread for a specific HDA audio stream.
4479 *
4480 * @returns IPRT status code.
4481 * @param pThis HDA state.
4482 * @param pStream HDA audio stream to create the async I/O thread for.
4483 */
4484static int hdaStreamAsyncIOCreate(PHDASTATE pThis, PHDASTREAM pStream)
4485{
4486 PHDASTREAMSTATEAIO pAIO = &pStream->State.AIO;
4487
4488 int rc;
4489
4490 if (!ASMAtomicReadBool(&pAIO->fStarted))
4491 {
4492 pAIO->fShutdown = false;
4493
4494 rc = RTSemEventCreate(&pAIO->Event);
4495 if (RT_SUCCESS(rc))
4496 {
4497 rc = RTCritSectInit(&pAIO->CritSect);
4498 if (RT_SUCCESS(rc))
4499 {
4500 HDASTREAMTHREADCTX Ctx = { pThis, pStream };
4501
4502 char szThreadName[64];
4503 RTStrPrintf2(szThreadName, sizeof(szThreadName), "hdaAIO%RU8", pStream->u8SD);
4504
4505 rc = RTThreadCreate(&pAIO->Thread, hdaStreamAsyncIOThread, &Ctx,
4506 0, RTTHREADTYPE_IO, RTTHREADFLAGS_WAITABLE, szThreadName);
4507 if (RT_SUCCESS(rc))
4508 rc = RTThreadUserWait(pAIO->Thread, 10 * 1000 /* 10s timeout */);
4509 }
4510 }
4511 }
4512 else
4513 rc = VINF_SUCCESS;
4514
4515 LogFunc(("[SD%RU8]: Returning %Rrc\n", pStream->u8SD, rc));
4516 return rc;
4517}
4518
4519/**
4520 * Destroys the async I/O thread of a specific HDA audio stream.
4521 *
4522 * @returns IPRT status code.
4523 * @param pThis HDA state.
4524 * @param pStream HDA audio stream to destroy the async I/O thread for.
4525 */
4526static int hdaStreamAsyncIODestroy(PHDASTATE pThis, PHDASTREAM pStream)
4527{
4528 PHDASTREAMSTATEAIO pAIO = &pStream->State.AIO;
4529
4530 if (!ASMAtomicReadBool(&pAIO->fStarted))
4531 return VINF_SUCCESS;
4532
4533 ASMAtomicWriteBool(&pAIO->fShutdown, true);
4534
4535 int rc = hdaStreamAsyncIONotify(pThis, pStream);
4536 AssertRC(rc);
4537
4538 int rcThread;
4539 rc = RTThreadWait(pAIO->Thread, 30 * 1000 /* 30s timeout */, &rcThread);
4540 LogFunc(("Async I/O thread ended with %Rrc (%Rrc)\n", rc, rcThread));
4541
4542 if (RT_SUCCESS(rc))
4543 {
4544 rc = RTCritSectDelete(&pAIO->CritSect);
4545 AssertRC(rc);
4546
4547 rc = RTSemEventDestroy(pAIO->Event);
4548 AssertRC(rc);
4549
4550 pAIO->fStarted = false;
4551 pAIO->fShutdown = false;
4552 pAIO->fEnabled = false;
4553 }
4554
4555 LogFunc(("[SD%RU8]: Returning %Rrc\n", pStream->u8SD, rc));
4556 return rc;
4557}
4558
4559/**
4560 * Lets the stream's async I/O thread know that there is some data to process.
4561 *
4562 * @returns IPRT status code.
4563 * @param pThis HDA state.
4564 * @param pStream HDA stream to notify async I/O thread for.
4565 */
4566static int hdaStreamAsyncIONotify(PHDASTATE pThis, PHDASTREAM pStream)
4567{
4568 RT_NOREF(pThis);
4569 return RTSemEventSignal(pStream->State.AIO.Event);
4570}
4571
4572/**
4573 * Locks the async I/O thread of a specific HDA audio stream.
4574 *
4575 * @param pStream HDA stream to lock async I/O thread for.
4576 */
4577static void hdaStreamAsyncIOLock(PHDASTREAM pStream)
4578{
4579 PHDASTREAMSTATEAIO pAIO = &pStream->State.AIO;
4580
4581 if (!ASMAtomicReadBool(&pAIO->fStarted))
4582 return;
4583
4584 int rc2 = RTCritSectEnter(&pAIO->CritSect);
4585 AssertRC(rc2);
4586}
4587
4588/**
4589 * Unlocks the async I/O thread of a specific HDA audio stream.
4590 *
4591 * @param pStream HDA stream to unlock async I/O thread for.
4592 */
4593static void hdaStreamAsyncIOUnlock(PHDASTREAM pStream)
4594{
4595 PHDASTREAMSTATEAIO pAIO = &pStream->State.AIO;
4596
4597 if (!ASMAtomicReadBool(&pAIO->fStarted))
4598 return;
4599
4600 int rc2 = RTCritSectLeave(&pAIO->CritSect);
4601 AssertRC(rc2);
4602}
4603
4604/**
4605 * Enables (resumes) or disables (pauses) the async I/O thread.
4606 *
4607 * @param pStream HDA stream to enable/disable async I/O thread for.
4608 * @param fEnable Whether to enable or disable the I/O thread.
4609 *
4610 * @remarks Does not do locking.
4611 */
4612static void hdaStreamAsyncIOEnable(PHDASTREAM pStream, bool fEnable)
4613{
4614 PHDASTREAMSTATEAIO pAIO = &pStream->State.AIO;
4615 ASMAtomicXchgBool(&pAIO->fEnabled, fEnable);
4616}
4617#endif /* VBOX_WITH_AUDIO_HDA_ASYNC_IO */
4618
4619/**
4620 * Updates a HDA stream according to its usage (input / output).
4621 *
4622 * For an SDO (output) stream this means reading DMA data from the device to
4623 * the connected audio sink(s).
4624 *
4625 * For an SDI (input) stream this is reading audio data from the connected
4626 * audio sink(s) and writing it as DMA data to the device.
4627 *
4628 * @returns IPRT status code.
4629 * @param pThis HDA state.
4630 * @param pStream HDA stream to update.
4631 */
4632static int hdaStreamUpdate(PHDASTATE pThis, PHDASTREAM pStream)
4633{
4634 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
4635 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
4636
4637 hdaStreamLock(pStream);
4638
4639 PHDAMIXERSINK pSink = pStream->pMixSink;
4640 AssertPtr(pSink);
4641
4642 PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
4643 AssertPtr(pCircBuf);
4644
4645 if (!AudioMixerSinkIsActive(pSink->pMixSink))
4646 {
4647 hdaStreamUnlock(pStream);
4648 return VINF_SUCCESS;
4649 }
4650
4651 Log2Func(("[SD%RU8]\n", pStream->u8SD));
4652
4653 bool fDone = false;
4654 uint8_t cTransfers = 0;
4655
4656 while (!fDone)
4657 {
4658 int rc2;
4659 uint32_t cbDMA = 0;
4660
4661 if (hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_OUT) /* Output (SDO). */
4662 {
4663 STAM_PROFILE_START(&pThis->StatOut, a);
4664
4665 /*
4666 * Read from DMA.
4667 */
4668
4669 uint8_t abFIFO[HDA_FIFO_MAX + 1];
4670 size_t offFIFO = 0;
4671
4672 /* Do one DMA transfer with FIFOS size at a time. */
4673 rc2 = hdaStreamDoDMA(pThis, pStream, abFIFO, sizeof(abFIFO), (uint32_t)pStream->u16FIFOS /* cbToProcess */, &cbDMA);
4674 AssertRC(rc2);
4675
4676 uint32_t cbDMALeft = cbDMA;
4677
4678 while ( cbDMALeft
4679 && RTCircBufFree(pCircBuf))
4680 {
4681 void *pvDst;
4682 size_t cbDst;
4683
4684 RTCircBufAcquireWriteBlock(pCircBuf, cbDMALeft, &pvDst, &cbDst);
4685
4686 if (cbDst)
4687 {
4688 memcpy(pvDst, abFIFO + offFIFO, cbDst);
4689
4690 offFIFO += cbDst;
4691 Assert(offFIFO <= sizeof(abFIFO));
4692 }
4693
4694 RTCircBufReleaseWriteBlock(pCircBuf, cbDst);
4695
4696 Assert(cbDst <= cbDMALeft);
4697 cbDMALeft -= (uint32_t)cbDst;
4698 }
4699
4700#ifdef DEBUG_andy
4701 AssertMsg(cbDMALeft == 0, ("%RU32 bytes of DMA data left, CircBuf=%zu/%zu\n",
4702 cbDMALeft, RTCircBufUsed(pCircBuf), RTCircBufSize(pCircBuf)));
4703#endif
4704 /*
4705 * Process backends.
4706 */
4707
4708 uint32_t cbUsed = (uint32_t)RTCircBufUsed(pCircBuf);
4709 if (cbUsed)
4710 {
4711#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
4712 /* Let the asynchronous thread know that there is some new data to process. */
4713 hdaStreamAsyncIONotify(pThis, pStream);
4714#else
4715 /* Read audio data from the HDA stream and write to the backends. */
4716 rc2 = hdaStreamRead(pThis, pStream, cbUsed, NULL /* pcbRead */);
4717 AssertRC(rc2);
4718#endif
4719 }
4720
4721 /* All DMA transfers done for now? */
4722 if ( !cbDMA
4723#ifndef VBOX_WITH_AUDIO_HDA_ASYNC_IO
4724 /* All data read *and* processed for now? */
4725 && RTCircBufUsed(pCircBuf) == 0
4726#endif
4727 )
4728 {
4729 fDone = true;
4730 }
4731
4732#ifndef VBOX_WITH_AUDIO_HDA_ASYNC_IO
4733 rc2 = AudioMixerSinkUpdate(pSink->pMixSink);
4734 AssertRC(rc2);
4735#endif
4736 STAM_PROFILE_STOP(&pThis->StatOut, a);
4737 }
4738 else if (hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN) /* Input (SDI). */
4739 {
4740 STAM_PROFILE_START(&pThis->StatIn, a);
4741
4742 /*
4743 * Process backends.
4744 */
4745
4746#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
4747 /* Let the asynchronous thread know that there is some new data to process. */
4748 hdaStreamAsyncIONotify(pThis, pStream);
4749#else
4750 rc2 = AudioMixerSinkUpdate(pSink->pMixSink);
4751 AssertRC(rc2);
4752
4753 /* Write read data from the backend to the HDA stream. */
4754 rc2 = hdaStreamWrite(pThis, pStream, pStream->u16FIFOS, NULL /* pcbWritten */);
4755 AssertRC(rc2);
4756#endif
4757 /*
4758 * Write to DMA.
4759 */
4760
4761 void *pvSrc;
4762 size_t cbSrc;
4763
4764 RTCircBufAcquireReadBlock(pCircBuf, pStream->u16FIFOS, &pvSrc, &cbSrc);
4765
4766 if (cbSrc)
4767 {
4768 /* Do one DMA transfer with FIFOS size at a time. */
4769 rc2 = hdaStreamDoDMA(pThis, pStream, pvSrc, (uint32_t)cbSrc, (uint32_t)cbSrc /* cbToProcess */, &cbDMA);
4770 AssertRC(rc2);
4771 }
4772
4773 RTCircBufReleaseReadBlock(pCircBuf, cbDMA);
4774
4775 /* All DMA transfers done for now? */
4776 if (!cbDMA)
4777 fDone = true;
4778
4779 STAM_PROFILE_STOP(&pThis->StatIn, a);
4780 }
4781 else
4782 AssertFailed();
4783
4784 if (++cTransfers > 32) /* Failsafe counter. */
4785 fDone = true;
4786
4787 } /* while !fDone */
4788
4789 Log2Func(("[SD%RU8] End\n", pStream->u8SD));
4790
4791 hdaStreamUnlock(pStream);
4792
4793 return VINF_SUCCESS;
4794}
4795#endif /* IN_RING3 */
4796
4797/* MMIO callbacks */
4798
4799/**
4800 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
4801 *
4802 * @note During implementation, we discovered so-called "forgotten" or "hole"
4803 * registers whose description is not listed in the RPM, datasheet, or
4804 * spec.
4805 */
4806PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
4807{
4808 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4809 int rc;
4810 RT_NOREF_PV(pvUser);
4811
4812 /*
4813 * Look up and log.
4814 */
4815 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
4816 int idxRegDsc = hdaRegLookup(offReg); /* Register descriptor index. */
4817#ifdef LOG_ENABLED
4818 unsigned const cbLog = cb;
4819 uint32_t offRegLog = offReg;
4820#endif
4821
4822 Log3Func(("offReg=%#x cb=%#x\n", offReg, cb));
4823 Assert(cb == 4); Assert((offReg & 3) == 0);
4824
4825 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
4826 LogFunc(("Access to registers except GCTL is blocked while reset\n"));
4827
4828 if (idxRegDsc == -1)
4829 LogRel(("HDA: Invalid read access @0x%x (bytes=%u)\n", offReg, cb));
4830
4831 if (idxRegDsc != -1)
4832 {
4833 /* ASSUMES gapless DWORD at end of map. */
4834 if (g_aHdaRegMap[idxRegDsc].size == 4)
4835 {
4836 /*
4837 * Straight forward DWORD access.
4838 */
4839 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
4840 Log3Func(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
4841 }
4842 else
4843 {
4844 /*
4845 * Multi register read (unless there are trailing gaps).
4846 * ASSUMES that only DWORD reads have sideeffects.
4847 */
4848 uint32_t u32Value = 0;
4849 unsigned cbLeft = 4;
4850 do
4851 {
4852 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
4853 uint32_t u32Tmp = 0;
4854
4855 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
4856 Log3Func(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
4857 if (rc != VINF_SUCCESS)
4858 break;
4859 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
4860
4861 cbLeft -= cbReg;
4862 offReg += cbReg;
4863 idxRegDsc++;
4864 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
4865
4866 if (rc == VINF_SUCCESS)
4867 *(uint32_t *)pv = u32Value;
4868 else
4869 Assert(!IOM_SUCCESS(rc));
4870 }
4871 }
4872 else
4873 {
4874 rc = VINF_IOM_MMIO_UNUSED_FF;
4875 Log3Func(("\tHole at %x is accessed for read\n", offReg));
4876 }
4877
4878 /*
4879 * Log the outcome.
4880 */
4881#ifdef LOG_ENABLED
4882 if (cbLog == 4)
4883 Log3Func(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
4884 else if (cbLog == 2)
4885 Log3Func(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
4886 else if (cbLog == 1)
4887 Log3Func(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
4888#endif
4889 return rc;
4890}
4891
4892
4893DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
4894{
4895 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
4896 {
4897 Log(("hdaWriteReg: Warning: Access to %s is blocked while controller is in reset mode\n", g_aHdaRegMap[idxRegDsc].abbrev));
4898 LogRel2(("HDA: Warning: Access to register %s is blocked while controller is in reset mode\n",
4899 g_aHdaRegMap[idxRegDsc].abbrev));
4900 return VINF_SUCCESS;
4901 }
4902
4903 /*
4904 * Handle RD (register description) flags.
4905 */
4906
4907 /* For SDI / SDO: Check if writes to those registers are allowed while SDCTL's RUN bit is set. */
4908 if (idxRegDsc >= HDA_NUM_GENERAL_REGS)
4909 {
4910 const uint32_t uSDCTL = HDA_STREAM_REG(pThis, CTL, HDA_SD_NUM_FROM_REG(pThis, CTL, idxRegDsc));
4911
4912 /*
4913 * Some OSes (like Win 10 AU) violate the spec by writing stuff to registers which are not supposed to be be touched
4914 * while SDCTL's RUN bit is set. So just ignore those values.
4915 */
4916
4917 /* Is the RUN bit currently set? */
4918 if ( RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN))
4919 /* Are writes to the register denied if RUN bit is set? */
4920 && !(g_aHdaRegMap[idxRegDsc].fFlags & HDA_RD_FLAG_SD_WRITE_RUN))
4921 {
4922 Log(("hdaWriteReg: Warning: Access to %s is blocked! %R[sdctl]\n", g_aHdaRegMap[idxRegDsc].abbrev, uSDCTL));
4923 LogRel2(("HDA: Warning: Access to register %s is blocked while the stream's RUN bit is set\n",
4924 g_aHdaRegMap[idxRegDsc].abbrev));
4925 return VINF_SUCCESS;
4926 }
4927 }
4928
4929#ifdef LOG_ENABLED
4930 uint32_t const idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4931 uint32_t const u32OldValue = pThis->au32Regs[idxRegMem];
4932#endif
4933 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
4934 Log3Func(("Written value %#x to %s[%d byte]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
4935 g_aHdaRegMap[idxRegDsc].size, u32OldValue, pThis->au32Regs[idxRegMem], pszLog));
4936 RT_NOREF(pszLog);
4937 return rc;
4938}
4939
4940
4941/**
4942 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
4943 */
4944PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
4945{
4946 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4947 int rc;
4948 RT_NOREF_PV(pvUser);
4949
4950 /*
4951 * The behavior of accesses that aren't aligned on natural boundraries is
4952 * undefined. Just reject them outright.
4953 */
4954 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
4955 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
4956 if (GCPhysAddr & (cb - 1))
4957 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
4958
4959 /*
4960 * Look up and log the access.
4961 */
4962 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
4963 int idxRegDsc = hdaRegLookup(offReg);
4964 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
4965 uint64_t u64Value;
4966 if (cb == 4) u64Value = *(uint32_t const *)pv;
4967 else if (cb == 2) u64Value = *(uint16_t const *)pv;
4968 else if (cb == 1) u64Value = *(uint8_t const *)pv;
4969 else if (cb == 8) u64Value = *(uint64_t const *)pv;
4970 else
4971 {
4972 u64Value = 0; /* shut up gcc. */
4973 AssertReleaseMsgFailed(("%u\n", cb));
4974 }
4975
4976#ifdef LOG_ENABLED
4977 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
4978 if (idxRegDsc == -1)
4979 Log3Func(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
4980 else if (cb == 4)
4981 Log3Func(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4982 else if (cb == 2)
4983 Log3Func(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4984 else if (cb == 1)
4985 Log3Func(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4986
4987 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
4988 Log3Func(("\tsize=%RU32 != cb=%u!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
4989#endif
4990
4991 /*
4992 * Try for a direct hit first.
4993 */
4994 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
4995 {
4996 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
4997 Log3Func(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
4998 }
4999 /*
5000 * Partial or multiple register access, loop thru the requested memory.
5001 */
5002 else
5003 {
5004 /*
5005 * If it's an access beyond the start of the register, shift the input
5006 * value and fill in missing bits. Natural alignment rules means we
5007 * will only see 1 or 2 byte accesses of this kind, so no risk of
5008 * shifting out input values.
5009 */
5010 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(offReg)) != -1)
5011 {
5012 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
5013 offReg -= cbBefore;
5014 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
5015 u64Value <<= cbBefore * 8;
5016 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
5017 Log3Func(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
5018 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
5019 }
5020
5021 /* Loop thru the write area, it may cover multiple registers. */
5022 rc = VINF_SUCCESS;
5023 for (;;)
5024 {
5025 uint32_t cbReg;
5026 if (idxRegDsc != -1)
5027 {
5028 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
5029 cbReg = g_aHdaRegMap[idxRegDsc].size;
5030 if (cb < cbReg)
5031 {
5032 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
5033 Log3Func(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
5034 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
5035 }
5036#ifdef LOG_ENABLED
5037 uint32_t uLogOldVal = pThis->au32Regs[idxRegMem];
5038#endif
5039 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
5040 Log3Func(("\t%#x -> %#x\n", uLogOldVal, pThis->au32Regs[idxRegMem]));
5041 }
5042 else
5043 {
5044 LogRel(("HDA: Invalid write access @0x%x\n", offReg));
5045 cbReg = 1;
5046 }
5047 if (rc != VINF_SUCCESS)
5048 break;
5049 if (cbReg >= cb)
5050 break;
5051
5052 /* Advance. */
5053 offReg += cbReg;
5054 cb -= cbReg;
5055 u64Value >>= cbReg * 8;
5056 if (idxRegDsc == -1)
5057 idxRegDsc = hdaRegLookup(offReg);
5058 else
5059 {
5060 idxRegDsc++;
5061 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
5062 || g_aHdaRegMap[idxRegDsc].offset != offReg)
5063 {
5064 idxRegDsc = -1;
5065 }
5066 }
5067 }
5068 }
5069
5070 return rc;
5071}
5072
5073
5074/* PCI callback. */
5075
5076#ifdef IN_RING3
5077/**
5078 * @callback_method_impl{FNPCIIOREGIONMAP}
5079 */
5080static DECLCALLBACK(int) hdaPciIoRegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
5081 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
5082{
5083 RT_NOREF(iRegion, enmType);
5084 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
5085
5086 /*
5087 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
5088 *
5089 * Let IOM talk DWORDs when reading, saves a lot of complications. On
5090 * writing though, we have to do it all ourselves because of sideeffects.
5091 */
5092 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
5093 int rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
5094 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_PASSTHRU,
5095 hdaMMIOWrite, hdaMMIORead, "HDA");
5096 if (RT_FAILURE(rc))
5097 return rc;
5098
5099 if (pThis->fR0Enabled)
5100 {
5101 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
5102 "hdaMMIOWrite", "hdaMMIORead");
5103 if (RT_FAILURE(rc))
5104 return rc;
5105 }
5106
5107 if (pThis->fRCEnabled)
5108 {
5109 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
5110 "hdaMMIOWrite", "hdaMMIORead");
5111 if (RT_FAILURE(rc))
5112 return rc;
5113 }
5114
5115 pThis->MMIOBaseAddr = GCPhysAddress;
5116 return VINF_SUCCESS;
5117}
5118
5119
5120/* Saved state callbacks. */
5121
5122static int hdaSaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStrm)
5123{
5124 RT_NOREF(pDevIns);
5125#ifdef DEBUG
5126 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5127#endif
5128 LogFlowFunc(("[SD%RU8]\n", pStrm->u8SD));
5129
5130 /* Save stream ID. */
5131 int rc = SSMR3PutU8(pSSM, pStrm->u8SD);
5132 AssertRCReturn(rc, rc);
5133 Assert(pStrm->u8SD <= HDA_MAX_STREAMS);
5134
5135 rc = SSMR3PutStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE), 0 /*fFlags*/, g_aSSMStreamStateFields6, NULL);
5136 AssertRCReturn(rc, rc);
5137
5138#ifdef DEBUG /* Sanity checks. */
5139 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStrm->u8SD),
5140 HDA_STREAM_REG(pThis, BDPU, pStrm->u8SD));
5141 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStrm->u8SD);
5142 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStrm->u8SD);
5143
5144 hdaBDLEDumpAll(pThis, u64BaseDMA, u16LVI + 1);
5145
5146 Assert(u64BaseDMA == pStrm->u64BDLBase);
5147 Assert(u16LVI == pStrm->u16LVI);
5148 Assert(u32CBL == pStrm->u32CBL);
5149#endif
5150
5151 rc = SSMR3PutStructEx(pSSM, &pStrm->State.BDLE.Desc, sizeof(HDABDLEDESC),
5152 0 /*fFlags*/, g_aSSMBDLEDescFields6, NULL);
5153 AssertRCReturn(rc, rc);
5154
5155 rc = SSMR3PutStructEx(pSSM, &pStrm->State.BDLE.State, sizeof(HDABDLESTATE),
5156 0 /*fFlags*/, g_aSSMBDLEStateFields6, NULL);
5157 AssertRCReturn(rc, rc);
5158
5159#ifdef DEBUG /* Sanity checks. */
5160 PHDABDLE pBDLE = &pStrm->State.BDLE;
5161 if (u64BaseDMA)
5162 {
5163 Assert(pStrm->State.uCurBDLE <= u16LVI + 1);
5164
5165 HDABDLE curBDLE;
5166 rc = hdaBDLEFetch(pThis, &curBDLE, u64BaseDMA, pStrm->State.uCurBDLE);
5167 AssertRC(rc);
5168
5169 Assert(curBDLE.Desc.u32BufSize == pBDLE->Desc.u32BufSize);
5170 Assert(curBDLE.Desc.u64BufAdr == pBDLE->Desc.u64BufAdr);
5171 Assert(curBDLE.Desc.fFlags == pBDLE->Desc.fFlags);
5172 }
5173 else
5174 {
5175 Assert(pBDLE->Desc.u64BufAdr == 0);
5176 Assert(pBDLE->Desc.u32BufSize == 0);
5177 }
5178#endif
5179 return rc;
5180}
5181
5182/**
5183 * @callback_method_impl{FNSSMDEVSAVEEXEC}
5184 */
5185static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5186{
5187 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5188
5189 /* Save Codec nodes states. */
5190 hdaCodecSaveState(pThis->pCodec, pSSM);
5191
5192 /* Save MMIO registers. */
5193 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
5194 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
5195
5196 /* Save number of streams. */
5197 SSMR3PutU32(pSSM, HDA_MAX_STREAMS);
5198
5199 /* Save stream states. */
5200 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5201 {
5202 int rc = hdaSaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
5203 AssertRCReturn(rc, rc);
5204 }
5205
5206 return VINF_SUCCESS;
5207}
5208
5209
5210/**
5211 * @callback_method_impl{FNSSMDEVLOADEXEC}
5212 */
5213static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5214{
5215 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5216
5217 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
5218
5219 LogRel2(("hdaLoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
5220
5221 /*
5222 * Load Codec nodes states.
5223 */
5224 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
5225 if (RT_FAILURE(rc))
5226 {
5227 LogRel(("HDA: Failed loading codec state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
5228 return rc;
5229 }
5230
5231 /*
5232 * Load MMIO registers.
5233 */
5234 uint32_t cRegs;
5235 switch (uVersion)
5236 {
5237 case HDA_SSM_VERSION_1:
5238 /* Starting with r71199, we would save 112 instead of 113
5239 registers due to some code cleanups. This only affected trunk
5240 builds in the 4.1 development period. */
5241 cRegs = 113;
5242 if (SSMR3HandleRevision(pSSM) >= 71199)
5243 {
5244 uint32_t uVer = SSMR3HandleVersion(pSSM);
5245 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
5246 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
5247 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
5248 cRegs = 112;
5249 }
5250 break;
5251
5252 case HDA_SSM_VERSION_2:
5253 case HDA_SSM_VERSION_3:
5254 cRegs = 112;
5255 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= 112);
5256 break;
5257
5258 /* Since version 4 we store the register count to stay flexible. */
5259 case HDA_SSM_VERSION_4:
5260 case HDA_SSM_VERSION_5:
5261 case HDA_SSM_VERSION:
5262 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
5263 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
5264 LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
5265 break;
5266
5267 default:
5268 LogRel(("HDA: Unsupported / too new saved state version (%RU32)\n", uVersion));
5269 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
5270 }
5271
5272 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
5273 {
5274 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
5275 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
5276 }
5277 else
5278 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
5279
5280 /*
5281 * Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
5282 * *every* BDLE state, whereas it only needs to be stored
5283 * *once* for every stream. Most of the BDLE state we can
5284 * get out of the registers anyway, so just ignore those values.
5285 *
5286 * Also, only the current BDLE was saved, regardless whether
5287 * there were more than one (and there are at least two entries,
5288 * according to the spec).
5289 */
5290#define HDA_SSM_LOAD_BDLE_STATE_PRE_V5(v, x) \
5291 { \
5292 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */ \
5293 AssertRCReturn(rc, rc); \
5294 rc = SSMR3GetU64(pSSM, &x.Desc.u64BufAdr); /* u64BdleCviAddr */ \
5295 AssertRCReturn(rc, rc); \
5296 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleMaxCvi */ \
5297 AssertRCReturn(rc, rc); \
5298 rc = SSMR3GetU32(pSSM, &x.State.u32BDLIndex); /* u32BdleCvi */ \
5299 AssertRCReturn(rc, rc); \
5300 rc = SSMR3GetU32(pSSM, &x.Desc.u32BufSize); /* u32BdleCviLen */ \
5301 AssertRCReturn(rc, rc); \
5302 rc = SSMR3GetU32(pSSM, &x.State.u32BufOff); /* u32BdleCviPos */ \
5303 AssertRCReturn(rc, rc); \
5304 bool fIOC; \
5305 rc = SSMR3GetBool(pSSM, &fIOC); /* fBdleCviIoc */ \
5306 AssertRCReturn(rc, rc); \
5307 x.Desc.fFlags = fIOC ? HDA_BDLE_FLAG_IOC : 0; \
5308 rc = SSMR3GetU32(pSSM, &x.State.cbBelowFIFOW); /* cbUnderFifoW */ \
5309 AssertRCReturn(rc, rc); \
5310 rc = SSMR3Skip(pSSM, sizeof(uint8_t) * 256); /* FIFO */ \
5311 AssertRCReturn(rc, rc); \
5312 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */ \
5313 AssertRCReturn(rc, rc); \
5314 } \
5315
5316 /*
5317 * Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
5318 */
5319 switch (uVersion)
5320 {
5321 case HDA_SSM_VERSION_1:
5322 case HDA_SSM_VERSION_2:
5323 case HDA_SSM_VERSION_3:
5324 case HDA_SSM_VERSION_4:
5325 {
5326 /* Only load the internal states.
5327 * The rest will be initialized from the saved registers later. */
5328
5329 /* Note 1: Only the *current* BDLE for a stream was saved! */
5330 /* Note 2: The stream's saving order is/was fixed, so don't touch! */
5331
5332 /* Output */
5333 PHDASTREAM pStream = &pThis->aStreams[4];
5334 rc = hdaStreamInit(pThis, pStream, 4 /* Stream descriptor, hardcoded */);
5335 if (RT_FAILURE(rc))
5336 break;
5337 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
5338 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
5339
5340 /* Microphone-In */
5341 pStream = &pThis->aStreams[2];
5342 rc = hdaStreamInit(pThis, pStream, 2 /* Stream descriptor, hardcoded */);
5343 if (RT_FAILURE(rc))
5344 break;
5345 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
5346 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
5347
5348 /* Line-In */
5349 pStream = &pThis->aStreams[0];
5350 rc = hdaStreamInit(pThis, pStream, 0 /* Stream descriptor, hardcoded */);
5351 if (RT_FAILURE(rc))
5352 break;
5353 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
5354 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
5355 break;
5356 }
5357
5358 /* Since v5 we support flexible stream and BDLE counts. */
5359 case HDA_SSM_VERSION_5:
5360 case HDA_SSM_VERSION:
5361 {
5362 uint32_t cStreams;
5363 rc = SSMR3GetU32(pSSM, &cStreams);
5364 if (RT_FAILURE(rc))
5365 break;
5366
5367 LogRel2(("hdaLoadExec: cStreams=%RU32\n", cStreams));
5368
5369 /* Load stream states. */
5370 for (uint32_t i = 0; i < cStreams; i++)
5371 {
5372 uint8_t uSD;
5373 rc = SSMR3GetU8(pSSM, &uSD);
5374 if (RT_FAILURE(rc))
5375 break;
5376
5377 PHDASTREAM pStrm = hdaStreamGetFromSD(pThis, uSD);
5378 HDASTREAM StreamDummy;
5379
5380 if (!pStrm)
5381 {
5382 RT_ZERO(StreamDummy);
5383 pStrm = &StreamDummy;
5384 LogRel2(("HDA: Warning: Stream ID=%RU32 not supported, skipping to load ...\n", uSD));
5385 break;
5386 }
5387
5388 rc = hdaStreamInit(pThis, pStrm, uSD);
5389 if (RT_FAILURE(rc))
5390 {
5391 LogRel(("HDA: Stream #%RU32: Initialization of stream %RU8 failed, rc=%Rrc\n", i, uSD, rc));
5392 break;
5393 }
5394
5395 if (uVersion == HDA_SSM_VERSION_5)
5396 {
5397 /* Get the current BDLE entry and skip the rest. */
5398 uint16_t cBDLE;
5399
5400 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
5401 AssertRC(rc);
5402 rc = SSMR3GetU16(pSSM, &cBDLE); /* cBDLE */
5403 AssertRC(rc);
5404 rc = SSMR3GetU16(pSSM, &pStrm->State.uCurBDLE); /* uCurBDLE */
5405 AssertRC(rc);
5406 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
5407 AssertRC(rc);
5408
5409 uint32_t u32BDLEIndex;
5410 for (uint16_t a = 0; a < cBDLE; a++)
5411 {
5412 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
5413 AssertRC(rc);
5414 rc = SSMR3GetU32(pSSM, &u32BDLEIndex); /* u32BDLIndex */
5415 AssertRC(rc);
5416
5417 /* Does the current BDLE index match the current BDLE to process? */
5418 if (u32BDLEIndex == pStrm->State.uCurBDLE)
5419 {
5420 rc = SSMR3GetU32(pSSM, &pStrm->State.BDLE.State.cbBelowFIFOW); /* cbBelowFIFOW */
5421 AssertRC(rc);
5422 rc = SSMR3Skip(pSSM, sizeof(uint8_t) * 256); /* FIFO, deprecated */
5423 AssertRC(rc);
5424 rc = SSMR3GetU32(pSSM, &pStrm->State.BDLE.State.u32BufOff); /* u32BufOff */
5425 AssertRC(rc);
5426 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
5427 AssertRC(rc);
5428 }
5429 else /* Skip not current BDLEs. */
5430 {
5431 rc = SSMR3Skip(pSSM, sizeof(uint32_t) /* cbBelowFIFOW */
5432 + sizeof(uint8_t) * 256 /* FIFO, deprecated */
5433 + sizeof(uint32_t) /* u32BufOff */
5434 + sizeof(uint32_t)); /* End marker */
5435 AssertRC(rc);
5436 }
5437 }
5438 }
5439 else
5440 {
5441 rc = SSMR3GetStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE),
5442 0 /* fFlags */, g_aSSMStreamStateFields6, NULL);
5443 if (RT_FAILURE(rc))
5444 break;
5445
5446 rc = SSMR3GetStructEx(pSSM, &pStrm->State.BDLE.Desc, sizeof(HDABDLEDESC),
5447 0 /* fFlags */, g_aSSMBDLEDescFields6, NULL);
5448 if (RT_FAILURE(rc))
5449 break;
5450
5451 rc = SSMR3GetStructEx(pSSM, &pStrm->State.BDLE.State, sizeof(HDABDLESTATE),
5452 0 /* fFlags */, g_aSSMBDLEStateFields6, NULL);
5453 if (RT_FAILURE(rc))
5454 break;
5455 }
5456 }
5457 break;
5458 }
5459
5460 default:
5461 AssertReleaseFailed(); /* Never reached. */
5462 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
5463 }
5464
5465#undef HDA_SSM_LOAD_BDLE_STATE_PRE_V5
5466
5467 if (RT_SUCCESS(rc))
5468 {
5469 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
5470 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
5471 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
5472
5473 /* Also make sure to update the DMA position bit if this was enabled when saving the state. */
5474 pThis->fDMAPosition = RT_BOOL(pThis->u64DPBase & RT_BIT_64(0));
5475 }
5476
5477 if (RT_SUCCESS(rc))
5478 {
5479 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5480 {
5481 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, i);
5482 if (pStream)
5483 {
5484 hdaStreamEnable(pThis, pStream, false /* fEnable */);
5485
5486 bool fActive = RT_BOOL(HDA_STREAM_REG(pThis, CTL, i) & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN));
5487 if (fActive)
5488 {
5489 int rc2 = hdaStreamEnable(pThis, pStream, true /* fEnable */);
5490 AssertRC(rc2);
5491 }
5492 }
5493 }
5494 }
5495
5496 if (RT_FAILURE(rc))
5497 LogRel(("HDA: Failed loading device state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
5498
5499 LogFlowFuncLeaveRC(rc);
5500 return rc;
5501}
5502
5503#ifdef DEBUG
5504/* Debug and log type formatters. */
5505
5506/**
5507 * @callback_method_impl{FNRTSTRFORMATTYPE}
5508 */
5509static DECLCALLBACK(size_t) hdaDbgFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5510 const char *pszType, void const *pvValue,
5511 int cchWidth, int cchPrecision, unsigned fFlags,
5512 void *pvUser)
5513{
5514 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5515 PHDABDLE pBDLE = (PHDABDLE)pvValue;
5516 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5517 "BDLE(idx:%RU32, off:%RU32, fifow:%RU32, IOC:%RTbool, DMA[%RU32 bytes @ 0x%x])",
5518 pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW,
5519 pBDLE->Desc.fFlags & HDA_BDLE_FLAG_IOC, pBDLE->Desc.u32BufSize, pBDLE->Desc.u64BufAdr);
5520}
5521
5522/**
5523 * @callback_method_impl{FNRTSTRFORMATTYPE}
5524 */
5525static DECLCALLBACK(size_t) hdaDbgFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5526 const char *pszType, void const *pvValue,
5527 int cchWidth, int cchPrecision, unsigned fFlags,
5528 void *pvUser)
5529{
5530 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5531 uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
5532 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5533 "SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
5534 uSDCTL,
5535 (uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DIR)) ? "OUT" : "IN",
5536 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, TP)),
5537 (uSDCTL & HDA_REG_FIELD_MASK(SDCTL, STRIPE)) >> HDA_SDCTL_STRIPE_SHIFT,
5538 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, DEIE)),
5539 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, FEIE)),
5540 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, ICE)),
5541 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN)),
5542 RT_BOOL(uSDCTL & HDA_REG_FIELD_FLAG_MASK(SDCTL, SRST)));
5543}
5544
5545/**
5546 * @callback_method_impl{FNRTSTRFORMATTYPE}
5547 */
5548static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5549 const char *pszType, void const *pvValue,
5550 int cchWidth, int cchPrecision, unsigned fFlags,
5551 void *pvUser)
5552{
5553 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5554 uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
5555 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, uSDFIFOS ? uSDFIFOS + 1 : 0);
5556}
5557
5558/**
5559 * @callback_method_impl{FNRTSTRFORMATTYPE}
5560 */
5561static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5562 const char *pszType, void const *pvValue,
5563 int cchWidth, int cchPrecision, unsigned fFlags,
5564 void *pvUser)
5565{
5566 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5567 uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
5568 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
5569}
5570
5571/**
5572 * @callback_method_impl{FNRTSTRFORMATTYPE}
5573 */
5574static DECLCALLBACK(size_t) hdaDbgFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5575 const char *pszType, void const *pvValue,
5576 int cchWidth, int cchPrecision, unsigned fFlags,
5577 void *pvUser)
5578{
5579 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5580 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
5581 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5582 "SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
5583 uSdSts,
5584 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FIFORDY)),
5585 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, DE)),
5586 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, FE)),
5587 RT_BOOL(uSdSts & HDA_REG_FIELD_FLAG_MASK(SDSTS, BCIS)));
5588}
5589
5590static int hdaDbgLookupRegByName(const char *pszArgs)
5591{
5592 int iReg = 0;
5593 for (; iReg < HDA_NUM_REGS; ++iReg)
5594 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
5595 return iReg;
5596 return -1;
5597}
5598
5599
5600static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
5601{
5602 Assert( pThis
5603 && iHdaIndex >= 0
5604 && iHdaIndex < HDA_NUM_REGS);
5605 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
5606}
5607
5608/**
5609 * @callback_method_impl{FNDBGFHANDLERDEV}
5610 */
5611static DECLCALLBACK(void) hdaDbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5612{
5613 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5614 int iHdaRegisterIndex = hdaDbgLookupRegByName(pszArgs);
5615 if (iHdaRegisterIndex != -1)
5616 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
5617 else
5618 {
5619 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NUM_REGS; ++iHdaRegisterIndex)
5620 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
5621 }
5622}
5623
5624static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
5625{
5626 Assert( pThis
5627 && iIdx >= 0
5628 && iIdx < HDA_MAX_STREAMS);
5629
5630 const PHDASTREAM pStrm = &pThis->aStreams[iIdx];
5631
5632 pHlp->pfnPrintf(pHlp, "Stream #%d:\n", iIdx);
5633 pHlp->pfnPrintf(pHlp, "\tSD%dCTL : %R[sdctl]\n", iIdx, HDA_STREAM_REG(pThis, CTL, iIdx));
5634 pHlp->pfnPrintf(pHlp, "\tSD%dCTS : %R[sdsts]\n", iIdx, HDA_STREAM_REG(pThis, STS, iIdx));
5635 pHlp->pfnPrintf(pHlp, "\tSD%dFIFOS: %R[sdfifos]\n", iIdx, HDA_STREAM_REG(pThis, FIFOS, iIdx));
5636 pHlp->pfnPrintf(pHlp, "\tSD%dFIFOW: %R[sdfifow]\n", iIdx, HDA_STREAM_REG(pThis, FIFOW, iIdx));
5637 pHlp->pfnPrintf(pHlp, "\tBDLE : %R[bdle]\n", &pStrm->State.BDLE);
5638}
5639
5640static void hdaDbgPrintBDLE(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
5641{
5642 Assert( pThis
5643 && iIdx >= 0
5644 && iIdx < HDA_MAX_STREAMS);
5645
5646 const PHDASTREAM pStrm = &pThis->aStreams[iIdx];
5647 const PHDABDLE pBDLE = &pStrm->State.BDLE;
5648
5649 pHlp->pfnPrintf(pHlp, "Stream #%d BDLE:\n", iIdx);
5650
5651 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, iIdx),
5652 HDA_STREAM_REG(pThis, BDPU, iIdx));
5653 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, iIdx);
5654 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, iIdx);
5655
5656 if (!u64BaseDMA)
5657 return;
5658
5659 pHlp->pfnPrintf(pHlp, "\tCurrent: %R[bdle]\n\n", pBDLE);
5660
5661 pHlp->pfnPrintf(pHlp, "\tMemory:\n");
5662
5663 uint32_t cbBDLE = 0;
5664 for (uint16_t i = 0; i < u16LVI + 1; i++)
5665 {
5666 HDABDLEDESC bd;
5667 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i * sizeof(HDABDLEDESC), &bd, sizeof(bd));
5668
5669 pHlp->pfnPrintf(pHlp, "\t\t%s #%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
5670 pBDLE->State.u32BDLIndex == i ? "*" : " ", i, bd.u64BufAdr, bd.u32BufSize, bd.fFlags & HDA_BDLE_FLAG_IOC);
5671
5672 cbBDLE += bd.u32BufSize;
5673 }
5674
5675 pHlp->pfnPrintf(pHlp, "Total: %RU32 bytes\n", cbBDLE);
5676
5677 if (cbBDLE != u32CBL)
5678 pHlp->pfnPrintf(pHlp, "Warning: %RU32 bytes does not match CBL (%RU32)!\n", cbBDLE, u32CBL);
5679
5680 pHlp->pfnPrintf(pHlp, "DMA counters (base @ 0x%llx):\n", u64BaseDMA);
5681 if (!u64BaseDMA) /* No DMA base given? Bail out. */
5682 {
5683 pHlp->pfnPrintf(pHlp, "\tNo counters found\n");
5684 return;
5685 }
5686
5687 for (int i = 0; i < u16LVI + 1; i++)
5688 {
5689 uint32_t uDMACnt;
5690 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
5691 &uDMACnt, sizeof(uDMACnt));
5692
5693 pHlp->pfnPrintf(pHlp, "\t#%03d DMA @ 0x%x\n", i , uDMACnt);
5694 }
5695}
5696
5697static int hdaDbgLookupStrmIdx(PHDASTATE pThis, const char *pszArgs)
5698{
5699 RT_NOREF(pThis, pszArgs);
5700 /** @todo Add args parsing. */
5701 return -1;
5702}
5703
5704/**
5705 * @callback_method_impl{FNDBGFHANDLERDEV}
5706 */
5707static DECLCALLBACK(void) hdaDbgInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5708{
5709 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5710 int iHdaStreamdex = hdaDbgLookupStrmIdx(pThis, pszArgs);
5711 if (iHdaStreamdex != -1)
5712 hdaDbgPrintStream(pThis, pHlp, iHdaStreamdex);
5713 else
5714 for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
5715 hdaDbgPrintStream(pThis, pHlp, iHdaStreamdex);
5716}
5717
5718/**
5719 * @callback_method_impl{FNDBGFHANDLERDEV}
5720 */
5721static DECLCALLBACK(void) hdaDbgInfoBDLE(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5722{
5723 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5724 int iHdaStreamdex = hdaDbgLookupStrmIdx(pThis, pszArgs);
5725 if (iHdaStreamdex != -1)
5726 hdaDbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
5727 else
5728 for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
5729 hdaDbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
5730}
5731
5732/**
5733 * @callback_method_impl{FNDBGFHANDLERDEV}
5734 */
5735static DECLCALLBACK(void) hdaDbgInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5736{
5737 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5738
5739 if (pThis->pCodec->pfnDbgListNodes)
5740 pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
5741 else
5742 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
5743}
5744
5745/**
5746 * @callback_method_impl{FNDBGFHANDLERDEV}
5747 */
5748static DECLCALLBACK(void) hdaDbgInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5749{
5750 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5751
5752 if (pThis->pCodec->pfnDbgSelector)
5753 pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
5754 else
5755 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
5756}
5757
5758/**
5759 * @callback_method_impl{FNDBGFHANDLERDEV}
5760 */
5761static DECLCALLBACK(void) hdaDbgInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5762{
5763 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5764
5765 if (pThis->pMixer)
5766 AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
5767 else
5768 pHlp->pfnPrintf(pHlp, "Mixer not available\n");
5769}
5770#endif /* DEBUG */
5771
5772/* PDMIBASE */
5773
5774/**
5775 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
5776 */
5777static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
5778{
5779 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
5780 Assert(&pThis->IBase == pInterface);
5781
5782 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
5783 return NULL;
5784}
5785
5786
5787/* PDMDEVREG */
5788
5789/**
5790 * Reset notification.
5791 *
5792 * @returns VBox status code.
5793 * @param pDevIns The device instance data.
5794 *
5795 * @remark The original sources didn't install a reset handler, but it seems to
5796 * make sense to me so we'll do it.
5797 */
5798static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
5799{
5800 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5801
5802 LogFlowFuncEnter();
5803
5804# ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
5805 /*
5806 * Stop the timer, if any.
5807 */
5808 hdaTimerStop(pThis);
5809
5810 pThis->cStreamsActive = 0;
5811# endif
5812
5813 /* See 6.2.1. */
5814 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(HDA_MAX_SDO /* Ouput streams */,
5815 HDA_MAX_SDI /* Input streams */,
5816 0 /* Bidirectional output streams */,
5817 0 /* Serial data out signals */,
5818 1 /* 64-bit */);
5819 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
5820 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
5821 /* Announce the full 60 words output payload. */
5822 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
5823 /* Announce the full 29 words input payload. */
5824 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
5825 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
5826 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
5827 HDA_REG(pThis, CORBRP) = 0x0;
5828 HDA_REG(pThis, RIRBWP) = 0x0;
5829
5830 /*
5831 * Stop any audio currently playing and/or recording.
5832 */
5833 if (pThis->SinkFront.pMixSink)
5834 AudioMixerSinkReset(pThis->SinkFront.pMixSink);
5835# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5836 if (pThis->SinkMicIn.pMixSink)
5837 AudioMixerSinkReset(pThis->SinkMicIn.pMixSink);
5838# endif
5839 if (pThis->SinkLineIn.pMixSink)
5840 AudioMixerSinkReset(pThis->SinkLineIn.pMixSink);
5841# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
5842 if (pThis->SinkCenterLFE.pMixSink)
5843 AudioMixerSinkReset(pThis->SinkCenterLFE.pMixSink);
5844 if (pThis->SinkRear.pMixSink)
5845 AudioMixerSinkReset(pThis->SinkRear.pMixSink);
5846# endif
5847
5848 /*
5849 * Reset the codec.
5850 */
5851 if ( pThis->pCodec
5852 && pThis->pCodec->pfnReset)
5853 {
5854 pThis->pCodec->pfnReset(pThis->pCodec);
5855 }
5856
5857 /*
5858 * Set some sensible defaults for which HDA sinks
5859 * are connected to which stream number.
5860 *
5861 * We use SD0 for input and SD4 for output by default.
5862 * These stream numbers can be changed by the guest dynamically lateron.
5863 */
5864#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5865 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_MIC_IN , 1 /* SD0 */, 0 /* Channel */);
5866#endif
5867 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_LINE_IN , 1 /* SD0 */, 0 /* Channel */);
5868
5869 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_FRONT , 5 /* SD4 */, 0 /* Channel */);
5870#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
5871 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_CENTER_LFE, 5 /* SD4 */, 0 /* Channel */);
5872 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_REAR , 5 /* SD4 */, 0 /* Channel */);
5873#endif
5874
5875 pThis->cbCorbBuf = 256 * sizeof(uint32_t); /** @todo Use a define here. */
5876
5877 if (pThis->pu32CorbBuf)
5878 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
5879 else
5880 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
5881
5882 pThis->cbRirbBuf = 256 * sizeof(uint64_t); /** @todo Use a define here. */
5883 if (pThis->pu64RirbBuf)
5884 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
5885 else
5886 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
5887
5888 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
5889
5890 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5891 {
5892 /* Remove the RUN bit from SDnCTL in case the stream was in a running state before. */
5893 HDA_STREAM_REG(pThis, CTL, i) &= ~HDA_REG_FIELD_FLAG_MASK(SDCTL, RUN);
5894 hdaStreamReset(pThis, &pThis->aStreams[i]);
5895 }
5896
5897 /* Clear stream tags <-> objects mapping table. */
5898 RT_ZERO(pThis->aTags);
5899
5900 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
5901 HDA_REG(pThis, STATESTS) = 0x1;
5902
5903 LogFlowFuncLeave();
5904 LogRel(("HDA: Reset\n"));
5905}
5906
5907/**
5908 * @interface_method_impl{PDMDEVREG,pfnDestruct}
5909 */
5910static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
5911{
5912 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5913
5914 PHDADRIVER pDrv;
5915 while (!RTListIsEmpty(&pThis->lstDrv))
5916 {
5917 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
5918
5919 RTListNodeRemove(&pDrv->Node);
5920 RTMemFree(pDrv);
5921 }
5922
5923 if (pThis->pCodec)
5924 {
5925 hdaCodecDestruct(pThis->pCodec);
5926
5927 RTMemFree(pThis->pCodec);
5928 pThis->pCodec = NULL;
5929 }
5930
5931 RTMemFree(pThis->pu32CorbBuf);
5932 pThis->pu32CorbBuf = NULL;
5933
5934 RTMemFree(pThis->pu64RirbBuf);
5935 pThis->pu64RirbBuf = NULL;
5936
5937 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5938 hdaStreamDestroy(pThis, &pThis->aStreams[i]);
5939
5940 return VINF_SUCCESS;
5941}
5942
5943
5944/**
5945 * Attach command, internal version.
5946 *
5947 * This is called to let the device attach to a driver for a specified LUN
5948 * during runtime. This is not called during VM construction, the device
5949 * constructor has to attach to all the available drivers.
5950 *
5951 * @returns VBox status code.
5952 * @param pDevIns The device instance.
5953 * @param pDrv Driver to (re-)use for (re-)attaching to.
5954 * If NULL is specified, a new driver will be created and appended
5955 * to the driver list.
5956 * @param uLUN The logical unit which is being detached.
5957 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5958 */
5959static int hdaAttachInternal(PPDMDEVINS pDevIns, PHDADRIVER pDrv, unsigned uLUN, uint32_t fFlags)
5960{
5961 RT_NOREF(fFlags);
5962 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5963
5964 /*
5965 * Attach driver.
5966 */
5967 char *pszDesc = NULL;
5968 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
5969 AssertReleaseMsgReturn(pszDesc,
5970 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
5971 VERR_NO_MEMORY);
5972
5973 PPDMIBASE pDrvBase;
5974 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
5975 &pThis->IBase, &pDrvBase, pszDesc);
5976 if (RT_SUCCESS(rc))
5977 {
5978 if (pDrv == NULL)
5979 pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
5980 if (pDrv)
5981 {
5982 pDrv->pDrvBase = pDrvBase;
5983 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
5984 AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
5985 pDrv->pHDAState = pThis;
5986 pDrv->uLUN = uLUN;
5987
5988 /*
5989 * For now we always set the driver at LUN 0 as our primary
5990 * host backend. This might change in the future.
5991 */
5992 if (pDrv->uLUN == 0)
5993 pDrv->Flags |= PDMAUDIODRVFLAGS_PRIMARY;
5994
5995 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->Flags));
5996
5997 /* Attach to driver list if not attached yet. */
5998 if (!pDrv->fAttached)
5999 {
6000 RTListAppend(&pThis->lstDrv, &pDrv->Node);
6001 pDrv->fAttached = true;
6002 }
6003 }
6004 else
6005 rc = VERR_NO_MEMORY;
6006 }
6007 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
6008 LogFunc(("No attached driver for LUN #%u\n", uLUN));
6009
6010 if (RT_FAILURE(rc))
6011 {
6012 /* Only free this string on failure;
6013 * must remain valid for the live of the driver instance. */
6014 RTStrFree(pszDesc);
6015 }
6016
6017 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
6018 return rc;
6019}
6020
6021/**
6022 * Attach command.
6023 *
6024 * This is called to let the device attach to a driver for a specified LUN
6025 * during runtime. This is not called during VM construction, the device
6026 * constructor has to attach to all the available drivers.
6027 *
6028 * @returns VBox status code.
6029 * @param pDevIns The device instance.
6030 * @param uLUN The logical unit which is being detached.
6031 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
6032 */
6033static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
6034{
6035 return hdaAttachInternal(pDevIns, NULL /* pDrv */, uLUN, fFlags);
6036}
6037
6038static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
6039{
6040 RT_NOREF(pDevIns, uLUN, fFlags);
6041 LogFunc(("iLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
6042}
6043
6044/**
6045 * Powers off the device.
6046 *
6047 * @param pDevIns Device instance to power off.
6048 */
6049static DECLCALLBACK(void) hdaPowerOff(PPDMDEVINS pDevIns)
6050{
6051 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
6052
6053 LogRel2(("HDA: Powering off ...\n"));
6054
6055 /* Ditto goes for the codec, which in turn uses the mixer. */
6056 hdaCodecPowerOff(pThis->pCodec);
6057
6058 /**
6059 * Note: Destroy the mixer while powering off and *not* in hdaDestruct,
6060 * giving the mixer the chance to release any references held to
6061 * PDM audio streams it maintains.
6062 */
6063 if (pThis->pMixer)
6064 {
6065 AudioMixerDestroy(pThis->pMixer);
6066 pThis->pMixer = NULL;
6067 }
6068}
6069
6070/**
6071 * Re-attaches a new driver to the device's driver chain.
6072 *
6073 * @returns VBox status code.
6074 * @param pThis Device instance to re-attach driver to.
6075 * @param pDrv Driver instance used for attaching to.
6076 * If NULL is specified, a new driver will be created and appended
6077 * to the driver list.
6078 * @param uLUN The logical unit which is being re-detached.
6079 * @param pszDriver Driver name.
6080 */
6081static int hdaReattach(PHDASTATE pThis, PHDADRIVER pDrv, uint8_t uLUN, const char *pszDriver)
6082{
6083 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
6084 AssertPtrReturn(pszDriver, VERR_INVALID_POINTER);
6085
6086 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
6087 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
6088 PCFGMNODE pDev0 = CFGMR3GetChild(pRoot, "Devices/hda/0/");
6089
6090 /* Remove LUN branch. */
6091 CFGMR3RemoveNode(CFGMR3GetChildF(pDev0, "LUN#%u/", uLUN));
6092
6093 if (pDrv)
6094 {
6095 /* Re-use a driver instance => detach the driver before. */
6096 int rc = PDMDevHlpDriverDetach(pThis->pDevInsR3, PDMIBASE_2_PDMDRV(pDrv->pDrvBase), 0 /* fFlags */);
6097 if (RT_FAILURE(rc))
6098 return rc;
6099 }
6100
6101#define RC_CHECK() if (RT_FAILURE(rc)) { AssertReleaseRC(rc); break; }
6102
6103 int rc = VINF_SUCCESS;
6104 do
6105 {
6106 PCFGMNODE pLunL0;
6107 rc = CFGMR3InsertNodeF(pDev0, &pLunL0, "LUN#%u/", uLUN); RC_CHECK();
6108 rc = CFGMR3InsertString(pLunL0, "Driver", "AUDIO"); RC_CHECK();
6109 rc = CFGMR3InsertNode(pLunL0, "Config/", NULL); RC_CHECK();
6110
6111 PCFGMNODE pLunL1, pLunL2;
6112 rc = CFGMR3InsertNode (pLunL0, "AttachedDriver/", &pLunL1); RC_CHECK();
6113 rc = CFGMR3InsertNode (pLunL1, "Config/", &pLunL2); RC_CHECK();
6114 rc = CFGMR3InsertString(pLunL1, "Driver", pszDriver); RC_CHECK();
6115
6116 rc = CFGMR3InsertString(pLunL2, "AudioDriver", pszDriver); RC_CHECK();
6117
6118 } while (0);
6119
6120 if (RT_SUCCESS(rc))
6121 rc = hdaAttachInternal(pThis->pDevInsR3, pDrv, uLUN, 0 /* fFlags */);
6122
6123 LogFunc(("pThis=%p, uLUN=%u, pszDriver=%s, rc=%Rrc\n", pThis, uLUN, pszDriver, rc));
6124
6125#undef RC_CHECK
6126
6127 return rc;
6128}
6129
6130/**
6131 * @interface_method_impl{PDMDEVREG,pfnConstruct}
6132 */
6133static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
6134{
6135 RT_NOREF(iInstance);
6136 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
6137 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
6138 Assert(iInstance == 0);
6139
6140 /*
6141 * Validations.
6142 */
6143 if (!CFGMR3AreValuesValid(pCfg, "R0Enabled\0"
6144 "RCEnabled\0"
6145 "TimerHz\0"))
6146 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
6147 N_ ("Invalid configuration for the Intel HDA device"));
6148
6149 int rc = CFGMR3QueryBoolDef(pCfg, "RCEnabled", &pThis->fRCEnabled, false);
6150 if (RT_FAILURE(rc))
6151 return PDMDEV_SET_ERROR(pDevIns, rc,
6152 N_("HDA configuration error: failed to read RCEnabled as boolean"));
6153 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, false);
6154 if (RT_FAILURE(rc))
6155 return PDMDEV_SET_ERROR(pDevIns, rc,
6156 N_("HDA configuration error: failed to read R0Enabled as boolean"));
6157#ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
6158 uint16_t uTimerHz;
6159 rc = CFGMR3QueryU16Def(pCfg, "TimerHz", &uTimerHz, HDA_TIMER_HZ /* Default value, if not set. */);
6160 if (RT_FAILURE(rc))
6161 return PDMDEV_SET_ERROR(pDevIns, rc,
6162 N_("HDA configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
6163#endif
6164
6165 /*
6166 * Initialize data (most of it anyway).
6167 */
6168 pThis->pDevInsR3 = pDevIns;
6169 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
6170 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
6171 /* IBase */
6172 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
6173
6174 /* PCI Device */
6175 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
6176 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
6177
6178 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
6179 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
6180 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
6181 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
6182 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
6183 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
6184 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
6185 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
6186 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
6187 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
6188 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
6189
6190#if defined(HDA_AS_PCI_EXPRESS)
6191 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
6192#elif defined(VBOX_WITH_MSI_DEVICES)
6193 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
6194#else
6195 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
6196#endif
6197
6198 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
6199 /// of these values needs to be properly documented!
6200 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
6201 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
6202
6203 /* Power Management */
6204 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
6205 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
6206 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
6207
6208#ifdef HDA_AS_PCI_EXPRESS
6209 /* PCI Express */
6210 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
6211 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
6212 /* Device flags */
6213 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
6214 /* version */ 0x1 |
6215 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
6216 /* MSI */ (100) << 9 );
6217 /* Device capabilities */
6218 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
6219 /* Device control */
6220 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
6221 /* Device status */
6222 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
6223 /* Link caps */
6224 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
6225 /* Link control */
6226 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
6227 /* Link status */
6228 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
6229 /* Slot capabilities */
6230 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
6231 /* Slot control */
6232 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
6233 /* Slot status */
6234 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
6235 /* Root control */
6236 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
6237 /* Root capabilities */
6238 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
6239 /* Root status */
6240 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
6241 /* Device capabilities 2 */
6242 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
6243 /* Device control 2 */
6244 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
6245 /* Link control 2 */
6246 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
6247 /* Slot control 2 */
6248 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
6249#endif
6250
6251 /*
6252 * Register the PCI device.
6253 */
6254 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
6255 if (RT_FAILURE(rc))
6256 return rc;
6257
6258 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
6259 if (RT_FAILURE(rc))
6260 return rc;
6261
6262#ifdef VBOX_WITH_MSI_DEVICES
6263 PDMMSIREG MsiReg;
6264 RT_ZERO(MsiReg);
6265 MsiReg.cMsiVectors = 1;
6266 MsiReg.iMsiCapOffset = 0x60;
6267 MsiReg.iMsiNextOffset = 0x50;
6268 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
6269 if (RT_FAILURE(rc))
6270 {
6271 /* That's OK, we can work without MSI */
6272 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
6273 }
6274#endif
6275
6276 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
6277 if (RT_FAILURE(rc))
6278 return rc;
6279
6280 RTListInit(&pThis->lstDrv);
6281
6282#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
6283 LogRel(("HDA: Asynchronous I/O enabled\n"));
6284#endif
6285
6286 uint8_t uLUN;
6287 for (uLUN = 0; uLUN < UINT8_MAX; ++uLUN)
6288 {
6289 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
6290 rc = hdaAttachInternal(pDevIns, NULL /* pDrv */, uLUN, 0 /* fFlags */);
6291 if (RT_FAILURE(rc))
6292 {
6293 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
6294 rc = VINF_SUCCESS;
6295 else if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
6296 {
6297 hdaReattach(pThis, NULL /* pDrv */, uLUN, "NullAudio");
6298 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
6299 N_("Host audio backend initialization has failed. Selecting the NULL audio backend "
6300 "with the consequence that no sound is audible"));
6301 /* Attaching to the NULL audio backend will never fail. */
6302 rc = VINF_SUCCESS;
6303 }
6304 break;
6305 }
6306 }
6307
6308 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
6309
6310 if (RT_SUCCESS(rc))
6311 {
6312 rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
6313 if (RT_SUCCESS(rc))
6314 {
6315 /*
6316 * Add mixer output sinks.
6317 */
6318#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
6319 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Front",
6320 AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
6321 AssertRC(rc);
6322 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Center / Subwoofer",
6323 AUDMIXSINKDIR_OUTPUT, &pThis->SinkCenterLFE.pMixSink);
6324 AssertRC(rc);
6325 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Rear",
6326 AUDMIXSINKDIR_OUTPUT, &pThis->SinkRear.pMixSink);
6327 AssertRC(rc);
6328#else
6329 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] PCM Output",
6330 AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
6331 AssertRC(rc);
6332#endif
6333 /*
6334 * Add mixer input sinks.
6335 */
6336 rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Line In",
6337 AUDMIXSINKDIR_INPUT, &pThis->SinkLineIn.pMixSink);
6338 AssertRC(rc);
6339#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
6340 rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Microphone In",
6341 AUDMIXSINKDIR_INPUT, &pThis->SinkMicIn.pMixSink);
6342 AssertRC(rc);
6343#endif
6344 /* There is no master volume control. Set the master to max. */
6345 PDMAUDIOVOLUME vol = { false, 255, 255 };
6346 rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
6347 AssertRC(rc);
6348 }
6349 }
6350
6351 if (RT_SUCCESS(rc))
6352 {
6353 /* Construct codec. */
6354 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
6355 if (!pThis->pCodec)
6356 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
6357
6358 /* Set codec callbacks to this controller. */
6359 pThis->pCodec->pfnCbMixerAddStream = hdaMixerAddStream;
6360 pThis->pCodec->pfnCbMixerRemoveStream = hdaMixerRemoveStream;
6361 pThis->pCodec->pfnCbMixerSetStream = hdaMixerSetStream;
6362 pThis->pCodec->pfnCbMixerSetVolume = hdaMixerSetVolume;
6363
6364 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
6365
6366 /* Construct the codec. */
6367 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfg);
6368 if (RT_FAILURE(rc))
6369 AssertRCReturn(rc, rc);
6370
6371 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
6372 verb F20 should provide device/codec recognition. */
6373 Assert(pThis->pCodec->u16VendorId);
6374 Assert(pThis->pCodec->u16DeviceId);
6375 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
6376 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
6377 }
6378
6379 if (RT_SUCCESS(rc))
6380 {
6381 /*
6382 * Create all hardware streams.
6383 */
6384 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
6385 {
6386 rc = hdaStreamCreate(pThis, &pThis->aStreams[i], i /* uSD */);
6387 AssertRC(rc);
6388 }
6389
6390#ifdef VBOX_WITH_AUDIO_HDA_ONETIME_INIT
6391 /*
6392 * Initialize the driver chain.
6393 */
6394 PHDADRIVER pDrv;
6395 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
6396 {
6397 /*
6398 * Only primary drivers are critical for the VM to run. Everything else
6399 * might not worth showing an own error message box in the GUI.
6400 */
6401 if (!(pDrv->Flags & PDMAUDIODRVFLAGS_PRIMARY))
6402 continue;
6403
6404 PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
6405 AssertPtr(pCon);
6406
6407 bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
6408# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
6409 bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
6410# endif
6411 bool fValidOut = AudioMixerStreamIsValid(pDrv->Front.pMixStrm);
6412# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
6413 /** @todo Anything to do here? */
6414# endif
6415
6416 if ( !fValidLineIn
6417# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
6418 && !fValidMicIn
6419# endif
6420 && !fValidOut)
6421 {
6422 LogRel(("HDA: Falling back to NULL backend (no sound audible)\n"));
6423
6424 hdaReset(pDevIns);
6425 hdaReattach(pThis, pDrv, pDrv->uLUN, "NullAudio");
6426
6427 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
6428 N_("No audio devices could be opened. Selecting the NULL audio backend "
6429 "with the consequence that no sound is audible"));
6430 }
6431 else
6432 {
6433 bool fWarn = false;
6434
6435 PDMAUDIOBACKENDCFG backendCfg;
6436 int rc2 = pCon->pfnGetConfig(pCon, &backendCfg);
6437 if (RT_SUCCESS(rc2))
6438 {
6439 if (backendCfg.cMaxStreamsIn)
6440 {
6441# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
6442 /* If the audio backend supports two or more input streams at once,
6443 * warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
6444 if (backendCfg.cMaxStreamsIn >= 2)
6445 fWarn = !fValidLineIn || !fValidMicIn;
6446 /* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
6447 * *not* ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
6448 * One of the two simply is not in use then. */
6449 else if (backendCfg.cMaxStreamsIn == 1)
6450 fWarn = !fValidLineIn && !fValidMicIn;
6451 /* Don't warn if our backend is not able of supporting any input streams at all. */
6452# else /* !VBOX_WITH_AUDIO_HDA_MIC_IN */
6453 /* We only have line-in as input source. */
6454 fWarn = !fValidLineIn;
6455# endif /* VBOX_WITH_AUDIO_HDA_MIC_IN */
6456 }
6457
6458 if ( !fWarn
6459 && backendCfg.cMaxStreamsOut)
6460 {
6461 fWarn = !fValidOut;
6462 }
6463 }
6464 else
6465 {
6466 LogRel(("HDA: Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
6467 fWarn = true;
6468 }
6469
6470 if (fWarn)
6471 {
6472 char szMissingStreams[255];
6473 size_t len = 0;
6474 if (!fValidLineIn)
6475 {
6476 LogRel(("HDA: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
6477 len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
6478 }
6479# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
6480 if (!fValidMicIn)
6481 {
6482 LogRel(("HDA: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
6483 len += RTStrPrintf(szMissingStreams + len,
6484 sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
6485 }
6486# endif /* VBOX_WITH_AUDIO_HDA_MIC_IN */
6487 if (!fValidOut)
6488 {
6489 LogRel(("HDA: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
6490 len += RTStrPrintf(szMissingStreams + len,
6491 sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
6492 }
6493
6494 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
6495 N_("Some HDA audio streams (%s) could not be opened. Guest applications generating audio "
6496 "output or depending on audio input may hang. Make sure your host audio device "
6497 "is working properly. Check the logfile for error messages of the audio "
6498 "subsystem"), szMissingStreams);
6499 }
6500 }
6501 }
6502#endif /* VBOX_WITH_AUDIO_HDA_ONETIME_INIT */
6503 }
6504
6505 if (RT_SUCCESS(rc))
6506 {
6507 hdaReset(pDevIns);
6508
6509 /*
6510 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
6511 * hdaReset shouldn't affects these registers.
6512 */
6513 HDA_REG(pThis, WAKEEN) = 0x0;
6514 HDA_REG(pThis, STATESTS) = 0x0;
6515
6516#ifdef DEBUG
6517 /*
6518 * Debug and string formatter types.
6519 */
6520 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaDbgInfo);
6521 PDMDevHlpDBGFInfoRegister(pDevIns, "hdabdle", "HDA stream BDLE info. (hdabdle [stream number])", hdaDbgInfoBDLE);
6522 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaDbgInfoStream);
6523 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaDbgInfoCodecNodes);
6524 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaDbgInfoCodecSelector);
6525 PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaDbgInfoMixer);
6526
6527 rc = RTStrFormatTypeRegister("bdle", hdaDbgFmtBDLE, NULL);
6528 AssertRC(rc);
6529 rc = RTStrFormatTypeRegister("sdctl", hdaDbgFmtSDCTL, NULL);
6530 AssertRC(rc);
6531 rc = RTStrFormatTypeRegister("sdsts", hdaDbgFmtSDSTS, NULL);
6532 AssertRC(rc);
6533 rc = RTStrFormatTypeRegister("sdfifos", hdaDbgFmtSDFIFOS, NULL);
6534 AssertRC(rc);
6535 rc = RTStrFormatTypeRegister("sdfifow", hdaDbgFmtSDFIFOW, NULL);
6536 AssertRC(rc);
6537#endif /* DEBUG */
6538
6539 /*
6540 * Some debug assertions.
6541 */
6542 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
6543 {
6544 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
6545 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
6546
6547 /* binary search order. */
6548 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
6549 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6550 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
6551
6552 /* alignment. */
6553 AssertReleaseMsg( pReg->size == 1
6554 || (pReg->size == 2 && (pReg->offset & 1) == 0)
6555 || (pReg->size == 3 && (pReg->offset & 3) == 0)
6556 || (pReg->size == 4 && (pReg->offset & 3) == 0),
6557 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6558
6559 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
6560 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
6561 if (pReg->offset & 3)
6562 {
6563 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
6564 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6565 if (pPrevReg)
6566 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
6567 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6568 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
6569 }
6570#if 0
6571 if ((pReg->offset + pReg->size) & 3)
6572 {
6573 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6574 if (pNextReg)
6575 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
6576 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6577 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
6578 }
6579#endif
6580 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
6581 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
6582 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6583 }
6584 }
6585
6586# ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
6587 if (RT_SUCCESS(rc))
6588 {
6589 /* Create the emulation timer. */
6590 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
6591 TMTIMER_FLAGS_NO_CRIT_SECT, "DevHDA", &pThis->pTimer);
6592 AssertRCReturn(rc, rc);
6593
6594 if (RT_SUCCESS(rc))
6595 {
6596 pThis->cTimerTicks = TMTimerGetFreq(pThis->pTimer) / uTimerHz;
6597 pThis->uTimerTS = TMTimerGet(pThis->pTimer);
6598 LogFunc(("Timer ticks=%RU64 (%RU16 Hz)\n", pThis->cTimerTicks, uTimerHz));
6599 }
6600 }
6601# else
6602 if (RT_SUCCESS(rc))
6603 {
6604 PHDADRIVER pDrv;
6605 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
6606 {
6607 /* Only register primary driver.
6608 * The device emulation does the output multiplexing then. */
6609 if (pDrv->Flags != PDMAUDIODRVFLAGS_PRIMARY)
6610 continue;
6611
6612 PDMAUDIOCALLBACK AudioCallbacks[2];
6613
6614 HDACALLBACKCTX Ctx = { pThis, pDrv };
6615
6616 AudioCallbacks[0].enmType = PDMAUDIOCALLBACKTYPE_INPUT;
6617 AudioCallbacks[0].pfnCallback = hdaCallbackInput;
6618 AudioCallbacks[0].pvCtx = &Ctx;
6619 AudioCallbacks[0].cbCtx = sizeof(HDACALLBACKCTX);
6620
6621 AudioCallbacks[1].enmType = PDMAUDIOCALLBACKTYPE_OUTPUT;
6622 AudioCallbacks[1].pfnCallback = hdaCallbackOutput;
6623 AudioCallbacks[1].pvCtx = &Ctx;
6624 AudioCallbacks[1].cbCtx = sizeof(HDACALLBACKCTX);
6625
6626 rc = pDrv->pConnector->pfnRegisterCallbacks(pDrv->pConnector, AudioCallbacks, RT_ELEMENTS(AudioCallbacks));
6627 if (RT_FAILURE(rc))
6628 break;
6629 }
6630 }
6631# endif
6632
6633# ifdef VBOX_WITH_STATISTICS
6634 if (RT_SUCCESS(rc))
6635 {
6636 /*
6637 * Register statistics.
6638 */
6639# ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
6640 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
6641# endif
6642 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIn, STAMTYPE_PROFILE, "/Devices/HDA/Input", STAMUNIT_TICKS_PER_CALL, "Profiling input.");
6643 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatOut, STAMTYPE_PROFILE, "/Devices/HDA/Output", STAMUNIT_TICKS_PER_CALL, "Profiling output.");
6644 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
6645 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
6646 }
6647# endif
6648
6649#ifdef HDA_DEBUG_DUMP_PCM_DATA
6650 RTFileDelete(HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaDMARead.pcm");
6651 RTFileDelete(HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaDMAWrite.pcm");
6652 RTFileDelete(HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaStreamRead.pcm");
6653 RTFileDelete(HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaStreamWrite.pcm");
6654#endif
6655
6656 LogFlowFuncLeaveRC(rc);
6657 return rc;
6658}
6659
6660/**
6661 * The device registration structure.
6662 */
6663const PDMDEVREG g_DeviceHDA =
6664{
6665 /* u32Version */
6666 PDM_DEVREG_VERSION,
6667 /* szName */
6668 "hda",
6669 /* szRCMod */
6670 "VBoxDDRC.rc",
6671 /* szR0Mod */
6672 "VBoxDDR0.r0",
6673 /* pszDescription */
6674 "Intel HD Audio Controller",
6675 /* fFlags */
6676 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
6677 /* fClass */
6678 PDM_DEVREG_CLASS_AUDIO,
6679 /* cMaxInstances */
6680 1,
6681 /* cbInstance */
6682 sizeof(HDASTATE),
6683 /* pfnConstruct */
6684 hdaConstruct,
6685 /* pfnDestruct */
6686 hdaDestruct,
6687 /* pfnRelocate */
6688 NULL,
6689 /* pfnMemSetup */
6690 NULL,
6691 /* pfnPowerOn */
6692 NULL,
6693 /* pfnReset */
6694 hdaReset,
6695 /* pfnSuspend */
6696 NULL,
6697 /* pfnResume */
6698 NULL,
6699 /* pfnAttach */
6700 hdaAttach,
6701 /* pfnDetach */
6702 hdaDetach,
6703 /* pfnQueryInterface. */
6704 NULL,
6705 /* pfnInitComplete */
6706 NULL,
6707 /* pfnPowerOff */
6708 hdaPowerOff,
6709 /* pfnSoftReset */
6710 NULL,
6711 /* u32VersionEnd */
6712 PDM_DEVREG_VERSION
6713};
6714
6715#endif /* IN_RING3 */
6716#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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