VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevHDA.cpp@ 67308

Last change on this file since 67308 was 67265, checked in by vboxsync, 8 years ago

HDA: Enabled info callbacks for release builds as well.
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1/* $Id: DevHDA.cpp 67265 2017-06-06 09:36:12Z vboxsync $ */
2/** @file
3 * DevHDA - VBox Intel HD Audio Controller.
4 *
5 * Implemented against the specifications found in "High Definition Audio
6 * Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7 * HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8 */
9
10/*
11 * Copyright (C) 2006-2017 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22
23/*********************************************************************************************************************************
24* Header Files *
25*********************************************************************************************************************************/
26#define LOG_GROUP LOG_GROUP_DEV_HDA
27#include <VBox/log.h>
28#include <VBox/vmm/pdmdev.h>
29#include <VBox/vmm/pdmaudioifs.h>
30#include <VBox/version.h>
31
32#include <iprt/assert.h>
33#include <iprt/asm.h>
34#include <iprt/asm-math.h>
35#include <iprt/file.h>
36#include <iprt/list.h>
37#ifdef IN_RING3
38# include <iprt/mem.h>
39# include <iprt/semaphore.h>
40# include <iprt/string.h>
41# include <iprt/uuid.h>
42#endif
43
44#include "VBoxDD.h"
45
46#include "AudioMixBuffer.h"
47#include "AudioMixer.h"
48#include "HDACodec.h"
49#include "DevHDACommon.h"
50#include "DrvAudio.h"
51
52
53/*********************************************************************************************************************************
54* Defined Constants And Macros *
55*********************************************************************************************************************************/
56//#define HDA_AS_PCI_EXPRESS
57#define VBOX_WITH_INTEL_HDA
58
59/*
60 * HDA_DEBUG_DUMP_PCM_DATA enables dumping the raw PCM data
61 * to a file on the host. Be sure to adjust HDA_DEBUG_DUMP_PCM_DATA_PATH
62 * to your needs before using this!
63 */
64//#define HDA_DEBUG_DUMP_PCM_DATA
65#ifdef HDA_DEBUG_DUMP_PCM_DATA
66# ifdef RT_OS_WINDOWS
67# define HDA_DEBUG_DUMP_PCM_DATA_PATH "c:\\temp\\"
68# else
69# define HDA_DEBUG_DUMP_PCM_DATA_PATH "/tmp/"
70# endif
71#endif
72
73#if defined(VBOX_WITH_HP_HDA)
74/* HP Pavilion dv4t-1300 */
75# define HDA_PCI_VENDOR_ID 0x103c
76# define HDA_PCI_DEVICE_ID 0x30f7
77#elif defined(VBOX_WITH_INTEL_HDA)
78/* Intel HDA controller */
79# define HDA_PCI_VENDOR_ID 0x8086
80# define HDA_PCI_DEVICE_ID 0x2668
81#elif defined(VBOX_WITH_NVIDIA_HDA)
82/* nVidia HDA controller */
83# define HDA_PCI_VENDOR_ID 0x10de
84# define HDA_PCI_DEVICE_ID 0x0ac0
85#else
86# error "Please specify your HDA device vendor/device IDs"
87#endif
88
89/** @todo r=bird: Looking at what the linux driver (accidentally?) does when
90 * updating CORBWP, I belive that the ICH6 datahsheet is wrong and that CORBRP
91 * is read only except for bit 15 like the HDA spec states.
92 *
93 * Btw. the CORBRPRST implementation is incomplete according to both docs (sw
94 * writes 1, hw sets it to 1 (after completion), sw reads 1, sw writes 0). */
95#define BIRD_THINKS_CORBRP_IS_MOSTLY_RO
96
97/* Make sure that interleaving streams support is enabled if the 5.1 surround code is being used. */
98#if defined (VBOX_WITH_AUDIO_HDA_51_SURROUND) && !defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT)
99# define VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT
100#endif
101
102/** Default timer frequency (in Hz). */
103#define HDA_TIMER_HZ 100
104
105/**
106 * At the moment we support 4 input + 4 output streams max, which is 8 in total.
107 * Bidirectional streams are currently *not* supported.
108 *
109 * Note: When changing any of those values, be prepared for some saved state
110 * fixups / trouble!
111 */
112#define HDA_MAX_SDI 4
113#define HDA_MAX_SDO 4
114#define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
115AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
116
117/** Number of general registers. */
118#define HDA_NUM_GENERAL_REGS 34
119/** Number of total registers in the HDA's register map. */
120#define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */))
121/** Total number of stream tags (channels). Index 0 is reserved / invalid. */
122#define HDA_MAX_TAGS 16
123
124/**
125 * NB: Register values stored in memory (au32Regs[]) are indexed through
126 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
127 * register descriptors in g_aHdaRegMap[] are indexed through the
128 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
129 *
130 * The au32Regs[] layout is kept unchanged for saved state
131 * compatibility.
132 */
133
134/* Registers */
135#define HDA_REG_IND_NAME(x) HDA_REG_##x
136#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
137#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
138#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
139
140
141#define HDA_REG_GCAP 0 /* range 0x00-0x01*/
142#define HDA_RMX_GCAP 0
143/* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
144 * oss (15:12) - number of output streams supported
145 * iss (11:8) - number of input streams supported
146 * bss (7:3) - number of bidirectional streams supported
147 * bds (2:1) - number of serial data out (SDO) signals supported
148 * b64sup (0) - 64 bit addressing supported.
149 */
150#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
151 ( (((oss) & 0xF) << 12) \
152 | (((iss) & 0xF) << 8) \
153 | (((bss) & 0x1F) << 3) \
154 | (((bds) & 0x3) << 1) \
155 | ((b64sup) & 1))
156
157#define HDA_REG_VMIN 1 /* 0x02 */
158#define HDA_RMX_VMIN 1
159
160#define HDA_REG_VMAJ 2 /* 0x03 */
161#define HDA_RMX_VMAJ 2
162
163#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
164#define HDA_RMX_OUTPAY 3
165
166#define HDA_REG_INPAY 4 /* 0x06-0x07 */
167#define HDA_RMX_INPAY 4
168
169#define HDA_REG_GCTL 5 /* 0x08-0x0B */
170#define HDA_RMX_GCTL 5
171#define HDA_GCTL_UNSOL RT_BIT(8) /* Accept Unsolicited Response Enable */
172#define HDA_GCTL_FCNTRL RT_BIT(1) /* Flush Control */
173#define HDA_GCTL_CRST RT_BIT(0) /* Controller Reset */
174
175#define HDA_REG_WAKEEN 6 /* 0x0C */
176#define HDA_RMX_WAKEEN 6
177
178#define HDA_REG_STATESTS 7 /* 0x0E */
179#define HDA_RMX_STATESTS 7
180#define HDA_STATESTS_SCSF_MASK 0x7 /* State Change Status Flags (6.2.8). */
181
182#define HDA_REG_GSTS 8 /* 0x10-0x11*/
183#define HDA_RMX_GSTS 8
184#define HDA_GSTS_FSTS RT_BIT(1) /* Flush Status */
185
186#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
187#define HDA_RMX_OUTSTRMPAY 112
188
189#define HDA_REG_INSTRMPAY 10 /* 0x1a */
190#define HDA_RMX_INSTRMPAY 113
191
192#define HDA_REG_INTCTL 11 /* 0x20 */
193#define HDA_RMX_INTCTL 9
194#define HDA_INTCTL_GIE RT_BIT(31) /* Global Interrupt Enable */
195#define HDA_INTCTL_CIE RT_BIT(30) /* Controller Interrupt Enable */
196/* Bits 0-29 correspond to streams 0-29. */
197
198#define HDA_REG_INTSTS 12 /* 0x24 */
199#define HDA_RMX_INTSTS 10
200#define HDA_INTSTS_GIS RT_BIT(31) /* Global Interrupt Status */
201#define HDA_INTSTS_CIS RT_BIT(30) /* Controller Interrupt Status */
202/* Bits 0-29 correspond to streams 0-29. */
203
204#define HDA_REG_WALCLK 13 /* 0x30 */
205/* NB: HDA_RMX_WALCLK is not defined because the register is not stored in memory. */
206
207/* Note: The HDA specification defines a SSYNC register at offset 0x38. The
208 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
209 * the datasheet.
210 */
211#define HDA_REG_SSYNC 14 /* 0x34 */
212#define HDA_RMX_SSYNC 12
213
214#define HDA_REG_CORBLBASE 15 /* 0x40 */
215#define HDA_RMX_CORBLBASE 13
216
217#define HDA_REG_CORBUBASE 16 /* 0x44 */
218#define HDA_RMX_CORBUBASE 14
219
220#define HDA_REG_CORBWP 17 /* 0x48 */
221#define HDA_RMX_CORBWP 15
222
223#define HDA_REG_CORBRP 18 /* 0x4A */
224#define HDA_RMX_CORBRP 16
225#define HDA_CORBRP_RST RT_BIT(15) /* CORB Read Pointer Reset */
226
227#define HDA_REG_CORBCTL 19 /* 0x4C */
228#define HDA_RMX_CORBCTL 17
229#define HDA_CORBCTL_DMA RT_BIT(1) /* Enable CORB DMA Engine */
230#define HDA_CORBCTL_CMEIE RT_BIT(0) /* CORB Memory Error Interrupt Enable */
231
232#define HDA_REG_CORBSTS 20 /* 0x4D */
233#define HDA_RMX_CORBSTS 18
234
235#define HDA_REG_CORBSIZE 21 /* 0x4E */
236#define HDA_RMX_CORBSIZE 19
237/* NB: Up to and including ICH 10, sizes of CORB and RIRB are fixed at 256 entries. */
238
239#define HDA_REG_RIRBLBASE 22 /* 0x50 */
240#define HDA_RMX_RIRBLBASE 20
241
242#define HDA_REG_RIRBUBASE 23 /* 0x54 */
243#define HDA_RMX_RIRBUBASE 21
244
245#define HDA_REG_RIRBWP 24 /* 0x58 */
246#define HDA_RMX_RIRBWP 22
247#define HDA_RIRBWP_RST RT_BIT(15) /* RIRB Write Pointer Reset */
248
249#define HDA_REG_RINTCNT 25 /* 0x5A */
250#define HDA_RMX_RINTCNT 23
251#define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
252
253#define HDA_REG_RIRBCTL 26 /* 0x5C */
254#define HDA_RMX_RIRBCTL 24
255#define HDA_RIRBCTL_ROIC RT_BIT(2) /* Response Overrun Interrupt Control */
256#define HDA_RIRBCTL_RDMAEN RT_BIT(1) /* RIRB DMA Enable */
257#define HDA_RIRBCTL_RINTCTL RT_BIT(0) /* Response Interrupt Control */
258
259#define HDA_REG_RIRBSTS 27 /* 0x5D */
260#define HDA_RMX_RIRBSTS 25
261#define HDA_RIRBSTS_RIRBOIS RT_BIT(2) /* Response Overrun Interrupt Status */
262#define HDA_RIRBSTS_RINTFL RT_BIT(0) /* Response Interrupt Flag */
263
264#define HDA_REG_RIRBSIZE 28 /* 0x5E */
265#define HDA_RMX_RIRBSIZE 26
266
267#define HDA_REG_IC 29 /* 0x60 */
268#define HDA_RMX_IC 27
269
270#define HDA_REG_IR 30 /* 0x64 */
271#define HDA_RMX_IR 28
272
273#define HDA_REG_IRS 31 /* 0x68 */
274#define HDA_RMX_IRS 29
275#define HDA_IRS_IRV RT_BIT(1) /* Immediate Result Valid */
276#define HDA_IRS_ICB RT_BIT(0) /* Immediate Command Busy */
277
278#define HDA_REG_DPLBASE 32 /* 0x70 */
279#define HDA_RMX_DPLBASE 30
280
281#define HDA_REG_DPUBASE 33 /* 0x74 */
282#define HDA_RMX_DPUBASE 31
283
284#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
285
286#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
287#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
288/* Note: sdnum here _MUST_ be stream reg number [0,7]. */
289#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
290
291#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
292
293/** @todo Condense marcos! */
294
295#define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80; other streams offset by 0x20 */
296#define HDA_RMX_SD0CTL 32
297#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
298#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
299#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
300#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
301#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
302#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
303#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
304
305#define HDA_SDCTL_NUM_MASK 0xF
306#define HDA_SDCTL_NUM_SHIFT 20
307#define HDA_SDCTL_DIR RT_BIT(19) /* Direction (Bidirectional streams only!) */
308#define HDA_SDCTL_TP RT_BIT(18) /* Traffic Priority (PCI Express) */
309#define HDA_SDCTL_STRIPE_MASK 0x3
310#define HDA_SDCTL_STRIPE_SHIFT 16
311#define HDA_SDCTL_DEIE RT_BIT(4) /* Descriptor Error Interrupt Enable */
312#define HDA_SDCTL_FEIE RT_BIT(3) /* FIFO Error Interrupt Enable */
313#define HDA_SDCTL_IOCE RT_BIT(2) /* Interrupt On Completion Enable */
314#define HDA_SDCTL_RUN RT_BIT(1) /* Stream Run */
315#define HDA_SDCTL_SRST RT_BIT(0) /* Stream Reset */
316
317#define HDA_REG_SD0STS 35 /* 0x83; other streams offset by 0x20 */
318#define HDA_RMX_SD0STS 33
319#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
320#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
321#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
322#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
323#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
324#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
325#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
326
327#define HDA_SDSTS_FIFORDY RT_BIT(5) /* FIFO Ready */
328#define HDA_SDSTS_DESE RT_BIT(4) /* Descriptor Error */
329#define HDA_SDSTS_FIFOE RT_BIT(3) /* FIFO Error */
330#define HDA_SDSTS_BCIS RT_BIT(2) /* Buffer Completion Interrupt Status */
331
332#define HDA_REG_SD0LPIB 36 /* 0x84; other streams offset by 0x20 */
333#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
334#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
335#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
336#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
337#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
338#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
339#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
340#define HDA_RMX_SD0LPIB 34
341#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
342#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
343#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
344#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
345#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
346#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
347#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
348
349#define HDA_REG_SD0CBL 37 /* 0x88; other streams offset by 0x20 */
350#define HDA_RMX_SD0CBL 35
351#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
352#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
353#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
354#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
355#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
356#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
357#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
358
359#define HDA_REG_SD0LVI 38 /* 0x8C; other streams offset by 0x20 */
360#define HDA_RMX_SD0LVI 36
361#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
362#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
363#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
364#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
365#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
366#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
367#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
368
369#define HDA_REG_SD0FIFOW 39 /* 0x8E; other streams offset by 0x20 */
370#define HDA_RMX_SD0FIFOW 37
371#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
372#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
373#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
374#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
375#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
376#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
377#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
378
379/*
380 * ICH6 datasheet defined limits for FIFOW values (18.2.38).
381 */
382#define HDA_SDFIFOW_8B 0x2
383#define HDA_SDFIFOW_16B 0x3
384#define HDA_SDFIFOW_32B 0x4
385
386#define HDA_REG_SD0FIFOS 40 /* 0x90; other streams offset by 0x20 */
387#define HDA_RMX_SD0FIFOS 38
388#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
389#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
390#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
391#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
392#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
393#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
394#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
395
396/*
397 * ICH6 datasheet defines limits for FIFOS registers (18.2.39)
398 * formula: size - 1
399 * Other values not listed are not supported.
400 */
401/** Maximum FIFO size (in bytes). */
402#define HDA_FIFO_MAX 256
403
404#define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
405#define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
406
407#define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
408#define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
409#define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
410#define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
411#define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
412#define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
413
414#define HDA_REG_SD0FMT 41 /* 0x92; other streams offset by 0x20 */
415#define HDA_RMX_SD0FMT 39
416#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
417#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
418#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
419#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
420#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
421#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
422#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
423
424#define HDA_REG_SD0BDPL 42 /* 0x98; other streams offset by 0x20 */
425#define HDA_RMX_SD0BDPL 40
426#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
427#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
428#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
429#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
430#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
431#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
432#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
433
434#define HDA_REG_SD0BDPU 43 /* 0x9C; other streams offset by 0x20 */
435#define HDA_RMX_SD0BDPU 41
436#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
437#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
438#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
439#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
440#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
441#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
442#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
443
444#define HDA_BDLE_FLAG_IOC RT_BIT(0) /* Interrupt on completion (IOC). */
445
446#define HDA_CODEC_CAD_SHIFT 28
447/* Encodes the (required) LUN into a codec command. */
448#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
449
450
451
452/*********************************************************************************************************************************
453* Structures and Typedefs *
454*********************************************************************************************************************************/
455
456/**
457 * Internal state of a Buffer Descriptor List Entry (BDLE),
458 * needed to keep track of the data needed for the actual device
459 * emulation.
460 */
461typedef struct HDABDLESTATE
462{
463 /** Own index within the BDL (Buffer Descriptor List). */
464 uint32_t u32BDLIndex;
465 /** Number of bytes below the stream's FIFO watermark (SDFIFOW).
466 * Used to check if we need fill up the FIFO again. */
467 uint32_t cbBelowFIFOW;
468 /** Current offset in DMA buffer (in bytes).*/
469 uint32_t u32BufOff;
470 uint32_t Padding;
471} HDABDLESTATE, *PHDABDLESTATE;
472
473/**
474 * BDL description structure.
475 * Do not touch this, as this must match to the HDA specs.
476 */
477typedef struct HDABDLEDESC
478{
479 /** Starting address of the actual buffer. Must be 128-bit aligned. */
480 uint64_t u64BufAdr;
481 /** Size of the actual buffer (in bytes). */
482 uint32_t u32BufSize;
483 /** Bit 0: Interrupt on completion; the controller will generate
484 * an interrupt when the last byte of the buffer has been
485 * fetched by the DMA engine.
486 *
487 * Rest is reserved for further use and must be 0. */
488 uint32_t fFlags;
489} HDABDLEDESC, *PHDABDLEDESC;
490AssertCompileSize(HDABDLEDESC, 16); /* Always 16 byte. Also must be aligned on 128-byte boundary. */
491
492/**
493 * Buffer Descriptor List Entry (BDLE) (3.6.3).
494 */
495typedef struct HDABDLE
496{
497 /** The actual BDL description. */
498 HDABDLEDESC Desc;
499 /** Internal state of this BDLE.
500 * Not part of the actual BDLE registers. */
501 HDABDLESTATE State;
502} HDABDLE, *PHDABDLE;
503
504/**
505 * Structure for keeping an audio stream data mapping.
506 */
507typedef struct HDASTREAMMAPPING
508{
509 /** The stream's layout. */
510 PDMAUDIOSTREAMLAYOUT enmLayout;
511 /** Number of audio channels in this stream. */
512 uint8_t cChannels;
513 /** Array of audio channels. */
514 R3PTRTYPE(PPDMAUDIOSTREAMCHANNEL) paChannels;
515 /** Circular buffer holding for holding audio data for this mapping. */
516 R3PTRTYPE(PRTCIRCBUF) pCircBuf;
517} HDASTREAMMAPPING, *PHDASTREAMMAPPING;
518
519#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
520/**
521 * Structure keeping the HDA stream's state for asynchronous I/O.
522 */
523typedef struct HDASTREAMSTATEAIO
524{
525 /** Thread handle for the actual I/O thread. */
526 RTTHREAD Thread;
527 /** Event for letting the thread know there is some data to process. */
528 RTSEMEVENT Event;
529 /** Critical section for synchronizing access. */
530 RTCRITSECT CritSect;
531 /** Started indicator. */
532 volatile bool fStarted;
533 /** Shutdown indicator. */
534 volatile bool fShutdown;
535 /** Whether the thread should do any data processing or not. */
536 volatile bool fEnabled;
537 uint32_t Padding1;
538} HDASTREAMSTATEAIO, *PHDASTREAMSTATEAIO;
539#endif
540
541/**
542 * Internal state of a HDA stream.
543 */
544typedef struct HDASTREAMSTATE
545{
546 /** Current BDLE to use. Wraps around to 0 if
547 * maximum (cBDLE) is reached. */
548 uint16_t uCurBDLE;
549 /** Flag indicating whether this stream currently is
550 * in reset mode and therefore not acccessible by the guest. */
551 volatile bool fInReset;
552 /** Unused, padding. */
553 uint32_t Padding0;
554 /** Critical section to serialize access. */
555 RTCRITSECT CritSect;
556#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
557 /** Asynchronous I/O state members. */
558 HDASTREAMSTATEAIO AIO;
559#endif
560 /** This stream's data mapping. */
561 HDASTREAMMAPPING Mapping;
562 /** Current BDLE (Buffer Descriptor List Entry). */
563 HDABDLE BDLE;
564 /** Circular buffer (FIFO) for holding DMA'ed data. */
565 R3PTRTYPE(PRTCIRCBUF) pCircBuf;
566} HDASTREAMSTATE, *PHDASTREAMSTATE;
567
568/**
569 * Structure defining an HDA mixer sink.
570 * Its purpose is to know which audio mixer sink is bound to
571 * which SDn (SDI/SDO) device stream.
572 *
573 * This is needed in order to handle interleaved streams
574 * (that is, multiple channels in one stream) or non-interleaved
575 * streams (each channel has a dedicated stream).
576 *
577 * This is only known to the actual device emulation level.
578 */
579typedef struct HDAMIXERSINK
580{
581 /** SDn ID this sink is assigned to. 0 if not assigned. */
582 uint8_t uSD;
583 /** Channel ID of SDn ID. Only valid if SDn ID is valid. */
584 uint8_t uChannel;
585 uint8_t Padding[3];
586 /** Pointer to the actual audio mixer sink. */
587 R3PTRTYPE(PAUDMIXSINK) pMixSink;
588} HDAMIXERSINK, *PHDAMIXERSINK;
589
590/**
591 * Structure for keeping a HDA stream (SDI / SDO).
592 *
593 * Note: This HDA stream has nothing to do with a regular audio stream handled
594 * by the audio connector or the audio mixer. This HDA stream is a serial data in/out
595 * stream (SDI/SDO) defined in hardware and can contain multiple audio streams
596 * in one single SDI/SDO (interleaving streams).
597 *
598 * How a specific SDI/SDO is mapped to our internal audio streams relies on the
599 * stream channel mappings.
600 *
601 * Contains only register values which do *not* change until a
602 * stream reset occurs.
603 */
604typedef struct HDASTREAM
605{
606 /** Stream descriptor number (SDn). */
607 uint8_t u8SD;
608 uint8_t Padding0[7];
609 /** DMA base address (SDnBDPU - SDnBDPL). */
610 uint64_t u64BDLBase;
611 /** Cyclic Buffer Length (SDnCBL).
612 * Represents the size of the ring buffer. */
613 uint32_t u32CBL;
614 /** Format (SDnFMT). */
615 uint16_t u16FMT;
616 /** FIFO Size (FIFOS).
617 * Maximum number of bytes that may have been DMA'd into
618 * memory but not yet transmitted on the link. */
619 uint16_t u16FIFOS;
620 /** FIFO Watermark. */
621 uint16_t u16FIFOW;
622 /** Last Valid Index (SDnLVI). */
623 uint16_t u16LVI;
624 uint16_t Padding1[2];
625 /** Pointer to HDA sink this stream is attached to. */
626 R3PTRTYPE(PHDAMIXERSINK) pMixSink;
627 /** Internal state of this stream. */
628 HDASTREAMSTATE State;
629} HDASTREAM, *PHDASTREAM;
630
631#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
632/**
633 * Structure for keeping a HDA stream thread context.
634 */
635typedef struct HDASTREAMTHREADCTX
636{
637 PHDASTATE pThis;
638 PHDASTREAM pStream;
639} HDASTREAMTHREADCTX, *PHDASTREAMTHREADCTX;
640#endif
641
642/**
643 * Structure for mapping a stream tag to an HDA stream.
644 */
645typedef struct HDATAG
646{
647 /** Own stream tag. */
648 uint8_t uTag;
649 uint8_t Padding[7];
650 /** Pointer to associated stream. */
651 R3PTRTYPE(PHDASTREAM) pStrm;
652} HDATAG, *PHDATAG;
653
654/**
655 * Structure defining a (host backend) driver stream.
656 * Each driver has its own instances of audio mixer streams, which then
657 * can go into the same (or even different) audio mixer sinks.
658 */
659typedef struct HDADRIVERSTREAM
660{
661 union
662 {
663 /** Desired playback destination (for an output stream). */
664 PDMAUDIOPLAYBACKDEST Dest;
665 /** Desired recording source (for an input stream). */
666 PDMAUDIORECSOURCE Source;
667 } DestSource;
668 uint8_t Padding1[4];
669 /** Associated mixer handle. */
670 R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
671} HDADRIVERSTREAM, *PHDADRIVERSTREAM;
672
673/**
674 * Struct for maintaining a host backend driver.
675 * This driver must be associated to one, and only one,
676 * HDA codec. The HDA controller does the actual multiplexing
677 * of HDA codec data to various host backend drivers then.
678 *
679 * This HDA device uses a timer in order to synchronize all
680 * read/write accesses across all attached LUNs / backends.
681 */
682typedef struct HDADRIVER
683{
684 /** Node for storing this driver in our device driver list of HDASTATE. */
685 RTLISTNODER3 Node;
686 /** Pointer to HDA controller (state). */
687 R3PTRTYPE(PHDASTATE) pHDAState;
688 /** Driver flags. */
689 PDMAUDIODRVFLAGS fFlags;
690 uint8_t u32Padding0[2];
691 /** LUN to which this driver has been assigned. */
692 uint8_t uLUN;
693 /** Whether this driver is in an attached state or not. */
694 bool fAttached;
695 /** Pointer to attached driver base interface. */
696 R3PTRTYPE(PPDMIBASE) pDrvBase;
697 /** Audio connector interface to the underlying host backend. */
698 R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
699 /** Mixer stream for line input. */
700 HDADRIVERSTREAM LineIn;
701#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
702 /** Mixer stream for mic input. */
703 HDADRIVERSTREAM MicIn;
704#endif
705 /** Mixer stream for front output. */
706 HDADRIVERSTREAM Front;
707#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
708 /** Mixer stream for center/LFE output. */
709 HDADRIVERSTREAM CenterLFE;
710 /** Mixer stream for rear output. */
711 HDADRIVERSTREAM Rear;
712#endif
713} HDADRIVER;
714
715/**
716 * ICH Intel HD Audio Controller state.
717 */
718typedef struct HDASTATE
719{
720 /** The PCI device structure. */
721 PDMPCIDEV PciDev;
722 /** R3 Pointer to the device instance. */
723 PPDMDEVINSR3 pDevInsR3;
724 /** R0 Pointer to the device instance. */
725 PPDMDEVINSR0 pDevInsR0;
726 /** R0 Pointer to the device instance. */
727 PPDMDEVINSRC pDevInsRC;
728 /** Padding for alignment. */
729 uint32_t u32Padding;
730 /** The base interface for LUN\#0. */
731 PDMIBASE IBase;
732 RTGCPHYS MMIOBaseAddr;
733 /** The HDA's register set. */
734 uint32_t au32Regs[HDA_NUM_REGS];
735 /** Internal stream states. */
736 HDASTREAM aStreams[HDA_MAX_STREAMS];
737 /** Mapping table between stream tags and stream states. */
738 HDATAG aTags[HDA_MAX_TAGS];
739 /** CORB buffer base address. */
740 uint64_t u64CORBBase;
741 /** RIRB buffer base address. */
742 uint64_t u64RIRBBase;
743 /** DMA base address.
744 * Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
745 uint64_t u64DPBase;
746 /** DMA position buffer enable bit. */
747 bool fDMAPosition;
748 /** Padding for alignment. */
749 uint8_t u8Padding0[7];
750 /** Pointer to CORB buffer. */
751 R3PTRTYPE(uint32_t *) pu32CorbBuf;
752 /** Size in bytes of CORB buffer. */
753 uint32_t cbCorbBuf;
754 /** Padding for alignment. */
755 uint32_t u32Padding1;
756 /** Pointer to RIRB buffer. */
757 R3PTRTYPE(uint64_t *) pu64RirbBuf;
758 /** Size in bytes of RIRB buffer. */
759 uint32_t cbRirbBuf;
760 /** Indicates if HDA controller is in reset mode. */
761 bool fInReset;
762 /** Flag whether the R0 part is enabled. */
763 bool fR0Enabled;
764 /** Flag whether the RC part is enabled. */
765 bool fRCEnabled;
766 /** Number of active (running) SDn streams. */
767 uint8_t cStreamsActive;
768#ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
769 /** The timer for pumping data thru the attached LUN drivers. */
770 PTMTIMERR3 pTimer;
771 /** Flag indicating whether the timer is active or not. */
772 bool fTimerActive;
773 uint8_t u8Padding1[7];
774 /** Timer ticks per Hz. */
775 uint64_t cTimerTicks;
776 /** Timestamp of the last timer callback (hdaTimer).
777 * Used to calculate the time actually elapsed between two timer callbacks. */
778 uint64_t uTimerTS;
779 uint64_t uTimerMS;
780#endif
781#ifdef VBOX_WITH_STATISTICS
782# ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
783 STAMPROFILE StatTimer;
784# endif
785 STAMPROFILE StatIn;
786 STAMPROFILE StatOut;
787 STAMCOUNTER StatBytesRead;
788 STAMCOUNTER StatBytesWritten;
789#endif
790 /** Pointer to HDA codec to use. */
791 R3PTRTYPE(PHDACODEC) pCodec;
792 /** List of associated LUN drivers (HDADRIVER). */
793 RTLISTANCHORR3 lstDrv;
794 /** The device' software mixer. */
795 R3PTRTYPE(PAUDIOMIXER) pMixer;
796 /** HDA sink for (front) output. */
797 HDAMIXERSINK SinkFront;
798#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
799 /** HDA sink for center / LFE output. */
800 HDAMIXERSINK SinkCenterLFE;
801 /** HDA sink for rear output. */
802 HDAMIXERSINK SinkRear;
803#endif
804 /** HDA mixer sink for line input. */
805 HDAMIXERSINK SinkLineIn;
806#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
807 /** Audio mixer sink for microphone input. */
808 HDAMIXERSINK SinkMicIn;
809#endif
810 uint64_t u64BaseTS;
811 /** Response Interrupt Count (RINTCNT). */
812 uint8_t u8RespIntCnt;
813 /** Padding for alignment. */
814 uint8_t au8Padding2[7];
815} HDASTATE;
816/** Pointer to the ICH Intel HD Audio Controller state. */
817typedef HDASTATE *PHDASTATE;
818
819#ifdef VBOX_WITH_AUDIO_HDA_CALLBACKS
820typedef struct HDACALLBACKCTX
821{
822 PHDASTATE pThis;
823 PHDADRIVER pDriver;
824} HDACALLBACKCTX, *PHDACALLBACKCTX;
825#endif
826
827
828/*********************************************************************************************************************************
829* Internal Functions *
830*********************************************************************************************************************************/
831#ifndef VBOX_DEVICE_STRUCT_TESTCASE
832#ifdef IN_RING3
833static FNPDMDEVRESET hdaReset;
834#endif
835
836/** @name Register read/write stubs.
837 * @{
838 */
839static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
840static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
841/** @} */
842
843/** @name Global register set read/write functions.
844 * @{
845 */
846static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
847static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
848static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
849static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
850static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
851static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
852static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
853static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
854static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
855static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
856static int hdaRegWriteINTCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
857static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
858static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
859static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
860/** @} */
861
862/** @name {IOB}SDn write functions.
863 * @{
864 */
865static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
866static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
867static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
868static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
869static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
870static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
871static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
872static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
873static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
874/** @} */
875
876/** @name Generic register read/write functions.
877 * @{
878 */
879static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
880static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
881static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
882#ifdef IN_RING3
883static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
884#endif
885static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
886static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
887static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
888static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
889/** @} */
890
891/** @name Stream functions.
892 * @{
893 */
894#ifdef IN_RING3
895static void hdaStreamDestroy(PHDASTATE pThis, PHDASTREAM pStream);
896static int hdaStreamDoDMA(PHDASTATE pThis, PHDASTREAM pStream, void *pvBuf, uint32_t cbBuf, uint32_t cbToProcess, uint32_t *pcbProcessed);
897static int hdaStreamEnable(PHDASTATE pThis, PHDASTREAM pStream, bool fEnable);
898static int hdaStreamUpdate(PHDASTATE pThis, PHDASTREAM pStream);
899DECLINLINE(uint32_t) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStream, uint32_t u32LPIB);
900static void hdaStreamLock(PHDASTREAM pStream);
901static void hdaStreamUnlock(PHDASTREAM pStream);
902#endif /* IN_RING3 */
903/** @} */
904
905/** @name Async I/O stream functions.
906 * @{
907 */
908#ifdef IN_RING3
909# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
910static DECLCALLBACK(int) hdaStreamAsyncIOThread(RTTHREAD hThreadSelf, void *pvUser);
911static int hdaStreamAsyncIOCreate(PHDASTATE pThis, PHDASTREAM pStream);
912static int hdaStreamAsyncIODestroy(PHDASTATE pThis, PHDASTREAM pStream);
913static int hdaStreamAsyncIONotify(PHDASTATE pThis, PHDASTREAM pStream);
914static void hdaStreamAsyncIOLock(PHDASTREAM pStream);
915static void hdaStreamAsyncIOUnlock(PHDASTREAM pStream);
916static void hdaStreamAsyncIOEnable(PHDASTREAM pStream, bool fEnable);
917# endif
918#endif
919/** @} */
920
921/** @name Stream mapping functions.
922 * @{
923 */
924#ifdef IN_RING3
925static int hdaStreamMapInit(PHDASTREAMMAPPING pMapping, PPDMAUDIOSTREAMCFG pCfg);
926static void hdaStreamMapDestroy(PHDASTREAMMAPPING pMapping);
927static void hdaStreamMapReset(PHDASTREAMMAPPING pMapping);
928#endif /* IN_RING3 */
929/** @} */
930
931/** @name HDA device functions.
932 * @{
933 */
934#ifdef IN_RING3
935static void hdaDoTransfers(PHDASTATE pThis);
936#endif /* IN_RING3 */
937static int hdaProcessInterrupt(PHDASTATE pThis);
938/** @} */
939
940/** @name BDLE (Buffer Descriptor List Entry) functions.
941 * @{
942 */
943#ifdef IN_RING3
944static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry);
945# ifdef LOG_ENABLED
946static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BaseDMA, uint16_t cBDLE);
947# endif
948#endif /* IN_RING3 */
949/** @} */
950
951/** @name Timer functions.
952 * @{
953 */
954#if !defined(VBOX_WITH_AUDIO_HDA_CALLBACKS) && defined(IN_RING3)
955static void hdaTimerMaybeStart(PHDASTATE pThis);
956static void hdaTimerMaybeStop(PHDASTATE pThis);
957static void hdaTimerMain(PHDASTATE pThis);
958#endif
959/** @} */
960
961
962/*********************************************************************************************************************************
963* Global Variables *
964*********************************************************************************************************************************/
965
966/** Offset of the SD0 register map. */
967#define HDA_REG_DESC_SD0_BASE 0x80
968
969/** Turn a short global register name into an memory index and a stringized name. */
970#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
971
972/** Turns a short stream register name into an memory index and a stringized name. */
973#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
974
975/** Same as above for a register *not* stored in memory. */
976#define HDA_REG_IDX_NOMEM(abbrev) 0, #abbrev
977
978/** No register description (RD) flags defined. */
979#define HDA_RD_FLAG_NONE 0
980/** Writes to SD are allowed while RUN bit is set. */
981#define HDA_RD_FLAG_SD_WRITE_RUN RT_BIT(0)
982
983/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
984#define HDA_REG_MAP_STRM(offset, name) \
985 /* offset size read mask write mask flags read callback write callback index + abbrev description */ \
986 /* ------- ------- ---------- ---------- ------------------------- -------------- ----------------- ----------------------------- ----------- */ \
987 /* Offset 0x80 (SD0) */ \
988 { offset, 0x00003, 0x00FF001F, 0x00F0001F, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL) , #name " Stream Descriptor Control" }, \
989 /* Offset 0x83 (SD0) */ \
990 { offset + 0x3, 0x00001, 0x0000003C, 0x0000001C, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU8 , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS) , #name " Status" }, \
991 /* Offset 0x84 (SD0) */ \
992 { offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadLPIB, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
993 /* Offset 0x88 (SD0) */ \
994 { offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDCBL , HDA_REG_IDX_STRM(name, CBL) , #name " Cyclic Buffer Length" }, \
995 /* Offset 0x8C (SD0) */ \
996 { offset + 0xC, 0x00002, 0x0000FFFF, 0x0000FFFF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDLVI , HDA_REG_IDX_STRM(name, LVI) , #name " Last Valid Index" }, \
997 /* Reserved: FIFO Watermark. ** @todo Document this! */ \
998 { offset + 0xE, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
999 /* Offset 0x90 (SD0) */ \
1000 { offset + 0x10, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
1001 /* Offset 0x92 (SD0) */ \
1002 { offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFMT , HDA_REG_IDX_STRM(name, FMT) , #name " Stream Format" }, \
1003 /* Reserved: 0x94 - 0x98. */ \
1004 /* Offset 0x98 (SD0) */ \
1005 { offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
1006 /* Offset 0x9C (SD0) */ \
1007 { offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
1008
1009/** Defines a single audio stream register set (e.g. OSD0). */
1010#define HDA_REG_MAP_DEF_STREAM(index, name) \
1011 HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
1012
1013/* See 302349 p 6.2. */
1014static const struct HDAREGDESC
1015{
1016 /** Register offset in the register space. */
1017 uint32_t offset;
1018 /** Size in bytes. Registers of size > 4 are in fact tables. */
1019 uint32_t size;
1020 /** Readable bits. */
1021 uint32_t readable;
1022 /** Writable bits. */
1023 uint32_t writable;
1024 /** Register descriptor (RD) flags of type HDA_RD_FLAG_.
1025 * These are used to specify the handling (read/write)
1026 * policy of the register. */
1027 uint32_t fFlags;
1028 /** Read callback. */
1029 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
1030 /** Write callback. */
1031 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
1032 /** Index into the register storage array. */
1033 uint32_t mem_idx;
1034 /** Abbreviated name. */
1035 const char *abbrev;
1036 /** Descripton. */
1037 const char *desc;
1038} g_aHdaRegMap[HDA_NUM_REGS] =
1039
1040{
1041 /* offset size read mask write mask flags read callback write callback index + abbrev */
1042 /*------- ------- ---------- ---------- ----------------- ---------------- ------------------- ------------------------ */
1043 { 0x00000, 0x00002, 0x0000FFFB, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(GCAP) }, /* Global Capabilities */
1044 { 0x00002, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMIN) }, /* Minor Version */
1045 { 0x00003, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMAJ) }, /* Major Version */
1046 { 0x00004, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTPAY) }, /* Output Payload Capabilities */
1047 { 0x00006, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INPAY) }, /* Input Payload Capabilities */
1048 { 0x00008, 0x00004, 0x00000103, 0x00000103, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteGCTL , HDA_REG_IDX(GCTL) }, /* Global Control */
1049 { 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(WAKEEN) }, /* Wake Enable */
1050 { 0x0000e, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteSTATESTS, HDA_REG_IDX(STATESTS) }, /* State Change Status */
1051 { 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadUnimpl, hdaRegWriteUnimpl , HDA_REG_IDX(GSTS) }, /* Global Status */
1052 { 0x00018, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTSTRMPAY) }, /* Output Stream Payload Capability */
1053 { 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INSTRMPAY) }, /* Input Stream Payload Capability */
1054 { 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteINTCTL , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */
1055 { 0x00024, 0x00004, 0xC00000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */
1056 { 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadWALCLK, hdaRegWriteUnimpl , HDA_REG_IDX_NOMEM(WALCLK) }, /* Wall Clock Counter */
1057 { 0x00034, 0x00004, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */
1058 { 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
1059 { 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBUBASE) }, /* CORB Upper Base Address */
1060 { 0x00048, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteCORBWP , HDA_REG_IDX(CORBWP) }, /* CORB Write Pointer */
1061 { 0x0004A, 0x00002, 0x000080FF, 0x000080FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteCORBRP , HDA_REG_IDX(CORBRP) }, /* CORB Read Pointer */
1062 { 0x0004C, 0x00001, 0x00000003, 0x00000003, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL) }, /* CORB Control */
1063 { 0x0004D, 0x00001, 0x00000001, 0x00000001, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS) }, /* CORB Status */
1064 { 0x0004E, 0x00001, 0x000000F3, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(CORBSIZE) }, /* CORB Size */
1065 { 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBLBASE) }, /* RIRB Lower Base Address */
1066 { 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBUBASE) }, /* RIRB Upper Base Address */
1067 { 0x00058, 0x00002, 0x000000FF, 0x00008000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteRIRBWP , HDA_REG_IDX(RIRBWP) }, /* RIRB Write Pointer */
1068 { 0x0005A, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(RINTCNT) }, /* Response Interrupt Count */
1069 { 0x0005C, 0x00001, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteU8 , HDA_REG_IDX(RIRBCTL) }, /* RIRB Control */
1070 { 0x0005D, 0x00001, 0x00000005, 0x00000005, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS) }, /* RIRB Status */
1071 { 0x0005E, 0x00001, 0x000000F3, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(RIRBSIZE) }, /* RIRB Size */
1072 { 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(IC) }, /* Immediate Command */
1073 { 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(IR) }, /* Immediate Response */
1074 { 0x00068, 0x00002, 0x00000002, 0x00000002, HDA_RD_FLAG_NONE, hdaRegReadIRS , hdaRegWriteIRS , HDA_REG_IDX(IRS) }, /* Immediate Command Status */
1075 { 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPLBASE) }, /* DMA Position Lower Base */
1076 { 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPUBASE) }, /* DMA Position Upper Base */
1077 /* 4 Serial Data In (SDI). */
1078 HDA_REG_MAP_DEF_STREAM(0, SD0),
1079 HDA_REG_MAP_DEF_STREAM(1, SD1),
1080 HDA_REG_MAP_DEF_STREAM(2, SD2),
1081 HDA_REG_MAP_DEF_STREAM(3, SD3),
1082 /* 4 Serial Data Out (SDO). */
1083 HDA_REG_MAP_DEF_STREAM(4, SD4),
1084 HDA_REG_MAP_DEF_STREAM(5, SD5),
1085 HDA_REG_MAP_DEF_STREAM(6, SD6),
1086 HDA_REG_MAP_DEF_STREAM(7, SD7)
1087};
1088
1089/**
1090 * HDA register aliases (HDA spec 3.3.45).
1091 * @remarks Sorted by offReg.
1092 */
1093static const struct
1094{
1095 /** The alias register offset. */
1096 uint32_t offReg;
1097 /** The register index. */
1098 int idxAlias;
1099} g_aHdaRegAliases[] =
1100{
1101 { 0x2084, HDA_REG_SD0LPIB },
1102 { 0x20a4, HDA_REG_SD1LPIB },
1103 { 0x20c4, HDA_REG_SD2LPIB },
1104 { 0x20e4, HDA_REG_SD3LPIB },
1105 { 0x2104, HDA_REG_SD4LPIB },
1106 { 0x2124, HDA_REG_SD5LPIB },
1107 { 0x2144, HDA_REG_SD6LPIB },
1108 { 0x2164, HDA_REG_SD7LPIB },
1109};
1110
1111#ifdef IN_RING3
1112/** HDABDLEDESC field descriptors for the v6+ saved state. */
1113static SSMFIELD const g_aSSMBDLEDescFields6[] =
1114{
1115 SSMFIELD_ENTRY(HDABDLEDESC, u64BufAdr),
1116 SSMFIELD_ENTRY(HDABDLEDESC, u32BufSize),
1117 SSMFIELD_ENTRY(HDABDLEDESC, fFlags),
1118 SSMFIELD_ENTRY_TERM()
1119};
1120
1121/** HDABDLESTATE field descriptors for the v6+ saved state. */
1122static SSMFIELD const g_aSSMBDLEStateFields6[] =
1123{
1124 SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
1125 SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
1126 SSMFIELD_ENTRY_OLD(FIFO, 256),
1127 SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
1128 SSMFIELD_ENTRY_TERM()
1129};
1130
1131/** HDASTREAMSTATE field descriptors for the v6+ saved state. */
1132static SSMFIELD const g_aSSMStreamStateFields6[] =
1133{
1134 SSMFIELD_ENTRY_OLD(cBDLE, 2),
1135 SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
1136 SSMFIELD_ENTRY_OLD(fDoStop, 1),
1137 SSMFIELD_ENTRY_OLD(fActive, 1),
1138 SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
1139 SSMFIELD_ENTRY_TERM()
1140};
1141#endif
1142
1143/**
1144 * 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
1145 */
1146static uint32_t const g_afMasks[5] =
1147{
1148 UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
1149};
1150
1151
1152#ifdef IN_RING3
1153/**
1154 * Retrieves the number of bytes of a FIFOW register.
1155 *
1156 * @return Number of bytes of a given FIFOW register.
1157 */
1158DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
1159{
1160 uint32_t cb;
1161 switch (u32RegFIFOW)
1162 {
1163 case HDA_SDFIFOW_8B: cb = 8; break;
1164 case HDA_SDFIFOW_16B: cb = 16; break;
1165 case HDA_SDFIFOW_32B: cb = 32; break;
1166 default: cb = 0; break;
1167 }
1168
1169 Assert(RT_IS_POWER_OF_TWO(cb));
1170 return cb;
1171}
1172
1173
1174DECLINLINE(uint32_t) hdaStreamUpdateLPIB(PHDASTATE pThis, PHDASTREAM pStream, uint32_t u32LPIB)
1175{
1176 AssertPtrReturn(pThis, 0);
1177 AssertPtrReturn(pStream, 0);
1178
1179 AssertMsg(u32LPIB <= pStream->u32CBL,
1180 ("[SD%RU8] New LPIB (%RU32) exceeds CBL (%RU32)\n", pStream->u8SD, u32LPIB, pStream->u32CBL));
1181
1182 u32LPIB = RT_MIN(u32LPIB, pStream->u32CBL);
1183
1184 LogFlowFunc(("[SD%RU8]: LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n",
1185 pStream->u8SD, u32LPIB, pThis->fDMAPosition));
1186
1187 /* Update LPIB in any case. */
1188 HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) = u32LPIB;
1189
1190 /* Do we need to tell the current DMA position? */
1191 if (pThis->fDMAPosition)
1192 {
1193 int rc2 = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns),
1194 (pThis->u64DPBase & DPBASE_ADDR_MASK) + (pStream->u8SD * 2 * sizeof(uint32_t)),
1195 (void *)&u32LPIB, sizeof(uint32_t));
1196 AssertRC(rc2);
1197 }
1198
1199 return u32LPIB;
1200}
1201
1202
1203/**
1204 * Locks an HDA stream for serialized access.
1205 *
1206 * @returns IPRT status code.
1207 * @param pStream HDA stream to lock.
1208 */
1209static void hdaStreamLock(PHDASTREAM pStream)
1210{
1211 AssertPtrReturnVoid(pStream);
1212 int rc2 = RTCritSectEnter(&pStream->State.CritSect);
1213 AssertRC(rc2);
1214}
1215
1216
1217/**
1218 * Unlocks a formerly locked HDA stream.
1219 *
1220 * @returns IPRT status code.
1221 * @param pStream HDA stream to unlock.
1222 */
1223static void hdaStreamUnlock(PHDASTREAM pStream)
1224{
1225 AssertPtrReturnVoid(pStream);
1226 int rc2 = RTCritSectLeave(&pStream->State.CritSect);
1227 AssertRC(rc2);
1228}
1229
1230
1231/**
1232 * Fetches the next BDLE to use for a stream.
1233 *
1234 * @return IPRT status code.
1235 */
1236DECLINLINE(int) hdaStreamGetNextBDLE(PHDASTATE pThis, PHDASTREAM pStream, bool *pfWrapAround)
1237{
1238 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1239 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1240
1241 NOREF(pThis);
1242
1243 Assert(pStream->State.uCurBDLE < pStream->u16LVI + 1);
1244
1245 LogFlowFuncEnter();
1246
1247# ifdef LOG_ENABLED
1248 uint32_t const uOldBDLE = pStream->State.uCurBDLE;
1249# endif
1250
1251 PHDABDLE pBDLE = &pStream->State.BDLE;
1252 bool fWrapAround = false;
1253
1254 AssertMsg(pBDLE->State.u32BufOff == pBDLE->Desc.u32BufSize, ("BDLE not finished yet: %R[bdle]\n", pBDLE));
1255
1256 /*
1257 * Switch to the next BDLE entry and do a wrap around
1258 * if we reached the end of the Buffer Descriptor List (BDL).
1259 */
1260 pStream->State.uCurBDLE++;
1261 if (pStream->State.uCurBDLE == pStream->u16LVI + 1)
1262 {
1263 pStream->State.uCurBDLE = 0;
1264 fWrapAround = true;
1265 }
1266
1267 Assert(pStream->State.uCurBDLE < pStream->u16LVI + 1);
1268
1269 /* Fetch the next BDLE entry. */
1270 int rc = hdaBDLEFetch(pThis, pBDLE, pStream->u64BDLBase, pStream->State.uCurBDLE);
1271 if (RT_SUCCESS(rc))
1272 {
1273 LogFlowFunc(("[SD%RU8]: uOldBDLE=%RU16, uCurBDLE=%RU16, LVI=%RU32, rc=%Rrc, %R[bdle]\n",
1274 pStream->u8SD, uOldBDLE, pStream->State.uCurBDLE, pStream->u16LVI, rc, pBDLE));
1275
1276 if (pfWrapAround)
1277 *pfWrapAround = fWrapAround;
1278 }
1279
1280 return rc;
1281}
1282
1283
1284/**
1285 * Returns the HDA stream of specified stream descriptor number.
1286 *
1287 * @return Pointer to HDA stream, or NULL if none found.
1288 */
1289DECLINLINE(PHDASTREAM) hdaStreamGetFromSD(PHDASTATE pThis, uint8_t uSD)
1290{
1291 AssertPtrReturn(pThis, NULL);
1292 AssertReturn(uSD <= HDA_MAX_STREAMS, NULL);
1293
1294 if (uSD >= HDA_MAX_STREAMS)
1295 {
1296 AssertMsgFailed(("Invalid / non-handled SD%RU8\n", uSD));
1297 return NULL;
1298 }
1299
1300 return &pThis->aStreams[uSD];
1301}
1302
1303
1304/**
1305 * Returns the HDA stream of specified HDA sink.
1306 *
1307 * @return Pointer to HDA stream, or NULL if none found.
1308 */
1309DECLINLINE(PHDASTREAM) hdaSinkGetStream(PHDASTATE pThis, PHDAMIXERSINK pSink)
1310{
1311 AssertPtrReturn(pThis, NULL);
1312 AssertPtrReturn(pSink, NULL);
1313
1314 /** @todo Do something with the channel mapping here? */
1315 return hdaStreamGetFromSD(pThis, pSink->uSD);
1316}
1317
1318
1319/**
1320 * Returns the audio direction of a specified stream descriptor.
1321 *
1322 * The register layout specifies that input streams (SDI) come first,
1323 * followed by the output streams (SDO). So every stream ID below HDA_MAX_SDI
1324 * is an input stream, whereas everything >= HDA_MAX_SDI is an output stream.
1325 *
1326 * Note: SDnFMT register does not provide that information, so we have to judge
1327 * for ourselves.
1328 *
1329 * @return Audio direction.
1330 */
1331DECLINLINE(PDMAUDIODIR) hdaGetDirFromSD(uint8_t uSD)
1332{
1333 AssertReturn(uSD <= HDA_MAX_STREAMS, PDMAUDIODIR_UNKNOWN);
1334
1335 if (uSD < HDA_MAX_SDI)
1336 return PDMAUDIODIR_IN;
1337
1338 return PDMAUDIODIR_OUT;
1339}
1340#endif /* IN_RING3 */
1341
1342
1343static void hdaUpdateINTSTS(PHDASTATE pThis)
1344{
1345 uint32_t intSts = 0;
1346
1347 /** @todo r=michaln This is ignoring HDA_RIRBCTL_ROIC! */
1348 if (/* Response Overrun Interrupt Status (ROIS aka RIRBOIS) */
1349 (HDA_REG(pThis, RIRBSTS) & HDA_RIRBSTS_RIRBOIS)
1350 /* Response Interrupt */
1351 || (HDA_REG(pThis, RIRBSTS) & HDA_RIRBSTS_RINTFL)
1352 /* SDIN State Change Status Flags (SCSF) */
1353 || (HDA_REG(pThis, STATESTS) & HDA_STATESTS_SCSF_MASK))
1354 {
1355 intSts |= HDA_INTSTS_CIS; /* Set the Controller Interrupt Status (CIS). */
1356 }
1357
1358 /** @todo r=michaln The logic here ignores enable bits and is generally completely broken. */
1359 for (int iStrm = 0; iStrm < 8; ++iStrm)
1360 {
1361 if ( (HDA_REG(pThis, INTCTL) & RT_BIT(iStrm))
1362 && (HDA_STREAM_REG(pThis, STS, iStrm) & (HDA_SDSTS_DESE | HDA_SDSTS_FIFOE | HDA_SDSTS_BCIS)))
1363 {
1364 Log3Func(("[SD%d] interrupt set\n", iStrm));
1365 intSts |= RT_BIT(iStrm);
1366 }
1367 }
1368
1369 if (intSts)
1370 intSts |= HDA_INTSTS_GIS; /* Set the Global Interrupt Status (GIS). */
1371
1372 HDA_REG(pThis, INTSTS) = intSts;
1373
1374 Log3Func(("INTSTS=%x\n", intSts));
1375}
1376
1377static int hdaProcessInterrupt(PHDASTATE pThis)
1378{
1379 hdaUpdateINTSTS(pThis);
1380
1381 int iLevel = 0;
1382
1383 /* Global Interrupt Status (GIS) set? */
1384 /** @todo r=michaln: This is wrong. It is possible to have GIS set when CIS and all stream interrupts are disabled. */
1385 if (HDA_REG(pThis, INTSTS) & HDA_INTSTS_GIS)
1386 iLevel = 1;
1387
1388 Log3Func(("INTCTL=%x, INTSTS=%x, Level=%d\n", HDA_REG(pThis, INTCTL), HDA_REG(pThis, INTSTS), iLevel));
1389
1390 /* Global Interrupt Enable (GIE) set? */
1391 if (HDA_REG(pThis, INTCTL) & HDA_INTCTL_GIE)
1392 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, iLevel);
1393
1394 return VINF_SUCCESS;
1395}
1396
1397/**
1398 * Looks up a register at the exact offset given by @a offReg.
1399 *
1400 * @returns Register index on success, -1 if not found.
1401 * @param offReg The register offset.
1402 */
1403static int hdaRegLookup(uint32_t offReg)
1404{
1405 /*
1406 * Aliases.
1407 */
1408 if (offReg >= g_aHdaRegAliases[0].offReg)
1409 {
1410 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1411 if (offReg == g_aHdaRegAliases[i].offReg)
1412 return g_aHdaRegAliases[i].idxAlias;
1413 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1414 return -1;
1415 }
1416
1417 /*
1418 * Binary search the
1419 */
1420 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1421 int idxLow = 0;
1422 for (;;)
1423 {
1424 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1425 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1426 {
1427 if (idxLow == idxMiddle)
1428 break;
1429 idxEnd = idxMiddle;
1430 }
1431 else if (offReg > g_aHdaRegMap[idxMiddle].offset)
1432 {
1433 idxLow = idxMiddle + 1;
1434 if (idxLow >= idxEnd)
1435 break;
1436 }
1437 else
1438 return idxMiddle;
1439 }
1440
1441#ifdef RT_STRICT
1442 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1443 Assert(g_aHdaRegMap[i].offset != offReg);
1444#endif
1445 return -1;
1446}
1447
1448/**
1449 * Looks up a register covering the offset given by @a offReg.
1450 *
1451 * @returns Register index on success, -1 if not found.
1452 * @param offReg The register offset.
1453 */
1454static int hdaRegLookupWithin(uint32_t offReg)
1455{
1456 /*
1457 * Aliases.
1458 */
1459 if (offReg >= g_aHdaRegAliases[0].offReg)
1460 {
1461 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
1462 {
1463 uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
1464 if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
1465 return g_aHdaRegAliases[i].idxAlias;
1466 }
1467 Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
1468 return -1;
1469 }
1470
1471 /*
1472 * Binary search the register map.
1473 */
1474 int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
1475 int idxLow = 0;
1476 for (;;)
1477 {
1478 int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
1479 if (offReg < g_aHdaRegMap[idxMiddle].offset)
1480 {
1481 if (idxLow == idxMiddle)
1482 break;
1483 idxEnd = idxMiddle;
1484 }
1485 else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
1486 {
1487 idxLow = idxMiddle + 1;
1488 if (idxLow >= idxEnd)
1489 break;
1490 }
1491 else
1492 return idxMiddle;
1493 }
1494
1495#ifdef RT_STRICT
1496 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
1497 Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
1498#endif
1499 return -1;
1500}
1501
1502#ifdef IN_RING3
1503
1504static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
1505{
1506 int rc = VINF_SUCCESS;
1507 if (fLocal)
1508 {
1509 Assert((HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA));
1510 Assert(pThis->u64CORBBase);
1511 AssertPtr(pThis->pu32CorbBuf);
1512 Assert(pThis->cbCorbBuf);
1513
1514 rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
1515 if (RT_FAILURE(rc))
1516 AssertRCReturn(rc, rc);
1517# ifdef DEBUG_CMD_BUFFER
1518 uint8_t i = 0;
1519 do
1520 {
1521 LogFunc(("CORB%02x: ", i));
1522 uint8_t j = 0;
1523 do
1524 {
1525 const char *pszPrefix;
1526 if ((i + j) == HDA_REG(pThis, CORBRP));
1527 pszPrefix = "[R]";
1528 else if ((i + j) == HDA_REG(pThis, CORBWP));
1529 pszPrefix = "[W]";
1530 else
1531 pszPrefix = " "; /* three spaces */
1532 LogFunc(("%s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
1533 j++;
1534 } while (j < 8);
1535 LogFunc(("\n"));
1536 i += 8;
1537 } while(i != 0);
1538# endif
1539 }
1540 else
1541 {
1542 Assert((HDA_REG(pThis, RIRBCTL) & HDA_RIRBCTL_RDMAEN));
1543 rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
1544 if (RT_FAILURE(rc))
1545 AssertRCReturn(rc, rc);
1546# ifdef DEBUG_CMD_BUFFER
1547 uint8_t i = 0;
1548 do {
1549 LogFunc(("RIRB%02x: ", i));
1550 uint8_t j = 0;
1551 do {
1552 const char *prefix;
1553 if ((i + j) == HDA_REG(pThis, RIRBWP))
1554 prefix = "[W]";
1555 else
1556 prefix = " ";
1557 LogFunc((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
1558 } while (++j < 8);
1559 LogFunc(("\n"));
1560 i += 8;
1561 } while (i != 0);
1562# endif
1563 }
1564 return rc;
1565}
1566
1567static int hdaCORBCmdProcess(PHDASTATE pThis)
1568{
1569 int rc = hdaCmdSync(pThis, true);
1570 if (RT_FAILURE(rc))
1571 AssertRCReturn(rc, rc);
1572
1573 uint8_t corbRp = HDA_REG(pThis, CORBRP);
1574 uint8_t corbWp = HDA_REG(pThis, CORBWP);
1575 uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
1576
1577 Assert((corbWp != corbRp));
1578 Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1579
1580 while (corbRp != corbWp)
1581 {
1582 uint64_t uResp;
1583 uint32_t uCmd = pThis->pu32CorbBuf[++corbRp];
1584
1585 int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(uCmd, 0 /* Codec index */), &uResp);
1586 if (RT_FAILURE(rc2))
1587 LogFunc(("Codec lookup failed with rc=%Rrc\n", rc2));
1588
1589 (rirbWp)++;
1590
1591 if ( (uResp & CODEC_RESPONSE_UNSOLICITED)
1592 && !(HDA_REG(pThis, GCTL) & HDA_GCTL_UNSOL))
1593 {
1594 LogFunc(("Unexpected unsolicited response\n"));
1595 HDA_REG(pThis, CORBRP) = corbRp;
1596 return rc;
1597 }
1598
1599 pThis->pu64RirbBuf[rirbWp] = uResp;
1600
1601 pThis->u8RespIntCnt++;
1602 if (pThis->u8RespIntCnt == RINTCNT_N(pThis))
1603 break;
1604 }
1605
1606 HDA_REG(pThis, CORBRP) = corbRp;
1607 HDA_REG(pThis, RIRBWP) = rirbWp;
1608
1609 rc = hdaCmdSync(pThis, false);
1610
1611 Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
1612
1613 if (HDA_REG(pThis, RIRBCTL) & HDA_RIRBCTL_RINTCTL)
1614 {
1615 HDA_REG(pThis, RIRBSTS) |= HDA_RIRBSTS_RINTFL;
1616
1617 pThis->u8RespIntCnt = 0;
1618 rc = hdaProcessInterrupt(pThis);
1619 }
1620
1621 if (RT_FAILURE(rc))
1622 AssertRCReturn(rc, rc);
1623 return rc;
1624}
1625
1626static int hdaStreamCreate(PHDASTATE pThis, PHDASTREAM pStream, uint8_t uSD)
1627{
1628 RT_NOREF(pThis);
1629 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1630 AssertReturn(uSD <= HDA_MAX_STREAMS, VERR_INVALID_PARAMETER);
1631
1632 int rc = RTCritSectInit(&pStream->State.CritSect);
1633 if (RT_SUCCESS(rc))
1634 {
1635 pStream->u8SD = uSD;
1636 pStream->pMixSink = NULL;
1637
1638 pStream->State.fInReset = false;
1639 }
1640
1641 if (RT_SUCCESS(rc))
1642 rc = RTCircBufCreate(&pStream->State.pCircBuf, _4K); /** @todo Make this configurable. */
1643
1644 LogFlowFunc(("uSD=%RU8\n", uSD));
1645 return rc;
1646}
1647
1648static void hdaStreamDestroy(PHDASTATE pThis, PHDASTREAM pStream)
1649{
1650 AssertPtrReturnVoid(pStream);
1651
1652 LogFlowFunc(("[SD%RU8]: Destroying ...\n", pStream->u8SD));
1653
1654 hdaStreamMapDestroy(&pStream->State.Mapping);
1655
1656 int rc2;
1657
1658#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1659 rc2 = hdaStreamAsyncIODestroy(pThis, pStream);
1660 AssertRC(rc2);
1661#else
1662 RT_NOREF(pThis);
1663#endif
1664
1665 rc2 = RTCritSectDelete(&pStream->State.CritSect);
1666 AssertRC(rc2);
1667
1668 if (pStream->State.pCircBuf)
1669 {
1670 RTCircBufDestroy(pStream->State.pCircBuf);
1671 pStream->State.pCircBuf = NULL;
1672 }
1673
1674 LogFlowFuncLeave();
1675}
1676
1677static int hdaStreamInit(PHDASTATE pThis, PHDASTREAM pStream, uint8_t u8SD)
1678{
1679 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1680 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1681
1682 pStream->u8SD = u8SD;
1683 pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
1684 HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
1685 pStream->u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
1686 pStream->u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
1687 pStream->u16FIFOS = HDA_STREAM_REG(pThis, FIFOS, pStream->u8SD) + 1;
1688
1689 RT_ZERO(pStream->State.BDLE);
1690 pStream->State.uCurBDLE = 0;
1691
1692 hdaStreamMapReset(&pStream->State.Mapping);
1693
1694 LogFlowFunc(("[SD%RU8]: DMA @ 0x%x (%RU32 bytes), LVI=%RU16, FIFOS=%RU16\n",
1695 pStream->u8SD, pStream->u64BDLBase, pStream->u32CBL, pStream->u16LVI, pStream->u16FIFOS));
1696
1697# ifdef DEBUG
1698 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
1699 HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
1700 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
1701 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
1702
1703 LogFlowFunc(("\t-> DMA @ 0x%x, LVI=%RU16, CBL=%RU32\n", u64BaseDMA, u16LVI, u32CBL));
1704
1705 hdaBDLEDumpAll(pThis, u64BaseDMA, u16LVI + 1);
1706# endif
1707
1708 return VINF_SUCCESS;
1709}
1710
1711/**
1712 * Resets an HDA stream.
1713 *
1714 * @param pThis HDA state.
1715 * @param pStream HDA stream to reset.
1716 */
1717static void hdaStreamReset(PHDASTATE pThis, PHDASTREAM pStream)
1718{
1719 AssertPtrReturnVoid(pThis);
1720 AssertPtrReturnVoid(pStream);
1721
1722 const uint8_t uSD = pStream->u8SD;
1723
1724# ifdef VBOX_STRICT
1725 AssertReleaseMsg(!RT_BOOL(HDA_STREAM_REG(pThis, CTL, uSD) & HDA_SDCTL_RUN),
1726 ("[SD%RU8] Cannot reset stream while in running state\n", uSD));
1727# endif
1728
1729 LogFunc(("[SD%RU8]: Reset\n", uSD));
1730
1731 /*
1732 * First, reset the internal stream state.
1733 */
1734 RT_ZERO(pStream->State.BDLE);
1735 pStream->State.uCurBDLE = 0;
1736
1737 if (pStream->State.pCircBuf)
1738 RTCircBufReset(pStream->State.pCircBuf);
1739
1740 /*
1741 * Second, initialize the registers.
1742 */
1743 HDA_STREAM_REG(pThis, STS, uSD) = HDA_SDSTS_FIFORDY;
1744 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
1745 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
1746 HDA_STREAM_REG(pThis, CTL, uSD) = 0x40000 | (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_SDCTL_SRST);
1747 /*
1748 * ICH6 defines default values (120 bytes for input and 192 bytes for output descriptors) of FIFO size. 18.2.39.
1749 * BUT: Windows guests seem to read the FIFOS but define a DMA region which does not fit to that FIFO size
1750 * (e.g. 1792 bytes DMA region vs. 192 bytes FIFOS).
1751 * This will lead to crackling and corrupted sound -- so define a 256 bytes FIOS for output streams here per default.
1752 */
1753 HDA_STREAM_REG(pThis, FIFOS, uSD) = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? HDA_SDIFIFO_120B : HDA_SDOFIFO_256B;
1754 /* See 18.2.38: Always defaults to 0x4 (32 bytes). */
1755 HDA_STREAM_REG(pThis, FIFOW, uSD) = HDA_SDFIFOW_32B;
1756 HDA_STREAM_REG(pThis, LPIB, uSD) = 0;
1757 HDA_STREAM_REG(pThis, CBL, uSD) = 0;
1758 HDA_STREAM_REG(pThis, LVI, uSD) = 0;
1759 HDA_STREAM_REG(pThis, FMT, uSD) = HDA_SDFMT_MAKE(HDA_SDFMT_TYPE_PCM, HDA_SDFMT_BASE_44KHZ,
1760 HDA_SDFMT_MULT_1X, HDA_SDFMT_DIV_1X, HDA_SDFMT_16_BIT,
1761 HDA_SDFMT_CHAN_STEREO);
1762 HDA_STREAM_REG(pThis, BDPU, uSD) = 0;
1763 HDA_STREAM_REG(pThis, BDPL, uSD) = 0;
1764
1765 int rc2 = hdaStreamInit(pThis, pStream, uSD);
1766 AssertRC(rc2);
1767}
1768
1769/**
1770 * Enables or disables an HDA audio stream.
1771 *
1772 * @returns IPRT status code.
1773 * @param pThis HDA state.
1774 * @param pStream HDA stream to enable or disable.
1775 * @param fEnable Whether to enable or disble the stream.
1776 */
1777static int hdaStreamEnable(PHDASTATE pThis, PHDASTREAM pStream, bool fEnable)
1778{
1779 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1780 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1781
1782 LogFunc(("[SD%RU8]: fEnable=%RTbool, pMixSink=%p\n", pStream->u8SD, fEnable, pStream->pMixSink));
1783
1784 int rc = VINF_SUCCESS;
1785
1786 hdaStreamLock(pStream);
1787
1788#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1789 hdaStreamAsyncIOLock(pStream);
1790 hdaStreamAsyncIOEnable(pStream, fEnable);
1791#endif
1792
1793 if (pStream->pMixSink) /* Stream attached to a sink? */
1794 {
1795 AUDMIXSINKCMD enmCmd = fEnable
1796 ? AUDMIXSINKCMD_ENABLE : AUDMIXSINKCMD_DISABLE;
1797
1798 /* First, enable or disable the stream and the stream's sink, if any. */
1799 if (pStream->pMixSink->pMixSink)
1800 rc = AudioMixerSinkCtl(pStream->pMixSink->pMixSink, enmCmd);
1801 }
1802
1803#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1804 hdaStreamAsyncIOUnlock(pStream);
1805#endif
1806
1807 /* Make sure to leave the lock before (eventually) starting the timer. */
1808 hdaStreamUnlock(pStream);
1809
1810#ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
1811 /* Second, see if we need to start or stop the timer. */
1812 if (!fEnable)
1813 hdaTimerMaybeStop(pThis);
1814 else
1815 hdaTimerMaybeStart(pThis);
1816#endif
1817
1818 LogFunc(("[SD%RU8]: cStreamsActive=%RU8, rc=%Rrc\n", pStream->u8SD, pThis->cStreamsActive, rc));
1819 return rc;
1820}
1821
1822# if defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_AUDIO_HDA_51_SURROUND)
1823static int hdaStreamChannelExtract(PPDMAUDIOSTREAMCHANNEL pChan, const void *pvBuf, size_t cbBuf)
1824{
1825 AssertPtrReturn(pChan, VERR_INVALID_POINTER);
1826 AssertPtrReturn(pvBuf, VERR_INVALID_POINTER);
1827 AssertReturn(cbBuf, VERR_INVALID_PARAMETER);
1828
1829 AssertRelease(pChan->cbOff <= cbBuf);
1830
1831 const uint8_t *pu8Buf = (const uint8_t *)pvBuf;
1832
1833 size_t cbSrc = cbBuf - pChan->cbOff;
1834 const uint8_t *pvSrc = &pu8Buf[pChan->cbOff];
1835
1836 size_t cbDst;
1837 uint8_t *pvDst;
1838 RTCircBufAcquireWriteBlock(pChan->Data.pCircBuf, cbBuf, (void **)&pvDst, &cbDst);
1839
1840 cbSrc = RT_MIN(cbSrc, cbDst);
1841
1842 while (cbSrc)
1843 {
1844 AssertBreak(cbDst >= cbSrc);
1845
1846 /* Enough data for at least one next frame? */
1847 if (cbSrc < pChan->cbFrame)
1848 break;
1849
1850 memcpy(pvDst, pvSrc, pChan->cbFrame);
1851
1852 /* Advance to next channel frame in stream. */
1853 pvSrc += pChan->cbStep;
1854 Assert(cbSrc >= pChan->cbStep);
1855 cbSrc -= pChan->cbStep;
1856
1857 /* Advance destination by one frame. */
1858 pvDst += pChan->cbFrame;
1859 Assert(cbDst >= pChan->cbFrame);
1860 cbDst -= pChan->cbFrame;
1861
1862 /* Adjust offset. */
1863 pChan->cbOff += pChan->cbFrame;
1864 }
1865
1866 RTCircBufReleaseWriteBlock(pChan->Data.pCircBuf, cbDst);
1867
1868 return VINF_SUCCESS;
1869}
1870# endif /* defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_AUDIO_HDA_51_SURROUND) */
1871
1872# if 0 /** @todo hdaStreamChannelAdvance is unused */
1873static int hdaStreamChannelAdvance(PPDMAUDIOSTREAMCHANNEL pChan, size_t cbAdv)
1874{
1875 AssertPtrReturn(pChan, VERR_INVALID_POINTER);
1876
1877 if (!cbAdv)
1878 return VINF_SUCCESS;
1879
1880 return VINF_SUCCESS;
1881}
1882# endif
1883
1884static int hdaStreamChannelDataInit(PPDMAUDIOSTREAMCHANNELDATA pChanData, uint32_t fFlags)
1885{
1886 int rc = RTCircBufCreate(&pChanData->pCircBuf, 256); /** @todo Make this configurable? */
1887 if (RT_SUCCESS(rc))
1888 {
1889 pChanData->fFlags = fFlags;
1890 }
1891
1892 return rc;
1893}
1894
1895/**
1896 * Frees a stream channel data block again.
1897 *
1898 * @param pChanData Pointer to channel data to free.
1899 */
1900static void hdaStreamChannelDataDestroy(PPDMAUDIOSTREAMCHANNELDATA pChanData)
1901{
1902 if (!pChanData)
1903 return;
1904
1905 if (pChanData->pCircBuf)
1906 {
1907 RTCircBufDestroy(pChanData->pCircBuf);
1908 pChanData->pCircBuf = NULL;
1909 }
1910
1911 pChanData->fFlags = PDMAUDIOSTREAMCHANNELDATA_FLAG_NONE;
1912}
1913
1914# if defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_AUDIO_HDA_51_SURROUND)
1915
1916static int hdaStreamChannelAcquireData(PPDMAUDIOSTREAMCHANNELDATA pChanData, void *pvData, size_t *pcbData)
1917{
1918 AssertPtrReturn(pChanData, VERR_INVALID_POINTER);
1919 AssertPtrReturn(pvData, VERR_INVALID_POINTER);
1920 AssertPtrReturn(pcbData, VERR_INVALID_POINTER);
1921
1922 RTCircBufAcquireReadBlock(pChanData->pCircBuf, 256 /** @todo Make this configurarble? */, &pvData, &pChanData->cbAcq);
1923
1924 *pcbData = pChanData->cbAcq;
1925 return VINF_SUCCESS;
1926}
1927
1928static int hdaStreamChannelReleaseData(PPDMAUDIOSTREAMCHANNELDATA pChanData)
1929{
1930 AssertPtrReturn(pChanData, VERR_INVALID_POINTER);
1931 RTCircBufReleaseReadBlock(pChanData->pCircBuf, pChanData->cbAcq);
1932
1933 return VINF_SUCCESS;
1934}
1935
1936# endif /* defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT) || defined(VBOX_WITH_AUDIO_HDA_51_SURROUND) */
1937
1938# if 0 /* currently unused */
1939static int hdaStreamWaitForStateChange(PHDASTREAM pStream, RTMSINTERVAL msTimeout)
1940{
1941 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
1942
1943 LogFlowFunc(("[SD%RU8]: msTimeout=%RU32\n", pStream->u8SD, msTimeout));
1944 return RTSemEventWait(pStream->State.hStateChangedEvent, msTimeout);
1945}
1946# endif /* currently unused */
1947
1948#endif /* IN_RING3 */
1949
1950/* Register access handlers. */
1951
1952static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1953{
1954 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg);
1955 *pu32Value = 0;
1956 return VINF_SUCCESS;
1957}
1958
1959static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1960{
1961 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
1962 return VINF_SUCCESS;
1963}
1964
1965/* U8 */
1966static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1967{
1968 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
1969 return hdaRegReadU32(pThis, iReg, pu32Value);
1970}
1971
1972static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1973{
1974 Assert((u32Value & 0xffffff00) == 0);
1975 return hdaRegWriteU32(pThis, iReg, u32Value);
1976}
1977
1978/* U16 */
1979static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1980{
1981 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
1982 return hdaRegReadU32(pThis, iReg, pu32Value);
1983}
1984
1985static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1986{
1987 Assert((u32Value & 0xffff0000) == 0);
1988 return hdaRegWriteU32(pThis, iReg, u32Value);
1989}
1990
1991/* U24 */
1992static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1993{
1994 Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
1995 return hdaRegReadU32(pThis, iReg, pu32Value);
1996}
1997
1998#ifdef IN_RING3
1999static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2000{
2001 Assert((u32Value & 0xff000000) == 0);
2002 return hdaRegWriteU32(pThis, iReg, u32Value);
2003}
2004#endif
2005
2006/* U32 */
2007static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2008{
2009 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2010
2011 *pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
2012 return VINF_SUCCESS;
2013}
2014
2015static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2016{
2017 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2018
2019 pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
2020 | (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
2021 return VINF_SUCCESS;
2022}
2023
2024static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2025{
2026 RT_NOREF_PV(iReg);
2027
2028 if (u32Value & HDA_GCTL_CRST)
2029 {
2030 /* Set the CRST bit to indicate that we're leaving reset mode. */
2031 HDA_REG(pThis, GCTL) |= HDA_GCTL_CRST;
2032
2033 if (pThis->fInReset)
2034 {
2035 LogFunc(("Guest leaving HDA reset\n"));
2036 pThis->fInReset = false;
2037 }
2038 }
2039 else
2040 {
2041#ifdef IN_RING3
2042 /* Enter reset state. */
2043 LogFunc(("Guest entering HDA reset with DMA(RIRB:%s, CORB:%s)\n",
2044 HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA ? "on" : "off",
2045 HDA_REG(pThis, RIRBCTL) & HDA_RIRBCTL_RDMAEN ? "on" : "off"));
2046
2047 /* Clear the CRST bit to indicate that we're in reset state. */
2048 HDA_REG(pThis, GCTL) &= ~HDA_GCTL_CRST;
2049 pThis->fInReset = true;
2050
2051 hdaReset(pThis->CTX_SUFF(pDevIns));
2052#else
2053 return VINF_IOM_R3_MMIO_WRITE;
2054#endif
2055 }
2056
2057 if (u32Value & HDA_GCTL_FCNTRL)
2058 {
2059 /* Flush: GSTS:1 set, see 6.2.6. */
2060 HDA_REG(pThis, GSTS) |= HDA_GSTS_FSTS; /* Set the flush status. */
2061 /* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
2062 }
2063 return VINF_SUCCESS;
2064}
2065
2066static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2067{
2068 uint32_t v = HDA_REG_IND(pThis, iReg);
2069 uint32_t nv = u32Value & HDA_STATESTS_SCSF_MASK;
2070
2071 HDA_REG(pThis, STATESTS) &= ~(v & nv); /* Write of 1 clears corresponding bit. */
2072
2073 return hdaProcessInterrupt(pThis);
2074}
2075
2076static int hdaRegWriteINTCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2077{
2078 RT_NOREF(iReg);
2079
2080 int rc;
2081
2082 HDA_REG(pThis, INTCTL) = u32Value;
2083
2084 /* Global Interrupt Enable (GIE) set? */
2085 if (u32Value & HDA_INTCTL_GIE)
2086 {
2087 rc = hdaProcessInterrupt(pThis);
2088 }
2089 else
2090 {
2091 /* Make sure to lower interrupt line, as Global Interrupt Enable (GIE) is disabled. */
2092 PDMDevHlpPCISetIrq(pThis->CTX_SUFF(pDevIns), 0, 0 /* iLevel */);
2093
2094 rc = VINF_SUCCESS;
2095 }
2096
2097 return rc;
2098}
2099
2100static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2101{
2102 const uint8_t u8Strm = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
2103 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, u8Strm);
2104#ifdef LOG_ENABLED
2105 const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, u8Strm);
2106 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32\n", u8Strm, u32LPIB, u32CBL));
2107#endif
2108
2109 *pu32Value = u32LPIB;
2110 return VINF_SUCCESS;
2111}
2112
2113static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2114{
2115 RT_NOREF_PV(iReg);
2116
2117 /* HDA spec (1a): 3.3.16 WALCLK counter ticks with 24Mhz bitclock rate. */
2118 *pu32Value = (uint32_t)ASMMultU64ByU32DivByU32(PDMDevHlpTMTimeVirtGetNano(pThis->CTX_SUFF(pDevIns))
2119 - pThis->u64BaseTS, 24, 1000);
2120 LogFlowFunc(("%RU32\n", *pu32Value));
2121 return VINF_SUCCESS;
2122}
2123
2124static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2125{
2126 RT_NOREF_PV(iReg);
2127
2128 if (u32Value & HDA_CORBRP_RST)
2129 {
2130 HDA_REG(pThis, CORBRP) = 0;
2131 }
2132#ifndef BIRD_THINKS_CORBRP_IS_MOSTLY_RO
2133 else
2134 return hdaRegWriteU8(pThis, iReg, u32Value);
2135#endif
2136 return VINF_SUCCESS;
2137}
2138
2139static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2140{
2141#ifdef IN_RING3
2142 int rc = hdaRegWriteU8(pThis, iReg, u32Value);
2143 AssertRC(rc);
2144 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2145 && (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA))
2146 {
2147 return hdaCORBCmdProcess(pThis);
2148 }
2149 return rc;
2150#else
2151 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2152 return VINF_IOM_R3_MMIO_WRITE;
2153#endif
2154}
2155
2156static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2157{
2158 RT_NOREF_PV(iReg);
2159
2160 uint32_t v = HDA_REG(pThis, CORBSTS);
2161 HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
2162 return VINF_SUCCESS;
2163}
2164
2165static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2166{
2167#ifdef IN_RING3
2168 int rc;
2169 rc = hdaRegWriteU16(pThis, iReg, u32Value);
2170 if (RT_FAILURE(rc))
2171 AssertRCReturn(rc, rc);
2172 if (HDA_REG(pThis, CORBWP) == HDA_REG(pThis, CORBRP))
2173 return VINF_SUCCESS;
2174 if (!(HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA))
2175 return VINF_SUCCESS;
2176 rc = hdaCORBCmdProcess(pThis);
2177 return rc;
2178#else /* !IN_RING3 */
2179 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2180 return VINF_IOM_R3_MMIO_WRITE;
2181#endif /* IN_RING3 */
2182}
2183
2184static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2185{
2186#ifdef IN_RING3
2187 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2188 return VINF_SUCCESS;
2189
2190 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, CBL, iReg));
2191 if (!pStream)
2192 {
2193 LogFunc(("[SD%RU8]: Warning: Changing SDCBL on non-attached stream (0x%x)\n",
2194 HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
2195 return hdaRegWriteU32(pThis, iReg, u32Value);
2196 }
2197
2198 pStream->u32CBL = u32Value;
2199
2200 /* Reset BDLE state. */
2201 RT_ZERO(pStream->State.BDLE);
2202 pStream->State.uCurBDLE = 0;
2203
2204 int rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2205 AssertRC(rc2);
2206
2207 LogFlowFunc(("[SD%RU8]: CBL=%RU32\n", pStream->u8SD, u32Value));
2208
2209 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2210#else /* !IN_RING3 */
2211 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2212 return VINF_IOM_R3_MMIO_WRITE;
2213#endif /* IN_RING3 */
2214}
2215
2216static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2217{
2218#ifdef IN_RING3
2219 /*
2220 * Some guests write too much (that is, 32-bit with the top 8 bit being junk)
2221 * instead of 24-bit required for SDCTL. So just mask this here to be safe.
2222 */
2223 u32Value = (u32Value & 0x00ffffff);
2224
2225 bool fRun = RT_BOOL(u32Value & HDA_SDCTL_RUN);
2226 bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_SDCTL_RUN);
2227
2228 bool fReset = RT_BOOL(u32Value & HDA_SDCTL_SRST);
2229 bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_SDCTL_SRST);
2230
2231 /* Get the stream descriptor. */
2232 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
2233
2234 LogFunc(("[SD%RU8]: fRun=%RTbool, fInRun=%RTbool, fReset=%RTbool, fInReset=%RTbool, %R[sdctl]\n",
2235 uSD, fRun, fInRun, fReset, fInReset, u32Value));
2236
2237 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2238 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2239
2240 /*
2241 * Extract the stream tag the guest wants to use for this specific
2242 * stream descriptor (SDn). This only can happen if the stream is in a non-running
2243 * state, so we're doing the lookup and assignment here.
2244 *
2245 * So depending on the guest OS, SD3 can use stream tag 4, for example.
2246 */
2247 uint8_t uTag = (u32Value >> HDA_SDCTL_NUM_SHIFT) & HDA_SDCTL_NUM_MASK;
2248 if (uTag > HDA_MAX_TAGS)
2249 {
2250 LogFunc(("[SD%RU8]: Warning: Invalid stream tag %RU8 specified!\n", uSD, uTag));
2251 return hdaRegWriteU24(pThis, iReg, u32Value);
2252 }
2253
2254 PHDATAG pTag = &pThis->aTags[uTag];
2255 AssertPtr(pTag);
2256
2257 LogFunc(("[SD%RU8]: Using stream tag=%RU8\n", uSD, uTag));
2258
2259 /* Assign new values. */
2260 pTag->uTag = uTag;
2261 pTag->pStrm = hdaStreamGetFromSD(pThis, uSD);
2262
2263 PHDASTREAM pStream = pTag->pStrm;
2264 AssertPtr(pStream);
2265
2266 if (fInReset)
2267 {
2268 Assert(!fReset);
2269 Assert(!fInRun && !fRun);
2270
2271 /* Exit reset state. */
2272 ASMAtomicXchgBool(&pStream->State.fInReset, false);
2273
2274 /* Report that we're done resetting this stream by clearing SRST. */
2275 HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_SRST;
2276
2277 LogFunc(("[SD%RU8]: Reset exit\n", uSD));
2278 }
2279 else if (fReset)
2280 {
2281 /* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
2282 Assert(!fInRun && !fRun);
2283
2284 LogFunc(("[SD%RU8]: Reset enter\n", pStream->u8SD));
2285
2286 /* Enter reset state. */
2287 Assert(ASMAtomicReadBool(&pStream->State.fInReset) == false); /* No nested calls. */
2288 ASMAtomicXchgBool(&pStream->State.fInReset, true);
2289
2290 hdaStreamLock(pStream);
2291
2292 hdaStreamReset(pThis, pStream);
2293
2294 hdaStreamUnlock(pStream);
2295 }
2296 else
2297 {
2298 /*
2299 * We enter here to change DMA states only.
2300 */
2301 if (fInRun != fRun)
2302 {
2303 Assert(!fReset && !fInReset);
2304 LogFunc(("[SD%RU8]: State changed (fRun=%RTbool)\n", pStream->u8SD, fRun));
2305
2306 if (fRun)
2307 {
2308 /* Make sure to first fetch the current BDLE before enabling the stream below. */
2309 int rc2 = hdaBDLEFetch(pThis, &pStream->State.BDLE, pStream->u64BDLBase, pStream->State.uCurBDLE);
2310 AssertRC(rc2);
2311 }
2312
2313 hdaStreamEnable(pThis, pStream, fRun /* fEnable */);
2314 }
2315 }
2316
2317 int rc2 = hdaRegWriteU24(pThis, iReg, u32Value);
2318 AssertRC(rc2);
2319
2320 /* Make sure to handle interrupts here as well. */
2321 hdaProcessInterrupt(pThis);
2322
2323 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2324#else /* !IN_RING3 */
2325 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2326 return VINF_IOM_R3_MMIO_WRITE;
2327#endif /* IN_RING3 */
2328}
2329
2330static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2331{
2332 uint32_t v = HDA_REG_IND(pThis, iReg);
2333
2334 /* Clear (zero) FIFOE, DESE and BCIS bits when writing 1 to it (6.2.33). */
2335 HDA_REG_IND(pThis, iReg) &= ~(u32Value & v);
2336
2337 LogFunc(("SDSTS 0x%x -> 0x%x\n", v, HDA_REG_IND(pThis, iReg)));
2338
2339 hdaProcessInterrupt(pThis);
2340 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2341}
2342
2343static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2344{
2345#ifdef IN_RING3
2346 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2347 return VINF_SUCCESS;
2348
2349 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, LVI, iReg);
2350
2351 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, uSD);
2352 if (!pStream)
2353 {
2354 AssertMsgFailed(("[SD%RU8]: Warning: Changing SDLVI on non-attached stream (0x%x)\n", uSD, u32Value));
2355 return hdaRegWriteU16(pThis, iReg, u32Value);
2356 }
2357
2358 /** @todo Validate LVI. */
2359 pStream->u16LVI = u32Value;
2360 LogFunc(("[SD%RU8]: Updating LVI to %RU16\n", uSD, pStream->u16LVI));
2361
2362 /* Reset BDLE state. */
2363 RT_ZERO(pStream->State.BDLE);
2364 pStream->State.uCurBDLE = 0;
2365
2366 int rc2 = hdaRegWriteU16(pThis, iReg, u32Value);
2367 AssertRC(rc2);
2368
2369 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2370#else /* !IN_RING3 */
2371 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2372 return VINF_IOM_R3_MMIO_WRITE;
2373#endif /* IN_RING3 */
2374}
2375
2376static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2377{
2378#ifdef IN_RING3
2379 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg);
2380
2381 if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_IN) /* FIFOW for input streams only. */
2382 {
2383 LogRel(("HDA: Warning: Guest tried to write read-only FIFOW to output stream #%RU8, ignoring\n", uSD));
2384 return VINF_SUCCESS;
2385 }
2386
2387 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg));
2388 if (!pStream)
2389 {
2390 AssertMsgFailed(("[SD%RU8]: Warning: Changing FIFOW on non-attached stream (0x%x)\n", uSD, u32Value));
2391 return hdaRegWriteU16(pThis, iReg, u32Value);
2392 }
2393
2394 uint32_t u32FIFOW = 0;
2395
2396 switch (u32Value)
2397 {
2398 case HDA_SDFIFOW_8B:
2399 case HDA_SDFIFOW_16B:
2400 case HDA_SDFIFOW_32B:
2401 u32FIFOW = u32Value;
2402 break;
2403 default:
2404 LogRel(("HDA: Warning: Guest tried write unsupported FIFOW (0x%x) to stream #%RU8, defaulting to 32 bytes\n",
2405 u32Value, uSD));
2406 AssertFailed();
2407 u32FIFOW = HDA_SDFIFOW_32B;
2408 break;
2409 }
2410
2411 if (u32FIFOW)
2412 {
2413 pStream->u16FIFOW = hdaSDFIFOWToBytes(u32FIFOW);
2414 LogFunc(("[SD%RU8]: Updating FIFOW to %RU32 bytes\n", uSD, pStream->u16FIFOW));
2415
2416 int rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOW);
2417 AssertRC(rc2);
2418 }
2419
2420 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2421#else /* !IN_RING3 */
2422 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2423 return VINF_IOM_R3_MMIO_WRITE;
2424#endif /* IN_RING3 */
2425}
2426
2427/**
2428 * @note This method could be called for changing value on Output Streams only (ICH6 datasheet 18.2.39).
2429 */
2430static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2431{
2432#ifdef IN_RING3
2433 uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOS, iReg);
2434
2435 if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_OUT) /* FIFOS for output streams only. */
2436 {
2437 LogRel(("HDA: Warning: Guest tried to write read-only FIFOS to input stream #%RU8, ignoring\n", uSD));
2438 return VINF_SUCCESS;
2439 }
2440
2441 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, uSD);
2442 if (!pStream)
2443 {
2444 AssertMsgFailed(("[SD%RU8]: Warning: Changing FIFOS on non-attached stream (0x%x)\n", uSD, u32Value));
2445 return hdaRegWriteU16(pThis, iReg, u32Value);
2446 }
2447
2448 uint32_t u32FIFOS = 0;
2449
2450 switch(u32Value)
2451 {
2452 case HDA_SDOFIFO_16B:
2453 case HDA_SDOFIFO_32B:
2454 case HDA_SDOFIFO_64B:
2455 case HDA_SDOFIFO_128B:
2456 case HDA_SDOFIFO_192B:
2457 case HDA_SDOFIFO_256B:
2458 u32FIFOS = u32Value;
2459 break;
2460
2461 default:
2462 LogRel(("HDA: Warning: Guest tried write unsupported FIFOS (0x%x) to stream #%RU8, defaulting to 192 bytes\n",
2463 u32Value, uSD));
2464 AssertFailed();
2465 u32FIFOS = HDA_SDOFIFO_192B;
2466 break;
2467 }
2468
2469 if (u32FIFOS)
2470 {
2471 pStream->u16FIFOS = u32FIFOS + 1;
2472 LogFunc(("[SD%RU8]: Updating FIFOS to %RU32 bytes\n", uSD, pStream->u16FIFOS));
2473
2474 int rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOS);
2475 AssertRC(rc2);
2476 }
2477
2478 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2479#else /* !IN_RING3 */
2480 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2481 return VINF_IOM_R3_MMIO_WRITE;
2482#endif /* IN_RING3 */
2483}
2484
2485#ifdef IN_RING3
2486static int hdaSDFMTToStrmCfg(uint32_t u32SDFMT, PPDMAUDIOSTREAMCFG pStrmCfg)
2487{
2488 AssertPtrReturn(pStrmCfg, VERR_INVALID_POINTER);
2489
2490# define EXTRACT_VALUE(v, mask, shift) ((v & ((mask) << (shift))) >> (shift))
2491
2492 int rc = VINF_SUCCESS;
2493
2494 uint32_t u32Hz = EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BASE_RATE_MASK, HDA_SDFMT_BASE_RATE_SHIFT)
2495 ? 44100 : 48000;
2496 uint32_t u32HzMult = 1;
2497 uint32_t u32HzDiv = 1;
2498
2499 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT))
2500 {
2501 case 0: u32HzMult = 1; break;
2502 case 1: u32HzMult = 2; break;
2503 case 2: u32HzMult = 3; break;
2504 case 3: u32HzMult = 4; break;
2505 default:
2506 LogFunc(("Unsupported multiplier %x\n",
2507 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_MULT_MASK, HDA_SDFMT_MULT_SHIFT)));
2508 rc = VERR_NOT_SUPPORTED;
2509 break;
2510 }
2511 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT))
2512 {
2513 case 0: u32HzDiv = 1; break;
2514 case 1: u32HzDiv = 2; break;
2515 case 2: u32HzDiv = 3; break;
2516 case 3: u32HzDiv = 4; break;
2517 case 4: u32HzDiv = 5; break;
2518 case 5: u32HzDiv = 6; break;
2519 case 6: u32HzDiv = 7; break;
2520 case 7: u32HzDiv = 8; break;
2521 default:
2522 LogFunc(("Unsupported divisor %x\n",
2523 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_DIV_MASK, HDA_SDFMT_DIV_SHIFT)));
2524 rc = VERR_NOT_SUPPORTED;
2525 break;
2526 }
2527
2528 uint8_t cBits = 0;
2529 switch (EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT))
2530 {
2531 case 0:
2532 cBits = 8;
2533 break;
2534 case 1:
2535 cBits = 16;
2536 break;
2537 case 4:
2538 cBits = 32;
2539 break;
2540 default:
2541 AssertMsgFailed(("Unsupported bits per sample %x\n",
2542 EXTRACT_VALUE(u32SDFMT, HDA_SDFMT_BITS_MASK, HDA_SDFMT_BITS_SHIFT)));
2543 rc = VERR_NOT_SUPPORTED;
2544 break;
2545 }
2546
2547 if (RT_SUCCESS(rc))
2548 {
2549 RT_ZERO(pStrmCfg->Props);
2550
2551 pStrmCfg->Props.uHz = u32Hz * u32HzMult / u32HzDiv;
2552 pStrmCfg->Props.cChannels = (u32SDFMT & 0xf) + 1;
2553 pStrmCfg->Props.cBits = cBits;
2554 pStrmCfg->Props.fSigned = true;
2555 pStrmCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pStrmCfg->Props.cBits, pStrmCfg->Props.cChannels);
2556 }
2557
2558# undef EXTRACT_VALUE
2559 return rc;
2560}
2561
2562static int hdaAddStreamOut(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
2563{
2564 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2565 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2566
2567 AssertReturn(pCfg->enmDir == PDMAUDIODIR_OUT, VERR_INVALID_PARAMETER);
2568
2569 LogFlowFunc(("Stream=%s\n", pCfg->szName));
2570
2571 int rc = VINF_SUCCESS;
2572
2573 bool fUseFront = true; /* Always use front out by default. */
2574#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2575 bool fUseRear;
2576 bool fUseCenter;
2577 bool fUseLFE;
2578
2579 fUseRear = fUseCenter = fUseLFE = false;
2580
2581 /*
2582 * Use commonly used setups for speaker configurations.
2583 */
2584
2585 /** @todo Make the following configurable through mixer API and/or CFGM? */
2586 switch (pCfg->cChannels)
2587 {
2588 case 3: /* 2.1: Front (Stereo) + LFE. */
2589 {
2590 fUseLFE = true;
2591 break;
2592 }
2593
2594 case 4: /* Quadrophonic: Front (Stereo) + Rear (Stereo). */
2595 {
2596 fUseRear = true;
2597 break;
2598 }
2599
2600 case 5: /* 4.1: Front (Stereo) + Rear (Stereo) + LFE. */
2601 {
2602 fUseRear = true;
2603 fUseLFE = true;
2604 break;
2605 }
2606
2607 case 6: /* 5.1: Front (Stereo) + Rear (Stereo) + Center/LFE. */
2608 {
2609 fUseRear = true;
2610 fUseCenter = true;
2611 fUseLFE = true;
2612 break;
2613 }
2614
2615 default: /* Unknown; fall back to 2 front channels (stereo). */
2616 {
2617 rc = VERR_NOT_SUPPORTED;
2618 break;
2619 }
2620 }
2621#else /* !VBOX_WITH_AUDIO_HDA_51_SURROUND */
2622 /* Only support mono or stereo channels. */
2623 if ( pCfg->Props.cChannels != 1 /* Mono */
2624 && pCfg->Props.cChannels != 2 /* Stereo */)
2625 {
2626 rc = VERR_NOT_SUPPORTED;
2627 }
2628#endif
2629
2630 if (rc == VERR_NOT_SUPPORTED)
2631 {
2632 LogRel(("HDA: Unsupported channel count (%RU8), falling back to stereo channels\n", pCfg->Props.cChannels));
2633 pCfg->Props.cChannels = 2;
2634
2635 rc = VINF_SUCCESS;
2636 }
2637
2638 do
2639 {
2640 if (RT_FAILURE(rc))
2641 break;
2642
2643 if (fUseFront)
2644 {
2645 RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Front");
2646 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_FRONT;
2647 pCfg->Props.cChannels = 2;
2648
2649 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT);
2650 if (RT_SUCCESS(rc))
2651 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT, pCfg);
2652 }
2653
2654#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2655 if ( RT_SUCCESS(rc)
2656 && (fUseCenter || fUseLFE))
2657 {
2658 RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Center/LFE");
2659 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_CENTER_LFE;
2660 pCfg->Props.cChannels = (fUseCenter && fUseLFE) ? 2 : 1;
2661
2662 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE);
2663 if (RT_SUCCESS(rc))
2664 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE, pCfg);
2665 }
2666
2667 if ( RT_SUCCESS(rc)
2668 && fUseRear)
2669 {
2670 RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Rear");
2671 pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_REAR;
2672 pCfg->Props.cChannels = 2;
2673
2674 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR);
2675 if (RT_SUCCESS(rc))
2676 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR, pCfg);
2677 }
2678#endif /* VBOX_WITH_AUDIO_HDA_51_SURROUND */
2679
2680 } while (0);
2681
2682 LogFlowFuncLeaveRC(rc);
2683 return rc;
2684}
2685
2686static int hdaAddStreamIn(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
2687{
2688 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2689 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2690
2691 AssertReturn(pCfg->enmDir == PDMAUDIODIR_IN, VERR_INVALID_PARAMETER);
2692
2693 LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Source));
2694
2695 int rc;
2696
2697 switch (pCfg->DestSource.Source)
2698 {
2699 case PDMAUDIORECSOURCE_LINE:
2700 {
2701 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN);
2702 if (RT_SUCCESS(rc))
2703 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN, pCfg);
2704 break;
2705 }
2706#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2707 case PDMAUDIORECSOURCE_MIC:
2708 {
2709 rc = hdaCodecRemoveStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN);
2710 if (RT_SUCCESS(rc))
2711 rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN, pCfg);
2712 break;
2713 }
2714#endif
2715 default:
2716 rc = VERR_NOT_SUPPORTED;
2717 break;
2718 }
2719
2720 LogFlowFuncLeaveRC(rc);
2721 return rc;
2722}
2723#endif /* IN_RING3 */
2724
2725static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2726{
2727#ifdef IN_RING3
2728 PDMAUDIOSTREAMCFG strmCfg;
2729 RT_ZERO(strmCfg);
2730
2731 int rc = hdaSDFMTToStrmCfg(u32Value, &strmCfg);
2732 if (RT_FAILURE(rc))
2733 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2734
2735 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FMT, iReg));
2736 if (!pStream)
2737 {
2738 LogFunc(("[SD%RU8]: Warning: Changing SDFMT on non-attached stream (0x%x)\n",
2739 HDA_SD_NUM_FROM_REG(pThis, FMT, iReg), u32Value));
2740 return hdaRegWriteU16(pThis, iReg, u32Value);
2741 }
2742
2743 LogFunc(("[SD%RU8]: Hz=%RU32, Channels=%RU8, cBits=%RU8\n",
2744 pStream->u8SD, strmCfg.Props.uHz, strmCfg.Props.cChannels, strmCfg.Props.cBits));
2745
2746 /* Set audio direction. */
2747 strmCfg.enmDir = hdaGetDirFromSD(pStream->u8SD);
2748 switch (strmCfg.enmDir)
2749 {
2750 case PDMAUDIODIR_IN:
2751# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2752# error "Implement me!"
2753# else
2754 strmCfg.DestSource.Source = PDMAUDIORECSOURCE_LINE;
2755 RTStrCopy(strmCfg.szName, sizeof(strmCfg.szName), "Line In");
2756# endif
2757 break;
2758
2759 case PDMAUDIODIR_OUT:
2760 /* Destination(s) will be set in hdaAddStreamOut(),
2761 * based on the channels / stream layout. */
2762 break;
2763
2764 default:
2765 rc = VERR_NOT_SUPPORTED;
2766 break;
2767 }
2768
2769#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
2770 if (RT_SUCCESS(rc))
2771 {
2772 rc = hdaStreamAsyncIOCreate(pThis, pStream);
2773 AssertRC(rc);
2774 }
2775#endif
2776
2777 /*
2778 * Initialize the stream mapping in any case, regardless if
2779 * we support surround audio or not. This is needed to handle
2780 * the supported channels within a single audio stream, e.g. mono/stereo.
2781 *
2782 * In other words, the stream mapping *always* knowns the real
2783 * number of channels in a single audio stream.
2784 */
2785 if (RT_SUCCESS(rc))
2786 {
2787 rc = hdaStreamMapInit(&pStream->State.Mapping, &strmCfg);
2788 AssertRC(rc);
2789 }
2790
2791 if (RT_SUCCESS(rc))
2792 {
2793 PHDADRIVER pDrv;
2794 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2795 {
2796 int rc2;
2797 switch (strmCfg.enmDir)
2798 {
2799 case PDMAUDIODIR_OUT:
2800 rc2 = hdaAddStreamOut(pThis, &strmCfg);
2801 break;
2802
2803 case PDMAUDIODIR_IN:
2804 rc2 = hdaAddStreamIn(pThis, &strmCfg);
2805 break;
2806
2807 default:
2808 rc2 = VERR_NOT_SUPPORTED;
2809 AssertFailed();
2810 break;
2811 }
2812
2813 if ( RT_FAILURE(rc2)
2814 && (pDrv->fFlags & PDMAUDIODRVFLAGS_PRIMARY)) /* We only care about primary drivers here, the rest may fail. */
2815 {
2816 if (RT_SUCCESS(rc))
2817 rc = rc2;
2818 /* Keep going. */
2819 }
2820 }
2821
2822 /* If (re-)opening the stream by the codec above failed, don't write the new
2823 * format to the register so that the guest is aware it didn't work. */
2824 if (RT_SUCCESS(rc))
2825 {
2826 rc = hdaRegWriteU16(pThis, iReg, u32Value);
2827 AssertRC(rc);
2828 }
2829 else
2830 LogFunc(("[SD%RU8]: (Re-)Opening stream failed with rc=%Rrc\n", pStream->u8SD, rc));
2831 }
2832
2833 return VINF_SUCCESS; /* Never return failure. */
2834#else /* !IN_RING3 */
2835 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2836 return VINF_IOM_R3_MMIO_WRITE;
2837#endif
2838}
2839
2840/* Note: Will be called for both, BDPL and BDPU, registers. */
2841DECLINLINE(int) hdaRegWriteSDBDPX(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value, uint8_t uSD)
2842{
2843#ifdef IN_RING3
2844 if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
2845 return VINF_SUCCESS;
2846
2847 int rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2848 AssertRC(rc2);
2849
2850 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, uSD);
2851 if (!pStream)
2852 return VINF_SUCCESS;
2853
2854 /* Update BDL base. */
2855 pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, uSD),
2856 HDA_STREAM_REG(pThis, BDPU, uSD));
2857 AssertMsg(pStream->u64BDLBase, ("BDL base invalid\n"));
2858
2859 /* Reset BDLE state. */
2860 RT_ZERO(pStream->State.BDLE);
2861 pStream->State.uCurBDLE = 0;
2862
2863 LogFlowFunc(("[SD%RU8]: BDLBase=0x%x\n", pStream->u8SD, pStream->u64BDLBase));
2864
2865 return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2866#else /* !IN_RING3 */
2867 RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value); RT_NOREF_PV(uSD);
2868 return VINF_IOM_R3_MMIO_WRITE;
2869#endif /* IN_RING3 */
2870}
2871
2872static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2873{
2874 return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPL, iReg));
2875}
2876
2877static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2878{
2879 return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPU, iReg));
2880}
2881
2882static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2883{
2884 /* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
2885 if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2886 || (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA))
2887 {
2888 HDA_REG(pThis, IRS) = HDA_IRS_ICB; /* busy */
2889 }
2890
2891 return hdaRegReadU32(pThis, iReg, pu32Value);
2892}
2893
2894static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2895{
2896 RT_NOREF_PV(iReg);
2897
2898 /*
2899 * If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
2900 * write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
2901 */
2902 if ( (u32Value & HDA_IRS_ICB)
2903 && !(HDA_REG(pThis, IRS) & HDA_IRS_ICB))
2904 {
2905#ifdef IN_RING3
2906 uint32_t uCmd = HDA_REG(pThis, IC);
2907
2908 if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
2909 {
2910 /*
2911 * 3.4.3: Defines behavior of immediate Command status register.
2912 */
2913 LogRel(("HDA: Guest attempted process immediate verb (%x) with active CORB\n", uCmd));
2914 return VINF_SUCCESS;
2915 }
2916
2917 HDA_REG(pThis, IRS) = HDA_IRS_ICB; /* busy */
2918
2919 uint64_t uResp;
2920 int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec,
2921 HDA_CODEC_CMD(uCmd, 0 /* LUN */), &uResp);
2922 if (RT_FAILURE(rc2))
2923 LogFunc(("Codec lookup failed with rc2=%Rrc\n", rc2));
2924
2925 HDA_REG(pThis, IR) = (uint32_t)uResp; /** @todo r=andy Do we need a 64-bit response? */
2926 HDA_REG(pThis, IRS) = HDA_IRS_IRV; /* result is ready */
2927 /** @todo r=michaln We just set the IRS value, why are we clearing unset bits? */
2928 HDA_REG(pThis, IRS) &= ~HDA_IRS_ICB; /* busy is clear */
2929 return VINF_SUCCESS;
2930#else /* !IN_RING3 */
2931 return VINF_IOM_R3_MMIO_WRITE;
2932#endif /* !IN_RING3 */
2933 }
2934
2935 /*
2936 * Once the guest read the response, it should clear the IRV bit of the IRS register.
2937 */
2938 HDA_REG(pThis, IRS) &= ~(u32Value & HDA_IRS_IRV);
2939 return VINF_SUCCESS;
2940}
2941
2942static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2943{
2944 RT_NOREF_PV(iReg);
2945
2946 if (u32Value & HDA_RIRBWP_RST)
2947 HDA_REG(pThis, RIRBWP) = 0;
2948
2949 /* The remaining bits are O, see 6.2.22. */
2950 return VINF_SUCCESS;
2951}
2952
2953static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2954{
2955 uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2956 int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2957 if (RT_FAILURE(rc))
2958 AssertRCReturn(rc, rc);
2959
2960 switch(iReg)
2961 {
2962 case HDA_REG_CORBLBASE:
2963 pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
2964 pThis->u64CORBBase |= pThis->au32Regs[iRegMem];
2965 break;
2966 case HDA_REG_CORBUBASE:
2967 pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
2968 pThis->u64CORBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2969 break;
2970 case HDA_REG_RIRBLBASE:
2971 pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
2972 pThis->u64RIRBBase |= pThis->au32Regs[iRegMem];
2973 break;
2974 case HDA_REG_RIRBUBASE:
2975 pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
2976 pThis->u64RIRBBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2977 break;
2978 case HDA_REG_DPLBASE:
2979 {
2980 pThis->u64DPBase &= UINT64_C(0xFFFFFFFF00000000);
2981 pThis->u64DPBase |= pThis->au32Regs[iRegMem];
2982
2983 /* Also make sure to handle the DMA position enable bit. */
2984 pThis->fDMAPosition = RT_BOOL(pThis->u64DPBase & RT_BIT_64(0));
2985 LogRel2(("HDA: %s DMA position buffer\n", pThis->fDMAPosition ? "Enabled" : "Disabled"));
2986 break;
2987 }
2988 case HDA_REG_DPUBASE:
2989 pThis->u64DPBase &= UINT64_C(0x00000000FFFFFFFF);
2990 pThis->u64DPBase |= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2991 break;
2992 default:
2993 AssertMsgFailed(("Invalid index\n"));
2994 break;
2995 }
2996
2997 LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
2998 pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
2999 return rc;
3000}
3001
3002static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
3003{
3004 RT_NOREF_PV(iReg);
3005
3006 uint8_t v = HDA_REG(pThis, RIRBSTS);
3007 HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
3008
3009 return hdaProcessInterrupt(pThis);
3010}
3011
3012#ifdef IN_RING3
3013#ifdef LOG_ENABLED
3014static void hdaBDLEDumpAll(PHDASTATE pThis, uint64_t u64BDLBase, uint16_t cBDLE)
3015{
3016 LogFlowFunc(("BDLEs @ 0x%x (%RU16):\n", u64BDLBase, cBDLE));
3017 if (!u64BDLBase)
3018 return;
3019
3020 uint32_t cbBDLE = 0;
3021 for (uint16_t i = 0; i < cBDLE; i++)
3022 {
3023 HDABDLEDESC bd;
3024 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BDLBase + i * sizeof(HDABDLEDESC), &bd, sizeof(bd));
3025
3026 LogFunc(("\t#%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
3027 i, bd.u64BufAdr, bd.u32BufSize, bd.fFlags & HDA_BDLE_FLAG_IOC));
3028
3029 cbBDLE += bd.u32BufSize;
3030 }
3031
3032 LogFlowFunc(("Total: %RU32 bytes\n", cbBDLE));
3033
3034 if (!pThis->u64DPBase) /* No DMA base given? Bail out. */
3035 return;
3036
3037 LogFlowFunc(("DMA counters:\n"));
3038
3039 for (int i = 0; i < cBDLE; i++)
3040 {
3041 uint32_t uDMACnt;
3042 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
3043 &uDMACnt, sizeof(uDMACnt));
3044
3045 LogFlowFunc(("\t#%03d DMA @ 0x%x\n", i , uDMACnt));
3046 }
3047}
3048#endif
3049
3050/**
3051 * Fetches a Bundle Descriptor List Entry (BDLE) from the DMA engine.
3052 *
3053 * @param pThis Pointer to HDA state.
3054 * @param pBDLE Where to store the fetched result.
3055 * @param u64BaseDMA Address base of DMA engine to use.
3056 * @param u16Entry BDLE entry to fetch.
3057 */
3058static int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry)
3059{
3060 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3061 AssertPtrReturn(pBDLE, VERR_INVALID_POINTER);
3062 AssertReturn(u64BaseDMA, VERR_INVALID_PARAMETER);
3063
3064 if (!u64BaseDMA)
3065 {
3066 LogRel2(("HDA: Unable to fetch BDLE #%RU16 - no base DMA address set (yet)\n", u16Entry));
3067 return VERR_NOT_FOUND;
3068 }
3069 /** @todo Compare u16Entry with LVI. */
3070
3071 int rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + u16Entry * sizeof(HDABDLEDESC),
3072 &pBDLE->Desc, sizeof(pBDLE->Desc));
3073 if (RT_FAILURE(rc))
3074 return rc;
3075
3076 /* Set internal state. */
3077 pBDLE->State.u32BufOff = 0;
3078 pBDLE->State.u32BDLIndex = u16Entry;
3079
3080 return VINF_SUCCESS;
3081}
3082
3083/**
3084 * Returns the number of outstanding stream data bytes which need to be processed
3085 * by the DMA engine assigned to this stream.
3086 *
3087 * @return Number of bytes for the DMA engine to process.
3088 */
3089DECLINLINE(uint32_t) hdaStreamGetTransferSize(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbMax)
3090{
3091 AssertPtrReturn(pThis, 0);
3092 AssertPtrReturn(pStream, 0);
3093 AssertReturn (cbMax, 0);
3094
3095 PHDABDLE pBDLE = &pStream->State.BDLE;
3096
3097 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3098 Assert(u32LPIB <= pStream->u32CBL);
3099
3100 /* Do we have space left in the CBL at all? */
3101 uint32_t cbData = pStream->u32CBL - u32LPIB;
3102
3103 /* Limit to the available free space of the current BDLE. */
3104 cbData = RT_MIN(cbData, pBDLE->Desc.u32BufSize - pBDLE->State.u32BufOff);
3105
3106 /* Make sure we only transfer as many bytes as requested. */
3107 cbData = RT_MIN(cbData, cbMax);
3108
3109 if (pBDLE->State.cbBelowFIFOW)
3110 {
3111 /* Are we not going to reach (or exceed) the FIFO watermark yet with the data to copy?
3112 * No need to read data from DMA then. */
3113 if (cbData > pBDLE->State.cbBelowFIFOW)
3114 {
3115 /* Subtract the amount of bytes that still would fit in the stream's FIFO
3116 * and therefore do not need to be processed by DMA. */
3117 cbData -= pBDLE->State.cbBelowFIFOW;
3118 }
3119 }
3120
3121 AssertMsg((cbData % 2 == 0), ("Transfer size invalid: %RU32\n", cbData));
3122
3123 Log3Func(("[SD%RU8]: CBL=%RU32, LPIB=%RU32, FIFOS=%RU16, cbData=%RU32, %R[bdle]\n", pStream->u8SD,
3124 pStream->u32CBL, HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), pStream->u16FIFOS,
3125 cbData, pBDLE));
3126
3127 return cbData;
3128}
3129
3130DECLINLINE(void) hdaBDLEUpdate(PHDABDLE pBDLE, uint32_t cbData, uint32_t cbProcessed)
3131{
3132 AssertPtrReturnVoid(pBDLE);
3133
3134 if (!cbData || !cbProcessed)
3135 return;
3136
3137 Assert(pBDLE->Desc.u32BufSize >= cbProcessed);
3138
3139 /* Fewer than cbBelowFIFOW bytes were copied.
3140 * Probably we need to move the buffer, but it is rather hard to imagine a situation
3141 * where it might happen. */
3142 AssertMsg((cbProcessed == pBDLE->State.cbBelowFIFOW + cbData), /* we assume that we write the entire buffer including unreported bytes */
3143 ("cbProcessed=%RU32 != pBDLE->State.cbBelowFIFOW=%RU32 + cbData=%RU32\n",
3144 cbProcessed, pBDLE->State.cbBelowFIFOW, cbData));
3145
3146#if 0
3147 if ( pBDLE->State.cbBelowFIFOW
3148 && pBDLE->State.cbBelowFIFOW <= cbWritten)
3149 {
3150 LogFlowFunc(("BDLE(cbUnderFifoW:%RU32, off:%RU32, size:%RU32)\n",
3151 pBDLE->State.cbBelowFIFOW, pBDLE->State.u32BufOff, pBDLE->Desc.u32BufSize));
3152 }
3153#endif
3154
3155 pBDLE->State.cbBelowFIFOW -= RT_MIN(pBDLE->State.cbBelowFIFOW, cbProcessed);
3156 Assert(pBDLE->State.cbBelowFIFOW == 0);
3157
3158 /* We always increment the position of DMA buffer counter because we're always reading
3159 * into an intermediate buffer. */
3160 Assert(pBDLE->Desc.u32BufSize >= (pBDLE->State.u32BufOff + cbProcessed));
3161 pBDLE->State.u32BufOff += cbProcessed;
3162
3163 LogFlowFunc(("cbData=%RU32, cbProcessed=%RU32, %R[bdle]\n", cbData, cbProcessed, pBDLE));
3164}
3165
3166#ifdef IN_RING3
3167/**
3168 * Initializes a stream mapping structure according to the given stream configuration.
3169 *
3170 * @return IPRT status code.
3171 * @param pMapping Pointer to mapping to initialize.
3172 * @param pCfg Pointer to stream configuration to use.
3173 */
3174static int hdaStreamMapInit(PHDASTREAMMAPPING pMapping, PPDMAUDIOSTREAMCFG pCfg)
3175{
3176 AssertPtrReturn(pMapping, VERR_INVALID_POINTER);
3177 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3178
3179 AssertReturn(pCfg->Props.cChannels, VERR_INVALID_PARAMETER);
3180
3181 hdaStreamMapReset(pMapping);
3182
3183 pMapping->paChannels = (PPDMAUDIOSTREAMCHANNEL)RTMemAlloc(sizeof(PDMAUDIOSTREAMCHANNEL) * pCfg->Props.cChannels);
3184 if (!pMapping->paChannels)
3185 return VERR_NO_MEMORY;
3186
3187 if (!DrvAudioHlpStreamCfgIsValid(pCfg))
3188 return VERR_INVALID_PARAMETER;
3189
3190 int rc = VINF_SUCCESS;
3191
3192 Assert(RT_IS_POWER_OF_TWO(pCfg->Props.cBits));
3193
3194 /** @todo We assume all channels in a stream have the same format. */
3195 PPDMAUDIOSTREAMCHANNEL pChan = pMapping->paChannels;
3196 for (uint8_t i = 0; i < pCfg->Props.cChannels; i++)
3197 {
3198 pChan->uChannel = i;
3199 pChan->cbStep = (pCfg->Props.cBits / 2);
3200 pChan->cbFrame = pChan->cbStep * pCfg->Props.cChannels;
3201 pChan->cbFirst = i * pChan->cbStep;
3202 pChan->cbOff = pChan->cbFirst;
3203
3204 int rc2 = hdaStreamChannelDataInit(&pChan->Data, PDMAUDIOSTREAMCHANNELDATA_FLAG_NONE);
3205 if (RT_SUCCESS(rc))
3206 rc = rc2;
3207
3208 if (RT_FAILURE(rc))
3209 break;
3210
3211 pChan++;
3212 }
3213
3214 if ( RT_SUCCESS(rc)
3215 /* Create circular buffer if not created yet. */
3216 && !pMapping->pCircBuf)
3217 {
3218 rc = RTCircBufCreate(&pMapping->pCircBuf, _4K); /** @todo Make size configurable? */
3219 }
3220
3221 if (RT_SUCCESS(rc))
3222 {
3223 pMapping->cChannels = pCfg->Props.cChannels;
3224#ifdef VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT
3225 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_INTERLEAVED;
3226#else
3227 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
3228#endif
3229 }
3230
3231 return rc;
3232}
3233
3234/**
3235 * Destroys a given stream mapping.
3236 *
3237 * @param pMapping Pointer to mapping to destroy.
3238 */
3239static void hdaStreamMapDestroy(PHDASTREAMMAPPING pMapping)
3240{
3241 hdaStreamMapReset(pMapping);
3242
3243 if (pMapping->pCircBuf)
3244 {
3245 RTCircBufDestroy(pMapping->pCircBuf);
3246 pMapping->pCircBuf = NULL;
3247 }
3248}
3249
3250/**
3251 * Resets a given stream mapping.
3252 *
3253 * @param pMapping Pointer to mapping to reset.
3254 */
3255static void hdaStreamMapReset(PHDASTREAMMAPPING pMapping)
3256{
3257 AssertPtrReturnVoid(pMapping);
3258
3259 pMapping->enmLayout = PDMAUDIOSTREAMLAYOUT_UNKNOWN;
3260
3261 if (pMapping->cChannels)
3262 {
3263 for (uint8_t i = 0; i < pMapping->cChannels; i++)
3264 hdaStreamChannelDataDestroy(&pMapping->paChannels[i].Data);
3265
3266 AssertPtr(pMapping->paChannels);
3267 RTMemFree(pMapping->paChannels);
3268 pMapping->paChannels = NULL;
3269
3270 pMapping->cChannels = 0;
3271 }
3272}
3273#endif /* IN_RING3 */
3274
3275DECLINLINE(bool) hdaStreamNeedsNextBDLE(PHDASTATE pThis, PHDASTREAM pStream)
3276{
3277 AssertPtrReturn(pThis, false);
3278 AssertPtrReturn(pStream, false);
3279
3280 PHDABDLE pBDLE = &pStream->State.BDLE;
3281 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD);
3282
3283 /* Did we reach the CBL (Cyclic Buffer List) limit? */
3284 bool fCBLLimitReached = u32LPIB >= pStream->u32CBL;
3285
3286 /* Do we need to use the next BDLE entry? Either because we reached
3287 * the CBL limit or our internal DMA buffer is full. */
3288 bool fNeedsNextBDLE = ( fCBLLimitReached
3289 || (pBDLE->State.u32BufOff >= pBDLE->Desc.u32BufSize));
3290
3291 Assert(u32LPIB <= pStream->u32CBL);
3292 Assert(pBDLE->State.u32BufOff <= pBDLE->Desc.u32BufSize);
3293
3294 LogFlowFunc(("[SD%RU8]: LPIB=%RU32, CBL=%RU32, fCBLLimitReached=%RTbool, fNeedsNextBDLE=%RTbool, %R[bdle]\n",
3295 pStream->u8SD, u32LPIB, pStream->u32CBL, fCBLLimitReached, fNeedsNextBDLE, pBDLE));
3296
3297 return fNeedsNextBDLE;
3298}
3299
3300DECLINLINE(void) hdaStreamTransferUpdate(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbInc)
3301{
3302 AssertPtrReturnVoid(pThis);
3303 AssertPtrReturnVoid(pStream);
3304
3305 if (!cbInc) /* Nothing to do? Bail out early. */
3306 return;
3307
3308 /*
3309 * If we're below the FIFO watermark (SDFIFOW), it's expected that HDA
3310 * doesn't fetch anything via DMA, so just update LPIB.
3311 * (ICH6 datasheet 18.2.38).
3312 */
3313 PHDABDLE pBDLE = &pStream->State.BDLE;
3314 if (pBDLE->State.cbBelowFIFOW == 0) /* Did we hit (or exceed) the watermark? */
3315 {
3316 uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) + cbInc;
3317
3318 Log3Func(("[SD%RU8]: LPIB: %RU32 -> %RU32, CBL=%RU32\n",
3319 pStream->u8SD, HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), u32LPIB, pStream->u32CBL));
3320
3321 hdaStreamUpdateLPIB(pThis, pStream, u32LPIB);
3322 }
3323}
3324
3325static bool hdaBDLEIsComplete(PHDABDLE pBDLE, bool *pfInterrupt)
3326{
3327 AssertPtrReturn(pBDLE, true);
3328
3329 bool fInterrupt = false;
3330 bool fIsComplete = false;
3331
3332 /* Check if the current BDLE entry is complete (full). */
3333 if (pBDLE->State.u32BufOff >= pBDLE->Desc.u32BufSize)
3334 {
3335 Assert(pBDLE->State.u32BufOff <= pBDLE->Desc.u32BufSize);
3336
3337 if (/* IOC (Interrupt On Completion) bit set? */
3338 pBDLE->Desc.fFlags & HDA_BDLE_FLAG_IOC
3339 /* All data put into the DMA FIFO? */
3340 && pBDLE->State.cbBelowFIFOW == 0
3341 )
3342 {
3343 fInterrupt = true;
3344 }
3345
3346 fIsComplete = true;
3347 }
3348
3349 if (pfInterrupt)
3350 *pfInterrupt = fInterrupt;
3351
3352 LogFlowFunc(("%R[bdle] fIsComplete=%RTbool, fInterrupt=%RTbool\n", pBDLE, fIsComplete, fInterrupt));
3353
3354 return fIsComplete;
3355}
3356
3357/**
3358 * Retrieves a corresponding sink for a given mixer control.
3359 * Returns NULL if no sink is found.
3360 *
3361 * @return PHDAMIXERSINK
3362 * @param pThis HDA state.
3363 * @param enmMixerCtl Mixer control to get the corresponding sink for.
3364 */
3365static PHDAMIXERSINK hdaMixerControlToSink(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
3366{
3367 PHDAMIXERSINK pSink;
3368
3369 switch (enmMixerCtl)
3370 {
3371 case PDMAUDIOMIXERCTL_VOLUME_MASTER:
3372 /* Fall through is intentional. */
3373 case PDMAUDIOMIXERCTL_FRONT:
3374 pSink = &pThis->SinkFront;
3375 break;
3376#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3377 case PDMAUDIOMIXERCTL_CENTER_LFE:
3378 pSink = &pThis->SinkCenterLFE;
3379 break;
3380 case PDMAUDIOMIXERCTL_REAR:
3381 pSink = &pThis->SinkRear;
3382 break;
3383#endif
3384 case PDMAUDIOMIXERCTL_LINE_IN:
3385 pSink = &pThis->SinkLineIn;
3386 break;
3387#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3388 case PDMAUDIOMIXERCTL_MIC_IN:
3389 pSink = &pThis->SinkMicIn;
3390 break;
3391#endif
3392 default:
3393 pSink = NULL;
3394 AssertMsgFailed(("Unhandled mixer control\n"));
3395 break;
3396 }
3397
3398 return pSink;
3399}
3400
3401static DECLCALLBACK(int) hdaMixerAddStream(PHDASTATE pThis, PHDAMIXERSINK pSink, PPDMAUDIOSTREAMCFG pCfg)
3402{
3403 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3404 AssertPtrReturn(pSink, VERR_INVALID_POINTER);
3405 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3406
3407 LogFunc(("Sink=%s, Stream=%s\n", pSink->pMixSink->pszName, pCfg->szName));
3408
3409 if (!DrvAudioHlpStreamCfgIsValid(pCfg))
3410 return VERR_INVALID_PARAMETER;
3411
3412 int rc = AudioMixerSinkSetFormat(pSink->pMixSink, &pCfg->Props);
3413 if (RT_FAILURE(rc))
3414 return rc;
3415
3416 PHDADRIVER pDrv;
3417 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3418 {
3419 int rc2 = VINF_SUCCESS;
3420 PHDADRIVERSTREAM pDrvStream = NULL;
3421
3422 PPDMAUDIOSTREAMCFG pStreamCfg = DrvAudioHlpStreamCfgDup(pCfg);
3423 if (!pStreamCfg)
3424 {
3425 rc = VERR_NO_MEMORY;
3426 break;
3427 }
3428
3429 /* Include the driver's LUN in the stream name for easier identification. */
3430 RTStrPrintf(pStreamCfg->szName, RT_ELEMENTS(pStreamCfg->szName), "[LUN#%RU8] %s", pDrv->uLUN, pCfg->szName);
3431
3432 if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
3433 {
3434 LogFunc(("enmRecSource=%d\n", pStreamCfg->DestSource.Source));
3435
3436 switch (pStreamCfg->DestSource.Source)
3437 {
3438 case PDMAUDIORECSOURCE_LINE:
3439 pDrvStream = &pDrv->LineIn;
3440 break;
3441#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3442 case PDMAUDIORECSOURCE_MIC:
3443 pDrvStream = &pDrv->MicIn;
3444 break;
3445#endif
3446 default:
3447 rc2 = VERR_NOT_SUPPORTED;
3448 break;
3449 }
3450 }
3451 else if (pStreamCfg->enmDir == PDMAUDIODIR_OUT)
3452 {
3453 LogFunc(("enmPlaybackDest=%d\n", pStreamCfg->DestSource.Dest));
3454
3455 switch (pStreamCfg->DestSource.Dest)
3456 {
3457 case PDMAUDIOPLAYBACKDEST_FRONT:
3458 pDrvStream = &pDrv->Front;
3459 break;
3460#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3461 case PDMAUDIOPLAYBACKDEST_CENTER_LFE:
3462 pDrvStream = &pDrv->CenterLFE;
3463 break;
3464 case PDMAUDIOPLAYBACKDEST_REAR:
3465 pDrvStream = &pDrv->Rear;
3466 break;
3467#endif
3468 default:
3469 rc2 = VERR_NOT_SUPPORTED;
3470 break;
3471 }
3472 }
3473 else
3474 rc2 = VERR_NOT_SUPPORTED;
3475
3476 if (RT_SUCCESS(rc2))
3477 {
3478 AssertPtr(pDrvStream);
3479
3480 AudioMixerSinkRemoveStream(pSink->pMixSink, pDrvStream->pMixStrm);
3481
3482 AudioMixerStreamDestroy(pDrvStream->pMixStrm);
3483 pDrvStream->pMixStrm = NULL;
3484
3485 PAUDMIXSTREAM pMixStrm;
3486 rc2 = AudioMixerSinkCreateStream(pSink->pMixSink, pDrv->pConnector, pStreamCfg, 0 /* fFlags */, &pMixStrm);
3487 if (RT_SUCCESS(rc2))
3488 {
3489 rc2 = AudioMixerSinkAddStream(pSink->pMixSink, pMixStrm);
3490 LogFlowFunc(("LUN#%RU8: Added \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName , rc2));
3491 }
3492
3493 if (RT_SUCCESS(rc2))
3494 pDrvStream->pMixStrm = pMixStrm;
3495
3496 /* If creating a stream fails, be forgiving and continue -- don't pass rc2 to rc here. */
3497 }
3498
3499 if (pStreamCfg)
3500 {
3501 RTMemFree(pStreamCfg);
3502 pStreamCfg = NULL;
3503 }
3504 }
3505
3506 LogFlowFuncLeaveRC(rc);
3507 return rc;
3508}
3509
3510/**
3511 * Adds a new audio stream to a specific mixer control.
3512 * Depending on the mixer control the stream then gets assigned to one of the internal
3513 * mixer sinks, which in turn then handle the mixing of all connected streams to that sink.
3514 *
3515 * @return IPRT status code.
3516 * @param pThis HDA state.
3517 * @param enmMixerCtl Mixer control to assign new stream to.
3518 * @param pCfg Stream configuration for the new stream.
3519 */
3520static DECLCALLBACK(int) hdaMixerAddStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOSTREAMCFG pCfg)
3521{
3522 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3523 AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
3524
3525 int rc;
3526
3527 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3528 if (pSink)
3529 {
3530 rc = hdaMixerAddStream(pThis, pSink, pCfg);
3531
3532 AssertPtr(pSink->pMixSink);
3533 LogFlowFunc(("Sink=%s, enmMixerCtl=%d\n", pSink->pMixSink->pszName, enmMixerCtl));
3534 }
3535 else
3536 rc = VERR_NOT_FOUND;
3537
3538 LogFlowFuncLeaveRC(rc);
3539 return rc;
3540}
3541
3542/**
3543 * Removes a specified mixer control from the HDA's mixer.
3544 *
3545 * @return IPRT status code.
3546 * @param pThis HDA state.
3547 * @param enmMixerCtl Mixer control to remove.
3548 *
3549 * @remarks Can be called as a callback by the HDA codec.
3550 */
3551static DECLCALLBACK(int) hdaMixerRemoveStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
3552{
3553 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3554
3555 int rc;
3556
3557 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3558 if (pSink)
3559 {
3560 PHDADRIVER pDrv;
3561 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3562 {
3563 PAUDMIXSTREAM pMixStream = NULL;
3564 switch (enmMixerCtl)
3565 {
3566 /*
3567 * Input.
3568 */
3569 case PDMAUDIOMIXERCTL_LINE_IN:
3570 pMixStream = pDrv->LineIn.pMixStrm;
3571 pDrv->LineIn.pMixStrm = NULL;
3572 break;
3573#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3574 case PDMAUDIOMIXERCTL_MIC_IN:
3575 pMixStream = pDrv->MicIn.pMixStrm;
3576 pDrv->MicIn.pMixStrm = NULL;
3577 break;
3578#endif
3579 /*
3580 * Output.
3581 */
3582 case PDMAUDIOMIXERCTL_FRONT:
3583 pMixStream = pDrv->Front.pMixStrm;
3584 pDrv->Front.pMixStrm = NULL;
3585 break;
3586#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3587 case PDMAUDIOMIXERCTL_CENTER_LFE:
3588 pMixStream = pDrv->CenterLFE.pMixStrm;
3589 pDrv->CenterLFE.pMixStrm = NULL;
3590 break;
3591 case PDMAUDIOMIXERCTL_REAR:
3592 pMixStream = pDrv->Rear.pMixStrm;
3593 pDrv->Rear.pMixStrm = NULL;
3594 break;
3595#endif
3596 default:
3597 AssertMsgFailed(("Mixer control %d not implemented\n", enmMixerCtl));
3598 break;
3599 }
3600
3601 if (pMixStream)
3602 {
3603 AudioMixerSinkRemoveStream(pSink->pMixSink, pMixStream);
3604 AudioMixerStreamDestroy(pMixStream);
3605
3606 pMixStream = NULL;
3607 }
3608 }
3609
3610 AudioMixerSinkRemoveAllStreams(pSink->pMixSink);
3611 rc = VINF_SUCCESS;
3612 }
3613 else
3614 rc = VERR_NOT_FOUND;
3615
3616 LogFlowFunc(("enmMixerCtl=%d, rc=%Rrc\n", enmMixerCtl, rc));
3617 return rc;
3618}
3619
3620/**
3621 * Sets a SDn stream number and channel to a particular mixer control.
3622 *
3623 * @returns IPRT status code.
3624 * @param pThis HDA State.
3625 * @param enmMixerCtl Mixer control to set SD stream number and channel for.
3626 * @param uSD SD stream number (number + 1) to set. Set to 0 for unassign.
3627 * @param uChannel Channel to set. Only valid if a valid SD stream number is specified.
3628 *
3629 * @remarks Can be called as a callback by the HDA codec.
3630 */
3631static DECLCALLBACK(int) hdaMixerSetStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, uint8_t uSD, uint8_t uChannel)
3632{
3633 LogFlowFunc(("enmMixerCtl=%RU32, uSD=%RU8, uChannel=%RU8\n", enmMixerCtl, uSD, uChannel));
3634
3635 if (uSD == 0) /* Stream number 0 is reserved. */
3636 {
3637 LogFlowFunc(("Invalid SDn (%RU8) number for mixer control %d, ignoring\n", uSD, enmMixerCtl));
3638 return VINF_SUCCESS;
3639 }
3640 /* uChannel is optional. */
3641
3642 /* SDn0 starts as 1. */
3643 Assert(uSD);
3644 uSD--;
3645
3646 int rc;
3647
3648 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3649 if (pSink)
3650 {
3651 if ( (uSD < HDA_MAX_SDI)
3652 && AudioMixerSinkGetDir(pSink->pMixSink) == AUDMIXSINKDIR_OUTPUT)
3653 {
3654 uSD += HDA_MAX_SDI;
3655 }
3656
3657 LogFlowFunc(("%s: Setting to stream ID=%RU8, channel=%RU8, enmMixerCtl=%RU32\n",
3658 pSink->pMixSink->pszName, uSD, uChannel, enmMixerCtl));
3659
3660 Assert(uSD < HDA_MAX_STREAMS);
3661
3662 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, uSD);
3663 if (pStream)
3664 {
3665 hdaStreamLock(pStream);
3666
3667 pSink->uSD = uSD;
3668 pSink->uChannel = uChannel;
3669 pStream->pMixSink = pSink;
3670
3671 hdaStreamUnlock(pStream);
3672
3673 rc = VINF_SUCCESS;
3674 }
3675 else
3676 {
3677 LogRel(("HDA: Guest wanted to assign invalid stream ID=%RU8 (channel %RU8) to mixer control %RU32, skipping\n",
3678 uSD, uChannel, enmMixerCtl));
3679 rc = VERR_INVALID_PARAMETER;
3680 }
3681 }
3682 else
3683 rc = VERR_NOT_FOUND;
3684
3685 LogFlowFuncLeaveRC(rc);
3686 return rc;
3687}
3688
3689/**
3690 * Sets the volume of a specified mixer control.
3691 *
3692 * @return IPRT status code.
3693 * @param pThis HDA State.
3694 * @param enmMixerCtl Mixer control to set volume for.
3695 * @param pVol Pointer to volume data to set.
3696 *
3697 * @remarks Can be called as a callback by the HDA codec.
3698 */
3699static DECLCALLBACK(int) hdaMixerSetVolume(PHDASTATE pThis,
3700 PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOVOLUME pVol)
3701{
3702 int rc;
3703
3704 PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
3705 if (pSink)
3706 {
3707 /* Set the volume.
3708 * We assume that the codec already converted it to the correct range. */
3709 rc = AudioMixerSinkSetVolume(pSink->pMixSink, pVol);
3710 }
3711 else
3712 rc = VERR_NOT_FOUND;
3713
3714 LogFlowFuncLeaveRC(rc);
3715 return rc;
3716}
3717
3718#ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
3719/**
3720 * Starts the internal audio device timer (if not started yet).
3721 *
3722 * @param pThis HDA state.
3723 */
3724static void hdaTimerMaybeStart(PHDASTATE pThis)
3725{
3726 LogFlowFuncEnter();
3727
3728 if (!pThis->pTimer)
3729 return;
3730
3731 pThis->cStreamsActive++;
3732
3733 /* Only start the timer at the first active stream. */
3734 if (pThis->cStreamsActive == 1)
3735 {
3736 LogRel2(("HDA: Starting transfers\n"));
3737
3738 /* Set timer flag. */
3739 ASMAtomicXchgBool(&pThis->fTimerActive, true);
3740
3741 /* Update current time timestamp. */
3742 pThis->uTimerTS = TMTimerGet(pThis->pTimer);
3743
3744 /* Start transfers. */
3745 hdaTimerMain(pThis);
3746 }
3747}
3748
3749/**
3750 * Stops the internal audio device timer.
3751 *
3752 * @param pThis HDA state.
3753 */
3754static void hdaTimerStop(PHDASTATE pThis)
3755{
3756 LogFlowFuncEnter();
3757
3758 /* Set timer flag. */
3759 ASMAtomicXchgBool(&pThis->fTimerActive, false);
3760}
3761
3762/**
3763 * Decreases the active HDA streams count by one and
3764 * then checks if the internal audio device timer can be
3765 * stopped.
3766 *
3767 * @param pThis HDA state.
3768 */
3769static void hdaTimerMaybeStop(PHDASTATE pThis)
3770{
3771 LogFlowFuncEnter();
3772
3773 if (!pThis->pTimer)
3774 return;
3775
3776 if (pThis->cStreamsActive) /* Disable can be called mupltiple times. */
3777 {
3778 pThis->cStreamsActive--;
3779
3780 if (pThis->cStreamsActive == 0)
3781 hdaTimerStop(pThis);
3782 }
3783}
3784
3785/**
3786 * Main routine for the device timer.
3787 *
3788 * @returns IPRT status code.
3789 * @param pThis HDA state.
3790 */
3791static void hdaTimerMain(PHDASTATE pThis)
3792{
3793 AssertPtrReturnVoid(pThis);
3794
3795 STAM_PROFILE_START(&pThis->StatTimer, a);
3796
3797 uint64_t cTicksNow = TMTimerGet(pThis->pTimer);
3798
3799 /* Update current time timestamp. */
3800 pThis->uTimerTS = cTicksNow;
3801
3802 /* Flag indicating whether to kick the timer again for a
3803 * new data processing round. */
3804 bool fKickTimer = false;
3805
3806 hdaDoTransfers(pThis);
3807
3808 /* Do we need to kick the timer again? */
3809 if ( AudioMixerSinkIsActive(pThis->SinkFront.pMixSink)
3810#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3811 || AudioMixerSinkIsActive(pThis->SinkCenterLFE.pMixSink)
3812 || AudioMixerSinkIsActive(pThis->SinkRear.pMixSink)
3813#endif
3814 || AudioMixerSinkIsActive(pThis->SinkLineIn.pMixSink)
3815#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3816 || AudioMixerSinkIsActive(pThis->SinkMicIn.pMixSink)
3817#endif
3818 )
3819 {
3820 fKickTimer = true;
3821 }
3822
3823 pThis->uTimerMS = RTTimeMilliTS();
3824
3825 if ( ASMAtomicReadBool(&pThis->fTimerActive)
3826 || fKickTimer)
3827 {
3828 /* Kick the timer again. */
3829 uint64_t cTicks = pThis->cTimerTicks;
3830 /** @todo adjust cTicks down by now much cbOutMin represents. */
3831 TMTimerSet(pThis->pTimer, cTicksNow + cTicks);
3832 }
3833 else
3834 LogRel2(("HDA: Stopping transfers\n"));
3835
3836 STAM_PROFILE_STOP(&pThis->StatTimer, a);
3837}
3838
3839/**
3840 * Timer callback which handles the audio data transfers on a periodic basis.
3841 *
3842 * @param pDevIns Device instance.
3843 * @param pTimer Timer which was used when calling this.
3844 * @param pvUser User argument as PHDASTATE.
3845 */
3846static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3847{
3848 RT_NOREF(pDevIns, pTimer);
3849
3850 PHDASTATE pThis = (PHDASTATE)pvUser;
3851 Assert(pThis == PDMINS_2_DATA(pDevIns, PHDASTATE));
3852 AssertPtr(pThis);
3853
3854 hdaTimerMain(pThis);
3855}
3856
3857#else /* VBOX_WITH_AUDIO_HDA_CALLBACKS */
3858
3859static DECLCALLBACK(int) hdaCallbackInput(PDMAUDIOCBTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
3860{
3861 Assert(enmType == PDMAUDIOCALLBACKTYPE_INPUT);
3862 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
3863 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
3864 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
3865 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
3866
3867 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
3868 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
3869
3870 PPDMAUDIOCBDATA_DATA_INPUT pData = (PPDMAUDIOCBDATA_DATA_INPUT)pvUser;
3871 AssertReturn(cbUser == sizeof(PDMAUDIOCBDATA_DATA_INPUT), VERR_INVALID_PARAMETER);
3872
3873 return hdaStreamDoDMA(pCtx->pThis, PI_INDEX, UINT32_MAX, &pData->cbOutRead);
3874}
3875
3876static DECLCALLBACK(int) hdaCallbackOutput(PDMAUDIOCBTYPE enmType, void *pvCtx, size_t cbCtx, void *pvUser, size_t cbUser)
3877{
3878 Assert(enmType == PDMAUDIOCALLBACKTYPE_OUTPUT);
3879 AssertPtrReturn(pvCtx, VERR_INVALID_POINTER);
3880 AssertReturn(cbCtx, VERR_INVALID_PARAMETER);
3881 AssertPtrReturn(pvUser, VERR_INVALID_POINTER);
3882 AssertReturn(cbUser, VERR_INVALID_PARAMETER);
3883
3884 PHDACALLBACKCTX pCtx = (PHDACALLBACKCTX)pvCtx;
3885 AssertReturn(cbCtx == sizeof(HDACALLBACKCTX), VERR_INVALID_PARAMETER);
3886
3887 PPDMAUDIOCBDATA_DATA_OUTPUT pData = (PPDMAUDIOCBDATA_DATA_OUTPUT)pvUser;
3888 AssertReturn(cbUser == sizeof(PDMAUDIOCBDATA_DATA_OUTPUT), VERR_INVALID_PARAMETER);
3889
3890 PHDASTATE pThis = pCtx->pThis;
3891
3892 int rc = hdaStreamDoDMA(pCtx->pThis, PO_INDEX, UINT32_MAX, &pData->cbOutWritten);
3893 if ( RT_SUCCESS(rc)
3894 && pData->cbOutWritten)
3895 {
3896 PHDADRIVER pDrv;
3897 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
3898 {
3899 uint32_t cSamplesPlayed;
3900 int rc2 = pDrv->pConnector->pfnPlay(pDrv->pConnector, &cSamplesPlayed);
3901 LogFlowFunc(("LUN#%RU8: cSamplesPlayed=%RU32, rc=%Rrc\n", pDrv->uLUN, cSamplesPlayed, rc2));
3902 }
3903 }
3904}
3905#endif /* VBOX_WITH_AUDIO_HDA_CALLBACKS */
3906
3907/**
3908 * Main routine to perform the actual audio data transfers from the HDA streams
3909 * to the backend(s) and vice versa.
3910 *
3911 * @param pThis HDA state.
3912 */
3913static void hdaDoTransfers(PHDASTATE pThis)
3914{
3915 PHDASTREAM pStreamLineIn = hdaSinkGetStream(pThis, &pThis->SinkLineIn);
3916#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3917 PHDASTREAM pStreamMicIn = hdaSinkGetStream(pThis, &pThis->SinkMicIn);
3918#endif
3919 PHDASTREAM pStreamFront = hdaSinkGetStream(pThis, &pThis->SinkFront);
3920#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3921 /** @todo See note below. */
3922#endif
3923
3924 hdaStreamUpdate(pThis, pStreamLineIn);
3925#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3926 hdaStreamUpdate(pThis, pStreamMicIn);
3927#endif
3928 hdaStreamUpdate(pThis, pStreamFront);
3929
3930
3931#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3932 int rc2 = AudioMixerSinkUpdate(pThis->SinkCenterLFE.pMixSink);
3933 AssertRC(rc2);
3934
3935 rc2 = AudioMixerSinkUpdate(pThis->SinkRear.pMixSink);
3936 AssertRC(rc2);
3937 /** @todo Check for stream interleaving and only call hdaStreamDoDMA() if required! */
3938
3939 /*
3940 * Only call hdaTransfer if CenterLFE and/or Rear are on different SDs,
3941 * otherwise we have to use the interleaved streams support for getting the data
3942 * out of the Front sink (depending on the mapping layout).
3943 */
3944#endif
3945}
3946
3947#ifdef DEBUG_andy
3948# define HDA_DEBUG_DMA
3949#endif
3950
3951/**
3952 * Does a single DMA transfer for a specific HDA stream (SDI/SDO).
3953 * This either can be a read or write operation, depending on the HDA stream.
3954 *
3955 * @returns IPRT status code.
3956 * @param pThis HDA state.
3957 * @param pStream HDA stream to do the DMA transfer for.
3958 * @param pvBuf Pointer to buffer data to write data to / read data from.
3959 * @param cbBuf Size of buffer (in bytes).
3960 * @param cbToProcess Size (in bytes) to transfer (read/write).
3961 * @param pcbProcessed Size (in bytes) transferred (read/written). Optional.
3962 */
3963static int hdaStreamDoDMA(PHDASTATE pThis, PHDASTREAM pStream, void *pvBuf, uint32_t cbBuf,
3964 uint32_t cbToProcess, uint32_t *pcbProcessed)
3965{
3966 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
3967 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
3968 AssertPtrReturn(pvBuf, VERR_INVALID_POINTER);
3969 AssertReturn(cbBuf >= cbToProcess, VERR_INVALID_PARAMETER);
3970 /* pcbProcessed is optional. */
3971
3972 if (ASMAtomicReadBool(&pThis->fInReset)) /* HDA controller in reset mode? Bail out. */
3973 {
3974 if (pcbProcessed)
3975 *pcbProcessed = 0;
3976 return VINF_SUCCESS;
3977 }
3978
3979 bool fProceed = true;
3980
3981 Log3Func(("[SD%RU8] %R[sdsts] cbToProcess=%RU32\n",
3982 pStream->u8SD, HDA_STREAM_REG(pThis, STS, pStream->u8SD), cbToProcess));
3983
3984 /* Is the stream not in a running state currently? */
3985 if (!(HDA_STREAM_REG(pThis, CTL, pStream->u8SD) & HDA_SDCTL_RUN))
3986 fProceed = false;
3987 /* Is the BCIS (Buffer Completion Interrupt Status) flag set? Then we have to wait and skip. */
3988 else if ((HDA_STREAM_REG(pThis, STS, pStream->u8SD) & HDA_SDSTS_BCIS))
3989 fProceed = false;
3990
3991 if (!fProceed)
3992 {
3993#ifdef HDA_DEBUG_DMA
3994 Log3Func(("[SD%RU8] DMA: Skip\n", pStream->u8SD));
3995#endif
3996 if (pcbProcessed)
3997 *pcbProcessed = 0;
3998 return VINF_SUCCESS;
3999 }
4000
4001 int rc = VINF_SUCCESS;
4002
4003#ifdef HDA_DEBUG_DMA
4004 Log3Func(("[SD%RU8] DMA: Start\n", pStream->u8SD));
4005#endif
4006
4007 /* Sanity checks. */
4008 Assert(pStream->u8SD <= HDA_MAX_STREAMS);
4009 Assert(pStream->u64BDLBase);
4010 Assert(pStream->u32CBL);
4011
4012 /* State sanity checks. */
4013 Assert(pStream->State.fInReset == false);
4014 Assert(HDA_STREAM_REG(pThis, LPIB, pStream->u8SD) <= pStream->u32CBL);
4015
4016 bool fSendInterrupt = false;
4017
4018 /* Only do one FIFO size at a time. */
4019 uint32_t cbLeft = RT_MIN(pStream->u16FIFOS, RT_MIN(cbToProcess, cbBuf));
4020 uint32_t cbTotal = 0;
4021 uint32_t cbChunk = 0;
4022 uint32_t cbChunkProcessed = 0;
4023
4024#ifdef HDA_DEBUG_DMA
4025 LogFunc(("[SD%RU8] DMA: cbToProcess=%RU32, cbLeft=%RU32\n", pStream->u8SD, cbToProcess, cbLeft));
4026#endif
4027
4028 /* Get the maximum number of BDL entries. */
4029 uint16_t cBDLE = pStream->u16LVI + 1;
4030
4031 while ( cbLeft
4032 && cBDLE--)
4033 {
4034 cbChunk = hdaStreamGetTransferSize(pThis, pStream, cbLeft);
4035 cbChunkProcessed = 0;
4036
4037 PHDABDLE pBDLE = &pStream->State.BDLE;
4038
4039 if (cbChunk)
4040 {
4041 if (hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_OUT) /* Output (SDO). */
4042 {
4043 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns),
4044 pBDLE->Desc.u64BufAdr + pBDLE->State.u32BufOff,
4045 (uint8_t *)pvBuf + cbTotal, cbChunk);
4046 }
4047 else /* Input (SDI). */
4048 {
4049 PDMDevHlpPhysWrite(pThis->CTX_SUFF(pDevIns),
4050 pBDLE->Desc.u64BufAdr + pBDLE->State.u32BufOff,
4051 (uint8_t *)pvBuf + cbTotal, cbChunk);
4052 }
4053
4054#ifdef HDA_DEBUG_DUMP_PCM_DATA
4055 RTFILE fh;
4056 RTFileOpen(&fh,
4057 hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_OUT
4058 ? HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaDMARead.pcm" : HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaDMAWrite.pcm",
4059 RTFILE_O_OPEN_CREATE | RTFILE_O_APPEND | RTFILE_O_WRITE | RTFILE_O_DENY_NONE);
4060 RTFileWrite(fh, (uint8_t *)pvBuf + cbTotal, cbChunk, NULL);
4061 RTFileClose(fh);
4062#endif
4063 }
4064
4065 cbChunkProcessed = cbChunk;
4066
4067 hdaBDLEUpdate(pBDLE, cbChunkProcessed, cbChunkProcessed);
4068
4069 LogFunc(("[SD%RU8] DMA: Entry %RU32 Pos %RU32/%RU32 Chunk %RU32\n",
4070 pStream->u8SD, pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->Desc.u32BufSize, cbChunk));
4071
4072 Assert(cbLeft >= cbChunkProcessed);
4073 cbLeft -= cbChunkProcessed;
4074 cbTotal += cbChunkProcessed;
4075 Assert(cbTotal <= cbToProcess);
4076
4077 hdaStreamTransferUpdate(pThis, pStream, cbChunkProcessed);
4078
4079#ifdef HDA_DEBUG_DMA
4080 LogFunc(("[SD%RU8] DMA: LPIB %RU32 Pos %RU32 Left %RU32\n",
4081 pStream->u8SD, HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), cbTotal, cbLeft));
4082#endif
4083 bool fNeedsInterrupt = false;
4084 bool fBDLEIsComplete = hdaBDLEIsComplete(pBDLE, &fNeedsInterrupt);
4085
4086 if (fNeedsInterrupt)
4087 fSendInterrupt = true;
4088
4089 if (fBDLEIsComplete)
4090 {
4091 /* Do we need to fetch the next Buffer Descriptor Entry (BDLE)? */
4092 if (hdaStreamNeedsNextBDLE(pThis, pStream))
4093 {
4094 bool fWrapAround;
4095 rc = hdaStreamGetNextBDLE(pThis, pStream, &fWrapAround);
4096 if ( RT_SUCCESS(rc)
4097 && fWrapAround)
4098 {
4099 hdaStreamUpdateLPIB(pThis, pStream, 0);
4100 }
4101 }
4102 }
4103
4104 if (RT_FAILURE(rc))
4105 break;
4106 }
4107
4108 Log3Func(("[SD%RU8]: cbLeft=%RU32, rc=%Rrc\n", pStream->u8SD, cbLeft, rc));
4109
4110 if (fSendInterrupt)
4111 {
4112#ifdef HDA_DEBUG_DMA
4113 Log3Func(("[SD%RU8] DMA: Interrupt\n", pStream->u8SD));
4114#endif
4115 /**
4116 * Set the BCIS (Buffer Completion Interrupt Status) flag as the
4117 * last byte of data for the current descriptor has been fetched
4118 * from memory and put into the DMA FIFO.
4119 *
4120 * Speech synthesis works fine on Mac Guest if this bit isn't set
4121 * but in general sound quality gets worse.
4122 *
4123 * This must be set in *any* case.
4124 */
4125 HDA_STREAM_REG(pThis, STS, pStream->u8SD) |= HDA_SDSTS_BCIS;
4126 Log3Func(("[SD%RU8]: BCIS set\n", pStream->u8SD));
4127
4128 hdaProcessInterrupt(pThis);
4129 }
4130
4131 if (RT_SUCCESS(rc))
4132 {
4133 if (pcbProcessed)
4134 *pcbProcessed = cbTotal;
4135 }
4136
4137#ifdef HDA_DEBUG_DMA
4138 Log3Func(("[SD%RU8] DMA: End\n", pStream->u8SD));
4139#endif
4140
4141 return rc;
4142}
4143
4144/**
4145 * Writes audio data from a mixer sink into an HDA stream's DMA buffer.
4146 *
4147 * @returns IPRT status code.
4148 * @param pThis HDA state.
4149 * @param pStream HDA stream to write to.
4150 * @param cbToWrite Number of bytes to write.
4151 * @param pcbWritten Number of bytes written. Optional.
4152 */
4153static int hdaStreamWrite(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToWrite, uint32_t *pcbWritten)
4154{
4155 RT_NOREF(pThis);
4156 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
4157 AssertReturn(cbToWrite, VERR_INVALID_PARAMETER);
4158 /* pcbWritten is optional. */
4159
4160 PHDAMIXERSINK pSink = pStream->pMixSink;
4161 if (!pSink)
4162 {
4163 AssertMsgFailed(("[SD%RU8]: Can't write to a stream with no sink attached\n", pStream->u8SD));
4164
4165 if (pcbWritten)
4166 *pcbWritten = 0;
4167 return VINF_SUCCESS;
4168 }
4169
4170 PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
4171 AssertPtr(pCircBuf);
4172
4173 void *pvDst;
4174 size_t cbDst;
4175
4176 uint32_t cbWritten = 0;
4177
4178 RTCircBufAcquireWriteBlock(pCircBuf, cbToWrite, &pvDst, &cbDst);
4179
4180 if (cbDst)
4181 {
4182 int rc2 = AudioMixerSinkRead(pSink->pMixSink, AUDMIXOP_COPY, pvDst, (uint32_t)cbDst, &cbWritten);
4183 AssertRC(rc2);
4184
4185 Assert(cbDst >= cbWritten);
4186 Log2Func(("[SD%RU8]: %zu/%zu bytes written\n", pStream->u8SD, cbWritten, cbDst));
4187
4188#ifdef HDA_DEBUG_DUMP_PCM_DATA
4189 RTFILE fh;
4190 RTFileOpen(&fh, HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaStreamWrite.pcm",
4191 RTFILE_O_OPEN_CREATE | RTFILE_O_APPEND | RTFILE_O_WRITE | RTFILE_O_DENY_NONE);
4192 RTFileWrite(fh, pvDst, cbWritten, NULL);
4193 RTFileClose(fh);
4194#endif
4195 }
4196
4197 RTCircBufReleaseWriteBlock(pCircBuf, cbWritten);
4198
4199 if (pcbWritten)
4200 *pcbWritten = cbWritten;
4201
4202 return VINF_SUCCESS;
4203}
4204
4205/**
4206 * Reads audio data from an HDA stream's DMA buffer and writes into a specified mixer sink.
4207 *
4208 * @returns IPRT status code.
4209 * @param pThis HDA state.
4210 * @param pStream HDA stream to read audio data from.
4211 * @param cbToRead Number of bytes to read.
4212 * @param pcbRead Number of bytes read. Optional.
4213 */
4214static int hdaStreamRead(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToRead, uint32_t *pcbRead)
4215{
4216 RT_NOREF(pThis);
4217 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
4218 AssertReturn(cbToRead, VERR_INVALID_PARAMETER);
4219 /* pcbWritten is optional. */
4220
4221 PHDAMIXERSINK pSink = pStream->pMixSink;
4222 if (!pSink)
4223 {
4224 AssertMsgFailed(("[SD%RU8]: Can't read from a stream with no sink attached\n", pStream->u8SD));
4225
4226 if (pcbRead)
4227 *pcbRead = 0;
4228 return VINF_SUCCESS;
4229 }
4230
4231 PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
4232 AssertPtr(pCircBuf);
4233
4234 void *pvSrc;
4235 size_t cbSrc;
4236
4237 uint32_t cbRead = 0;
4238
4239 RTCircBufAcquireReadBlock(pCircBuf, cbToRead, &pvSrc, &cbSrc);
4240
4241 if (cbSrc)
4242 {
4243 Log2Func(("[SD%RU8]: Reading %zu bytes ...\n", pStream->u8SD, cbSrc));
4244
4245#ifdef HDA_DEBUG_DUMP_PCM_DATA
4246 RTFILE fh;
4247 RTFileOpen(&fh, HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaStreamRead.pcm",
4248 RTFILE_O_OPEN_CREATE | RTFILE_O_APPEND | RTFILE_O_WRITE | RTFILE_O_DENY_NONE);
4249 RTFileWrite(fh, pvSrc, cbSrc, NULL);
4250 RTFileClose(fh);
4251#endif
4252 int rc2 = AudioMixerSinkWrite(pSink->pMixSink, AUDMIXOP_COPY, pvSrc, (uint32_t)cbSrc, &cbRead);
4253 AssertRC(rc2);
4254
4255 Assert(cbSrc >= cbRead);
4256 Log2Func(("[SD%RU8]: %zu/%zu bytes read\n", pStream->u8SD, cbRead, cbSrc));
4257 }
4258
4259 RTCircBufReleaseReadBlock(pCircBuf, cbRead);
4260
4261 if (pcbRead)
4262 *pcbRead = cbRead;
4263
4264 return VINF_SUCCESS;
4265}
4266
4267#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
4268/**
4269 * Asynchronous I/O thread for a HDA stream.
4270 * This will do the heavy lifting work for us as soon as it's getting notified by another thread.
4271 *
4272 * @returns IPRT status code.
4273 * @param hThreadSelf Thread handle.
4274 * @param pvUser User argument. Must be of type PHDASTREAMTHREADCTX.
4275 */
4276static DECLCALLBACK(int) hdaStreamAsyncIOThread(RTTHREAD hThreadSelf, void *pvUser)
4277{
4278 PHDASTREAMTHREADCTX pCtx = (PHDASTREAMTHREADCTX)pvUser;
4279 AssertPtr(pCtx);
4280
4281 PHDASTATE pThis = pCtx->pThis;
4282 AssertPtr(pThis);
4283
4284 PHDASTREAM pStream = pCtx->pStream;
4285 AssertPtr(pStream);
4286
4287 PHDASTREAMSTATEAIO pAIO = &pCtx->pStream->State.AIO;
4288
4289 PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
4290 AssertPtr(pCircBuf);
4291
4292 ASMAtomicXchgBool(&pAIO->fStarted, true);
4293
4294 RTThreadUserSignal(hThreadSelf);
4295
4296 LogFunc(("[SD%RU8]: Started\n", pStream->u8SD));
4297
4298 for (;;)
4299 {
4300 int rc2 = RTSemEventWait(pAIO->Event, RT_INDEFINITE_WAIT);
4301 if (RT_FAILURE(rc2))
4302 break;
4303
4304 if (ASMAtomicReadBool(&pAIO->fShutdown))
4305 break;
4306
4307 PHDAMIXERSINK pSink = pStream->pMixSink;
4308
4309 rc2 = RTCritSectEnter(&pAIO->CritSect);
4310 if (RT_SUCCESS(rc2))
4311 {
4312 if (!pAIO->fEnabled)
4313 {
4314 RTCritSectLeave(&pAIO->CritSect);
4315 continue;
4316 }
4317
4318 uint32_t cbToProcess;
4319 uint32_t cbProcessed = 0;
4320
4321 if (hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_OUT) /* Output (SDO). */
4322 {
4323 cbToProcess = (uint32_t)RTCircBufUsed(pCircBuf);
4324 if (cbToProcess)
4325 rc2 = hdaStreamRead(pThis, pStream, cbToProcess, &cbProcessed);
4326 }
4327 else /* Input (SDI). */
4328 {
4329 cbToProcess = (uint32_t)RTCircBufFree(pCircBuf);
4330 if (cbToProcess)
4331 rc2 = hdaStreamWrite(pThis, pStream, cbToProcess, &cbProcessed);
4332 }
4333
4334 if ( pSink
4335 && RT_SUCCESS(rc2))
4336 {
4337 rc2 = AudioMixerSinkUpdate(pSink->pMixSink);
4338 }
4339
4340 int rc3 = RTCritSectLeave(&pAIO->CritSect);
4341 AssertRC(rc3);
4342 }
4343
4344 AssertRC(rc2);
4345 }
4346
4347 LogFunc(("[SD%RU8]: Ended\n", pStream->u8SD));
4348
4349 ASMAtomicXchgBool(&pAIO->fStarted, false);
4350
4351 return VINF_SUCCESS;
4352}
4353
4354/**
4355 * Creates the async I/O thread for a specific HDA audio stream.
4356 *
4357 * @returns IPRT status code.
4358 * @param pThis HDA state.
4359 * @param pStream HDA audio stream to create the async I/O thread for.
4360 */
4361static int hdaStreamAsyncIOCreate(PHDASTATE pThis, PHDASTREAM pStream)
4362{
4363 PHDASTREAMSTATEAIO pAIO = &pStream->State.AIO;
4364
4365 int rc;
4366
4367 if (!ASMAtomicReadBool(&pAIO->fStarted))
4368 {
4369 pAIO->fShutdown = false;
4370
4371 rc = RTSemEventCreate(&pAIO->Event);
4372 if (RT_SUCCESS(rc))
4373 {
4374 rc = RTCritSectInit(&pAIO->CritSect);
4375 if (RT_SUCCESS(rc))
4376 {
4377 HDASTREAMTHREADCTX Ctx = { pThis, pStream };
4378
4379 char szThreadName[64];
4380 RTStrPrintf2(szThreadName, sizeof(szThreadName), "hdaAIO%RU8", pStream->u8SD);
4381
4382 rc = RTThreadCreate(&pAIO->Thread, hdaStreamAsyncIOThread, &Ctx,
4383 0, RTTHREADTYPE_IO, RTTHREADFLAGS_WAITABLE, szThreadName);
4384 if (RT_SUCCESS(rc))
4385 rc = RTThreadUserWait(pAIO->Thread, 10 * 1000 /* 10s timeout */);
4386 }
4387 }
4388 }
4389 else
4390 rc = VINF_SUCCESS;
4391
4392 LogFunc(("[SD%RU8]: Returning %Rrc\n", pStream->u8SD, rc));
4393 return rc;
4394}
4395
4396/**
4397 * Destroys the async I/O thread of a specific HDA audio stream.
4398 *
4399 * @returns IPRT status code.
4400 * @param pThis HDA state.
4401 * @param pStream HDA audio stream to destroy the async I/O thread for.
4402 */
4403static int hdaStreamAsyncIODestroy(PHDASTATE pThis, PHDASTREAM pStream)
4404{
4405 PHDASTREAMSTATEAIO pAIO = &pStream->State.AIO;
4406
4407 if (!ASMAtomicReadBool(&pAIO->fStarted))
4408 return VINF_SUCCESS;
4409
4410 ASMAtomicWriteBool(&pAIO->fShutdown, true);
4411
4412 int rc = hdaStreamAsyncIONotify(pThis, pStream);
4413 AssertRC(rc);
4414
4415 int rcThread;
4416 rc = RTThreadWait(pAIO->Thread, 30 * 1000 /* 30s timeout */, &rcThread);
4417 LogFunc(("Async I/O thread ended with %Rrc (%Rrc)\n", rc, rcThread));
4418
4419 if (RT_SUCCESS(rc))
4420 {
4421 rc = RTCritSectDelete(&pAIO->CritSect);
4422 AssertRC(rc);
4423
4424 rc = RTSemEventDestroy(pAIO->Event);
4425 AssertRC(rc);
4426
4427 pAIO->fStarted = false;
4428 pAIO->fShutdown = false;
4429 pAIO->fEnabled = false;
4430 }
4431
4432 LogFunc(("[SD%RU8]: Returning %Rrc\n", pStream->u8SD, rc));
4433 return rc;
4434}
4435
4436/**
4437 * Lets the stream's async I/O thread know that there is some data to process.
4438 *
4439 * @returns IPRT status code.
4440 * @param pThis HDA state.
4441 * @param pStream HDA stream to notify async I/O thread for.
4442 */
4443static int hdaStreamAsyncIONotify(PHDASTATE pThis, PHDASTREAM pStream)
4444{
4445 RT_NOREF(pThis);
4446 return RTSemEventSignal(pStream->State.AIO.Event);
4447}
4448
4449/**
4450 * Locks the async I/O thread of a specific HDA audio stream.
4451 *
4452 * @param pStream HDA stream to lock async I/O thread for.
4453 */
4454static void hdaStreamAsyncIOLock(PHDASTREAM pStream)
4455{
4456 PHDASTREAMSTATEAIO pAIO = &pStream->State.AIO;
4457
4458 if (!ASMAtomicReadBool(&pAIO->fStarted))
4459 return;
4460
4461 int rc2 = RTCritSectEnter(&pAIO->CritSect);
4462 AssertRC(rc2);
4463}
4464
4465/**
4466 * Unlocks the async I/O thread of a specific HDA audio stream.
4467 *
4468 * @param pStream HDA stream to unlock async I/O thread for.
4469 */
4470static void hdaStreamAsyncIOUnlock(PHDASTREAM pStream)
4471{
4472 PHDASTREAMSTATEAIO pAIO = &pStream->State.AIO;
4473
4474 if (!ASMAtomicReadBool(&pAIO->fStarted))
4475 return;
4476
4477 int rc2 = RTCritSectLeave(&pAIO->CritSect);
4478 AssertRC(rc2);
4479}
4480
4481/**
4482 * Enables (resumes) or disables (pauses) the async I/O thread.
4483 *
4484 * @param pStream HDA stream to enable/disable async I/O thread for.
4485 * @param fEnable Whether to enable or disable the I/O thread.
4486 *
4487 * @remarks Does not do locking.
4488 */
4489static void hdaStreamAsyncIOEnable(PHDASTREAM pStream, bool fEnable)
4490{
4491 PHDASTREAMSTATEAIO pAIO = &pStream->State.AIO;
4492 ASMAtomicXchgBool(&pAIO->fEnabled, fEnable);
4493}
4494#endif /* VBOX_WITH_AUDIO_HDA_ASYNC_IO */
4495
4496/**
4497 * Updates a HDA stream according to its usage (input / output).
4498 *
4499 * For an SDO (output) stream this means reading DMA data from the device to
4500 * the connected audio sink(s).
4501 *
4502 * For an SDI (input) stream this is reading audio data from the connected
4503 * audio sink(s) and writing it as DMA data to the device.
4504 *
4505 * @returns IPRT status code.
4506 * @param pThis HDA state.
4507 * @param pStream HDA stream to update.
4508 */
4509static int hdaStreamUpdate(PHDASTATE pThis, PHDASTREAM pStream)
4510{
4511 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
4512 AssertPtrReturn(pStream, VERR_INVALID_POINTER);
4513
4514 hdaStreamLock(pStream);
4515
4516 PHDAMIXERSINK pSink = pStream->pMixSink;
4517 AssertPtr(pSink);
4518
4519 PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
4520 AssertPtr(pCircBuf);
4521
4522 if (!AudioMixerSinkIsActive(pSink->pMixSink))
4523 {
4524 hdaStreamUnlock(pStream);
4525 return VINF_SUCCESS;
4526 }
4527
4528 Log2Func(("[SD%RU8]\n", pStream->u8SD));
4529
4530 bool fDone = false;
4531 uint8_t cTransfers = 0;
4532
4533 while (!fDone)
4534 {
4535 int rc2;
4536 uint32_t cbDMA = 0;
4537
4538 if (hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_OUT) /* Output (SDO). */
4539 {
4540 STAM_PROFILE_START(&pThis->StatOut, a);
4541
4542 /*
4543 * Read from DMA.
4544 */
4545
4546 uint8_t abFIFO[HDA_FIFO_MAX + 1];
4547 size_t offFIFO = 0;
4548
4549 /* Do one DMA transfer with FIFOS size at a time. */
4550 rc2 = hdaStreamDoDMA(pThis, pStream, abFIFO, sizeof(abFIFO), (uint32_t)pStream->u16FIFOS /* cbToProcess */, &cbDMA);
4551 AssertRC(rc2);
4552
4553 uint32_t cbDMALeft = cbDMA;
4554
4555 while ( cbDMALeft
4556 && RTCircBufFree(pCircBuf))
4557 {
4558 void *pvDst;
4559 size_t cbDst;
4560
4561 RTCircBufAcquireWriteBlock(pCircBuf, cbDMALeft, &pvDst, &cbDst);
4562
4563 if (cbDst)
4564 {
4565 memcpy(pvDst, abFIFO + offFIFO, cbDst);
4566
4567 offFIFO += cbDst;
4568 Assert(offFIFO <= sizeof(abFIFO));
4569 }
4570
4571 RTCircBufReleaseWriteBlock(pCircBuf, cbDst);
4572
4573 Assert(cbDst <= cbDMALeft);
4574 cbDMALeft -= (uint32_t)cbDst;
4575 }
4576
4577 AssertMsg(cbDMALeft == 0, ("%RU32 bytes of DMA data left, CircBuf=%zu/%zu\n",
4578 cbDMALeft, RTCircBufUsed(pCircBuf), RTCircBufSize(pCircBuf)));
4579
4580 /*
4581 * Process backends.
4582 */
4583
4584 uint32_t cbUsed = (uint32_t)RTCircBufUsed(pCircBuf);
4585 if (cbUsed)
4586 {
4587#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
4588 /* Let the asynchronous thread know that there is some new data to process. */
4589 hdaStreamAsyncIONotify(pThis, pStream);
4590#else
4591 /* Read audio data from the HDA stream and write to the backends. */
4592 rc2 = hdaStreamRead(pThis, pStream, cbUsed, NULL /* pcbRead */);
4593 AssertRC(rc2);
4594#endif
4595 }
4596
4597 /* All DMA transfers done for now? */
4598 if ( !cbDMA
4599#ifndef VBOX_WITH_AUDIO_HDA_ASYNC_IO
4600 /* All data read *and* processed for now? */
4601 && RTCircBufUsed(pCircBuf) == 0
4602#endif
4603 )
4604 {
4605 fDone = true;
4606 }
4607
4608#ifndef VBOX_WITH_AUDIO_HDA_ASYNC_IO
4609 rc2 = AudioMixerSinkUpdate(pSink->pMixSink);
4610 AssertRC(rc2);
4611#endif
4612 STAM_PROFILE_STOP(&pThis->StatOut, a);
4613 }
4614 else if (hdaGetDirFromSD(pStream->u8SD) == PDMAUDIODIR_IN) /* Input (SDI). */
4615 {
4616 STAM_PROFILE_START(&pThis->StatIn, a);
4617
4618 /*
4619 * Process backends.
4620 */
4621
4622#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
4623 /* Let the asynchronous thread know that there is some new data to process. */
4624 hdaStreamAsyncIONotify(pThis, pStream);
4625#else
4626 rc2 = AudioMixerSinkUpdate(pSink->pMixSink);
4627 AssertRC(rc2);
4628
4629 /* Write read data from the backend to the HDA stream. */
4630 rc2 = hdaStreamWrite(pThis, pStream, pStream->u16FIFOS, NULL /* pcbWritten */);
4631 AssertRC(rc2);
4632#endif
4633 /*
4634 * Write to DMA.
4635 */
4636
4637 void *pvSrc;
4638 size_t cbSrc;
4639
4640 RTCircBufAcquireReadBlock(pCircBuf, pStream->u16FIFOS, &pvSrc, &cbSrc);
4641
4642 if (cbSrc)
4643 {
4644 /* Do one DMA transfer with FIFOS size at a time. */
4645 rc2 = hdaStreamDoDMA(pThis, pStream, pvSrc, (uint32_t)cbSrc, (uint32_t)cbSrc /* cbToProcess */, &cbDMA);
4646 AssertRC(rc2);
4647 }
4648
4649 RTCircBufReleaseReadBlock(pCircBuf, cbDMA);
4650
4651 /* All DMA transfers done for now? */
4652 if (!cbDMA)
4653 fDone = true;
4654
4655 STAM_PROFILE_STOP(&pThis->StatIn, a);
4656 }
4657 else
4658 AssertFailed();
4659
4660 if (++cTransfers == UINT8_MAX) /* Failsafe counter. */
4661 fDone = true;
4662
4663 } /* while !fDone */
4664
4665#ifdef VBOX_STRICT
4666 AssertMsg(cTransfers < UINT8_MAX, ("HDA: Update for SD#%RU8 ran for too long\n", pStream->u8SD));
4667#endif
4668
4669 Log2Func(("[SD%RU8] End\n", pStream->u8SD));
4670
4671 hdaStreamUnlock(pStream);
4672
4673 return VINF_SUCCESS;
4674}
4675#endif /* IN_RING3 */
4676
4677/* MMIO callbacks */
4678
4679/**
4680 * @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
4681 *
4682 * @note During implementation, we discovered so-called "forgotten" or "hole"
4683 * registers whose description is not listed in the RPM, datasheet, or
4684 * spec.
4685 */
4686PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void *pv, unsigned cb)
4687{
4688 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4689 int rc;
4690 RT_NOREF_PV(pvUser);
4691
4692 /*
4693 * Look up and log.
4694 */
4695 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
4696 int idxRegDsc = hdaRegLookup(offReg); /* Register descriptor index. */
4697#ifdef LOG_ENABLED
4698 unsigned const cbLog = cb;
4699 uint32_t offRegLog = offReg;
4700#endif
4701
4702 Log3Func(("offReg=%#x cb=%#x\n", offReg, cb));
4703 Assert(cb == 4); Assert((offReg & 3) == 0);
4704
4705 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
4706 LogFunc(("Access to registers except GCTL is blocked while reset\n"));
4707
4708 if (idxRegDsc == -1)
4709 LogRel(("HDA: Invalid read access @0x%x (bytes=%u)\n", offReg, cb));
4710
4711 if (idxRegDsc != -1)
4712 {
4713 /* ASSUMES gapless DWORD at end of map. */
4714 if (g_aHdaRegMap[idxRegDsc].size == 4)
4715 {
4716 /*
4717 * Straight forward DWORD access.
4718 */
4719 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
4720 Log3Func(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, *(uint32_t *)pv, rc));
4721 }
4722 else
4723 {
4724 /*
4725 * Multi register read (unless there are trailing gaps).
4726 * ASSUMES that only DWORD reads have sideeffects.
4727 */
4728 uint32_t u32Value = 0;
4729 unsigned cbLeft = 4;
4730 do
4731 {
4732 uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
4733 uint32_t u32Tmp = 0;
4734
4735 rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
4736 Log3Func(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
4737 if (rc != VINF_SUCCESS)
4738 break;
4739 u32Value |= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
4740
4741 cbLeft -= cbReg;
4742 offReg += cbReg;
4743 idxRegDsc++;
4744 } while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
4745
4746 if (rc == VINF_SUCCESS)
4747 *(uint32_t *)pv = u32Value;
4748 else
4749 Assert(!IOM_SUCCESS(rc));
4750 }
4751 }
4752 else
4753 {
4754 rc = VINF_IOM_MMIO_UNUSED_FF;
4755 Log3Func(("\tHole at %x is accessed for read\n", offReg));
4756 }
4757
4758 /*
4759 * Log the outcome.
4760 */
4761#ifdef LOG_ENABLED
4762 if (cbLog == 4)
4763 Log3Func(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, *(uint32_t *)pv, rc));
4764 else if (cbLog == 2)
4765 Log3Func(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, *(uint16_t *)pv, rc));
4766 else if (cbLog == 1)
4767 Log3Func(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, *(uint8_t *)pv, rc));
4768#endif
4769 return rc;
4770}
4771
4772
4773DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
4774{
4775 if (pThis->fInReset && idxRegDsc != HDA_REG_GCTL)
4776 {
4777 Log(("hdaWriteReg: Warning: Access to %s is blocked while controller is in reset mode\n", g_aHdaRegMap[idxRegDsc].abbrev));
4778 LogRel2(("HDA: Warning: Access to register %s is blocked while controller is in reset mode\n",
4779 g_aHdaRegMap[idxRegDsc].abbrev));
4780 return VINF_SUCCESS;
4781 }
4782
4783 /*
4784 * Handle RD (register description) flags.
4785 */
4786
4787 /* For SDI / SDO: Check if writes to those registers are allowed while SDCTL's RUN bit is set. */
4788 if (idxRegDsc >= HDA_NUM_GENERAL_REGS)
4789 {
4790 const uint32_t uSDCTL = HDA_STREAM_REG(pThis, CTL, HDA_SD_NUM_FROM_REG(pThis, CTL, idxRegDsc));
4791
4792 /*
4793 * Some OSes (like Win 10 AU) violate the spec by writing stuff to registers which are not supposed to be be touched
4794 * while SDCTL's RUN bit is set. So just ignore those values.
4795 */
4796
4797 /* Is the RUN bit currently set? */
4798 if ( RT_BOOL(uSDCTL & HDA_SDCTL_RUN)
4799 /* Are writes to the register denied if RUN bit is set? */
4800 && !(g_aHdaRegMap[idxRegDsc].fFlags & HDA_RD_FLAG_SD_WRITE_RUN))
4801 {
4802 Log(("hdaWriteReg: Warning: Access to %s is blocked! %R[sdctl]\n", g_aHdaRegMap[idxRegDsc].abbrev, uSDCTL));
4803 LogRel2(("HDA: Warning: Access to register %s is blocked while the stream's RUN bit is set\n",
4804 g_aHdaRegMap[idxRegDsc].abbrev));
4805 return VINF_SUCCESS;
4806 }
4807 }
4808
4809#ifdef LOG_ENABLED
4810 uint32_t const idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4811 uint32_t const u32OldValue = pThis->au32Regs[idxRegMem];
4812#endif
4813 int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
4814 Log3Func(("Written value %#x to %s[%d byte]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
4815 g_aHdaRegMap[idxRegDsc].size, u32OldValue, pThis->au32Regs[idxRegMem], pszLog));
4816 RT_NOREF(pszLog);
4817 return rc;
4818}
4819
4820
4821/**
4822 * @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
4823 */
4824PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS GCPhysAddr, void const *pv, unsigned cb)
4825{
4826 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4827 int rc;
4828 RT_NOREF_PV(pvUser);
4829
4830 /*
4831 * The behavior of accesses that aren't aligned on natural boundraries is
4832 * undefined. Just reject them outright.
4833 */
4834 /** @todo IOM could check this, it could also split the 8 byte accesses for us. */
4835 Assert(cb == 1 || cb == 2 || cb == 4 || cb == 8);
4836 if (GCPhysAddr & (cb - 1))
4837 return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
4838
4839 /*
4840 * Look up and log the access.
4841 */
4842 uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
4843 int idxRegDsc = hdaRegLookup(offReg);
4844 uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
4845 uint64_t u64Value;
4846 if (cb == 4) u64Value = *(uint32_t const *)pv;
4847 else if (cb == 2) u64Value = *(uint16_t const *)pv;
4848 else if (cb == 1) u64Value = *(uint8_t const *)pv;
4849 else if (cb == 8) u64Value = *(uint64_t const *)pv;
4850 else
4851 {
4852 u64Value = 0; /* shut up gcc. */
4853 AssertReleaseMsgFailed(("%u\n", cb));
4854 }
4855
4856#ifdef LOG_ENABLED
4857 uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
4858 if (idxRegDsc == -1)
4859 Log3Func(("@%#05x u32=%#010x cb=%d\n", offReg, *(uint32_t const *)pv, cb));
4860 else if (cb == 4)
4861 Log3Func(("@%#05x u32=%#010x %s\n", offReg, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4862 else if (cb == 2)
4863 Log3Func(("@%#05x u16=%#06x (%#010x) %s\n", offReg, *(uint16_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4864 else if (cb == 1)
4865 Log3Func(("@%#05x u8=%#04x (%#010x) %s\n", offReg, *(uint8_t *)pv, *(uint32_t *)pv, g_aHdaRegMap[idxRegDsc].abbrev));
4866
4867 if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
4868 Log3Func(("\tsize=%RU32 != cb=%u!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
4869#endif
4870
4871 /*
4872 * Try for a direct hit first.
4873 */
4874 if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
4875 {
4876 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
4877 Log3Func(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
4878 }
4879 /*
4880 * Partial or multiple register access, loop thru the requested memory.
4881 */
4882 else
4883 {
4884 /*
4885 * If it's an access beyond the start of the register, shift the input
4886 * value and fill in missing bits. Natural alignment rules means we
4887 * will only see 1 or 2 byte accesses of this kind, so no risk of
4888 * shifting out input values.
4889 */
4890 if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(offReg)) != -1)
4891 {
4892 uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
4893 offReg -= cbBefore;
4894 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4895 u64Value <<= cbBefore * 8;
4896 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
4897 Log3Func(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
4898 cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
4899 }
4900
4901 /* Loop thru the write area, it may cover multiple registers. */
4902 rc = VINF_SUCCESS;
4903 for (;;)
4904 {
4905 uint32_t cbReg;
4906 if (idxRegDsc != -1)
4907 {
4908 idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
4909 cbReg = g_aHdaRegMap[idxRegDsc].size;
4910 if (cb < cbReg)
4911 {
4912 u64Value |= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
4913 Log3Func(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
4914 g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
4915 }
4916#ifdef LOG_ENABLED
4917 uint32_t uLogOldVal = pThis->au32Regs[idxRegMem];
4918#endif
4919 rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
4920 Log3Func(("\t%#x -> %#x\n", uLogOldVal, pThis->au32Regs[idxRegMem]));
4921 }
4922 else
4923 {
4924 LogRel(("HDA: Invalid write access @0x%x\n", offReg));
4925 cbReg = 1;
4926 }
4927 if (rc != VINF_SUCCESS)
4928 break;
4929 if (cbReg >= cb)
4930 break;
4931
4932 /* Advance. */
4933 offReg += cbReg;
4934 cb -= cbReg;
4935 u64Value >>= cbReg * 8;
4936 if (idxRegDsc == -1)
4937 idxRegDsc = hdaRegLookup(offReg);
4938 else
4939 {
4940 idxRegDsc++;
4941 if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
4942 || g_aHdaRegMap[idxRegDsc].offset != offReg)
4943 {
4944 idxRegDsc = -1;
4945 }
4946 }
4947 }
4948 }
4949
4950 return rc;
4951}
4952
4953
4954/* PCI callback. */
4955
4956#ifdef IN_RING3
4957/**
4958 * @callback_method_impl{FNPCIIOREGIONMAP}
4959 */
4960static DECLCALLBACK(int) hdaPciIoRegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
4961 RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
4962{
4963 RT_NOREF(iRegion, enmType);
4964 PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
4965
4966 /*
4967 * 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
4968 *
4969 * Let IOM talk DWORDs when reading, saves a lot of complications. On
4970 * writing though, we have to do it all ourselves because of sideeffects.
4971 */
4972 Assert(enmType == PCI_ADDRESS_SPACE_MEM);
4973 int rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /*pvUser*/,
4974 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_PASSTHRU,
4975 hdaMMIOWrite, hdaMMIORead, "HDA");
4976 if (RT_FAILURE(rc))
4977 return rc;
4978
4979 if (pThis->fR0Enabled)
4980 {
4981 rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /*pvUser*/,
4982 "hdaMMIOWrite", "hdaMMIORead");
4983 if (RT_FAILURE(rc))
4984 return rc;
4985 }
4986
4987 if (pThis->fRCEnabled)
4988 {
4989 rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /*pvUser*/,
4990 "hdaMMIOWrite", "hdaMMIORead");
4991 if (RT_FAILURE(rc))
4992 return rc;
4993 }
4994
4995 pThis->MMIOBaseAddr = GCPhysAddress;
4996 return VINF_SUCCESS;
4997}
4998
4999
5000/* Saved state callbacks. */
5001
5002static int hdaSaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStrm)
5003{
5004 RT_NOREF(pDevIns);
5005#ifdef DEBUG
5006 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5007#endif
5008 LogFlowFunc(("[SD%RU8]\n", pStrm->u8SD));
5009
5010 /* Save stream ID. */
5011 int rc = SSMR3PutU8(pSSM, pStrm->u8SD);
5012 AssertRCReturn(rc, rc);
5013 Assert(pStrm->u8SD <= HDA_MAX_STREAMS);
5014
5015 rc = SSMR3PutStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE), 0 /*fFlags*/, g_aSSMStreamStateFields6, NULL);
5016 AssertRCReturn(rc, rc);
5017
5018#ifdef DEBUG /* Sanity checks. */
5019 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStrm->u8SD),
5020 HDA_STREAM_REG(pThis, BDPU, pStrm->u8SD));
5021 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStrm->u8SD);
5022 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStrm->u8SD);
5023
5024 hdaBDLEDumpAll(pThis, u64BaseDMA, u16LVI + 1);
5025
5026 Assert(u64BaseDMA == pStrm->u64BDLBase);
5027 Assert(u16LVI == pStrm->u16LVI);
5028 Assert(u32CBL == pStrm->u32CBL);
5029#endif
5030
5031 rc = SSMR3PutStructEx(pSSM, &pStrm->State.BDLE.Desc, sizeof(HDABDLEDESC),
5032 0 /*fFlags*/, g_aSSMBDLEDescFields6, NULL);
5033 AssertRCReturn(rc, rc);
5034
5035 rc = SSMR3PutStructEx(pSSM, &pStrm->State.BDLE.State, sizeof(HDABDLESTATE),
5036 0 /*fFlags*/, g_aSSMBDLEStateFields6, NULL);
5037 AssertRCReturn(rc, rc);
5038
5039#ifdef DEBUG /* Sanity checks. */
5040 PHDABDLE pBDLE = &pStrm->State.BDLE;
5041 if (u64BaseDMA)
5042 {
5043 Assert(pStrm->State.uCurBDLE <= u16LVI + 1);
5044
5045 HDABDLE curBDLE;
5046 rc = hdaBDLEFetch(pThis, &curBDLE, u64BaseDMA, pStrm->State.uCurBDLE);
5047 AssertRC(rc);
5048
5049 Assert(curBDLE.Desc.u32BufSize == pBDLE->Desc.u32BufSize);
5050 Assert(curBDLE.Desc.u64BufAdr == pBDLE->Desc.u64BufAdr);
5051 Assert(curBDLE.Desc.fFlags == pBDLE->Desc.fFlags);
5052 }
5053 else
5054 {
5055 Assert(pBDLE->Desc.u64BufAdr == 0);
5056 Assert(pBDLE->Desc.u32BufSize == 0);
5057 }
5058#endif
5059 return rc;
5060}
5061
5062/**
5063 * @callback_method_impl{FNSSMDEVSAVEEXEC}
5064 */
5065static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
5066{
5067 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5068
5069 /* Save Codec nodes states. */
5070 hdaCodecSaveState(pThis->pCodec, pSSM);
5071
5072 /* Save MMIO registers. */
5073 SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
5074 SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
5075
5076 /* Save number of streams. */
5077 SSMR3PutU32(pSSM, HDA_MAX_STREAMS);
5078
5079 /* Save stream states. */
5080 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5081 {
5082 int rc = hdaSaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
5083 AssertRCReturn(rc, rc);
5084 }
5085
5086 return VINF_SUCCESS;
5087}
5088
5089
5090/**
5091 * @callback_method_impl{FNSSMDEVLOADEXEC}
5092 */
5093static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
5094{
5095 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5096
5097 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
5098
5099 LogRel2(("hdaLoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
5100
5101 /*
5102 * Load Codec nodes states.
5103 */
5104 int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
5105 if (RT_FAILURE(rc))
5106 {
5107 LogRel(("HDA: Failed loading codec state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
5108 return rc;
5109 }
5110
5111 /*
5112 * Load MMIO registers.
5113 */
5114 uint32_t cRegs;
5115 switch (uVersion)
5116 {
5117 case HDA_SSM_VERSION_1:
5118 /* Starting with r71199, we would save 112 instead of 113
5119 registers due to some code cleanups. This only affected trunk
5120 builds in the 4.1 development period. */
5121 cRegs = 113;
5122 if (SSMR3HandleRevision(pSSM) >= 71199)
5123 {
5124 uint32_t uVer = SSMR3HandleVersion(pSSM);
5125 if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
5126 && VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
5127 && VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
5128 cRegs = 112;
5129 }
5130 break;
5131
5132 case HDA_SSM_VERSION_2:
5133 case HDA_SSM_VERSION_3:
5134 cRegs = 112;
5135 AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= 112);
5136 break;
5137
5138 /* Since version 4 we store the register count to stay flexible. */
5139 case HDA_SSM_VERSION_4:
5140 case HDA_SSM_VERSION_5:
5141 case HDA_SSM_VERSION:
5142 rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
5143 if (cRegs != RT_ELEMENTS(pThis->au32Regs))
5144 LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
5145 break;
5146
5147 default:
5148 LogRel(("HDA: Unsupported / too new saved state version (%RU32)\n", uVersion));
5149 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
5150 }
5151
5152 if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
5153 {
5154 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
5155 SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
5156 }
5157 else
5158 SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
5159
5160 /*
5161 * Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
5162 * *every* BDLE state, whereas it only needs to be stored
5163 * *once* for every stream. Most of the BDLE state we can
5164 * get out of the registers anyway, so just ignore those values.
5165 *
5166 * Also, only the current BDLE was saved, regardless whether
5167 * there were more than one (and there are at least two entries,
5168 * according to the spec).
5169 */
5170#define HDA_SSM_LOAD_BDLE_STATE_PRE_V5(v, x) \
5171 { \
5172 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */ \
5173 AssertRCReturn(rc, rc); \
5174 rc = SSMR3GetU64(pSSM, &x.Desc.u64BufAdr); /* u64BdleCviAddr */ \
5175 AssertRCReturn(rc, rc); \
5176 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleMaxCvi */ \
5177 AssertRCReturn(rc, rc); \
5178 rc = SSMR3GetU32(pSSM, &x.State.u32BDLIndex); /* u32BdleCvi */ \
5179 AssertRCReturn(rc, rc); \
5180 rc = SSMR3GetU32(pSSM, &x.Desc.u32BufSize); /* u32BdleCviLen */ \
5181 AssertRCReturn(rc, rc); \
5182 rc = SSMR3GetU32(pSSM, &x.State.u32BufOff); /* u32BdleCviPos */ \
5183 AssertRCReturn(rc, rc); \
5184 bool fIOC; \
5185 rc = SSMR3GetBool(pSSM, &fIOC); /* fBdleCviIoc */ \
5186 AssertRCReturn(rc, rc); \
5187 x.Desc.fFlags = fIOC ? HDA_BDLE_FLAG_IOC : 0; \
5188 rc = SSMR3GetU32(pSSM, &x.State.cbBelowFIFOW); /* cbUnderFifoW */ \
5189 AssertRCReturn(rc, rc); \
5190 rc = SSMR3Skip(pSSM, sizeof(uint8_t) * 256); /* FIFO */ \
5191 AssertRCReturn(rc, rc); \
5192 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */ \
5193 AssertRCReturn(rc, rc); \
5194 } \
5195
5196 /*
5197 * Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
5198 */
5199 switch (uVersion)
5200 {
5201 case HDA_SSM_VERSION_1:
5202 case HDA_SSM_VERSION_2:
5203 case HDA_SSM_VERSION_3:
5204 case HDA_SSM_VERSION_4:
5205 {
5206 /* Only load the internal states.
5207 * The rest will be initialized from the saved registers later. */
5208
5209 /* Note 1: Only the *current* BDLE for a stream was saved! */
5210 /* Note 2: The stream's saving order is/was fixed, so don't touch! */
5211
5212 /* Output */
5213 PHDASTREAM pStream = &pThis->aStreams[4];
5214 rc = hdaStreamInit(pThis, pStream, 4 /* Stream descriptor, hardcoded */);
5215 if (RT_FAILURE(rc))
5216 break;
5217 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
5218 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
5219
5220 /* Microphone-In */
5221 pStream = &pThis->aStreams[2];
5222 rc = hdaStreamInit(pThis, pStream, 2 /* Stream descriptor, hardcoded */);
5223 if (RT_FAILURE(rc))
5224 break;
5225 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
5226 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
5227
5228 /* Line-In */
5229 pStream = &pThis->aStreams[0];
5230 rc = hdaStreamInit(pThis, pStream, 0 /* Stream descriptor, hardcoded */);
5231 if (RT_FAILURE(rc))
5232 break;
5233 HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
5234 pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
5235 break;
5236 }
5237
5238 /* Since v5 we support flexible stream and BDLE counts. */
5239 case HDA_SSM_VERSION_5:
5240 case HDA_SSM_VERSION:
5241 {
5242 uint32_t cStreams;
5243 rc = SSMR3GetU32(pSSM, &cStreams);
5244 if (RT_FAILURE(rc))
5245 break;
5246
5247 LogRel2(("hdaLoadExec: cStreams=%RU32\n", cStreams));
5248
5249 /* Load stream states. */
5250 for (uint32_t i = 0; i < cStreams; i++)
5251 {
5252 uint8_t uSD;
5253 rc = SSMR3GetU8(pSSM, &uSD);
5254 if (RT_FAILURE(rc))
5255 break;
5256
5257 PHDASTREAM pStrm = hdaStreamGetFromSD(pThis, uSD);
5258 HDASTREAM StreamDummy;
5259
5260 if (!pStrm)
5261 {
5262 RT_ZERO(StreamDummy);
5263 pStrm = &StreamDummy;
5264 LogRel2(("HDA: Warning: Stream ID=%RU32 not supported, skipping to load ...\n", uSD));
5265 break;
5266 }
5267
5268 rc = hdaStreamInit(pThis, pStrm, uSD);
5269 if (RT_FAILURE(rc))
5270 {
5271 LogRel(("HDA: Stream #%RU32: Initialization of stream %RU8 failed, rc=%Rrc\n", i, uSD, rc));
5272 break;
5273 }
5274
5275 if (uVersion == HDA_SSM_VERSION_5)
5276 {
5277 /* Get the current BDLE entry and skip the rest. */
5278 uint16_t cBDLE;
5279
5280 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
5281 AssertRC(rc);
5282 rc = SSMR3GetU16(pSSM, &cBDLE); /* cBDLE */
5283 AssertRC(rc);
5284 rc = SSMR3GetU16(pSSM, &pStrm->State.uCurBDLE); /* uCurBDLE */
5285 AssertRC(rc);
5286 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
5287 AssertRC(rc);
5288
5289 uint32_t u32BDLEIndex;
5290 for (uint16_t a = 0; a < cBDLE; a++)
5291 {
5292 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
5293 AssertRC(rc);
5294 rc = SSMR3GetU32(pSSM, &u32BDLEIndex); /* u32BDLIndex */
5295 AssertRC(rc);
5296
5297 /* Does the current BDLE index match the current BDLE to process? */
5298 if (u32BDLEIndex == pStrm->State.uCurBDLE)
5299 {
5300 rc = SSMR3GetU32(pSSM, &pStrm->State.BDLE.State.cbBelowFIFOW); /* cbBelowFIFOW */
5301 AssertRC(rc);
5302 rc = SSMR3Skip(pSSM, sizeof(uint8_t) * 256); /* FIFO, deprecated */
5303 AssertRC(rc);
5304 rc = SSMR3GetU32(pSSM, &pStrm->State.BDLE.State.u32BufOff); /* u32BufOff */
5305 AssertRC(rc);
5306 rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
5307 AssertRC(rc);
5308 }
5309 else /* Skip not current BDLEs. */
5310 {
5311 rc = SSMR3Skip(pSSM, sizeof(uint32_t) /* cbBelowFIFOW */
5312 + sizeof(uint8_t) * 256 /* FIFO, deprecated */
5313 + sizeof(uint32_t) /* u32BufOff */
5314 + sizeof(uint32_t)); /* End marker */
5315 AssertRC(rc);
5316 }
5317 }
5318 }
5319 else
5320 {
5321 rc = SSMR3GetStructEx(pSSM, &pStrm->State, sizeof(HDASTREAMSTATE),
5322 0 /* fFlags */, g_aSSMStreamStateFields6, NULL);
5323 if (RT_FAILURE(rc))
5324 break;
5325
5326 rc = SSMR3GetStructEx(pSSM, &pStrm->State.BDLE.Desc, sizeof(HDABDLEDESC),
5327 0 /* fFlags */, g_aSSMBDLEDescFields6, NULL);
5328 if (RT_FAILURE(rc))
5329 break;
5330
5331 rc = SSMR3GetStructEx(pSSM, &pStrm->State.BDLE.State, sizeof(HDABDLESTATE),
5332 0 /* fFlags */, g_aSSMBDLEStateFields6, NULL);
5333 if (RT_FAILURE(rc))
5334 break;
5335 }
5336 }
5337 break;
5338 }
5339
5340 default:
5341 AssertReleaseFailed(); /* Never reached. */
5342 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
5343 }
5344
5345#undef HDA_SSM_LOAD_BDLE_STATE_PRE_V5
5346
5347 if (RT_SUCCESS(rc))
5348 {
5349 pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
5350 pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
5351 pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE), HDA_REG(pThis, DPUBASE));
5352
5353 /* Also make sure to update the DMA position bit if this was enabled when saving the state. */
5354 pThis->fDMAPosition = RT_BOOL(pThis->u64DPBase & RT_BIT_64(0));
5355 }
5356
5357 if (RT_SUCCESS(rc))
5358 {
5359 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5360 {
5361 PHDASTREAM pStream = hdaStreamGetFromSD(pThis, i);
5362 if (pStream)
5363 {
5364 hdaStreamEnable(pThis, pStream, false /* fEnable */);
5365
5366 bool fActive = RT_BOOL(HDA_STREAM_REG(pThis, CTL, i) & HDA_SDCTL_RUN);
5367 if (fActive)
5368 {
5369 int rc2 = hdaStreamEnable(pThis, pStream, true /* fEnable */);
5370 AssertRC(rc2);
5371 }
5372 }
5373 }
5374 }
5375
5376 if (RT_FAILURE(rc))
5377 LogRel(("HDA: Failed loading device state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
5378
5379 LogFlowFuncLeaveRC(rc);
5380 return rc;
5381}
5382
5383
5384/* Debug and log type formatters. */
5385
5386/**
5387 * @callback_method_impl{FNRTSTRFORMATTYPE}
5388 */
5389static DECLCALLBACK(size_t) hdaDbgFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5390 const char *pszType, void const *pvValue,
5391 int cchWidth, int cchPrecision, unsigned fFlags,
5392 void *pvUser)
5393{
5394 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5395 PHDABDLE pBDLE = (PHDABDLE)pvValue;
5396 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5397 "BDLE(idx:%RU32, off:%RU32, fifow:%RU32, IOC:%RTbool, DMA[%RU32 bytes @ 0x%x])",
5398 pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW,
5399 pBDLE->Desc.fFlags & HDA_BDLE_FLAG_IOC, pBDLE->Desc.u32BufSize, pBDLE->Desc.u64BufAdr);
5400}
5401
5402/**
5403 * @callback_method_impl{FNRTSTRFORMATTYPE}
5404 */
5405static DECLCALLBACK(size_t) hdaDbgFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5406 const char *pszType, void const *pvValue,
5407 int cchWidth, int cchPrecision, unsigned fFlags,
5408 void *pvUser)
5409{
5410 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5411 uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
5412 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5413 "SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
5414 uSDCTL,
5415 uSDCTL & HDA_SDCTL_DIR ? "OUT" : "IN",
5416 RT_BOOL(uSDCTL & HDA_SDCTL_TP),
5417 (uSDCTL & HDA_SDCTL_STRIPE_MASK) >> HDA_SDCTL_STRIPE_SHIFT,
5418 RT_BOOL(uSDCTL & HDA_SDCTL_DEIE),
5419 RT_BOOL(uSDCTL & HDA_SDCTL_FEIE),
5420 RT_BOOL(uSDCTL & HDA_SDCTL_IOCE),
5421 RT_BOOL(uSDCTL & HDA_SDCTL_RUN),
5422 RT_BOOL(uSDCTL & HDA_SDCTL_SRST));
5423}
5424
5425/**
5426 * @callback_method_impl{FNRTSTRFORMATTYPE}
5427 */
5428static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5429 const char *pszType, void const *pvValue,
5430 int cchWidth, int cchPrecision, unsigned fFlags,
5431 void *pvUser)
5432{
5433 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5434 uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
5435 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, uSDFIFOS ? uSDFIFOS + 1 : 0);
5436}
5437
5438/**
5439 * @callback_method_impl{FNRTSTRFORMATTYPE}
5440 */
5441static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5442 const char *pszType, void const *pvValue,
5443 int cchWidth, int cchPrecision, unsigned fFlags,
5444 void *pvUser)
5445{
5446 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5447 uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
5448 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
5449}
5450
5451/**
5452 * @callback_method_impl{FNRTSTRFORMATTYPE}
5453 */
5454static DECLCALLBACK(size_t) hdaDbgFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
5455 const char *pszType, void const *pvValue,
5456 int cchWidth, int cchPrecision, unsigned fFlags,
5457 void *pvUser)
5458{
5459 RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
5460 uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
5461 return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
5462 "SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
5463 uSdSts,
5464 RT_BOOL(uSdSts & HDA_SDSTS_FIFORDY),
5465 RT_BOOL(uSdSts & HDA_SDSTS_DESE),
5466 RT_BOOL(uSdSts & HDA_SDSTS_FIFOE),
5467 RT_BOOL(uSdSts & HDA_SDSTS_BCIS));
5468}
5469
5470static int hdaDbgLookupRegByName(const char *pszArgs)
5471{
5472 int iReg = 0;
5473 for (; iReg < HDA_NUM_REGS; ++iReg)
5474 if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
5475 return iReg;
5476 return -1;
5477}
5478
5479
5480static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
5481{
5482 Assert( pThis
5483 && iHdaIndex >= 0
5484 && iHdaIndex < HDA_NUM_REGS);
5485 pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
5486}
5487
5488/**
5489 * @callback_method_impl{FNDBGFHANDLERDEV}
5490 */
5491static DECLCALLBACK(void) hdaDbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5492{
5493 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5494 int iHdaRegisterIndex = hdaDbgLookupRegByName(pszArgs);
5495 if (iHdaRegisterIndex != -1)
5496 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
5497 else
5498 {
5499 for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NUM_REGS; ++iHdaRegisterIndex)
5500 hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
5501 }
5502}
5503
5504static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
5505{
5506 Assert( pThis
5507 && iIdx >= 0
5508 && iIdx < HDA_MAX_STREAMS);
5509
5510 const PHDASTREAM pStrm = &pThis->aStreams[iIdx];
5511
5512 pHlp->pfnPrintf(pHlp, "Stream #%d:\n", iIdx);
5513 pHlp->pfnPrintf(pHlp, "\tSD%dCTL : %R[sdctl]\n", iIdx, HDA_STREAM_REG(pThis, CTL, iIdx));
5514 pHlp->pfnPrintf(pHlp, "\tSD%dCTS : %R[sdsts]\n", iIdx, HDA_STREAM_REG(pThis, STS, iIdx));
5515 pHlp->pfnPrintf(pHlp, "\tSD%dFIFOS: %R[sdfifos]\n", iIdx, HDA_STREAM_REG(pThis, FIFOS, iIdx));
5516 pHlp->pfnPrintf(pHlp, "\tSD%dFIFOW: %R[sdfifow]\n", iIdx, HDA_STREAM_REG(pThis, FIFOW, iIdx));
5517 pHlp->pfnPrintf(pHlp, "\tBDLE : %R[bdle]\n", &pStrm->State.BDLE);
5518}
5519
5520static void hdaDbgPrintBDLE(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
5521{
5522 Assert( pThis
5523 && iIdx >= 0
5524 && iIdx < HDA_MAX_STREAMS);
5525
5526 const PHDASTREAM pStrm = &pThis->aStreams[iIdx];
5527 const PHDABDLE pBDLE = &pStrm->State.BDLE;
5528
5529 pHlp->pfnPrintf(pHlp, "Stream #%d BDLE:\n", iIdx);
5530
5531 uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, iIdx),
5532 HDA_STREAM_REG(pThis, BDPU, iIdx));
5533 uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, iIdx);
5534 uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, iIdx);
5535
5536 if (!u64BaseDMA)
5537 return;
5538
5539 pHlp->pfnPrintf(pHlp, "\tCurrent: %R[bdle]\n\n", pBDLE);
5540
5541 pHlp->pfnPrintf(pHlp, "\tMemory:\n");
5542
5543 uint32_t cbBDLE = 0;
5544 for (uint16_t i = 0; i < u16LVI + 1; i++)
5545 {
5546 HDABDLEDESC bd;
5547 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i * sizeof(HDABDLEDESC), &bd, sizeof(bd));
5548
5549 pHlp->pfnPrintf(pHlp, "\t\t%s #%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
5550 pBDLE->State.u32BDLIndex == i ? "*" : " ", i, bd.u64BufAdr, bd.u32BufSize, bd.fFlags & HDA_BDLE_FLAG_IOC);
5551
5552 cbBDLE += bd.u32BufSize;
5553 }
5554
5555 pHlp->pfnPrintf(pHlp, "Total: %RU32 bytes\n", cbBDLE);
5556
5557 if (cbBDLE != u32CBL)
5558 pHlp->pfnPrintf(pHlp, "Warning: %RU32 bytes does not match CBL (%RU32)!\n", cbBDLE, u32CBL);
5559
5560 pHlp->pfnPrintf(pHlp, "DMA counters (base @ 0x%llx):\n", u64BaseDMA);
5561 if (!u64BaseDMA) /* No DMA base given? Bail out. */
5562 {
5563 pHlp->pfnPrintf(pHlp, "\tNo counters found\n");
5564 return;
5565 }
5566
5567 for (int i = 0; i < u16LVI + 1; i++)
5568 {
5569 uint32_t uDMACnt;
5570 PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
5571 &uDMACnt, sizeof(uDMACnt));
5572
5573 pHlp->pfnPrintf(pHlp, "\t#%03d DMA @ 0x%x\n", i , uDMACnt);
5574 }
5575}
5576
5577static int hdaDbgLookupStrmIdx(PHDASTATE pThis, const char *pszArgs)
5578{
5579 RT_NOREF(pThis, pszArgs);
5580 /** @todo Add args parsing. */
5581 return -1;
5582}
5583
5584/**
5585 * @callback_method_impl{FNDBGFHANDLERDEV}
5586 */
5587static DECLCALLBACK(void) hdaDbgInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5588{
5589 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5590 int iHdaStreamdex = hdaDbgLookupStrmIdx(pThis, pszArgs);
5591 if (iHdaStreamdex != -1)
5592 hdaDbgPrintStream(pThis, pHlp, iHdaStreamdex);
5593 else
5594 for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
5595 hdaDbgPrintStream(pThis, pHlp, iHdaStreamdex);
5596}
5597
5598/**
5599 * @callback_method_impl{FNDBGFHANDLERDEV}
5600 */
5601static DECLCALLBACK(void) hdaDbgInfoBDLE(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5602{
5603 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5604 int iHdaStreamdex = hdaDbgLookupStrmIdx(pThis, pszArgs);
5605 if (iHdaStreamdex != -1)
5606 hdaDbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
5607 else
5608 for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
5609 hdaDbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
5610}
5611
5612/**
5613 * @callback_method_impl{FNDBGFHANDLERDEV}
5614 */
5615static DECLCALLBACK(void) hdaDbgInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5616{
5617 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5618
5619 if (pThis->pCodec->pfnDbgListNodes)
5620 pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
5621 else
5622 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
5623}
5624
5625/**
5626 * @callback_method_impl{FNDBGFHANDLERDEV}
5627 */
5628static DECLCALLBACK(void) hdaDbgInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5629{
5630 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5631
5632 if (pThis->pCodec->pfnDbgSelector)
5633 pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
5634 else
5635 pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
5636}
5637
5638/**
5639 * @callback_method_impl{FNDBGFHANDLERDEV}
5640 */
5641static DECLCALLBACK(void) hdaDbgInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
5642{
5643 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5644
5645 if (pThis->pMixer)
5646 AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
5647 else
5648 pHlp->pfnPrintf(pHlp, "Mixer not available\n");
5649}
5650
5651
5652/* PDMIBASE */
5653
5654/**
5655 * @interface_method_impl{PDMIBASE,pfnQueryInterface}
5656 */
5657static DECLCALLBACK(void *) hdaQueryInterface(struct PDMIBASE *pInterface, const char *pszIID)
5658{
5659 PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
5660 Assert(&pThis->IBase == pInterface);
5661
5662 PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
5663 return NULL;
5664}
5665
5666
5667/* PDMDEVREG */
5668
5669/**
5670 * Reset notification.
5671 *
5672 * @returns VBox status code.
5673 * @param pDevIns The device instance data.
5674 *
5675 * @remark The original sources didn't install a reset handler, but it seems to
5676 * make sense to me so we'll do it.
5677 */
5678static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
5679{
5680 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5681
5682 LogFlowFuncEnter();
5683
5684# ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
5685 /*
5686 * Stop the timer, if any.
5687 */
5688 hdaTimerStop(pThis);
5689
5690 pThis->cStreamsActive = 0;
5691# endif
5692
5693 /* See 6.2.1. */
5694 HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(HDA_MAX_SDO /* Ouput streams */,
5695 HDA_MAX_SDI /* Input streams */,
5696 0 /* Bidirectional output streams */,
5697 0 /* Serial data out signals */,
5698 1 /* 64-bit */);
5699 HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
5700 HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
5701 /* Announce the full 60 words output payload. */
5702 HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
5703 /* Announce the full 29 words input payload. */
5704 HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
5705 HDA_REG(pThis, CORBSIZE) = 0x42; /* see 6.2.1 */
5706 HDA_REG(pThis, RIRBSIZE) = 0x42; /* see 6.2.1 */
5707 HDA_REG(pThis, CORBRP) = 0x0;
5708 HDA_REG(pThis, RIRBWP) = 0x0;
5709
5710 /*
5711 * Stop any audio currently playing and/or recording.
5712 */
5713 if (pThis->SinkFront.pMixSink)
5714 AudioMixerSinkReset(pThis->SinkFront.pMixSink);
5715# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5716 if (pThis->SinkMicIn.pMixSink)
5717 AudioMixerSinkReset(pThis->SinkMicIn.pMixSink);
5718# endif
5719 if (pThis->SinkLineIn.pMixSink)
5720 AudioMixerSinkReset(pThis->SinkLineIn.pMixSink);
5721# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
5722 if (pThis->SinkCenterLFE.pMixSink)
5723 AudioMixerSinkReset(pThis->SinkCenterLFE.pMixSink);
5724 if (pThis->SinkRear.pMixSink)
5725 AudioMixerSinkReset(pThis->SinkRear.pMixSink);
5726# endif
5727
5728 /*
5729 * Reset the codec.
5730 */
5731 if ( pThis->pCodec
5732 && pThis->pCodec->pfnReset)
5733 {
5734 pThis->pCodec->pfnReset(pThis->pCodec);
5735 }
5736
5737 /*
5738 * Set some sensible defaults for which HDA sinks
5739 * are connected to which stream number.
5740 *
5741 * We use SD0 for input and SD4 for output by default.
5742 * These stream numbers can be changed by the guest dynamically lateron.
5743 */
5744#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5745 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_MIC_IN , 1 /* SD0 */, 0 /* Channel */);
5746#endif
5747 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_LINE_IN , 1 /* SD0 */, 0 /* Channel */);
5748
5749 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_FRONT , 5 /* SD4 */, 0 /* Channel */);
5750#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
5751 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_CENTER_LFE, 5 /* SD4 */, 0 /* Channel */);
5752 hdaMixerSetStream(pThis, PDMAUDIOMIXERCTL_REAR , 5 /* SD4 */, 0 /* Channel */);
5753#endif
5754
5755 pThis->cbCorbBuf = 256 * sizeof(uint32_t); /** @todo Use a define here. */
5756
5757 if (pThis->pu32CorbBuf)
5758 RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
5759 else
5760 pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
5761
5762 pThis->cbRirbBuf = 256 * sizeof(uint64_t); /** @todo Use a define here. */
5763 if (pThis->pu64RirbBuf)
5764 RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
5765 else
5766 pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
5767
5768 pThis->u64BaseTS = PDMDevHlpTMTimeVirtGetNano(pDevIns);
5769
5770 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5771 {
5772 /* Remove the RUN bit from SDnCTL in case the stream was in a running state before. */
5773 HDA_STREAM_REG(pThis, CTL, i) &= ~HDA_SDCTL_RUN;
5774 hdaStreamReset(pThis, &pThis->aStreams[i]);
5775 }
5776
5777 /* Clear stream tags <-> objects mapping table. */
5778 RT_ZERO(pThis->aTags);
5779
5780 /* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
5781 HDA_REG(pThis, STATESTS) = 0x1;
5782
5783 LogFlowFuncLeave();
5784 LogRel(("HDA: Reset\n"));
5785}
5786
5787/**
5788 * @interface_method_impl{PDMDEVREG,pfnDestruct}
5789 */
5790static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
5791{
5792 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5793
5794 PHDADRIVER pDrv;
5795 while (!RTListIsEmpty(&pThis->lstDrv))
5796 {
5797 pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
5798
5799 RTListNodeRemove(&pDrv->Node);
5800 RTMemFree(pDrv);
5801 }
5802
5803 if (pThis->pCodec)
5804 {
5805 hdaCodecDestruct(pThis->pCodec);
5806
5807 RTMemFree(pThis->pCodec);
5808 pThis->pCodec = NULL;
5809 }
5810
5811 RTMemFree(pThis->pu32CorbBuf);
5812 pThis->pu32CorbBuf = NULL;
5813
5814 RTMemFree(pThis->pu64RirbBuf);
5815 pThis->pu64RirbBuf = NULL;
5816
5817 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
5818 hdaStreamDestroy(pThis, &pThis->aStreams[i]);
5819
5820 return VINF_SUCCESS;
5821}
5822
5823
5824/**
5825 * Attach command, internal version.
5826 *
5827 * This is called to let the device attach to a driver for a specified LUN
5828 * during runtime. This is not called during VM construction, the device
5829 * constructor has to attach to all the available drivers.
5830 *
5831 * @returns VBox status code.
5832 * @param pDevIns The device instance.
5833 * @param pDrv Driver to (re-)use for (re-)attaching to.
5834 * If NULL is specified, a new driver will be created and appended
5835 * to the driver list.
5836 * @param uLUN The logical unit which is being detached.
5837 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5838 */
5839static int hdaAttachInternal(PPDMDEVINS pDevIns, PHDADRIVER pDrv, unsigned uLUN, uint32_t fFlags)
5840{
5841 RT_NOREF(fFlags);
5842 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5843
5844 /*
5845 * Attach driver.
5846 */
5847 char *pszDesc = NULL;
5848 if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
5849 AssertReleaseMsgReturn(pszDesc,
5850 ("Not enough memory for HDA driver port description of LUN #%u\n", uLUN),
5851 VERR_NO_MEMORY);
5852
5853 PPDMIBASE pDrvBase;
5854 int rc = PDMDevHlpDriverAttach(pDevIns, uLUN,
5855 &pThis->IBase, &pDrvBase, pszDesc);
5856 if (RT_SUCCESS(rc))
5857 {
5858 if (pDrv == NULL)
5859 pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
5860 if (pDrv)
5861 {
5862 pDrv->pDrvBase = pDrvBase;
5863 pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
5864 AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
5865 pDrv->pHDAState = pThis;
5866 pDrv->uLUN = uLUN;
5867
5868 /*
5869 * For now we always set the driver at LUN 0 as our primary
5870 * host backend. This might change in the future.
5871 */
5872 if (pDrv->uLUN == 0)
5873 pDrv->fFlags |= PDMAUDIODRVFLAGS_PRIMARY;
5874
5875 LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->fFlags));
5876
5877 /* Attach to driver list if not attached yet. */
5878 if (!pDrv->fAttached)
5879 {
5880 RTListAppend(&pThis->lstDrv, &pDrv->Node);
5881 pDrv->fAttached = true;
5882 }
5883 }
5884 else
5885 rc = VERR_NO_MEMORY;
5886 }
5887 else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5888 LogFunc(("No attached driver for LUN #%u\n", uLUN));
5889
5890 if (RT_FAILURE(rc))
5891 {
5892 /* Only free this string on failure;
5893 * must remain valid for the live of the driver instance. */
5894 RTStrFree(pszDesc);
5895 }
5896
5897 LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
5898 return rc;
5899}
5900
5901/**
5902 * Attach command.
5903 *
5904 * This is called to let the device attach to a driver for a specified LUN
5905 * during runtime. This is not called during VM construction, the device
5906 * constructor has to attach to all the available drivers.
5907 *
5908 * @returns VBox status code.
5909 * @param pDevIns The device instance.
5910 * @param uLUN The logical unit which is being detached.
5911 * @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
5912 */
5913static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
5914{
5915 return hdaAttachInternal(pDevIns, NULL /* pDrv */, uLUN, fFlags);
5916}
5917
5918static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
5919{
5920 RT_NOREF(pDevIns, uLUN, fFlags);
5921 LogFunc(("iLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
5922}
5923
5924/**
5925 * Powers off the device.
5926 *
5927 * @param pDevIns Device instance to power off.
5928 */
5929static DECLCALLBACK(void) hdaPowerOff(PPDMDEVINS pDevIns)
5930{
5931 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
5932
5933 LogRel2(("HDA: Powering off ...\n"));
5934
5935 /* Ditto goes for the codec, which in turn uses the mixer. */
5936 hdaCodecPowerOff(pThis->pCodec);
5937
5938 /**
5939 * Note: Destroy the mixer while powering off and *not* in hdaDestruct,
5940 * giving the mixer the chance to release any references held to
5941 * PDM audio streams it maintains.
5942 */
5943 if (pThis->pMixer)
5944 {
5945 AudioMixerDestroy(pThis->pMixer);
5946 pThis->pMixer = NULL;
5947 }
5948}
5949
5950/**
5951 * Re-attaches a new driver to the device's driver chain.
5952 *
5953 * @returns VBox status code.
5954 * @param pThis Device instance to re-attach driver to.
5955 * @param pDrv Driver instance used for attaching to.
5956 * If NULL is specified, a new driver will be created and appended
5957 * to the driver list.
5958 * @param uLUN The logical unit which is being re-detached.
5959 * @param pszDriver Driver name.
5960 */
5961static int hdaReattach(PHDASTATE pThis, PHDADRIVER pDrv, uint8_t uLUN, const char *pszDriver)
5962{
5963 AssertPtrReturn(pThis, VERR_INVALID_POINTER);
5964 AssertPtrReturn(pszDriver, VERR_INVALID_POINTER);
5965
5966 PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
5967 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
5968 PCFGMNODE pDev0 = CFGMR3GetChild(pRoot, "Devices/hda/0/");
5969
5970 /* Remove LUN branch. */
5971 CFGMR3RemoveNode(CFGMR3GetChildF(pDev0, "LUN#%u/", uLUN));
5972
5973 if (pDrv)
5974 {
5975 /* Re-use a driver instance => detach the driver before. */
5976 int rc = PDMDevHlpDriverDetach(pThis->pDevInsR3, PDMIBASE_2_PDMDRV(pDrv->pDrvBase), 0 /* fFlags */);
5977 if (RT_FAILURE(rc))
5978 return rc;
5979 }
5980
5981#define RC_CHECK() if (RT_FAILURE(rc)) { AssertReleaseRC(rc); break; }
5982
5983 int rc = VINF_SUCCESS;
5984 do
5985 {
5986 PCFGMNODE pLunL0;
5987 rc = CFGMR3InsertNodeF(pDev0, &pLunL0, "LUN#%u/", uLUN); RC_CHECK();
5988 rc = CFGMR3InsertString(pLunL0, "Driver", "AUDIO"); RC_CHECK();
5989 rc = CFGMR3InsertNode(pLunL0, "Config/", NULL); RC_CHECK();
5990
5991 PCFGMNODE pLunL1, pLunL2;
5992 rc = CFGMR3InsertNode (pLunL0, "AttachedDriver/", &pLunL1); RC_CHECK();
5993 rc = CFGMR3InsertNode (pLunL1, "Config/", &pLunL2); RC_CHECK();
5994 rc = CFGMR3InsertString(pLunL1, "Driver", pszDriver); RC_CHECK();
5995
5996 rc = CFGMR3InsertString(pLunL2, "AudioDriver", pszDriver); RC_CHECK();
5997
5998 } while (0);
5999
6000 if (RT_SUCCESS(rc))
6001 rc = hdaAttachInternal(pThis->pDevInsR3, pDrv, uLUN, 0 /* fFlags */);
6002
6003 LogFunc(("pThis=%p, uLUN=%u, pszDriver=%s, rc=%Rrc\n", pThis, uLUN, pszDriver, rc));
6004
6005#undef RC_CHECK
6006
6007 return rc;
6008}
6009
6010/**
6011 * @interface_method_impl{PDMDEVREG,pfnConstruct}
6012 */
6013static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
6014{
6015 RT_NOREF(iInstance);
6016 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
6017 PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
6018 Assert(iInstance == 0);
6019
6020 /*
6021 * Validations.
6022 */
6023 if (!CFGMR3AreValuesValid(pCfg, "R0Enabled\0"
6024 "RCEnabled\0"
6025 "TimerHz\0"))
6026 return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
6027 N_ ("Invalid configuration for the Intel HDA device"));
6028
6029 int rc = CFGMR3QueryBoolDef(pCfg, "RCEnabled", &pThis->fRCEnabled, false);
6030 if (RT_FAILURE(rc))
6031 return PDMDEV_SET_ERROR(pDevIns, rc,
6032 N_("HDA configuration error: failed to read RCEnabled as boolean"));
6033 rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, false);
6034 if (RT_FAILURE(rc))
6035 return PDMDEV_SET_ERROR(pDevIns, rc,
6036 N_("HDA configuration error: failed to read R0Enabled as boolean"));
6037#ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
6038 uint16_t uTimerHz;
6039 rc = CFGMR3QueryU16Def(pCfg, "TimerHz", &uTimerHz, HDA_TIMER_HZ /* Default value, if not set. */);
6040 if (RT_FAILURE(rc))
6041 return PDMDEV_SET_ERROR(pDevIns, rc,
6042 N_("HDA configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
6043#endif
6044
6045 /*
6046 * Initialize data (most of it anyway).
6047 */
6048 pThis->pDevInsR3 = pDevIns;
6049 pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
6050 pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
6051 /* IBase */
6052 pThis->IBase.pfnQueryInterface = hdaQueryInterface;
6053
6054 /* PCI Device */
6055 PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
6056 PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
6057
6058 PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
6059 PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
6060 PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
6061 PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
6062 PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
6063 PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
6064 PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
6065 PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
6066 false /* fIoSpace */, false /* fPrefetchable */, true /* f64Bit */, 0x00000000);
6067 PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
6068 PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
6069
6070#if defined(HDA_AS_PCI_EXPRESS)
6071 PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
6072#elif defined(VBOX_WITH_MSI_DEVICES)
6073 PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
6074#else
6075 PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
6076#endif
6077
6078 /// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
6079 /// of these values needs to be properly documented!
6080 /* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
6081 PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
6082
6083 /* Power Management */
6084 PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
6085 PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
6086 PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI | 0x02 /* version, PM1.1 */ );
6087
6088#ifdef HDA_AS_PCI_EXPRESS
6089 /* PCI Express */
6090 PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
6091 PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
6092 /* Device flags */
6093 PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
6094 /* version */ 0x1 |
6095 /* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) |
6096 /* MSI */ (100) << 9 );
6097 /* Device capabilities */
6098 PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
6099 /* Device control */
6100 PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
6101 /* Device status */
6102 PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
6103 /* Link caps */
6104 PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
6105 /* Link control */
6106 PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
6107 /* Link status */
6108 PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
6109 /* Slot capabilities */
6110 PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
6111 /* Slot control */
6112 PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
6113 /* Slot status */
6114 PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
6115 /* Root control */
6116 PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
6117 /* Root capabilities */
6118 PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
6119 /* Root status */
6120 PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
6121 /* Device capabilities 2 */
6122 PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
6123 /* Device control 2 */
6124 PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
6125 /* Link control 2 */
6126 PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
6127 /* Slot control 2 */
6128 PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
6129#endif
6130
6131 /*
6132 * Register the PCI device.
6133 */
6134 rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
6135 if (RT_FAILURE(rc))
6136 return rc;
6137
6138 rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
6139 if (RT_FAILURE(rc))
6140 return rc;
6141
6142#ifdef VBOX_WITH_MSI_DEVICES
6143 PDMMSIREG MsiReg;
6144 RT_ZERO(MsiReg);
6145 MsiReg.cMsiVectors = 1;
6146 MsiReg.iMsiCapOffset = 0x60;
6147 MsiReg.iMsiNextOffset = 0x50;
6148 rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
6149 if (RT_FAILURE(rc))
6150 {
6151 /* That's OK, we can work without MSI */
6152 PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
6153 }
6154#endif
6155
6156 rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
6157 if (RT_FAILURE(rc))
6158 return rc;
6159
6160 RTListInit(&pThis->lstDrv);
6161
6162#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
6163 LogRel(("HDA: Asynchronous I/O enabled\n"));
6164#endif
6165
6166 uint8_t uLUN;
6167 for (uLUN = 0; uLUN < UINT8_MAX; ++uLUN)
6168 {
6169 LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
6170 rc = hdaAttachInternal(pDevIns, NULL /* pDrv */, uLUN, 0 /* fFlags */);
6171 if (RT_FAILURE(rc))
6172 {
6173 if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
6174 rc = VINF_SUCCESS;
6175 else if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
6176 {
6177 hdaReattach(pThis, NULL /* pDrv */, uLUN, "NullAudio");
6178 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
6179 N_("Host audio backend initialization has failed. Selecting the NULL audio backend "
6180 "with the consequence that no sound is audible"));
6181 /* Attaching to the NULL audio backend will never fail. */
6182 rc = VINF_SUCCESS;
6183 }
6184 break;
6185 }
6186 }
6187
6188 LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
6189
6190 if (RT_SUCCESS(rc))
6191 {
6192 rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
6193 if (RT_SUCCESS(rc))
6194 {
6195 /*
6196 * Add mixer output sinks.
6197 */
6198#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
6199 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Front",
6200 AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
6201 AssertRC(rc);
6202 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Center / Subwoofer",
6203 AUDMIXSINKDIR_OUTPUT, &pThis->SinkCenterLFE.pMixSink);
6204 AssertRC(rc);
6205 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Rear",
6206 AUDMIXSINKDIR_OUTPUT, &pThis->SinkRear.pMixSink);
6207 AssertRC(rc);
6208#else
6209 rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] PCM Output",
6210 AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
6211 AssertRC(rc);
6212#endif
6213 /*
6214 * Add mixer input sinks.
6215 */
6216 rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Line In",
6217 AUDMIXSINKDIR_INPUT, &pThis->SinkLineIn.pMixSink);
6218 AssertRC(rc);
6219#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
6220 rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Microphone In",
6221 AUDMIXSINKDIR_INPUT, &pThis->SinkMicIn.pMixSink);
6222 AssertRC(rc);
6223#endif
6224 /* There is no master volume control. Set the master to max. */
6225 PDMAUDIOVOLUME vol = { false, 255, 255 };
6226 rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
6227 AssertRC(rc);
6228 }
6229 }
6230
6231 if (RT_SUCCESS(rc))
6232 {
6233 /* Construct codec. */
6234 pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
6235 if (!pThis->pCodec)
6236 return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
6237
6238 /* Set codec callbacks to this controller. */
6239 pThis->pCodec->pfnCbMixerAddStream = hdaMixerAddStream;
6240 pThis->pCodec->pfnCbMixerRemoveStream = hdaMixerRemoveStream;
6241 pThis->pCodec->pfnCbMixerSetStream = hdaMixerSetStream;
6242 pThis->pCodec->pfnCbMixerSetVolume = hdaMixerSetVolume;
6243
6244 pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
6245
6246 /* Construct the codec. */
6247 rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfg);
6248 if (RT_FAILURE(rc))
6249 AssertRCReturn(rc, rc);
6250
6251 /* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
6252 verb F20 should provide device/codec recognition. */
6253 Assert(pThis->pCodec->u16VendorId);
6254 Assert(pThis->pCodec->u16DeviceId);
6255 PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
6256 PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
6257 }
6258
6259 if (RT_SUCCESS(rc))
6260 {
6261 /*
6262 * Create all hardware streams.
6263 */
6264 for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
6265 {
6266 rc = hdaStreamCreate(pThis, &pThis->aStreams[i], i /* uSD */);
6267 AssertRC(rc);
6268 }
6269
6270#ifdef VBOX_WITH_AUDIO_HDA_ONETIME_INIT
6271 /*
6272 * Initialize the driver chain.
6273 */
6274 PHDADRIVER pDrv;
6275 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
6276 {
6277 /*
6278 * Only primary drivers are critical for the VM to run. Everything else
6279 * might not worth showing an own error message box in the GUI.
6280 */
6281 if (!(pDrv->fFlags & PDMAUDIODRVFLAGS_PRIMARY))
6282 continue;
6283
6284 PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
6285 AssertPtr(pCon);
6286
6287 bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
6288# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
6289 bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
6290# endif
6291 bool fValidOut = AudioMixerStreamIsValid(pDrv->Front.pMixStrm);
6292# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
6293 /** @todo Anything to do here? */
6294# endif
6295
6296 if ( !fValidLineIn
6297# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
6298 && !fValidMicIn
6299# endif
6300 && !fValidOut)
6301 {
6302 LogRel(("HDA: Falling back to NULL backend (no sound audible)\n"));
6303
6304 hdaReset(pDevIns);
6305 hdaReattach(pThis, pDrv, pDrv->uLUN, "NullAudio");
6306
6307 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
6308 N_("No audio devices could be opened. Selecting the NULL audio backend "
6309 "with the consequence that no sound is audible"));
6310 }
6311 else
6312 {
6313 bool fWarn = false;
6314
6315 PDMAUDIOBACKENDCFG backendCfg;
6316 int rc2 = pCon->pfnGetConfig(pCon, &backendCfg);
6317 if (RT_SUCCESS(rc2))
6318 {
6319 if (backendCfg.cMaxStreamsIn)
6320 {
6321# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
6322 /* If the audio backend supports two or more input streams at once,
6323 * warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
6324 if (backendCfg.cMaxStreamsIn >= 2)
6325 fWarn = !fValidLineIn || !fValidMicIn;
6326 /* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
6327 * *not* ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
6328 * One of the two simply is not in use then. */
6329 else if (backendCfg.cMaxStreamsIn == 1)
6330 fWarn = !fValidLineIn && !fValidMicIn;
6331 /* Don't warn if our backend is not able of supporting any input streams at all. */
6332# else /* !VBOX_WITH_AUDIO_HDA_MIC_IN */
6333 /* We only have line-in as input source. */
6334 fWarn = !fValidLineIn;
6335# endif /* VBOX_WITH_AUDIO_HDA_MIC_IN */
6336 }
6337
6338 if ( !fWarn
6339 && backendCfg.cMaxStreamsOut)
6340 {
6341 fWarn = !fValidOut;
6342 }
6343 }
6344 else
6345 {
6346 LogRel(("HDA: Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
6347 fWarn = true;
6348 }
6349
6350 if (fWarn)
6351 {
6352 char szMissingStreams[255];
6353 size_t len = 0;
6354 if (!fValidLineIn)
6355 {
6356 LogRel(("HDA: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
6357 len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
6358 }
6359# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
6360 if (!fValidMicIn)
6361 {
6362 LogRel(("HDA: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
6363 len += RTStrPrintf(szMissingStreams + len,
6364 sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
6365 }
6366# endif /* VBOX_WITH_AUDIO_HDA_MIC_IN */
6367 if (!fValidOut)
6368 {
6369 LogRel(("HDA: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
6370 len += RTStrPrintf(szMissingStreams + len,
6371 sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
6372 }
6373
6374 PDMDevHlpVMSetRuntimeError(pDevIns, 0 /*fFlags*/, "HostAudioNotResponding",
6375 N_("Some HDA audio streams (%s) could not be opened. Guest applications generating audio "
6376 "output or depending on audio input may hang. Make sure your host audio device "
6377 "is working properly. Check the logfile for error messages of the audio "
6378 "subsystem"), szMissingStreams);
6379 }
6380 }
6381 }
6382#endif /* VBOX_WITH_AUDIO_HDA_ONETIME_INIT */
6383 }
6384
6385 if (RT_SUCCESS(rc))
6386 {
6387 hdaReset(pDevIns);
6388
6389 /*
6390 * 18.2.6,7 defines that values of this registers might be cleared on power on/reset
6391 * hdaReset shouldn't affects these registers.
6392 */
6393 HDA_REG(pThis, WAKEEN) = 0x0;
6394 HDA_REG(pThis, STATESTS) = 0x0;
6395
6396 /*
6397 * Debug and string formatter types.
6398 */
6399 PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaDbgInfo);
6400 PDMDevHlpDBGFInfoRegister(pDevIns, "hdabdle", "HDA stream BDLE info. (hdabdle [stream number])", hdaDbgInfoBDLE);
6401 PDMDevHlpDBGFInfoRegister(pDevIns, "hdastrm", "HDA stream info. (hdastrm [stream number])", hdaDbgInfoStream);
6402 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaDbgInfoCodecNodes);
6403 PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaDbgInfoCodecSelector);
6404 PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaDbgInfoMixer);
6405
6406 rc = RTStrFormatTypeRegister("bdle", hdaDbgFmtBDLE, NULL);
6407 AssertRC(rc);
6408 rc = RTStrFormatTypeRegister("sdctl", hdaDbgFmtSDCTL, NULL);
6409 AssertRC(rc);
6410 rc = RTStrFormatTypeRegister("sdsts", hdaDbgFmtSDSTS, NULL);
6411 AssertRC(rc);
6412 rc = RTStrFormatTypeRegister("sdfifos", hdaDbgFmtSDFIFOS, NULL);
6413 AssertRC(rc);
6414 rc = RTStrFormatTypeRegister("sdfifow", hdaDbgFmtSDFIFOW, NULL);
6415 AssertRC(rc);
6416
6417 /*
6418 * Some debug assertions.
6419 */
6420 for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
6421 {
6422 struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
6423 struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
6424
6425 /* binary search order. */
6426 AssertReleaseMsg(!pNextReg || pReg->offset + pReg->size <= pNextReg->offset,
6427 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6428 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
6429
6430 /* alignment. */
6431 AssertReleaseMsg( pReg->size == 1
6432 || (pReg->size == 2 && (pReg->offset & 1) == 0)
6433 || (pReg->size == 3 && (pReg->offset & 3) == 0)
6434 || (pReg->size == 4 && (pReg->offset & 3) == 0),
6435 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6436
6437 /* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
6438 AssertRelease(((pReg->offset + pReg->size) & 3) == 0 || pNextReg);
6439 if (pReg->offset & 3)
6440 {
6441 struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
6442 AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6443 if (pPrevReg)
6444 AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
6445 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6446 i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
6447 }
6448#if 0
6449 if ((pReg->offset + pReg->size) & 3)
6450 {
6451 AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6452 if (pNextReg)
6453 AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
6454 ("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
6455 i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
6456 }
6457#endif
6458 /* The final entry is a full DWORD, no gaps! Allows shortcuts. */
6459 AssertReleaseMsg(pNextReg || ((pReg->offset + pReg->size) & 3) == 0,
6460 ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
6461 }
6462 }
6463
6464# ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
6465 if (RT_SUCCESS(rc))
6466 {
6467 /* Create the emulation timer. */
6468 rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL, hdaTimer, pThis,
6469 TMTIMER_FLAGS_NO_CRIT_SECT, "DevHDA", &pThis->pTimer);
6470 AssertRCReturn(rc, rc);
6471
6472 if (RT_SUCCESS(rc))
6473 {
6474 pThis->cTimerTicks = TMTimerGetFreq(pThis->pTimer) / uTimerHz;
6475 pThis->uTimerTS = TMTimerGet(pThis->pTimer);
6476 LogFunc(("Timer ticks=%RU64 (%RU16 Hz)\n", pThis->cTimerTicks, uTimerHz));
6477 }
6478 }
6479# else
6480 if (RT_SUCCESS(rc))
6481 {
6482 PHDADRIVER pDrv;
6483 RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
6484 {
6485 /* Only register primary driver.
6486 * The device emulation does the output multiplexing then. */
6487 if (pDrv->fFlags != PDMAUDIODRVFLAGS_PRIMARY)
6488 continue;
6489
6490 PDMAUDIOCALLBACK AudioCallbacks[2];
6491
6492 HDACALLBACKCTX Ctx = { pThis, pDrv };
6493
6494 AudioCallbacks[0].enmType = PDMAUDIOCALLBACKTYPE_INPUT;
6495 AudioCallbacks[0].pfnCallback = hdaCallbackInput;
6496 AudioCallbacks[0].pvCtx = &Ctx;
6497 AudioCallbacks[0].cbCtx = sizeof(HDACALLBACKCTX);
6498
6499 AudioCallbacks[1].enmType = PDMAUDIOCALLBACKTYPE_OUTPUT;
6500 AudioCallbacks[1].pfnCallback = hdaCallbackOutput;
6501 AudioCallbacks[1].pvCtx = &Ctx;
6502 AudioCallbacks[1].cbCtx = sizeof(HDACALLBACKCTX);
6503
6504 rc = pDrv->pConnector->pfnRegisterCallbacks(pDrv->pConnector, AudioCallbacks, RT_ELEMENTS(AudioCallbacks));
6505 if (RT_FAILURE(rc))
6506 break;
6507 }
6508 }
6509# endif
6510
6511# ifdef VBOX_WITH_STATISTICS
6512 if (RT_SUCCESS(rc))
6513 {
6514 /*
6515 * Register statistics.
6516 */
6517# ifndef VBOX_WITH_AUDIO_HDA_CALLBACKS
6518 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
6519# endif
6520 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIn, STAMTYPE_PROFILE, "/Devices/HDA/Input", STAMUNIT_TICKS_PER_CALL, "Profiling input.");
6521 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatOut, STAMTYPE_PROFILE, "/Devices/HDA/Output", STAMUNIT_TICKS_PER_CALL, "Profiling output.");
6522 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
6523 PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
6524 }
6525# endif
6526
6527#ifdef HDA_DEBUG_DUMP_PCM_DATA
6528 RTFileDelete(HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaDMARead.pcm");
6529 RTFileDelete(HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaDMAWrite.pcm");
6530 RTFileDelete(HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaStreamRead.pcm");
6531 RTFileDelete(HDA_DEBUG_DUMP_PCM_DATA_PATH "hdaStreamWrite.pcm");
6532#endif
6533
6534 LogFlowFuncLeaveRC(rc);
6535 return rc;
6536}
6537
6538/**
6539 * The device registration structure.
6540 */
6541const PDMDEVREG g_DeviceHDA =
6542{
6543 /* u32Version */
6544 PDM_DEVREG_VERSION,
6545 /* szName */
6546 "hda",
6547 /* szRCMod */
6548 "VBoxDDRC.rc",
6549 /* szR0Mod */
6550 "VBoxDDR0.r0",
6551 /* pszDescription */
6552 "Intel HD Audio Controller",
6553 /* fFlags */
6554 PDM_DEVREG_FLAGS_DEFAULT_BITS | PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0,
6555 /* fClass */
6556 PDM_DEVREG_CLASS_AUDIO,
6557 /* cMaxInstances */
6558 1,
6559 /* cbInstance */
6560 sizeof(HDASTATE),
6561 /* pfnConstruct */
6562 hdaConstruct,
6563 /* pfnDestruct */
6564 hdaDestruct,
6565 /* pfnRelocate */
6566 NULL,
6567 /* pfnMemSetup */
6568 NULL,
6569 /* pfnPowerOn */
6570 NULL,
6571 /* pfnReset */
6572 hdaReset,
6573 /* pfnSuspend */
6574 NULL,
6575 /* pfnResume */
6576 NULL,
6577 /* pfnAttach */
6578 hdaAttach,
6579 /* pfnDetach */
6580 hdaDetach,
6581 /* pfnQueryInterface. */
6582 NULL,
6583 /* pfnInitComplete */
6584 NULL,
6585 /* pfnPowerOff */
6586 hdaPowerOff,
6587 /* pfnSoftReset */
6588 NULL,
6589 /* u32VersionEnd */
6590 PDM_DEVREG_VERSION
6591};
6592
6593#endif /* IN_RING3 */
6594#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
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