DevHDA.cpp@ 70905

Last change on this file since 70905 was 70905, checked in by vboxsync, 7 years ago
Audio/DevHDA.cpp: Separate stream adding / removal in own functions and only add streams when actual starting transfers.
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File size: 189.4 KB

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1	/* $Id: DevHDA.cpp 70905 2018-02-08 10:30:58Z vboxsync $ */
2	/** @file
3	* DevHDA.cpp - VBox Intel HD Audio Controller.
4	*
5	* Implemented against the specifications found in "High Definition Audio
6	* Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7	* HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8	*/
9
10	/*
11	* Copyright (C) 2006-2017 Oracle Corporation
12	*
13	* This file is part of VirtualBox Open Source Edition (OSE), as
14	* available from http://www.virtualbox.org. This file is free software;
15	* you can redistribute it and/or modify it under the terms of the GNU
16	* General Public License (GPL) as published by the Free Software
17	* Foundation, in version 2 as it comes in the "COPYING" file of the
18	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20	*/
21
22
23	/*********************************************************************************************************************************
24	* Header Files *
25	*********************************************************************************************************************************/
26	#define LOG_GROUP LOG_GROUP_DEV_HDA
27	#include <VBox/log.h>
28
29	#include <VBox/vmm/pdmdev.h>
30	#include <VBox/vmm/pdmaudioifs.h>
31	#include <VBox/version.h>
32
33	#include <iprt/assert.h>
34	#include <iprt/asm.h>
35	#include <iprt/asm-math.h>
36	#include <iprt/file.h>
37	#include <iprt/list.h>
38	#ifdef IN_RING3
39	# include <iprt/mem.h>
40	# include <iprt/semaphore.h>
41	# include <iprt/string.h>
42	# include <iprt/uuid.h>
43	#endif
44
45	#include "VBoxDD.h"
46
47	#include "AudioMixBuffer.h"
48	#include "AudioMixer.h"
49
50	#include "DevHDA.h"
51	#include "DevHDACommon.h"
52
53	#include "HDACodec.h"
54	#include "HDAStream.h"
55	# if defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT) \|\| defined(VBOX_WITH_AUDIO_HDA_51_SURROUND)
56	# include "HDAStreamChannel.h"
57	# endif
58	#include "HDAStreamMap.h"
59	#include "HDAStreamPeriod.h"
60
61	#include "DrvAudio.h"
62
63
64	/*********************************************************************************************************************************
65	* Defined Constants And Macros *
66	*********************************************************************************************************************************/
67	//#define HDA_AS_PCI_EXPRESS
68
69	/* Installs a DMA access handler (via PGM callback) to monitor
70	* HDA's DMA operations, that is, writing / reading audio stream data.
71	*
72	* !!! Note: Certain guests are that timing sensitive that when enabling !!!
73	* !!! such a handler will mess up audio completely (e.g. Windows 7). !!! */
74	//#define HDA_USE_DMA_ACCESS_HANDLER
75	#ifdef HDA_USE_DMA_ACCESS_HANDLER
76	# include <VBox/vmm/pgm.h>
77	#endif
78
79	/* Uses the DMA access handler to read the written DMA audio (output) data.
80	* Only valid if HDA_USE_DMA_ACCESS_HANDLER is set.
81	*
82	* Also see the note / warning for HDA_USE_DMA_ACCESS_HANDLER. */
83	//# define HDA_USE_DMA_ACCESS_HANDLER_WRITING
84
85	/* Useful to debug the device' timing. */
86	//#define HDA_DEBUG_TIMING
87
88	/* To debug silence coming from the guest in form of audio gaps.
89	* Very crude implementation for now. */
90	//#define HDA_DEBUG_SILENCE
91
92	#if defined(VBOX_WITH_HP_HDA)
93	/* HP Pavilion dv4t-1300 */
94	# define HDA_PCI_VENDOR_ID 0x103c
95	# define HDA_PCI_DEVICE_ID 0x30f7
96	#elif defined(VBOX_WITH_INTEL_HDA)
97	/* Intel HDA controller */
98	# define HDA_PCI_VENDOR_ID 0x8086
99	# define HDA_PCI_DEVICE_ID 0x2668
100	#elif defined(VBOX_WITH_NVIDIA_HDA)
101	/* nVidia HDA controller */
102	# define HDA_PCI_VENDOR_ID 0x10de
103	# define HDA_PCI_DEVICE_ID 0x0ac0
104	#else
105	# error "Please specify your HDA device vendor/device IDs"
106	#endif
107
108	/* Make sure that interleaving streams support is enabled if the 5.1 surround code is being used. */
109	#if defined (VBOX_WITH_AUDIO_HDA_51_SURROUND) && !defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT)
110	# define VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT
111	#endif
112
113
114	/*********************************************************************************************************************************
115	* Structures and Typedefs *
116	*********************************************************************************************************************************/
117
118	/**
119	* Structure defining a (host backend) driver stream.
120	* Each driver has its own instances of audio mixer streams, which then
121	* can go into the same (or even different) audio mixer sinks.
122	*/
123	typedef struct HDADRIVERSTREAM
124	{
125	union
126	{
127	/** Desired playback destination (for an output stream). */
128	PDMAUDIOPLAYBACKDEST Dest;
129	/** Desired recording source (for an input stream). */
130	PDMAUDIORECSOURCE Source;
131	} DestSource;
132	uint8_t Padding1[4];
133	/** Associated mixer handle. */
134	R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
135	} HDADRIVERSTREAM, *PHDADRIVERSTREAM;
136
137	#ifdef HDA_USE_DMA_ACCESS_HANDLER
138	/**
139	* Struct for keeping an HDA DMA access handler context.
140	*/
141	typedef struct HDADMAACCESSHANDLER
142	{
143	/** Node for storing this handler in our list in HDASTREAMSTATE. */
144	RTLISTNODER3 Node;
145	/** Pointer to stream to which this access handler is assigned to. */
146	R3PTRTYPE(PHDASTREAM) pStream;
147	/** Access handler type handle. */
148	PGMPHYSHANDLERTYPE hAccessHandlerType;
149	/** First address this handler uses. */
150	RTGCPHYS GCPhysFirst;
151	/** Last address this handler uses. */
152	RTGCPHYS GCPhysLast;
153	/** Actual BDLE address to handle. */
154	RTGCPHYS BDLEAddr;
155	/** Actual BDLE buffer size to handle. */
156	RTGCPHYS BDLESize;
157	/** Whether the access handler has been registered or not. */
158	bool fRegistered;
159	uint8_t Padding[3];
160	} HDADMAACCESSHANDLER, *PHDADMAACCESSHANDLER;
161	#endif
162
163	/**
164	* Struct for maintaining a host backend driver.
165	* This driver must be associated to one, and only one,
166	* HDA codec. The HDA controller does the actual multiplexing
167	* of HDA codec data to various host backend drivers then.
168	*
169	* This HDA device uses a timer in order to synchronize all
170	* read/write accesses across all attached LUNs / backends.
171	*/
172	typedef struct HDADRIVER
173	{
174	/** Node for storing this driver in our device driver list of HDASTATE. */
175	RTLISTNODER3 Node;
176	/** Pointer to HDA controller (state). */
177	R3PTRTYPE(PHDASTATE) pHDAState;
178	/** Driver flags. */
179	PDMAUDIODRVFLAGS fFlags;
180	uint8_t u32Padding0[2];
181	/** LUN to which this driver has been assigned. */
182	uint8_t uLUN;
183	/** Whether this driver is in an attached state or not. */
184	bool fAttached;
185	/** Pointer to attached driver base interface. */
186	R3PTRTYPE(PPDMIBASE) pDrvBase;
187	/** Audio connector interface to the underlying host backend. */
188	R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
189	/** Mixer stream for line input. */
190	HDADRIVERSTREAM LineIn;
191	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
192	/** Mixer stream for mic input. */
193	HDADRIVERSTREAM MicIn;
194	#endif
195	/** Mixer stream for front output. */
196	HDADRIVERSTREAM Front;
197	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
198	/** Mixer stream for center/LFE output. */
199	HDADRIVERSTREAM CenterLFE;
200	/** Mixer stream for rear output. */
201	HDADRIVERSTREAM Rear;
202	#endif
203	} HDADRIVER;
204
205
206	/*********************************************************************************************************************************
207	* Internal Functions *
208	*********************************************************************************************************************************/
209	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
210	#ifdef IN_RING3
211	static void hdaGCTLReset(PHDASTATE pThis);
212	#endif
213
214	/** @name Register read/write stubs.
215	* @{
216	*/
217	static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
218	static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
219	/** @} */
220
221	/** @name Global register set read/write functions.
222	* @{
223	*/
224	static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
225	static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
226	static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
227	static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
228	static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
229	static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
230	static int hdaRegWriteCORBSIZE(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
231	static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
232	static int hdaRegWriteRINTCNT(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
233	static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
234	static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
235	static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
236	static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
237	static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
238	static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
239	/** @} */
240
241	/** @name {IOB}SDn write functions.
242	* @{
243	*/
244	static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
245	static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
246	static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
247	static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
248	static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
249	static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
250	static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
251	static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
252	static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
253	/** @} */
254
255	/** @name Generic register read/write functions.
256	* @{
257	*/
258	static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
259	static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
260	static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
261	#ifdef IN_RING3
262	static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
263	#endif
264	static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
265	static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
266	static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
267	static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
268	/** @} */
269
270	/** @name HDA device functions.
271	* @{
272	*/
273	#ifdef IN_RING3
274	static int hdaAddStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg);
275	static int hdaRemoveStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg);
276	# ifdef HDA_USE_DMA_ACCESS_HANDLER
277	static DECLCALLBACK(VBOXSTRICTRC) hdaDMAAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void pvPhys, void pvBuf, size_t cbBuf, PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser);
278	# endif
279	static void hdaDoTransfers(PHDASTATE pThis);
280	#endif /* IN_RING3 */
281	/** @} */
282
283	/** @name Timer functions.
284	* @{
285	*/
286	#ifdef IN_RING3
287	static void hdaTimerMain(PHDASTATE pThis);
288	#endif
289	/** @} */
290
291
292	/*********************************************************************************************************************************
293	* Global Variables *
294	*********************************************************************************************************************************/
295
296	/** No register description (RD) flags defined. */
297	#define HDA_RD_FLAG_NONE 0
298	/** Writes to SD are allowed while RUN bit is set. */
299	#define HDA_RD_FLAG_SD_WRITE_RUN RT_BIT(0)
300
301	/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
302	#define HDA_REG_MAP_STRM(offset, name) \
303	/* offset size read mask write mask flags read callback write callback index + abbrev description */ \
304	/* ------- ------- ---------- ---------- ------------------------- -------------- ----------------- ----------------------------- ----------- */ \
305	/* Offset 0x80 (SD0) */ \
306	{ offset, 0x00003, 0x00FF001F, 0x00F0001F, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL) , #name " Stream Descriptor Control" }, \
307	/* Offset 0x83 (SD0) */ \
308	{ offset + 0x3, 0x00001, 0x0000003C, 0x0000001C, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU8 , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS) , #name " Status" }, \
309	/* Offset 0x84 (SD0) */ \
310	{ offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadLPIB, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
311	/* Offset 0x88 (SD0) */ \
312	{ offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDCBL , HDA_REG_IDX_STRM(name, CBL) , #name " Cyclic Buffer Length" }, \
313	/* Offset 0x8C (SD0) */ \
314	{ offset + 0xC, 0x00002, 0x0000FFFF, 0x0000FFFF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDLVI , HDA_REG_IDX_STRM(name, LVI) , #name " Last Valid Index" }, \
315	/* Reserved: FIFO Watermark. ** @todo Document this! */ \
316	{ offset + 0xE, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
317	/* Offset 0x90 (SD0) */ \
318	{ offset + 0x10, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
319	/* Offset 0x92 (SD0) */ \
320	{ offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFMT , HDA_REG_IDX_STRM(name, FMT) , #name " Stream Format" }, \
321	/* Reserved: 0x94 - 0x98. */ \
322	/* Offset 0x98 (SD0) */ \
323	{ offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
324	/* Offset 0x9C (SD0) */ \
325	{ offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
326
327	/** Defines a single audio stream register set (e.g. OSD0). */
328	#define HDA_REG_MAP_DEF_STREAM(index, name) \
329	HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
330
331	/* See 302349 p 6.2. */
332	const HDAREGDESC g_aHdaRegMap[HDA_NUM_REGS] =
333	{
334	/* offset size read mask write mask flags read callback write callback index + abbrev */
335	/------- ------- ---------- ---------- ----------------- ---------------- ------------------- ------------------------ /
336	{ 0x00000, 0x00002, 0x0000FFFB, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(GCAP) }, /* Global Capabilities */
337	{ 0x00002, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMIN) }, /* Minor Version */
338	{ 0x00003, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMAJ) }, /* Major Version */
339	{ 0x00004, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTPAY) }, /* Output Payload Capabilities */
340	{ 0x00006, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INPAY) }, /* Input Payload Capabilities */
341	{ 0x00008, 0x00004, 0x00000103, 0x00000103, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteGCTL , HDA_REG_IDX(GCTL) }, /* Global Control */
342	{ 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(WAKEEN) }, /* Wake Enable */
343	{ 0x0000e, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteSTATESTS, HDA_REG_IDX(STATESTS) }, /* State Change Status */
344	{ 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadUnimpl, hdaRegWriteUnimpl , HDA_REG_IDX(GSTS) }, /* Global Status */
345	{ 0x00018, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTSTRMPAY) }, /* Output Stream Payload Capability */
346	{ 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INSTRMPAY) }, /* Input Stream Payload Capability */
347	{ 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */
348	{ 0x00024, 0x00004, 0xC00000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */
349	{ 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadWALCLK, hdaRegWriteUnimpl , HDA_REG_IDX_NOMEM(WALCLK) }, /* Wall Clock Counter */
350	{ 0x00034, 0x00004, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */
351	{ 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
352	{ 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBUBASE) }, /* CORB Upper Base Address */
353	{ 0x00048, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteCORBWP , HDA_REG_IDX(CORBWP) }, /* CORB Write Pointer */
354	{ 0x0004A, 0x00002, 0x000080FF, 0x00008000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteCORBRP , HDA_REG_IDX(CORBRP) }, /* CORB Read Pointer */
355	{ 0x0004C, 0x00001, 0x00000003, 0x00000003, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL) }, /* CORB Control */
356	{ 0x0004D, 0x00001, 0x00000001, 0x00000001, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS) }, /* CORB Status */
357	{ 0x0004E, 0x00001, 0x000000F3, 0x00000003, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBSIZE, HDA_REG_IDX(CORBSIZE) }, /* CORB Size */
358	{ 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBLBASE) }, /* RIRB Lower Base Address */
359	{ 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBUBASE) }, /* RIRB Upper Base Address */
360	{ 0x00058, 0x00002, 0x000000FF, 0x00008000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteRIRBWP , HDA_REG_IDX(RIRBWP) }, /* RIRB Write Pointer */
361	{ 0x0005A, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteRINTCNT , HDA_REG_IDX(RINTCNT) }, /* Response Interrupt Count */
362	{ 0x0005C, 0x00001, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteU8 , HDA_REG_IDX(RIRBCTL) }, /* RIRB Control */
363	{ 0x0005D, 0x00001, 0x00000005, 0x00000005, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS) }, /* RIRB Status */
364	{ 0x0005E, 0x00001, 0x000000F3, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(RIRBSIZE) }, /* RIRB Size */
365	{ 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(IC) }, /* Immediate Command */
366	{ 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(IR) }, /* Immediate Response */
367	{ 0x00068, 0x00002, 0x00000002, 0x00000002, HDA_RD_FLAG_NONE, hdaRegReadIRS , hdaRegWriteIRS , HDA_REG_IDX(IRS) }, /* Immediate Command Status */
368	{ 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPLBASE) }, /* DMA Position Lower Base */
369	{ 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPUBASE) }, /* DMA Position Upper Base */
370	/* 4 Serial Data In (SDI). */
371	HDA_REG_MAP_DEF_STREAM(0, SD0),
372	HDA_REG_MAP_DEF_STREAM(1, SD1),
373	HDA_REG_MAP_DEF_STREAM(2, SD2),
374	HDA_REG_MAP_DEF_STREAM(3, SD3),
375	/* 4 Serial Data Out (SDO). */
376	HDA_REG_MAP_DEF_STREAM(4, SD4),
377	HDA_REG_MAP_DEF_STREAM(5, SD5),
378	HDA_REG_MAP_DEF_STREAM(6, SD6),
379	HDA_REG_MAP_DEF_STREAM(7, SD7)
380	};
381
382	const HDAREGALIAS g_aHdaRegAliases[] =
383	{
384	{ 0x2084, HDA_REG_SD0LPIB },
385	{ 0x20a4, HDA_REG_SD1LPIB },
386	{ 0x20c4, HDA_REG_SD2LPIB },
387	{ 0x20e4, HDA_REG_SD3LPIB },
388	{ 0x2104, HDA_REG_SD4LPIB },
389	{ 0x2124, HDA_REG_SD5LPIB },
390	{ 0x2144, HDA_REG_SD6LPIB },
391	{ 0x2164, HDA_REG_SD7LPIB }
392	};
393
394	#ifdef IN_RING3
395	/** HDABDLEDESC field descriptors for the v7 saved state. */
396	static SSMFIELD const g_aSSMBDLEDescFields7[] =
397	{
398	SSMFIELD_ENTRY(HDABDLEDESC, u64BufAdr),
399	SSMFIELD_ENTRY(HDABDLEDESC, u32BufSize),
400	SSMFIELD_ENTRY(HDABDLEDESC, fFlags),
401	SSMFIELD_ENTRY_TERM()
402	};
403
404	/** HDABDLESTATE field descriptors for the v6+ saved state. */
405	static SSMFIELD const g_aSSMBDLEStateFields6[] =
406	{
407	SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
408	SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
409	SSMFIELD_ENTRY_OLD(FIFO, HDA_FIFO_MAX), /* Deprecated; now is handled in the stream's circular buffer. */
410	SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
411	SSMFIELD_ENTRY_TERM()
412	};
413
414	/** HDABDLESTATE field descriptors for the v7 saved state. */
415	static SSMFIELD const g_aSSMBDLEStateFields7[] =
416	{
417	SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
418	SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
419	SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
420	SSMFIELD_ENTRY_TERM()
421	};
422
423	/** HDASTREAMSTATE field descriptors for the v6 saved state. */
424	static SSMFIELD const g_aSSMStreamStateFields6[] =
425	{
426	SSMFIELD_ENTRY_OLD(cBDLE, sizeof(uint16_t)), /* Deprecated. */
427	SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
428	SSMFIELD_ENTRY_OLD(fStop, 1), /* Deprecated; see SSMR3PutBool(). */
429	SSMFIELD_ENTRY_OLD(fRunning, 1), /* Deprecated; using the HDA_SDCTL_RUN bit is sufficient. */
430	SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
431	SSMFIELD_ENTRY_TERM()
432	};
433
434	/** HDASTREAMSTATE field descriptors for the v7 saved state. */
435	static SSMFIELD const g_aSSMStreamStateFields7[] =
436	{
437	SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
438	SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
439	SSMFIELD_ENTRY(HDASTREAMSTATE, tsTransferNext),
440	SSMFIELD_ENTRY_TERM()
441	};
442
443	/** HDASTREAMPERIOD field descriptors for the v7 saved state. */
444	static SSMFIELD const g_aSSMStreamPeriodFields7[] =
445	{
446	SSMFIELD_ENTRY(HDASTREAMPERIOD, u64StartWalClk),
447	SSMFIELD_ENTRY(HDASTREAMPERIOD, u64ElapsedWalClk),
448	SSMFIELD_ENTRY(HDASTREAMPERIOD, framesTransferred),
449	SSMFIELD_ENTRY(HDASTREAMPERIOD, cIntPending),
450	SSMFIELD_ENTRY_TERM()
451	};
452	#endif
453
454	/**
455	* 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
456	*/
457	static uint32_t const g_afMasks[5] =
458	{
459	UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
460	};
461
462	/**
463	* Acquires the HDA lock.
464	*/
465	#define DEVHDA_LOCK(a_pThis) \
466	do { \
467	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
468	AssertRC(rcLock); \
469	} while (0)
470
471	/**
472	* Acquires the HDA lock or returns.
473	*/
474	# define DEVHDA_LOCK_RETURN(a_pThis, a_rcBusy) \
475	do { \
476	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, a_rcBusy); \
477	if (rcLock != VINF_SUCCESS) \
478	{ \
479	AssertRC(rcLock); \
480	return rcLock; \
481	} \
482	} while (0)
483
484	/**
485	* Acquires the HDA lock or returns.
486	*/
487	# define DEVHDA_LOCK_RETURN_VOID(a_pThis) \
488	do { \
489	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
490	if (rcLock != VINF_SUCCESS) \
491	{ \
492	AssertRC(rcLock); \
493	return; \
494	} \
495	} while (0)
496
497	/**
498	* Releases the HDA lock.
499	*/
500	#define DEVHDA_UNLOCK(a_pThis) \
501	do { PDMCritSectLeave(&(a_pThis)->CritSect); } while (0)
502
503	/**
504	* Acquires the TM lock and HDA lock, returns on failure.
505	*/
506	#define DEVHDA_LOCK_BOTH_RETURN_VOID(a_pThis) \
507	do { \
508	int rcLock = TMTimerLock((a_pThis)->pTimer, VERR_IGNORED); \
509	if (rcLock != VINF_SUCCESS) \
510	{ \
511	AssertRC(rcLock); \
512	return; \
513	} \
514	rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
515	if (rcLock != VINF_SUCCESS) \
516	{ \
517	AssertRC(rcLock); \
518	TMTimerUnlock((a_pThis)->pTimer); \
519	return; \
520	} \
521	} while (0)
522
523	/**
524	* Acquires the TM lock and HDA lock, returns on failure.
525	*/
526	#define DEVHDA_LOCK_BOTH_RETURN(a_pThis, a_rcBusy) \
527	do { \
528	int rcLock = TMTimerLock((a_pThis)->pTimer, (a_rcBusy)); \
529	if (rcLock != VINF_SUCCESS) \
530	return rcLock; \
531	rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, (a_rcBusy)); \
532	if (rcLock != VINF_SUCCESS) \
533	{ \
534	AssertRC(rcLock); \
535	TMTimerUnlock((a_pThis)->pTimer); \
536	return rcLock; \
537	} \
538	} while (0)
539
540	/**
541	* Releases the HDA lock and TM lock.
542	*/
543	#define DEVHDA_UNLOCK_BOTH(a_pThis) \
544	do { \
545	PDMCritSectLeave(&(a_pThis)->CritSect); \
546	TMTimerUnlock((a_pThis)->pTimer); \
547	} while (0)
548
549	#ifdef IN_RING3
550	/**
551	* Retrieves the number of bytes of a FIFOW register.
552	*
553	* @return Number of bytes of a given FIFOW register.
554	*/
555	DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
556	{
557	uint32_t cb;
558	switch (u32RegFIFOW)
559	{
560	case HDA_SDFIFOW_8B: cb = 8; break;
561	case HDA_SDFIFOW_16B: cb = 16; break;
562	case HDA_SDFIFOW_32B: cb = 32; break;
563	default: cb = 0; break;
564	}
565
566	Assert(RT_IS_POWER_OF_TWO(cb));
567	return cb;
568	}
569
570	/**
571	* Reschedules pending interrupts for all audio streams which have complete
572	* audio periods but did not have the chance to issue their (pending) interrupts yet.
573	*
574	* @param pThis The HDA device state.
575	*/
576	static void hdaReschedulePendingInterrupts(PHDASTATE pThis)
577	{
578	bool fInterrupt = false;
579
580	for (uint8_t i = 0; i < HDA_MAX_STREAMS; ++i)
581	{
582	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, i);
583	if (!pStream)
584	continue;
585
586	if ( hdaStreamPeriodIsComplete (&pStream->State.Period)
587	&& hdaStreamPeriodNeedsInterrupt(&pStream->State.Period)
588	&& hdaWalClkSet(pThis, hdaStreamPeriodGetAbsElapsedWalClk(&pStream->State.Period), false /* fForce */))
589	{
590	fInterrupt = true;
591	break;
592	}
593	}
594
595	LogFunc(("fInterrupt=%RTbool\n", fInterrupt));
596
597	#ifndef DEBUG
598	hdaProcessInterrupt(pThis);
599	#else
600	hdaProcessInterrupt(pThis, __FUNCTION__);
601	#endif
602	}
603	#endif
604
605	/**
606	* Looks up a register at the exact offset given by @a offReg.
607	*
608	* @returns Register index on success, -1 if not found.
609	* @param offReg The register offset.
610	*/
611	static int hdaRegLookup(uint32_t offReg)
612	{
613	/*
614	* Aliases.
615	*/
616	if (offReg >= g_aHdaRegAliases[0].offReg)
617	{
618	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
619	if (offReg == g_aHdaRegAliases[i].offReg)
620	return g_aHdaRegAliases[i].idxAlias;
621	Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
622	return -1;
623	}
624
625	/*
626	* Binary search the
627	*/
628	int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
629	int idxLow = 0;
630	for (;;)
631	{
632	int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
633	if (offReg < g_aHdaRegMap[idxMiddle].offset)
634	{
635	if (idxLow == idxMiddle)
636	break;
637	idxEnd = idxMiddle;
638	}
639	else if (offReg > g_aHdaRegMap[idxMiddle].offset)
640	{
641	idxLow = idxMiddle + 1;
642	if (idxLow >= idxEnd)
643	break;
644	}
645	else
646	return idxMiddle;
647	}
648
649	#ifdef RT_STRICT
650	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
651	Assert(g_aHdaRegMap[i].offset != offReg);
652	#endif
653	return -1;
654	}
655
656	/**
657	* Looks up a register covering the offset given by @a offReg.
658	*
659	* @returns Register index on success, -1 if not found.
660	* @param offReg The register offset.
661	*/
662	static int hdaRegLookupWithin(uint32_t offReg)
663	{
664	/*
665	* Aliases.
666	*/
667	if (offReg >= g_aHdaRegAliases[0].offReg)
668	{
669	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
670	{
671	uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
672	if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
673	return g_aHdaRegAliases[i].idxAlias;
674	}
675	Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
676	return -1;
677	}
678
679	/*
680	* Binary search the register map.
681	*/
682	int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
683	int idxLow = 0;
684	for (;;)
685	{
686	int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
687	if (offReg < g_aHdaRegMap[idxMiddle].offset)
688	{
689	if (idxLow == idxMiddle)
690	break;
691	idxEnd = idxMiddle;
692	}
693	else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
694	{
695	idxLow = idxMiddle + 1;
696	if (idxLow >= idxEnd)
697	break;
698	}
699	else
700	return idxMiddle;
701	}
702
703	#ifdef RT_STRICT
704	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
705	Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
706	#endif
707	return -1;
708	}
709
710	#ifdef IN_RING3
711	/**
712	* Synchronizes the CORB / RIRB buffers between internal <-> device state.
713	*
714	* @returns IPRT status code.
715	* @param pThis HDA state.
716	* @param fLocal Specify true to synchronize HDA state's CORB buffer with the device state,
717	* or false to synchronize the device state's RIRB buffer with the HDA state.
718	*
719	* @todo r=andy Break this up into two functions?
720	*/
721	static int hdaCmdSync(PHDASTATE pThis, bool fLocal)
722	{
723	int rc = VINF_SUCCESS;
724	if (fLocal)
725	{
726	if (pThis->u64CORBBase)
727	{
728	AssertPtr(pThis->pu32CorbBuf);
729	Assert(pThis->cbCorbBuf);
730
731	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
732	if (RT_FAILURE(rc))
733	AssertRCReturn(rc, rc);
734	}
735	}
736	else
737	{
738	if (pThis->u64RIRBBase)
739	{
740	AssertPtr(pThis->pu64RirbBuf);
741	Assert(pThis->cbRirbBuf);
742
743	rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
744	if (RT_FAILURE(rc))
745	AssertRCReturn(rc, rc);
746	}
747	}
748
749	#ifdef DEBUG_CMD_BUFFER
750	LogFunc(("fLocal=%RTbool\n", fLocal));
751
752	uint8_t i = 0;
753	do
754	{
755	LogFunc(("CORB%02x: ", i));
756	uint8_t j = 0;
757	do
758	{
759	const char *pszPrefix;
760	if ((i + j) == HDA_REG(pThis, CORBRP))
761	pszPrefix = "[R]";
762	else if ((i + j) == HDA_REG(pThis, CORBWP))
763	pszPrefix = "[W]";
764	else
765	pszPrefix = " "; /* three spaces */
766	Log((" %s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
767	j++;
768	} while (j < 8);
769	Log(("\n"));
770	i += 8;
771	} while(i != 0);
772
773	do {
774	LogFunc(("RIRB%02x: ", i));
775	uint8_t j = 0;
776	do {
777	const char *prefix;
778	if ((i + j) == HDA_REG(pThis, RIRBWP))
779	prefix = "[W]";
780	else
781	prefix = " ";
782	Log((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
783	} while (++j < 8);
784	Log(("\n"));
785	i += 8;
786	} while (i != 0);
787	#endif
788	return rc;
789	}
790
791	/**
792	* Processes the next CORB buffer command in the queue.
793	* This will invoke the HDA codec verb dispatcher.
794	*
795	* @returns IPRT status code.
796	* @param pThis HDA state.
797	*/
798	static int hdaCORBCmdProcess(PHDASTATE pThis)
799	{
800	uint8_t corbRp = HDA_REG(pThis, CORBRP);
801	uint8_t corbWp = HDA_REG(pThis, CORBWP);
802	uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
803
804	Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", corbRp, corbWp, rirbWp));
805
806	if (!(HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA))
807	{
808	LogFunc(("CORB DMA not active, skipping\n"));
809	return VINF_SUCCESS;
810	}
811
812	Assert(pThis->cbCorbBuf);
813
814	int rc = hdaCmdSync(pThis, true /* Sync from guest */);
815	AssertRCReturn(rc, rc);
816
817	uint16_t cIntCnt = HDA_REG(pThis, RINTCNT) & 0xff;
818
819	if (!cIntCnt) /* 0 means 256 interrupts. */
820	cIntCnt = HDA_MAX_RINTCNT;
821
822	Log3Func(("START CORB(RP:%x, WP:%x) RIRBWP:%x, RINTCNT:%RU8/%RU8\n",
823	corbRp, corbWp, rirbWp, pThis->u16RespIntCnt, cIntCnt));
824
825	while (corbRp != corbWp)
826	{
827	corbRp = (corbRp + 1) % (pThis->cbCorbBuf / HDA_CORB_ELEMENT_SIZE); /* Advance +1 as the first command(s) are at CORBWP + 1. */
828
829	uint32_t uCmd = pThis->pu32CorbBuf[corbRp];
830	uint64_t uResp = 0;
831
832	rc = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(uCmd, 0 /* Codec index */), &uResp);
833	if (RT_FAILURE(rc))
834	LogFunc(("Codec lookup failed with rc=%Rrc\n", rc));
835
836	Log3Func(("Codec verb %08x -> response %016lx\n", uCmd, uResp));
837
838	if ( (uResp & CODEC_RESPONSE_UNSOLICITED)
839	&& !(HDA_REG(pThis, GCTL) & HDA_GCTL_UNSOL))
840	{
841	LogFunc(("Unexpected unsolicited response.\n"));
842	HDA_REG(pThis, CORBRP) = corbRp;
843
844	/** @todo r=andy No CORB/RIRB syncing to guest required in that case? */
845	return rc;
846	}
847
848	rirbWp = (rirbWp + 1) % HDA_RIRB_SIZE;
849
850	pThis->pu64RirbBuf[rirbWp] = uResp;
851
852	pThis->u16RespIntCnt++;
853
854	bool fSendInterrupt = false;
855
856	if (pThis->u16RespIntCnt == cIntCnt) /* Response interrupt count reached? */
857	{
858	pThis->u16RespIntCnt = 0; /* Reset internal interrupt response counter. */
859
860	Log3Func(("Response interrupt count reached (%RU16)\n", pThis->u16RespIntCnt));
861	fSendInterrupt = true;
862
863	}
864	else if (corbRp == corbWp) /* Did we reach the end of the current command buffer? */
865	{
866	Log3Func(("Command buffer empty\n"));
867	fSendInterrupt = true;
868	}
869
870	if (fSendInterrupt)
871	{
872	if (HDA_REG(pThis, RIRBCTL) & HDA_RIRBCTL_RINTCTL) /* Response Interrupt Control (RINTCTL) enabled? */
873	{
874	HDA_REG(pThis, RIRBSTS) \|= HDA_RIRBSTS_RINTFL;
875
876	#ifndef DEBUG
877	rc = hdaProcessInterrupt(pThis);
878	#else
879	rc = hdaProcessInterrupt(pThis, __FUNCTION__);
880	#endif
881	}
882	}
883	}
884
885	Log3Func(("END CORB(RP:%x, WP:%x) RIRBWP:%x, RINTCNT:%RU8/%RU8\n",
886	corbRp, corbWp, rirbWp, pThis->u16RespIntCnt, cIntCnt));
887
888	HDA_REG(pThis, CORBRP) = corbRp;
889	HDA_REG(pThis, RIRBWP) = rirbWp;
890
891	rc = hdaCmdSync(pThis, false /* Sync to guest */);
892	AssertRCReturn(rc, rc);
893
894	if (RT_FAILURE(rc))
895	AssertRCReturn(rc, rc);
896
897	return rc;
898	}
899	#endif /* IN_RING3 */
900
901	/* Register access handlers. */
902
903	static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
904	{
905	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg);
906	*pu32Value = 0;
907	return VINF_SUCCESS;
908	}
909
910	static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
911	{
912	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
913	return VINF_SUCCESS;
914	}
915
916	/* U8 */
917	static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
918	{
919	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
920	return hdaRegReadU32(pThis, iReg, pu32Value);
921	}
922
923	static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
924	{
925	Assert((u32Value & 0xffffff00) == 0);
926	return hdaRegWriteU32(pThis, iReg, u32Value);
927	}
928
929	/* U16 */
930	static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
931	{
932	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
933	return hdaRegReadU32(pThis, iReg, pu32Value);
934	}
935
936	static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
937	{
938	Assert((u32Value & 0xffff0000) == 0);
939	return hdaRegWriteU32(pThis, iReg, u32Value);
940	}
941
942	/* U24 */
943	static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
944	{
945	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
946	return hdaRegReadU32(pThis, iReg, pu32Value);
947	}
948
949	#ifdef IN_RING3
950	static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
951	{
952	Assert((u32Value & 0xff000000) == 0);
953	return hdaRegWriteU32(pThis, iReg, u32Value);
954	}
955	#endif
956
957	/* U32 */
958	static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
959	{
960	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
961
962	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
963
964	*pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
965
966	DEVHDA_UNLOCK(pThis);
967	return VINF_SUCCESS;
968	}
969
970	static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
971	{
972	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
973
974	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
975
976	pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
977	\| (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
978	DEVHDA_UNLOCK(pThis);
979	return VINF_SUCCESS;
980	}
981
982	static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
983	{
984	RT_NOREF_PV(iReg);
985
986	if (u32Value & HDA_GCTL_CRST)
987	{
988	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
989
990	/* Set the CRST bit to indicate that we're leaving reset mode. */
991	HDA_REG(pThis, GCTL) \|= HDA_GCTL_CRST;
992	LogFunc(("Guest leaving HDA reset\n"));
993
994	DEVHDA_UNLOCK(pThis);
995	}
996	else
997	{
998	#ifdef IN_RING3
999	DEVHDA_LOCK(pThis);
1000
1001	/* Enter reset state. */
1002	LogFunc(("Guest entering HDA reset with DMA(RIRB:%s, CORB:%s)\n",
1003	HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA ? "on" : "off",
1004	HDA_REG(pThis, RIRBCTL) & HDA_RIRBCTL_RDMAEN ? "on" : "off"));
1005
1006	/* Clear the CRST bit to indicate that we're in reset state. */
1007	HDA_REG(pThis, GCTL) &= ~HDA_GCTL_CRST;
1008
1009	hdaGCTLReset(pThis);
1010
1011	DEVHDA_UNLOCK(pThis);
1012	#else
1013	return VINF_IOM_R3_MMIO_WRITE;
1014	#endif
1015	}
1016
1017	if (u32Value & HDA_GCTL_FCNTRL)
1018	{
1019	DEVHDA_LOCK(pThis);
1020
1021	/* Flush: GSTS:1 set, see 6.2.6. */
1022	HDA_REG(pThis, GSTS) \|= HDA_GSTS_FSTS; /* Set the flush status. */
1023	/* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
1024
1025	DEVHDA_UNLOCK(pThis);
1026	}
1027
1028	return VINF_SUCCESS;
1029	}
1030
1031	static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1032	{
1033	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1034
1035	uint32_t v = HDA_REG_IND(pThis, iReg);
1036	uint32_t nv = u32Value & HDA_STATESTS_SCSF_MASK;
1037
1038	HDA_REG(pThis, STATESTS) &= ~(v & nv); /* Write of 1 clears corresponding bit. */
1039
1040	DEVHDA_UNLOCK(pThis);
1041
1042	return VINF_SUCCESS;
1043	}
1044
1045	static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1046	{
1047	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
1048
1049	const uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
1050	uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, uSD);
1051	#ifdef LOG_ENABLED
1052	const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, uSD);
1053	LogFlowFunc(("[SD%RU8] LPIB=%RU32, CBL=%RU32\n", uSD, u32LPIB, u32CBL));
1054	#endif
1055
1056	*pu32Value = u32LPIB;
1057
1058	DEVHDA_UNLOCK(pThis);
1059	return VINF_SUCCESS;
1060	}
1061
1062	#ifdef IN_RING3
1063	/**
1064	* Returns the current maximum value the wall clock counter can be set to.
1065	* This maximum value depends on all currently handled HDA streams and their own current timing.
1066	*
1067	* @return Current maximum value the wall clock counter can be set to.
1068	* @param pThis HDA state.
1069	*
1070	* @remark Does not actually set the wall clock counter.
1071	*/
1072	uint64_t hdaWalClkGetMax(PHDASTATE pThis)
1073	{
1074	const uint64_t u64WalClkCur = ASMAtomicReadU64(&pThis->u64WalClk);
1075	const uint64_t u64FrontAbsWalClk = pThis->SinkFront.pStream
1076	? hdaStreamPeriodGetAbsElapsedWalClk(&pThis->SinkFront.pStream->State.Period) : 0;
1077	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1078	# error "Implement me!"
1079	#endif
1080	const uint64_t u64LineInAbsWalClk = pThis->SinkLineIn.pStream
1081	? hdaStreamPeriodGetAbsElapsedWalClk(&pThis->SinkLineIn.pStream->State.Period) : 0;
1082	#ifdef VBOX_WITH_HDA_MIC_IN
1083	const uint64_t u64MicInAbsWalClk = pThis->SinkMicIn.pStream
1084	? hdaStreamPeriodGetAbsElapsedWalClk(&pThis->SinkMicIn.pStream->State.Period) : 0;
1085	#endif
1086
1087	uint64_t u64WalClkNew = RT_MAX(u64WalClkCur, u64FrontAbsWalClk);
1088	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1089	# error "Implement me!"
1090	#endif
1091	u64WalClkNew = RT_MAX(u64WalClkNew, u64LineInAbsWalClk);
1092	#ifdef VBOX_WITH_HDA_MIC_IN
1093	u64WalClkNew = RT_MAX(u64WalClkNew, u64MicInAbsWalClk);
1094	#endif
1095
1096	Log3Func(("%RU64 -> Front=%RU64, LineIn=%RU64 -> %RU64\n",
1097	u64WalClkCur, u64FrontAbsWalClk, u64LineInAbsWalClk, u64WalClkNew));
1098
1099	return u64WalClkNew;
1100	}
1101	#endif /* IN_RING3 */
1102
1103	static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1104	{
1105	#ifdef IN_RING3
1106	RT_NOREF(iReg);
1107
1108	DEVHDA_LOCK(pThis);
1109
1110	*pu32Value = RT_LO_U32(ASMAtomicReadU64(&pThis->u64WalClk));
1111
1112	Log3Func(("%RU32 (max @ %RU64)\n",*pu32Value, hdaWalClkGetMax(pThis)));
1113
1114	DEVHDA_UNLOCK(pThis);
1115	return VINF_SUCCESS;
1116	#else
1117	RT_NOREF(pThis, iReg, pu32Value);
1118	return VINF_IOM_R3_MMIO_WRITE;
1119	#endif
1120	}
1121
1122	static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1123	{
1124	RT_NOREF(iReg);
1125
1126	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1127
1128	if (u32Value & HDA_CORBRP_RST)
1129	{
1130	/* Do a CORB reset. */
1131	if (pThis->cbCorbBuf)
1132	{
1133	Assert(pThis->pu32CorbBuf);
1134	RT_BZERO((void *)pThis->pu32CorbBuf, pThis->cbCorbBuf);
1135	}
1136
1137	LogRel2(("HDA: CORB reset\n"));
1138
1139	HDA_REG(pThis, CORBRP) = HDA_CORBRP_RST; /* Clears the pointer. */
1140	}
1141	else
1142	HDA_REG(pThis, CORBRP) &= ~HDA_CORBRP_RST; /* Only CORBRP_RST bit is writable. */
1143
1144	DEVHDA_UNLOCK(pThis);
1145	return VINF_SUCCESS;
1146	}
1147
1148	static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1149	{
1150	#ifdef IN_RING3
1151	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1152
1153	int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1154	AssertRC(rc);
1155
1156	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Start DMA engine. */
1157	{
1158	rc = hdaCORBCmdProcess(pThis);
1159	}
1160	else
1161	LogFunc(("CORB DMA not running, skipping\n"));
1162
1163	DEVHDA_UNLOCK(pThis);
1164	return rc;
1165	#else
1166	RT_NOREF(pThis, iReg, u32Value);
1167	return VINF_IOM_R3_MMIO_WRITE;
1168	#endif
1169	}
1170
1171	static int hdaRegWriteCORBSIZE(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1172	{
1173	#ifdef IN_RING3
1174	RT_NOREF(iReg);
1175
1176	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1177
1178	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
1179	{
1180	LogFunc(("CORB DMA is (still) running, skipping\n"));
1181
1182	DEVHDA_UNLOCK(pThis);
1183	return VINF_SUCCESS;
1184	}
1185
1186	u32Value = (u32Value & HDA_CORBSIZE_SZ);
1187
1188	uint16_t cEntries = HDA_CORB_SIZE; /* Set default. */
1189
1190	switch (u32Value)
1191	{
1192	case 0: /* 8 byte; 2 entries. */
1193	cEntries = 2;
1194	break;
1195
1196	case 1: /* 64 byte; 16 entries. */
1197	cEntries = 16;
1198	break;
1199
1200	case 2: /* 1 KB; 256 entries. */
1201	/* Use default size. */
1202	break;
1203
1204	default:
1205	LogRel(("HDA: Guest tried to set an invalid CORB size (0x%x), keeping default\n", u32Value));
1206	u32Value = 2;
1207	/* Use default size. */
1208	break;
1209	}
1210
1211	uint32_t cbCorbBuf = cEntries * sizeof(uint32_t);
1212
1213	if (cbCorbBuf != pThis->cbCorbBuf)
1214	{
1215	if (pThis->pu32CorbBuf)
1216	{
1217	RTMemFree(pThis->pu32CorbBuf);
1218	pThis->pu32CorbBuf = NULL;
1219	}
1220
1221	if (cbCorbBuf)
1222	{
1223	Assert(cbCorbBuf % sizeof(uint32_t) == 0);
1224
1225	pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(cbCorbBuf);
1226	pThis->cbCorbBuf = cbCorbBuf;
1227	}
1228	}
1229
1230	LogFunc(("CORB buffer size is now %RU32 bytes (%u entries)\n", pThis->cbCorbBuf, pThis->cbCorbBuf / HDA_CORB_ELEMENT_SIZE));
1231
1232	HDA_REG(pThis, CORBSIZE) = u32Value;
1233
1234	DEVHDA_UNLOCK(pThis);
1235	return VINF_SUCCESS;
1236	#else
1237	RT_NOREF(pThis, iReg, u32Value);
1238	return VINF_IOM_R3_MMIO_WRITE;
1239	#endif
1240	}
1241
1242	static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1243	{
1244	RT_NOREF_PV(iReg);
1245
1246	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1247
1248	uint32_t v = HDA_REG(pThis, CORBSTS);
1249	HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1250
1251	DEVHDA_UNLOCK(pThis);
1252	return VINF_SUCCESS;
1253	}
1254
1255	static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1256	{
1257	#ifdef IN_RING3
1258	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1259
1260	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
1261	if (RT_FAILURE(rc))
1262	AssertRCReturn(rc, rc);
1263
1264	rc = hdaCORBCmdProcess(pThis);
1265
1266	DEVHDA_UNLOCK(pThis);
1267	return rc;
1268	#else
1269	RT_NOREF(pThis, iReg, u32Value);
1270	return VINF_IOM_R3_MMIO_WRITE;
1271	#endif
1272	}
1273
1274	static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1275	{
1276	#ifdef IN_RING3
1277	DEVHDA_LOCK(pThis);
1278
1279	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, CBL, iReg));
1280	if (!pStream)
1281	{
1282	LogFunc(("[SD%RU8] Warning: Changing SDCBL on non-attached stream (0x%x)\n",
1283	HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
1284
1285	DEVHDA_UNLOCK(pThis);
1286	return hdaRegWriteU32(pThis, iReg, u32Value);
1287	}
1288
1289	pStream->u32CBL = u32Value;
1290
1291	LogFlowFunc(("[SD%RU8] CBL=%RU32\n", pStream->u8SD, u32Value));
1292
1293	DEVHDA_UNLOCK(pThis);
1294
1295	int rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
1296	AssertRC(rc2);
1297
1298	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1299	#else /* !IN_RING3 */
1300	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
1301	return VINF_IOM_R3_MMIO_WRITE;
1302	#endif /* IN_RING3 */
1303	}
1304
1305	static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1306	{
1307	#ifdef IN_RING3
1308	DEVHDA_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1309
1310	/*
1311	* Some guests write too much (that is, 32-bit with the top 8 bit being junk)
1312	* instead of 24-bit required for SDCTL. So just mask this here to be safe.
1313	*/
1314	u32Value = (u32Value & 0x00ffffff);
1315
1316	bool fRun = RT_BOOL(u32Value & HDA_SDCTL_RUN);
1317	bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_SDCTL_RUN);
1318
1319	bool fReset = RT_BOOL(u32Value & HDA_SDCTL_SRST);
1320	bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_SDCTL_SRST);
1321
1322	/* Get the stream descriptor. */
1323	uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
1324
1325	LogFunc(("[SD%RU8] fRun=%RTbool, fInRun=%RTbool, fReset=%RTbool, fInReset=%RTbool, %R[sdctl]\n",
1326	uSD, fRun, fInRun, fReset, fInReset, u32Value));
1327
1328	/*
1329	* Extract the stream tag the guest wants to use for this specific
1330	* stream descriptor (SDn). This only can happen if the stream is in a non-running
1331	* state, so we're doing the lookup and assignment here.
1332	*
1333	* So depending on the guest OS, SD3 can use stream tag 4, for example.
1334	*/
1335	uint8_t uTag = (u32Value >> HDA_SDCTL_NUM_SHIFT) & HDA_SDCTL_NUM_MASK;
1336	if (uTag > HDA_MAX_TAGS)
1337	{
1338	LogFunc(("[SD%RU8] Warning: Invalid stream tag %RU8 specified!\n", uSD, uTag));
1339
1340	DEVHDA_UNLOCK_BOTH(pThis);
1341	return hdaRegWriteU24(pThis, iReg, u32Value);
1342	}
1343
1344	PHDATAG pTag = &pThis->aTags[uTag];
1345	AssertPtr(pTag);
1346
1347	LogFunc(("[SD%RU8] Using stream tag=%RU8\n", uSD, uTag));
1348
1349	/* Assign new values. */
1350	pTag->uTag = uTag;
1351	pTag->pStream = hdaGetStreamFromSD(pThis, uSD);
1352
1353	PHDASTREAM pStream = pTag->pStream;
1354	AssertPtr(pStream);
1355
1356	if (fInReset)
1357	{
1358	Assert(!fReset);
1359	Assert(!fInRun && !fRun);
1360
1361	/* Exit reset state. */
1362	ASMAtomicXchgBool(&pStream->State.fInReset, false);
1363
1364	/* Report that we're done resetting this stream by clearing SRST. */
1365	HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_SRST;
1366
1367	LogFunc(("[SD%RU8] Reset exit\n", uSD));
1368	}
1369	else if (fReset)
1370	{
1371	/* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
1372	Assert(!fInRun && !fRun);
1373
1374	LogFunc(("[SD%RU8] Reset enter\n", uSD));
1375
1376	hdaStreamLock(pStream);
1377
1378	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1379	hdaStreamAsyncIOLock(pStream);
1380	hdaStreamAsyncIOEnable(pStream, false /* fEnable */);
1381	# endif
1382	/* Make sure to remove the run bit before doing the actual stream reset. */
1383	HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_RUN;
1384
1385	hdaStreamReset(pThis, pStream, pStream->u8SD);
1386
1387	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1388	hdaStreamAsyncIOUnlock(pStream);
1389	# endif
1390	hdaStreamUnlock(pStream);
1391	}
1392	else
1393	{
1394	/*
1395	* We enter here to change DMA states only.
1396	*/
1397	if (fInRun != fRun)
1398	{
1399	Assert(!fReset && !fInReset);
1400	LogFunc(("[SD%RU8] State changed (fRun=%RTbool)\n", uSD, fRun));
1401
1402	hdaStreamLock(pStream);
1403
1404	int rc2;
1405
1406	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1407	if (fRun)
1408	rc2 = hdaStreamAsyncIOCreate(pStream);
1409
1410	hdaStreamAsyncIOLock(pStream);
1411	# endif
1412	if (fRun)
1413	{
1414	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1415	hdaStreamAsyncIOEnable(pStream, fRun /* fEnable */);
1416	# endif
1417	/* (Re-)initialize the stream with current values. */
1418	rc2 = hdaStreamInit(pStream, pStream->u8SD);
1419	AssertRC(rc2);
1420
1421	/* Remove the old stream from the device setup. */
1422	hdaRemoveStream(pThis, &pStream->State.Cfg);
1423
1424	/* Add the stream to the device setup. */
1425	rc2 = hdaAddStream(pThis, &pStream->State.Cfg);
1426	AssertRC(rc2);
1427	}
1428
1429	/* Enable/disable the stream. */
1430	rc2 = hdaStreamEnable(pStream, fRun /* fEnable */);
1431	AssertRC(rc2);
1432
1433	if (fRun)
1434	{
1435	/* Keep track of running streams. */
1436	pThis->cStreamsActive++;
1437
1438	/* (Re-)init the stream's period. */
1439	hdaStreamPeriodInit(&pStream->State.Period,
1440	pStream->u8SD, pStream->u16LVI, pStream->u32CBL, &pStream->State.Cfg);
1441
1442	/* Begin a new period for this stream. */
1443	rc2 = hdaStreamPeriodBegin(&pStream->State.Period, hdaWalClkGetCurrent(pThis)/* Use current wall clock time */);
1444	AssertRC(rc2);
1445
1446	rc2 = hdaTimerSet(pThis, TMTimerGet(pThis->pTimer) + pStream->State.cTransferTicks, false /* fForce */);
1447	AssertRC(rc2);
1448	}
1449	else
1450	{
1451	/* Keep track of running streams. */
1452	Assert(pThis->cStreamsActive);
1453	if (pThis->cStreamsActive)
1454	pThis->cStreamsActive--;
1455
1456	/* Make sure to (re-)schedule outstanding (delayed) interrupts. */
1457	hdaReschedulePendingInterrupts(pThis);
1458
1459	/* Reset the period. */
1460	hdaStreamPeriodReset(&pStream->State.Period);
1461	}
1462
1463	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1464	hdaStreamAsyncIOUnlock(pStream);
1465	# endif
1466	/* Make sure to leave the lock before (eventually) starting the timer. */
1467	hdaStreamUnlock(pStream);
1468	}
1469	}
1470
1471	int rc2 = hdaRegWriteU24(pThis, iReg, u32Value);
1472	AssertRC(rc2);
1473
1474	DEVHDA_UNLOCK_BOTH(pThis);
1475
1476	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1477	#else /* !IN_RING3 */
1478	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
1479	return VINF_IOM_R3_MMIO_WRITE;
1480	#endif /* IN_RING3 */
1481	}
1482
1483	static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1484	{
1485	#ifdef IN_RING3
1486	DEVHDA_LOCK_BOTH_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1487
1488	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, STS, iReg));
1489	if (!pStream)
1490	{
1491	AssertMsgFailed(("[SD%RU8] Warning: Writing SDSTS on non-attached stream (0x%x)\n",
1492	HDA_SD_NUM_FROM_REG(pThis, STS, iReg), u32Value));
1493
1494	DEVHDA_UNLOCK_BOTH(pThis);
1495	return hdaRegWriteU16(pThis, iReg, u32Value);
1496	}
1497
1498	hdaStreamLock(pStream);
1499
1500	uint32_t v = HDA_REG_IND(pThis, iReg);
1501
1502	/* Clear (zero) FIFOE, DESE and BCIS bits when writing 1 to it (6.2.33). */
1503	HDA_REG_IND(pThis, iReg) &= ~(u32Value & v);
1504
1505	/* Some guests tend to write SDnSTS even if the stream is not running.
1506	* So make sure to check if the RUN bit is set first. */
1507	const bool fRunning = pStream->State.fRunning;
1508
1509	Log3Func(("[SD%RU8] fRunning=%RTbool %R[sdsts]\n", pStream->u8SD, fRunning, v));
1510
1511	PHDASTREAMPERIOD pPeriod = &pStream->State.Period;
1512
1513	if (hdaStreamPeriodLock(pPeriod))
1514	{
1515	const bool fNeedsInterrupt = hdaStreamPeriodNeedsInterrupt(pPeriod);
1516	if (fNeedsInterrupt)
1517	hdaStreamPeriodReleaseInterrupt(pPeriod);
1518
1519	if (hdaStreamPeriodIsComplete(pPeriod))
1520	{
1521	/* Make sure to try to update the WALCLK register if a period is complete.
1522	* Use the maximum WALCLK value all (active) streams agree to. */
1523	const uint64_t uWalClkMax = hdaWalClkGetMax(pThis);
1524	if (uWalClkMax > hdaWalClkGetCurrent(pThis))
1525	hdaWalClkSet(pThis, uWalClkMax, false /* fForce */);
1526
1527	hdaStreamPeriodEnd(pPeriod);
1528
1529	if (fRunning)
1530	hdaStreamPeriodBegin(pPeriod, hdaWalClkGetCurrent(pThis) /* Use current wall clock time */);
1531	}
1532
1533	hdaStreamPeriodUnlock(pPeriod); /* Unlock before processing interrupt. */
1534	}
1535
1536	#ifndef DEBUG
1537	hdaProcessInterrupt(pThis);
1538	#else
1539	hdaProcessInterrupt(pThis, __FUNCTION__);
1540	#endif
1541
1542	const uint64_t tsNow = TMTimerGet(pThis->pTimer);
1543	Assert(tsNow >= pStream->State.tsTransferLast);
1544
1545	const uint64_t cTicksElapsed = tsNow - pStream->State.tsTransferLast;
1546	#ifdef LOG_ENABLED
1547	const uint64_t cTicksTransferred = pStream->State.cbTransferProcessed * pStream->State.cTicksPerByte;
1548	#endif
1549
1550	uint64_t cTicksToNext = pStream->State.cTransferTicks;
1551	if (cTicksToNext) /* Only do any calculations if the stream currently is set up for transfers. */
1552	{
1553	Log3Func(("[SD%RU8] cTicksElapsed=%RU64, cTicksTransferred=%RU64, cTicksToNext=%RU64\n",
1554	pStream->u8SD, cTicksElapsed, cTicksTransferred, cTicksToNext));
1555
1556	Log3Func(("[SD%RU8] cbTransferProcessed=%RU32, cbTransferChunk=%RU32, cbTransferSize=%RU32\n",
1557	pStream->u8SD, pStream->State.cbTransferProcessed, pStream->State.cbTransferChunk, pStream->State.cbTransferSize));
1558
1559	if (cTicksElapsed <= cTicksToNext)
1560	{
1561	cTicksToNext = cTicksToNext - cTicksElapsed;
1562	}
1563	else /* Catch up. */
1564	{
1565	Log3Func(("[SD%RU8] Warning: Lagging behind (%RU64 ticks elapsed, maximum allowed is %RU64)\n",
1566	pStream->u8SD, cTicksElapsed, cTicksToNext));
1567
1568	LogRelMax2(64, ("HDA: Stream #%RU8 interrupt lagging behind (expected %uus, got %uus), trying to catch up ...\n",
1569	pStream->u8SD,
1570	(TMTimerGetFreq(pThis->pTimer) / pThis->u16TimerHz) / 1000, (tsNow - pStream->State.tsTransferLast) / 1000));
1571
1572	cTicksToNext = 0;
1573	}
1574
1575	Log3Func(("[SD%RU8] -> cTicksToNext=%RU64\n", pStream->u8SD, cTicksToNext));
1576
1577	/* Reset processed data counter. */
1578	pStream->State.cbTransferProcessed = 0;
1579	pStream->State.tsTransferNext = tsNow + cTicksToNext;
1580
1581	/* Only re-arm the timer if there were pending transfer interrupts left
1582	* -- it could happen that we land in here if a guest writes to SDnSTS
1583	* unconditionally. */
1584	if (pStream->State.cTransferPendingInterrupts)
1585	{
1586	pStream->State.cTransferPendingInterrupts--;
1587
1588	/* Re-arm the timer. */
1589	hdaTimerSet(pThis, tsNow + cTicksToNext, false /* fForce */);
1590	}
1591	}
1592
1593	hdaStreamUnlock(pStream);
1594
1595	DEVHDA_UNLOCK_BOTH(pThis);
1596	return VINF_SUCCESS;
1597	#else /* IN_RING3 */
1598	RT_NOREF(pThis, iReg, u32Value);
1599	return VINF_IOM_R3_MMIO_WRITE;
1600	#endif /* !IN_RING3 */
1601	}
1602
1603	static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1604	{
1605	#ifdef IN_RING3
1606	DEVHDA_LOCK(pThis);
1607
1608	if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
1609	{
1610	DEVHDA_UNLOCK(pThis);
1611	return VINF_SUCCESS;
1612	}
1613
1614	uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, LVI, iReg);
1615
1616	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
1617	if (!pStream)
1618	{
1619	AssertMsgFailed(("[SD%RU8] Warning: Changing SDLVI on non-attached stream (0x%x)\n", uSD, u32Value));
1620
1621	DEVHDA_UNLOCK(pThis);
1622	return hdaRegWriteU16(pThis, iReg, u32Value);
1623	}
1624
1625	/** @todo Validate LVI. */
1626	pStream->u16LVI = u32Value;
1627	LogFunc(("[SD%RU8] Updating LVI to %RU16\n", uSD, pStream->u16LVI));
1628
1629	# ifdef HDA_USE_DMA_ACCESS_HANDLER
1630	if (hdaGetDirFromSD(uSD) == PDMAUDIODIR_OUT)
1631	{
1632	/* Try registering the DMA handlers.
1633	* As we can't be sure in which order LVI + BDL base are set, try registering in both routines. */
1634	if (hdaStreamRegisterDMAHandlers(pThis, pStream))
1635	LogFunc(("[SD%RU8] DMA logging enabled\n", pStream->u8SD));
1636	}
1637	# endif
1638
1639	DEVHDA_UNLOCK(pThis);
1640
1641	int rc2 = hdaRegWriteU16(pThis, iReg, u32Value);
1642	AssertRC(rc2);
1643
1644	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1645	#else /* !IN_RING3 */
1646	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
1647	return VINF_IOM_R3_MMIO_WRITE;
1648	#endif /* IN_RING3 */
1649	}
1650
1651	static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1652	{
1653	#ifdef IN_RING3
1654	DEVHDA_LOCK(pThis);
1655
1656	uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg);
1657
1658	if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_IN) /* FIFOW for input streams only. */
1659	{
1660	LogRel(("HDA: Warning: Guest tried to write read-only FIFOW to output stream #%RU8, ignoring\n", uSD));
1661
1662	DEVHDA_UNLOCK(pThis);
1663	return VINF_SUCCESS;
1664	}
1665
1666	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg));
1667	if (!pStream)
1668	{
1669	AssertMsgFailed(("[SD%RU8] Warning: Changing FIFOW on non-attached stream (0x%x)\n", uSD, u32Value));
1670
1671	DEVHDA_UNLOCK(pThis);
1672	return hdaRegWriteU16(pThis, iReg, u32Value);
1673	}
1674
1675	uint32_t u32FIFOW = 0;
1676
1677	switch (u32Value)
1678	{
1679	case HDA_SDFIFOW_8B:
1680	case HDA_SDFIFOW_16B:
1681	case HDA_SDFIFOW_32B:
1682	u32FIFOW = u32Value;
1683	break;
1684	default:
1685	LogRel(("HDA: Warning: Guest tried write unsupported FIFOW (0x%x) to stream #%RU8, defaulting to 32 bytes\n",
1686	u32Value, uSD));
1687	AssertFailed();
1688	u32FIFOW = HDA_SDFIFOW_32B;
1689	break;
1690	}
1691
1692	if (u32FIFOW)
1693	{
1694	pStream->u16FIFOW = hdaSDFIFOWToBytes(u32FIFOW);
1695	LogFunc(("[SD%RU8] Updating FIFOW to %RU32 bytes\n", uSD, pStream->u16FIFOW));
1696
1697	DEVHDA_UNLOCK(pThis);
1698
1699	int rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOW);
1700	AssertRC(rc2);
1701	}
1702
1703	DEVHDA_UNLOCK(pThis);
1704	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1705	#else /* !IN_RING3 */
1706	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
1707	return VINF_IOM_R3_MMIO_WRITE;
1708	#endif /* IN_RING3 */
1709	}
1710
1711	/**
1712	* @note This method could be called for changing value on Output Streams only (ICH6 datasheet 18.2.39).
1713	*/
1714	static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1715	{
1716	#ifdef IN_RING3
1717	DEVHDA_LOCK(pThis);
1718
1719	uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOS, iReg);
1720
1721	if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_OUT) /* FIFOS for output streams only. */
1722	{
1723	LogRel(("HDA: Warning: Guest tried to write read-only FIFOS to input stream #%RU8, ignoring\n", uSD));
1724
1725	DEVHDA_UNLOCK(pThis);
1726	return VINF_SUCCESS;
1727	}
1728
1729	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
1730	if (!pStream)
1731	{
1732	AssertMsgFailed(("[SD%RU8] Warning: Changing FIFOS on non-attached stream (0x%x)\n", uSD, u32Value));
1733
1734	DEVHDA_UNLOCK(pThis);
1735	return hdaRegWriteU16(pThis, iReg, u32Value);
1736	}
1737
1738	uint32_t u32FIFOS = 0;
1739
1740	switch(u32Value)
1741	{
1742	case HDA_SDOFIFO_16B:
1743	case HDA_SDOFIFO_32B:
1744	case HDA_SDOFIFO_64B:
1745	case HDA_SDOFIFO_128B:
1746	case HDA_SDOFIFO_192B:
1747	case HDA_SDOFIFO_256B:
1748	u32FIFOS = u32Value;
1749	break;
1750
1751	default:
1752	LogRel(("HDA: Warning: Guest tried write unsupported FIFOS (0x%x) to stream #%RU8, defaulting to 192 bytes\n",
1753	u32Value, uSD));
1754	AssertFailed();
1755	u32FIFOS = HDA_SDOFIFO_192B;
1756	break;
1757	}
1758
1759	if (u32FIFOS)
1760	{
1761	pStream->u16FIFOS = u32FIFOS + 1;
1762	LogFunc(("[SD%RU8] Updating FIFOS to %RU32 bytes\n", uSD, pStream->u16FIFOS));
1763
1764	DEVHDA_UNLOCK(pThis);
1765
1766	int rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOS);
1767	AssertRC(rc2);
1768	}
1769	else
1770	DEVHDA_UNLOCK(pThis);
1771
1772	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1773	#else /* !IN_RING3 */
1774	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
1775	return VINF_IOM_R3_MMIO_WRITE;
1776	#endif /* IN_RING3 */
1777	}
1778
1779	#ifdef IN_RING3
1780	/**
1781	* Adds an audio output stream to the device setup using the given configuration.
1782	*
1783	* @returns IPRT status code.
1784	* @param pThis Device state.
1785	* @param pCfg Stream configuration to use for adding a stream.
1786	*/
1787	static int hdaAddStreamOut(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1788	{
1789	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1790	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1791
1792	AssertReturn(pCfg->enmDir == PDMAUDIODIR_OUT, VERR_INVALID_PARAMETER);
1793
1794	LogFlowFunc(("Stream=%s\n", pCfg->szName));
1795
1796	int rc = VINF_SUCCESS;
1797
1798	bool fUseFront = true; /* Always use front out by default. */
1799	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1800	bool fUseRear;
1801	bool fUseCenter;
1802	bool fUseLFE;
1803
1804	fUseRear = fUseCenter = fUseLFE = false;
1805
1806	/*
1807	* Use commonly used setups for speaker configurations.
1808	*/
1809
1810	/** @todo Make the following configurable through mixer API and/or CFGM? */
1811	switch (pCfg->Props.cChannels)
1812	{
1813	case 3: /* 2.1: Front (Stereo) + LFE. */
1814	{
1815	fUseLFE = true;
1816	break;
1817	}
1818
1819	case 4: /* Quadrophonic: Front (Stereo) + Rear (Stereo). */
1820	{
1821	fUseRear = true;
1822	break;
1823	}
1824
1825	case 5: /* 4.1: Front (Stereo) + Rear (Stereo) + LFE. */
1826	{
1827	fUseRear = true;
1828	fUseLFE = true;
1829	break;
1830	}
1831
1832	case 6: /* 5.1: Front (Stereo) + Rear (Stereo) + Center/LFE. */
1833	{
1834	fUseRear = true;
1835	fUseCenter = true;
1836	fUseLFE = true;
1837	break;
1838	}
1839
1840	default: /* Unknown; fall back to 2 front channels (stereo). */
1841	{
1842	rc = VERR_NOT_SUPPORTED;
1843	break;
1844	}
1845	}
1846	#else /* !VBOX_WITH_AUDIO_HDA_51_SURROUND */
1847	/* Only support mono or stereo channels. */
1848	if ( pCfg->Props.cChannels != 1 /* Mono */
1849	&& pCfg->Props.cChannels != 2 /* Stereo */)
1850	{
1851	rc = VERR_NOT_SUPPORTED;
1852	}
1853	#endif
1854
1855	if (rc == VERR_NOT_SUPPORTED)
1856	{
1857	LogRel2(("HDA: Warning: Unsupported channel count (%RU8), falling back to stereo channels (2)\n", pCfg->Props.cChannels));
1858
1859	/* Fall back to 2 channels (see below in fUseFront block). */
1860	rc = VINF_SUCCESS;
1861	}
1862
1863	do
1864	{
1865	if (RT_FAILURE(rc))
1866	break;
1867
1868	if (fUseFront)
1869	{
1870	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Front");
1871
1872	pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_FRONT;
1873	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1874
1875	pCfg->Props.cChannels = 2;
1876	pCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pCfg->Props.cBits, pCfg->Props.cChannels);
1877
1878	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT, pCfg);
1879	}
1880
1881	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1882	if ( RT_SUCCESS(rc)
1883	&& (fUseCenter \|\| fUseLFE))
1884	{
1885	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Center/LFE");
1886
1887	pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_CENTER_LFE;
1888	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1889
1890	pCfg->Props.cChannels = (fUseCenter && fUseLFE) ? 2 : 1;
1891	pCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pCfg->Props.cBits, pCfg->Props.cChannels);
1892
1893	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE, pCfg);
1894	}
1895
1896	if ( RT_SUCCESS(rc)
1897	&& fUseRear)
1898	{
1899	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Rear");
1900
1901	pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_REAR;
1902	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1903
1904	pCfg->Props.cChannels = 2;
1905	pCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pCfg->Props.cBits, pCfg->Props.cChannels);
1906
1907	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR, pCfg);
1908	}
1909	#endif /* VBOX_WITH_AUDIO_HDA_51_SURROUND */
1910
1911	} while (0);
1912
1913	LogFlowFuncLeaveRC(rc);
1914	return rc;
1915	}
1916
1917	/**
1918	* Adds an audio input stream to the device setup using the given configuration.
1919	*
1920	* @returns IPRT status code.
1921	* @param pThis Device state.
1922	* @param pCfg Stream configuration to use for adding a stream.
1923	*/
1924	static int hdaAddStreamIn(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1925	{
1926	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1927	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1928
1929	AssertReturn(pCfg->enmDir == PDMAUDIODIR_IN, VERR_INVALID_PARAMETER);
1930
1931	LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Source));
1932
1933	int rc;
1934
1935	switch (pCfg->DestSource.Source)
1936	{
1937	case PDMAUDIORECSOURCE_LINE:
1938	{
1939	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN, pCfg);
1940	break;
1941	}
1942	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
1943	case PDMAUDIORECSOURCE_MIC:
1944	{
1945	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN, pCfg);
1946	break;
1947	}
1948	#endif
1949	default:
1950	rc = VERR_NOT_SUPPORTED;
1951	break;
1952	}
1953
1954	LogFlowFuncLeaveRC(rc);
1955	return rc;
1956	}
1957
1958	/**
1959	* Adds an audio stream to the device setup using the given configuration.
1960	*
1961	* @returns IPRT status code.
1962	* @param pThis Device state.
1963	* @param pCfg Stream configuration to use for adding a stream.
1964	*/
1965	static int hdaAddStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1966	{
1967	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1968	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1969
1970	int rc;
1971
1972	LogFlowFuncEnter();
1973
1974	switch (pCfg->enmDir)
1975	{
1976	case PDMAUDIODIR_OUT:
1977	rc = hdaAddStreamOut(pThis, pCfg);
1978	break;
1979
1980	case PDMAUDIODIR_IN:
1981	rc = hdaAddStreamIn(pThis, pCfg);
1982	break;
1983
1984	default:
1985	rc = VERR_NOT_SUPPORTED;
1986	AssertFailed();
1987	break;
1988	}
1989
1990	LogFlowFunc(("Returning %Rrc\n", rc));
1991
1992	return rc;
1993	}
1994
1995	/**
1996	* Removes an audio stream from the device setup using the given configuration.
1997	*
1998	* @returns IPRT status code.
1999	* @param pThis Device state.
2000	* @param pCfg Stream configuration to use for removing a stream.
2001	*/
2002	static int hdaRemoveStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
2003	{
2004	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2005	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2006
2007	int rc = VINF_SUCCESS;
2008
2009	PDMAUDIOMIXERCTL enmMixerCtl = PDMAUDIOMIXERCTL_UNKNOWN;
2010	switch (pCfg->enmDir)
2011	{
2012	case PDMAUDIODIR_IN:
2013	{
2014	LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Source));
2015
2016	switch (pCfg->DestSource.Source)
2017	{
2018	case PDMAUDIORECSOURCE_LINE: enmMixerCtl = PDMAUDIOMIXERCTL_LINE_IN; break;
2019	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2020	case PDMAUDIORECSOURCE_MIC: enmMixerCtl = PDMAUDIOMIXERCTL_MIC_IN; break;
2021	#endif
2022	default:
2023	rc = VERR_NOT_SUPPORTED;
2024	break;
2025	}
2026
2027	break;
2028	}
2029
2030	case PDMAUDIODIR_OUT:
2031	{
2032	LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Dest));
2033
2034	switch (pCfg->DestSource.Dest)
2035	{
2036	case PDMAUDIOPLAYBACKDEST_FRONT: enmMixerCtl = PDMAUDIOMIXERCTL_FRONT; break;
2037	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2038	case PDMAUDIOPLAYBACKDEST_CENTER_LFE: enmMixerCtl = PDMAUDIOMIXERCTL_CENTER_LFE; break;
2039	case PDMAUDIOPLAYBACKDEST_REAR: enmMixerCtl = PDMAUDIOMIXERCTL_REAR; break;
2040	#endif
2041	default:
2042	rc = VERR_NOT_SUPPORTED;
2043	break;
2044	}
2045	break;
2046	}
2047
2048	default:
2049	rc = VERR_NOT_SUPPORTED;
2050	break;
2051	}
2052
2053	if (RT_SUCCESS(rc))
2054	rc = hdaCodecRemoveStream(pThis->pCodec, enmMixerCtl);
2055
2056	LogFlowFuncLeaveRC(rc);
2057	return rc;
2058	}
2059	#endif /* IN_RING3 */
2060
2061	static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2062	{
2063	#ifdef IN_RING3
2064	DEVHDA_LOCK(pThis);
2065
2066	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FMT, iReg));
2067	if (!pStream)
2068	{
2069	LogFunc(("[SD%RU8] Warning: Changing SDFMT on non-attached stream (0x%x)\n",
2070	HDA_SD_NUM_FROM_REG(pThis, FMT, iReg), u32Value));
2071	return hdaRegWriteU16(pThis, iReg, u32Value);
2072	}
2073
2074	/* Write the wanted stream format into the register in any case.
2075	*
2076	* This is important for e.g. MacOS guests, as those try to initialize streams which are not reported
2077	* by the device emulation (wants 4 channels, only have 2 channels at the moment).
2078	*
2079	* When ignoring those (invalid) formats, this leads to MacOS thinking that the device is malfunctioning
2080	* and therefore disabling the device completely. */
2081	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
2082	AssertRC(rc);
2083
2084	DEVHDA_UNLOCK(pThis);
2085	return VINF_SUCCESS; /* Never return failure. */
2086	#else /* !IN_RING3 */
2087	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
2088	return VINF_IOM_R3_MMIO_WRITE;
2089	#endif
2090	}
2091
2092	/* Note: Will be called for both, BDPL and BDPU, registers. */
2093	DECLINLINE(int) hdaRegWriteSDBDPX(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value, uint8_t uSD)
2094	{
2095	#ifdef IN_RING3
2096	int rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2097	AssertRC(rc2);
2098
2099	DEVHDA_LOCK(pThis);
2100
2101	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
2102	if (!pStream)
2103	{
2104	DEVHDA_UNLOCK(pThis);
2105	return VINF_SUCCESS;
2106	}
2107
2108	/* Update BDL base. */
2109	pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, uSD),
2110	HDA_STREAM_REG(pThis, BDPU, uSD));
2111
2112	# ifdef HDA_USE_DMA_ACCESS_HANDLER
2113	if (hdaGetDirFromSD(uSD) == PDMAUDIODIR_OUT)
2114	{
2115	/* Try registering the DMA handlers.
2116	* As we can't be sure in which order LVI + BDL base are set, try registering in both routines. */
2117	if (hdaStreamRegisterDMAHandlers(pThis, pStream))
2118	LogFunc(("[SD%RU8] DMA logging enabled\n", pStream->u8SD));
2119	}
2120	# endif
2121
2122	LogFlowFunc(("[SD%RU8] BDLBase=0x%x\n", pStream->u8SD, pStream->u64BDLBase));
2123
2124	DEVHDA_UNLOCK(pThis);
2125
2126	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2127	#else /* !IN_RING3 */
2128	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value); RT_NOREF_PV(uSD);
2129	return VINF_IOM_R3_MMIO_WRITE;
2130	#endif /* IN_RING3 */
2131	}
2132
2133	static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2134	{
2135	return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPL, iReg));
2136	}
2137
2138	static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2139	{
2140	return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPU, iReg));
2141	}
2142
2143	static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2144	{
2145	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
2146
2147	/* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
2148	if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2149	\|\| (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA))
2150	{
2151	HDA_REG(pThis, IRS) = HDA_IRS_ICB; /* busy */
2152	}
2153
2154	DEVHDA_UNLOCK(pThis);
2155
2156	return hdaRegReadU32(pThis, iReg, pu32Value);
2157	}
2158
2159	static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2160	{
2161	RT_NOREF_PV(iReg);
2162
2163	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2164
2165	/*
2166	* If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
2167	* write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
2168	*/
2169	if ( (u32Value & HDA_IRS_ICB)
2170	&& !(HDA_REG(pThis, IRS) & HDA_IRS_ICB))
2171	{
2172	#ifdef IN_RING3
2173	uint32_t uCmd = HDA_REG(pThis, IC);
2174
2175	if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
2176	{
2177	DEVHDA_UNLOCK(pThis);
2178
2179	/*
2180	* 3.4.3: Defines behavior of immediate Command status register.
2181	*/
2182	LogRel(("HDA: Guest attempted process immediate verb (%x) with active CORB\n", uCmd));
2183	return VINF_SUCCESS;
2184	}
2185
2186	HDA_REG(pThis, IRS) = HDA_IRS_ICB; /* busy */
2187
2188	uint64_t uResp;
2189	int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec,
2190	HDA_CODEC_CMD(uCmd, 0 /* LUN */), &uResp);
2191	if (RT_FAILURE(rc2))
2192	LogFunc(("Codec lookup failed with rc2=%Rrc\n", rc2));
2193
2194	HDA_REG(pThis, IR) = (uint32_t)uResp; /** @todo r=andy Do we need a 64-bit response? */
2195	HDA_REG(pThis, IRS) = HDA_IRS_IRV; /* result is ready */
2196	/** @todo r=michaln We just set the IRS value, why are we clearing unset bits? */
2197	HDA_REG(pThis, IRS) &= ~HDA_IRS_ICB; /* busy is clear */
2198
2199	DEVHDA_UNLOCK(pThis);
2200	return VINF_SUCCESS;
2201	#else /* !IN_RING3 */
2202	DEVHDA_UNLOCK(pThis);
2203	return VINF_IOM_R3_MMIO_WRITE;
2204	#endif /* !IN_RING3 */
2205	}
2206
2207	/*
2208	* Once the guest read the response, it should clear the IRV bit of the IRS register.
2209	*/
2210	HDA_REG(pThis, IRS) &= ~(u32Value & HDA_IRS_IRV);
2211
2212	DEVHDA_UNLOCK(pThis);
2213	return VINF_SUCCESS;
2214	}
2215
2216	static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2217	{
2218	RT_NOREF(iReg);
2219
2220	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2221
2222	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
2223	{
2224	LogFunc(("CORB DMA (still) running, skipping\n"));
2225
2226	DEVHDA_UNLOCK(pThis);
2227	return VINF_SUCCESS;
2228	}
2229
2230	if (u32Value & HDA_RIRBWP_RST)
2231	{
2232	/* Do a RIRB reset. */
2233	if (pThis->cbRirbBuf)
2234	{
2235	Assert(pThis->pu64RirbBuf);
2236	RT_BZERO((void *)pThis->pu64RirbBuf, pThis->cbRirbBuf);
2237	}
2238
2239	LogRel2(("HDA: RIRB reset\n"));
2240
2241	HDA_REG(pThis, RIRBWP) = 0;
2242	}
2243
2244	DEVHDA_UNLOCK(pThis);
2245
2246	/* The remaining bits are O, see 6.2.22. */
2247	return VINF_SUCCESS;
2248	}
2249
2250	static int hdaRegWriteRINTCNT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2251	{
2252	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2253
2254	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
2255	{
2256	LogFunc(("CORB DMA is (still) running, skipping\n"));
2257
2258	DEVHDA_UNLOCK(pThis);
2259	return VINF_SUCCESS;
2260	}
2261
2262	RT_NOREF(iReg);
2263
2264	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
2265	AssertRC(rc);
2266
2267	LogFunc(("Response interrupt count is now %RU8\n", HDA_REG(pThis, RINTCNT) & 0xFF));
2268
2269	DEVHDA_UNLOCK(pThis);
2270	return rc;
2271	}
2272
2273	static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2274	{
2275	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2276	int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2277	if (RT_FAILURE(rc))
2278	AssertRCReturn(rc, rc);
2279
2280	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2281
2282	switch(iReg)
2283	{
2284	case HDA_REG_CORBLBASE:
2285	pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
2286	pThis->u64CORBBase \|= pThis->au32Regs[iRegMem];
2287	break;
2288	case HDA_REG_CORBUBASE:
2289	pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
2290	pThis->u64CORBBase \|= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2291	break;
2292	case HDA_REG_RIRBLBASE:
2293	pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
2294	pThis->u64RIRBBase \|= pThis->au32Regs[iRegMem];
2295	break;
2296	case HDA_REG_RIRBUBASE:
2297	pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
2298	pThis->u64RIRBBase \|= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2299	break;
2300	case HDA_REG_DPLBASE:
2301	{
2302	pThis->u64DPBase = pThis->au32Regs[iRegMem] & DPBASE_ADDR_MASK;
2303	Assert(pThis->u64DPBase % 128 == 0); /* Must be 128-byte aligned. */
2304
2305	/* Also make sure to handle the DMA position enable bit. */
2306	pThis->fDMAPosition = pThis->au32Regs[iRegMem] & RT_BIT_32(0);
2307	LogRel(("HDA: %s DMA position buffer\n", pThis->fDMAPosition ? "Enabled" : "Disabled"));
2308	break;
2309	}
2310	case HDA_REG_DPUBASE:
2311	pThis->u64DPBase = RT_MAKE_U64(RT_LO_U32(pThis->u64DPBase) & DPBASE_ADDR_MASK, pThis->au32Regs[iRegMem]);
2312	break;
2313	default:
2314	AssertMsgFailed(("Invalid index\n"));
2315	break;
2316	}
2317
2318	LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
2319	pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
2320
2321	DEVHDA_UNLOCK(pThis);
2322	return rc;
2323	}
2324
2325	static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2326	{
2327	RT_NOREF_PV(iReg);
2328
2329	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2330
2331	uint8_t v = HDA_REG(pThis, RIRBSTS);
2332	HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
2333
2334	DEVHDA_UNLOCK(pThis);
2335
2336	#ifndef DEBUG
2337	return hdaProcessInterrupt(pThis);
2338	#else
2339	return hdaProcessInterrupt(pThis, __FUNCTION__);
2340	#endif
2341	}
2342
2343	#ifdef IN_RING3
2344	/**
2345	* Retrieves a corresponding sink for a given mixer control.
2346	* Returns NULL if no sink is found.
2347	*
2348	* @return PHDAMIXERSINK
2349	* @param pThis HDA state.
2350	* @param enmMixerCtl Mixer control to get the corresponding sink for.
2351	*/
2352	static PHDAMIXERSINK hdaMixerControlToSink(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
2353	{
2354	PHDAMIXERSINK pSink;
2355
2356	switch (enmMixerCtl)
2357	{
2358	case PDMAUDIOMIXERCTL_VOLUME_MASTER:
2359	/* Fall through is intentional. */
2360	case PDMAUDIOMIXERCTL_FRONT:
2361	pSink = &pThis->SinkFront;
2362	break;
2363	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2364	case PDMAUDIOMIXERCTL_CENTER_LFE:
2365	pSink = &pThis->SinkCenterLFE;
2366	break;
2367	case PDMAUDIOMIXERCTL_REAR:
2368	pSink = &pThis->SinkRear;
2369	break;
2370	#endif
2371	case PDMAUDIOMIXERCTL_LINE_IN:
2372	pSink = &pThis->SinkLineIn;
2373	break;
2374	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2375	case PDMAUDIOMIXERCTL_MIC_IN:
2376	pSink = &pThis->SinkMicIn;
2377	break;
2378	#endif
2379	default:
2380	pSink = NULL;
2381	AssertMsgFailed(("Unhandled mixer control\n"));
2382	break;
2383	}
2384
2385	return pSink;
2386	}
2387
2388	/**
2389	* Adds a driver stream to a specific mixer sink.
2390	*
2391	* @returns IPRT status code.
2392	* @param pThis HDA state.
2393	* @param pMixSink Audio mixer sink to add audio streams to.
2394	* @param pCfg Audio stream configuration to use for the audio streams to add.
2395	* @param pDrv Driver stream to add.
2396	*/
2397	static int hdaMixerAddDrvStream(PHDASTATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg, PHDADRIVER pDrv)
2398	{
2399	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2400	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
2401	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2402
2403	LogFunc(("Sink=%s, Stream=%s\n", pMixSink->pszName, pCfg->szName));
2404
2405	PPDMAUDIOSTREAMCFG pStreamCfg = DrvAudioHlpStreamCfgDup(pCfg);
2406	if (!pStreamCfg)
2407	return VERR_NO_MEMORY;
2408
2409	if (!RTStrPrintf(pStreamCfg->szName, sizeof(pStreamCfg->szName), "%s", pCfg->szName))
2410	{
2411	RTMemFree(pStreamCfg);
2412	return VERR_BUFFER_OVERFLOW;
2413	}
2414
2415	LogFunc(("[LUN#%RU8] %s\n", pDrv->uLUN, pStreamCfg->szName));
2416
2417	int rc = VINF_SUCCESS;
2418
2419	PHDADRIVERSTREAM pDrvStream = NULL;
2420
2421	if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
2422	{
2423	LogFunc(("enmRecSource=%d\n", pStreamCfg->DestSource.Source));
2424
2425	switch (pStreamCfg->DestSource.Source)
2426	{
2427	case PDMAUDIORECSOURCE_LINE:
2428	pDrvStream = &pDrv->LineIn;
2429	break;
2430	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2431	case PDMAUDIORECSOURCE_MIC:
2432	pDrvStream = &pDrv->MicIn;
2433	break;
2434	#endif
2435	default:
2436	rc = VERR_NOT_SUPPORTED;
2437	break;
2438	}
2439	}
2440	else if (pStreamCfg->enmDir == PDMAUDIODIR_OUT)
2441	{
2442	LogFunc(("enmPlaybackDest=%d\n", pStreamCfg->DestSource.Dest));
2443
2444	switch (pStreamCfg->DestSource.Dest)
2445	{
2446	case PDMAUDIOPLAYBACKDEST_FRONT:
2447	pDrvStream = &pDrv->Front;
2448	break;
2449	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2450	case PDMAUDIOPLAYBACKDEST_CENTER_LFE:
2451	pDrvStream = &pDrv->CenterLFE;
2452	break;
2453	case PDMAUDIOPLAYBACKDEST_REAR:
2454	pDrvStream = &pDrv->Rear;
2455	break;
2456	#endif
2457	default:
2458	rc = VERR_NOT_SUPPORTED;
2459	break;
2460	}
2461	}
2462	else
2463	rc = VERR_NOT_SUPPORTED;
2464
2465	if (RT_SUCCESS(rc))
2466	{
2467	AssertPtr(pDrvStream);
2468	AssertMsg(pDrvStream->pMixStrm == NULL, ("[LUN#%RU8] Driver stream already present when it must not\n", pDrv->uLUN));
2469
2470	PAUDMIXSTREAM pMixStrm;
2471	rc = AudioMixerSinkCreateStream(pMixSink, pDrv->pConnector, pStreamCfg, 0 /* fFlags */, &pMixStrm);
2472	if (RT_SUCCESS(rc))
2473	{
2474	rc = AudioMixerSinkAddStream(pMixSink, pMixStrm);
2475	LogFlowFunc(("LUN#%RU8: Added \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
2476	}
2477
2478	if (RT_SUCCESS(rc))
2479	pDrvStream->pMixStrm = pMixStrm;
2480	}
2481
2482	if (pStreamCfg)
2483	{
2484	RTMemFree(pStreamCfg);
2485	pStreamCfg = NULL;
2486	}
2487
2488	LogFlowFuncLeaveRC(rc);
2489	return rc;
2490	}
2491
2492	/**
2493	* Adds all current driver streams to a specific mixer sink.
2494	*
2495	* @returns IPRT status code.
2496	* @param pThis HDA state.
2497	* @param pMixSink Audio mixer sink to add stream to.
2498	* @param pCfg Audio stream configuration to use for the audio streams to add.
2499	*/
2500	static int hdaMixerAddDrvStreams(PHDASTATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg)
2501	{
2502	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2503	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
2504	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2505
2506	LogFunc(("Sink=%s, Stream=%s\n", pMixSink->pszName, pCfg->szName));
2507
2508	if (!DrvAudioHlpStreamCfgIsValid(pCfg))
2509	return VERR_INVALID_PARAMETER;
2510
2511	int rc = AudioMixerSinkSetFormat(pMixSink, &pCfg->Props);
2512	if (RT_FAILURE(rc))
2513	return rc;
2514
2515	PHDADRIVER pDrv;
2516	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2517	{
2518	int rc2 = hdaMixerAddDrvStream(pThis, pMixSink, pCfg, pDrv);
2519	if (RT_FAILURE(rc2))
2520	LogFunc(("Attaching stream failed with %Rrc\n", rc2));
2521
2522	/* Do not pass failure to rc here, as there might be drivers which aren't
2523	* configured / ready yet. */
2524	}
2525
2526	return rc;
2527	}
2528
2529	/**
2530	* Adds a new audio stream to a specific mixer control.
2531	* Depending on the mixer control the stream then gets assigned to one of the internal
2532	* mixer sinks, which in turn then handle the mixing of all connected streams to that sink.
2533	*
2534	* @return IPRT status code.
2535	* @param pThis HDA state.
2536	* @param enmMixerCtl Mixer control to assign new stream to.
2537	* @param pCfg Stream configuration for the new stream.
2538	*/
2539	static DECLCALLBACK(int) hdaMixerAddStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOSTREAMCFG pCfg)
2540	{
2541	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2542	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2543
2544	int rc;
2545
2546	PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
2547	if (pSink)
2548	{
2549	rc = hdaMixerAddDrvStreams(pThis, pSink->pMixSink, pCfg);
2550
2551	AssertPtr(pSink->pMixSink);
2552	LogFlowFunc(("Sink=%s, Mixer control=%s\n", pSink->pMixSink->pszName, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl)));
2553	}
2554	else
2555	rc = VERR_NOT_FOUND;
2556
2557	LogFlowFuncLeaveRC(rc);
2558	return rc;
2559	}
2560
2561	/**
2562	* Removes a specified mixer control from the HDA's mixer.
2563	*
2564	* @return IPRT status code.
2565	* @param pThis HDA state.
2566	* @param enmMixerCtl Mixer control to remove.
2567	*
2568	* @remarks Can be called as a callback by the HDA codec.
2569	*/
2570	static DECLCALLBACK(int) hdaMixerRemoveStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
2571	{
2572	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2573
2574	int rc;
2575
2576	PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
2577	if (pSink)
2578	{
2579	PHDADRIVER pDrv;
2580	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2581	{
2582	PAUDMIXSTREAM pMixStream = NULL;
2583	switch (enmMixerCtl)
2584	{
2585	/*
2586	* Input.
2587	*/
2588	case PDMAUDIOMIXERCTL_LINE_IN:
2589	pMixStream = pDrv->LineIn.pMixStrm;
2590	pDrv->LineIn.pMixStrm = NULL;
2591	break;
2592	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2593	case PDMAUDIOMIXERCTL_MIC_IN:
2594	pMixStream = pDrv->MicIn.pMixStrm;
2595	pDrv->MicIn.pMixStrm = NULL;
2596	break;
2597	#endif
2598	/*
2599	* Output.
2600	*/
2601	case PDMAUDIOMIXERCTL_FRONT:
2602	pMixStream = pDrv->Front.pMixStrm;
2603	pDrv->Front.pMixStrm = NULL;
2604	break;
2605	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2606	case PDMAUDIOMIXERCTL_CENTER_LFE:
2607	pMixStream = pDrv->CenterLFE.pMixStrm;
2608	pDrv->CenterLFE.pMixStrm = NULL;
2609	break;
2610	case PDMAUDIOMIXERCTL_REAR:
2611	pMixStream = pDrv->Rear.pMixStrm;
2612	pDrv->Rear.pMixStrm = NULL;
2613	break;
2614	#endif
2615	default:
2616	AssertMsgFailed(("Mixer control %d not implemented\n", enmMixerCtl));
2617	break;
2618	}
2619
2620	if (pMixStream)
2621	{
2622	AudioMixerSinkRemoveStream(pSink->pMixSink, pMixStream);
2623	AudioMixerStreamDestroy(pMixStream);
2624
2625	pMixStream = NULL;
2626	}
2627	}
2628
2629	AudioMixerSinkRemoveAllStreams(pSink->pMixSink);
2630	rc = VINF_SUCCESS;
2631	}
2632	else
2633	rc = VERR_NOT_FOUND;
2634
2635	LogFunc(("Mixer control=%s, rc=%Rrc\n", DrvAudioHlpAudMixerCtlToStr(enmMixerCtl), rc));
2636	return rc;
2637	}
2638
2639	/**
2640	* Controls an input / output converter widget, that is, which converter is connected
2641	* to which stream (and channel).
2642	*
2643	* @returns IPRT status code.
2644	* @param pThis HDA State.
2645	* @param enmMixerCtl Mixer control to set SD stream number and channel for.
2646	* @param uSD SD stream number (number + 1) to set. Set to 0 for unassign.
2647	* @param uChannel Channel to set. Only valid if a valid SD stream number is specified.
2648	*
2649	* @remarks Can be called as a callback by the HDA codec.
2650	*/
2651	static DECLCALLBACK(int) hdaMixerControl(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, uint8_t uSD, uint8_t uChannel)
2652	{
2653	LogFunc(("enmMixerCtl=%s, uSD=%RU8, uChannel=%RU8\n", DrvAudioHlpAudMixerCtlToStr(enmMixerCtl), uSD, uChannel));
2654
2655	if (uSD == 0) /* Stream number 0 is reserved. */
2656	{
2657	Log2Func(("Invalid SDn (%RU8) number for mixer control '%s', ignoring\n", uSD, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl)));
2658	return VINF_SUCCESS;
2659	}
2660	/* uChannel is optional. */
2661
2662	/* SDn0 starts as 1. */
2663	Assert(uSD);
2664	uSD--;
2665
2666	#ifndef VBOX_WITH_AUDIO_HDA_MIC_IN
2667	/* Only SDI0 (Line-In) is supported. */
2668	if ( hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN
2669	&& uSD >= 1)
2670	{
2671	LogRel2(("HDA: Dedicated Mic-In support not imlpemented / built-in (stream #%RU8), using Line-In (stream #0) instead\n", uSD));
2672	uSD = 0;
2673	}
2674	#endif
2675
2676	int rc = VINF_SUCCESS;
2677
2678	PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
2679	if (pSink)
2680	{
2681	AssertPtr(pSink->pMixSink);
2682
2683	/* If this an output stream, determine the correct SD#. */
2684	if ( (uSD < HDA_MAX_SDI)
2685	&& AudioMixerSinkGetDir(pSink->pMixSink) == AUDMIXSINKDIR_OUTPUT)
2686	{
2687	uSD += HDA_MAX_SDI;
2688	}
2689
2690	/* Detach the existing stream from the sink. */
2691	if ( pSink->pStream
2692	&& ( pSink->pStream->u8SD != uSD
2693	\|\| pSink->pStream->u8Channel != uChannel)
2694	)
2695	{
2696	LogFunc(("Sink '%s' was assigned to stream #%RU8 (channel %RU8) before\n",
2697	pSink->pMixSink->pszName, pSink->pStream->u8SD, pSink->pStream->u8Channel));
2698
2699	hdaStreamLock(pSink->pStream);
2700
2701	/* Only disable the stream if the stream descriptor # has changed. */
2702	if (pSink->pStream->u8SD != uSD)
2703	hdaStreamEnable(pSink->pStream, false);
2704
2705	pSink->pStream->pMixSink = NULL;
2706
2707	hdaStreamUnlock(pSink->pStream);
2708
2709	pSink->pStream = NULL;
2710	}
2711
2712	Assert(uSD < HDA_MAX_STREAMS);
2713
2714	/* Attach the new stream to the sink.
2715	* Enabling the stream will be done by the gust via a separate SDnCTL call then. */
2716	if (pSink->pStream == NULL)
2717	{
2718	LogRel2(("HDA: Setting sink '%s' to stream #%RU8 (channel %RU8), mixer control=%s\n",
2719	pSink->pMixSink->pszName, uSD, uChannel, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl)));
2720
2721	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
2722	if (pStream)
2723	{
2724	hdaStreamLock(pStream);
2725
2726	pSink->pStream = pStream;
2727
2728	pStream->u8Channel = uChannel;
2729	pStream->pMixSink = pSink;
2730
2731	hdaStreamUnlock(pStream);
2732
2733	rc = VINF_SUCCESS;
2734	}
2735	else
2736	rc = VERR_NOT_IMPLEMENTED;
2737	}
2738	}
2739	else
2740	rc = VERR_NOT_FOUND;
2741
2742	if (RT_FAILURE(rc))
2743	LogRel(("HDA: Converter control for stream #%RU8 (channel %RU8) / mixer control '%s' failed with %Rrc, skipping\n",
2744	uSD, uChannel, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl), rc));
2745
2746	LogFlowFuncLeaveRC(rc);
2747	return rc;
2748	}
2749
2750	/**
2751	* Sets the volume of a specified mixer control.
2752	*
2753	* @return IPRT status code.
2754	* @param pThis HDA State.
2755	* @param enmMixerCtl Mixer control to set volume for.
2756	* @param pVol Pointer to volume data to set.
2757	*
2758	* @remarks Can be called as a callback by the HDA codec.
2759	*/
2760	static DECLCALLBACK(int) hdaMixerSetVolume(PHDASTATE pThis,
2761	PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOVOLUME pVol)
2762	{
2763	int rc;
2764
2765	PHDAMIXERSINK pSink = hdaMixerControlToSink(pThis, enmMixerCtl);
2766	if ( pSink
2767	&& pSink->pMixSink)
2768	{
2769	LogRel2(("HDA: Setting volume for mixer sink '%s' to %RU8/%RU8 (%s)\n",
2770	pSink->pMixSink->pszName, pVol->uLeft, pVol->uRight, pVol->fMuted ? "Muted" : "Unmuted"));
2771
2772	/* Set the volume.
2773	* We assume that the codec already converted it to the correct range. */
2774	rc = AudioMixerSinkSetVolume(pSink->pMixSink, pVol);
2775	}
2776	else
2777	rc = VERR_NOT_FOUND;
2778
2779	LogFlowFuncLeaveRC(rc);
2780	return rc;
2781	}
2782
2783	/**
2784	* Main routine for the device timer.
2785	*
2786	* @param pThis HDA state.
2787	*/
2788	static void hdaTimerMain(PHDASTATE pThis)
2789	{
2790	AssertPtrReturnVoid(pThis);
2791
2792	STAM_PROFILE_START(&pThis->StatTimer, a);
2793
2794	DEVHDA_LOCK_BOTH_RETURN_VOID(pThis);
2795
2796	/* Do all transfers from/to DMA. */
2797	hdaDoTransfers(pThis);
2798
2799	/* Flag indicating whether to kick the timer again for a
2800	* new data processing round. */
2801	bool fSinksActive = false;
2802
2803	/* Do we need to kick the timer again? */
2804	if ( AudioMixerSinkIsActive(pThis->SinkFront.pMixSink)
2805	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2806	\|\| AudioMixerSinkIsActive(pThis->SinkCenterLFE.pMixSink)
2807	\|\| AudioMixerSinkIsActive(pThis->SinkRear.pMixSink)
2808	#endif
2809	\|\| AudioMixerSinkIsActive(pThis->SinkLineIn.pMixSink)
2810	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2811	\|\| AudioMixerSinkIsActive(pThis->SinkMicIn.pMixSink)
2812	#endif
2813	)
2814	{
2815	fSinksActive = true;
2816	}
2817
2818	bool fTimerScheduled = false;
2819	if ( hdaStreamTransferIsScheduled(hdaGetStreamFromSink(pThis, &pThis->SinkFront))
2820	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2821	\|\| hdaStreamTransferIsScheduled(hdaGetStreamFromSink(pThis, &pThis->SinkMicIn))
2822	#endif
2823	\|\| hdaStreamTransferIsScheduled(hdaGetStreamFromSink(pThis, &pThis->SinkLineIn)))
2824	{
2825	fTimerScheduled = true;
2826	}
2827
2828	Log3Func(("fSinksActive=%RTbool, fTimerScheduled=%RTbool\n", fSinksActive, fTimerScheduled));
2829
2830	if ( fSinksActive
2831	&& !fTimerScheduled)
2832	{
2833	hdaTimerSet(pThis, TMTimerGet(pThis->pTimer) + TMTimerGetFreq(pThis->pTimer) / pThis->u16TimerHz, true /* fForce */);
2834	}
2835
2836	DEVHDA_UNLOCK_BOTH(pThis);
2837
2838	STAM_PROFILE_STOP(&pThis->StatTimer, a);
2839	}
2840
2841	#ifdef HDA_USE_DMA_ACCESS_HANDLER
2842	/**
2843	* HC access handler for the FIFO.
2844	*
2845	* @returns VINF_SUCCESS if the handler have carried out the operation.
2846	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2847	* @param pVM VM Handle.
2848	* @param pVCpu The cross context CPU structure for the calling EMT.
2849	* @param GCPhys The physical address the guest is writing to.
2850	* @param pvPhys The HC mapping of that address.
2851	* @param pvBuf What the guest is reading/writing.
2852	* @param cbBuf How much it's reading/writing.
2853	* @param enmAccessType The access type.
2854	* @param enmOrigin Who is making the access.
2855	* @param pvUser User argument.
2856	*/
2857	static DECLCALLBACK(VBOXSTRICTRC) hdaDMAAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys,
2858	void *pvBuf, size_t cbBuf,
2859	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2860	{
2861	RT_NOREF(pVM, pVCpu, pvPhys, pvBuf, enmOrigin);
2862
2863	PHDADMAACCESSHANDLER pHandler = (PHDADMAACCESSHANDLER)pvUser;
2864	AssertPtr(pHandler);
2865
2866	PHDASTREAM pStream = pHandler->pStream;
2867	AssertPtr(pStream);
2868
2869	Assert(GCPhys >= pHandler->GCPhysFirst);
2870	Assert(GCPhys <= pHandler->GCPhysLast);
2871	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
2872
2873	/* Not within BDLE range? Bail out. */
2874	if ( (GCPhys < pHandler->BDLEAddr)
2875	\|\| (GCPhys + cbBuf > pHandler->BDLEAddr + pHandler->BDLESize))
2876	{
2877	return VINF_PGM_HANDLER_DO_DEFAULT;
2878	}
2879
2880	switch(enmAccessType)
2881	{
2882	case PGMACCESSTYPE_WRITE:
2883	{
2884	# ifdef DEBUG
2885	PHDASTREAMDBGINFO pStreamDbg = &pStream->Dbg;
2886
2887	const uint64_t tsNowNs = RTTimeNanoTS();
2888	const uint32_t tsElapsedMs = (tsNowNs - pStreamDbg->tsWriteSlotBegin) / 1000 / 1000;
2889
2890	uint64_t cWritesHz = ASMAtomicReadU64(&pStreamDbg->cWritesHz);
2891	uint64_t cbWrittenHz = ASMAtomicReadU64(&pStreamDbg->cbWrittenHz);
2892
2893	if (tsElapsedMs >= (1000 / HDA_TIMER_HZ_DEFAULT))
2894	{
2895	LogFunc(("[SD%RU8] %RU32ms elapsed, cbWritten=%RU64, cWritten=%RU64 -- %RU32 bytes on average per time slot (%zums)\n",
2896	pStream->u8SD, tsElapsedMs, cbWrittenHz, cWritesHz,
2897	ASMDivU64ByU32RetU32(cbWrittenHz, cWritesHz ? cWritesHz : 1), 1000 / HDA_TIMER_HZ_DEFAULT));
2898
2899	pStreamDbg->tsWriteSlotBegin = tsNowNs;
2900
2901	cWritesHz = 0;
2902	cbWrittenHz = 0;
2903	}
2904
2905	cWritesHz += 1;
2906	cbWrittenHz += cbBuf;
2907
2908	ASMAtomicIncU64(&pStreamDbg->cWritesTotal);
2909	ASMAtomicAddU64(&pStreamDbg->cbWrittenTotal, cbBuf);
2910
2911	ASMAtomicWriteU64(&pStreamDbg->cWritesHz, cWritesHz);
2912	ASMAtomicWriteU64(&pStreamDbg->cbWrittenHz, cbWrittenHz);
2913
2914	LogFunc(("[SD%RU8] Writing %3zu @ 0x%x (off %zu)\n",
2915	pStream->u8SD, cbBuf, GCPhys, GCPhys - pHandler->BDLEAddr));
2916
2917	LogFunc(("[SD%RU8] cWrites=%RU64, cbWritten=%RU64 -> %RU32 bytes on average\n",
2918	pStream->u8SD, pStreamDbg->cWritesTotal, pStreamDbg->cbWrittenTotal,
2919	ASMDivU64ByU32RetU32(pStreamDbg->cbWrittenTotal, pStreamDbg->cWritesTotal)));
2920	# endif
2921
2922	if (pThis->fDebugEnabled)
2923	{
2924	RTFILE fh;
2925	RTFileOpen(&fh, VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH "hdaDMAAccessWrite.pcm",
2926	RTFILE_O_OPEN_CREATE \| RTFILE_O_APPEND \| RTFILE_O_WRITE \| RTFILE_O_DENY_NONE);
2927	RTFileWrite(fh, pvBuf, cbBuf, NULL);
2928	RTFileClose(fh);
2929	}
2930
2931	# ifdef HDA_USE_DMA_ACCESS_HANDLER_WRITING
2932	PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
2933	AssertPtr(pCircBuf);
2934
2935	uint8_t pbBuf = (uint8_t )pvBuf;
2936	while (cbBuf)
2937	{
2938	/* Make sure we only copy as much as the stream's FIFO can hold (SDFIFOS, 18.2.39). */
2939	void *pvChunk;
2940	size_t cbChunk;
2941	RTCircBufAcquireWriteBlock(pCircBuf, cbBuf, &pvChunk, &cbChunk);
2942
2943	if (cbChunk)
2944	{
2945	memcpy(pvChunk, pbBuf, cbChunk);
2946
2947	pbBuf += cbChunk;
2948	Assert(cbBuf >= cbChunk);
2949	cbBuf -= cbChunk;
2950	}
2951	else
2952	{
2953	//AssertMsg(RTCircBufFree(pCircBuf), ("No more space but still %zu bytes to write\n", cbBuf));
2954	break;
2955	}
2956
2957	LogFunc(("[SD%RU8] cbChunk=%zu\n", pStream->u8SD, cbChunk));
2958
2959	RTCircBufReleaseWriteBlock(pCircBuf, cbChunk);
2960	}
2961	# endif /* HDA_USE_DMA_ACCESS_HANDLER_WRITING */
2962	break;
2963	}
2964
2965	default:
2966	AssertMsgFailed(("Access type not implemented\n"));
2967	break;
2968	}
2969
2970	return VINF_PGM_HANDLER_DO_DEFAULT;
2971	}
2972	#endif /* HDA_USE_DMA_ACCESS_HANDLER */
2973
2974	/**
2975	* Soft reset of the device triggered via GCTL.
2976	*
2977	* @param pThis HDA state.
2978	*
2979	*/
2980	static void hdaGCTLReset(PHDASTATE pThis)
2981	{
2982	LogFlowFuncEnter();
2983
2984	pThis->cStreamsActive = 0;
2985
2986	HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(HDA_MAX_SDO, HDA_MAX_SDI, 0, 0, 1); /* see 6.2.1 */
2987	HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
2988	HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
2989	HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
2990	HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
2991	HDA_REG(pThis, CORBSIZE) = 0x42; /* Up to 256 CORB entries see 6.2.1 */
2992	HDA_REG(pThis, RIRBSIZE) = 0x42; /* Up to 256 RIRB entries see 6.2.1 */
2993	HDA_REG(pThis, CORBRP) = 0x0;
2994	HDA_REG(pThis, CORBWP) = 0x0;
2995	HDA_REG(pThis, RIRBWP) = 0x0;
2996	/* Some guests (like Haiku) don't set RINTCNT explicitly but expect an interrupt after each
2997	* RIRB response -- so initialize RINTCNT to 1 by default. */
2998	HDA_REG(pThis, RINTCNT) = 0x1;
2999
3000	/*
3001	* Stop any audio currently playing and/or recording.
3002	*/
3003	pThis->SinkFront.pStream = NULL;
3004	if (pThis->SinkFront.pMixSink)
3005	AudioMixerSinkReset(pThis->SinkFront.pMixSink);
3006	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3007	pThis->SinkMicIn.pStream = NULL;
3008	if (pThis->SinkMicIn.pMixSink)
3009	AudioMixerSinkReset(pThis->SinkMicIn.pMixSink);
3010	# endif
3011	pThis->SinkLineIn.pStream = NULL;
3012	if (pThis->SinkLineIn.pMixSink)
3013	AudioMixerSinkReset(pThis->SinkLineIn.pMixSink);
3014	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3015	pThis->SinkCenterLFE = NULL;
3016	if (pThis->SinkCenterLFE.pMixSink)
3017	AudioMixerSinkReset(pThis->SinkCenterLFE.pMixSink);
3018	pThis->SinkRear.pStream = NULL;
3019	if (pThis->SinkRear.pMixSink)
3020	AudioMixerSinkReset(pThis->SinkRear.pMixSink);
3021	# endif
3022
3023	/*
3024	* Reset the codec.
3025	*/
3026	if ( pThis->pCodec
3027	&& pThis->pCodec->pfnReset)
3028	{
3029	pThis->pCodec->pfnReset(pThis->pCodec);
3030	}
3031
3032	/*
3033	* Set some sensible defaults for which HDA sinks
3034	* are connected to which stream number.
3035	*
3036	* We use SD0 for input and SD4 for output by default.
3037	* These stream numbers can be changed by the guest dynamically lateron.
3038	*/
3039	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3040	hdaMixerControl(pThis, PDMAUDIOMIXERCTL_MIC_IN , 1 /* SD0 /, 0 / Channel */);
3041	#endif
3042	hdaMixerControl(pThis, PDMAUDIOMIXERCTL_LINE_IN , 1 /* SD0 /, 0 / Channel */);
3043
3044	hdaMixerControl(pThis, PDMAUDIOMIXERCTL_FRONT , 5 /* SD4 /, 0 / Channel */);
3045	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3046	hdaMixerControl(pThis, PDMAUDIOMIXERCTL_CENTER_LFE, 5 /* SD4 /, 0 / Channel */);
3047	hdaMixerControl(pThis, PDMAUDIOMIXERCTL_REAR , 5 /* SD4 /, 0 / Channel */);
3048	#endif
3049
3050	pThis->cbCorbBuf = HDA_CORB_SIZE * sizeof(uint32_t);
3051
3052	if (pThis->pu32CorbBuf)
3053	RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
3054	else
3055	pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
3056
3057	pThis->cbRirbBuf = HDA_RIRB_SIZE * sizeof(uint64_t);
3058	if (pThis->pu64RirbBuf)
3059	RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
3060	else
3061	pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
3062
3063	/* Clear our internal response interrupt counter. */
3064	pThis->u16RespIntCnt = 0;
3065
3066	for (uint8_t uSD = 0; uSD < HDA_MAX_STREAMS; ++uSD)
3067	{
3068	/* Remove the RUN bit from SDnCTL in case the stream was in a running state before. */
3069	HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_RUN;
3070	hdaStreamReset(pThis, &pThis->aStreams[uSD], uSD);
3071	}
3072
3073	/* Clear stream tags <-> objects mapping table. */
3074	RT_ZERO(pThis->aTags);
3075
3076	/* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
3077	HDA_REG(pThis, STATESTS) = 0x1;
3078
3079	LogFlowFuncLeave();
3080	LogRel(("HDA: Reset\n"));
3081	}
3082
3083	/**
3084	* Timer callback which handles the audio data transfers on a periodic basis.
3085	*
3086	* @param pDevIns Device instance.
3087	* @param pTimer Timer which was used when calling this.
3088	* @param pvUser User argument as PHDASTATE.
3089	*/
3090	static DECLCALLBACK(void) hdaTimer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
3091	{
3092	RT_NOREF(pDevIns, pTimer);
3093
3094	PHDASTATE pThis = (PHDASTATE)pvUser;
3095	Assert(pThis == PDMINS_2_DATA(pDevIns, PHDASTATE));
3096	AssertPtr(pThis);
3097
3098	hdaTimerMain(pThis);
3099	}
3100
3101	/**
3102	* Main routine to perform the actual audio data transfers from the HDA streams
3103	* to the backend(s) and vice versa.
3104	*
3105	* @param pThis HDA state.
3106	*/
3107	static void hdaDoTransfers(PHDASTATE pThis)
3108	{
3109	PHDASTREAM pStreamLineIn = hdaGetStreamFromSink(pThis, &pThis->SinkLineIn);
3110	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3111	PHDASTREAM pStreamMicIn = hdaGetStreamFromSink(pThis, &pThis->SinkMicIn);
3112	#endif
3113	PHDASTREAM pStreamFront = hdaGetStreamFromSink(pThis, &pThis->SinkFront);
3114
3115	hdaStreamUpdate(pStreamFront, true /* fInTimer */);
3116	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3117	hdaStreamUpdate(pStreamMicIn, true /* fInTimer */);
3118	#endif
3119	hdaStreamUpdate(pStreamLineIn, true /* fInTimer */);
3120	}
3121
3122	#ifdef DEBUG_andy
3123	# define HDA_DEBUG_DMA
3124	#endif
3125
3126	#endif /* IN_RING3 */
3127
3128	/* MMIO callbacks */
3129
3130	/**
3131	* @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
3132	*
3133	* @note During implementation, we discovered so-called "forgotten" or "hole"
3134	* registers whose description is not listed in the RPM, datasheet, or
3135	* spec.
3136	*/
3137	PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
3138	{
3139	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3140	int rc;
3141	RT_NOREF_PV(pvUser);
3142
3143	/*
3144	* Look up and log.
3145	*/
3146	uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3147	int idxRegDsc = hdaRegLookup(offReg); /* Register descriptor index. */
3148	#ifdef LOG_ENABLED
3149	unsigned const cbLog = cb;
3150	uint32_t offRegLog = offReg;
3151	#endif
3152
3153	Log3Func(("offReg=%#x cb=%#x\n", offReg, cb));
3154	Assert(cb == 4); Assert((offReg & 3) == 0);
3155
3156	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
3157
3158	if (!(HDA_REG(pThis, GCTL) & HDA_GCTL_CRST) && idxRegDsc != HDA_REG_GCTL)
3159	LogFunc(("Access to registers except GCTL is blocked while reset\n"));
3160
3161	if (idxRegDsc == -1)
3162	LogRel(("HDA: Invalid read access @0x%x (bytes=%u)\n", offReg, cb));
3163
3164	if (idxRegDsc != -1)
3165	{
3166	/* Leave lock before calling read function. */
3167	DEVHDA_UNLOCK(pThis);
3168
3169	/* ASSUMES gapless DWORD at end of map. */
3170	if (g_aHdaRegMap[idxRegDsc].size == 4)
3171	{
3172	/*
3173	* Straight forward DWORD access.
3174	*/
3175	rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
3176	Log3Func(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, (uint32_t )pv, rc));
3177	}
3178	else
3179	{
3180	/*
3181	* Multi register read (unless there are trailing gaps).
3182	* ASSUMES that only DWORD reads have sideeffects.
3183	*/
3184	uint32_t u32Value = 0;
3185	unsigned cbLeft = 4;
3186	do
3187	{
3188	uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
3189	uint32_t u32Tmp = 0;
3190
3191	rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
3192	Log3Func(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
3193	if (rc != VINF_SUCCESS)
3194	break;
3195	u32Value \|= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
3196
3197	cbLeft -= cbReg;
3198	offReg += cbReg;
3199	idxRegDsc++;
3200	} while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
3201
3202	if (rc == VINF_SUCCESS)
3203	(uint32_t )pv = u32Value;
3204	else
3205	Assert(!IOM_SUCCESS(rc));
3206	}
3207	}
3208	else
3209	{
3210	DEVHDA_UNLOCK(pThis);
3211
3212	rc = VINF_IOM_MMIO_UNUSED_FF;
3213	Log3Func(("\tHole at %x is accessed for read\n", offReg));
3214	}
3215
3216	/*
3217	* Log the outcome.
3218	*/
3219	#ifdef LOG_ENABLED
3220	if (cbLog == 4)
3221	Log3Func(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, (uint32_t )pv, rc));
3222	else if (cbLog == 2)
3223	Log3Func(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, (uint16_t )pv, rc));
3224	else if (cbLog == 1)
3225	Log3Func(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, (uint8_t )pv, rc));
3226	#endif
3227	return rc;
3228	}
3229
3230
3231	DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
3232	{
3233	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
3234
3235	if (!(HDA_REG(pThis, GCTL) & HDA_GCTL_CRST) && idxRegDsc != HDA_REG_GCTL)
3236	{
3237	Log(("hdaWriteReg: Warning: Access to %s is blocked while controller is in reset mode\n", g_aHdaRegMap[idxRegDsc].abbrev));
3238	LogRel2(("HDA: Warning: Access to register %s is blocked while controller is in reset mode\n",
3239	g_aHdaRegMap[idxRegDsc].abbrev));
3240
3241	DEVHDA_UNLOCK(pThis);
3242	return VINF_SUCCESS;
3243	}
3244
3245	/*
3246	* Handle RD (register description) flags.
3247	*/
3248
3249	/* For SDI / SDO: Check if writes to those registers are allowed while SDCTL's RUN bit is set. */
3250	if (idxRegDsc >= HDA_NUM_GENERAL_REGS)
3251	{
3252	const uint32_t uSDCTL = HDA_STREAM_REG(pThis, CTL, HDA_SD_NUM_FROM_REG(pThis, CTL, idxRegDsc));
3253
3254	/*
3255	* Some OSes (like Win 10 AU) violate the spec by writing stuff to registers which are not supposed to be be touched
3256	* while SDCTL's RUN bit is set. So just ignore those values.
3257	*/
3258
3259	/* Is the RUN bit currently set? */
3260	if ( RT_BOOL(uSDCTL & HDA_SDCTL_RUN)
3261	/* Are writes to the register denied if RUN bit is set? */
3262	&& !(g_aHdaRegMap[idxRegDsc].fFlags & HDA_RD_FLAG_SD_WRITE_RUN))
3263	{
3264	Log(("hdaWriteReg: Warning: Access to %s is blocked! %R[sdctl]\n", g_aHdaRegMap[idxRegDsc].abbrev, uSDCTL));
3265	LogRel2(("HDA: Warning: Access to register %s is blocked while the stream's RUN bit is set\n",
3266	g_aHdaRegMap[idxRegDsc].abbrev));
3267
3268	DEVHDA_UNLOCK(pThis);
3269	return VINF_SUCCESS;
3270	}
3271	}
3272
3273	/* Leave the lock before calling write function. */
3274	DEVHDA_UNLOCK(pThis);
3275
3276	#ifdef LOG_ENABLED
3277	uint32_t const idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3278	uint32_t const u32OldValue = pThis->au32Regs[idxRegMem];
3279	#endif
3280	int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
3281	Log3Func(("Written value %#x to %s[%d byte]; %x => %x%s\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
3282	g_aHdaRegMap[idxRegDsc].size, u32OldValue, pThis->au32Regs[idxRegMem], pszLog));
3283	RT_NOREF(pszLog);
3284	return rc;
3285	}
3286
3287
3288	/**
3289	* @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
3290	*/
3291	PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
3292	{
3293	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3294	int rc;
3295	RT_NOREF_PV(pvUser);
3296
3297	/*
3298	* The behavior of accesses that aren't aligned on natural boundraries is
3299	* undefined. Just reject them outright.
3300	*/
3301	/** @todo IOM could check this, it could also split the 8 byte accesses for us. */
3302	Assert(cb == 1 \|\| cb == 2 \|\| cb == 4 \|\| cb == 8);
3303	if (GCPhysAddr & (cb - 1))
3304	return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
3305
3306	/*
3307	* Look up and log the access.
3308	*/
3309	uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3310	int idxRegDsc = hdaRegLookup(offReg);
3311	uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
3312	uint64_t u64Value;
3313	if (cb == 4) u64Value = (uint32_t const )pv;
3314	else if (cb == 2) u64Value = (uint16_t const )pv;
3315	else if (cb == 1) u64Value = (uint8_t const )pv;
3316	else if (cb == 8) u64Value = (uint64_t const )pv;
3317	else
3318	{
3319	u64Value = 0; /* shut up gcc. */
3320	AssertReleaseMsgFailed(("%u\n", cb));
3321	}
3322
3323	#ifdef LOG_ENABLED
3324	uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
3325	if (idxRegDsc == -1)
3326	Log3Func(("@%#05x u32=%#010x cb=%d\n", offReg, (uint32_t const )pv, cb));
3327	else if (cb == 4)
3328	Log3Func(("@%#05x u32=%#010x %s\n", offReg, (uint32_t )pv, g_aHdaRegMap[idxRegDsc].abbrev));
3329	else if (cb == 2)
3330	Log3Func(("@%#05x u16=%#06x (%#010x) %s\n", offReg, (uint16_t )pv, (uint32_t )pv, g_aHdaRegMap[idxRegDsc].abbrev));
3331	else if (cb == 1)
3332	Log3Func(("@%#05x u8=%#04x (%#010x) %s\n", offReg, (uint8_t )pv, (uint32_t )pv, g_aHdaRegMap[idxRegDsc].abbrev));
3333
3334	if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
3335	Log3Func(("\tsize=%RU32 != cb=%u!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
3336	#endif
3337
3338	/*
3339	* Try for a direct hit first.
3340	*/
3341	if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
3342	{
3343	rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
3344	Log3Func(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
3345	}
3346	/*
3347	* Partial or multiple register access, loop thru the requested memory.
3348	*/
3349	else
3350	{
3351	/*
3352	* If it's an access beyond the start of the register, shift the input
3353	* value and fill in missing bits. Natural alignment rules means we
3354	* will only see 1 or 2 byte accesses of this kind, so no risk of
3355	* shifting out input values.
3356	*/
3357	if (idxRegDsc == -1 && (idxRegDsc = hdaRegLookupWithin(offReg)) != -1)
3358	{
3359	uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
3360	offReg -= cbBefore;
3361	idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3362	u64Value <<= cbBefore * 8;
3363	u64Value \|= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
3364	Log3Func(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
3365	cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
3366	}
3367
3368	/* Loop thru the write area, it may cover multiple registers. */
3369	rc = VINF_SUCCESS;
3370	for (;;)
3371	{
3372	uint32_t cbReg;
3373	if (idxRegDsc != -1)
3374	{
3375	idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3376	cbReg = g_aHdaRegMap[idxRegDsc].size;
3377	if (cb < cbReg)
3378	{
3379	u64Value \|= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
3380	Log3Func(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
3381	g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
3382	}
3383	#ifdef LOG_ENABLED
3384	uint32_t uLogOldVal = pThis->au32Regs[idxRegMem];
3385	#endif
3386	rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
3387	Log3Func(("\t%#x -> %#x\n", uLogOldVal, pThis->au32Regs[idxRegMem]));
3388	}
3389	else
3390	{
3391	LogRel(("HDA: Invalid write access @0x%x\n", offReg));
3392	cbReg = 1;
3393	}
3394	if (rc != VINF_SUCCESS)
3395	break;
3396	if (cbReg >= cb)
3397	break;
3398
3399	/* Advance. */
3400	offReg += cbReg;
3401	cb -= cbReg;
3402	u64Value >>= cbReg * 8;
3403	if (idxRegDsc == -1)
3404	idxRegDsc = hdaRegLookup(offReg);
3405	else
3406	{
3407	idxRegDsc++;
3408	if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
3409	\|\| g_aHdaRegMap[idxRegDsc].offset != offReg)
3410	{
3411	idxRegDsc = -1;
3412	}
3413	}
3414	}
3415	}
3416
3417	return rc;
3418	}
3419
3420
3421	/* PCI callback. */
3422
3423	#ifdef IN_RING3
3424	/**
3425	* @callback_method_impl{FNPCIIOREGIONMAP}
3426	*/
3427	static DECLCALLBACK(int) hdaPciIoRegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3428	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
3429	{
3430	RT_NOREF(iRegion, enmType);
3431	PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
3432
3433	/*
3434	* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
3435	*
3436	* Let IOM talk DWORDs when reading, saves a lot of complications. On
3437	* writing though, we have to do it all ourselves because of sideeffects.
3438	*/
3439	Assert(enmType == PCI_ADDRESS_SPACE_MEM);
3440	int rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /pvUser/,
3441	IOMMMIO_FLAGS_READ_DWORD
3442	\| IOMMMIO_FLAGS_WRITE_PASSTHRU,
3443	hdaMMIOWrite, hdaMMIORead, "HDA");
3444
3445	if (RT_FAILURE(rc))
3446	return rc;
3447
3448	if (pThis->fR0Enabled)
3449	{
3450	rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /pvUser/,
3451	"hdaMMIOWrite", "hdaMMIORead");
3452	if (RT_FAILURE(rc))
3453	return rc;
3454	}
3455
3456	if (pThis->fRCEnabled)
3457	{
3458	rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /pvUser/,
3459	"hdaMMIOWrite", "hdaMMIORead");
3460	if (RT_FAILURE(rc))
3461	return rc;
3462	}
3463
3464	pThis->MMIOBaseAddr = GCPhysAddress;
3465	return VINF_SUCCESS;
3466	}
3467
3468
3469	/* Saved state callbacks. */
3470
3471	static int hdaSaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStream)
3472	{
3473	RT_NOREF(pDevIns);
3474	#ifdef VBOX_STRICT
3475	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3476	#endif
3477
3478	Log2Func(("[SD%RU8]\n", pStream->u8SD));
3479
3480	/* Save stream ID. */
3481	int rc = SSMR3PutU8(pSSM, pStream->u8SD);
3482	AssertRCReturn(rc, rc);
3483	Assert(pStream->u8SD < HDA_MAX_STREAMS);
3484
3485	rc = SSMR3PutStructEx(pSSM, &pStream->State, sizeof(HDASTREAMSTATE), 0 /fFlags/, g_aSSMStreamStateFields7, NULL);
3486	AssertRCReturn(rc, rc);
3487
3488	#ifdef VBOX_STRICT /* Sanity checks. */
3489	uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
3490	HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
3491	uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
3492	uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
3493
3494	Assert(u64BaseDMA == pStream->u64BDLBase);
3495	Assert(u16LVI == pStream->u16LVI);
3496	Assert(u32CBL == pStream->u32CBL);
3497	#endif
3498
3499	rc = SSMR3PutStructEx(pSSM, &pStream->State.BDLE.Desc, sizeof(HDABDLEDESC),
3500	0 /fFlags/, g_aSSMBDLEDescFields7, NULL);
3501	AssertRCReturn(rc, rc);
3502
3503	rc = SSMR3PutStructEx(pSSM, &pStream->State.BDLE.State, sizeof(HDABDLESTATE),
3504	0 /fFlags/, g_aSSMBDLEStateFields7, NULL);
3505	AssertRCReturn(rc, rc);
3506
3507	rc = SSMR3PutStructEx(pSSM, &pStream->State.Period, sizeof(HDASTREAMPERIOD),
3508	0 /* fFlags */, g_aSSMStreamPeriodFields7, NULL);
3509	AssertRCReturn(rc, rc);
3510
3511	#ifdef VBOX_STRICT /* Sanity checks. */
3512	PHDABDLE pBDLE = &pStream->State.BDLE;
3513	if (u64BaseDMA)
3514	{
3515	Assert(pStream->State.uCurBDLE <= u16LVI + 1);
3516
3517	HDABDLE curBDLE;
3518	rc = hdaBDLEFetch(pThis, &curBDLE, u64BaseDMA, pStream->State.uCurBDLE);
3519	AssertRC(rc);
3520
3521	Assert(curBDLE.Desc.u32BufSize == pBDLE->Desc.u32BufSize);
3522	Assert(curBDLE.Desc.u64BufAdr == pBDLE->Desc.u64BufAdr);
3523	Assert(curBDLE.Desc.fFlags == pBDLE->Desc.fFlags);
3524	}
3525	else
3526	{
3527	Assert(pBDLE->Desc.u64BufAdr == 0);
3528	Assert(pBDLE->Desc.u32BufSize == 0);
3529	}
3530	#endif
3531
3532	uint32_t cbCircBufSize = 0;
3533	uint32_t cbCircBufUsed = 0;
3534
3535	if (pStream->State.pCircBuf)
3536	{
3537	cbCircBufSize = (uint32_t)RTCircBufSize(pStream->State.pCircBuf);
3538	cbCircBufUsed = (uint32_t)RTCircBufUsed(pStream->State.pCircBuf);
3539	}
3540
3541	rc = SSMR3PutU32(pSSM, cbCircBufSize);
3542	AssertRCReturn(rc, rc);
3543
3544	rc = SSMR3PutU32(pSSM, cbCircBufUsed);
3545	AssertRCReturn(rc, rc);
3546
3547	if (cbCircBufUsed)
3548	{
3549	/*
3550	* We now need to get the circular buffer's data without actually modifying
3551	* the internal read / used offsets -- otherwise we would end up with broken audio
3552	* data after saving the state.
3553	*
3554	* So get the current read offset and serialize the buffer data manually based on that.
3555	*/
3556	size_t cbCircBufOffRead = RTCircBufOffsetRead(pStream->State.pCircBuf);
3557
3558	void *pvBuf;
3559	size_t cbBuf;
3560	RTCircBufAcquireReadBlock(pStream->State.pCircBuf, cbCircBufUsed, &pvBuf, &cbBuf);
3561
3562	if (cbBuf)
3563	{
3564	size_t cbToRead = cbCircBufUsed;
3565	size_t cbEnd = 0;
3566
3567	if (cbCircBufUsed > cbCircBufOffRead)
3568	cbEnd = cbCircBufUsed - cbCircBufOffRead;
3569
3570	if (cbEnd) /* Save end of buffer first. */
3571	{
3572	rc = SSMR3PutMem(pSSM, (uint8_t )pvBuf + cbCircBufSize - cbEnd / End of buffer */, cbEnd);
3573	AssertRCReturn(rc, rc);
3574
3575	Assert(cbToRead >= cbEnd);
3576	cbToRead -= cbEnd;
3577	}
3578
3579	if (cbToRead) /* Save remaining stuff at start of buffer (if any). */
3580	{
3581	rc = SSMR3PutMem(pSSM, (uint8_t )pvBuf - cbCircBufUsed / Start of buffer */, cbToRead);
3582	AssertRCReturn(rc, rc);
3583	}
3584	}
3585
3586	RTCircBufReleaseReadBlock(pStream->State.pCircBuf, 0 /* Don't advance read pointer -- see comment above */);
3587	}
3588
3589	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n",
3590	pStream->u8SD,
3591	HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), HDA_STREAM_REG(pThis, CBL, pStream->u8SD), HDA_STREAM_REG(pThis, LVI, pStream->u8SD)));
3592
3593	#ifdef LOG_ENABLED
3594	hdaBDLEDumpAll(pThis, pStream->u64BDLBase, pStream->u16LVI + 1);
3595	#endif
3596
3597	return rc;
3598	}
3599
3600	/**
3601	* @callback_method_impl{FNSSMDEVSAVEEXEC}
3602	*/
3603	static DECLCALLBACK(int) hdaSaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3604	{
3605	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3606
3607	/* Save Codec nodes states. */
3608	hdaCodecSaveState(pThis->pCodec, pSSM);
3609
3610	/* Save MMIO registers. */
3611	SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3612	SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3613
3614	/* Save controller-specifc internals. */
3615	SSMR3PutU64(pSSM, pThis->u64WalClk);
3616	SSMR3PutU8(pSSM, pThis->u8IRQL);
3617
3618	/* Save number of streams. */
3619	SSMR3PutU32(pSSM, HDA_MAX_STREAMS);
3620
3621	/* Save stream states. */
3622	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
3623	{
3624	int rc = hdaSaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
3625	AssertRCReturn(rc, rc);
3626	}
3627
3628	return VINF_SUCCESS;
3629	}
3630
3631	/**
3632	* Does required post processing when loading a saved state.
3633	*
3634	* @param pThis Pointer to HDA state.
3635	*/
3636	static int hdaLoadExecPost(PHDASTATE pThis)
3637	{
3638	int rc = VINF_SUCCESS;
3639
3640	uint64_t tsExpire = 0; /* Timestamp of new timer expiration time / Whether to resume the device timer. */
3641
3642	/*
3643	* Enable all previously active streams.
3644	*/
3645	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
3646	{
3647	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, i);
3648	if (pStream)
3649	{
3650	int rc2;
3651
3652	bool fActive = RT_BOOL(HDA_STREAM_REG(pThis, CTL, i) & HDA_SDCTL_RUN);
3653	if (fActive)
3654	{
3655	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
3656	/* Make sure to also create the async I/O thread before actually enabling the stream. */
3657	rc2 = hdaStreamAsyncIOCreate(pStream);
3658	AssertRC(rc2);
3659
3660	/* ... and enabling it. */
3661	hdaStreamAsyncIOEnable(pStream, true /* fEnable */);
3662	#endif
3663	/* Resume the stream's period. */
3664	hdaStreamPeriodResume(&pStream->State.Period);
3665
3666	/* (Re-)enable the stream. */
3667	rc2 = hdaStreamEnable(pStream, true /* fEnable */);
3668	AssertRC(rc2);
3669
3670	/* Add the stream to the device setup. */
3671	rc2 = hdaAddStream(pThis, &pStream->State.Cfg);
3672	AssertRC(rc2);
3673
3674	#ifdef HDA_USE_DMA_ACCESS_HANDLER
3675	/* (Re-)install the DMA handler. */
3676	hdaStreamRegisterDMAHandlers(pThis, pStream);
3677	#endif
3678	/* Determine the earliest timing slot we need to use. */
3679	if (tsExpire)
3680	tsExpire = RT_MIN(tsExpire, hdaStreamTransferGetNext(pStream));
3681	else
3682	tsExpire = hdaStreamTransferGetNext(pStream);
3683
3684	Log2Func(("[SD%RU8] tsExpire=%RU64\n", pStream->u8SD, tsExpire));
3685
3686	/* Also keep track of the currently active streams. */
3687	pThis->cStreamsActive++;
3688	}
3689	}
3690	}
3691
3692	/* Start the timer if one of the above streams were active during taking the saved state. */
3693	if (tsExpire)
3694	{
3695	LogFunc(("Resuming timer at %RU64\n", tsExpire));
3696	hdaTimerSet(pThis, tsExpire, true /* fForce */);
3697	}
3698
3699	LogFlowFuncLeaveRC(rc);
3700	return rc;
3701	}
3702
3703
3704	/**
3705	* Handles loading of all saved state versions older than the current one.
3706	*
3707	* @param pThis Pointer to HDA state.
3708	* @param pSSM Pointer to SSM handle.
3709	* @param uVersion Saved state version to load.
3710	* @param uPass Loading stage to handle.
3711	*/
3712	static int hdaLoadExecLegacy(PHDASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3713	{
3714	RT_NOREF(uPass);
3715
3716	int rc = VINF_SUCCESS;
3717
3718	/*
3719	* Load MMIO registers.
3720	*/
3721	uint32_t cRegs;
3722	switch (uVersion)
3723	{
3724	case HDA_SSM_VERSION_1:
3725	/* Starting with r71199, we would save 112 instead of 113
3726	registers due to some code cleanups. This only affected trunk
3727	builds in the 4.1 development period. */
3728	cRegs = 113;
3729	if (SSMR3HandleRevision(pSSM) >= 71199)
3730	{
3731	uint32_t uVer = SSMR3HandleVersion(pSSM);
3732	if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3733	&& VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3734	&& VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3735	cRegs = 112;
3736	}
3737	break;
3738
3739	case HDA_SSM_VERSION_2:
3740	case HDA_SSM_VERSION_3:
3741	cRegs = 112;
3742	AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= 112);
3743	break;
3744
3745	/* Since version 4 we store the register count to stay flexible. */
3746	case HDA_SSM_VERSION_4:
3747	case HDA_SSM_VERSION_5:
3748	case HDA_SSM_VERSION_6:
3749	rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3750	if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3751	LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3752	break;
3753
3754	default:
3755	LogRel(("HDA: Warning: Unsupported / too new saved state version (%RU32)\n", uVersion));
3756	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3757	}
3758
3759	if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3760	{
3761	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3762	SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3763	}
3764	else
3765	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3766
3767	/* Make sure to update the base addresses first before initializing any streams down below. */
3768	pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3769	pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3770	pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE) & DPBASE_ADDR_MASK, HDA_REG(pThis, DPUBASE));
3771
3772	/* Also make sure to update the DMA position bit if this was enabled when saving the state. */
3773	pThis->fDMAPosition = RT_BOOL(HDA_REG(pThis, DPLBASE) & RT_BIT_32(0));
3774
3775	/*
3776	* Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
3777	* every BDLE state, whereas it only needs to be stored
3778	* once for every stream. Most of the BDLE state we can
3779	* get out of the registers anyway, so just ignore those values.
3780	*
3781	* Also, only the current BDLE was saved, regardless whether
3782	* there were more than one (and there are at least two entries,
3783	* according to the spec).
3784	*/
3785	#define HDA_SSM_LOAD_BDLE_STATE_PRE_V5(v, x) \
3786	{ \
3787	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */ \
3788	AssertRCReturn(rc, rc); \
3789	rc = SSMR3GetU64(pSSM, &x.Desc.u64BufAdr); /* u64BdleCviAddr */ \
3790	AssertRCReturn(rc, rc); \
3791	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleMaxCvi */ \
3792	AssertRCReturn(rc, rc); \
3793	rc = SSMR3GetU32(pSSM, &x.State.u32BDLIndex); /* u32BdleCvi */ \
3794	AssertRCReturn(rc, rc); \
3795	rc = SSMR3GetU32(pSSM, &x.Desc.u32BufSize); /* u32BdleCviLen */ \
3796	AssertRCReturn(rc, rc); \
3797	rc = SSMR3GetU32(pSSM, &x.State.u32BufOff); /* u32BdleCviPos */ \
3798	AssertRCReturn(rc, rc); \
3799	bool fIOC; \
3800	rc = SSMR3GetBool(pSSM, &fIOC); /* fBdleCviIoc */ \
3801	AssertRCReturn(rc, rc); \
3802	x.Desc.fFlags = fIOC ? HDA_BDLE_FLAG_IOC : 0; \
3803	rc = SSMR3GetU32(pSSM, &x.State.cbBelowFIFOW); /* cbUnderFifoW */ \
3804	AssertRCReturn(rc, rc); \
3805	rc = SSMR3Skip(pSSM, sizeof(uint8_t) * 256); /* FIFO */ \
3806	AssertRCReturn(rc, rc); \
3807	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */ \
3808	AssertRCReturn(rc, rc); \
3809	}
3810
3811	/*
3812	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3813	*/
3814	switch (uVersion)
3815	{
3816	case HDA_SSM_VERSION_1:
3817	case HDA_SSM_VERSION_2:
3818	case HDA_SSM_VERSION_3:
3819	case HDA_SSM_VERSION_4:
3820	{
3821	/* Only load the internal states.
3822	* The rest will be initialized from the saved registers later. */
3823
3824	/* Note 1: Only the current BDLE for a stream was saved! */
3825	/* Note 2: The stream's saving order is/was fixed, so don't touch! */
3826
3827	/* Output */
3828	PHDASTREAM pStream = &pThis->aStreams[4];
3829	rc = hdaStreamInit(pStream, 4 /* Stream descriptor, hardcoded */);
3830	if (RT_FAILURE(rc))
3831	break;
3832	HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
3833	pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
3834
3835	/* Microphone-In */
3836	pStream = &pThis->aStreams[2];
3837	rc = hdaStreamInit(pStream, 2 /* Stream descriptor, hardcoded */);
3838	if (RT_FAILURE(rc))
3839	break;
3840	HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
3841	pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
3842
3843	/* Line-In */
3844	pStream = &pThis->aStreams[0];
3845	rc = hdaStreamInit(pStream, 0 /* Stream descriptor, hardcoded */);
3846	if (RT_FAILURE(rc))
3847	break;
3848	HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
3849	pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
3850	break;
3851	}
3852
3853	#undef HDA_SSM_LOAD_BDLE_STATE_PRE_V5
3854
3855	default: /* Since v5 we support flexible stream and BDLE counts. */
3856	{
3857	uint32_t cStreams;
3858	rc = SSMR3GetU32(pSSM, &cStreams);
3859	if (RT_FAILURE(rc))
3860	break;
3861
3862	if (cStreams > HDA_MAX_STREAMS)
3863	cStreams = HDA_MAX_STREAMS; /* Sanity. */
3864
3865	/* Load stream states. */
3866	for (uint32_t i = 0; i < cStreams; i++)
3867	{
3868	uint8_t uStreamID;
3869	rc = SSMR3GetU8(pSSM, &uStreamID);
3870	if (RT_FAILURE(rc))
3871	break;
3872
3873	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uStreamID);
3874	HDASTREAM StreamDummy;
3875
3876	if (!pStream)
3877	{
3878	pStream = &StreamDummy;
3879	LogRel2(("HDA: Warning: Stream ID=%RU32 not supported, skipping to load ...\n", uStreamID));
3880	}
3881
3882	rc = hdaStreamInit(pStream, uStreamID);
3883	if (RT_FAILURE(rc))
3884	{
3885	LogRel(("HDA: Stream #%RU32: Initialization of stream %RU8 failed, rc=%Rrc\n", i, uStreamID, rc));
3886	break;
3887	}
3888
3889	/*
3890	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3891	*/
3892
3893	if (uVersion == HDA_SSM_VERSION_5)
3894	{
3895	/* Get the current BDLE entry and skip the rest. */
3896	uint16_t cBDLE;
3897
3898	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
3899	AssertRC(rc);
3900	rc = SSMR3GetU16(pSSM, &cBDLE); /* cBDLE */
3901	AssertRC(rc);
3902	rc = SSMR3GetU16(pSSM, &pStream->State.uCurBDLE); /* uCurBDLE */
3903	AssertRC(rc);
3904	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
3905	AssertRC(rc);
3906
3907	uint32_t u32BDLEIndex;
3908	for (uint16_t a = 0; a < cBDLE; a++)
3909	{
3910	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
3911	AssertRC(rc);
3912	rc = SSMR3GetU32(pSSM, &u32BDLEIndex); /* u32BDLIndex */
3913	AssertRC(rc);
3914
3915	/* Does the current BDLE index match the current BDLE to process? */
3916	if (u32BDLEIndex == pStream->State.uCurBDLE)
3917	{
3918	rc = SSMR3GetU32(pSSM, &pStream->State.BDLE.State.cbBelowFIFOW); /* cbBelowFIFOW */
3919	AssertRC(rc);
3920	rc = SSMR3Skip(pSSM, sizeof(uint8_t) * 256); /* FIFO, deprecated */
3921	AssertRC(rc);
3922	rc = SSMR3GetU32(pSSM, &pStream->State.BDLE.State.u32BufOff); /* u32BufOff */
3923	AssertRC(rc);
3924	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
3925	AssertRC(rc);
3926	}
3927	else /* Skip not current BDLEs. */
3928	{
3929	rc = SSMR3Skip(pSSM, sizeof(uint32_t) /* cbBelowFIFOW */
3930	+ sizeof(uint8_t) * 256 /* au8FIFO */
3931	+ sizeof(uint32_t) /* u32BufOff */
3932	+ sizeof(uint32_t)); /* End marker */
3933	AssertRC(rc);
3934	}
3935	}
3936	}
3937	else
3938	{
3939	rc = SSMR3GetStructEx(pSSM, &pStream->State, sizeof(HDASTREAMSTATE),
3940	0 /* fFlags */, g_aSSMStreamStateFields6, NULL);
3941	if (RT_FAILURE(rc))
3942	break;
3943
3944	/* Get HDABDLEDESC. */
3945	uint32_t uMarker;
3946	rc = SSMR3GetU32(pSSM, &uMarker); /* Begin marker. */
3947	AssertRC(rc);
3948	Assert(uMarker == UINT32_C(0x19200102) /* SSMR3STRUCT_BEGIN */);
3949	rc = SSMR3GetU64(pSSM, &pStream->State.BDLE.Desc.u64BufAdr);
3950	AssertRC(rc);
3951	rc = SSMR3GetU32(pSSM, &pStream->State.BDLE.Desc.u32BufSize);
3952	AssertRC(rc);
3953	bool fFlags = false;
3954	rc = SSMR3GetBool(pSSM, &fFlags); /* Saved states < v7 only stored the IOC as boolean flag. */
3955	AssertRC(rc);
3956	pStream->State.BDLE.Desc.fFlags = fFlags ? HDA_BDLE_FLAG_IOC : 0;
3957	rc = SSMR3GetU32(pSSM, &uMarker); /* End marker. */
3958	AssertRC(rc);
3959	Assert(uMarker == UINT32_C(0x19920406) /* SSMR3STRUCT_END */);
3960
3961	rc = SSMR3GetStructEx(pSSM, &pStream->State.BDLE.State, sizeof(HDABDLESTATE),
3962	0 /* fFlags */, g_aSSMBDLEStateFields6, NULL);
3963	if (RT_FAILURE(rc))
3964	break;
3965
3966	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n",
3967	uStreamID,
3968	HDA_STREAM_REG(pThis, LPIB, uStreamID), HDA_STREAM_REG(pThis, CBL, uStreamID), HDA_STREAM_REG(pThis, LVI, uStreamID)));
3969	#ifdef LOG_ENABLED
3970	hdaBDLEDumpAll(pThis, pStream->u64BDLBase, pStream->u16LVI + 1);
3971	#endif
3972	}
3973
3974	} /* for cStreams */
3975	break;
3976	} /* default */
3977	}
3978
3979	return rc;
3980	}
3981
3982	/**
3983	* @callback_method_impl{FNSSMDEVLOADEXEC}
3984	*/
3985	static DECLCALLBACK(int) hdaLoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3986	{
3987	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3988
3989	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3990
3991	LogRel2(("hdaLoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
3992
3993	/*
3994	* Load Codec nodes states.
3995	*/
3996	int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
3997	if (RT_FAILURE(rc))
3998	{
3999	LogRel(("HDA: Failed loading codec state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
4000	return rc;
4001	}
4002
4003	if (uVersion < HDA_SSM_VERSION) /* Handle older saved states? */
4004	{
4005	rc = hdaLoadExecLegacy(pThis, pSSM, uVersion, uPass);
4006	if (RT_SUCCESS(rc))
4007	rc = hdaLoadExecPost(pThis);
4008
4009	return rc;
4010	}
4011
4012	/*
4013	* Load MMIO registers.
4014	*/
4015	uint32_t cRegs;
4016	rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
4017	if (cRegs != RT_ELEMENTS(pThis->au32Regs))
4018	LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
4019
4020	if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
4021	{
4022	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
4023	SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
4024	}
4025	else
4026	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
4027
4028	/* Make sure to update the base addresses first before initializing any streams down below. */
4029	pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
4030	pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
4031	pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE) & DPBASE_ADDR_MASK, HDA_REG(pThis, DPUBASE));
4032
4033	/* Also make sure to update the DMA position bit if this was enabled when saving the state. */
4034	pThis->fDMAPosition = RT_BOOL(HDA_REG(pThis, DPLBASE) & RT_BIT_32(0));
4035
4036	/*
4037	* Load controller-specifc internals.
4038	* Don't annoy other team mates (forgot this for state v7).
4039	*/
4040	if ( SSMR3HandleRevision(pSSM) >= 116273
4041	\|\| SSMR3HandleVersion(pSSM) >= VBOX_FULL_VERSION_MAKE(5, 2, 0))
4042	{
4043	rc = SSMR3GetU64(pSSM, &pThis->u64WalClk);
4044	AssertRC(rc);
4045
4046	rc = SSMR3GetU8(pSSM, &pThis->u8IRQL);
4047	AssertRC(rc);
4048	}
4049
4050	/*
4051	* Load streams.
4052	*/
4053	uint32_t cStreams;
4054	rc = SSMR3GetU32(pSSM, &cStreams);
4055	AssertRC(rc);
4056
4057	if (cStreams > HDA_MAX_STREAMS)
4058	cStreams = HDA_MAX_STREAMS; /* Sanity. */
4059
4060	Log2Func(("cStreams=%RU32\n", cStreams));
4061
4062	/* Load stream states. */
4063	for (uint32_t i = 0; i < cStreams; i++)
4064	{
4065	uint8_t uStreamID;
4066	rc = SSMR3GetU8(pSSM, &uStreamID);
4067	AssertRC(rc);
4068
4069	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uStreamID);
4070	HDASTREAM StreamDummy;
4071
4072	if (!pStream)
4073	{
4074	pStream = &StreamDummy;
4075	LogRel2(("HDA: Warning: Loading of stream #%RU8 not supported, skipping to load ...\n", uStreamID));
4076	}
4077
4078	rc = hdaStreamInit(pStream, uStreamID);
4079	if (RT_FAILURE(rc))
4080	{
4081	LogRel(("HDA: Stream #%RU8: Loading initialization failed, rc=%Rrc\n", uStreamID, rc));
4082	/* Continue. */
4083	}
4084
4085	rc = SSMR3GetStructEx(pSSM, &pStream->State, sizeof(HDASTREAMSTATE),
4086	0 /* fFlags */, g_aSSMStreamStateFields7,
4087	NULL);
4088	AssertRC(rc);
4089
4090	/*
4091	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
4092	*/
4093	rc = SSMR3GetStructEx(pSSM, &pStream->State.BDLE.Desc, sizeof(HDABDLEDESC),
4094	0 /* fFlags */, g_aSSMBDLEDescFields7, NULL);
4095	AssertRC(rc);
4096
4097	rc = SSMR3GetStructEx(pSSM, &pStream->State.BDLE.State, sizeof(HDABDLESTATE),
4098	0 /* fFlags */, g_aSSMBDLEStateFields7, NULL);
4099	AssertRC(rc);
4100
4101	Log2Func(("[SD%RU8] %R[bdle]\n", pStream->u8SD, &pStream->State.BDLE));
4102
4103	/*
4104	* Load period state.
4105	* Don't annoy other team mates (forgot this for state v7).
4106	*/
4107	hdaStreamPeriodInit(&pStream->State.Period,
4108	pStream->u8SD, pStream->u16LVI, pStream->u32CBL, &pStream->State.Cfg);
4109
4110	if ( SSMR3HandleRevision(pSSM) >= 116273
4111	\|\| SSMR3HandleVersion(pSSM) >= VBOX_FULL_VERSION_MAKE(5, 2, 0))
4112	{
4113	rc = SSMR3GetStructEx(pSSM, &pStream->State.Period, sizeof(HDASTREAMPERIOD),
4114	0 /* fFlags */, g_aSSMStreamPeriodFields7, NULL);
4115	AssertRC(rc);
4116	}
4117
4118	/*
4119	* Load internal (FIFO) buffer.
4120	*/
4121	uint32_t cbCircBufSize = 0;
4122	rc = SSMR3GetU32(pSSM, &cbCircBufSize); /* cbCircBuf */
4123	AssertRC(rc);
4124
4125	uint32_t cbCircBufUsed = 0;
4126	rc = SSMR3GetU32(pSSM, &cbCircBufUsed); /* cbCircBuf */
4127	AssertRC(rc);
4128
4129	if (cbCircBufSize) /* If 0, skip the buffer. */
4130	{
4131	/* Paranoia. */
4132	AssertReleaseMsg(cbCircBufSize <= _1M,
4133	("HDA: Saved state contains bogus DMA buffer size (%RU32) for stream #%RU8",
4134	cbCircBufSize, uStreamID));
4135	AssertReleaseMsg(cbCircBufUsed <= cbCircBufSize,
4136	("HDA: Saved state contains invalid DMA buffer usage (%RU32/%RU32) for stream #%RU8",
4137	cbCircBufUsed, cbCircBufSize, uStreamID));
4138	AssertPtr(pStream->State.pCircBuf);
4139
4140	/* Do we need to cre-create the circular buffer do fit the data size? */
4141	if (cbCircBufSize != (uint32_t)RTCircBufSize(pStream->State.pCircBuf))
4142	{
4143	RTCircBufDestroy(pStream->State.pCircBuf);
4144	pStream->State.pCircBuf = NULL;
4145
4146	rc = RTCircBufCreate(&pStream->State.pCircBuf, cbCircBufSize);
4147	AssertRC(rc);
4148	}
4149
4150	if ( RT_SUCCESS(rc)
4151	&& cbCircBufUsed)
4152	{
4153	void *pvBuf;
4154	size_t cbBuf;
4155
4156	RTCircBufAcquireWriteBlock(pStream->State.pCircBuf, cbCircBufUsed, &pvBuf, &cbBuf);
4157
4158	if (cbBuf)
4159	{
4160	rc = SSMR3GetMem(pSSM, pvBuf, cbBuf);
4161	AssertRC(rc);
4162	}
4163
4164	RTCircBufReleaseWriteBlock(pStream->State.pCircBuf, cbBuf);
4165
4166	Assert(cbBuf == cbCircBufUsed);
4167	}
4168	}
4169
4170	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n",
4171	uStreamID,
4172	HDA_STREAM_REG(pThis, LPIB, uStreamID), HDA_STREAM_REG(pThis, CBL, uStreamID), HDA_STREAM_REG(pThis, LVI, uStreamID)));
4173	#ifdef LOG_ENABLED
4174	hdaBDLEDumpAll(pThis, pStream->u64BDLBase, pStream->u16LVI + 1);
4175	#endif
4176	/** @todo (Re-)initialize active periods? */
4177
4178	} /* for cStreams */
4179
4180	rc = hdaLoadExecPost(pThis);
4181	AssertRC(rc);
4182
4183	LogFlowFuncLeaveRC(rc);
4184	return rc;
4185	}
4186
4187	/* Debug and log type formatters. */
4188
4189	/**
4190	* @callback_method_impl{FNRTSTRFORMATTYPE}
4191	*/
4192	static DECLCALLBACK(size_t) hdaDbgFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4193	const char pszType, void const pvValue,
4194	int cchWidth, int cchPrecision, unsigned fFlags,
4195	void *pvUser)
4196	{
4197	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4198	PHDABDLE pBDLE = (PHDABDLE)pvValue;
4199	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4200	"BDLE(idx:%RU32, off:%RU32, fifow:%RU32, IOC:%RTbool, DMA[%RU32 bytes @ 0x%x])",
4201	pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW,
4202	pBDLE->Desc.fFlags & HDA_BDLE_FLAG_IOC, pBDLE->Desc.u32BufSize, pBDLE->Desc.u64BufAdr);
4203	}
4204
4205	/**
4206	* @callback_method_impl{FNRTSTRFORMATTYPE}
4207	*/
4208	static DECLCALLBACK(size_t) hdaDbgFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4209	const char pszType, void const pvValue,
4210	int cchWidth, int cchPrecision, unsigned fFlags,
4211	void *pvUser)
4212	{
4213	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4214	uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
4215	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4216	"SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
4217	uSDCTL,
4218	uSDCTL & HDA_SDCTL_DIR ? "OUT" : "IN",
4219	RT_BOOL(uSDCTL & HDA_SDCTL_TP),
4220	(uSDCTL & HDA_SDCTL_STRIPE_MASK) >> HDA_SDCTL_STRIPE_SHIFT,
4221	RT_BOOL(uSDCTL & HDA_SDCTL_DEIE),
4222	RT_BOOL(uSDCTL & HDA_SDCTL_FEIE),
4223	RT_BOOL(uSDCTL & HDA_SDCTL_IOCE),
4224	RT_BOOL(uSDCTL & HDA_SDCTL_RUN),
4225	RT_BOOL(uSDCTL & HDA_SDCTL_SRST));
4226	}
4227
4228	/**
4229	* @callback_method_impl{FNRTSTRFORMATTYPE}
4230	*/
4231	static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4232	const char pszType, void const pvValue,
4233	int cchWidth, int cchPrecision, unsigned fFlags,
4234	void *pvUser)
4235	{
4236	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4237	uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
4238	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, uSDFIFOS ? uSDFIFOS + 1 : 0);
4239	}
4240
4241	/**
4242	* @callback_method_impl{FNRTSTRFORMATTYPE}
4243	*/
4244	static DECLCALLBACK(size_t) hdaDbgFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4245	const char pszType, void const pvValue,
4246	int cchWidth, int cchPrecision, unsigned fFlags,
4247	void *pvUser)
4248	{
4249	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4250	uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
4251	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
4252	}
4253
4254	/**
4255	* @callback_method_impl{FNRTSTRFORMATTYPE}
4256	*/
4257	static DECLCALLBACK(size_t) hdaDbgFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4258	const char pszType, void const pvValue,
4259	int cchWidth, int cchPrecision, unsigned fFlags,
4260	void *pvUser)
4261	{
4262	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4263	uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
4264	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4265	"SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
4266	uSdSts,
4267	RT_BOOL(uSdSts & HDA_SDSTS_FIFORDY),
4268	RT_BOOL(uSdSts & HDA_SDSTS_DESE),
4269	RT_BOOL(uSdSts & HDA_SDSTS_FIFOE),
4270	RT_BOOL(uSdSts & HDA_SDSTS_BCIS));
4271	}
4272
4273	static int hdaDbgLookupRegByName(const char *pszArgs)
4274	{
4275	int iReg = 0;
4276	for (; iReg < HDA_NUM_REGS; ++iReg)
4277	if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
4278	return iReg;
4279	return -1;
4280	}
4281
4282
4283	static void hdaDbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
4284	{
4285	Assert( pThis
4286	&& iHdaIndex >= 0
4287	&& iHdaIndex < HDA_NUM_REGS);
4288	pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
4289	}
4290
4291	/**
4292	* @callback_method_impl{FNDBGFHANDLERDEV}
4293	*/
4294	static DECLCALLBACK(void) hdaDbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4295	{
4296	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4297	int iHdaRegisterIndex = hdaDbgLookupRegByName(pszArgs);
4298	if (iHdaRegisterIndex != -1)
4299	hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
4300	else
4301	{
4302	for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NUM_REGS; ++iHdaRegisterIndex)
4303	hdaDbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
4304	}
4305	}
4306
4307	static void hdaDbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
4308	{
4309	Assert( pThis
4310	&& iIdx >= 0
4311	&& iIdx < HDA_MAX_STREAMS);
4312
4313	const PHDASTREAM pStream = &pThis->aStreams[iIdx];
4314
4315	pHlp->pfnPrintf(pHlp, "Stream #%d:\n", iIdx);
4316	pHlp->pfnPrintf(pHlp, "\tSD%dCTL : %R[sdctl]\n", iIdx, HDA_STREAM_REG(pThis, CTL, iIdx));
4317	pHlp->pfnPrintf(pHlp, "\tSD%dCTS : %R[sdsts]\n", iIdx, HDA_STREAM_REG(pThis, STS, iIdx));
4318	pHlp->pfnPrintf(pHlp, "\tSD%dFIFOS: %R[sdfifos]\n", iIdx, HDA_STREAM_REG(pThis, FIFOS, iIdx));
4319	pHlp->pfnPrintf(pHlp, "\tSD%dFIFOW: %R[sdfifow]\n", iIdx, HDA_STREAM_REG(pThis, FIFOW, iIdx));
4320	pHlp->pfnPrintf(pHlp, "\tBDLE : %R[bdle]\n", &pStream->State.BDLE);
4321	}
4322
4323	static void hdaDbgPrintBDLE(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
4324	{
4325	Assert( pThis
4326	&& iIdx >= 0
4327	&& iIdx < HDA_MAX_STREAMS);
4328
4329	const PHDASTREAM pStream = &pThis->aStreams[iIdx];
4330	const PHDABDLE pBDLE = &pStream->State.BDLE;
4331
4332	pHlp->pfnPrintf(pHlp, "Stream #%d BDLE:\n", iIdx);
4333
4334	uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, iIdx),
4335	HDA_STREAM_REG(pThis, BDPU, iIdx));
4336	uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, iIdx);
4337	uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, iIdx);
4338
4339	if (!u64BaseDMA)
4340	return;
4341
4342	pHlp->pfnPrintf(pHlp, "\tCurrent: %R[bdle]\n\n", pBDLE);
4343
4344	pHlp->pfnPrintf(pHlp, "\tMemory:\n");
4345
4346	uint32_t cbBDLE = 0;
4347	for (uint16_t i = 0; i < u16LVI + 1; i++)
4348	{
4349	HDABDLEDESC bd;
4350	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i * sizeof(HDABDLEDESC), &bd, sizeof(bd));
4351
4352	pHlp->pfnPrintf(pHlp, "\t\t%s #%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
4353	pBDLE->State.u32BDLIndex == i ? "*" : " ", i, bd.u64BufAdr, bd.u32BufSize, bd.fFlags & HDA_BDLE_FLAG_IOC);
4354
4355	cbBDLE += bd.u32BufSize;
4356	}
4357
4358	pHlp->pfnPrintf(pHlp, "Total: %RU32 bytes\n", cbBDLE);
4359
4360	if (cbBDLE != u32CBL)
4361	pHlp->pfnPrintf(pHlp, "Warning: %RU32 bytes does not match CBL (%RU32)!\n", cbBDLE, u32CBL);
4362
4363	pHlp->pfnPrintf(pHlp, "DMA counters (base @ 0x%llx):\n", u64BaseDMA);
4364	if (!u64BaseDMA) /* No DMA base given? Bail out. */
4365	{
4366	pHlp->pfnPrintf(pHlp, "\tNo counters found\n");
4367	return;
4368	}
4369
4370	for (int i = 0; i < u16LVI + 1; i++)
4371	{
4372	uint32_t uDMACnt;
4373	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
4374	&uDMACnt, sizeof(uDMACnt));
4375
4376	pHlp->pfnPrintf(pHlp, "\t#%03d DMA @ 0x%x\n", i , uDMACnt);
4377	}
4378	}
4379
4380	static int hdaDbgLookupStrmIdx(PHDASTATE pThis, const char *pszArgs)
4381	{
4382	RT_NOREF(pThis, pszArgs);
4383	/** @todo Add args parsing. */
4384	return -1;
4385	}
4386
4387	/**
4388	* @callback_method_impl{FNDBGFHANDLERDEV}
4389	*/
4390	static DECLCALLBACK(void) hdaDbgInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4391	{
4392	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4393	int iHdaStreamdex = hdaDbgLookupStrmIdx(pThis, pszArgs);
4394	if (iHdaStreamdex != -1)
4395	hdaDbgPrintStream(pThis, pHlp, iHdaStreamdex);
4396	else
4397	for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
4398	hdaDbgPrintStream(pThis, pHlp, iHdaStreamdex);
4399	}
4400
4401	/**
4402	* @callback_method_impl{FNDBGFHANDLERDEV}
4403	*/
4404	static DECLCALLBACK(void) hdaDbgInfoBDLE(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4405	{
4406	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4407	int iHdaStreamdex = hdaDbgLookupStrmIdx(pThis, pszArgs);
4408	if (iHdaStreamdex != -1)
4409	hdaDbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
4410	else
4411	for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
4412	hdaDbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
4413	}
4414
4415	/**
4416	* @callback_method_impl{FNDBGFHANDLERDEV}
4417	*/
4418	static DECLCALLBACK(void) hdaDbgInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4419	{
4420	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4421
4422	if (pThis->pCodec->pfnDbgListNodes)
4423	pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
4424	else
4425	pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
4426	}
4427
4428	/**
4429	* @callback_method_impl{FNDBGFHANDLERDEV}
4430	*/
4431	static DECLCALLBACK(void) hdaDbgInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4432	{
4433	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4434
4435	if (pThis->pCodec->pfnDbgSelector)
4436	pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
4437	else
4438	pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
4439	}
4440
4441	/**
4442	* @callback_method_impl{FNDBGFHANDLERDEV}
4443	*/
4444	static DECLCALLBACK(void) hdaDbgInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4445	{
4446	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4447
4448	if (pThis->pMixer)
4449	AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
4450	else
4451	pHlp->pfnPrintf(pHlp, "Mixer not available\n");
4452	}
4453
4454
4455	/* PDMIBASE */
4456
4457	/**
4458	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
4459	*/
4460	static DECLCALLBACK(void ) hdaQueryInterface(struct PDMIBASE pInterface, const char *pszIID)
4461	{
4462	PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
4463	Assert(&pThis->IBase == pInterface);
4464
4465	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
4466	return NULL;
4467	}
4468
4469
4470	/* PDMDEVREG */
4471
4472
4473	/**
4474	* @interface_method_impl{PDMDEVREG,pfnReset}
4475	*/
4476	static DECLCALLBACK(void) hdaReset(PPDMDEVINS pDevIns)
4477	{
4478	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4479
4480	LogFlowFuncEnter();
4481
4482	DEVHDA_LOCK_RETURN_VOID(pThis);
4483
4484	/*
4485	* 18.2.6,7 defines that values of this registers might be cleared on power on/reset
4486	* hdaReset shouldn't affects these registers.
4487	*/
4488	HDA_REG(pThis, WAKEEN) = 0x0;
4489
4490	hdaGCTLReset(pThis);
4491
4492	/* Indicate that HDA is not in reset. The firmware is supposed to (un)reset HDA,
4493	* but we can take a shortcut.
4494	*/
4495	HDA_REG(pThis, GCTL) = HDA_GCTL_CRST;
4496
4497	DEVHDA_UNLOCK(pThis);
4498	}
4499
4500	/**
4501	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4502	*/
4503	static DECLCALLBACK(int) hdaDestruct(PPDMDEVINS pDevIns)
4504	{
4505	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4506
4507	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
4508
4509	PHDADRIVER pDrv;
4510	while (!RTListIsEmpty(&pThis->lstDrv))
4511	{
4512	pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
4513
4514	RTListNodeRemove(&pDrv->Node);
4515	RTMemFree(pDrv);
4516	}
4517
4518	if (pThis->pCodec)
4519	{
4520	hdaCodecDestruct(pThis->pCodec);
4521
4522	RTMemFree(pThis->pCodec);
4523	pThis->pCodec = NULL;
4524	}
4525
4526	RTMemFree(pThis->pu32CorbBuf);
4527	pThis->pu32CorbBuf = NULL;
4528
4529	RTMemFree(pThis->pu64RirbBuf);
4530	pThis->pu64RirbBuf = NULL;
4531
4532	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
4533	hdaStreamDestroy(&pThis->aStreams[i]);
4534
4535	DEVHDA_UNLOCK(pThis);
4536
4537	return VINF_SUCCESS;
4538	}
4539
4540
4541	/**
4542	* Attach command, internal version.
4543	*
4544	* This is called to let the device attach to a driver for a specified LUN
4545	* during runtime. This is not called during VM construction, the device
4546	* constructor has to attach to all the available drivers.
4547	*
4548	* @returns VBox status code.
4549	* @param pThis HDA state.
4550	* @param uLUN The logical unit which is being detached.
4551	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4552	* @param ppDrv Attached driver instance on success. Optional.
4553	*/
4554	static int hdaAttachInternal(PHDASTATE pThis, unsigned uLUN, uint32_t fFlags, PHDADRIVER *ppDrv)
4555	{
4556	RT_NOREF(fFlags);
4557
4558	/*
4559	* Attach driver.
4560	*/
4561	char *pszDesc;
4562	if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
4563	AssertLogRelFailedReturn(VERR_NO_MEMORY);
4564
4565	PPDMIBASE pDrvBase;
4566	int rc = PDMDevHlpDriverAttach(pThis->pDevInsR3, uLUN,
4567	&pThis->IBase, &pDrvBase, pszDesc);
4568	if (RT_SUCCESS(rc))
4569	{
4570	PHDADRIVER pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
4571	if (pDrv)
4572	{
4573	pDrv->pDrvBase = pDrvBase;
4574	pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
4575	AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
4576	pDrv->pHDAState = pThis;
4577	pDrv->uLUN = uLUN;
4578
4579	/*
4580	* For now we always set the driver at LUN 0 as our primary
4581	* host backend. This might change in the future.
4582	*/
4583	if (pDrv->uLUN == 0)
4584	pDrv->fFlags \|= PDMAUDIODRVFLAGS_PRIMARY;
4585
4586	LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->fFlags));
4587
4588	/* Attach to driver list if not attached yet. */
4589	if (!pDrv->fAttached)
4590	{
4591	RTListAppend(&pThis->lstDrv, &pDrv->Node);
4592	pDrv->fAttached = true;
4593	}
4594
4595	if (ppDrv)
4596	*ppDrv = pDrv;
4597	}
4598	else
4599	rc = VERR_NO_MEMORY;
4600	}
4601	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4602	LogFunc(("No attached driver for LUN #%u\n", uLUN));
4603
4604	if (RT_FAILURE(rc))
4605	{
4606	/* Only free this string on failure;
4607	* must remain valid for the live of the driver instance. */
4608	RTStrFree(pszDesc);
4609	}
4610
4611	LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
4612	return rc;
4613	}
4614
4615	/**
4616	* Detach command, internal version.
4617	*
4618	* This is called to let the device detach from a driver for a specified LUN
4619	* during runtime.
4620	*
4621	* @returns VBox status code.
4622	* @param pThis HDA state.
4623	* @param pDrv Driver to detach device from.
4624	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4625	*/
4626	static int hdaDetachInternal(PHDASTATE pThis, PHDADRIVER pDrv, uint32_t fFlags)
4627	{
4628	RT_NOREF(fFlags);
4629
4630	AudioMixerSinkRemoveStream(pThis->SinkFront.pMixSink, pDrv->Front.pMixStrm);
4631	AudioMixerStreamDestroy(pDrv->Front.pMixStrm);
4632	pDrv->Front.pMixStrm = NULL;
4633
4634	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
4635	AudioMixerSinkRemoveStream(pThis->SinkCenterLFE.pMixSink, pDrv->CenterLFE.pMixStrm);
4636	AudioMixerStreamDestroy(pDrv->CenterLFE.pMixStrm);
4637	pDrv->CenterLFE.pMixStrm = NULL;
4638
4639	AudioMixerSinkRemoveStream(pThis->SinkRear.pMixSink, pDrv->Rear.pMixStrm);
4640	AudioMixerStreamDestroy(pDrv->Rear.pMixStrm);
4641	pDrv->Rear.pMixStrm = NULL;
4642	#endif
4643
4644	AudioMixerSinkRemoveStream(pThis->SinkLineIn.pMixSink, pDrv->LineIn.pMixStrm);
4645	AudioMixerStreamDestroy(pDrv->LineIn.pMixStrm);
4646	pDrv->LineIn.pMixStrm = NULL;
4647
4648	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
4649	AudioMixerSinkRemoveStream(pThis->SinkMicIn.pMixSink, pDrv->MicIn.pMixStrm);
4650	AudioMixerStreamDestroy(pDrv->MicIn.pMixStrm);
4651	pDrv->MicIn.pMixStrm = NULL;
4652	#endif
4653
4654	RTListNodeRemove(&pDrv->Node);
4655
4656	LogFunc(("uLUN=%u, fFlags=0x%x\n", pDrv->uLUN, fFlags));
4657	return VINF_SUCCESS;
4658	}
4659
4660	/**
4661	* @interface_method_impl{PDMDEVREG,pfnAttach}
4662	*/
4663	static DECLCALLBACK(int) hdaAttach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4664	{
4665	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4666
4667	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
4668
4669	LogFunc(("uLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
4670
4671	PHDADRIVER pDrv;
4672	int rc2 = hdaAttachInternal(pThis, uLUN, fFlags, &pDrv);
4673	if (RT_SUCCESS(rc2))
4674	{
4675	PHDASTREAM pStream = hdaGetStreamFromSink(pThis, &pThis->SinkFront);
4676	if (DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
4677	hdaMixerAddDrvStream(pThis, pThis->SinkFront.pMixSink, &pStream->State.Cfg, pDrv);
4678
4679	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
4680	pStream = hdaGetStreamFromSink(pThis, &pThis->SinkCenterLFE);
4681	if (DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
4682	hdaMixerAddDrvStream(pThis, pThis->SinkCenterLFE.pMixSink, &pStream->State.Cfg, pDrv);
4683
4684	pStream = hdaGetStreamFromSink(pThis, &pThis->SinkRear);
4685	if (DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
4686	hdaMixerAddDrvStream(pThis, pThis->SinkRear.pMixSink, &pStream->State.Cfg, pDrv);
4687	#endif
4688	pStream = hdaGetStreamFromSink(pThis, &pThis->SinkLineIn);
4689	if (DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
4690	hdaMixerAddDrvStream(pThis, pThis->SinkLineIn.pMixSink, &pStream->State.Cfg, pDrv);
4691
4692	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
4693	pStream = hdaGetStreamFromSink(pThis, &pThis->SinkMicIn);
4694	if (DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
4695	hdaMixerAddDrvStream(pThis, pThis->SinkMicIn.pMixSink, &pStream->State.Cfg, pDrv);
4696	#endif
4697	}
4698
4699	DEVHDA_UNLOCK(pThis);
4700
4701	return VINF_SUCCESS;
4702	}
4703
4704	/**
4705	* @interface_method_impl{PDMDEVREG,pfnDetach}
4706	*/
4707	static DECLCALLBACK(void) hdaDetach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4708	{
4709	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4710
4711	DEVHDA_LOCK(pThis);
4712
4713	LogFunc(("uLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
4714
4715	PHDADRIVER pDrv, pDrvNext;
4716	RTListForEachSafe(&pThis->lstDrv, pDrv, pDrvNext, HDADRIVER, Node)
4717	{
4718	if (pDrv->uLUN == uLUN)
4719	{
4720	int rc2 = hdaDetachInternal(pThis, pDrv, fFlags);
4721	if (RT_SUCCESS(rc2))
4722	{
4723	RTMemFree(pDrv);
4724	pDrv = NULL;
4725	}
4726
4727	break;
4728	}
4729	}
4730
4731	DEVHDA_UNLOCK(pThis);
4732	}
4733
4734	/**
4735	* Re-attaches (replaces) a driver with a new driver.
4736	*
4737	* @returns VBox status code.
4738	* @param pThis Device instance to re-attach driver to.
4739	* @param pDrv Driver instance used for attaching to.
4740	* If NULL is specified, a new driver will be created and appended
4741	* to the driver list.
4742	* @param uLUN The logical unit which is being re-detached.
4743	* @param pszDriver New driver name to attach.
4744	*/
4745	static int hdaReattachInternal(PHDASTATE pThis, PHDADRIVER pDrv, uint8_t uLUN, const char *pszDriver)
4746	{
4747	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
4748	AssertPtrReturn(pszDriver, VERR_INVALID_POINTER);
4749
4750	int rc;
4751
4752	if (pDrv)
4753	{
4754	rc = hdaDetachInternal(pThis, pDrv, 0 /* fFlags */);
4755	if (RT_SUCCESS(rc))
4756	rc = PDMDevHlpDriverDetach(pThis->pDevInsR3, PDMIBASE_2_PDMDRV(pDrv->pDrvBase), 0 /* fFlags */);
4757
4758	if (RT_FAILURE(rc))
4759	return rc;
4760
4761	pDrv = NULL;
4762	}
4763
4764	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
4765	PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
4766	PCFGMNODE pDev0 = CFGMR3GetChild(pRoot, "Devices/hda/0/");
4767
4768	/* Remove LUN branch. */
4769	CFGMR3RemoveNode(CFGMR3GetChildF(pDev0, "LUN#%u/", uLUN));
4770
4771	#define RC_CHECK() if (RT_FAILURE(rc)) { AssertReleaseRC(rc); break; }
4772
4773	do
4774	{
4775	PCFGMNODE pLunL0;
4776	rc = CFGMR3InsertNodeF(pDev0, &pLunL0, "LUN#%u/", uLUN); RC_CHECK();
4777	rc = CFGMR3InsertString(pLunL0, "Driver", "AUDIO"); RC_CHECK();
4778	rc = CFGMR3InsertNode(pLunL0, "Config/", NULL); RC_CHECK();
4779
4780	PCFGMNODE pLunL1, pLunL2;
4781	rc = CFGMR3InsertNode (pLunL0, "AttachedDriver/", &pLunL1); RC_CHECK();
4782	rc = CFGMR3InsertNode (pLunL1, "Config/", &pLunL2); RC_CHECK();
4783	rc = CFGMR3InsertString(pLunL1, "Driver", pszDriver); RC_CHECK();
4784
4785	rc = CFGMR3InsertString(pLunL2, "AudioDriver", pszDriver); RC_CHECK();
4786
4787	} while (0);
4788
4789	if (RT_SUCCESS(rc))
4790	rc = hdaAttachInternal(pThis, uLUN, 0 /* fFlags /, NULL / ppDrv */);
4791
4792	LogFunc(("pThis=%p, uLUN=%u, pszDriver=%s, rc=%Rrc\n", pThis, uLUN, pszDriver, rc));
4793
4794	#undef RC_CHECK
4795
4796	return rc;
4797	}
4798
4799	/**
4800	* Powers off the device.
4801	*
4802	* @param pDevIns Device instance to power off.
4803	*/
4804	static DECLCALLBACK(void) hdaPowerOff(PPDMDEVINS pDevIns)
4805	{
4806	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4807
4808	DEVHDA_LOCK_RETURN_VOID(pThis);
4809
4810	LogRel2(("HDA: Powering off ...\n"));
4811
4812	/* Ditto goes for the codec, which in turn uses the mixer. */
4813	hdaCodecPowerOff(pThis->pCodec);
4814
4815	/**
4816	* Note: Destroy the mixer while powering off and not in hdaDestruct,
4817	* giving the mixer the chance to release any references held to
4818	* PDM audio streams it maintains.
4819	*/
4820	if (pThis->pMixer)
4821	{
4822	AudioMixerDestroy(pThis->pMixer);
4823	pThis->pMixer = NULL;
4824	}
4825
4826	DEVHDA_UNLOCK(pThis);
4827	}
4828
4829	/**
4830	* @interface_method_impl{PDMDEVREG,pfnConstruct}
4831	*/
4832	static DECLCALLBACK(int) hdaConstruct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4833	{
4834	RT_NOREF(iInstance);
4835	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
4836	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4837	Assert(iInstance == 0);
4838
4839	/*
4840	* Validations.
4841	*/
4842	if (!CFGMR3AreValuesValid(pCfg, "R0Enabled\0"
4843	"RCEnabled\0"
4844	"TimerHz\0"
4845	"PosAdjustEnabled\0"
4846	"PosAdjustFrames\0"
4847	"DebugEnabled\0"
4848	"DebugPathOut\0"))
4849	{
4850	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4851	N_ ("Invalid configuration for the Intel HDA device"));
4852	}
4853
4854	int rc = CFGMR3QueryBoolDef(pCfg, "RCEnabled", &pThis->fRCEnabled, false);
4855	if (RT_FAILURE(rc))
4856	return PDMDEV_SET_ERROR(pDevIns, rc,
4857	N_("HDA configuration error: failed to read RCEnabled as boolean"));
4858	rc = CFGMR3QueryBoolDef(pCfg, "R0Enabled", &pThis->fR0Enabled, false);
4859	if (RT_FAILURE(rc))
4860	return PDMDEV_SET_ERROR(pDevIns, rc,
4861	N_("HDA configuration error: failed to read R0Enabled as boolean"));
4862
4863	rc = CFGMR3QueryU16Def(pCfg, "TimerHz", &pThis->u16TimerHz, HDA_TIMER_HZ_DEFAULT /* Default value, if not set. */);
4864	if (RT_FAILURE(rc))
4865	return PDMDEV_SET_ERROR(pDevIns, rc,
4866	N_("HDA configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
4867
4868	if (pThis->u16TimerHz != HDA_TIMER_HZ_DEFAULT)
4869	LogRel(("HDA: Using custom device timer rate (%RU16Hz)\n", pThis->u16TimerHz));
4870
4871	rc = CFGMR3QueryBoolDef(pCfg, "PosAdjustEnabled", &pThis->fPosAdjustEnabled, true);
4872	if (RT_FAILURE(rc))
4873	return PDMDEV_SET_ERROR(pDevIns, rc,
4874	N_("HDA configuration error: failed to read position adjustment enabled as boolean"));
4875
4876	if (!pThis->fPosAdjustEnabled)
4877	LogRel(("HDA: Position adjustment is disabled\n"));
4878
4879	rc = CFGMR3QueryU16Def(pCfg, "PosAdjustFrames", &pThis->cPosAdjustFrames, HDA_POS_ADJUST_DEFAULT);
4880	if (RT_FAILURE(rc))
4881	return PDMDEV_SET_ERROR(pDevIns, rc,
4882	N_("HDA configuration error: failed to read position adjustment frames as unsigned integer"));
4883
4884	if (pThis->cPosAdjustFrames)
4885	LogRel(("HDA: Using custom position adjustment (%RU16 audio frames)\n", pThis->cPosAdjustFrames));
4886
4887	rc = CFGMR3QueryBoolDef(pCfg, "DebugEnabled", &pThis->Dbg.fEnabled, false);
4888	if (RT_FAILURE(rc))
4889	return PDMDEV_SET_ERROR(pDevIns, rc,
4890	N_("HDA configuration error: failed to read debugging enabled flag as boolean"));
4891
4892	rc = CFGMR3QueryStringDef(pCfg, "DebugPathOut", pThis->Dbg.szOutPath, sizeof(pThis->Dbg.szOutPath),
4893	VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH);
4894	if (RT_FAILURE(rc))
4895	return PDMDEV_SET_ERROR(pDevIns, rc,
4896	N_("HDA configuration error: failed to read debugging output path flag as string"));
4897
4898	if (!strlen(pThis->Dbg.szOutPath))
4899	RTStrPrintf(pThis->Dbg.szOutPath, sizeof(pThis->Dbg.szOutPath), VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH);
4900
4901	if (pThis->Dbg.fEnabled)
4902	LogRel2(("HDA: Debug output will be saved to '%s'\n", pThis->Dbg.szOutPath));
4903
4904	/*
4905	* Use an own critical section for the device instead of the default
4906	* one provided by PDM. This allows fine-grained locking in combination
4907	* with TM when timer-specific stuff is being called in e.g. the MMIO handlers.
4908	*/
4909	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "HDA");
4910	AssertRCReturn(rc, rc);
4911
4912	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4913	AssertRCReturn(rc, rc);
4914
4915	/*
4916	* Initialize data (most of it anyway).
4917	*/
4918	pThis->pDevInsR3 = pDevIns;
4919	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
4920	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4921	/* IBase */
4922	pThis->IBase.pfnQueryInterface = hdaQueryInterface;
4923
4924	/* PCI Device */
4925	PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
4926	PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
4927
4928	PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
4929	PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
4930	PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
4931	PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
4932	PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
4933	PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
4934	PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
4935	PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
4936	false /* fIoSpace /, false / fPrefetchable /, true / f64Bit */, 0x00000000);
4937	PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
4938	PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
4939
4940	#if defined(HDA_AS_PCI_EXPRESS)
4941	PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
4942	#elif defined(VBOX_WITH_MSI_DEVICES)
4943	PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
4944	#else
4945	PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
4946	#endif
4947
4948	/// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
4949	/// of these values needs to be properly documented!
4950	/* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
4951	PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
4952
4953	/* Power Management */
4954	PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
4955	PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
4956	PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI \| 0x02 /* version, PM1.1 */ );
4957
4958	#ifdef HDA_AS_PCI_EXPRESS
4959	/* PCI Express */
4960	PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
4961	PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
4962	/* Device flags */
4963	PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
4964	/* version */ 0x1 \|
4965	/* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) \|
4966	/* MSI */ (100) << 9 );
4967	/* Device capabilities */
4968	PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
4969	/* Device control */
4970	PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
4971	/* Device status */
4972	PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
4973	/* Link caps */
4974	PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
4975	/* Link control */
4976	PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
4977	/* Link status */
4978	PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
4979	/* Slot capabilities */
4980	PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
4981	/* Slot control */
4982	PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
4983	/* Slot status */
4984	PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
4985	/* Root control */
4986	PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
4987	/* Root capabilities */
4988	PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
4989	/* Root status */
4990	PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
4991	/* Device capabilities 2 */
4992	PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
4993	/* Device control 2 */
4994	PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
4995	/* Link control 2 */
4996	PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
4997	/* Slot control 2 */
4998	PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
4999	#endif
5000
5001	/*
5002	* Register the PCI device.
5003	*/
5004	rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
5005	if (RT_FAILURE(rc))
5006	return rc;
5007
5008	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaPciIoRegionMap);
5009	if (RT_FAILURE(rc))
5010	return rc;
5011
5012	#ifdef VBOX_WITH_MSI_DEVICES
5013	PDMMSIREG MsiReg;
5014	RT_ZERO(MsiReg);
5015	MsiReg.cMsiVectors = 1;
5016	MsiReg.iMsiCapOffset = 0x60;
5017	MsiReg.iMsiNextOffset = 0x50;
5018	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5019	if (RT_FAILURE(rc))
5020	{
5021	/* That's OK, we can work without MSI */
5022	PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
5023	}
5024	#endif
5025
5026	rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaSaveExec, hdaLoadExec);
5027	if (RT_FAILURE(rc))
5028	return rc;
5029
5030	RTListInit(&pThis->lstDrv);
5031
5032	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
5033	LogRel(("HDA: Asynchronous I/O enabled\n"));
5034	#endif
5035
5036	uint8_t uLUN;
5037	for (uLUN = 0; uLUN < UINT8_MAX; ++uLUN)
5038	{
5039	LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
5040	rc = hdaAttachInternal(pThis, uLUN, 0 /* fFlags /, NULL / ppDrv */);
5041	if (RT_FAILURE(rc))
5042	{
5043	if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5044	rc = VINF_SUCCESS;
5045	else if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
5046	{
5047	hdaReattachInternal(pThis, NULL /* pDrv */, uLUN, "NullAudio");
5048	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
5049	N_("Host audio backend initialization has failed. Selecting the NULL audio backend "
5050	"with the consequence that no sound is audible"));
5051	/* Attaching to the NULL audio backend will never fail. */
5052	rc = VINF_SUCCESS;
5053	}
5054	break;
5055	}
5056	}
5057
5058	LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
5059
5060	if (RT_SUCCESS(rc))
5061	{
5062	rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
5063	if (RT_SUCCESS(rc))
5064	{
5065	/*
5066	* Add mixer output sinks.
5067	*/
5068	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
5069	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Front",
5070	AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
5071	AssertRC(rc);
5072	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Center / Subwoofer",
5073	AUDMIXSINKDIR_OUTPUT, &pThis->SinkCenterLFE.pMixSink);
5074	AssertRC(rc);
5075	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Rear",
5076	AUDMIXSINKDIR_OUTPUT, &pThis->SinkRear.pMixSink);
5077	AssertRC(rc);
5078	#else
5079	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] PCM Output",
5080	AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
5081	AssertRC(rc);
5082	#endif
5083	/*
5084	* Add mixer input sinks.
5085	*/
5086	rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Line In",
5087	AUDMIXSINKDIR_INPUT, &pThis->SinkLineIn.pMixSink);
5088	AssertRC(rc);
5089	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5090	rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Microphone In",
5091	AUDMIXSINKDIR_INPUT, &pThis->SinkMicIn.pMixSink);
5092	AssertRC(rc);
5093	#endif
5094	/* There is no master volume control. Set the master to max. */
5095	PDMAUDIOVOLUME vol = { false, 255, 255 };
5096	rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
5097	AssertRC(rc);
5098	}
5099	}
5100
5101	if (RT_SUCCESS(rc))
5102	{
5103	/* Construct codec. */
5104	pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
5105	if (!pThis->pCodec)
5106	return PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
5107
5108	/* Set codec callbacks to this controller. */
5109	pThis->pCodec->pfnCbMixerAddStream = hdaMixerAddStream;
5110	pThis->pCodec->pfnCbMixerRemoveStream = hdaMixerRemoveStream;
5111	pThis->pCodec->pfnCbMixerControl = hdaMixerControl;
5112	pThis->pCodec->pfnCbMixerSetVolume = hdaMixerSetVolume;
5113
5114	pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
5115
5116	/* Construct the codec. */
5117	rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfg);
5118	if (RT_FAILURE(rc))
5119	AssertRCReturn(rc, rc);
5120
5121	/* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
5122	verb F20 should provide device/codec recognition. */
5123	Assert(pThis->pCodec->u16VendorId);
5124	Assert(pThis->pCodec->u16DeviceId);
5125	PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
5126	PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
5127	}
5128
5129	if (RT_SUCCESS(rc))
5130	{
5131	/*
5132	* Create all hardware streams.
5133	*/
5134	for (uint8_t i = 0; i < HDA_MAX_STREAMS; ++i)
5135	{
5136	rc = hdaStreamCreate(&pThis->aStreams[i], pThis, i /* u8SD */);
5137	AssertRC(rc);
5138	}
5139
5140	#ifdef VBOX_WITH_AUDIO_HDA_ONETIME_INIT
5141	/*
5142	* Initialize the driver chain.
5143	*/
5144	PHDADRIVER pDrv;
5145	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
5146	{
5147	/*
5148	* Only primary drivers are critical for the VM to run. Everything else
5149	* might not worth showing an own error message box in the GUI.
5150	*/
5151	if (!(pDrv->fFlags & PDMAUDIODRVFLAGS_PRIMARY))
5152	continue;
5153
5154	PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
5155	AssertPtr(pCon);
5156
5157	bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
5158	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5159	bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
5160	# endif
5161	bool fValidOut = AudioMixerStreamIsValid(pDrv->Front.pMixStrm);
5162	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
5163	/** @todo Anything to do here? */
5164	# endif
5165
5166	if ( !fValidLineIn
5167	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5168	&& !fValidMicIn
5169	# endif
5170	&& !fValidOut)
5171	{
5172	LogRel(("HDA: Falling back to NULL backend (no sound audible)\n"));
5173
5174	hdaReset(pDevIns);
5175	hdaReattachInternal(pThis, pDrv, pDrv->uLUN, "NullAudio");
5176
5177	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
5178	N_("No audio devices could be opened. Selecting the NULL audio backend "
5179	"with the consequence that no sound is audible"));
5180	}
5181	else
5182	{
5183	bool fWarn = false;
5184
5185	PDMAUDIOBACKENDCFG backendCfg;
5186	int rc2 = pCon->pfnGetConfig(pCon, &backendCfg);
5187	if (RT_SUCCESS(rc2))
5188	{
5189	if (backendCfg.cMaxStreamsIn)
5190	{
5191	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5192	/* If the audio backend supports two or more input streams at once,
5193	* warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
5194	if (backendCfg.cMaxStreamsIn >= 2)
5195	fWarn = !fValidLineIn \|\| !fValidMicIn;
5196	/* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
5197	* not ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
5198	* One of the two simply is not in use then. */
5199	else if (backendCfg.cMaxStreamsIn == 1)
5200	fWarn = !fValidLineIn && !fValidMicIn;
5201	/* Don't warn if our backend is not able of supporting any input streams at all. */
5202	# else /* !VBOX_WITH_AUDIO_HDA_MIC_IN */
5203	/* We only have line-in as input source. */
5204	fWarn = !fValidLineIn;
5205	# endif /* VBOX_WITH_AUDIO_HDA_MIC_IN */
5206	}
5207
5208	if ( !fWarn
5209	&& backendCfg.cMaxStreamsOut)
5210	{
5211	fWarn = !fValidOut;
5212	}
5213	}
5214	else
5215	{
5216	LogRel(("HDA: Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
5217	fWarn = true;
5218	}
5219
5220	if (fWarn)
5221	{
5222	char szMissingStreams[255];
5223	size_t len = 0;
5224	if (!fValidLineIn)
5225	{
5226	LogRel(("HDA: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
5227	len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
5228	}
5229	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5230	if (!fValidMicIn)
5231	{
5232	LogRel(("HDA: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
5233	len += RTStrPrintf(szMissingStreams + len,
5234	sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
5235	}
5236	# endif /* VBOX_WITH_AUDIO_HDA_MIC_IN */
5237	if (!fValidOut)
5238	{
5239	LogRel(("HDA: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
5240	len += RTStrPrintf(szMissingStreams + len,
5241	sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
5242	}
5243
5244	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
5245	N_("Some HDA audio streams (%s) could not be opened. Guest applications generating audio "
5246	"output or depending on audio input may hang. Make sure your host audio device "
5247	"is working properly. Check the logfile for error messages of the audio "
5248	"subsystem"), szMissingStreams);
5249	}
5250	}
5251	}
5252	#endif /* VBOX_WITH_AUDIO_HDA_ONETIME_INIT */
5253	}
5254
5255	if (RT_SUCCESS(rc))
5256	{
5257	hdaReset(pDevIns);
5258
5259	/*
5260	* Debug and string formatter types.
5261	*/
5262	PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaDbgInfo);
5263	PDMDevHlpDBGFInfoRegister(pDevIns, "hdabdle", "HDA stream BDLE info. (hdabdle [stream number])", hdaDbgInfoBDLE);
5264	PDMDevHlpDBGFInfoRegister(pDevIns, "hdastream", "HDA stream info. (hdastream [stream number])", hdaDbgInfoStream);
5265	PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaDbgInfoCodecNodes);
5266	PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaDbgInfoCodecSelector);
5267	PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaDbgInfoMixer);
5268
5269	rc = RTStrFormatTypeRegister("bdle", hdaDbgFmtBDLE, NULL);
5270	AssertRC(rc);
5271	rc = RTStrFormatTypeRegister("sdctl", hdaDbgFmtSDCTL, NULL);
5272	AssertRC(rc);
5273	rc = RTStrFormatTypeRegister("sdsts", hdaDbgFmtSDSTS, NULL);
5274	AssertRC(rc);
5275	rc = RTStrFormatTypeRegister("sdfifos", hdaDbgFmtSDFIFOS, NULL);
5276	AssertRC(rc);
5277	rc = RTStrFormatTypeRegister("sdfifow", hdaDbgFmtSDFIFOW, NULL);
5278	AssertRC(rc);
5279
5280	/*
5281	* Some debug assertions.
5282	*/
5283	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
5284	{
5285	struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
5286	struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
5287
5288	/* binary search order. */
5289	AssertReleaseMsg(!pNextReg \|\| pReg->offset + pReg->size <= pNextReg->offset,
5290	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5291	i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
5292
5293	/* alignment. */
5294	AssertReleaseMsg( pReg->size == 1
5295	\|\| (pReg->size == 2 && (pReg->offset & 1) == 0)
5296	\|\| (pReg->size == 3 && (pReg->offset & 3) == 0)
5297	\|\| (pReg->size == 4 && (pReg->offset & 3) == 0),
5298	("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5299
5300	/* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
5301	AssertRelease(((pReg->offset + pReg->size) & 3) == 0 \|\| pNextReg);
5302	if (pReg->offset & 3)
5303	{
5304	struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
5305	AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5306	if (pPrevReg)
5307	AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
5308	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5309	i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
5310	}
5311	#if 0
5312	if ((pReg->offset + pReg->size) & 3)
5313	{
5314	AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5315	if (pNextReg)
5316	AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
5317	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5318	i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
5319	}
5320	#endif
5321	/* The final entry is a full DWORD, no gaps! Allows shortcuts. */
5322	AssertReleaseMsg(pNextReg \|\| ((pReg->offset + pReg->size) & 3) == 0,
5323	("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5324	}
5325	}
5326
5327	if (RT_SUCCESS(rc))
5328	{
5329	/* Create the emulation timer.
5330	*
5331	* Note: Use TMCLOCK_VIRTUAL_SYNC here, as the guest's HDA driver
5332	* relies on exact (virtual) DMA timing and uses DMA Position Buffers
5333	* instead of the LPIB registers.
5334	*/
5335	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, hdaTimer, pThis,
5336	TMTIMER_FLAGS_NO_CRIT_SECT, "HDA Timer", &pThis->pTimer);
5337	AssertRCReturn(rc, rc);
5338
5339	/* Use our own critcal section for the device timer.
5340	* That way we can control more fine-grained when to lock what. */
5341	rc = TMR3TimerSetCritSect(pThis->pTimer, &pThis->CritSect);
5342	AssertRCReturn(rc, rc);
5343	}
5344
5345	# ifdef VBOX_WITH_STATISTICS
5346	if (RT_SUCCESS(rc))
5347	{
5348	/*
5349	* Register statistics.
5350	*/
5351	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaTimer.");
5352	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIn, STAMTYPE_PROFILE, "/Devices/HDA/Input", STAMUNIT_TICKS_PER_CALL, "Profiling input.");
5353	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatOut, STAMTYPE_PROFILE, "/Devices/HDA/Output", STAMUNIT_TICKS_PER_CALL, "Profiling output.");
5354	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
5355	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
5356	}
5357	# endif
5358
5359	LogFlowFuncLeaveRC(rc);
5360	return rc;
5361	}
5362
5363	/**
5364	* The device registration structure.
5365	*/
5366	const PDMDEVREG g_DeviceHDA =
5367	{
5368	/* u32Version */
5369	PDM_DEVREG_VERSION,
5370	/* szName */
5371	"hda",
5372	/* szRCMod */
5373	"VBoxDDRC.rc",
5374	/* szR0Mod */
5375	"VBoxDDR0.r0",
5376	/* pszDescription */
5377	"Intel HD Audio Controller",
5378	/* fFlags */
5379	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
5380	/* fClass */
5381	PDM_DEVREG_CLASS_AUDIO,
5382	/* cMaxInstances */
5383	1,
5384	/* cbInstance */
5385	sizeof(HDASTATE),
5386	/* pfnConstruct */
5387	hdaConstruct,
5388	/* pfnDestruct */
5389	hdaDestruct,
5390	/* pfnRelocate */
5391	NULL,
5392	/* pfnMemSetup */
5393	NULL,
5394	/* pfnPowerOn */
5395	NULL,
5396	/* pfnReset */
5397	hdaReset,
5398	/* pfnSuspend */
5399	NULL,
5400	/* pfnResume */
5401	NULL,
5402	/* pfnAttach */
5403	hdaAttach,
5404	/* pfnDetach */
5405	hdaDetach,
5406	/* pfnQueryInterface. */
5407	NULL,
5408	/* pfnInitComplete */
5409	NULL,
5410	/* pfnPowerOff */
5411	hdaPowerOff,
5412	/* pfnSoftReset */
5413	NULL,
5414	/* u32VersionEnd */
5415	PDM_DEVREG_VERSION
5416	};
5417
5418	#endif /* IN_RING3 */
5419	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5420

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source: vbox/trunk/src/VBox/Devices/Audio/DevHDA.cpp@ 70905

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