DevHDA.cpp@ 73838

Last change on this file since 73838 was 73838, checked in by vboxsync, 6 years ago
Audio: Added the backend's (friendly) name into the backend configuration.
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1	/* $Id: DevHDA.cpp 73838 2018-08-22 16:15:08Z vboxsync $ */
2	/** @file
3	* DevHDA.cpp - VBox Intel HD Audio Controller.
4	*
5	* Implemented against the specifications found in "High Definition Audio
6	* Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7	* HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8	*/
9
10	/*
11	* Copyright (C) 2006-2018 Oracle Corporation
12	*
13	* This file is part of VirtualBox Open Source Edition (OSE), as
14	* available from http://www.virtualbox.org. This file is free software;
15	* you can redistribute it and/or modify it under the terms of the GNU
16	* General Public License (GPL) as published by the Free Software
17	* Foundation, in version 2 as it comes in the "COPYING" file of the
18	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20	*/
21
22
23	/*********************************************************************************************************************************
24	* Header Files *
25	*********************************************************************************************************************************/
26	#define LOG_GROUP LOG_GROUP_DEV_HDA
27	#include <VBox/log.h>
28
29	#include <VBox/vmm/pdmdev.h>
30	#include <VBox/vmm/pdmaudioifs.h>
31	#include <VBox/version.h>
32	#include <VBox/AssertGuest.h>
33
34	#include <iprt/assert.h>
35	#include <iprt/asm.h>
36	#include <iprt/asm-math.h>
37	#include <iprt/file.h>
38	#include <iprt/list.h>
39	#ifdef IN_RING3
40	# include <iprt/mem.h>
41	# include <iprt/semaphore.h>
42	# include <iprt/string.h>
43	# include <iprt/uuid.h>
44	#endif
45
46	#include "VBoxDD.h"
47
48	#include "AudioMixBuffer.h"
49	#include "AudioMixer.h"
50
51	#include "DevHDA.h"
52	#include "DevHDACommon.h"
53
54	#include "HDACodec.h"
55	#include "HDAStream.h"
56	# if defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT) \|\| defined(VBOX_WITH_AUDIO_HDA_51_SURROUND)
57	# include "HDAStreamChannel.h"
58	# endif
59	#include "HDAStreamMap.h"
60	#include "HDAStreamPeriod.h"
61
62	#include "DrvAudio.h"
63
64
65	/*********************************************************************************************************************************
66	* Defined Constants And Macros *
67	*********************************************************************************************************************************/
68	//#define HDA_AS_PCI_EXPRESS
69
70	/* Installs a DMA access handler (via PGM callback) to monitor
71	* HDA's DMA operations, that is, writing / reading audio stream data.
72	*
73	* !!! Note: Certain guests are that timing sensitive that when enabling !!!
74	* !!! such a handler will mess up audio completely (e.g. Windows 7). !!! */
75	//#define HDA_USE_DMA_ACCESS_HANDLER
76	#ifdef HDA_USE_DMA_ACCESS_HANDLER
77	# include <VBox/vmm/pgm.h>
78	#endif
79
80	/* Uses the DMA access handler to read the written DMA audio (output) data.
81	* Only valid if HDA_USE_DMA_ACCESS_HANDLER is set.
82	*
83	* Also see the note / warning for HDA_USE_DMA_ACCESS_HANDLER. */
84	//# define HDA_USE_DMA_ACCESS_HANDLER_WRITING
85
86	/* Useful to debug the device' timing. */
87	//#define HDA_DEBUG_TIMING
88
89	/* To debug silence coming from the guest in form of audio gaps.
90	* Very crude implementation for now. */
91	//#define HDA_DEBUG_SILENCE
92
93	#if defined(VBOX_WITH_HP_HDA)
94	/* HP Pavilion dv4t-1300 */
95	# define HDA_PCI_VENDOR_ID 0x103c
96	# define HDA_PCI_DEVICE_ID 0x30f7
97	#elif defined(VBOX_WITH_INTEL_HDA)
98	/* Intel HDA controller */
99	# define HDA_PCI_VENDOR_ID 0x8086
100	# define HDA_PCI_DEVICE_ID 0x2668
101	#elif defined(VBOX_WITH_NVIDIA_HDA)
102	/* nVidia HDA controller */
103	# define HDA_PCI_VENDOR_ID 0x10de
104	# define HDA_PCI_DEVICE_ID 0x0ac0
105	#else
106	# error "Please specify your HDA device vendor/device IDs"
107	#endif
108
109	/* Make sure that interleaving streams support is enabled if the 5.1 surround code is being used. */
110	#if defined (VBOX_WITH_AUDIO_HDA_51_SURROUND) && !defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT)
111	# define VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT
112	#endif
113
114	/**
115	* Acquires the HDA lock.
116	*/
117	#define DEVHDA_LOCK(a_pThis) \
118	do { \
119	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
120	AssertRC(rcLock); \
121	} while (0)
122
123	/**
124	* Acquires the HDA lock or returns.
125	*/
126	# define DEVHDA_LOCK_RETURN(a_pThis, a_rcBusy) \
127	do { \
128	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, a_rcBusy); \
129	if (rcLock != VINF_SUCCESS) \
130	{ \
131	AssertRC(rcLock); \
132	return rcLock; \
133	} \
134	} while (0)
135
136	/**
137	* Acquires the HDA lock or returns.
138	*/
139	# define DEVHDA_LOCK_RETURN_VOID(a_pThis) \
140	do { \
141	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
142	if (rcLock != VINF_SUCCESS) \
143	{ \
144	AssertRC(rcLock); \
145	return; \
146	} \
147	} while (0)
148
149	/**
150	* Releases the HDA lock.
151	*/
152	#define DEVHDA_UNLOCK(a_pThis) \
153	do { PDMCritSectLeave(&(a_pThis)->CritSect); } while (0)
154
155	/**
156	* Acquires the TM lock and HDA lock, returns on failure.
157	*/
158	#define DEVHDA_LOCK_BOTH_RETURN_VOID(a_pThis, a_SD) \
159	do { \
160	int rcLock = TMTimerLock((a_pThis)->pTimer[a_SD], VERR_IGNORED); \
161	if (rcLock != VINF_SUCCESS) \
162	{ \
163	AssertRC(rcLock); \
164	return; \
165	} \
166	rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
167	if (rcLock != VINF_SUCCESS) \
168	{ \
169	AssertRC(rcLock); \
170	TMTimerUnlock((a_pThis)->pTimer[a_SD]); \
171	return; \
172	} \
173	} while (0)
174
175	/**
176	* Acquires the TM lock and HDA lock, returns on failure.
177	*/
178	#define DEVHDA_LOCK_BOTH_RETURN(a_pThis, a_SD, a_rcBusy) \
179	do { \
180	int rcLock = TMTimerLock((a_pThis)->pTimer[a_SD], (a_rcBusy)); \
181	if (rcLock != VINF_SUCCESS) \
182	return rcLock; \
183	rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, (a_rcBusy)); \
184	if (rcLock != VINF_SUCCESS) \
185	{ \
186	AssertRC(rcLock); \
187	TMTimerUnlock((a_pThis)->pTimer[a_SD]); \
188	return rcLock; \
189	} \
190	} while (0)
191
192	/**
193	* Releases the HDA lock and TM lock.
194	*/
195	#define DEVHDA_UNLOCK_BOTH(a_pThis, a_SD) \
196	do { \
197	PDMCritSectLeave(&(a_pThis)->CritSect); \
198	TMTimerUnlock((a_pThis)->pTimer[a_SD]); \
199	} while (0)
200
201
202	/*********************************************************************************************************************************
203	* Structures and Typedefs *
204	*********************************************************************************************************************************/
205
206	/**
207	* Structure defining a (host backend) driver stream.
208	* Each driver has its own instances of audio mixer streams, which then
209	* can go into the same (or even different) audio mixer sinks.
210	*/
211	typedef struct HDADRIVERSTREAM
212	{
213	union
214	{
215	/** Desired playback destination (for an output stream). */
216	PDMAUDIOPLAYBACKDEST Dest;
217	/** Desired recording source (for an input stream). */
218	PDMAUDIORECSOURCE Source;
219	} DestSource;
220	uint8_t Padding1[4];
221	/** Associated mixer handle. */
222	R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
223	} HDADRIVERSTREAM, *PHDADRIVERSTREAM;
224
225	#ifdef HDA_USE_DMA_ACCESS_HANDLER
226	/**
227	* Struct for keeping an HDA DMA access handler context.
228	*/
229	typedef struct HDADMAACCESSHANDLER
230	{
231	/** Node for storing this handler in our list in HDASTREAMSTATE. */
232	RTLISTNODER3 Node;
233	/** Pointer to stream to which this access handler is assigned to. */
234	R3PTRTYPE(PHDASTREAM) pStream;
235	/** Access handler type handle. */
236	PGMPHYSHANDLERTYPE hAccessHandlerType;
237	/** First address this handler uses. */
238	RTGCPHYS GCPhysFirst;
239	/** Last address this handler uses. */
240	RTGCPHYS GCPhysLast;
241	/** Actual BDLE address to handle. */
242	RTGCPHYS BDLEAddr;
243	/** Actual BDLE buffer size to handle. */
244	RTGCPHYS BDLESize;
245	/** Whether the access handler has been registered or not. */
246	bool fRegistered;
247	uint8_t Padding[3];
248	} HDADMAACCESSHANDLER, *PHDADMAACCESSHANDLER;
249	#endif
250
251	/**
252	* Struct for maintaining a host backend driver.
253	* This driver must be associated to one, and only one,
254	* HDA codec. The HDA controller does the actual multiplexing
255	* of HDA codec data to various host backend drivers then.
256	*
257	* This HDA device uses a timer in order to synchronize all
258	* read/write accesses across all attached LUNs / backends.
259	*/
260	typedef struct HDADRIVER
261	{
262	/** Node for storing this driver in our device driver list of HDASTATE. */
263	RTLISTNODER3 Node;
264	/** Pointer to HDA controller (state). */
265	R3PTRTYPE(PHDASTATE) pHDAState;
266	/** Driver flags. */
267	PDMAUDIODRVFLAGS fFlags;
268	uint8_t u32Padding0[2];
269	/** LUN to which this driver has been assigned. */
270	uint8_t uLUN;
271	/** Whether this driver is in an attached state or not. */
272	bool fAttached;
273	/** Pointer to attached driver base interface. */
274	R3PTRTYPE(PPDMIBASE) pDrvBase;
275	/** Audio connector interface to the underlying host backend. */
276	R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
277	/** Mixer stream for line input. */
278	HDADRIVERSTREAM LineIn;
279	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
280	/** Mixer stream for mic input. */
281	HDADRIVERSTREAM MicIn;
282	#endif
283	/** Mixer stream for front output. */
284	HDADRIVERSTREAM Front;
285	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
286	/** Mixer stream for center/LFE output. */
287	HDADRIVERSTREAM CenterLFE;
288	/** Mixer stream for rear output. */
289	HDADRIVERSTREAM Rear;
290	#endif
291	} HDADRIVER;
292
293
294	/*********************************************************************************************************************************
295	* Internal Functions *
296	*********************************************************************************************************************************/
297	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
298	#ifdef IN_RING3
299	static void hdaR3GCTLReset(PHDASTATE pThis);
300	#endif
301
302	/** @name Register read/write stubs.
303	* @{
304	*/
305	static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
306	static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
307	/** @} */
308
309	/** @name Global register set read/write functions.
310	* @{
311	*/
312	static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
313	static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
314	static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
315	static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
316	static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
317	static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
318	static int hdaRegWriteCORBSIZE(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
319	static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
320	static int hdaRegWriteRINTCNT(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
321	static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
322	static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
323	static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
324	static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
325	static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
326	static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
327	/** @} */
328
329	/** @name {IOB}SDn write functions.
330	* @{
331	*/
332	static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
333	static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
334	static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
335	static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
336	static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
337	static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
338	static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
339	static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
340	static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
341	/** @} */
342
343	/** @name Generic register read/write functions.
344	* @{
345	*/
346	static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
347	static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
348	static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
349	#ifdef IN_RING3
350	static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
351	#endif
352	static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
353	static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
354	static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
355	static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
356	/** @} */
357
358	/** @name HDA device functions.
359	* @{
360	*/
361	#ifdef IN_RING3
362	static int hdaR3AddStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg);
363	static int hdaR3RemoveStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg);
364	static int hdaR3UpdateStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg);
365	# ifdef HDA_USE_DMA_ACCESS_HANDLER
366	static DECLCALLBACK(VBOXSTRICTRC) hdaR3DMAAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys,
367	void *pvBuf, size_t cbBuf,
368	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser);
369	# endif
370	#endif /* IN_RING3 */
371	/** @} */
372
373
374	/*********************************************************************************************************************************
375	* Global Variables *
376	*********************************************************************************************************************************/
377
378	/** No register description (RD) flags defined. */
379	#define HDA_RD_FLAG_NONE 0
380	/** Writes to SD are allowed while RUN bit is set. */
381	#define HDA_RD_FLAG_SD_WRITE_RUN RT_BIT(0)
382
383	/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
384	#define HDA_REG_MAP_STRM(offset, name) \
385	/* offset size read mask write mask flags read callback write callback index + abbrev description */ \
386	/* ------- ------- ---------- ---------- ------------------------- -------------- ----------------- ----------------------------- ----------- */ \
387	/* Offset 0x80 (SD0) */ \
388	{ offset, 0x00003, 0x00FF001F, 0x00F0001F, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL) , #name " Stream Descriptor Control" }, \
389	/* Offset 0x83 (SD0) */ \
390	{ offset + 0x3, 0x00001, 0x0000003C, 0x0000001C, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU8 , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS) , #name " Status" }, \
391	/* Offset 0x84 (SD0) */ \
392	{ offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadLPIB, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
393	/* Offset 0x88 (SD0) */ \
394	{ offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDCBL , HDA_REG_IDX_STRM(name, CBL) , #name " Cyclic Buffer Length" }, \
395	/* Offset 0x8C (SD0) */ \
396	{ offset + 0xC, 0x00002, 0x0000FFFF, 0x0000FFFF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDLVI , HDA_REG_IDX_STRM(name, LVI) , #name " Last Valid Index" }, \
397	/* Reserved: FIFO Watermark. ** @todo Document this! */ \
398	{ offset + 0xE, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
399	/* Offset 0x90 (SD0) */ \
400	{ offset + 0x10, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
401	/* Offset 0x92 (SD0) */ \
402	{ offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFMT , HDA_REG_IDX_STRM(name, FMT) , #name " Stream Format" }, \
403	/* Reserved: 0x94 - 0x98. */ \
404	/* Offset 0x98 (SD0) */ \
405	{ offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
406	/* Offset 0x9C (SD0) */ \
407	{ offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
408
409	/** Defines a single audio stream register set (e.g. OSD0). */
410	#define HDA_REG_MAP_DEF_STREAM(index, name) \
411	HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
412
413	/* See 302349 p 6.2. */
414	const HDAREGDESC g_aHdaRegMap[HDA_NUM_REGS] =
415	{
416	/* offset size read mask write mask flags read callback write callback index + abbrev */
417	/------- ------- ---------- ---------- ----------------- ---------------- ------------------- ------------------------ /
418	{ 0x00000, 0x00002, 0x0000FFFB, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(GCAP) }, /* Global Capabilities */
419	{ 0x00002, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMIN) }, /* Minor Version */
420	{ 0x00003, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMAJ) }, /* Major Version */
421	{ 0x00004, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTPAY) }, /* Output Payload Capabilities */
422	{ 0x00006, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INPAY) }, /* Input Payload Capabilities */
423	{ 0x00008, 0x00004, 0x00000103, 0x00000103, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteGCTL , HDA_REG_IDX(GCTL) }, /* Global Control */
424	{ 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(WAKEEN) }, /* Wake Enable */
425	{ 0x0000e, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteSTATESTS, HDA_REG_IDX(STATESTS) }, /* State Change Status */
426	{ 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadUnimpl, hdaRegWriteUnimpl , HDA_REG_IDX(GSTS) }, /* Global Status */
427	{ 0x00018, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTSTRMPAY) }, /* Output Stream Payload Capability */
428	{ 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INSTRMPAY) }, /* Input Stream Payload Capability */
429	{ 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */
430	{ 0x00024, 0x00004, 0xC00000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */
431	{ 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadWALCLK, hdaRegWriteUnimpl , HDA_REG_IDX_NOMEM(WALCLK) }, /* Wall Clock Counter */
432	{ 0x00034, 0x00004, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */
433	{ 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
434	{ 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBUBASE) }, /* CORB Upper Base Address */
435	{ 0x00048, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteCORBWP , HDA_REG_IDX(CORBWP) }, /* CORB Write Pointer */
436	{ 0x0004A, 0x00002, 0x000080FF, 0x00008000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteCORBRP , HDA_REG_IDX(CORBRP) }, /* CORB Read Pointer */
437	{ 0x0004C, 0x00001, 0x00000003, 0x00000003, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL) }, /* CORB Control */
438	{ 0x0004D, 0x00001, 0x00000001, 0x00000001, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS) }, /* CORB Status */
439	{ 0x0004E, 0x00001, 0x000000F3, 0x00000003, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBSIZE, HDA_REG_IDX(CORBSIZE) }, /* CORB Size */
440	{ 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBLBASE) }, /* RIRB Lower Base Address */
441	{ 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBUBASE) }, /* RIRB Upper Base Address */
442	{ 0x00058, 0x00002, 0x000000FF, 0x00008000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteRIRBWP , HDA_REG_IDX(RIRBWP) }, /* RIRB Write Pointer */
443	{ 0x0005A, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteRINTCNT , HDA_REG_IDX(RINTCNT) }, /* Response Interrupt Count */
444	{ 0x0005C, 0x00001, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteU8 , HDA_REG_IDX(RIRBCTL) }, /* RIRB Control */
445	{ 0x0005D, 0x00001, 0x00000005, 0x00000005, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS) }, /* RIRB Status */
446	{ 0x0005E, 0x00001, 0x000000F3, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(RIRBSIZE) }, /* RIRB Size */
447	{ 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(IC) }, /* Immediate Command */
448	{ 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(IR) }, /* Immediate Response */
449	{ 0x00068, 0x00002, 0x00000002, 0x00000002, HDA_RD_FLAG_NONE, hdaRegReadIRS , hdaRegWriteIRS , HDA_REG_IDX(IRS) }, /* Immediate Command Status */
450	{ 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPLBASE) }, /* DMA Position Lower Base */
451	{ 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPUBASE) }, /* DMA Position Upper Base */
452	/* 4 Serial Data In (SDI). */
453	HDA_REG_MAP_DEF_STREAM(0, SD0),
454	HDA_REG_MAP_DEF_STREAM(1, SD1),
455	HDA_REG_MAP_DEF_STREAM(2, SD2),
456	HDA_REG_MAP_DEF_STREAM(3, SD3),
457	/* 4 Serial Data Out (SDO). */
458	HDA_REG_MAP_DEF_STREAM(4, SD4),
459	HDA_REG_MAP_DEF_STREAM(5, SD5),
460	HDA_REG_MAP_DEF_STREAM(6, SD6),
461	HDA_REG_MAP_DEF_STREAM(7, SD7)
462	};
463
464	const HDAREGALIAS g_aHdaRegAliases[] =
465	{
466	{ 0x2084, HDA_REG_SD0LPIB },
467	{ 0x20a4, HDA_REG_SD1LPIB },
468	{ 0x20c4, HDA_REG_SD2LPIB },
469	{ 0x20e4, HDA_REG_SD3LPIB },
470	{ 0x2104, HDA_REG_SD4LPIB },
471	{ 0x2124, HDA_REG_SD5LPIB },
472	{ 0x2144, HDA_REG_SD6LPIB },
473	{ 0x2164, HDA_REG_SD7LPIB }
474	};
475
476	#ifdef IN_RING3
477
478	/** HDABDLEDESC field descriptors for the v7 saved state. */
479	static SSMFIELD const g_aSSMBDLEDescFields7[] =
480	{
481	SSMFIELD_ENTRY(HDABDLEDESC, u64BufAdr),
482	SSMFIELD_ENTRY(HDABDLEDESC, u32BufSize),
483	SSMFIELD_ENTRY(HDABDLEDESC, fFlags),
484	SSMFIELD_ENTRY_TERM()
485	};
486
487	/** HDABDLESTATE field descriptors for the v6+ saved state. */
488	static SSMFIELD const g_aSSMBDLEStateFields6[] =
489	{
490	SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
491	SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
492	SSMFIELD_ENTRY_OLD(FIFO, HDA_FIFO_MAX), /* Deprecated; now is handled in the stream's circular buffer. */
493	SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
494	SSMFIELD_ENTRY_TERM()
495	};
496
497	/** HDABDLESTATE field descriptors for the v7 saved state. */
498	static SSMFIELD const g_aSSMBDLEStateFields7[] =
499	{
500	SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
501	SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
502	SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
503	SSMFIELD_ENTRY_TERM()
504	};
505
506	/** HDASTREAMSTATE field descriptors for the v6 saved state. */
507	static SSMFIELD const g_aSSMStreamStateFields6[] =
508	{
509	SSMFIELD_ENTRY_OLD(cBDLE, sizeof(uint16_t)), /* Deprecated. */
510	SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
511	SSMFIELD_ENTRY_OLD(fStop, 1), /* Deprecated; see SSMR3PutBool(). */
512	SSMFIELD_ENTRY_OLD(fRunning, 1), /* Deprecated; using the HDA_SDCTL_RUN bit is sufficient. */
513	SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
514	SSMFIELD_ENTRY_TERM()
515	};
516
517	/** HDASTREAMSTATE field descriptors for the v7 saved state. */
518	static SSMFIELD const g_aSSMStreamStateFields7[] =
519	{
520	SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
521	SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
522	SSMFIELD_ENTRY(HDASTREAMSTATE, tsTransferNext),
523	SSMFIELD_ENTRY_TERM()
524	};
525
526	/** HDASTREAMPERIOD field descriptors for the v7 saved state. */
527	static SSMFIELD const g_aSSMStreamPeriodFields7[] =
528	{
529	SSMFIELD_ENTRY(HDASTREAMPERIOD, u64StartWalClk),
530	SSMFIELD_ENTRY(HDASTREAMPERIOD, u64ElapsedWalClk),
531	SSMFIELD_ENTRY(HDASTREAMPERIOD, framesTransferred),
532	SSMFIELD_ENTRY(HDASTREAMPERIOD, cIntPending),
533	SSMFIELD_ENTRY_TERM()
534	};
535
536	/**
537	* 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
538	*/
539	static uint32_t const g_afMasks[5] =
540	{
541	UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
542	};
543
544	#endif /* IN_RING3 */
545
546
547
548	/**
549	* Retrieves the number of bytes of a FIFOW register.
550	*
551	* @return Number of bytes of a given FIFOW register.
552	*/
553	DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
554	{
555	uint32_t cb;
556	switch (u32RegFIFOW)
557	{
558	case HDA_SDFIFOW_8B: cb = 8; break;
559	case HDA_SDFIFOW_16B: cb = 16; break;
560	case HDA_SDFIFOW_32B: cb = 32; break;
561	default: cb = 0; break;
562	}
563
564	Assert(RT_IS_POWER_OF_TWO(cb));
565	return cb;
566	}
567
568	#ifdef IN_RING3
569	/**
570	* Reschedules pending interrupts for all audio streams which have complete
571	* audio periods but did not have the chance to issue their (pending) interrupts yet.
572	*
573	* @param pThis The HDA device state.
574	*/
575	static void hdaR3ReschedulePendingInterrupts(PHDASTATE pThis)
576	{
577	bool fInterrupt = false;
578
579	for (uint8_t i = 0; i < HDA_MAX_STREAMS; ++i)
580	{
581	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, i);
582	if (!pStream)
583	continue;
584
585	if ( hdaR3StreamPeriodIsComplete (&pStream->State.Period)
586	&& hdaR3StreamPeriodNeedsInterrupt(&pStream->State.Period)
587	&& hdaR3WalClkSet(pThis, hdaR3StreamPeriodGetAbsElapsedWalClk(&pStream->State.Period), false /* fForce */))
588	{
589	fInterrupt = true;
590	break;
591	}
592	}
593
594	LogFunc(("fInterrupt=%RTbool\n", fInterrupt));
595
596	# ifndef LOG_ENABLED
597	hdaProcessInterrupt(pThis);
598	# else
599	hdaProcessInterrupt(pThis, __FUNCTION__);
600	# endif
601	}
602	#endif /* IN_RING3 */
603
604	/**
605	* Looks up a register at the exact offset given by @a offReg.
606	*
607	* @returns Register index on success, -1 if not found.
608	* @param offReg The register offset.
609	*/
610	static int hdaRegLookup(uint32_t offReg)
611	{
612	/*
613	* Aliases.
614	*/
615	if (offReg >= g_aHdaRegAliases[0].offReg)
616	{
617	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
618	if (offReg == g_aHdaRegAliases[i].offReg)
619	return g_aHdaRegAliases[i].idxAlias;
620	Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
621	return -1;
622	}
623
624	/*
625	* Binary search the
626	*/
627	int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
628	int idxLow = 0;
629	for (;;)
630	{
631	int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
632	if (offReg < g_aHdaRegMap[idxMiddle].offset)
633	{
634	if (idxLow == idxMiddle)
635	break;
636	idxEnd = idxMiddle;
637	}
638	else if (offReg > g_aHdaRegMap[idxMiddle].offset)
639	{
640	idxLow = idxMiddle + 1;
641	if (idxLow >= idxEnd)
642	break;
643	}
644	else
645	return idxMiddle;
646	}
647
648	#ifdef RT_STRICT
649	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
650	Assert(g_aHdaRegMap[i].offset != offReg);
651	#endif
652	return -1;
653	}
654
655	#ifdef IN_RING3
656
657	/**
658	* Looks up a register covering the offset given by @a offReg.
659	*
660	* @returns Register index on success, -1 if not found.
661	* @param offReg The register offset.
662	*/
663	static int hdaR3RegLookupWithin(uint32_t offReg)
664	{
665	/*
666	* Aliases.
667	*/
668	if (offReg >= g_aHdaRegAliases[0].offReg)
669	{
670	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
671	{
672	uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
673	if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
674	return g_aHdaRegAliases[i].idxAlias;
675	}
676	Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
677	return -1;
678	}
679
680	/*
681	* Binary search the register map.
682	*/
683	int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
684	int idxLow = 0;
685	for (;;)
686	{
687	int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
688	if (offReg < g_aHdaRegMap[idxMiddle].offset)
689	{
690	if (idxLow == idxMiddle)
691	break;
692	idxEnd = idxMiddle;
693	}
694	else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
695	{
696	idxLow = idxMiddle + 1;
697	if (idxLow >= idxEnd)
698	break;
699	}
700	else
701	return idxMiddle;
702	}
703
704	# ifdef RT_STRICT
705	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
706	Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
707	# endif
708	return -1;
709	}
710
711
712	/**
713	* Synchronizes the CORB / RIRB buffers between internal <-> device state.
714	*
715	* @returns IPRT status code.
716	* @param pThis HDA state.
717	* @param fLocal Specify true to synchronize HDA state's CORB buffer with the device state,
718	* or false to synchronize the device state's RIRB buffer with the HDA state.
719	*
720	* @todo r=andy Break this up into two functions?
721	*/
722	static int hdaR3CmdSync(PHDASTATE pThis, bool fLocal)
723	{
724	int rc = VINF_SUCCESS;
725	if (fLocal)
726	{
727	if (pThis->u64CORBBase)
728	{
729	AssertPtr(pThis->pu32CorbBuf);
730	Assert(pThis->cbCorbBuf);
731
732	/** @todo r=bird: An explanation is required why PDMDevHlpPhysRead is used with
733	* the CORB and PDMDevHlpPCIPhysWrite with RIRB below. There are
734	* similar unexplained inconsistencies in DevHDACommon.cpp. */
735	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
736	Log(("hdaR3CmdSync/CORB: read %RGp LB %#x (%Rrc)\n", pThis->u64CORBBase, pThis->cbCorbBuf, rc));
737	AssertRCReturn(rc, rc);
738	}
739	}
740	else
741	{
742	if (pThis->u64RIRBBase)
743	{
744	AssertPtr(pThis->pu64RirbBuf);
745	Assert(pThis->cbRirbBuf);
746
747	rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
748	Log(("hdaR3CmdSync/RIRB: phys read %RGp LB %#x (%Rrc)\n", pThis->u64RIRBBase, pThis->pu64RirbBuf, rc));
749	AssertRCReturn(rc, rc);
750	}
751	}
752
753	# ifdef DEBUG_CMD_BUFFER
754	LogFunc(("fLocal=%RTbool\n", fLocal));
755
756	uint8_t i = 0;
757	do
758	{
759	LogFunc(("CORB%02x: ", i));
760	uint8_t j = 0;
761	do
762	{
763	const char *pszPrefix;
764	if ((i + j) == HDA_REG(pThis, CORBRP))
765	pszPrefix = "[R]";
766	else if ((i + j) == HDA_REG(pThis, CORBWP))
767	pszPrefix = "[W]";
768	else
769	pszPrefix = " "; /* three spaces */
770	Log((" %s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
771	j++;
772	} while (j < 8);
773	Log(("\n"));
774	i += 8;
775	} while(i != 0);
776
777	do
778	{
779	LogFunc(("RIRB%02x: ", i));
780	uint8_t j = 0;
781	do
782	{
783	const char *prefix;
784	if ((i + j) == HDA_REG(pThis, RIRBWP))
785	prefix = "[W]";
786	else
787	prefix = " ";
788	Log((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
789	} while (++j < 8);
790	Log(("\n"));
791	i += 8;
792	} while (i != 0);
793	# endif
794	return rc;
795	}
796
797	/**
798	* Processes the next CORB buffer command in the queue.
799	*
800	* This will invoke the HDA codec verb dispatcher.
801	*
802	* @returns IPRT status code.
803	* @param pThis HDA state.
804	*/
805	static int hdaR3CORBCmdProcess(PHDASTATE pThis)
806	{
807	uint8_t corbRp = HDA_REG(pThis, CORBRP);
808	uint8_t corbWp = HDA_REG(pThis, CORBWP);
809	uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
810
811	Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", corbRp, corbWp, rirbWp));
812
813	if (!(HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA))
814	{
815	LogFunc(("CORB DMA not active, skipping\n"));
816	return VINF_SUCCESS;
817	}
818
819	Assert(pThis->cbCorbBuf);
820
821	int rc = hdaR3CmdSync(pThis, true /* Sync from guest */);
822	AssertRCReturn(rc, rc);
823
824	uint16_t cIntCnt = HDA_REG(pThis, RINTCNT) & 0xff;
825
826	if (!cIntCnt) /* 0 means 256 interrupts. */
827	cIntCnt = HDA_MAX_RINTCNT;
828
829	Log3Func(("START CORB(RP:%x, WP:%x) RIRBWP:%x, RINTCNT:%RU8/%RU8\n",
830	corbRp, corbWp, rirbWp, pThis->u16RespIntCnt, cIntCnt));
831
832	while (corbRp != corbWp)
833	{
834	corbRp = (corbRp + 1) % (pThis->cbCorbBuf / HDA_CORB_ELEMENT_SIZE); /* Advance +1 as the first command(s) are at CORBWP + 1. */
835
836	uint32_t uCmd = pThis->pu32CorbBuf[corbRp];
837	uint64_t uResp = 0;
838
839	rc = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(uCmd, 0 /* Codec index */), &uResp);
840	if (RT_FAILURE(rc))
841	LogFunc(("Codec lookup failed with rc=%Rrc\n", rc));
842
843	Log3Func(("Codec verb %08x -> response %016lx\n", uCmd, uResp));
844
845	if ( (uResp & CODEC_RESPONSE_UNSOLICITED)
846	&& !(HDA_REG(pThis, GCTL) & HDA_GCTL_UNSOL))
847	{
848	LogFunc(("Unexpected unsolicited response.\n"));
849	HDA_REG(pThis, CORBRP) = corbRp;
850
851	/** @todo r=andy No CORB/RIRB syncing to guest required in that case? */
852	return rc;
853	}
854
855	rirbWp = (rirbWp + 1) % HDA_RIRB_SIZE;
856
857	pThis->pu64RirbBuf[rirbWp] = uResp;
858
859	pThis->u16RespIntCnt++;
860
861	bool fSendInterrupt = false;
862
863	if (pThis->u16RespIntCnt == cIntCnt) /* Response interrupt count reached? */
864	{
865	pThis->u16RespIntCnt = 0; /* Reset internal interrupt response counter. */
866
867	Log3Func(("Response interrupt count reached (%RU16)\n", pThis->u16RespIntCnt));
868	fSendInterrupt = true;
869
870	}
871	else if (corbRp == corbWp) /* Did we reach the end of the current command buffer? */
872	{
873	Log3Func(("Command buffer empty\n"));
874	fSendInterrupt = true;
875	}
876
877	if (fSendInterrupt)
878	{
879	if (HDA_REG(pThis, RIRBCTL) & HDA_RIRBCTL_RINTCTL) /* Response Interrupt Control (RINTCTL) enabled? */
880	{
881	HDA_REG(pThis, RIRBSTS) \|= HDA_RIRBSTS_RINTFL;
882
883	# ifndef LOG_ENABLED
884	rc = hdaProcessInterrupt(pThis);
885	# else
886	rc = hdaProcessInterrupt(pThis, __FUNCTION__);
887	# endif
888	}
889	}
890	}
891
892	Log3Func(("END CORB(RP:%x, WP:%x) RIRBWP:%x, RINTCNT:%RU8/%RU8\n",
893	corbRp, corbWp, rirbWp, pThis->u16RespIntCnt, cIntCnt));
894
895	HDA_REG(pThis, CORBRP) = corbRp;
896	HDA_REG(pThis, RIRBWP) = rirbWp;
897
898	rc = hdaR3CmdSync(pThis, false /* Sync to guest */);
899	AssertRCReturn(rc, rc);
900
901	if (RT_FAILURE(rc))
902	AssertRCReturn(rc, rc);
903
904	return rc;
905	}
906
907	#endif /* IN_RING3 */
908
909	/* Register access handlers. */
910
911	static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
912	{
913	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg);
914	*pu32Value = 0;
915	return VINF_SUCCESS;
916	}
917
918	static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
919	{
920	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
921	return VINF_SUCCESS;
922	}
923
924	/* U8 */
925	static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
926	{
927	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
928	return hdaRegReadU32(pThis, iReg, pu32Value);
929	}
930
931	static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
932	{
933	Assert((u32Value & 0xffffff00) == 0);
934	return hdaRegWriteU32(pThis, iReg, u32Value);
935	}
936
937	/* U16 */
938	static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
939	{
940	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
941	return hdaRegReadU32(pThis, iReg, pu32Value);
942	}
943
944	static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
945	{
946	Assert((u32Value & 0xffff0000) == 0);
947	return hdaRegWriteU32(pThis, iReg, u32Value);
948	}
949
950	/* U24 */
951	static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
952	{
953	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
954	return hdaRegReadU32(pThis, iReg, pu32Value);
955	}
956
957	#ifdef IN_RING3
958	static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
959	{
960	Assert((u32Value & 0xff000000) == 0);
961	return hdaRegWriteU32(pThis, iReg, u32Value);
962	}
963	#endif
964
965	/* U32 */
966	static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
967	{
968	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
969
970	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
971
972	*pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
973
974	DEVHDA_UNLOCK(pThis);
975	return VINF_SUCCESS;
976	}
977
978	static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
979	{
980	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
981
982	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
983
984	pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
985	\| (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
986	DEVHDA_UNLOCK(pThis);
987	return VINF_SUCCESS;
988	}
989
990	static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
991	{
992	RT_NOREF_PV(iReg);
993	#ifdef IN_RING3
994	DEVHDA_LOCK(pThis);
995	#else
996	if (!(u32Value & HDA_GCTL_CRST))
997	return VINF_IOM_R3_MMIO_WRITE;
998	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
999	#endif
1000
1001	if (u32Value & HDA_GCTL_CRST)
1002	{
1003	/* Set the CRST bit to indicate that we're leaving reset mode. */
1004	HDA_REG(pThis, GCTL) \|= HDA_GCTL_CRST;
1005	LogFunc(("Guest leaving HDA reset\n"));
1006	}
1007	else
1008	{
1009	#ifdef IN_RING3
1010	/* Enter reset state. */
1011	LogFunc(("Guest entering HDA reset with DMA(RIRB:%s, CORB:%s)\n",
1012	HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA ? "on" : "off",
1013	HDA_REG(pThis, RIRBCTL) & HDA_RIRBCTL_RDMAEN ? "on" : "off"));
1014
1015	/* Clear the CRST bit to indicate that we're in reset state. */
1016	HDA_REG(pThis, GCTL) &= ~HDA_GCTL_CRST;
1017
1018	hdaR3GCTLReset(pThis);
1019	#else
1020	AssertFailedReturnStmt(DEVHDA_UNLOCK(pThis), VINF_IOM_R3_MMIO_WRITE);
1021	#endif
1022	}
1023
1024	if (u32Value & HDA_GCTL_FCNTRL)
1025	{
1026	/* Flush: GSTS:1 set, see 6.2.6. */
1027	HDA_REG(pThis, GSTS) \|= HDA_GSTS_FSTS; /* Set the flush status. */
1028	/* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
1029	}
1030
1031	DEVHDA_UNLOCK(pThis);
1032	return VINF_SUCCESS;
1033	}
1034
1035	static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1036	{
1037	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1038
1039	uint32_t v = HDA_REG_IND(pThis, iReg);
1040	uint32_t nv = u32Value & HDA_STATESTS_SCSF_MASK;
1041
1042	HDA_REG(pThis, STATESTS) &= ~(v & nv); /* Write of 1 clears corresponding bit. */
1043
1044	DEVHDA_UNLOCK(pThis);
1045	return VINF_SUCCESS;
1046	}
1047
1048	static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1049	{
1050	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
1051
1052	const uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
1053	uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, uSD);
1054	#ifdef LOG_ENABLED
1055	const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, uSD);
1056	LogFlowFunc(("[SD%RU8] LPIB=%RU32, CBL=%RU32\n", uSD, u32LPIB, u32CBL));
1057	#endif
1058
1059	*pu32Value = u32LPIB;
1060
1061	DEVHDA_UNLOCK(pThis);
1062	return VINF_SUCCESS;
1063	}
1064
1065	#ifdef IN_RING3
1066	/**
1067	* Returns the current maximum value the wall clock counter can be set to.
1068	* This maximum value depends on all currently handled HDA streams and their own current timing.
1069	*
1070	* @return Current maximum value the wall clock counter can be set to.
1071	* @param pThis HDA state.
1072	*
1073	* @remark Does not actually set the wall clock counter.
1074	*/
1075	static uint64_t hdaR3WalClkGetMax(PHDASTATE pThis)
1076	{
1077	const uint64_t u64WalClkCur = ASMAtomicReadU64(&pThis->u64WalClk);
1078	const uint64_t u64FrontAbsWalClk = pThis->SinkFront.pStream
1079	? hdaR3StreamPeriodGetAbsElapsedWalClk(&pThis->SinkFront.pStream->State.Period) : 0;
1080	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1081	# error "Implement me!"
1082	# endif
1083	const uint64_t u64LineInAbsWalClk = pThis->SinkLineIn.pStream
1084	? hdaR3StreamPeriodGetAbsElapsedWalClk(&pThis->SinkLineIn.pStream->State.Period) : 0;
1085	# ifdef VBOX_WITH_HDA_MIC_IN
1086	const uint64_t u64MicInAbsWalClk = pThis->SinkMicIn.pStream
1087	? hdaR3StreamPeriodGetAbsElapsedWalClk(&pThis->SinkMicIn.pStream->State.Period) : 0;
1088	# endif
1089
1090	uint64_t u64WalClkNew = RT_MAX(u64WalClkCur, u64FrontAbsWalClk);
1091	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1092	# error "Implement me!"
1093	# endif
1094	u64WalClkNew = RT_MAX(u64WalClkNew, u64LineInAbsWalClk);
1095	# ifdef VBOX_WITH_HDA_MIC_IN
1096	u64WalClkNew = RT_MAX(u64WalClkNew, u64MicInAbsWalClk);
1097	# endif
1098
1099	Log3Func(("%RU64 -> Front=%RU64, LineIn=%RU64 -> %RU64\n",
1100	u64WalClkCur, u64FrontAbsWalClk, u64LineInAbsWalClk, u64WalClkNew));
1101
1102	return u64WalClkNew;
1103	}
1104	#endif /* IN_RING3 */
1105
1106	static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1107	{
1108	#ifdef IN_RING3
1109	RT_NOREF(iReg);
1110
1111	DEVHDA_LOCK(pThis);
1112
1113	*pu32Value = RT_LO_U32(ASMAtomicReadU64(&pThis->u64WalClk));
1114
1115	Log3Func(("%RU32 (max @ %RU64)\n",*pu32Value, hdaR3WalClkGetMax(pThis)));
1116
1117	DEVHDA_UNLOCK(pThis);
1118	return VINF_SUCCESS;
1119	#else
1120	RT_NOREF(pThis, iReg, pu32Value);
1121	return VINF_IOM_R3_MMIO_READ;
1122	#endif
1123	}
1124
1125	static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1126	{
1127	RT_NOREF(iReg);
1128	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1129
1130	if (u32Value & HDA_CORBRP_RST)
1131	{
1132	/* Do a CORB reset. */
1133	if (pThis->cbCorbBuf)
1134	{
1135	#ifdef IN_RING3
1136	Assert(pThis->pu32CorbBuf);
1137	RT_BZERO((void *)pThis->pu32CorbBuf, pThis->cbCorbBuf);
1138	#else
1139	DEVHDA_UNLOCK(pThis);
1140	return VINF_IOM_R3_MMIO_WRITE;
1141	#endif
1142	}
1143
1144	LogRel2(("HDA: CORB reset\n"));
1145
1146	HDA_REG(pThis, CORBRP) = HDA_CORBRP_RST; /* Clears the pointer. */
1147	}
1148	else
1149	HDA_REG(pThis, CORBRP) &= ~HDA_CORBRP_RST; /* Only CORBRP_RST bit is writable. */
1150
1151	DEVHDA_UNLOCK(pThis);
1152	return VINF_SUCCESS;
1153	}
1154
1155	static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1156	{
1157	#ifdef IN_RING3
1158	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1159
1160	int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1161	AssertRC(rc);
1162
1163	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Start DMA engine. */
1164	{
1165	rc = hdaR3CORBCmdProcess(pThis);
1166	}
1167	else
1168	LogFunc(("CORB DMA not running, skipping\n"));
1169
1170	DEVHDA_UNLOCK(pThis);
1171	return rc;
1172	#else
1173	RT_NOREF(pThis, iReg, u32Value);
1174	return VINF_IOM_R3_MMIO_WRITE;
1175	#endif
1176	}
1177
1178	static int hdaRegWriteCORBSIZE(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1179	{
1180	#ifdef IN_RING3
1181	RT_NOREF(iReg);
1182	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1183
1184	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
1185	{
1186	LogFunc(("CORB DMA is (still) running, skipping\n"));
1187
1188	DEVHDA_UNLOCK(pThis);
1189	return VINF_SUCCESS;
1190	}
1191
1192	u32Value = (u32Value & HDA_CORBSIZE_SZ);
1193
1194	uint16_t cEntries = HDA_CORB_SIZE; /* Set default. */
1195
1196	switch (u32Value)
1197	{
1198	case 0: /* 8 byte; 2 entries. */
1199	cEntries = 2;
1200	break;
1201
1202	case 1: /* 64 byte; 16 entries. */
1203	cEntries = 16;
1204	break;
1205
1206	case 2: /* 1 KB; 256 entries. */
1207	/* Use default size. */
1208	break;
1209
1210	default:
1211	LogRel(("HDA: Guest tried to set an invalid CORB size (0x%x), keeping default\n", u32Value));
1212	u32Value = 2;
1213	/* Use default size. */
1214	break;
1215	}
1216
1217	uint32_t cbCorbBuf = cEntries * HDA_CORB_ELEMENT_SIZE;
1218	Assert(cbCorbBuf <= HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE); /* Paranoia. */
1219
1220	if (cbCorbBuf != pThis->cbCorbBuf)
1221	{
1222	RT_BZERO(pThis->pu32CorbBuf, HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE); /* Clear CORB when setting a new size. */
1223	pThis->cbCorbBuf = cbCorbBuf;
1224	}
1225
1226	LogFunc(("CORB buffer size is now %RU32 bytes (%u entries)\n", pThis->cbCorbBuf, pThis->cbCorbBuf / HDA_CORB_ELEMENT_SIZE));
1227
1228	HDA_REG(pThis, CORBSIZE) = u32Value;
1229
1230	DEVHDA_UNLOCK(pThis);
1231	return VINF_SUCCESS;
1232	#else
1233	RT_NOREF(pThis, iReg, u32Value);
1234	return VINF_IOM_R3_MMIO_WRITE;
1235	#endif
1236	}
1237
1238	static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1239	{
1240	RT_NOREF_PV(iReg);
1241	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1242
1243	uint32_t v = HDA_REG(pThis, CORBSTS);
1244	HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1245
1246	DEVHDA_UNLOCK(pThis);
1247	return VINF_SUCCESS;
1248	}
1249
1250	static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1251	{
1252	#ifdef IN_RING3
1253	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1254
1255	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
1256	AssertRCSuccess(rc);
1257
1258	rc = hdaR3CORBCmdProcess(pThis);
1259
1260	DEVHDA_UNLOCK(pThis);
1261	return rc;
1262	#else
1263	RT_NOREF(pThis, iReg, u32Value);
1264	return VINF_IOM_R3_MMIO_WRITE;
1265	#endif
1266	}
1267
1268	static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1269	{
1270	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1271
1272	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, CBL, iReg));
1273	if (pStream)
1274	{
1275	pStream->u32CBL = u32Value;
1276	LogFlowFunc(("[SD%RU8] CBL=%RU32\n", pStream->u8SD, u32Value));
1277	}
1278	else
1279	LogFunc(("[SD%RU8] Warning: Changing SDCBL on non-attached stream (0x%x)\n",
1280	HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
1281
1282	int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1283	AssertRCSuccess(rc);
1284
1285	DEVHDA_UNLOCK(pThis);
1286	return rc;
1287	}
1288
1289	static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1290	{
1291	#ifdef IN_RING3
1292	/* Get the stream descriptor. */
1293	const uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
1294
1295	DEVHDA_LOCK_BOTH_RETURN(pThis, uSD, VINF_IOM_R3_MMIO_WRITE);
1296
1297	/*
1298	* Some guests write too much (that is, 32-bit with the top 8 bit being junk)
1299	* instead of 24-bit required for SDCTL. So just mask this here to be safe.
1300	*/
1301	u32Value &= 0x00ffffff;
1302
1303	bool fRun = RT_BOOL(u32Value & HDA_SDCTL_RUN);
1304	bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_SDCTL_RUN);
1305
1306	bool fReset = RT_BOOL(u32Value & HDA_SDCTL_SRST);
1307	bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_SDCTL_SRST);
1308
1309	LogFunc(("[SD%RU8] fRun=%RTbool, fInRun=%RTbool, fReset=%RTbool, fInReset=%RTbool, %R[sdctl]\n",
1310	uSD, fRun, fInRun, fReset, fInReset, u32Value));
1311
1312	/*
1313	* Extract the stream tag the guest wants to use for this specific
1314	* stream descriptor (SDn). This only can happen if the stream is in a non-running
1315	* state, so we're doing the lookup and assignment here.
1316	*
1317	* So depending on the guest OS, SD3 can use stream tag 4, for example.
1318	*/
1319	uint8_t uTag = (u32Value >> HDA_SDCTL_NUM_SHIFT) & HDA_SDCTL_NUM_MASK;
1320	if (uTag > HDA_MAX_TAGS)
1321	{
1322	LogFunc(("[SD%RU8] Warning: Invalid stream tag %RU8 specified!\n", uSD, uTag));
1323
1324	int rc = hdaRegWriteU24(pThis, iReg, u32Value);
1325	DEVHDA_UNLOCK_BOTH(pThis, uSD);
1326	return rc;
1327	}
1328
1329	PHDATAG pTag = &pThis->aTags[uTag];
1330	AssertPtr(pTag);
1331
1332	LogFunc(("[SD%RU8] Using stream tag=%RU8\n", uSD, uTag));
1333
1334	/* Assign new values. */
1335	pTag->uTag = uTag;
1336	pTag->pStream = hdaGetStreamFromSD(pThis, uSD);
1337
1338	PHDASTREAM pStream = pTag->pStream;
1339	AssertPtr(pStream);
1340
1341	if (fInReset)
1342	{
1343	Assert(!fReset);
1344	Assert(!fInRun && !fRun);
1345
1346	/* Exit reset state. */
1347	ASMAtomicXchgBool(&pStream->State.fInReset, false);
1348
1349	/* Report that we're done resetting this stream by clearing SRST. */
1350	HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_SRST;
1351
1352	LogFunc(("[SD%RU8] Reset exit\n", uSD));
1353	}
1354	else if (fReset)
1355	{
1356	/* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
1357	Assert(!fInRun && !fRun);
1358
1359	LogFunc(("[SD%RU8] Reset enter\n", uSD));
1360
1361	hdaR3StreamLock(pStream);
1362
1363	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1364	hdaR3StreamAsyncIOLock(pStream);
1365	# endif
1366	/* Make sure to remove the run bit before doing the actual stream reset. */
1367	HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_RUN;
1368
1369	hdaR3StreamReset(pThis, pStream, pStream->u8SD);
1370
1371	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1372	hdaR3StreamAsyncIOUnlock(pStream);
1373	# endif
1374	hdaR3StreamUnlock(pStream);
1375	}
1376	else
1377	{
1378	/*
1379	* We enter here to change DMA states only.
1380	*/
1381	if (fInRun != fRun)
1382	{
1383	Assert(!fReset && !fInReset);
1384	LogFunc(("[SD%RU8] State changed (fRun=%RTbool)\n", uSD, fRun));
1385
1386	hdaR3StreamLock(pStream);
1387
1388	int rc2;
1389
1390	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1391	if (fRun)
1392	rc2 = hdaR3StreamAsyncIOCreate(pStream);
1393
1394	hdaR3StreamAsyncIOLock(pStream);
1395	# endif
1396	if (fRun)
1397	{
1398	/* (Re-)initialize the stream with current values. */
1399	rc2 = hdaR3StreamInit(pStream, pStream->u8SD);
1400	AssertRC(rc2);
1401
1402	/* Remove the old stream from the device setup. */
1403	hdaR3RemoveStream(pThis, &pStream->State.Cfg);
1404
1405	/* Add the stream to the device setup. */
1406	rc2 = hdaR3AddStream(pThis, &pStream->State.Cfg);
1407	AssertRC(rc2);
1408	}
1409
1410	/* Enable/disable the stream. */
1411	rc2 = hdaR3StreamEnable(pStream, fRun /* fEnable */);
1412	AssertRC(rc2);
1413
1414	if (fRun)
1415	{
1416	/* Keep track of running streams. */
1417	pThis->cStreamsActive++;
1418
1419	/* (Re-)init the stream's period. */
1420	hdaR3StreamPeriodInit(&pStream->State.Period,
1421	pStream->u8SD, pStream->u16LVI, pStream->u32CBL, &pStream->State.Cfg);
1422
1423	/* Begin a new period for this stream. */
1424	rc2 = hdaR3StreamPeriodBegin(&pStream->State.Period, hdaWalClkGetCurrent(pThis)/* Use current wall clock time */);
1425	AssertRC(rc2);
1426
1427	rc2 = hdaR3TimerSet(pThis, pStream, TMTimerGet(pThis->pTimer[pStream->u8SD]) + pStream->State.cTransferTicks, false /* fForce */);
1428	AssertRC(rc2);
1429	}
1430	else
1431	{
1432	/* Keep track of running streams. */
1433	Assert(pThis->cStreamsActive);
1434	if (pThis->cStreamsActive)
1435	pThis->cStreamsActive--;
1436
1437	/* Make sure to (re-)schedule outstanding (delayed) interrupts. */
1438	hdaR3ReschedulePendingInterrupts(pThis);
1439
1440	/* Reset the period. */
1441	hdaR3StreamPeriodReset(&pStream->State.Period);
1442	}
1443
1444	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1445	hdaR3StreamAsyncIOUnlock(pStream);
1446	# endif
1447	/* Make sure to leave the lock before (eventually) starting the timer. */
1448	hdaR3StreamUnlock(pStream);
1449	}
1450	}
1451
1452	int rc2 = hdaRegWriteU24(pThis, iReg, u32Value);
1453	AssertRC(rc2);
1454
1455	DEVHDA_UNLOCK_BOTH(pThis, uSD);
1456	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1457	#else /* !IN_RING3 */
1458	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
1459	return VINF_IOM_R3_MMIO_WRITE;
1460	#endif /* IN_RING3 */
1461	}
1462
1463	static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1464	{
1465	#ifdef IN_RING3
1466	const uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, STS, iReg);
1467
1468	DEVHDA_LOCK_BOTH_RETURN(pThis, uSD, VINF_IOM_R3_MMIO_WRITE);
1469
1470	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
1471	if (!pStream)
1472	{
1473	AssertMsgFailed(("[SD%RU8] Warning: Writing SDSTS on non-attached stream (0x%x)\n",
1474	HDA_SD_NUM_FROM_REG(pThis, STS, iReg), u32Value));
1475
1476	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
1477	DEVHDA_UNLOCK_BOTH(pThis, uSD);
1478	return rc;
1479	}
1480
1481	hdaR3StreamLock(pStream);
1482
1483	uint32_t v = HDA_REG_IND(pThis, iReg);
1484
1485	/* Clear (zero) FIFOE, DESE and BCIS bits when writing 1 to it (6.2.33). */
1486	HDA_REG_IND(pThis, iReg) &= ~(u32Value & v);
1487
1488	/* Some guests tend to write SDnSTS even if the stream is not running.
1489	* So make sure to check if the RUN bit is set first. */
1490	const bool fRunning = pStream->State.fRunning;
1491
1492	Log3Func(("[SD%RU8] fRunning=%RTbool %R[sdsts]\n", pStream->u8SD, fRunning, v));
1493
1494	PHDASTREAMPERIOD pPeriod = &pStream->State.Period;
1495
1496	if (hdaR3StreamPeriodLock(pPeriod))
1497	{
1498	const bool fNeedsInterrupt = hdaR3StreamPeriodNeedsInterrupt(pPeriod);
1499	if (fNeedsInterrupt)
1500	hdaR3StreamPeriodReleaseInterrupt(pPeriod);
1501
1502	if (hdaR3StreamPeriodIsComplete(pPeriod))
1503	{
1504	/* Make sure to try to update the WALCLK register if a period is complete.
1505	* Use the maximum WALCLK value all (active) streams agree to. */
1506	const uint64_t uWalClkMax = hdaR3WalClkGetMax(pThis);
1507	if (uWalClkMax > hdaWalClkGetCurrent(pThis))
1508	hdaR3WalClkSet(pThis, uWalClkMax, false /* fForce */);
1509
1510	hdaR3StreamPeriodEnd(pPeriod);
1511
1512	if (fRunning)
1513	hdaR3StreamPeriodBegin(pPeriod, hdaWalClkGetCurrent(pThis) /* Use current wall clock time */);
1514	}
1515
1516	hdaR3StreamPeriodUnlock(pPeriod); /* Unlock before processing interrupt. */
1517	}
1518
1519	# ifndef LOG_ENABLED
1520	hdaProcessInterrupt(pThis);
1521	# else
1522	hdaProcessInterrupt(pThis, __FUNCTION__);
1523	# endif
1524
1525	const uint64_t tsNow = TMTimerGet(pThis->pTimer[uSD]);
1526	Assert(tsNow >= pStream->State.tsTransferLast);
1527
1528	const uint64_t cTicksElapsed = tsNow - pStream->State.tsTransferLast;
1529	# ifdef LOG_ENABLED
1530	const uint64_t cTicksTransferred = pStream->State.cbTransferProcessed * pStream->State.cTicksPerByte;
1531	# endif
1532
1533	uint64_t cTicksToNext = pStream->State.cTransferTicks;
1534	if (cTicksToNext) /* Only do any calculations if the stream currently is set up for transfers. */
1535	{
1536	Log3Func(("[SD%RU8] cTicksElapsed=%RU64, cTicksTransferred=%RU64, cTicksToNext=%RU64\n",
1537	pStream->u8SD, cTicksElapsed, cTicksTransferred, cTicksToNext));
1538
1539	Log3Func(("[SD%RU8] cbTransferProcessed=%RU32, cbTransferChunk=%RU32, cbTransferSize=%RU32\n",
1540	pStream->u8SD, pStream->State.cbTransferProcessed, pStream->State.cbTransferChunk, pStream->State.cbTransferSize));
1541
1542	if (cTicksElapsed <= cTicksToNext)
1543	{
1544	cTicksToNext = cTicksToNext - cTicksElapsed;
1545	}
1546	else /* Catch up. */
1547	{
1548	Log3Func(("[SD%RU8] Warning: Lagging behind (%RU64 ticks elapsed, maximum allowed is %RU64)\n",
1549	pStream->u8SD, cTicksElapsed, cTicksToNext));
1550
1551	LogRelMax2(64, ("HDA: Stream #%RU8 interrupt lagging behind (expected %uus, got %uus), trying to catch up ...\n",
1552	pStream->u8SD,
1553	(TMTimerGetFreq(pThis->pTimer[pStream->u8SD]) / pThis->u16TimerHz) / 1000,(tsNow - pStream->State.tsTransferLast) / 1000));
1554
1555	cTicksToNext = 0;
1556	}
1557
1558	Log3Func(("[SD%RU8] -> cTicksToNext=%RU64\n", pStream->u8SD, cTicksToNext));
1559
1560	/* Reset processed data counter. */
1561	pStream->State.cbTransferProcessed = 0;
1562	pStream->State.tsTransferNext = tsNow + cTicksToNext;
1563
1564	/* Only re-arm the timer if there were pending transfer interrupts left
1565	* -- it could happen that we land in here if a guest writes to SDnSTS
1566	* unconditionally. */
1567	if (pStream->State.cTransferPendingInterrupts)
1568	{
1569	pStream->State.cTransferPendingInterrupts--;
1570
1571	/* Re-arm the timer. */
1572	LogFunc(("Timer set SD%RU8\n", pStream->u8SD));
1573	hdaR3TimerSet(pThis, pStream, tsNow + cTicksToNext, false /* fForce */);
1574	}
1575	}
1576
1577	hdaR3StreamUnlock(pStream);
1578
1579	DEVHDA_UNLOCK_BOTH(pThis, uSD);
1580	return VINF_SUCCESS;
1581	#else /* IN_RING3 */
1582	RT_NOREF(pThis, iReg, u32Value);
1583	return VINF_IOM_R3_MMIO_WRITE;
1584	#endif /* !IN_RING3 */
1585	}
1586
1587	static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1588	{
1589	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1590
1591	if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
1592	{ /* nothing to do */ }
1593	else
1594	{
1595	uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, LVI, iReg);
1596	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
1597	if (pStream)
1598	{
1599	/** @todo Validate LVI. */
1600	pStream->u16LVI = u32Value;
1601	LogFunc(("[SD%RU8] Updating LVI to %RU16\n", uSD, pStream->u16LVI));
1602
1603	#ifdef HDA_USE_DMA_ACCESS_HANDLER
1604	if (hdaGetDirFromSD(uSD) == PDMAUDIODIR_OUT)
1605	{
1606	/* Try registering the DMA handlers.
1607	* As we can't be sure in which order LVI + BDL base are set, try registering in both routines. */
1608	if (hdaR3StreamRegisterDMAHandlers(pThis, pStream))
1609	LogFunc(("[SD%RU8] DMA logging enabled\n", pStream->u8SD));
1610	}
1611	#endif
1612	}
1613	else
1614	AssertMsgFailed(("[SD%RU8] Warning: Changing SDLVI on non-attached stream (0x%x)\n", uSD, u32Value));
1615
1616	int rc2 = hdaRegWriteU16(pThis, iReg, u32Value);
1617	AssertRC(rc2);
1618	}
1619
1620	DEVHDA_UNLOCK(pThis);
1621	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1622	}
1623
1624	static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1625	{
1626	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1627
1628	uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg);
1629
1630	if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_IN) /* FIFOW for input streams only. */
1631	{
1632	#ifndef IN_RING0
1633	LogRel(("HDA: Warning: Guest tried to write read-only FIFOW to output stream #%RU8, ignoring\n", uSD));
1634	DEVHDA_UNLOCK(pThis);
1635	return VINF_SUCCESS;
1636	#else
1637	DEVHDA_UNLOCK(pThis);
1638	return VINF_IOM_R3_MMIO_WRITE;
1639	#endif
1640	}
1641
1642	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg));
1643	if (!pStream)
1644	{
1645	AssertMsgFailed(("[SD%RU8] Warning: Changing FIFOW on non-attached stream (0x%x)\n", uSD, u32Value));
1646
1647	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
1648	DEVHDA_UNLOCK(pThis);
1649	return rc;
1650	}
1651
1652	uint32_t u32FIFOW = 0;
1653
1654	switch (u32Value)
1655	{
1656	case HDA_SDFIFOW_8B:
1657	case HDA_SDFIFOW_16B:
1658	case HDA_SDFIFOW_32B:
1659	u32FIFOW = u32Value;
1660	break;
1661	default:
1662	ASSERT_GUEST_LOGREL_MSG_FAILED(("Guest tried write unsupported FIFOW (0x%x) to stream #%RU8, defaulting to 32 bytes\n",
1663	u32Value, uSD));
1664	u32FIFOW = HDA_SDFIFOW_32B;
1665	break;
1666	}
1667
1668	if (u32FIFOW)
1669	{
1670	pStream->u16FIFOW = hdaSDFIFOWToBytes(u32FIFOW);
1671	LogFunc(("[SD%RU8] Updating FIFOW to %RU32 bytes\n", uSD, pStream->u16FIFOW));
1672
1673	int rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOW);
1674	AssertRC(rc2);
1675	}
1676
1677	DEVHDA_UNLOCK(pThis);
1678	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1679	}
1680
1681	/**
1682	* @note This method could be called for changing value on Output Streams only (ICH6 datasheet 18.2.39).
1683	*/
1684	static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1685	{
1686	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1687
1688	uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOS, iReg);
1689
1690	if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_OUT) /* FIFOS for output streams only. */
1691	{
1692	LogRel(("HDA: Warning: Guest tried to write read-only FIFOS to input stream #%RU8, ignoring\n", uSD));
1693
1694	DEVHDA_UNLOCK(pThis);
1695	return VINF_SUCCESS;
1696	}
1697
1698	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
1699	if (!pStream)
1700	{
1701	AssertMsgFailed(("[SD%RU8] Warning: Changing FIFOS on non-attached stream (0x%x)\n", uSD, u32Value));
1702
1703	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
1704	DEVHDA_UNLOCK(pThis);
1705	return rc;
1706	}
1707
1708	uint32_t u32FIFOS = 0;
1709
1710	switch(u32Value)
1711	{
1712	case HDA_SDOFIFO_16B:
1713	case HDA_SDOFIFO_32B:
1714	case HDA_SDOFIFO_64B:
1715	case HDA_SDOFIFO_128B:
1716	case HDA_SDOFIFO_192B:
1717	case HDA_SDOFIFO_256B:
1718	u32FIFOS = u32Value;
1719	break;
1720
1721	default:
1722	ASSERT_GUEST_LOGREL_MSG_FAILED(("Guest tried write unsupported FIFOS (0x%x) to stream #%RU8, defaulting to 192 bytes\n",
1723	u32Value, uSD));
1724	u32FIFOS = HDA_SDOFIFO_192B;
1725	break;
1726	}
1727
1728	if (u32FIFOS)
1729	{
1730	pStream->u16FIFOS = u32FIFOS + 1;
1731	LogFunc(("[SD%RU8] Updating FIFOS to %RU32 bytes\n", uSD, pStream->u16FIFOS));
1732
1733	int rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOS);
1734	AssertRC(rc2);
1735	}
1736
1737	DEVHDA_UNLOCK(pThis);
1738	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1739	}
1740
1741	#ifdef IN_RING3
1742
1743	/**
1744	* Adds an audio output stream to the device setup using the given configuration.
1745	*
1746	* @returns IPRT status code.
1747	* @param pThis Device state.
1748	* @param pCfg Stream configuration to use for adding a stream.
1749	*/
1750	static int hdaR3AddStreamOut(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1751	{
1752	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1753	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1754
1755	AssertReturn(pCfg->enmDir == PDMAUDIODIR_OUT, VERR_INVALID_PARAMETER);
1756
1757	LogFlowFunc(("Stream=%s\n", pCfg->szName));
1758
1759	int rc = VINF_SUCCESS;
1760
1761	bool fUseFront = true; /* Always use front out by default. */
1762	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1763	bool fUseRear;
1764	bool fUseCenter;
1765	bool fUseLFE;
1766
1767	fUseRear = fUseCenter = fUseLFE = false;
1768
1769	/*
1770	* Use commonly used setups for speaker configurations.
1771	*/
1772
1773	/** @todo Make the following configurable through mixer API and/or CFGM? */
1774	switch (pCfg->Props.cChannels)
1775	{
1776	case 3: /* 2.1: Front (Stereo) + LFE. */
1777	{
1778	fUseLFE = true;
1779	break;
1780	}
1781
1782	case 4: /* Quadrophonic: Front (Stereo) + Rear (Stereo). */
1783	{
1784	fUseRear = true;
1785	break;
1786	}
1787
1788	case 5: /* 4.1: Front (Stereo) + Rear (Stereo) + LFE. */
1789	{
1790	fUseRear = true;
1791	fUseLFE = true;
1792	break;
1793	}
1794
1795	case 6: /* 5.1: Front (Stereo) + Rear (Stereo) + Center/LFE. */
1796	{
1797	fUseRear = true;
1798	fUseCenter = true;
1799	fUseLFE = true;
1800	break;
1801	}
1802
1803	default: /* Unknown; fall back to 2 front channels (stereo). */
1804	{
1805	rc = VERR_NOT_SUPPORTED;
1806	break;
1807	}
1808	}
1809	# else /* !VBOX_WITH_AUDIO_HDA_51_SURROUND */
1810	/* Only support mono or stereo channels. */
1811	if ( pCfg->Props.cChannels != 1 /* Mono */
1812	&& pCfg->Props.cChannels != 2 /* Stereo */)
1813	{
1814	rc = VERR_NOT_SUPPORTED;
1815	}
1816	# endif /* !VBOX_WITH_AUDIO_HDA_51_SURROUND */
1817
1818	if (rc == VERR_NOT_SUPPORTED)
1819	{
1820	LogRel2(("HDA: Warning: Unsupported channel count (%RU8), falling back to stereo channels (2)\n", pCfg->Props.cChannels));
1821
1822	/* Fall back to 2 channels (see below in fUseFront block). */
1823	rc = VINF_SUCCESS;
1824	}
1825
1826	do
1827	{
1828	if (RT_FAILURE(rc))
1829	break;
1830
1831	if (fUseFront)
1832	{
1833	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Front");
1834
1835	pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_FRONT;
1836	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1837
1838	pCfg->Props.cChannels = 2;
1839	pCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pCfg->Props.cBytes, pCfg->Props.cChannels);
1840
1841	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT, pCfg);
1842	}
1843
1844	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1845	if ( RT_SUCCESS(rc)
1846	&& (fUseCenter \|\| fUseLFE))
1847	{
1848	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Center/LFE");
1849
1850	pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_CENTER_LFE;
1851	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1852
1853	pCfg->Props.cChannels = (fUseCenter && fUseLFE) ? 2 : 1;
1854	pCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pCfg->Props.cBits, pCfg->Props.cChannels);
1855
1856	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE, pCfg);
1857	}
1858
1859	if ( RT_SUCCESS(rc)
1860	&& fUseRear)
1861	{
1862	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Rear");
1863
1864	pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_REAR;
1865	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1866
1867	pCfg->Props.cChannels = 2;
1868	pCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pCfg->Props.cBits, pCfg->Props.cChannels);
1869
1870	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR, pCfg);
1871	}
1872	# endif /* VBOX_WITH_AUDIO_HDA_51_SURROUND */
1873
1874	} while (0);
1875
1876	LogFlowFuncLeaveRC(rc);
1877	return rc;
1878	}
1879
1880	/**
1881	* Adds an audio input stream to the device setup using the given configuration.
1882	*
1883	* @returns IPRT status code.
1884	* @param pThis Device state.
1885	* @param pCfg Stream configuration to use for adding a stream.
1886	*/
1887	static int hdaR3AddStreamIn(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1888	{
1889	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1890	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1891
1892	AssertReturn(pCfg->enmDir == PDMAUDIODIR_IN, VERR_INVALID_PARAMETER);
1893
1894	LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Source));
1895
1896	int rc;
1897
1898	switch (pCfg->DestSource.Source)
1899	{
1900	case PDMAUDIORECSOURCE_LINE:
1901	{
1902	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN, pCfg);
1903	break;
1904	}
1905	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
1906	case PDMAUDIORECSOURCE_MIC:
1907	{
1908	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN, pCfg);
1909	break;
1910	}
1911	# endif
1912	default:
1913	rc = VERR_NOT_SUPPORTED;
1914	break;
1915	}
1916
1917	LogFlowFuncLeaveRC(rc);
1918	return rc;
1919	}
1920
1921	/**
1922	* Adds an audio stream to the device setup using the given configuration.
1923	*
1924	* @returns IPRT status code.
1925	* @param pThis Device state.
1926	* @param pCfg Stream configuration to use for adding a stream.
1927	*/
1928	static int hdaR3AddStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1929	{
1930	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1931	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1932
1933	int rc;
1934
1935	LogFlowFuncEnter();
1936
1937	switch (pCfg->enmDir)
1938	{
1939	case PDMAUDIODIR_OUT:
1940	rc = hdaR3AddStreamOut(pThis, pCfg);
1941	break;
1942
1943	case PDMAUDIODIR_IN:
1944	rc = hdaR3AddStreamIn(pThis, pCfg);
1945	break;
1946
1947	default:
1948	rc = VERR_NOT_SUPPORTED;
1949	AssertFailed();
1950	break;
1951	}
1952
1953	LogFlowFunc(("Returning %Rrc\n", rc));
1954
1955	return rc;
1956	}
1957
1958	/**
1959	* Removes an audio stream from the device setup using the given configuration.
1960	*
1961	* @returns IPRT status code.
1962	* @param pThis Device state.
1963	* @param pCfg Stream configuration to use for removing a stream.
1964	*/
1965	static int hdaR3RemoveStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1966	{
1967	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1968	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1969
1970	int rc = VINF_SUCCESS;
1971
1972	PDMAUDIOMIXERCTL enmMixerCtl = PDMAUDIOMIXERCTL_UNKNOWN;
1973	switch (pCfg->enmDir)
1974	{
1975	case PDMAUDIODIR_IN:
1976	{
1977	LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Source));
1978
1979	switch (pCfg->DestSource.Source)
1980	{
1981	case PDMAUDIORECSOURCE_LINE: enmMixerCtl = PDMAUDIOMIXERCTL_LINE_IN; break;
1982	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
1983	case PDMAUDIORECSOURCE_MIC: enmMixerCtl = PDMAUDIOMIXERCTL_MIC_IN; break;
1984	# endif
1985	default:
1986	rc = VERR_NOT_SUPPORTED;
1987	break;
1988	}
1989
1990	break;
1991	}
1992
1993	case PDMAUDIODIR_OUT:
1994	{
1995	LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Dest));
1996
1997	switch (pCfg->DestSource.Dest)
1998	{
1999	case PDMAUDIOPLAYBACKDEST_FRONT: enmMixerCtl = PDMAUDIOMIXERCTL_FRONT; break;
2000	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2001	case PDMAUDIOPLAYBACKDEST_CENTER_LFE: enmMixerCtl = PDMAUDIOMIXERCTL_CENTER_LFE; break;
2002	case PDMAUDIOPLAYBACKDEST_REAR: enmMixerCtl = PDMAUDIOMIXERCTL_REAR; break;
2003	# endif
2004	default:
2005	rc = VERR_NOT_SUPPORTED;
2006	break;
2007	}
2008	break;
2009	}
2010
2011	default:
2012	rc = VERR_NOT_SUPPORTED;
2013	break;
2014	}
2015
2016	if (RT_SUCCESS(rc))
2017	rc = hdaCodecRemoveStream(pThis->pCodec, enmMixerCtl);
2018
2019	LogFlowFuncLeaveRC(rc);
2020	return rc;
2021	}
2022
2023	/**
2024	* Updates an audio device stream with the given configuration.
2025	*
2026	* @returns IPRT status code.
2027	* @param pThis HDA state.
2028	* @param pCfg Stream configuration to apply.
2029	*/
2030	static int hdaR3UpdateStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
2031	{
2032	/* Remove the old stream from the device setup. */
2033	hdaR3RemoveStream(pThis, pCfg);
2034
2035	/* Add the stream to the device setup. */
2036	return hdaR3AddStream(pThis, pCfg);
2037	}
2038	#endif /* IN_RING3 */
2039
2040	static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2041	{
2042	DEVHDA_LOCK(pThis);
2043
2044	# ifdef LOG_ENABLED
2045	if (!hdaGetStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FMT, iReg)))
2046	LogFunc(("[SD%RU8] Warning: Changing SDFMT on non-attached stream (0x%x)\n",
2047	HDA_SD_NUM_FROM_REG(pThis, FMT, iReg), u32Value));
2048	# endif
2049
2050
2051	/* Write the wanted stream format into the register in any case.
2052	*
2053	* This is important for e.g. MacOS guests, as those try to initialize streams which are not reported
2054	* by the device emulation (wants 4 channels, only have 2 channels at the moment).
2055	*
2056	* When ignoring those (invalid) formats, this leads to MacOS thinking that the device is malfunctioning
2057	* and therefore disabling the device completely. */
2058	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
2059	AssertRC(rc);
2060
2061	DEVHDA_UNLOCK(pThis);
2062	return VINF_SUCCESS; /* Never return failure. */
2063	}
2064
2065	/* Note: Will be called for both, BDPL and BDPU, registers. */
2066	DECLINLINE(int) hdaRegWriteSDBDPX(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value, uint8_t uSD)
2067	{
2068	#ifdef IN_RING3
2069	DEVHDA_LOCK(pThis);
2070
2071	int rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2072	AssertRC(rc2);
2073
2074	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
2075	if (!pStream)
2076	{
2077	DEVHDA_UNLOCK(pThis);
2078	return VINF_SUCCESS;
2079	}
2080
2081	/* Update BDL base. */
2082	pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, uSD),
2083	HDA_STREAM_REG(pThis, BDPU, uSD));
2084
2085	# ifdef HDA_USE_DMA_ACCESS_HANDLER
2086	if (hdaGetDirFromSD(uSD) == PDMAUDIODIR_OUT)
2087	{
2088	/* Try registering the DMA handlers.
2089	* As we can't be sure in which order LVI + BDL base are set, try registering in both routines. */
2090	if (hdaR3StreamRegisterDMAHandlers(pThis, pStream))
2091	LogFunc(("[SD%RU8] DMA logging enabled\n", pStream->u8SD));
2092	}
2093	# endif
2094
2095	LogFlowFunc(("[SD%RU8] BDLBase=0x%x\n", pStream->u8SD, pStream->u64BDLBase));
2096
2097	DEVHDA_UNLOCK(pThis);
2098	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2099	#else /* !IN_RING3 */
2100	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value); RT_NOREF_PV(uSD);
2101	return VINF_IOM_R3_MMIO_WRITE;
2102	#endif /* IN_RING3 */
2103	}
2104
2105	static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2106	{
2107	return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPL, iReg));
2108	}
2109
2110	static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2111	{
2112	return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPU, iReg));
2113	}
2114
2115	static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2116	{
2117	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
2118
2119	/* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
2120	if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2121	\|\| (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA))
2122	{
2123	HDA_REG(pThis, IRS) = HDA_IRS_ICB; /* busy */
2124	}
2125
2126	int rc = hdaRegReadU32(pThis, iReg, pu32Value);
2127	DEVHDA_UNLOCK(pThis);
2128
2129	return rc;
2130	}
2131
2132	static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2133	{
2134	RT_NOREF_PV(iReg);
2135	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2136
2137	/*
2138	* If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
2139	* write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
2140	*/
2141	if ( (u32Value & HDA_IRS_ICB)
2142	&& !(HDA_REG(pThis, IRS) & HDA_IRS_ICB))
2143	{
2144	#ifdef IN_RING3
2145	uint32_t uCmd = HDA_REG(pThis, IC);
2146
2147	if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
2148	{
2149	DEVHDA_UNLOCK(pThis);
2150
2151	/*
2152	* 3.4.3: Defines behavior of immediate Command status register.
2153	*/
2154	LogRel(("HDA: Guest attempted process immediate verb (%x) with active CORB\n", uCmd));
2155	return VINF_SUCCESS;
2156	}
2157
2158	HDA_REG(pThis, IRS) = HDA_IRS_ICB; /* busy */
2159
2160	uint64_t uResp;
2161	int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec,
2162	HDA_CODEC_CMD(uCmd, 0 /* LUN */), &uResp);
2163	if (RT_FAILURE(rc2))
2164	LogFunc(("Codec lookup failed with rc2=%Rrc\n", rc2));
2165
2166	HDA_REG(pThis, IR) = (uint32_t)uResp; /** @todo r=andy Do we need a 64-bit response? */
2167	HDA_REG(pThis, IRS) = HDA_IRS_IRV; /* result is ready */
2168	/** @todo r=michaln We just set the IRS value, why are we clearing unset bits? */
2169	HDA_REG(pThis, IRS) &= ~HDA_IRS_ICB; /* busy is clear */
2170
2171	DEVHDA_UNLOCK(pThis);
2172	return VINF_SUCCESS;
2173	#else /* !IN_RING3 */
2174	DEVHDA_UNLOCK(pThis);
2175	return VINF_IOM_R3_MMIO_WRITE;
2176	#endif /* !IN_RING3 */
2177	}
2178
2179	/*
2180	* Once the guest read the response, it should clear the IRV bit of the IRS register.
2181	*/
2182	HDA_REG(pThis, IRS) &= ~(u32Value & HDA_IRS_IRV);
2183
2184	DEVHDA_UNLOCK(pThis);
2185	return VINF_SUCCESS;
2186	}
2187
2188	static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2189	{
2190	RT_NOREF(iReg);
2191	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2192
2193	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
2194	{
2195	LogFunc(("CORB DMA (still) running, skipping\n"));
2196
2197	DEVHDA_UNLOCK(pThis);
2198	return VINF_SUCCESS;
2199	}
2200
2201	if (u32Value & HDA_RIRBWP_RST)
2202	{
2203	/* Do a RIRB reset. */
2204	if (pThis->cbRirbBuf)
2205	{
2206	Assert(pThis->pu64RirbBuf);
2207	RT_BZERO((void *)pThis->pu64RirbBuf, pThis->cbRirbBuf);
2208	}
2209
2210	LogRel2(("HDA: RIRB reset\n"));
2211
2212	HDA_REG(pThis, RIRBWP) = 0;
2213	}
2214
2215	/* The remaining bits are O, see 6.2.22. */
2216
2217	DEVHDA_UNLOCK(pThis);
2218	return VINF_SUCCESS;
2219	}
2220
2221	static int hdaRegWriteRINTCNT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2222	{
2223	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2224
2225	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
2226	{
2227	LogFunc(("CORB DMA is (still) running, skipping\n"));
2228
2229	DEVHDA_UNLOCK(pThis);
2230	return VINF_SUCCESS;
2231	}
2232
2233	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
2234	AssertRC(rc);
2235
2236	LogFunc(("Response interrupt count is now %RU8\n", HDA_REG(pThis, RINTCNT) & 0xFF));
2237
2238	DEVHDA_UNLOCK(pThis);
2239	return rc;
2240	}
2241
2242	static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2243	{
2244	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2245	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2246
2247	int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2248	AssertRCSuccess(rc);
2249
2250	switch (iReg)
2251	{
2252	case HDA_REG_CORBLBASE:
2253	pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
2254	pThis->u64CORBBase \|= pThis->au32Regs[iRegMem];
2255	break;
2256	case HDA_REG_CORBUBASE:
2257	pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
2258	pThis->u64CORBBase \|= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2259	break;
2260	case HDA_REG_RIRBLBASE:
2261	pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
2262	pThis->u64RIRBBase \|= pThis->au32Regs[iRegMem];
2263	break;
2264	case HDA_REG_RIRBUBASE:
2265	pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
2266	pThis->u64RIRBBase \|= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2267	break;
2268	case HDA_REG_DPLBASE:
2269	{
2270	pThis->u64DPBase = pThis->au32Regs[iRegMem] & DPBASE_ADDR_MASK;
2271	Assert(pThis->u64DPBase % 128 == 0); /* Must be 128-byte aligned. */
2272
2273	/* Also make sure to handle the DMA position enable bit. */
2274	pThis->fDMAPosition = pThis->au32Regs[iRegMem] & RT_BIT_32(0);
2275	LogRel(("HDA: %s DMA position buffer\n", pThis->fDMAPosition ? "Enabled" : "Disabled"));
2276	break;
2277	}
2278	case HDA_REG_DPUBASE:
2279	pThis->u64DPBase = RT_MAKE_U64(RT_LO_U32(pThis->u64DPBase) & DPBASE_ADDR_MASK, pThis->au32Regs[iRegMem]);
2280	break;
2281	default:
2282	AssertMsgFailed(("Invalid index\n"));
2283	break;
2284	}
2285
2286	LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
2287	pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
2288
2289	DEVHDA_UNLOCK(pThis);
2290	return rc;
2291	}
2292
2293	static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2294	{
2295	RT_NOREF_PV(iReg);
2296	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2297
2298	uint8_t v = HDA_REG(pThis, RIRBSTS);
2299	HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
2300
2301	#ifndef LOG_ENABLED
2302	int rc = hdaProcessInterrupt(pThis);
2303	#else
2304	int rc = hdaProcessInterrupt(pThis, __FUNCTION__);
2305	#endif
2306
2307	DEVHDA_UNLOCK(pThis);
2308	return rc;
2309	}
2310
2311	#ifdef IN_RING3
2312
2313	/**
2314	* Retrieves a corresponding sink for a given mixer control.
2315	* Returns NULL if no sink is found.
2316	*
2317	* @return PHDAMIXERSINK
2318	* @param pThis HDA state.
2319	* @param enmMixerCtl Mixer control to get the corresponding sink for.
2320	*/
2321	static PHDAMIXERSINK hdaR3MixerControlToSink(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
2322	{
2323	PHDAMIXERSINK pSink;
2324
2325	switch (enmMixerCtl)
2326	{
2327	case PDMAUDIOMIXERCTL_VOLUME_MASTER:
2328	/* Fall through is intentional. */
2329	case PDMAUDIOMIXERCTL_FRONT:
2330	pSink = &pThis->SinkFront;
2331	break;
2332	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2333	case PDMAUDIOMIXERCTL_CENTER_LFE:
2334	pSink = &pThis->SinkCenterLFE;
2335	break;
2336	case PDMAUDIOMIXERCTL_REAR:
2337	pSink = &pThis->SinkRear;
2338	break;
2339	# endif
2340	case PDMAUDIOMIXERCTL_LINE_IN:
2341	pSink = &pThis->SinkLineIn;
2342	break;
2343	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2344	case PDMAUDIOMIXERCTL_MIC_IN:
2345	pSink = &pThis->SinkMicIn;
2346	break;
2347	# endif
2348	default:
2349	pSink = NULL;
2350	AssertMsgFailed(("Unhandled mixer control\n"));
2351	break;
2352	}
2353
2354	return pSink;
2355	}
2356
2357	/**
2358	* Adds a driver stream to a specific mixer sink.
2359	*
2360	* @returns IPRT status code (ignored by caller).
2361	* @param pThis HDA state.
2362	* @param pMixSink Audio mixer sink to add audio streams to.
2363	* @param pCfg Audio stream configuration to use for the audio streams to add.
2364	* @param pDrv Driver stream to add.
2365	*/
2366	static int hdaR3MixerAddDrvStream(PHDASTATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg, PHDADRIVER pDrv)
2367	{
2368	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2369	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
2370	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2371
2372	LogFunc(("Sink=%s, Stream=%s\n", pMixSink->pszName, pCfg->szName));
2373
2374	PPDMAUDIOSTREAMCFG pStreamCfg = DrvAudioHlpStreamCfgDup(pCfg);
2375	if (!pStreamCfg)
2376	return VERR_NO_MEMORY;
2377
2378	LogFunc(("[LUN#%RU8] %s\n", pDrv->uLUN, pStreamCfg->szName));
2379
2380	int rc = VINF_SUCCESS;
2381
2382	PHDADRIVERSTREAM pDrvStream = NULL;
2383
2384	if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
2385	{
2386	LogFunc(("enmRecSource=%d\n", pStreamCfg->DestSource.Source));
2387
2388	switch (pStreamCfg->DestSource.Source)
2389	{
2390	case PDMAUDIORECSOURCE_LINE:
2391	pDrvStream = &pDrv->LineIn;
2392	break;
2393	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2394	case PDMAUDIORECSOURCE_MIC:
2395	pDrvStream = &pDrv->MicIn;
2396	break;
2397	# endif
2398	default:
2399	rc = VERR_NOT_SUPPORTED;
2400	break;
2401	}
2402	}
2403	else if (pStreamCfg->enmDir == PDMAUDIODIR_OUT)
2404	{
2405	LogFunc(("enmPlaybackDest=%d\n", pStreamCfg->DestSource.Dest));
2406
2407	switch (pStreamCfg->DestSource.Dest)
2408	{
2409	case PDMAUDIOPLAYBACKDEST_FRONT:
2410	pDrvStream = &pDrv->Front;
2411	break;
2412	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2413	case PDMAUDIOPLAYBACKDEST_CENTER_LFE:
2414	pDrvStream = &pDrv->CenterLFE;
2415	break;
2416	case PDMAUDIOPLAYBACKDEST_REAR:
2417	pDrvStream = &pDrv->Rear;
2418	break;
2419	# endif
2420	default:
2421	rc = VERR_NOT_SUPPORTED;
2422	break;
2423	}
2424	}
2425	else
2426	rc = VERR_NOT_SUPPORTED;
2427
2428	if (RT_SUCCESS(rc))
2429	{
2430	AssertPtr(pDrvStream);
2431	AssertMsg(pDrvStream->pMixStrm == NULL, ("[LUN#%RU8] Driver stream already present when it must not\n", pDrv->uLUN));
2432
2433	PAUDMIXSTREAM pMixStrm;
2434	rc = AudioMixerSinkCreateStream(pMixSink, pDrv->pConnector, pStreamCfg, 0 /* fFlags */, &pMixStrm);
2435	LogFlowFunc(("LUN#%RU8: Created stream \"%s\" for sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
2436	if (RT_SUCCESS(rc))
2437	{
2438	rc = AudioMixerSinkAddStream(pMixSink, pMixStrm);
2439	LogFlowFunc(("LUN#%RU8: Added stream \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
2440	if (RT_SUCCESS(rc))
2441	{
2442	/* If this is an input stream, always set the latest (added) stream
2443	* as the recording source.
2444	* @todo Make the recording source dynamic (CFGM?). */
2445	if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
2446	{
2447	PDMAUDIOBACKENDCFG Cfg;
2448	rc = pDrv->pConnector->pfnGetConfig(pDrv->pConnector, &Cfg);
2449	if (RT_SUCCESS(rc))
2450	{
2451	if (Cfg.cMaxStreamsIn) /* At least one input source available? */
2452	{
2453	rc = AudioMixerSinkSetRecordingSource(pMixSink, pMixStrm);
2454	LogFlowFunc(("LUN#%RU8: Recording source for '%s' -> '%s', rc=%Rrc\n",
2455	pDrv->uLUN, pStreamCfg->szName, Cfg.szName, rc));
2456
2457	if (RT_SUCCESS(rc))
2458	LogRel(("HDA: Set recording source for '%s' to '%s'\n",
2459	pStreamCfg->szName, Cfg.szName));
2460	}
2461	else
2462	LogRel(("HDA: Backend '%s' currently is not offering any recording source for '%s', muting\n",
2463	Cfg.szName, pStreamCfg->szName));
2464	}
2465	else if (RT_FAILURE(rc))
2466	LogFunc(("LUN#%RU8: Unable to retrieve backend configuration for '%s', rc=%Rrc\n",
2467	pDrv->uLUN, pStreamCfg->szName, rc));
2468	}
2469	}
2470	}
2471
2472	if (RT_SUCCESS(rc))
2473	pDrvStream->pMixStrm = pMixStrm;
2474	}
2475
2476	RTMemFree(pStreamCfg);
2477
2478	LogFlowFuncLeaveRC(rc);
2479	return rc;
2480	}
2481
2482	/**
2483	* Adds all current driver streams to a specific mixer sink.
2484	*
2485	* @returns IPRT status code.
2486	* @param pThis HDA state.
2487	* @param pMixSink Audio mixer sink to add stream to.
2488	* @param pCfg Audio stream configuration to use for the audio streams to add.
2489	*/
2490	static int hdaR3MixerAddDrvStreams(PHDASTATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg)
2491	{
2492	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2493	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
2494	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2495
2496	LogFunc(("Sink=%s, Stream=%s\n", pMixSink->pszName, pCfg->szName));
2497
2498	if (!DrvAudioHlpStreamCfgIsValid(pCfg))
2499	return VERR_INVALID_PARAMETER;
2500
2501	int rc = AudioMixerSinkSetFormat(pMixSink, &pCfg->Props);
2502	if (RT_FAILURE(rc))
2503	return rc;
2504
2505	PHDADRIVER pDrv;
2506	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2507	{
2508	int rc2 = hdaR3MixerAddDrvStream(pThis, pMixSink, pCfg, pDrv);
2509	if (RT_FAILURE(rc2))
2510	LogFunc(("Attaching stream failed with %Rrc\n", rc2));
2511
2512	/* Do not pass failure to rc here, as there might be drivers which aren't
2513	* configured / ready yet. */
2514	}
2515
2516	return rc;
2517	}
2518
2519	/**
2520	* @interface_method_impl{HDACODEC,pfnCbMixerAddStream}
2521	*
2522	* Adds a new audio stream to a specific mixer control.
2523	*
2524	* Depending on the mixer control the stream then gets assigned to one of the internal
2525	* mixer sinks, which in turn then handle the mixing of all connected streams to that sink.
2526	*
2527	* @return IPRT status code.
2528	* @param pThis HDA state.
2529	* @param enmMixerCtl Mixer control to assign new stream to.
2530	* @param pCfg Stream configuration for the new stream.
2531	*/
2532	static DECLCALLBACK(int) hdaR3MixerAddStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOSTREAMCFG pCfg)
2533	{
2534	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2535	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2536
2537	int rc;
2538
2539	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2540	if (pSink)
2541	{
2542	rc = hdaR3MixerAddDrvStreams(pThis, pSink->pMixSink, pCfg);
2543
2544	AssertPtr(pSink->pMixSink);
2545	LogFlowFunc(("Sink=%s, Mixer control=%s\n", pSink->pMixSink->pszName, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl)));
2546	}
2547	else
2548	rc = VERR_NOT_FOUND;
2549
2550	LogFlowFuncLeaveRC(rc);
2551	return rc;
2552	}
2553
2554	/**
2555	* @interface_method_impl{HDACODEC,pfnCbMixerRemoveStream}
2556	*
2557	* Removes a specified mixer control from the HDA's mixer.
2558	*
2559	* @return IPRT status code.
2560	* @param pThis HDA state.
2561	* @param enmMixerCtl Mixer control to remove.
2562	*
2563	* @remarks Can be called as a callback by the HDA codec.
2564	*/
2565	static DECLCALLBACK(int) hdaR3MixerRemoveStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
2566	{
2567	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2568
2569	int rc;
2570
2571	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2572	if (pSink)
2573	{
2574	PHDADRIVER pDrv;
2575	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2576	{
2577	PAUDMIXSTREAM pMixStream = NULL;
2578	switch (enmMixerCtl)
2579	{
2580	/*
2581	* Input.
2582	*/
2583	case PDMAUDIOMIXERCTL_LINE_IN:
2584	pMixStream = pDrv->LineIn.pMixStrm;
2585	pDrv->LineIn.pMixStrm = NULL;
2586	break;
2587	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2588	case PDMAUDIOMIXERCTL_MIC_IN:
2589	pMixStream = pDrv->MicIn.pMixStrm;
2590	pDrv->MicIn.pMixStrm = NULL;
2591	break;
2592	# endif
2593	/*
2594	* Output.
2595	*/
2596	case PDMAUDIOMIXERCTL_FRONT:
2597	pMixStream = pDrv->Front.pMixStrm;
2598	pDrv->Front.pMixStrm = NULL;
2599	break;
2600	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2601	case PDMAUDIOMIXERCTL_CENTER_LFE:
2602	pMixStream = pDrv->CenterLFE.pMixStrm;
2603	pDrv->CenterLFE.pMixStrm = NULL;
2604	break;
2605	case PDMAUDIOMIXERCTL_REAR:
2606	pMixStream = pDrv->Rear.pMixStrm;
2607	pDrv->Rear.pMixStrm = NULL;
2608	break;
2609	# endif
2610	default:
2611	AssertMsgFailed(("Mixer control %d not implemented\n", enmMixerCtl));
2612	break;
2613	}
2614
2615	if (pMixStream)
2616	{
2617	AudioMixerSinkRemoveStream(pSink->pMixSink, pMixStream);
2618	AudioMixerStreamDestroy(pMixStream);
2619
2620	pMixStream = NULL;
2621	}
2622	}
2623
2624	AudioMixerSinkRemoveAllStreams(pSink->pMixSink);
2625	rc = VINF_SUCCESS;
2626	}
2627	else
2628	rc = VERR_NOT_FOUND;
2629
2630	LogFunc(("Mixer control=%s, rc=%Rrc\n", DrvAudioHlpAudMixerCtlToStr(enmMixerCtl), rc));
2631	return rc;
2632	}
2633
2634	/**
2635	* @interface_method_impl{HDACODEC,pfnCbMixerControl}
2636	*
2637	* Controls an input / output converter widget, that is, which converter is connected
2638	* to which stream (and channel).
2639	*
2640	* @returns IPRT status code.
2641	* @param pThis HDA State.
2642	* @param enmMixerCtl Mixer control to set SD stream number and channel for.
2643	* @param uSD SD stream number (number + 1) to set. Set to 0 for unassign.
2644	* @param uChannel Channel to set. Only valid if a valid SD stream number is specified.
2645	*
2646	* @remarks Can be called as a callback by the HDA codec.
2647	*/
2648	static DECLCALLBACK(int) hdaR3MixerControl(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, uint8_t uSD, uint8_t uChannel)
2649	{
2650	LogFunc(("enmMixerCtl=%s, uSD=%RU8, uChannel=%RU8\n", DrvAudioHlpAudMixerCtlToStr(enmMixerCtl), uSD, uChannel));
2651
2652	if (uSD == 0) /* Stream number 0 is reserved. */
2653	{
2654	Log2Func(("Invalid SDn (%RU8) number for mixer control '%s', ignoring\n", uSD, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl)));
2655	return VINF_SUCCESS;
2656	}
2657	/* uChannel is optional. */
2658
2659	/* SDn0 starts as 1. */
2660	Assert(uSD);
2661	uSD--;
2662
2663	# ifndef VBOX_WITH_AUDIO_HDA_MIC_IN
2664	/* Only SDI0 (Line-In) is supported. */
2665	if ( hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN
2666	&& uSD >= 1)
2667	{
2668	LogRel2(("HDA: Dedicated Mic-In support not imlpemented / built-in (stream #%RU8), using Line-In (stream #0) instead\n", uSD));
2669	uSD = 0;
2670	}
2671	# endif
2672
2673	int rc = VINF_SUCCESS;
2674
2675	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2676	if (pSink)
2677	{
2678	AssertPtr(pSink->pMixSink);
2679
2680	/* If this an output stream, determine the correct SD#. */
2681	if ( (uSD < HDA_MAX_SDI)
2682	&& AudioMixerSinkGetDir(pSink->pMixSink) == AUDMIXSINKDIR_OUTPUT)
2683	{
2684	uSD += HDA_MAX_SDI;
2685	}
2686
2687	/* Detach the existing stream from the sink. */
2688	if ( pSink->pStream
2689	&& ( pSink->pStream->u8SD != uSD
2690	\|\| pSink->pStream->u8Channel != uChannel)
2691	)
2692	{
2693	LogFunc(("Sink '%s' was assigned to stream #%RU8 (channel %RU8) before\n",
2694	pSink->pMixSink->pszName, pSink->pStream->u8SD, pSink->pStream->u8Channel));
2695
2696	hdaR3StreamLock(pSink->pStream);
2697
2698	/* Only disable the stream if the stream descriptor # has changed. */
2699	if (pSink->pStream->u8SD != uSD)
2700	hdaR3StreamEnable(pSink->pStream, false);
2701
2702	pSink->pStream->pMixSink = NULL;
2703
2704	hdaR3StreamUnlock(pSink->pStream);
2705
2706	pSink->pStream = NULL;
2707	}
2708
2709	Assert(uSD < HDA_MAX_STREAMS);
2710
2711	/* Attach the new stream to the sink.
2712	* Enabling the stream will be done by the gust via a separate SDnCTL call then. */
2713	if (pSink->pStream == NULL)
2714	{
2715	LogRel2(("HDA: Setting sink '%s' to stream #%RU8 (channel %RU8), mixer control=%s\n",
2716	pSink->pMixSink->pszName, uSD, uChannel, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl)));
2717
2718	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
2719	if (pStream)
2720	{
2721	hdaR3StreamLock(pStream);
2722
2723	pSink->pStream = pStream;
2724
2725	pStream->u8Channel = uChannel;
2726	pStream->pMixSink = pSink;
2727
2728	hdaR3StreamUnlock(pStream);
2729
2730	rc = VINF_SUCCESS;
2731	}
2732	else
2733	rc = VERR_NOT_IMPLEMENTED;
2734	}
2735	}
2736	else
2737	rc = VERR_NOT_FOUND;
2738
2739	if (RT_FAILURE(rc))
2740	LogRel(("HDA: Converter control for stream #%RU8 (channel %RU8) / mixer control '%s' failed with %Rrc, skipping\n",
2741	uSD, uChannel, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl), rc));
2742
2743	LogFlowFuncLeaveRC(rc);
2744	return rc;
2745	}
2746
2747	/**
2748	* @interface_method_impl{HDACODEC,pfnCbMixerSetVolume}
2749	*
2750	* Sets the volume of a specified mixer control.
2751	*
2752	* @return IPRT status code.
2753	* @param pThis HDA State.
2754	* @param enmMixerCtl Mixer control to set volume for.
2755	* @param pVol Pointer to volume data to set.
2756	*
2757	* @remarks Can be called as a callback by the HDA codec.
2758	*/
2759	static DECLCALLBACK(int) hdaR3MixerSetVolume(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOVOLUME pVol)
2760	{
2761	int rc;
2762
2763	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2764	if ( pSink
2765	&& pSink->pMixSink)
2766	{
2767	LogRel2(("HDA: Setting volume for mixer sink '%s' to %RU8/%RU8 (%s)\n",
2768	pSink->pMixSink->pszName, pVol->uLeft, pVol->uRight, pVol->fMuted ? "Muted" : "Unmuted"));
2769
2770	/* Set the volume.
2771	* We assume that the codec already converted it to the correct range. */
2772	rc = AudioMixerSinkSetVolume(pSink->pMixSink, pVol);
2773	}
2774	else
2775	rc = VERR_NOT_FOUND;
2776
2777	LogFlowFuncLeaveRC(rc);
2778	return rc;
2779	}
2780
2781	/**
2782	* Main routine for the stream's timer.
2783	*
2784	* @param pDevIns Device instance.
2785	* @param pTimer Timer this callback was called for.
2786	* @param pvUser Pointer to associated HDASTREAM.
2787	*/
2788	static DECLCALLBACK(void) hdaR3Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2789	{
2790	RT_NOREF(pDevIns, pTimer);
2791
2792	PHDASTREAM pStream = (PHDASTREAM)pvUser;
2793	AssertPtr(pStream);
2794
2795	PHDASTATE pThis = pStream->pHDAState;
2796
2797	DEVHDA_LOCK_BOTH_RETURN_VOID(pStream->pHDAState, pStream->u8SD);
2798
2799	hdaR3StreamUpdate(pStream, true /* fInTimer */);
2800
2801	/* Flag indicating whether to kick the timer again for a
2802	* new data processing round. */
2803	const bool fSinkActive = AudioMixerSinkIsActive(pStream->pMixSink->pMixSink);
2804	if (fSinkActive)
2805	{
2806	const bool fTimerScheduled = hdaR3StreamTransferIsScheduled(pStream);
2807	Log3Func(("fSinksActive=%RTbool, fTimerScheduled=%RTbool\n", fSinkActive, fTimerScheduled));
2808	if (!fTimerScheduled)
2809	hdaR3TimerSet(pThis, pStream,
2810	TMTimerGet(pThis->pTimer[pStream->u8SD])
2811	+ TMTimerGetFreq(pThis->pTimer[pStream->u8SD]) / pStream->pHDAState->u16TimerHz,
2812	true /* fForce */);
2813	}
2814	else
2815	Log3Func(("fSinksActive=%RTbool\n", fSinkActive));
2816
2817	DEVHDA_UNLOCK_BOTH(pThis, pStream->u8SD);
2818	}
2819
2820	# ifdef HDA_USE_DMA_ACCESS_HANDLER
2821	/**
2822	* HC access handler for the FIFO.
2823	*
2824	* @returns VINF_SUCCESS if the handler have carried out the operation.
2825	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2826	* @param pVM VM Handle.
2827	* @param pVCpu The cross context CPU structure for the calling EMT.
2828	* @param GCPhys The physical address the guest is writing to.
2829	* @param pvPhys The HC mapping of that address.
2830	* @param pvBuf What the guest is reading/writing.
2831	* @param cbBuf How much it's reading/writing.
2832	* @param enmAccessType The access type.
2833	* @param enmOrigin Who is making the access.
2834	* @param pvUser User argument.
2835	*/
2836	static DECLCALLBACK(VBOXSTRICTRC) hdaR3DMAAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys,
2837	void *pvBuf, size_t cbBuf,
2838	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2839	{
2840	RT_NOREF(pVM, pVCpu, pvPhys, pvBuf, enmOrigin);
2841
2842	PHDADMAACCESSHANDLER pHandler = (PHDADMAACCESSHANDLER)pvUser;
2843	AssertPtr(pHandler);
2844
2845	PHDASTREAM pStream = pHandler->pStream;
2846	AssertPtr(pStream);
2847
2848	Assert(GCPhys >= pHandler->GCPhysFirst);
2849	Assert(GCPhys <= pHandler->GCPhysLast);
2850	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
2851
2852	/* Not within BDLE range? Bail out. */
2853	if ( (GCPhys < pHandler->BDLEAddr)
2854	\|\| (GCPhys + cbBuf > pHandler->BDLEAddr + pHandler->BDLESize))
2855	{
2856	return VINF_PGM_HANDLER_DO_DEFAULT;
2857	}
2858
2859	switch(enmAccessType)
2860	{
2861	case PGMACCESSTYPE_WRITE:
2862	{
2863	# ifdef DEBUG
2864	PHDASTREAMDBGINFO pStreamDbg = &pStream->Dbg;
2865
2866	const uint64_t tsNowNs = RTTimeNanoTS();
2867	const uint32_t tsElapsedMs = (tsNowNs - pStreamDbg->tsWriteSlotBegin) / 1000 / 1000;
2868
2869	uint64_t cWritesHz = ASMAtomicReadU64(&pStreamDbg->cWritesHz);
2870	uint64_t cbWrittenHz = ASMAtomicReadU64(&pStreamDbg->cbWrittenHz);
2871
2872	if (tsElapsedMs >= (1000 / HDA_TIMER_HZ_DEFAULT))
2873	{
2874	LogFunc(("[SD%RU8] %RU32ms elapsed, cbWritten=%RU64, cWritten=%RU64 -- %RU32 bytes on average per time slot (%zums)\n",
2875	pStream->u8SD, tsElapsedMs, cbWrittenHz, cWritesHz,
2876	ASMDivU64ByU32RetU32(cbWrittenHz, cWritesHz ? cWritesHz : 1), 1000 / HDA_TIMER_HZ_DEFAULT));
2877
2878	pStreamDbg->tsWriteSlotBegin = tsNowNs;
2879
2880	cWritesHz = 0;
2881	cbWrittenHz = 0;
2882	}
2883
2884	cWritesHz += 1;
2885	cbWrittenHz += cbBuf;
2886
2887	ASMAtomicIncU64(&pStreamDbg->cWritesTotal);
2888	ASMAtomicAddU64(&pStreamDbg->cbWrittenTotal, cbBuf);
2889
2890	ASMAtomicWriteU64(&pStreamDbg->cWritesHz, cWritesHz);
2891	ASMAtomicWriteU64(&pStreamDbg->cbWrittenHz, cbWrittenHz);
2892
2893	LogFunc(("[SD%RU8] Writing %3zu @ 0x%x (off %zu)\n",
2894	pStream->u8SD, cbBuf, GCPhys, GCPhys - pHandler->BDLEAddr));
2895
2896	LogFunc(("[SD%RU8] cWrites=%RU64, cbWritten=%RU64 -> %RU32 bytes on average\n",
2897	pStream->u8SD, pStreamDbg->cWritesTotal, pStreamDbg->cbWrittenTotal,
2898	ASMDivU64ByU32RetU32(pStreamDbg->cbWrittenTotal, pStreamDbg->cWritesTotal)));
2899	# endif
2900
2901	if (pThis->fDebugEnabled)
2902	{
2903	RTFILE fh;
2904	RTFileOpen(&fh, VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH "hdaDMAAccessWrite.pcm",
2905	RTFILE_O_OPEN_CREATE \| RTFILE_O_APPEND \| RTFILE_O_WRITE \| RTFILE_O_DENY_NONE);
2906	RTFileWrite(fh, pvBuf, cbBuf, NULL);
2907	RTFileClose(fh);
2908	}
2909
2910	# ifdef HDA_USE_DMA_ACCESS_HANDLER_WRITING
2911	PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
2912	AssertPtr(pCircBuf);
2913
2914	uint8_t pbBuf = (uint8_t )pvBuf;
2915	while (cbBuf)
2916	{
2917	/* Make sure we only copy as much as the stream's FIFO can hold (SDFIFOS, 18.2.39). */
2918	void *pvChunk;
2919	size_t cbChunk;
2920	RTCircBufAcquireWriteBlock(pCircBuf, cbBuf, &pvChunk, &cbChunk);
2921
2922	if (cbChunk)
2923	{
2924	memcpy(pvChunk, pbBuf, cbChunk);
2925
2926	pbBuf += cbChunk;
2927	Assert(cbBuf >= cbChunk);
2928	cbBuf -= cbChunk;
2929	}
2930	else
2931	{
2932	//AssertMsg(RTCircBufFree(pCircBuf), ("No more space but still %zu bytes to write\n", cbBuf));
2933	break;
2934	}
2935
2936	LogFunc(("[SD%RU8] cbChunk=%zu\n", pStream->u8SD, cbChunk));
2937
2938	RTCircBufReleaseWriteBlock(pCircBuf, cbChunk);
2939	}
2940	# endif /* HDA_USE_DMA_ACCESS_HANDLER_WRITING */
2941	break;
2942	}
2943
2944	default:
2945	AssertMsgFailed(("Access type not implemented\n"));
2946	break;
2947	}
2948
2949	return VINF_PGM_HANDLER_DO_DEFAULT;
2950	}
2951	# endif /* HDA_USE_DMA_ACCESS_HANDLER */
2952
2953	/**
2954	* Soft reset of the device triggered via GCTL.
2955	*
2956	* @param pThis HDA state.
2957	*
2958	*/
2959	static void hdaR3GCTLReset(PHDASTATE pThis)
2960	{
2961	LogFlowFuncEnter();
2962
2963	pThis->cStreamsActive = 0;
2964
2965	HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(HDA_MAX_SDO, HDA_MAX_SDI, 0, 0, 1); /* see 6.2.1 */
2966	HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
2967	HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
2968	HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
2969	HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
2970	HDA_REG(pThis, CORBSIZE) = 0x42; /* Up to 256 CORB entries see 6.2.1 */
2971	HDA_REG(pThis, RIRBSIZE) = 0x42; /* Up to 256 RIRB entries see 6.2.1 */
2972	HDA_REG(pThis, CORBRP) = 0x0;
2973	HDA_REG(pThis, CORBWP) = 0x0;
2974	HDA_REG(pThis, RIRBWP) = 0x0;
2975	/* Some guests (like Haiku) don't set RINTCNT explicitly but expect an interrupt after each
2976	* RIRB response -- so initialize RINTCNT to 1 by default. */
2977	HDA_REG(pThis, RINTCNT) = 0x1;
2978
2979	/*
2980	* Stop any audio currently playing and/or recording.
2981	*/
2982	pThis->SinkFront.pStream = NULL;
2983	if (pThis->SinkFront.pMixSink)
2984	AudioMixerSinkReset(pThis->SinkFront.pMixSink);
2985	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2986	pThis->SinkMicIn.pStream = NULL;
2987	if (pThis->SinkMicIn.pMixSink)
2988	AudioMixerSinkReset(pThis->SinkMicIn.pMixSink);
2989	# endif
2990	pThis->SinkLineIn.pStream = NULL;
2991	if (pThis->SinkLineIn.pMixSink)
2992	AudioMixerSinkReset(pThis->SinkLineIn.pMixSink);
2993	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2994	pThis->SinkCenterLFE = NULL;
2995	if (pThis->SinkCenterLFE.pMixSink)
2996	AudioMixerSinkReset(pThis->SinkCenterLFE.pMixSink);
2997	pThis->SinkRear.pStream = NULL;
2998	if (pThis->SinkRear.pMixSink)
2999	AudioMixerSinkReset(pThis->SinkRear.pMixSink);
3000	# endif
3001
3002	/*
3003	* Reset the codec.
3004	*/
3005	if ( pThis->pCodec
3006	&& pThis->pCodec->pfnReset)
3007	{
3008	pThis->pCodec->pfnReset(pThis->pCodec);
3009	}
3010
3011	/*
3012	* Set some sensible defaults for which HDA sinks
3013	* are connected to which stream number.
3014	*
3015	* We use SD0 for input and SD4 for output by default.
3016	* These stream numbers can be changed by the guest dynamically lateron.
3017	*/
3018	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3019	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_MIC_IN , 1 /* SD0 /, 0 / Channel */);
3020	# endif
3021	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_LINE_IN , 1 /* SD0 /, 0 / Channel */);
3022
3023	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_FRONT , 5 /* SD4 /, 0 / Channel */);
3024	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3025	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_CENTER_LFE, 5 /* SD4 /, 0 / Channel */);
3026	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_REAR , 5 /* SD4 /, 0 / Channel */);
3027	# endif
3028
3029	/* Reset CORB. */
3030	pThis->cbCorbBuf = HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE;
3031	RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
3032
3033	/* Reset RIRB. */
3034	pThis->cbRirbBuf = HDA_RIRB_SIZE * HDA_RIRB_ELEMENT_SIZE;
3035	RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
3036
3037	/* Clear our internal response interrupt counter. */
3038	pThis->u16RespIntCnt = 0;
3039
3040	for (uint8_t uSD = 0; uSD < HDA_MAX_STREAMS; ++uSD)
3041	{
3042	int rc2 = hdaR3StreamEnable(&pThis->aStreams[uSD], false /* fEnable */);
3043	if (RT_SUCCESS(rc2))
3044	{
3045	/* Remove the RUN bit from SDnCTL in case the stream was in a running state before. */
3046	HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_RUN;
3047	hdaR3StreamReset(pThis, &pThis->aStreams[uSD], uSD);
3048	}
3049	}
3050
3051	/* Clear stream tags <-> objects mapping table. */
3052	RT_ZERO(pThis->aTags);
3053
3054	/* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
3055	HDA_REG(pThis, STATESTS) = 0x1;
3056
3057	LogFlowFuncLeave();
3058	LogRel(("HDA: Reset\n"));
3059	}
3060
3061	#endif /* IN_RING3 */
3062
3063	/* MMIO callbacks */
3064
3065	/**
3066	* @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
3067	*
3068	* @note During implementation, we discovered so-called "forgotten" or "hole"
3069	* registers whose description is not listed in the RPM, datasheet, or
3070	* spec.
3071	*/
3072	PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
3073	{
3074	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3075	int rc;
3076	RT_NOREF_PV(pvUser);
3077	Assert(pThis->uAlignmentCheckMagic == HDASTATE_ALIGNMENT_CHECK_MAGIC);
3078
3079	/*
3080	* Look up and log.
3081	*/
3082	uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3083	int idxRegDsc = hdaRegLookup(offReg); /* Register descriptor index. */
3084	#ifdef LOG_ENABLED
3085	unsigned const cbLog = cb;
3086	uint32_t offRegLog = offReg;
3087	#endif
3088
3089	Log3Func(("offReg=%#x cb=%#x\n", offReg, cb));
3090	Assert(cb == 4); Assert((offReg & 3) == 0);
3091
3092	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
3093
3094	if (!(HDA_REG(pThis, GCTL) & HDA_GCTL_CRST) && idxRegDsc != HDA_REG_GCTL)
3095	LogFunc(("Access to registers except GCTL is blocked while reset\n"));
3096
3097	if (idxRegDsc == -1)
3098	LogRel(("HDA: Invalid read access @0x%x (bytes=%u)\n", offReg, cb));
3099
3100	if (idxRegDsc != -1)
3101	{
3102	/* Leave lock before calling read function. */
3103	DEVHDA_UNLOCK(pThis);
3104
3105	/* ASSUMES gapless DWORD at end of map. */
3106	if (g_aHdaRegMap[idxRegDsc].size == 4)
3107	{
3108	/*
3109	* Straight forward DWORD access.
3110	*/
3111	rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
3112	Log3Func(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, (uint32_t )pv, rc));
3113	}
3114	else
3115	{
3116	/*
3117	* Multi register read (unless there are trailing gaps).
3118	* ASSUMES that only DWORD reads have sideeffects.
3119	*/
3120	#ifdef IN_RING3
3121	uint32_t u32Value = 0;
3122	unsigned cbLeft = 4;
3123	do
3124	{
3125	uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
3126	uint32_t u32Tmp = 0;
3127
3128	rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
3129	Log3Func(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
3130	if (rc != VINF_SUCCESS)
3131	break;
3132	u32Value \|= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
3133
3134	cbLeft -= cbReg;
3135	offReg += cbReg;
3136	idxRegDsc++;
3137	} while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
3138
3139	if (rc == VINF_SUCCESS)
3140	(uint32_t )pv = u32Value;
3141	else
3142	Assert(!IOM_SUCCESS(rc));
3143	#else /* !IN_RING3 */
3144	/* Take the easy way out. */
3145	rc = VINF_IOM_R3_MMIO_READ;
3146	#endif /* !IN_RING3 */
3147	}
3148	}
3149	else
3150	{
3151	DEVHDA_UNLOCK(pThis);
3152
3153	rc = VINF_IOM_MMIO_UNUSED_FF;
3154	Log3Func(("\tHole at %x is accessed for read\n", offReg));
3155	}
3156
3157	/*
3158	* Log the outcome.
3159	*/
3160	#ifdef LOG_ENABLED
3161	if (cbLog == 4)
3162	Log3Func(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, (uint32_t )pv, rc));
3163	else if (cbLog == 2)
3164	Log3Func(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, (uint16_t )pv, rc));
3165	else if (cbLog == 1)
3166	Log3Func(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, (uint8_t )pv, rc));
3167	#endif
3168	return rc;
3169	}
3170
3171
3172	DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
3173	{
3174	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
3175
3176	if (!(HDA_REG(pThis, GCTL) & HDA_GCTL_CRST) && idxRegDsc != HDA_REG_GCTL)
3177	{
3178	Log(("hdaWriteReg: Warning: Access to %s is blocked while controller is in reset mode\n", g_aHdaRegMap[idxRegDsc].abbrev));
3179	LogRel2(("HDA: Warning: Access to register %s is blocked while controller is in reset mode\n",
3180	g_aHdaRegMap[idxRegDsc].abbrev));
3181
3182	DEVHDA_UNLOCK(pThis);
3183	return VINF_SUCCESS;
3184	}
3185
3186	/*
3187	* Handle RD (register description) flags.
3188	*/
3189
3190	/* For SDI / SDO: Check if writes to those registers are allowed while SDCTL's RUN bit is set. */
3191	if (idxRegDsc >= HDA_NUM_GENERAL_REGS)
3192	{
3193	const uint32_t uSDCTL = HDA_STREAM_REG(pThis, CTL, HDA_SD_NUM_FROM_REG(pThis, CTL, idxRegDsc));
3194
3195	/*
3196	* Some OSes (like Win 10 AU) violate the spec by writing stuff to registers which are not supposed to be be touched
3197	* while SDCTL's RUN bit is set. So just ignore those values.
3198	*/
3199
3200	/* Is the RUN bit currently set? */
3201	if ( RT_BOOL(uSDCTL & HDA_SDCTL_RUN)
3202	/* Are writes to the register denied if RUN bit is set? */
3203	&& !(g_aHdaRegMap[idxRegDsc].fFlags & HDA_RD_FLAG_SD_WRITE_RUN))
3204	{
3205	Log(("hdaWriteReg: Warning: Access to %s is blocked! %R[sdctl]\n", g_aHdaRegMap[idxRegDsc].abbrev, uSDCTL));
3206	LogRel2(("HDA: Warning: Access to register %s is blocked while the stream's RUN bit is set\n",
3207	g_aHdaRegMap[idxRegDsc].abbrev));
3208
3209	DEVHDA_UNLOCK(pThis);
3210	return VINF_SUCCESS;
3211	}
3212	}
3213
3214	/* Leave the lock before calling write function. */
3215	/** @todo r=bird: Why do we need to do that?? There is no
3216	* explanation why this is necessary here...
3217	*
3218	* More or less all write functions retake the lock, so why not let
3219	* those who need to drop the lock or take additional locks release
3220	* it? See, releasing a lock you already got always runs the risk
3221	* of someone else grabbing it and forcing you to wait, better to
3222	* do the two-three things a write handle needs to do than enter
3223	* and exit the lock all the time. */
3224	DEVHDA_UNLOCK(pThis);
3225
3226	#ifdef LOG_ENABLED
3227	uint32_t const idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3228	uint32_t const u32OldValue = pThis->au32Regs[idxRegMem];
3229	#endif
3230	int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
3231	Log3Func(("Written value %#x to %s[%d byte]; %x => %x%s, rc=%d\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
3232	g_aHdaRegMap[idxRegDsc].size, u32OldValue, pThis->au32Regs[idxRegMem], pszLog, rc));
3233	RT_NOREF(pszLog);
3234	return rc;
3235	}
3236
3237
3238	/**
3239	* @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
3240	*/
3241	PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
3242	{
3243	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3244	int rc;
3245	RT_NOREF_PV(pvUser);
3246	Assert(pThis->uAlignmentCheckMagic == HDASTATE_ALIGNMENT_CHECK_MAGIC);
3247
3248	/*
3249	* The behavior of accesses that aren't aligned on natural boundraries is
3250	* undefined. Just reject them outright.
3251	*/
3252	/** @todo IOM could check this, it could also split the 8 byte accesses for us. */
3253	Assert(cb == 1 \|\| cb == 2 \|\| cb == 4 \|\| cb == 8);
3254	if (GCPhysAddr & (cb - 1))
3255	return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
3256
3257	/*
3258	* Look up and log the access.
3259	*/
3260	uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3261	int idxRegDsc = hdaRegLookup(offReg);
3262	#if defined(IN_RING3) \|\| defined(LOG_ENABLED)
3263	uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
3264	#endif
3265	uint64_t u64Value;
3266	if (cb == 4) u64Value = (uint32_t const )pv;
3267	else if (cb == 2) u64Value = (uint16_t const )pv;
3268	else if (cb == 1) u64Value = (uint8_t const )pv;
3269	else if (cb == 8) u64Value = (uint64_t const )pv;
3270	else
3271	{
3272	u64Value = 0; /* shut up gcc. */
3273	AssertReleaseMsgFailed(("%u\n", cb));
3274	}
3275
3276	#ifdef LOG_ENABLED
3277	uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
3278	if (idxRegDsc == -1)
3279	Log3Func(("@%#05x u32=%#010x cb=%d\n", offReg, (uint32_t const )pv, cb));
3280	else if (cb == 4)
3281	Log3Func(("@%#05x u32=%#010x %s\n", offReg, (uint32_t )pv, g_aHdaRegMap[idxRegDsc].abbrev));
3282	else if (cb == 2)
3283	Log3Func(("@%#05x u16=%#06x (%#010x) %s\n", offReg, (uint16_t )pv, (uint32_t )pv, g_aHdaRegMap[idxRegDsc].abbrev));
3284	else if (cb == 1)
3285	Log3Func(("@%#05x u8=%#04x (%#010x) %s\n", offReg, (uint8_t )pv, (uint32_t )pv, g_aHdaRegMap[idxRegDsc].abbrev));
3286
3287	if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
3288	Log3Func(("\tsize=%RU32 != cb=%u!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
3289	#endif
3290
3291	/*
3292	* Try for a direct hit first.
3293	*/
3294	if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
3295	{
3296	rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
3297	Log3Func(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
3298	}
3299	/*
3300	* Partial or multiple register access, loop thru the requested memory.
3301	*/
3302	else
3303	{
3304	#ifdef IN_RING3
3305	/*
3306	* If it's an access beyond the start of the register, shift the input
3307	* value and fill in missing bits. Natural alignment rules means we
3308	* will only see 1 or 2 byte accesses of this kind, so no risk of
3309	* shifting out input values.
3310	*/
3311	if (idxRegDsc == -1 && (idxRegDsc = hdaR3RegLookupWithin(offReg)) != -1)
3312	{
3313	uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
3314	offReg -= cbBefore;
3315	idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3316	u64Value <<= cbBefore * 8;
3317	u64Value \|= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
3318	Log3Func(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
3319	cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
3320	}
3321
3322	/* Loop thru the write area, it may cover multiple registers. */
3323	rc = VINF_SUCCESS;
3324	for (;;)
3325	{
3326	uint32_t cbReg;
3327	if (idxRegDsc != -1)
3328	{
3329	idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3330	cbReg = g_aHdaRegMap[idxRegDsc].size;
3331	if (cb < cbReg)
3332	{
3333	u64Value \|= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
3334	Log3Func(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
3335	g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
3336	}
3337	# ifdef LOG_ENABLED
3338	uint32_t uLogOldVal = pThis->au32Regs[idxRegMem];
3339	# endif
3340	rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
3341	Log3Func(("\t%#x -> %#x\n", uLogOldVal, pThis->au32Regs[idxRegMem]));
3342	}
3343	else
3344	{
3345	LogRel(("HDA: Invalid write access @0x%x\n", offReg));
3346	cbReg = 1;
3347	}
3348	if (rc != VINF_SUCCESS)
3349	break;
3350	if (cbReg >= cb)
3351	break;
3352
3353	/* Advance. */
3354	offReg += cbReg;
3355	cb -= cbReg;
3356	u64Value >>= cbReg * 8;
3357	if (idxRegDsc == -1)
3358	idxRegDsc = hdaRegLookup(offReg);
3359	else
3360	{
3361	idxRegDsc++;
3362	if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
3363	\|\| g_aHdaRegMap[idxRegDsc].offset != offReg)
3364	{
3365	idxRegDsc = -1;
3366	}
3367	}
3368	}
3369
3370	#else /* !IN_RING3 */
3371	/* Take the simple way out. */
3372	rc = VINF_IOM_R3_MMIO_WRITE;
3373	#endif /* !IN_RING3 */
3374	}
3375
3376	return rc;
3377	}
3378
3379
3380	/* PCI callback. */
3381
3382	#ifdef IN_RING3
3383	/**
3384	* @callback_method_impl{FNPCIIOREGIONMAP}
3385	*/
3386	static DECLCALLBACK(int) hdaR3PciIoRegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3387	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
3388	{
3389	RT_NOREF(iRegion, enmType);
3390	PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
3391
3392	/*
3393	* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
3394	*
3395	* Let IOM talk DWORDs when reading, saves a lot of complications. On
3396	* writing though, we have to do it all ourselves because of sideeffects.
3397	*/
3398	Assert(enmType == PCI_ADDRESS_SPACE_MEM);
3399	int rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /pvUser/,
3400	IOMMMIO_FLAGS_READ_DWORD
3401	\| IOMMMIO_FLAGS_WRITE_PASSTHRU,
3402	hdaMMIOWrite, hdaMMIORead, "HDA");
3403
3404	if (RT_FAILURE(rc))
3405	return rc;
3406
3407	if (pThis->fRZEnabled)
3408	{
3409	rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /pvUser/,
3410	"hdaMMIOWrite", "hdaMMIORead");
3411	if (RT_FAILURE(rc))
3412	return rc;
3413
3414	rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /pvUser/,
3415	"hdaMMIOWrite", "hdaMMIORead");
3416	if (RT_FAILURE(rc))
3417	return rc;
3418	}
3419
3420	pThis->MMIOBaseAddr = GCPhysAddress;
3421	return VINF_SUCCESS;
3422	}
3423
3424
3425	/* Saved state workers and callbacks. */
3426
3427	static int hdaR3SaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStream)
3428	{
3429	RT_NOREF(pDevIns);
3430	#ifdef VBOX_STRICT
3431	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3432	#endif
3433
3434	Log2Func(("[SD%RU8]\n", pStream->u8SD));
3435
3436	/* Save stream ID. */
3437	int rc = SSMR3PutU8(pSSM, pStream->u8SD);
3438	AssertRCReturn(rc, rc);
3439	Assert(pStream->u8SD < HDA_MAX_STREAMS);
3440
3441	rc = SSMR3PutStructEx(pSSM, &pStream->State, sizeof(HDASTREAMSTATE), 0 /fFlags/, g_aSSMStreamStateFields7, NULL);
3442	AssertRCReturn(rc, rc);
3443
3444	#ifdef VBOX_STRICT /* Sanity checks. */
3445	uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
3446	HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
3447	uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
3448	uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
3449
3450	Assert(u64BaseDMA == pStream->u64BDLBase);
3451	Assert(u16LVI == pStream->u16LVI);
3452	Assert(u32CBL == pStream->u32CBL);
3453	#endif
3454
3455	rc = SSMR3PutStructEx(pSSM, &pStream->State.BDLE.Desc, sizeof(HDABDLEDESC),
3456	0 /fFlags/, g_aSSMBDLEDescFields7, NULL);
3457	AssertRCReturn(rc, rc);
3458
3459	rc = SSMR3PutStructEx(pSSM, &pStream->State.BDLE.State, sizeof(HDABDLESTATE),
3460	0 /fFlags/, g_aSSMBDLEStateFields7, NULL);
3461	AssertRCReturn(rc, rc);
3462
3463	rc = SSMR3PutStructEx(pSSM, &pStream->State.Period, sizeof(HDASTREAMPERIOD),
3464	0 /* fFlags */, g_aSSMStreamPeriodFields7, NULL);
3465	AssertRCReturn(rc, rc);
3466
3467	#ifdef VBOX_STRICT /* Sanity checks. */
3468	PHDABDLE pBDLE = &pStream->State.BDLE;
3469	if (u64BaseDMA)
3470	{
3471	Assert(pStream->State.uCurBDLE <= u16LVI + 1);
3472
3473	HDABDLE curBDLE;
3474	rc = hdaR3BDLEFetch(pThis, &curBDLE, u64BaseDMA, pStream->State.uCurBDLE);
3475	AssertRC(rc);
3476
3477	Assert(curBDLE.Desc.u32BufSize == pBDLE->Desc.u32BufSize);
3478	Assert(curBDLE.Desc.u64BufAdr == pBDLE->Desc.u64BufAdr);
3479	Assert(curBDLE.Desc.fFlags == pBDLE->Desc.fFlags);
3480	}
3481	else
3482	{
3483	Assert(pBDLE->Desc.u64BufAdr == 0);
3484	Assert(pBDLE->Desc.u32BufSize == 0);
3485	}
3486	#endif
3487
3488	uint32_t cbCircBufSize = 0;
3489	uint32_t cbCircBufUsed = 0;
3490
3491	if (pStream->State.pCircBuf)
3492	{
3493	cbCircBufSize = (uint32_t)RTCircBufSize(pStream->State.pCircBuf);
3494	cbCircBufUsed = (uint32_t)RTCircBufUsed(pStream->State.pCircBuf);
3495	}
3496
3497	rc = SSMR3PutU32(pSSM, cbCircBufSize);
3498	AssertRCReturn(rc, rc);
3499
3500	rc = SSMR3PutU32(pSSM, cbCircBufUsed);
3501	AssertRCReturn(rc, rc);
3502
3503	if (cbCircBufUsed)
3504	{
3505	/*
3506	* We now need to get the circular buffer's data without actually modifying
3507	* the internal read / used offsets -- otherwise we would end up with broken audio
3508	* data after saving the state.
3509	*
3510	* So get the current read offset and serialize the buffer data manually based on that.
3511	*/
3512	size_t cbCircBufOffRead = RTCircBufOffsetRead(pStream->State.pCircBuf);
3513
3514	void *pvBuf;
3515	size_t cbBuf;
3516	RTCircBufAcquireReadBlock(pStream->State.pCircBuf, cbCircBufUsed, &pvBuf, &cbBuf);
3517
3518	if (cbBuf)
3519	{
3520	size_t cbToRead = cbCircBufUsed;
3521	size_t cbEnd = 0;
3522
3523	if (cbCircBufUsed > cbCircBufOffRead)
3524	cbEnd = cbCircBufUsed - cbCircBufOffRead;
3525
3526	if (cbEnd) /* Save end of buffer first. */
3527	{
3528	rc = SSMR3PutMem(pSSM, (uint8_t )pvBuf + cbCircBufSize - cbEnd / End of buffer */, cbEnd);
3529	AssertRCReturn(rc, rc);
3530
3531	Assert(cbToRead >= cbEnd);
3532	cbToRead -= cbEnd;
3533	}
3534
3535	if (cbToRead) /* Save remaining stuff at start of buffer (if any). */
3536	{
3537	rc = SSMR3PutMem(pSSM, (uint8_t )pvBuf - cbCircBufUsed / Start of buffer */, cbToRead);
3538	AssertRCReturn(rc, rc);
3539	}
3540	}
3541
3542	RTCircBufReleaseReadBlock(pStream->State.pCircBuf, 0 /* Don't advance read pointer -- see comment above */);
3543	}
3544
3545	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n",
3546	pStream->u8SD,
3547	HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), HDA_STREAM_REG(pThis, CBL, pStream->u8SD), HDA_STREAM_REG(pThis, LVI, pStream->u8SD)));
3548
3549	#ifdef LOG_ENABLED
3550	hdaR3BDLEDumpAll(pThis, pStream->u64BDLBase, pStream->u16LVI + 1);
3551	#endif
3552
3553	return rc;
3554	}
3555
3556	/**
3557	* @callback_method_impl{FNSSMDEVSAVEEXEC}
3558	*/
3559	static DECLCALLBACK(int) hdaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3560	{
3561	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3562
3563	/* Save Codec nodes states. */
3564	hdaCodecSaveState(pThis->pCodec, pSSM);
3565
3566	/* Save MMIO registers. */
3567	SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3568	SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3569
3570	/* Save controller-specifc internals. */
3571	SSMR3PutU64(pSSM, pThis->u64WalClk);
3572	SSMR3PutU8(pSSM, pThis->u8IRQL);
3573
3574	/* Save number of streams. */
3575	SSMR3PutU32(pSSM, HDA_MAX_STREAMS);
3576
3577	/* Save stream states. */
3578	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
3579	{
3580	int rc = hdaR3SaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
3581	AssertRCReturn(rc, rc);
3582	}
3583
3584	return VINF_SUCCESS;
3585	}
3586
3587	/**
3588	* Does required post processing when loading a saved state.
3589	*
3590	* @param pThis Pointer to HDA state.
3591	*/
3592	static int hdaR3LoadExecPost(PHDASTATE pThis)
3593	{
3594	int rc = VINF_SUCCESS;
3595
3596	/*
3597	* Enable all previously active streams.
3598	*/
3599	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
3600	{
3601	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, i);
3602	if (pStream)
3603	{
3604	int rc2;
3605
3606	bool fActive = RT_BOOL(HDA_STREAM_REG(pThis, CTL, i) & HDA_SDCTL_RUN);
3607	if (fActive)
3608	{
3609	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
3610	/* Make sure to also create the async I/O thread before actually enabling the stream. */
3611	rc2 = hdaR3StreamAsyncIOCreate(pStream);
3612	AssertRC(rc2);
3613
3614	/* ... and enabling it. */
3615	hdaR3StreamAsyncIOEnable(pStream, true /* fEnable */);
3616	#endif
3617	/* Resume the stream's period. */
3618	hdaR3StreamPeriodResume(&pStream->State.Period);
3619
3620	/* (Re-)enable the stream. */
3621	rc2 = hdaR3StreamEnable(pStream, true /* fEnable */);
3622	AssertRC(rc2);
3623
3624	/* Add the stream to the device setup. */
3625	rc2 = hdaR3AddStream(pThis, &pStream->State.Cfg);
3626	AssertRC(rc2);
3627
3628	#ifdef HDA_USE_DMA_ACCESS_HANDLER
3629	/* (Re-)install the DMA handler. */
3630	hdaR3StreamRegisterDMAHandlers(pThis, pStream);
3631	#endif
3632	if (hdaR3StreamTransferIsScheduled(pStream))
3633	hdaR3TimerSet(pThis, pStream, hdaR3StreamTransferGetNext(pStream), true /* fForce */);
3634
3635	/* Also keep track of the currently active streams. */
3636	pThis->cStreamsActive++;
3637	}
3638	}
3639	}
3640
3641	LogFlowFuncLeaveRC(rc);
3642	return rc;
3643	}
3644
3645
3646	/**
3647	* Handles loading of all saved state versions older than the current one.
3648	*
3649	* @param pThis Pointer to HDA state.
3650	* @param pSSM Pointer to SSM handle.
3651	* @param uVersion Saved state version to load.
3652	* @param uPass Loading stage to handle.
3653	*/
3654	static int hdaR3LoadExecLegacy(PHDASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3655	{
3656	RT_NOREF(uPass);
3657
3658	int rc = VINF_SUCCESS;
3659
3660	/*
3661	* Load MMIO registers.
3662	*/
3663	uint32_t cRegs;
3664	switch (uVersion)
3665	{
3666	case HDA_SSM_VERSION_1:
3667	/* Starting with r71199, we would save 112 instead of 113
3668	registers due to some code cleanups. This only affected trunk
3669	builds in the 4.1 development period. */
3670	cRegs = 113;
3671	if (SSMR3HandleRevision(pSSM) >= 71199)
3672	{
3673	uint32_t uVer = SSMR3HandleVersion(pSSM);
3674	if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3675	&& VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3676	&& VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3677	cRegs = 112;
3678	}
3679	break;
3680
3681	case HDA_SSM_VERSION_2:
3682	case HDA_SSM_VERSION_3:
3683	cRegs = 112;
3684	AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= 112);
3685	break;
3686
3687	/* Since version 4 we store the register count to stay flexible. */
3688	case HDA_SSM_VERSION_4:
3689	case HDA_SSM_VERSION_5:
3690	case HDA_SSM_VERSION_6:
3691	rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3692	if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3693	LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3694	break;
3695
3696	default:
3697	LogRel(("HDA: Warning: Unsupported / too new saved state version (%RU32)\n", uVersion));
3698	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3699	}
3700
3701	if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3702	{
3703	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3704	SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3705	}
3706	else
3707	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3708
3709	/* Make sure to update the base addresses first before initializing any streams down below. */
3710	pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3711	pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3712	pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE) & DPBASE_ADDR_MASK, HDA_REG(pThis, DPUBASE));
3713
3714	/* Also make sure to update the DMA position bit if this was enabled when saving the state. */
3715	pThis->fDMAPosition = RT_BOOL(HDA_REG(pThis, DPLBASE) & RT_BIT_32(0));
3716
3717	/*
3718	* Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
3719	* every BDLE state, whereas it only needs to be stored
3720	* once for every stream. Most of the BDLE state we can
3721	* get out of the registers anyway, so just ignore those values.
3722	*
3723	* Also, only the current BDLE was saved, regardless whether
3724	* there were more than one (and there are at least two entries,
3725	* according to the spec).
3726	*/
3727	#define HDA_SSM_LOAD_BDLE_STATE_PRE_V5(v, x) \
3728	{ \
3729	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */ \
3730	AssertRCReturn(rc, rc); \
3731	rc = SSMR3GetU64(pSSM, &x.Desc.u64BufAdr); /* u64BdleCviAddr */ \
3732	AssertRCReturn(rc, rc); \
3733	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleMaxCvi */ \
3734	AssertRCReturn(rc, rc); \
3735	rc = SSMR3GetU32(pSSM, &x.State.u32BDLIndex); /* u32BdleCvi */ \
3736	AssertRCReturn(rc, rc); \
3737	rc = SSMR3GetU32(pSSM, &x.Desc.u32BufSize); /* u32BdleCviLen */ \
3738	AssertRCReturn(rc, rc); \
3739	rc = SSMR3GetU32(pSSM, &x.State.u32BufOff); /* u32BdleCviPos */ \
3740	AssertRCReturn(rc, rc); \
3741	bool fIOC; \
3742	rc = SSMR3GetBool(pSSM, &fIOC); /* fBdleCviIoc */ \
3743	AssertRCReturn(rc, rc); \
3744	x.Desc.fFlags = fIOC ? HDA_BDLE_FLAG_IOC : 0; \
3745	rc = SSMR3GetU32(pSSM, &x.State.cbBelowFIFOW); /* cbUnderFifoW */ \
3746	AssertRCReturn(rc, rc); \
3747	rc = SSMR3Skip(pSSM, sizeof(uint8_t) * 256); /* FIFO */ \
3748	AssertRCReturn(rc, rc); \
3749	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */ \
3750	AssertRCReturn(rc, rc); \
3751	}
3752
3753	/*
3754	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3755	*/
3756	switch (uVersion)
3757	{
3758	case HDA_SSM_VERSION_1:
3759	case HDA_SSM_VERSION_2:
3760	case HDA_SSM_VERSION_3:
3761	case HDA_SSM_VERSION_4:
3762	{
3763	/* Only load the internal states.
3764	* The rest will be initialized from the saved registers later. */
3765
3766	/* Note 1: Only the current BDLE for a stream was saved! */
3767	/* Note 2: The stream's saving order is/was fixed, so don't touch! */
3768
3769	/* Output */
3770	PHDASTREAM pStream = &pThis->aStreams[4];
3771	rc = hdaR3StreamInit(pStream, 4 /* Stream descriptor, hardcoded */);
3772	if (RT_FAILURE(rc))
3773	break;
3774	HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
3775	pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
3776
3777	/* Microphone-In */
3778	pStream = &pThis->aStreams[2];
3779	rc = hdaR3StreamInit(pStream, 2 /* Stream descriptor, hardcoded */);
3780	if (RT_FAILURE(rc))
3781	break;
3782	HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
3783	pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
3784
3785	/* Line-In */
3786	pStream = &pThis->aStreams[0];
3787	rc = hdaR3StreamInit(pStream, 0 /* Stream descriptor, hardcoded */);
3788	if (RT_FAILURE(rc))
3789	break;
3790	HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
3791	pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
3792	break;
3793	}
3794
3795	#undef HDA_SSM_LOAD_BDLE_STATE_PRE_V5
3796
3797	default: /* Since v5 we support flexible stream and BDLE counts. */
3798	{
3799	uint32_t cStreams;
3800	rc = SSMR3GetU32(pSSM, &cStreams);
3801	if (RT_FAILURE(rc))
3802	break;
3803
3804	if (cStreams > HDA_MAX_STREAMS)
3805	cStreams = HDA_MAX_STREAMS; /* Sanity. */
3806
3807	/* Load stream states. */
3808	for (uint32_t i = 0; i < cStreams; i++)
3809	{
3810	uint8_t uStreamID;
3811	rc = SSMR3GetU8(pSSM, &uStreamID);
3812	if (RT_FAILURE(rc))
3813	break;
3814
3815	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uStreamID);
3816	HDASTREAM StreamDummy;
3817
3818	if (!pStream)
3819	{
3820	pStream = &StreamDummy;
3821	LogRel2(("HDA: Warning: Stream ID=%RU32 not supported, skipping to load ...\n", uStreamID));
3822	}
3823
3824	rc = hdaR3StreamInit(pStream, uStreamID);
3825	if (RT_FAILURE(rc))
3826	{
3827	LogRel(("HDA: Stream #%RU32: Initialization of stream %RU8 failed, rc=%Rrc\n", i, uStreamID, rc));
3828	break;
3829	}
3830
3831	/*
3832	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3833	*/
3834
3835	if (uVersion == HDA_SSM_VERSION_5)
3836	{
3837	/* Get the current BDLE entry and skip the rest. */
3838	uint16_t cBDLE;
3839
3840	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
3841	AssertRC(rc);
3842	rc = SSMR3GetU16(pSSM, &cBDLE); /* cBDLE */
3843	AssertRC(rc);
3844	rc = SSMR3GetU16(pSSM, &pStream->State.uCurBDLE); /* uCurBDLE */
3845	AssertRC(rc);
3846	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
3847	AssertRC(rc);
3848
3849	uint32_t u32BDLEIndex;
3850	for (uint16_t a = 0; a < cBDLE; a++)
3851	{
3852	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
3853	AssertRC(rc);
3854	rc = SSMR3GetU32(pSSM, &u32BDLEIndex); /* u32BDLIndex */
3855	AssertRC(rc);
3856
3857	/* Does the current BDLE index match the current BDLE to process? */
3858	if (u32BDLEIndex == pStream->State.uCurBDLE)
3859	{
3860	rc = SSMR3GetU32(pSSM, &pStream->State.BDLE.State.cbBelowFIFOW); /* cbBelowFIFOW */
3861	AssertRC(rc);
3862	rc = SSMR3Skip(pSSM, sizeof(uint8_t) * 256); /* FIFO, deprecated */
3863	AssertRC(rc);
3864	rc = SSMR3GetU32(pSSM, &pStream->State.BDLE.State.u32BufOff); /* u32BufOff */
3865	AssertRC(rc);
3866	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
3867	AssertRC(rc);
3868	}
3869	else /* Skip not current BDLEs. */
3870	{
3871	rc = SSMR3Skip(pSSM, sizeof(uint32_t) /* cbBelowFIFOW */
3872	+ sizeof(uint8_t) * 256 /* au8FIFO */
3873	+ sizeof(uint32_t) /* u32BufOff */
3874	+ sizeof(uint32_t)); /* End marker */
3875	AssertRC(rc);
3876	}
3877	}
3878	}
3879	else
3880	{
3881	rc = SSMR3GetStructEx(pSSM, &pStream->State, sizeof(HDASTREAMSTATE),
3882	0 /* fFlags */, g_aSSMStreamStateFields6, NULL);
3883	if (RT_FAILURE(rc))
3884	break;
3885
3886	/* Get HDABDLEDESC. */
3887	uint32_t uMarker;
3888	rc = SSMR3GetU32(pSSM, &uMarker); /* Begin marker. */
3889	AssertRC(rc);
3890	Assert(uMarker == UINT32_C(0x19200102) /* SSMR3STRUCT_BEGIN */);
3891	rc = SSMR3GetU64(pSSM, &pStream->State.BDLE.Desc.u64BufAdr);
3892	AssertRC(rc);
3893	rc = SSMR3GetU32(pSSM, &pStream->State.BDLE.Desc.u32BufSize);
3894	AssertRC(rc);
3895	bool fFlags = false;
3896	rc = SSMR3GetBool(pSSM, &fFlags); /* Saved states < v7 only stored the IOC as boolean flag. */
3897	AssertRC(rc);
3898	pStream->State.BDLE.Desc.fFlags = fFlags ? HDA_BDLE_FLAG_IOC : 0;
3899	rc = SSMR3GetU32(pSSM, &uMarker); /* End marker. */
3900	AssertRC(rc);
3901	Assert(uMarker == UINT32_C(0x19920406) /* SSMR3STRUCT_END */);
3902
3903	rc = SSMR3GetStructEx(pSSM, &pStream->State.BDLE.State, sizeof(HDABDLESTATE),
3904	0 /* fFlags */, g_aSSMBDLEStateFields6, NULL);
3905	if (RT_FAILURE(rc))
3906	break;
3907
3908	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n",
3909	uStreamID,
3910	HDA_STREAM_REG(pThis, LPIB, uStreamID), HDA_STREAM_REG(pThis, CBL, uStreamID), HDA_STREAM_REG(pThis, LVI, uStreamID)));
3911	#ifdef LOG_ENABLED
3912	hdaR3BDLEDumpAll(pThis, pStream->u64BDLBase, pStream->u16LVI + 1);
3913	#endif
3914	}
3915
3916	} /* for cStreams */
3917	break;
3918	} /* default */
3919	}
3920
3921	return rc;
3922	}
3923
3924	/**
3925	* @callback_method_impl{FNSSMDEVLOADEXEC}
3926	*/
3927	static DECLCALLBACK(int) hdaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3928	{
3929	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3930
3931	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3932
3933	LogRel2(("hdaR3LoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
3934
3935	/*
3936	* Load Codec nodes states.
3937	*/
3938	int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
3939	if (RT_FAILURE(rc))
3940	{
3941	LogRel(("HDA: Failed loading codec state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
3942	return rc;
3943	}
3944
3945	if (uVersion < HDA_SSM_VERSION) /* Handle older saved states? */
3946	{
3947	rc = hdaR3LoadExecLegacy(pThis, pSSM, uVersion, uPass);
3948	if (RT_SUCCESS(rc))
3949	rc = hdaR3LoadExecPost(pThis);
3950
3951	return rc;
3952	}
3953
3954	/*
3955	* Load MMIO registers.
3956	*/
3957	uint32_t cRegs;
3958	rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3959	if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3960	LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3961
3962	if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3963	{
3964	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3965	SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3966	}
3967	else
3968	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3969
3970	/* Make sure to update the base addresses first before initializing any streams down below. */
3971	pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3972	pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3973	pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE) & DPBASE_ADDR_MASK, HDA_REG(pThis, DPUBASE));
3974
3975	/* Also make sure to update the DMA position bit if this was enabled when saving the state. */
3976	pThis->fDMAPosition = RT_BOOL(HDA_REG(pThis, DPLBASE) & RT_BIT_32(0));
3977
3978	/*
3979	* Load controller-specifc internals.
3980	* Don't annoy other team mates (forgot this for state v7).
3981	*/
3982	if ( SSMR3HandleRevision(pSSM) >= 116273
3983	\|\| SSMR3HandleVersion(pSSM) >= VBOX_FULL_VERSION_MAKE(5, 2, 0))
3984	{
3985	rc = SSMR3GetU64(pSSM, &pThis->u64WalClk);
3986	AssertRC(rc);
3987
3988	rc = SSMR3GetU8(pSSM, &pThis->u8IRQL);
3989	AssertRC(rc);
3990	}
3991
3992	/*
3993	* Load streams.
3994	*/
3995	uint32_t cStreams;
3996	rc = SSMR3GetU32(pSSM, &cStreams);
3997	AssertRC(rc);
3998
3999	if (cStreams > HDA_MAX_STREAMS)
4000	cStreams = HDA_MAX_STREAMS; /* Sanity. */
4001
4002	Log2Func(("cStreams=%RU32\n", cStreams));
4003
4004	/* Load stream states. */
4005	for (uint32_t i = 0; i < cStreams; i++)
4006	{
4007	uint8_t uStreamID;
4008	rc = SSMR3GetU8(pSSM, &uStreamID);
4009	AssertRC(rc);
4010
4011	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uStreamID);
4012	HDASTREAM StreamDummy;
4013
4014	if (!pStream)
4015	{
4016	pStream = &StreamDummy;
4017	LogRel2(("HDA: Warning: Loading of stream #%RU8 not supported, skipping to load ...\n", uStreamID));
4018	}
4019
4020	rc = hdaR3StreamInit(pStream, uStreamID);
4021	if (RT_FAILURE(rc))
4022	{
4023	LogRel(("HDA: Stream #%RU8: Loading initialization failed, rc=%Rrc\n", uStreamID, rc));
4024	/* Continue. */
4025	}
4026
4027	rc = SSMR3GetStructEx(pSSM, &pStream->State, sizeof(HDASTREAMSTATE),
4028	0 /* fFlags */, g_aSSMStreamStateFields7,
4029	NULL);
4030	AssertRC(rc);
4031
4032	/*
4033	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
4034	*/
4035	rc = SSMR3GetStructEx(pSSM, &pStream->State.BDLE.Desc, sizeof(HDABDLEDESC),
4036	0 /* fFlags */, g_aSSMBDLEDescFields7, NULL);
4037	AssertRC(rc);
4038
4039	rc = SSMR3GetStructEx(pSSM, &pStream->State.BDLE.State, sizeof(HDABDLESTATE),
4040	0 /* fFlags */, g_aSSMBDLEStateFields7, NULL);
4041	AssertRC(rc);
4042
4043	Log2Func(("[SD%RU8] %R[bdle]\n", pStream->u8SD, &pStream->State.BDLE));
4044
4045	/*
4046	* Load period state.
4047	* Don't annoy other team mates (forgot this for state v7).
4048	*/
4049	hdaR3StreamPeriodInit(&pStream->State.Period,
4050	pStream->u8SD, pStream->u16LVI, pStream->u32CBL, &pStream->State.Cfg);
4051
4052	if ( SSMR3HandleRevision(pSSM) >= 116273
4053	\|\| SSMR3HandleVersion(pSSM) >= VBOX_FULL_VERSION_MAKE(5, 2, 0))
4054	{
4055	rc = SSMR3GetStructEx(pSSM, &pStream->State.Period, sizeof(HDASTREAMPERIOD),
4056	0 /* fFlags */, g_aSSMStreamPeriodFields7, NULL);
4057	AssertRC(rc);
4058	}
4059
4060	/*
4061	* Load internal (FIFO) buffer.
4062	*/
4063	uint32_t cbCircBufSize = 0;
4064	rc = SSMR3GetU32(pSSM, &cbCircBufSize); /* cbCircBuf */
4065	AssertRC(rc);
4066
4067	uint32_t cbCircBufUsed = 0;
4068	rc = SSMR3GetU32(pSSM, &cbCircBufUsed); /* cbCircBuf */
4069	AssertRC(rc);
4070
4071	if (cbCircBufSize) /* If 0, skip the buffer. */
4072	{
4073	/* Paranoia. */
4074	AssertReleaseMsg(cbCircBufSize <= _1M,
4075	("HDA: Saved state contains bogus DMA buffer size (%RU32) for stream #%RU8",
4076	cbCircBufSize, uStreamID));
4077	AssertReleaseMsg(cbCircBufUsed <= cbCircBufSize,
4078	("HDA: Saved state contains invalid DMA buffer usage (%RU32/%RU32) for stream #%RU8",
4079	cbCircBufUsed, cbCircBufSize, uStreamID));
4080	AssertPtr(pStream->State.pCircBuf);
4081
4082	/* Do we need to cre-create the circular buffer do fit the data size? */
4083	if (cbCircBufSize != (uint32_t)RTCircBufSize(pStream->State.pCircBuf))
4084	{
4085	RTCircBufDestroy(pStream->State.pCircBuf);
4086	pStream->State.pCircBuf = NULL;
4087
4088	rc = RTCircBufCreate(&pStream->State.pCircBuf, cbCircBufSize);
4089	AssertRC(rc);
4090	}
4091
4092	if ( RT_SUCCESS(rc)
4093	&& cbCircBufUsed)
4094	{
4095	void *pvBuf;
4096	size_t cbBuf;
4097
4098	RTCircBufAcquireWriteBlock(pStream->State.pCircBuf, cbCircBufUsed, &pvBuf, &cbBuf);
4099
4100	if (cbBuf)
4101	{
4102	rc = SSMR3GetMem(pSSM, pvBuf, cbBuf);
4103	AssertRC(rc);
4104	}
4105
4106	RTCircBufReleaseWriteBlock(pStream->State.pCircBuf, cbBuf);
4107
4108	Assert(cbBuf == cbCircBufUsed);
4109	}
4110	}
4111
4112	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n",
4113	uStreamID,
4114	HDA_STREAM_REG(pThis, LPIB, uStreamID), HDA_STREAM_REG(pThis, CBL, uStreamID), HDA_STREAM_REG(pThis, LVI, uStreamID)));
4115	#ifdef LOG_ENABLED
4116	hdaR3BDLEDumpAll(pThis, pStream->u64BDLBase, pStream->u16LVI + 1);
4117	#endif
4118	/** @todo (Re-)initialize active periods? */
4119
4120	} /* for cStreams */
4121
4122	rc = hdaR3LoadExecPost(pThis);
4123	AssertRC(rc);
4124
4125	LogFlowFuncLeaveRC(rc);
4126	return rc;
4127	}
4128
4129	/* IPRT format type handlers. */
4130
4131	/**
4132	* @callback_method_impl{FNRTSTRFORMATTYPE}
4133	*/
4134	static DECLCALLBACK(size_t) hdaR3StrFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4135	const char pszType, void const pvValue,
4136	int cchWidth, int cchPrecision, unsigned fFlags,
4137	void *pvUser)
4138	{
4139	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4140	PHDABDLE pBDLE = (PHDABDLE)pvValue;
4141	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4142	"BDLE(idx:%RU32, off:%RU32, fifow:%RU32, IOC:%RTbool, DMA[%RU32 bytes @ 0x%x])",
4143	pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW,
4144	pBDLE->Desc.fFlags & HDA_BDLE_FLAG_IOC, pBDLE->Desc.u32BufSize, pBDLE->Desc.u64BufAdr);
4145	}
4146
4147	/**
4148	* @callback_method_impl{FNRTSTRFORMATTYPE}
4149	*/
4150	static DECLCALLBACK(size_t) hdaR3StrFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4151	const char pszType, void const pvValue,
4152	int cchWidth, int cchPrecision, unsigned fFlags,
4153	void *pvUser)
4154	{
4155	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4156	uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
4157	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4158	"SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
4159	uSDCTL,
4160	uSDCTL & HDA_SDCTL_DIR ? "OUT" : "IN",
4161	RT_BOOL(uSDCTL & HDA_SDCTL_TP),
4162	(uSDCTL & HDA_SDCTL_STRIPE_MASK) >> HDA_SDCTL_STRIPE_SHIFT,
4163	RT_BOOL(uSDCTL & HDA_SDCTL_DEIE),
4164	RT_BOOL(uSDCTL & HDA_SDCTL_FEIE),
4165	RT_BOOL(uSDCTL & HDA_SDCTL_IOCE),
4166	RT_BOOL(uSDCTL & HDA_SDCTL_RUN),
4167	RT_BOOL(uSDCTL & HDA_SDCTL_SRST));
4168	}
4169
4170	/**
4171	* @callback_method_impl{FNRTSTRFORMATTYPE}
4172	*/
4173	static DECLCALLBACK(size_t) hdaR3StrFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4174	const char pszType, void const pvValue,
4175	int cchWidth, int cchPrecision, unsigned fFlags,
4176	void *pvUser)
4177	{
4178	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4179	uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
4180	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, uSDFIFOS ? uSDFIFOS + 1 : 0);
4181	}
4182
4183	/**
4184	* @callback_method_impl{FNRTSTRFORMATTYPE}
4185	*/
4186	static DECLCALLBACK(size_t) hdaR3StrFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4187	const char pszType, void const pvValue,
4188	int cchWidth, int cchPrecision, unsigned fFlags,
4189	void *pvUser)
4190	{
4191	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4192	uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
4193	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
4194	}
4195
4196	/**
4197	* @callback_method_impl{FNRTSTRFORMATTYPE}
4198	*/
4199	static DECLCALLBACK(size_t) hdaR3StrFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4200	const char pszType, void const pvValue,
4201	int cchWidth, int cchPrecision, unsigned fFlags,
4202	void *pvUser)
4203	{
4204	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4205	uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
4206	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4207	"SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
4208	uSdSts,
4209	RT_BOOL(uSdSts & HDA_SDSTS_FIFORDY),
4210	RT_BOOL(uSdSts & HDA_SDSTS_DESE),
4211	RT_BOOL(uSdSts & HDA_SDSTS_FIFOE),
4212	RT_BOOL(uSdSts & HDA_SDSTS_BCIS));
4213	}
4214
4215	/* Debug info dumpers */
4216
4217	static int hdaR3DbgLookupRegByName(const char *pszArgs)
4218	{
4219	int iReg = 0;
4220	for (; iReg < HDA_NUM_REGS; ++iReg)
4221	if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
4222	return iReg;
4223	return -1;
4224	}
4225
4226
4227	static void hdaR3DbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
4228	{
4229	Assert( pThis
4230	&& iHdaIndex >= 0
4231	&& iHdaIndex < HDA_NUM_REGS);
4232	pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
4233	}
4234
4235	/**
4236	* @callback_method_impl{FNDBGFHANDLERDEV}
4237	*/
4238	static DECLCALLBACK(void) hdaR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4239	{
4240	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4241	int iHdaRegisterIndex = hdaR3DbgLookupRegByName(pszArgs);
4242	if (iHdaRegisterIndex != -1)
4243	hdaR3DbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
4244	else
4245	{
4246	for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NUM_REGS; ++iHdaRegisterIndex)
4247	hdaR3DbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
4248	}
4249	}
4250
4251	static void hdaR3DbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
4252	{
4253	Assert( pThis
4254	&& iIdx >= 0
4255	&& iIdx < HDA_MAX_STREAMS);
4256
4257	const PHDASTREAM pStream = &pThis->aStreams[iIdx];
4258
4259	pHlp->pfnPrintf(pHlp, "Stream #%d:\n", iIdx);
4260	pHlp->pfnPrintf(pHlp, "\tSD%dCTL : %R[sdctl]\n", iIdx, HDA_STREAM_REG(pThis, CTL, iIdx));
4261	pHlp->pfnPrintf(pHlp, "\tSD%dCTS : %R[sdsts]\n", iIdx, HDA_STREAM_REG(pThis, STS, iIdx));
4262	pHlp->pfnPrintf(pHlp, "\tSD%dFIFOS: %R[sdfifos]\n", iIdx, HDA_STREAM_REG(pThis, FIFOS, iIdx));
4263	pHlp->pfnPrintf(pHlp, "\tSD%dFIFOW: %R[sdfifow]\n", iIdx, HDA_STREAM_REG(pThis, FIFOW, iIdx));
4264	pHlp->pfnPrintf(pHlp, "\tBDLE : %R[bdle]\n", &pStream->State.BDLE);
4265	}
4266
4267	static void hdaR3DbgPrintBDLE(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
4268	{
4269	Assert( pThis
4270	&& iIdx >= 0
4271	&& iIdx < HDA_MAX_STREAMS);
4272
4273	const PHDASTREAM pStream = &pThis->aStreams[iIdx];
4274	const PHDABDLE pBDLE = &pStream->State.BDLE;
4275
4276	pHlp->pfnPrintf(pHlp, "Stream #%d BDLE:\n", iIdx);
4277
4278	uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, iIdx),
4279	HDA_STREAM_REG(pThis, BDPU, iIdx));
4280	uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, iIdx);
4281	uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, iIdx);
4282
4283	if (!u64BaseDMA)
4284	return;
4285
4286	pHlp->pfnPrintf(pHlp, "\tCurrent: %R[bdle]\n\n", pBDLE);
4287
4288	pHlp->pfnPrintf(pHlp, "\tMemory:\n");
4289
4290	uint32_t cbBDLE = 0;
4291	for (uint16_t i = 0; i < u16LVI + 1; i++)
4292	{
4293	HDABDLEDESC bd;
4294	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i * sizeof(HDABDLEDESC), &bd, sizeof(bd));
4295
4296	pHlp->pfnPrintf(pHlp, "\t\t%s #%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
4297	pBDLE->State.u32BDLIndex == i ? "*" : " ", i, bd.u64BufAdr, bd.u32BufSize, bd.fFlags & HDA_BDLE_FLAG_IOC);
4298
4299	cbBDLE += bd.u32BufSize;
4300	}
4301
4302	pHlp->pfnPrintf(pHlp, "Total: %RU32 bytes\n", cbBDLE);
4303
4304	if (cbBDLE != u32CBL)
4305	pHlp->pfnPrintf(pHlp, "Warning: %RU32 bytes does not match CBL (%RU32)!\n", cbBDLE, u32CBL);
4306
4307	pHlp->pfnPrintf(pHlp, "DMA counters (base @ 0x%llx):\n", u64BaseDMA);
4308	if (!u64BaseDMA) /* No DMA base given? Bail out. */
4309	{
4310	pHlp->pfnPrintf(pHlp, "\tNo counters found\n");
4311	return;
4312	}
4313
4314	for (int i = 0; i < u16LVI + 1; i++)
4315	{
4316	uint32_t uDMACnt;
4317	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
4318	&uDMACnt, sizeof(uDMACnt));
4319
4320	pHlp->pfnPrintf(pHlp, "\t#%03d DMA @ 0x%x\n", i , uDMACnt);
4321	}
4322	}
4323
4324	static int hdaR3DbgLookupStrmIdx(PHDASTATE pThis, const char *pszArgs)
4325	{
4326	RT_NOREF(pThis, pszArgs);
4327	/** @todo Add args parsing. */
4328	return -1;
4329	}
4330
4331	/**
4332	* @callback_method_impl{FNDBGFHANDLERDEV}
4333	*/
4334	static DECLCALLBACK(void) hdaR3DbgInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4335	{
4336	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4337	int iHdaStreamdex = hdaR3DbgLookupStrmIdx(pThis, pszArgs);
4338	if (iHdaStreamdex != -1)
4339	hdaR3DbgPrintStream(pThis, pHlp, iHdaStreamdex);
4340	else
4341	for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
4342	hdaR3DbgPrintStream(pThis, pHlp, iHdaStreamdex);
4343	}
4344
4345	/**
4346	* @callback_method_impl{FNDBGFHANDLERDEV}
4347	*/
4348	static DECLCALLBACK(void) hdaR3DbgInfoBDLE(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4349	{
4350	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4351	int iHdaStreamdex = hdaR3DbgLookupStrmIdx(pThis, pszArgs);
4352	if (iHdaStreamdex != -1)
4353	hdaR3DbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
4354	else
4355	for (iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
4356	hdaR3DbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
4357	}
4358
4359	/**
4360	* @callback_method_impl{FNDBGFHANDLERDEV}
4361	*/
4362	static DECLCALLBACK(void) hdaR3DbgInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4363	{
4364	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4365
4366	if (pThis->pCodec->pfnDbgListNodes)
4367	pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
4368	else
4369	pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
4370	}
4371
4372	/**
4373	* @callback_method_impl{FNDBGFHANDLERDEV}
4374	*/
4375	static DECLCALLBACK(void) hdaR3DbgInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4376	{
4377	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4378
4379	if (pThis->pCodec->pfnDbgSelector)
4380	pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
4381	else
4382	pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
4383	}
4384
4385	/**
4386	* @callback_method_impl{FNDBGFHANDLERDEV}
4387	*/
4388	static DECLCALLBACK(void) hdaR3DbgInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4389	{
4390	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4391
4392	if (pThis->pMixer)
4393	AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
4394	else
4395	pHlp->pfnPrintf(pHlp, "Mixer not available\n");
4396	}
4397
4398
4399	/* PDMIBASE */
4400
4401	/**
4402	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
4403	*/
4404	static DECLCALLBACK(void ) hdaR3QueryInterface(struct PDMIBASE pInterface, const char *pszIID)
4405	{
4406	PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
4407	Assert(&pThis->IBase == pInterface);
4408
4409	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
4410	return NULL;
4411	}
4412
4413
4414	/* PDMDEVREG */
4415
4416	/**
4417	* Attach command, internal version.
4418	*
4419	* This is called to let the device attach to a driver for a specified LUN
4420	* during runtime. This is not called during VM construction, the device
4421	* constructor has to attach to all the available drivers.
4422	*
4423	* @returns VBox status code.
4424	* @param pThis HDA state.
4425	* @param uLUN The logical unit which is being detached.
4426	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4427	* @param ppDrv Attached driver instance on success. Optional.
4428	*/
4429	static int hdaR3AttachInternal(PHDASTATE pThis, unsigned uLUN, uint32_t fFlags, PHDADRIVER *ppDrv)
4430	{
4431	RT_NOREF(fFlags);
4432
4433	/*
4434	* Attach driver.
4435	*/
4436	char *pszDesc;
4437	if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
4438	AssertLogRelFailedReturn(VERR_NO_MEMORY);
4439
4440	PPDMIBASE pDrvBase;
4441	int rc = PDMDevHlpDriverAttach(pThis->pDevInsR3, uLUN,
4442	&pThis->IBase, &pDrvBase, pszDesc);
4443	if (RT_SUCCESS(rc))
4444	{
4445	PHDADRIVER pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
4446	if (pDrv)
4447	{
4448	pDrv->pDrvBase = pDrvBase;
4449	pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
4450	AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
4451	pDrv->pHDAState = pThis;
4452	pDrv->uLUN = uLUN;
4453
4454	/*
4455	* For now we always set the driver at LUN 0 as our primary
4456	* host backend. This might change in the future.
4457	*/
4458	if (pDrv->uLUN == 0)
4459	pDrv->fFlags \|= PDMAUDIODRVFLAGS_PRIMARY;
4460
4461	LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->fFlags));
4462
4463	/* Attach to driver list if not attached yet. */
4464	if (!pDrv->fAttached)
4465	{
4466	RTListAppend(&pThis->lstDrv, &pDrv->Node);
4467	pDrv->fAttached = true;
4468	}
4469
4470	if (ppDrv)
4471	*ppDrv = pDrv;
4472	}
4473	else
4474	rc = VERR_NO_MEMORY;
4475	}
4476	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4477	LogFunc(("No attached driver for LUN #%u\n", uLUN));
4478
4479	if (RT_FAILURE(rc))
4480	{
4481	/* Only free this string on failure;
4482	* must remain valid for the live of the driver instance. */
4483	RTStrFree(pszDesc);
4484	}
4485
4486	LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
4487	return rc;
4488	}
4489
4490	/**
4491	* Detach command, internal version.
4492	*
4493	* This is called to let the device detach from a driver for a specified LUN
4494	* during runtime.
4495	*
4496	* @returns VBox status code.
4497	* @param pThis HDA state.
4498	* @param pDrv Driver to detach device from.
4499	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4500	*/
4501	static int hdaR3DetachInternal(PHDASTATE pThis, PHDADRIVER pDrv, uint32_t fFlags)
4502	{
4503	RT_NOREF(fFlags);
4504
4505	AudioMixerSinkRemoveStream(pThis->SinkFront.pMixSink, pDrv->Front.pMixStrm);
4506	AudioMixerStreamDestroy(pDrv->Front.pMixStrm);
4507	pDrv->Front.pMixStrm = NULL;
4508
4509	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
4510	AudioMixerSinkRemoveStream(pThis->SinkCenterLFE.pMixSink, pDrv->CenterLFE.pMixStrm);
4511	AudioMixerStreamDestroy(pDrv->CenterLFE.pMixStrm);
4512	pDrv->CenterLFE.pMixStrm = NULL;
4513
4514	AudioMixerSinkRemoveStream(pThis->SinkRear.pMixSink, pDrv->Rear.pMixStrm);
4515	AudioMixerStreamDestroy(pDrv->Rear.pMixStrm);
4516	pDrv->Rear.pMixStrm = NULL;
4517	#endif
4518
4519	AudioMixerSinkRemoveStream(pThis->SinkLineIn.pMixSink, pDrv->LineIn.pMixStrm);
4520	AudioMixerStreamDestroy(pDrv->LineIn.pMixStrm);
4521	pDrv->LineIn.pMixStrm = NULL;
4522
4523	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
4524	AudioMixerSinkRemoveStream(pThis->SinkMicIn.pMixSink, pDrv->MicIn.pMixStrm);
4525	AudioMixerStreamDestroy(pDrv->MicIn.pMixStrm);
4526	pDrv->MicIn.pMixStrm = NULL;
4527	#endif
4528
4529	RTListNodeRemove(&pDrv->Node);
4530
4531	LogFunc(("uLUN=%u, fFlags=0x%x\n", pDrv->uLUN, fFlags));
4532	return VINF_SUCCESS;
4533	}
4534
4535	/**
4536	* @interface_method_impl{PDMDEVREG,pfnAttach}
4537	*/
4538	static DECLCALLBACK(int) hdaR3Attach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4539	{
4540	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4541
4542	DEVHDA_LOCK_RETURN(pThis, VERR_IGNORED);
4543
4544	LogFunc(("uLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
4545
4546	PHDADRIVER pDrv;
4547	int rc2 = hdaR3AttachInternal(pThis, uLUN, fFlags, &pDrv);
4548	if (RT_SUCCESS(rc2))
4549	{
4550	PHDASTREAM pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkFront);
4551	if (DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
4552	{
4553	rc2 = hdaR3UpdateStream(pThis, &pStream->State.Cfg);
4554	AssertRC(rc2);
4555	}
4556	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
4557	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkCenterLFE);
4558	if (DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
4559	{
4560	rc2 = hdaR3UpdateStream(pThis, &pStream->State.Cfg);
4561	AssertRC(rc2);
4562	}
4563
4564	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkRear);
4565	if (DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
4566	{
4567	rc2 = hdaR3UpdateStream(pThis, &pStream->State.Cfg);
4568	AssertRC(rc2);
4569	}
4570	#endif
4571	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkLineIn);
4572	if (DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
4573	{
4574	rc2 = hdaR3UpdateStream(pThis, &pStream->State.Cfg);
4575	AssertRC(rc2);
4576	}
4577
4578	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
4579	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkMicIn);
4580	if (DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
4581	{
4582	rc2 = hdaR3UpdateStream(pThis, &pStream->State.Cfg);
4583	AssertRC(rc2);
4584	}
4585	#endif
4586	}
4587
4588	DEVHDA_UNLOCK(pThis);
4589
4590	return VINF_SUCCESS;
4591	}
4592
4593	/**
4594	* @interface_method_impl{PDMDEVREG,pfnDetach}
4595	*/
4596	static DECLCALLBACK(void) hdaR3Detach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4597	{
4598	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4599
4600	DEVHDA_LOCK(pThis);
4601
4602	LogFunc(("uLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
4603
4604	PHDADRIVER pDrv, pDrvNext;
4605	RTListForEachSafe(&pThis->lstDrv, pDrv, pDrvNext, HDADRIVER, Node)
4606	{
4607	if (pDrv->uLUN == uLUN)
4608	{
4609	int rc2 = hdaR3DetachInternal(pThis, pDrv, fFlags);
4610	if (RT_SUCCESS(rc2))
4611	{
4612	RTMemFree(pDrv);
4613	pDrv = NULL;
4614	}
4615
4616	break;
4617	}
4618	}
4619
4620	DEVHDA_UNLOCK(pThis);
4621	}
4622
4623	/**
4624	* Powers off the device.
4625	*
4626	* @param pDevIns Device instance to power off.
4627	*/
4628	static DECLCALLBACK(void) hdaR3PowerOff(PPDMDEVINS pDevIns)
4629	{
4630	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4631
4632	DEVHDA_LOCK_RETURN_VOID(pThis);
4633
4634	LogRel2(("HDA: Powering off ...\n"));
4635
4636	/* Ditto goes for the codec, which in turn uses the mixer. */
4637	hdaCodecPowerOff(pThis->pCodec);
4638
4639	/*
4640	* Note: Destroy the mixer while powering off and not in hdaR3Destruct,
4641	* giving the mixer the chance to release any references held to
4642	* PDM audio streams it maintains.
4643	*/
4644	if (pThis->pMixer)
4645	{
4646	AudioMixerDestroy(pThis->pMixer);
4647	pThis->pMixer = NULL;
4648	}
4649
4650	DEVHDA_UNLOCK(pThis);
4651	}
4652
4653
4654	/**
4655	* Re-attaches (replaces) a driver with a new driver.
4656	*
4657	* This is only used by to attach the Null driver when it failed to attach the
4658	* one that was configured.
4659	*
4660	* @returns VBox status code.
4661	* @param pThis Device instance to re-attach driver to.
4662	* @param pDrv Driver instance used for attaching to.
4663	* If NULL is specified, a new driver will be created and appended
4664	* to the driver list.
4665	* @param uLUN The logical unit which is being re-detached.
4666	* @param pszDriver New driver name to attach.
4667	*/
4668	static int hdaR3ReattachInternal(PHDASTATE pThis, PHDADRIVER pDrv, uint8_t uLUN, const char *pszDriver)
4669	{
4670	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
4671	AssertPtrReturn(pszDriver, VERR_INVALID_POINTER);
4672
4673	int rc;
4674
4675	if (pDrv)
4676	{
4677	rc = hdaR3DetachInternal(pThis, pDrv, 0 /* fFlags */);
4678	if (RT_SUCCESS(rc))
4679	rc = PDMDevHlpDriverDetach(pThis->pDevInsR3, PDMIBASE_2_PDMDRV(pDrv->pDrvBase), 0 /* fFlags */);
4680
4681	if (RT_FAILURE(rc))
4682	return rc;
4683
4684	pDrv = NULL;
4685	}
4686
4687	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
4688	PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
4689	PCFGMNODE pDev0 = CFGMR3GetChild(pRoot, "Devices/hda/0/");
4690
4691	/* Remove LUN branch. */
4692	CFGMR3RemoveNode(CFGMR3GetChildF(pDev0, "LUN#%u/", uLUN));
4693
4694	#define RC_CHECK() if (RT_FAILURE(rc)) { AssertReleaseRC(rc); break; }
4695
4696	do
4697	{
4698	PCFGMNODE pLunL0;
4699	rc = CFGMR3InsertNodeF(pDev0, &pLunL0, "LUN#%u/", uLUN); RC_CHECK();
4700	rc = CFGMR3InsertString(pLunL0, "Driver", "AUDIO"); RC_CHECK();
4701	rc = CFGMR3InsertNode(pLunL0, "Config/", NULL); RC_CHECK();
4702
4703	PCFGMNODE pLunL1, pLunL2;
4704	rc = CFGMR3InsertNode (pLunL0, "AttachedDriver/", &pLunL1); RC_CHECK();
4705	rc = CFGMR3InsertNode (pLunL1, "Config/", &pLunL2); RC_CHECK();
4706	rc = CFGMR3InsertString(pLunL1, "Driver", pszDriver); RC_CHECK();
4707
4708	rc = CFGMR3InsertString(pLunL2, "AudioDriver", pszDriver); RC_CHECK();
4709
4710	} while (0);
4711
4712	if (RT_SUCCESS(rc))
4713	rc = hdaR3AttachInternal(pThis, uLUN, 0 /* fFlags /, NULL / ppDrv */);
4714
4715	LogFunc(("pThis=%p, uLUN=%u, pszDriver=%s, rc=%Rrc\n", pThis, uLUN, pszDriver, rc));
4716
4717	#undef RC_CHECK
4718
4719	return rc;
4720	}
4721
4722
4723	/**
4724	* @interface_method_impl{PDMDEVREG,pfnReset}
4725	*/
4726	static DECLCALLBACK(void) hdaR3Reset(PPDMDEVINS pDevIns)
4727	{
4728	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4729
4730	LogFlowFuncEnter();
4731
4732	DEVHDA_LOCK_RETURN_VOID(pThis);
4733
4734	/*
4735	* 18.2.6,7 defines that values of this registers might be cleared on power on/reset
4736	* hdaR3Reset shouldn't affects these registers.
4737	*/
4738	HDA_REG(pThis, WAKEEN) = 0x0;
4739
4740	hdaR3GCTLReset(pThis);
4741
4742	/* Indicate that HDA is not in reset. The firmware is supposed to (un)reset HDA,
4743	* but we can take a shortcut.
4744	*/
4745	HDA_REG(pThis, GCTL) = HDA_GCTL_CRST;
4746
4747	DEVHDA_UNLOCK(pThis);
4748	}
4749
4750
4751	/**
4752	* @interface_method_impl{PDMDEVREG,pfnRelocate}
4753	*/
4754	static DECLCALLBACK(void) hdaR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
4755	{
4756	NOREF(offDelta);
4757	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4758	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4759	}
4760
4761
4762	/**
4763	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4764	*/
4765	static DECLCALLBACK(int) hdaR3Destruct(PPDMDEVINS pDevIns)
4766	{
4767	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns); /* this shall come first */
4768	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4769	DEVHDA_LOCK(pThis); /** @todo r=bird: this will fail on early constructor failure. */
4770
4771	PHDADRIVER pDrv;
4772	while (!RTListIsEmpty(&pThis->lstDrv))
4773	{
4774	pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
4775
4776	RTListNodeRemove(&pDrv->Node);
4777	RTMemFree(pDrv);
4778	}
4779
4780	if (pThis->pCodec)
4781	{
4782	hdaCodecDestruct(pThis->pCodec);
4783
4784	RTMemFree(pThis->pCodec);
4785	pThis->pCodec = NULL;
4786	}
4787
4788	RTMemFree(pThis->pu32CorbBuf);
4789	pThis->pu32CorbBuf = NULL;
4790
4791	RTMemFree(pThis->pu64RirbBuf);
4792	pThis->pu64RirbBuf = NULL;
4793
4794	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
4795	hdaR3StreamDestroy(&pThis->aStreams[i]);
4796
4797	DEVHDA_UNLOCK(pThis);
4798	return VINF_SUCCESS;
4799	}
4800
4801
4802	/**
4803	* @interface_method_impl{PDMDEVREG,pfnConstruct}
4804	*/
4805	static DECLCALLBACK(int) hdaR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4806	{
4807	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); /* this shall come first */
4808	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4809	Assert(iInstance == 0); RT_NOREF(iInstance);
4810
4811	/*
4812	* Initialize the state sufficently to make the destructor work.
4813	*/
4814	pThis->uAlignmentCheckMagic = HDASTATE_ALIGNMENT_CHECK_MAGIC;
4815	RTListInit(&pThis->lstDrv);
4816	/** @todo r=bird: There are probably other things which should be
4817	* initialized here before we start failing. */
4818
4819	/*
4820	* Validations.
4821	*/
4822	if (!CFGMR3AreValuesValid(pCfg, "RZEnabled\0"
4823	"TimerHz\0"
4824	"PosAdjustEnabled\0"
4825	"PosAdjustFrames\0"
4826	"DebugEnabled\0"
4827	"DebugPathOut\0"))
4828	{
4829	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4830	N_ ("Invalid configuration for the Intel HDA device"));
4831	}
4832
4833	int rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pThis->fRZEnabled, true);
4834	if (RT_FAILURE(rc))
4835	return PDMDEV_SET_ERROR(pDevIns, rc,
4836	N_("HDA configuration error: failed to read RCEnabled as boolean"));
4837
4838
4839	rc = CFGMR3QueryU16Def(pCfg, "TimerHz", &pThis->u16TimerHz, HDA_TIMER_HZ_DEFAULT /* Default value, if not set. */);
4840	if (RT_FAILURE(rc))
4841	return PDMDEV_SET_ERROR(pDevIns, rc,
4842	N_("HDA configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
4843
4844	if (pThis->u16TimerHz != HDA_TIMER_HZ_DEFAULT)
4845	LogRel(("HDA: Using custom device timer rate (%RU16Hz)\n", pThis->u16TimerHz));
4846
4847	rc = CFGMR3QueryBoolDef(pCfg, "PosAdjustEnabled", &pThis->fPosAdjustEnabled, true);
4848	if (RT_FAILURE(rc))
4849	return PDMDEV_SET_ERROR(pDevIns, rc,
4850	N_("HDA configuration error: failed to read position adjustment enabled as boolean"));
4851
4852	if (!pThis->fPosAdjustEnabled)
4853	LogRel(("HDA: Position adjustment is disabled\n"));
4854
4855	rc = CFGMR3QueryU16Def(pCfg, "PosAdjustFrames", &pThis->cPosAdjustFrames, HDA_POS_ADJUST_DEFAULT);
4856	if (RT_FAILURE(rc))
4857	return PDMDEV_SET_ERROR(pDevIns, rc,
4858	N_("HDA configuration error: failed to read position adjustment frames as unsigned integer"));
4859
4860	if (pThis->cPosAdjustFrames)
4861	LogRel(("HDA: Using custom position adjustment (%RU16 audio frames)\n", pThis->cPosAdjustFrames));
4862
4863	rc = CFGMR3QueryBoolDef(pCfg, "DebugEnabled", &pThis->Dbg.fEnabled, false);
4864	if (RT_FAILURE(rc))
4865	return PDMDEV_SET_ERROR(pDevIns, rc,
4866	N_("HDA configuration error: failed to read debugging enabled flag as boolean"));
4867
4868	rc = CFGMR3QueryStringDef(pCfg, "DebugPathOut", pThis->Dbg.szOutPath, sizeof(pThis->Dbg.szOutPath),
4869	VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH);
4870	if (RT_FAILURE(rc))
4871	return PDMDEV_SET_ERROR(pDevIns, rc,
4872	N_("HDA configuration error: failed to read debugging output path flag as string"));
4873
4874	if (!strlen(pThis->Dbg.szOutPath))
4875	RTStrPrintf(pThis->Dbg.szOutPath, sizeof(pThis->Dbg.szOutPath), VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH);
4876
4877	if (pThis->Dbg.fEnabled)
4878	LogRel2(("HDA: Debug output will be saved to '%s'\n", pThis->Dbg.szOutPath));
4879
4880	/*
4881	* Use an own critical section for the device instead of the default
4882	* one provided by PDM. This allows fine-grained locking in combination
4883	* with TM when timer-specific stuff is being called in e.g. the MMIO handlers.
4884	*/
4885	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "HDA");
4886	AssertRCReturn(rc, rc);
4887
4888	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4889	AssertRCReturn(rc, rc);
4890
4891	/*
4892	* Initialize data (most of it anyway).
4893	*/
4894	pThis->pDevInsR3 = pDevIns;
4895	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
4896	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4897	/* IBase */
4898	pThis->IBase.pfnQueryInterface = hdaR3QueryInterface;
4899
4900	/* PCI Device */
4901	PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
4902	PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
4903
4904	PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
4905	PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
4906	PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
4907	PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
4908	PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
4909	PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
4910	PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
4911	PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
4912	false /* fIoSpace /, false / fPrefetchable /, true / f64Bit */, 0x00000000);
4913	PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
4914	PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
4915
4916	#if defined(HDA_AS_PCI_EXPRESS)
4917	PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
4918	#elif defined(VBOX_WITH_MSI_DEVICES)
4919	PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
4920	#else
4921	PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
4922	#endif
4923
4924	/// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
4925	/// of these values needs to be properly documented!
4926	/* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
4927	PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
4928
4929	/* Power Management */
4930	PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
4931	PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
4932	PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI \| 0x02 /* version, PM1.1 */ );
4933
4934	#ifdef HDA_AS_PCI_EXPRESS
4935	/* PCI Express */
4936	PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
4937	PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
4938	/* Device flags */
4939	PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
4940	/* version */ 0x1 \|
4941	/* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) \|
4942	/* MSI */ (100) << 9 );
4943	/* Device capabilities */
4944	PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
4945	/* Device control */
4946	PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
4947	/* Device status */
4948	PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
4949	/* Link caps */
4950	PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
4951	/* Link control */
4952	PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
4953	/* Link status */
4954	PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
4955	/* Slot capabilities */
4956	PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
4957	/* Slot control */
4958	PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
4959	/* Slot status */
4960	PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
4961	/* Root control */
4962	PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
4963	/* Root capabilities */
4964	PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
4965	/* Root status */
4966	PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
4967	/* Device capabilities 2 */
4968	PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
4969	/* Device control 2 */
4970	PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
4971	/* Link control 2 */
4972	PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
4973	/* Slot control 2 */
4974	PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
4975	#endif
4976
4977	/*
4978	* Register the PCI device.
4979	*/
4980	rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
4981	if (RT_FAILURE(rc))
4982	return rc;
4983
4984	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaR3PciIoRegionMap);
4985	if (RT_FAILURE(rc))
4986	return rc;
4987
4988	#ifdef VBOX_WITH_MSI_DEVICES
4989	PDMMSIREG MsiReg;
4990	RT_ZERO(MsiReg);
4991	MsiReg.cMsiVectors = 1;
4992	MsiReg.iMsiCapOffset = 0x60;
4993	MsiReg.iMsiNextOffset = 0x50;
4994	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
4995	if (RT_FAILURE(rc))
4996	{
4997	/* That's OK, we can work without MSI */
4998	PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
4999	}
5000	#endif
5001
5002	rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaR3SaveExec, hdaR3LoadExec);
5003	if (RT_FAILURE(rc))
5004	return rc;
5005
5006	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
5007	LogRel(("HDA: Asynchronous I/O enabled\n"));
5008	#endif
5009
5010	uint8_t uLUN;
5011	for (uLUN = 0; uLUN < UINT8_MAX; ++uLUN)
5012	{
5013	LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
5014	rc = hdaR3AttachInternal(pThis, uLUN, 0 /* fFlags /, NULL / ppDrv */);
5015	if (RT_FAILURE(rc))
5016	{
5017	if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5018	rc = VINF_SUCCESS;
5019	else if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
5020	{
5021	hdaR3ReattachInternal(pThis, NULL /* pDrv */, uLUN, "NullAudio");
5022	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
5023	N_("Host audio backend initialization has failed. Selecting the NULL audio backend "
5024	"with the consequence that no sound is audible"));
5025	/* Attaching to the NULL audio backend will never fail. */
5026	rc = VINF_SUCCESS;
5027	}
5028	break;
5029	}
5030	}
5031
5032	LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
5033
5034	if (RT_SUCCESS(rc))
5035	{
5036	rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
5037	if (RT_SUCCESS(rc))
5038	{
5039	/*
5040	* Add mixer output sinks.
5041	*/
5042	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
5043	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Front",
5044	AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
5045	AssertRC(rc);
5046	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Center / Subwoofer",
5047	AUDMIXSINKDIR_OUTPUT, &pThis->SinkCenterLFE.pMixSink);
5048	AssertRC(rc);
5049	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Rear",
5050	AUDMIXSINKDIR_OUTPUT, &pThis->SinkRear.pMixSink);
5051	AssertRC(rc);
5052	#else
5053	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] PCM Output",
5054	AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
5055	AssertRC(rc);
5056	#endif
5057	/*
5058	* Add mixer input sinks.
5059	*/
5060	rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Line In",
5061	AUDMIXSINKDIR_INPUT, &pThis->SinkLineIn.pMixSink);
5062	AssertRC(rc);
5063	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5064	rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Microphone In",
5065	AUDMIXSINKDIR_INPUT, &pThis->SinkMicIn.pMixSink);
5066	AssertRC(rc);
5067	#endif
5068	/* There is no master volume control. Set the master to max. */
5069	PDMAUDIOVOLUME vol = { false, 255, 255 };
5070	rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
5071	AssertRC(rc);
5072	}
5073	}
5074
5075	if (RT_SUCCESS(rc))
5076	{
5077	/* Allocate CORB buffer. */
5078	pThis->cbCorbBuf = HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE;
5079	pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
5080	if (pThis->pu32CorbBuf)
5081	{
5082	/* Allocate RIRB buffer. */
5083	pThis->cbRirbBuf = HDA_RIRB_SIZE * HDA_RIRB_ELEMENT_SIZE;
5084	pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
5085	if (pThis->pu64RirbBuf)
5086	{
5087	/* Allocate codec. */
5088	pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
5089	if (!pThis->pCodec)
5090	rc = PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
5091	}
5092	else
5093	rc = PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating RIRB"));
5094	}
5095	else
5096	rc = PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating CORB"));
5097
5098	if (RT_SUCCESS(rc))
5099	{
5100	/* Set codec callbacks to this controller. */
5101	pThis->pCodec->pfnCbMixerAddStream = hdaR3MixerAddStream;
5102	pThis->pCodec->pfnCbMixerRemoveStream = hdaR3MixerRemoveStream;
5103	pThis->pCodec->pfnCbMixerControl = hdaR3MixerControl;
5104	pThis->pCodec->pfnCbMixerSetVolume = hdaR3MixerSetVolume;
5105
5106	pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
5107
5108	/* Construct the codec. */
5109	rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfg);
5110	if (RT_FAILURE(rc))
5111	AssertRCReturn(rc, rc);
5112
5113	/* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
5114	verb F20 should provide device/codec recognition. */
5115	Assert(pThis->pCodec->u16VendorId);
5116	Assert(pThis->pCodec->u16DeviceId);
5117	PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
5118	PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
5119	}
5120	}
5121
5122	if (RT_SUCCESS(rc))
5123	{
5124	/*
5125	* Create all hardware streams.
5126	*/
5127	for (uint8_t i = 0; i < HDA_MAX_STREAMS; ++i)
5128	{
5129	/* Create the emulation timer (per stream).
5130	*
5131	* Note: Use TMCLOCK_VIRTUAL_SYNC here, as the guest's HDA driver
5132	* relies on exact (virtual) DMA timing and uses DMA Position Buffers
5133	* instead of the LPIB registers.
5134	*/
5135	char szTimer[16];
5136	RTStrPrintf2(szTimer, sizeof(szTimer), "HDA SD%RU8", i);
5137
5138	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, hdaR3Timer, &pThis->aStreams[i],
5139	TMTIMER_FLAGS_NO_CRIT_SECT, szTimer, &pThis->pTimer[i]);
5140	AssertRCReturn(rc, rc);
5141
5142	/* Use our own critcal section for the device timer.
5143	* That way we can control more fine-grained when to lock what. */
5144	rc = TMR3TimerSetCritSect(pThis->pTimer[i], &pThis->CritSect);
5145	AssertRCReturn(rc, rc);
5146
5147	rc = hdaR3StreamCreate(&pThis->aStreams[i], pThis, i /* u8SD */);
5148	AssertRC(rc);
5149	}
5150
5151	#ifdef VBOX_WITH_AUDIO_HDA_ONETIME_INIT
5152	/*
5153	* Initialize the driver chain.
5154	*/
5155	PHDADRIVER pDrv;
5156	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
5157	{
5158	/*
5159	* Only primary drivers are critical for the VM to run. Everything else
5160	* might not worth showing an own error message box in the GUI.
5161	*/
5162	if (!(pDrv->fFlags & PDMAUDIODRVFLAGS_PRIMARY))
5163	continue;
5164
5165	PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
5166	AssertPtr(pCon);
5167
5168	bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
5169	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5170	bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
5171	# endif
5172	bool fValidOut = AudioMixerStreamIsValid(pDrv->Front.pMixStrm);
5173	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
5174	/** @todo Anything to do here? */
5175	# endif
5176
5177	if ( !fValidLineIn
5178	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5179	&& !fValidMicIn
5180	# endif
5181	&& !fValidOut)
5182	{
5183	LogRel(("HDA: Falling back to NULL backend (no sound audible)\n"));
5184
5185	hdaR3Reset(pDevIns);
5186	hdaR3ReattachInternal(pThis, pDrv, pDrv->uLUN, "NullAudio");
5187
5188	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
5189	N_("No audio devices could be opened. Selecting the NULL audio backend "
5190	"with the consequence that no sound is audible"));
5191	}
5192	else
5193	{
5194	bool fWarn = false;
5195
5196	PDMAUDIOBACKENDCFG backendCfg;
5197	int rc2 = pCon->pfnGetConfig(pCon, &backendCfg);
5198	if (RT_SUCCESS(rc2))
5199	{
5200	if (backendCfg.cMaxStreamsIn)
5201	{
5202	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5203	/* If the audio backend supports two or more input streams at once,
5204	* warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
5205	if (backendCfg.cMaxStreamsIn >= 2)
5206	fWarn = !fValidLineIn \|\| !fValidMicIn;
5207	/* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
5208	* not ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
5209	* One of the two simply is not in use then. */
5210	else if (backendCfg.cMaxStreamsIn == 1)
5211	fWarn = !fValidLineIn && !fValidMicIn;
5212	/* Don't warn if our backend is not able of supporting any input streams at all. */
5213	# else /* !VBOX_WITH_AUDIO_HDA_MIC_IN */
5214	/* We only have line-in as input source. */
5215	fWarn = !fValidLineIn;
5216	# endif /* VBOX_WITH_AUDIO_HDA_MIC_IN */
5217	}
5218
5219	if ( !fWarn
5220	&& backendCfg.cMaxStreamsOut)
5221	{
5222	fWarn = !fValidOut;
5223	}
5224	}
5225	else
5226	{
5227	LogRel(("HDA: Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
5228	fWarn = true;
5229	}
5230
5231	if (fWarn)
5232	{
5233	char szMissingStreams[255];
5234	size_t len = 0;
5235	if (!fValidLineIn)
5236	{
5237	LogRel(("HDA: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
5238	len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
5239	}
5240	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5241	if (!fValidMicIn)
5242	{
5243	LogRel(("HDA: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
5244	len += RTStrPrintf(szMissingStreams + len,
5245	sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
5246	}
5247	# endif /* VBOX_WITH_AUDIO_HDA_MIC_IN */
5248	if (!fValidOut)
5249	{
5250	LogRel(("HDA: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
5251	len += RTStrPrintf(szMissingStreams + len,
5252	sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
5253	}
5254
5255	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
5256	N_("Some HDA audio streams (%s) could not be opened. Guest applications generating audio "
5257	"output or depending on audio input may hang. Make sure your host audio device "
5258	"is working properly. Check the logfile for error messages of the audio "
5259	"subsystem"), szMissingStreams);
5260	}
5261	}
5262	}
5263	#endif /* VBOX_WITH_AUDIO_HDA_ONETIME_INIT */
5264	}
5265
5266	if (RT_SUCCESS(rc))
5267	{
5268	hdaR3Reset(pDevIns);
5269
5270	/*
5271	* Debug and string formatter types.
5272	*/
5273	PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaR3DbgInfo);
5274	PDMDevHlpDBGFInfoRegister(pDevIns, "hdabdle", "HDA stream BDLE info. (hdabdle [stream number])", hdaR3DbgInfoBDLE);
5275	PDMDevHlpDBGFInfoRegister(pDevIns, "hdastream", "HDA stream info. (hdastream [stream number])", hdaR3DbgInfoStream);
5276	PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaR3DbgInfoCodecNodes);
5277	PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaR3DbgInfoCodecSelector);
5278	PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaR3DbgInfoMixer);
5279
5280	rc = RTStrFormatTypeRegister("bdle", hdaR3StrFmtBDLE, NULL);
5281	AssertRC(rc);
5282	rc = RTStrFormatTypeRegister("sdctl", hdaR3StrFmtSDCTL, NULL);
5283	AssertRC(rc);
5284	rc = RTStrFormatTypeRegister("sdsts", hdaR3StrFmtSDSTS, NULL);
5285	AssertRC(rc);
5286	rc = RTStrFormatTypeRegister("sdfifos", hdaR3StrFmtSDFIFOS, NULL);
5287	AssertRC(rc);
5288	rc = RTStrFormatTypeRegister("sdfifow", hdaR3StrFmtSDFIFOW, NULL);
5289	AssertRC(rc);
5290
5291	/*
5292	* Some debug assertions.
5293	*/
5294	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
5295	{
5296	struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
5297	struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
5298
5299	/* binary search order. */
5300	AssertReleaseMsg(!pNextReg \|\| pReg->offset + pReg->size <= pNextReg->offset,
5301	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5302	i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
5303
5304	/* alignment. */
5305	AssertReleaseMsg( pReg->size == 1
5306	\|\| (pReg->size == 2 && (pReg->offset & 1) == 0)
5307	\|\| (pReg->size == 3 && (pReg->offset & 3) == 0)
5308	\|\| (pReg->size == 4 && (pReg->offset & 3) == 0),
5309	("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5310
5311	/* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
5312	AssertRelease(((pReg->offset + pReg->size) & 3) == 0 \|\| pNextReg);
5313	if (pReg->offset & 3)
5314	{
5315	struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
5316	AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5317	if (pPrevReg)
5318	AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
5319	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5320	i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
5321	}
5322	#if 0
5323	if ((pReg->offset + pReg->size) & 3)
5324	{
5325	AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5326	if (pNextReg)
5327	AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
5328	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5329	i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
5330	}
5331	#endif
5332	/* The final entry is a full DWORD, no gaps! Allows shortcuts. */
5333	AssertReleaseMsg(pNextReg \|\| ((pReg->offset + pReg->size) & 3) == 0,
5334	("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5335	}
5336	}
5337
5338	# ifdef VBOX_WITH_STATISTICS
5339	if (RT_SUCCESS(rc))
5340	{
5341	/*
5342	* Register statistics.
5343	*/
5344	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaR3Timer.");
5345	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIn, STAMTYPE_PROFILE, "/Devices/HDA/Input", STAMUNIT_TICKS_PER_CALL, "Profiling input.");
5346	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatOut, STAMTYPE_PROFILE, "/Devices/HDA/Output", STAMUNIT_TICKS_PER_CALL, "Profiling output.");
5347	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
5348	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
5349	}
5350	# endif
5351
5352	LogFlowFuncLeaveRC(rc);
5353	return rc;
5354	}
5355
5356	/**
5357	* The device registration structure.
5358	*/
5359	const PDMDEVREG g_DeviceHDA =
5360	{
5361	/* u32Version */
5362	PDM_DEVREG_VERSION,
5363	/* szName */
5364	"hda",
5365	/* szRCMod */
5366	"VBoxDDRC.rc",
5367	/* szR0Mod */
5368	"VBoxDDR0.r0",
5369	/* pszDescription */
5370	"Intel HD Audio Controller",
5371	/* fFlags */
5372	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
5373	/* fClass */
5374	PDM_DEVREG_CLASS_AUDIO,
5375	/* cMaxInstances */
5376	1,
5377	/* cbInstance */
5378	sizeof(HDASTATE),
5379	/* pfnConstruct */
5380	hdaR3Construct,
5381	/* pfnDestruct */
5382	hdaR3Destruct,
5383	/* pfnRelocate */
5384	hdaR3Relocate,
5385	/* pfnMemSetup */
5386	NULL,
5387	/* pfnPowerOn */
5388	NULL,
5389	/* pfnReset */
5390	hdaR3Reset,
5391	/* pfnSuspend */
5392	NULL,
5393	/* pfnResume */
5394	NULL,
5395	/* pfnAttach */
5396	hdaR3Attach,
5397	/* pfnDetach */
5398	hdaR3Detach,
5399	/* pfnQueryInterface. */
5400	NULL,
5401	/* pfnInitComplete */
5402	NULL,
5403	/* pfnPowerOff */
5404	hdaR3PowerOff,
5405	/* pfnSoftReset */
5406	NULL,
5407	/* u32VersionEnd */
5408	PDM_DEVREG_VERSION
5409	};
5410
5411	#endif /* IN_RING3 */
5412	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5413

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source: vbox/trunk/src/VBox/Devices/Audio/DevHDA.cpp@ 73838

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