DevHDA.cpp@ 74518

Last change on this file since 74518 was 74067, checked in by vboxsync, 6 years ago
Audio/HDA: Implemented hdaR3MixerAddDrv() / hdaR3MixerRemoveDrv() and added the ability to (re-)set the recording source automatically when a driver get detached at runtime.
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File size: 194.7 KB

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1	/* $Id: DevHDA.cpp 74067 2018-09-04 13:22:49Z vboxsync $ */
2	/** @file
3	* DevHDA.cpp - VBox Intel HD Audio Controller.
4	*
5	* Implemented against the specifications found in "High Definition Audio
6	* Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7	* HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8	*/
9
10	/*
11	* Copyright (C) 2006-2018 Oracle Corporation
12	*
13	* This file is part of VirtualBox Open Source Edition (OSE), as
14	* available from http://www.virtualbox.org. This file is free software;
15	* you can redistribute it and/or modify it under the terms of the GNU
16	* General Public License (GPL) as published by the Free Software
17	* Foundation, in version 2 as it comes in the "COPYING" file of the
18	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20	*/
21
22
23	/*********************************************************************************************************************************
24	* Header Files *
25	*********************************************************************************************************************************/
26	#define LOG_GROUP LOG_GROUP_DEV_HDA
27	#include <VBox/log.h>
28
29	#include <VBox/vmm/pdmdev.h>
30	#include <VBox/vmm/pdmaudioifs.h>
31	#include <VBox/version.h>
32	#include <VBox/AssertGuest.h>
33
34	#include <iprt/assert.h>
35	#include <iprt/asm.h>
36	#include <iprt/asm-math.h>
37	#include <iprt/file.h>
38	#include <iprt/list.h>
39	#ifdef IN_RING3
40	# include <iprt/mem.h>
41	# include <iprt/semaphore.h>
42	# include <iprt/string.h>
43	# include <iprt/uuid.h>
44	#endif
45
46	#include "VBoxDD.h"
47
48	#include "AudioMixBuffer.h"
49	#include "AudioMixer.h"
50
51	#include "DevHDA.h"
52	#include "DevHDACommon.h"
53
54	#include "HDACodec.h"
55	#include "HDAStream.h"
56	# if defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT) \|\| defined(VBOX_WITH_AUDIO_HDA_51_SURROUND)
57	# include "HDAStreamChannel.h"
58	# endif
59	#include "HDAStreamMap.h"
60	#include "HDAStreamPeriod.h"
61
62	#include "DrvAudio.h"
63
64
65	/*********************************************************************************************************************************
66	* Defined Constants And Macros *
67	*********************************************************************************************************************************/
68	//#define HDA_AS_PCI_EXPRESS
69
70	/* Installs a DMA access handler (via PGM callback) to monitor
71	* HDA's DMA operations, that is, writing / reading audio stream data.
72	*
73	* !!! Note: Certain guests are that timing sensitive that when enabling !!!
74	* !!! such a handler will mess up audio completely (e.g. Windows 7). !!! */
75	//#define HDA_USE_DMA_ACCESS_HANDLER
76	#ifdef HDA_USE_DMA_ACCESS_HANDLER
77	# include <VBox/vmm/pgm.h>
78	#endif
79
80	/* Uses the DMA access handler to read the written DMA audio (output) data.
81	* Only valid if HDA_USE_DMA_ACCESS_HANDLER is set.
82	*
83	* Also see the note / warning for HDA_USE_DMA_ACCESS_HANDLER. */
84	//# define HDA_USE_DMA_ACCESS_HANDLER_WRITING
85
86	/* Useful to debug the device' timing. */
87	//#define HDA_DEBUG_TIMING
88
89	/* To debug silence coming from the guest in form of audio gaps.
90	* Very crude implementation for now. */
91	//#define HDA_DEBUG_SILENCE
92
93	#if defined(VBOX_WITH_HP_HDA)
94	/* HP Pavilion dv4t-1300 */
95	# define HDA_PCI_VENDOR_ID 0x103c
96	# define HDA_PCI_DEVICE_ID 0x30f7
97	#elif defined(VBOX_WITH_INTEL_HDA)
98	/* Intel HDA controller */
99	# define HDA_PCI_VENDOR_ID 0x8086
100	# define HDA_PCI_DEVICE_ID 0x2668
101	#elif defined(VBOX_WITH_NVIDIA_HDA)
102	/* nVidia HDA controller */
103	# define HDA_PCI_VENDOR_ID 0x10de
104	# define HDA_PCI_DEVICE_ID 0x0ac0
105	#else
106	# error "Please specify your HDA device vendor/device IDs"
107	#endif
108
109	/* Make sure that interleaving streams support is enabled if the 5.1 surround code is being used. */
110	#if defined (VBOX_WITH_AUDIO_HDA_51_SURROUND) && !defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT)
111	# define VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT
112	#endif
113
114	/**
115	* Acquires the HDA lock.
116	*/
117	#define DEVHDA_LOCK(a_pThis) \
118	do { \
119	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
120	AssertRC(rcLock); \
121	} while (0)
122
123	/**
124	* Acquires the HDA lock or returns.
125	*/
126	# define DEVHDA_LOCK_RETURN(a_pThis, a_rcBusy) \
127	do { \
128	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, a_rcBusy); \
129	if (rcLock != VINF_SUCCESS) \
130	{ \
131	AssertRC(rcLock); \
132	return rcLock; \
133	} \
134	} while (0)
135
136	/**
137	* Acquires the HDA lock or returns.
138	*/
139	# define DEVHDA_LOCK_RETURN_VOID(a_pThis) \
140	do { \
141	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
142	if (rcLock != VINF_SUCCESS) \
143	{ \
144	AssertRC(rcLock); \
145	return; \
146	} \
147	} while (0)
148
149	/**
150	* Releases the HDA lock.
151	*/
152	#define DEVHDA_UNLOCK(a_pThis) \
153	do { PDMCritSectLeave(&(a_pThis)->CritSect); } while (0)
154
155	/**
156	* Acquires the TM lock and HDA lock, returns on failure.
157	*/
158	#define DEVHDA_LOCK_BOTH_RETURN_VOID(a_pThis, a_SD) \
159	do { \
160	int rcLock = TMTimerLock((a_pThis)->pTimer[a_SD], VERR_IGNORED); \
161	if (rcLock != VINF_SUCCESS) \
162	{ \
163	AssertRC(rcLock); \
164	return; \
165	} \
166	rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
167	if (rcLock != VINF_SUCCESS) \
168	{ \
169	AssertRC(rcLock); \
170	TMTimerUnlock((a_pThis)->pTimer[a_SD]); \
171	return; \
172	} \
173	} while (0)
174
175	/**
176	* Acquires the TM lock and HDA lock, returns on failure.
177	*/
178	#define DEVHDA_LOCK_BOTH_RETURN(a_pThis, a_SD, a_rcBusy) \
179	do { \
180	int rcLock = TMTimerLock((a_pThis)->pTimer[a_SD], (a_rcBusy)); \
181	if (rcLock != VINF_SUCCESS) \
182	return rcLock; \
183	rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, (a_rcBusy)); \
184	if (rcLock != VINF_SUCCESS) \
185	{ \
186	AssertRC(rcLock); \
187	TMTimerUnlock((a_pThis)->pTimer[a_SD]); \
188	return rcLock; \
189	} \
190	} while (0)
191
192	/**
193	* Releases the HDA lock and TM lock.
194	*/
195	#define DEVHDA_UNLOCK_BOTH(a_pThis, a_SD) \
196	do { \
197	PDMCritSectLeave(&(a_pThis)->CritSect); \
198	TMTimerUnlock((a_pThis)->pTimer[a_SD]); \
199	} while (0)
200
201
202	/*********************************************************************************************************************************
203	* Structures and Typedefs *
204	*********************************************************************************************************************************/
205
206	/**
207	* Structure defining a (host backend) driver stream.
208	* Each driver has its own instances of audio mixer streams, which then
209	* can go into the same (or even different) audio mixer sinks.
210	*/
211	typedef struct HDADRIVERSTREAM
212	{
213	/** Associated mixer handle. */
214	R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
215	} HDADRIVERSTREAM, *PHDADRIVERSTREAM;
216
217	#ifdef HDA_USE_DMA_ACCESS_HANDLER
218	/**
219	* Struct for keeping an HDA DMA access handler context.
220	*/
221	typedef struct HDADMAACCESSHANDLER
222	{
223	/** Node for storing this handler in our list in HDASTREAMSTATE. */
224	RTLISTNODER3 Node;
225	/** Pointer to stream to which this access handler is assigned to. */
226	R3PTRTYPE(PHDASTREAM) pStream;
227	/** Access handler type handle. */
228	PGMPHYSHANDLERTYPE hAccessHandlerType;
229	/** First address this handler uses. */
230	RTGCPHYS GCPhysFirst;
231	/** Last address this handler uses. */
232	RTGCPHYS GCPhysLast;
233	/** Actual BDLE address to handle. */
234	RTGCPHYS BDLEAddr;
235	/** Actual BDLE buffer size to handle. */
236	RTGCPHYS BDLESize;
237	/** Whether the access handler has been registered or not. */
238	bool fRegistered;
239	uint8_t Padding[3];
240	} HDADMAACCESSHANDLER, *PHDADMAACCESSHANDLER;
241	#endif
242
243	/**
244	* Struct for maintaining a host backend driver.
245	* This driver must be associated to one, and only one,
246	* HDA codec. The HDA controller does the actual multiplexing
247	* of HDA codec data to various host backend drivers then.
248	*
249	* This HDA device uses a timer in order to synchronize all
250	* read/write accesses across all attached LUNs / backends.
251	*/
252	typedef struct HDADRIVER
253	{
254	/** Node for storing this driver in our device driver list of HDASTATE. */
255	RTLISTNODER3 Node;
256	/** Pointer to HDA controller (state). */
257	R3PTRTYPE(PHDASTATE) pHDAState;
258	/** Driver flags. */
259	PDMAUDIODRVFLAGS fFlags;
260	uint8_t u32Padding0[2];
261	/** LUN to which this driver has been assigned. */
262	uint8_t uLUN;
263	/** Whether this driver is in an attached state or not. */
264	bool fAttached;
265	/** Pointer to attached driver base interface. */
266	R3PTRTYPE(PPDMIBASE) pDrvBase;
267	/** Audio connector interface to the underlying host backend. */
268	R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
269	/** Mixer stream for line input. */
270	HDADRIVERSTREAM LineIn;
271	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
272	/** Mixer stream for mic input. */
273	HDADRIVERSTREAM MicIn;
274	#endif
275	/** Mixer stream for front output. */
276	HDADRIVERSTREAM Front;
277	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
278	/** Mixer stream for center/LFE output. */
279	HDADRIVERSTREAM CenterLFE;
280	/** Mixer stream for rear output. */
281	HDADRIVERSTREAM Rear;
282	#endif
283	} HDADRIVER;
284
285
286	/*********************************************************************************************************************************
287	* Internal Functions *
288	*********************************************************************************************************************************/
289	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
290	#ifdef IN_RING3
291	static void hdaR3GCTLReset(PHDASTATE pThis);
292	#endif
293
294	/** @name Register read/write stubs.
295	* @{
296	*/
297	static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
298	static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
299	/** @} */
300
301	/** @name Global register set read/write functions.
302	* @{
303	*/
304	static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
305	static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
306	static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
307	static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
308	static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
309	static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
310	static int hdaRegWriteCORBSIZE(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
311	static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
312	static int hdaRegWriteRINTCNT(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
313	static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
314	static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
315	static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
316	static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
317	static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
318	static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
319	/** @} */
320
321	/** @name {IOB}SDn write functions.
322	* @{
323	*/
324	static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
325	static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
326	static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
327	static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
328	static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
329	static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
330	static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
331	static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
332	static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
333	/** @} */
334
335	/** @name Generic register read/write functions.
336	* @{
337	*/
338	static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
339	static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
340	static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
341	#ifdef IN_RING3
342	static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
343	#endif
344	static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
345	static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
346	static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
347	static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
348	/** @} */
349
350	/** @name HDA device functions.
351	* @{
352	*/
353	#ifdef IN_RING3
354	static int hdaR3AddStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg);
355	static int hdaR3RemoveStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg);
356	# ifdef HDA_USE_DMA_ACCESS_HANDLER
357	static DECLCALLBACK(VBOXSTRICTRC) hdaR3DMAAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys,
358	void *pvBuf, size_t cbBuf,
359	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser);
360	# endif
361	#endif /* IN_RING3 */
362	/** @} */
363
364	/** @name HDA mixer functions.
365	* @{
366	*/
367	#ifdef IN_RING3
368	static int hdaR3MixerAddDrvStream(PHDASTATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg, PHDADRIVER pDrv);
369	#endif
370	/** @} */
371
372
373	/*********************************************************************************************************************************
374	* Global Variables *
375	*********************************************************************************************************************************/
376
377	/** No register description (RD) flags defined. */
378	#define HDA_RD_FLAG_NONE 0
379	/** Writes to SD are allowed while RUN bit is set. */
380	#define HDA_RD_FLAG_SD_WRITE_RUN RT_BIT(0)
381
382	/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
383	#define HDA_REG_MAP_STRM(offset, name) \
384	/* offset size read mask write mask flags read callback write callback index + abbrev description */ \
385	/* ------- ------- ---------- ---------- ------------------------- -------------- ----------------- ----------------------------- ----------- */ \
386	/* Offset 0x80 (SD0) */ \
387	{ offset, 0x00003, 0x00FF001F, 0x00F0001F, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL) , #name " Stream Descriptor Control" }, \
388	/* Offset 0x83 (SD0) */ \
389	{ offset + 0x3, 0x00001, 0x0000003C, 0x0000001C, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU8 , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS) , #name " Status" }, \
390	/* Offset 0x84 (SD0) */ \
391	{ offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadLPIB, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
392	/* Offset 0x88 (SD0) */ \
393	{ offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDCBL , HDA_REG_IDX_STRM(name, CBL) , #name " Cyclic Buffer Length" }, \
394	/* Offset 0x8C (SD0) */ \
395	{ offset + 0xC, 0x00002, 0x0000FFFF, 0x0000FFFF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDLVI , HDA_REG_IDX_STRM(name, LVI) , #name " Last Valid Index" }, \
396	/* Reserved: FIFO Watermark. ** @todo Document this! */ \
397	{ offset + 0xE, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
398	/* Offset 0x90 (SD0) */ \
399	{ offset + 0x10, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
400	/* Offset 0x92 (SD0) */ \
401	{ offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFMT , HDA_REG_IDX_STRM(name, FMT) , #name " Stream Format" }, \
402	/* Reserved: 0x94 - 0x98. */ \
403	/* Offset 0x98 (SD0) */ \
404	{ offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
405	/* Offset 0x9C (SD0) */ \
406	{ offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
407
408	/** Defines a single audio stream register set (e.g. OSD0). */
409	#define HDA_REG_MAP_DEF_STREAM(index, name) \
410	HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
411
412	/* See 302349 p 6.2. */
413	const HDAREGDESC g_aHdaRegMap[HDA_NUM_REGS] =
414	{
415	/* offset size read mask write mask flags read callback write callback index + abbrev */
416	/------- ------- ---------- ---------- ----------------- ---------------- ------------------- ------------------------ /
417	{ 0x00000, 0x00002, 0x0000FFFB, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(GCAP) }, /* Global Capabilities */
418	{ 0x00002, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMIN) }, /* Minor Version */
419	{ 0x00003, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMAJ) }, /* Major Version */
420	{ 0x00004, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTPAY) }, /* Output Payload Capabilities */
421	{ 0x00006, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INPAY) }, /* Input Payload Capabilities */
422	{ 0x00008, 0x00004, 0x00000103, 0x00000103, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteGCTL , HDA_REG_IDX(GCTL) }, /* Global Control */
423	{ 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(WAKEEN) }, /* Wake Enable */
424	{ 0x0000e, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteSTATESTS, HDA_REG_IDX(STATESTS) }, /* State Change Status */
425	{ 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadUnimpl, hdaRegWriteUnimpl , HDA_REG_IDX(GSTS) }, /* Global Status */
426	{ 0x00018, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTSTRMPAY) }, /* Output Stream Payload Capability */
427	{ 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INSTRMPAY) }, /* Input Stream Payload Capability */
428	{ 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */
429	{ 0x00024, 0x00004, 0xC00000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */
430	{ 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadWALCLK, hdaRegWriteUnimpl , HDA_REG_IDX_NOMEM(WALCLK) }, /* Wall Clock Counter */
431	{ 0x00034, 0x00004, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */
432	{ 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
433	{ 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBUBASE) }, /* CORB Upper Base Address */
434	{ 0x00048, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteCORBWP , HDA_REG_IDX(CORBWP) }, /* CORB Write Pointer */
435	{ 0x0004A, 0x00002, 0x000080FF, 0x00008000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteCORBRP , HDA_REG_IDX(CORBRP) }, /* CORB Read Pointer */
436	{ 0x0004C, 0x00001, 0x00000003, 0x00000003, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL) }, /* CORB Control */
437	{ 0x0004D, 0x00001, 0x00000001, 0x00000001, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS) }, /* CORB Status */
438	{ 0x0004E, 0x00001, 0x000000F3, 0x00000003, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBSIZE, HDA_REG_IDX(CORBSIZE) }, /* CORB Size */
439	{ 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBLBASE) }, /* RIRB Lower Base Address */
440	{ 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBUBASE) }, /* RIRB Upper Base Address */
441	{ 0x00058, 0x00002, 0x000000FF, 0x00008000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteRIRBWP , HDA_REG_IDX(RIRBWP) }, /* RIRB Write Pointer */
442	{ 0x0005A, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteRINTCNT , HDA_REG_IDX(RINTCNT) }, /* Response Interrupt Count */
443	{ 0x0005C, 0x00001, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteU8 , HDA_REG_IDX(RIRBCTL) }, /* RIRB Control */
444	{ 0x0005D, 0x00001, 0x00000005, 0x00000005, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS) }, /* RIRB Status */
445	{ 0x0005E, 0x00001, 0x000000F3, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(RIRBSIZE) }, /* RIRB Size */
446	{ 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(IC) }, /* Immediate Command */
447	{ 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(IR) }, /* Immediate Response */
448	{ 0x00068, 0x00002, 0x00000002, 0x00000002, HDA_RD_FLAG_NONE, hdaRegReadIRS , hdaRegWriteIRS , HDA_REG_IDX(IRS) }, /* Immediate Command Status */
449	{ 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPLBASE) }, /* DMA Position Lower Base */
450	{ 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPUBASE) }, /* DMA Position Upper Base */
451	/* 4 Serial Data In (SDI). */
452	HDA_REG_MAP_DEF_STREAM(0, SD0),
453	HDA_REG_MAP_DEF_STREAM(1, SD1),
454	HDA_REG_MAP_DEF_STREAM(2, SD2),
455	HDA_REG_MAP_DEF_STREAM(3, SD3),
456	/* 4 Serial Data Out (SDO). */
457	HDA_REG_MAP_DEF_STREAM(4, SD4),
458	HDA_REG_MAP_DEF_STREAM(5, SD5),
459	HDA_REG_MAP_DEF_STREAM(6, SD6),
460	HDA_REG_MAP_DEF_STREAM(7, SD7)
461	};
462
463	const HDAREGALIAS g_aHdaRegAliases[] =
464	{
465	{ 0x2084, HDA_REG_SD0LPIB },
466	{ 0x20a4, HDA_REG_SD1LPIB },
467	{ 0x20c4, HDA_REG_SD2LPIB },
468	{ 0x20e4, HDA_REG_SD3LPIB },
469	{ 0x2104, HDA_REG_SD4LPIB },
470	{ 0x2124, HDA_REG_SD5LPIB },
471	{ 0x2144, HDA_REG_SD6LPIB },
472	{ 0x2164, HDA_REG_SD7LPIB }
473	};
474
475	#ifdef IN_RING3
476
477	/** HDABDLEDESC field descriptors for the v7 saved state. */
478	static SSMFIELD const g_aSSMBDLEDescFields7[] =
479	{
480	SSMFIELD_ENTRY(HDABDLEDESC, u64BufAdr),
481	SSMFIELD_ENTRY(HDABDLEDESC, u32BufSize),
482	SSMFIELD_ENTRY(HDABDLEDESC, fFlags),
483	SSMFIELD_ENTRY_TERM()
484	};
485
486	/** HDABDLESTATE field descriptors for the v6+ saved state. */
487	static SSMFIELD const g_aSSMBDLEStateFields6[] =
488	{
489	SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
490	SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
491	SSMFIELD_ENTRY_OLD(FIFO, HDA_FIFO_MAX), /* Deprecated; now is handled in the stream's circular buffer. */
492	SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
493	SSMFIELD_ENTRY_TERM()
494	};
495
496	/** HDABDLESTATE field descriptors for the v7 saved state. */
497	static SSMFIELD const g_aSSMBDLEStateFields7[] =
498	{
499	SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
500	SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
501	SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
502	SSMFIELD_ENTRY_TERM()
503	};
504
505	/** HDASTREAMSTATE field descriptors for the v6 saved state. */
506	static SSMFIELD const g_aSSMStreamStateFields6[] =
507	{
508	SSMFIELD_ENTRY_OLD(cBDLE, sizeof(uint16_t)), /* Deprecated. */
509	SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
510	SSMFIELD_ENTRY_OLD(fStop, 1), /* Deprecated; see SSMR3PutBool(). */
511	SSMFIELD_ENTRY_OLD(fRunning, 1), /* Deprecated; using the HDA_SDCTL_RUN bit is sufficient. */
512	SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
513	SSMFIELD_ENTRY_TERM()
514	};
515
516	/** HDASTREAMSTATE field descriptors for the v7 saved state. */
517	static SSMFIELD const g_aSSMStreamStateFields7[] =
518	{
519	SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
520	SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
521	SSMFIELD_ENTRY(HDASTREAMSTATE, tsTransferNext),
522	SSMFIELD_ENTRY_TERM()
523	};
524
525	/** HDASTREAMPERIOD field descriptors for the v7 saved state. */
526	static SSMFIELD const g_aSSMStreamPeriodFields7[] =
527	{
528	SSMFIELD_ENTRY(HDASTREAMPERIOD, u64StartWalClk),
529	SSMFIELD_ENTRY(HDASTREAMPERIOD, u64ElapsedWalClk),
530	SSMFIELD_ENTRY(HDASTREAMPERIOD, framesTransferred),
531	SSMFIELD_ENTRY(HDASTREAMPERIOD, cIntPending),
532	SSMFIELD_ENTRY_TERM()
533	};
534
535	/**
536	* 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
537	*/
538	static uint32_t const g_afMasks[5] =
539	{
540	UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
541	};
542
543	#endif /* IN_RING3 */
544
545
546
547	/**
548	* Retrieves the number of bytes of a FIFOW register.
549	*
550	* @return Number of bytes of a given FIFOW register.
551	*/
552	DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
553	{
554	uint32_t cb;
555	switch (u32RegFIFOW)
556	{
557	case HDA_SDFIFOW_8B: cb = 8; break;
558	case HDA_SDFIFOW_16B: cb = 16; break;
559	case HDA_SDFIFOW_32B: cb = 32; break;
560	default: cb = 0; break;
561	}
562
563	Assert(RT_IS_POWER_OF_TWO(cb));
564	return cb;
565	}
566
567	#ifdef IN_RING3
568	/**
569	* Reschedules pending interrupts for all audio streams which have complete
570	* audio periods but did not have the chance to issue their (pending) interrupts yet.
571	*
572	* @param pThis The HDA device state.
573	*/
574	static void hdaR3ReschedulePendingInterrupts(PHDASTATE pThis)
575	{
576	bool fInterrupt = false;
577
578	for (uint8_t i = 0; i < HDA_MAX_STREAMS; ++i)
579	{
580	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, i);
581	if (!pStream)
582	continue;
583
584	if ( hdaR3StreamPeriodIsComplete (&pStream->State.Period)
585	&& hdaR3StreamPeriodNeedsInterrupt(&pStream->State.Period)
586	&& hdaR3WalClkSet(pThis, hdaR3StreamPeriodGetAbsElapsedWalClk(&pStream->State.Period), false /* fForce */))
587	{
588	fInterrupt = true;
589	break;
590	}
591	}
592
593	LogFunc(("fInterrupt=%RTbool\n", fInterrupt));
594
595	# ifndef LOG_ENABLED
596	hdaProcessInterrupt(pThis);
597	# else
598	hdaProcessInterrupt(pThis, __FUNCTION__);
599	# endif
600	}
601	#endif /* IN_RING3 */
602
603	/**
604	* Looks up a register at the exact offset given by @a offReg.
605	*
606	* @returns Register index on success, -1 if not found.
607	* @param offReg The register offset.
608	*/
609	static int hdaRegLookup(uint32_t offReg)
610	{
611	/*
612	* Aliases.
613	*/
614	if (offReg >= g_aHdaRegAliases[0].offReg)
615	{
616	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
617	if (offReg == g_aHdaRegAliases[i].offReg)
618	return g_aHdaRegAliases[i].idxAlias;
619	Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
620	return -1;
621	}
622
623	/*
624	* Binary search the
625	*/
626	int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
627	int idxLow = 0;
628	for (;;)
629	{
630	int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
631	if (offReg < g_aHdaRegMap[idxMiddle].offset)
632	{
633	if (idxLow == idxMiddle)
634	break;
635	idxEnd = idxMiddle;
636	}
637	else if (offReg > g_aHdaRegMap[idxMiddle].offset)
638	{
639	idxLow = idxMiddle + 1;
640	if (idxLow >= idxEnd)
641	break;
642	}
643	else
644	return idxMiddle;
645	}
646
647	#ifdef RT_STRICT
648	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
649	Assert(g_aHdaRegMap[i].offset != offReg);
650	#endif
651	return -1;
652	}
653
654	#ifdef IN_RING3
655
656	/**
657	* Looks up a register covering the offset given by @a offReg.
658	*
659	* @returns Register index on success, -1 if not found.
660	* @param offReg The register offset.
661	*/
662	static int hdaR3RegLookupWithin(uint32_t offReg)
663	{
664	/*
665	* Aliases.
666	*/
667	if (offReg >= g_aHdaRegAliases[0].offReg)
668	{
669	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
670	{
671	uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
672	if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
673	return g_aHdaRegAliases[i].idxAlias;
674	}
675	Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
676	return -1;
677	}
678
679	/*
680	* Binary search the register map.
681	*/
682	int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
683	int idxLow = 0;
684	for (;;)
685	{
686	int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
687	if (offReg < g_aHdaRegMap[idxMiddle].offset)
688	{
689	if (idxLow == idxMiddle)
690	break;
691	idxEnd = idxMiddle;
692	}
693	else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
694	{
695	idxLow = idxMiddle + 1;
696	if (idxLow >= idxEnd)
697	break;
698	}
699	else
700	return idxMiddle;
701	}
702
703	# ifdef RT_STRICT
704	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
705	Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
706	# endif
707	return -1;
708	}
709
710
711	/**
712	* Synchronizes the CORB / RIRB buffers between internal <-> device state.
713	*
714	* @returns IPRT status code.
715	* @param pThis HDA state.
716	* @param fLocal Specify true to synchronize HDA state's CORB buffer with the device state,
717	* or false to synchronize the device state's RIRB buffer with the HDA state.
718	*
719	* @todo r=andy Break this up into two functions?
720	*/
721	static int hdaR3CmdSync(PHDASTATE pThis, bool fLocal)
722	{
723	int rc = VINF_SUCCESS;
724	if (fLocal)
725	{
726	if (pThis->u64CORBBase)
727	{
728	AssertPtr(pThis->pu32CorbBuf);
729	Assert(pThis->cbCorbBuf);
730
731	/** @todo r=bird: An explanation is required why PDMDevHlpPhysRead is used with
732	* the CORB and PDMDevHlpPCIPhysWrite with RIRB below. There are
733	* similar unexplained inconsistencies in DevHDACommon.cpp. */
734	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
735	Log(("hdaR3CmdSync/CORB: read %RGp LB %#x (%Rrc)\n", pThis->u64CORBBase, pThis->cbCorbBuf, rc));
736	AssertRCReturn(rc, rc);
737	}
738	}
739	else
740	{
741	if (pThis->u64RIRBBase)
742	{
743	AssertPtr(pThis->pu64RirbBuf);
744	Assert(pThis->cbRirbBuf);
745
746	rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
747	Log(("hdaR3CmdSync/RIRB: phys read %RGp LB %#x (%Rrc)\n", pThis->u64RIRBBase, pThis->pu64RirbBuf, rc));
748	AssertRCReturn(rc, rc);
749	}
750	}
751
752	# ifdef DEBUG_CMD_BUFFER
753	LogFunc(("fLocal=%RTbool\n", fLocal));
754
755	uint8_t i = 0;
756	do
757	{
758	LogFunc(("CORB%02x: ", i));
759	uint8_t j = 0;
760	do
761	{
762	const char *pszPrefix;
763	if ((i + j) == HDA_REG(pThis, CORBRP))
764	pszPrefix = "[R]";
765	else if ((i + j) == HDA_REG(pThis, CORBWP))
766	pszPrefix = "[W]";
767	else
768	pszPrefix = " "; /* three spaces */
769	Log((" %s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
770	j++;
771	} while (j < 8);
772	Log(("\n"));
773	i += 8;
774	} while(i != 0);
775
776	do
777	{
778	LogFunc(("RIRB%02x: ", i));
779	uint8_t j = 0;
780	do
781	{
782	const char *prefix;
783	if ((i + j) == HDA_REG(pThis, RIRBWP))
784	prefix = "[W]";
785	else
786	prefix = " ";
787	Log((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
788	} while (++j < 8);
789	Log(("\n"));
790	i += 8;
791	} while (i != 0);
792	# endif
793	return rc;
794	}
795
796	/**
797	* Processes the next CORB buffer command in the queue.
798	*
799	* This will invoke the HDA codec verb dispatcher.
800	*
801	* @returns IPRT status code.
802	* @param pThis HDA state.
803	*/
804	static int hdaR3CORBCmdProcess(PHDASTATE pThis)
805	{
806	uint8_t corbRp = HDA_REG(pThis, CORBRP);
807	uint8_t corbWp = HDA_REG(pThis, CORBWP);
808	uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
809
810	Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", corbRp, corbWp, rirbWp));
811
812	if (!(HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA))
813	{
814	LogFunc(("CORB DMA not active, skipping\n"));
815	return VINF_SUCCESS;
816	}
817
818	Assert(pThis->cbCorbBuf);
819
820	int rc = hdaR3CmdSync(pThis, true /* Sync from guest */);
821	AssertRCReturn(rc, rc);
822
823	uint16_t cIntCnt = HDA_REG(pThis, RINTCNT) & 0xff;
824
825	if (!cIntCnt) /* 0 means 256 interrupts. */
826	cIntCnt = HDA_MAX_RINTCNT;
827
828	Log3Func(("START CORB(RP:%x, WP:%x) RIRBWP:%x, RINTCNT:%RU8/%RU8\n",
829	corbRp, corbWp, rirbWp, pThis->u16RespIntCnt, cIntCnt));
830
831	while (corbRp != corbWp)
832	{
833	corbRp = (corbRp + 1) % (pThis->cbCorbBuf / HDA_CORB_ELEMENT_SIZE); /* Advance +1 as the first command(s) are at CORBWP + 1. */
834
835	uint32_t uCmd = pThis->pu32CorbBuf[corbRp];
836	uint64_t uResp = 0;
837
838	rc = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(uCmd, 0 /* Codec index */), &uResp);
839	if (RT_FAILURE(rc))
840	LogFunc(("Codec lookup failed with rc=%Rrc\n", rc));
841
842	Log3Func(("Codec verb %08x -> response %016lx\n", uCmd, uResp));
843
844	if ( (uResp & CODEC_RESPONSE_UNSOLICITED)
845	&& !(HDA_REG(pThis, GCTL) & HDA_GCTL_UNSOL))
846	{
847	LogFunc(("Unexpected unsolicited response.\n"));
848	HDA_REG(pThis, CORBRP) = corbRp;
849
850	/** @todo r=andy No CORB/RIRB syncing to guest required in that case? */
851	return rc;
852	}
853
854	rirbWp = (rirbWp + 1) % HDA_RIRB_SIZE;
855
856	pThis->pu64RirbBuf[rirbWp] = uResp;
857
858	pThis->u16RespIntCnt++;
859
860	bool fSendInterrupt = false;
861
862	if (pThis->u16RespIntCnt == cIntCnt) /* Response interrupt count reached? */
863	{
864	pThis->u16RespIntCnt = 0; /* Reset internal interrupt response counter. */
865
866	Log3Func(("Response interrupt count reached (%RU16)\n", pThis->u16RespIntCnt));
867	fSendInterrupt = true;
868
869	}
870	else if (corbRp == corbWp) /* Did we reach the end of the current command buffer? */
871	{
872	Log3Func(("Command buffer empty\n"));
873	fSendInterrupt = true;
874	}
875
876	if (fSendInterrupt)
877	{
878	if (HDA_REG(pThis, RIRBCTL) & HDA_RIRBCTL_RINTCTL) /* Response Interrupt Control (RINTCTL) enabled? */
879	{
880	HDA_REG(pThis, RIRBSTS) \|= HDA_RIRBSTS_RINTFL;
881
882	# ifndef LOG_ENABLED
883	rc = hdaProcessInterrupt(pThis);
884	# else
885	rc = hdaProcessInterrupt(pThis, __FUNCTION__);
886	# endif
887	}
888	}
889	}
890
891	Log3Func(("END CORB(RP:%x, WP:%x) RIRBWP:%x, RINTCNT:%RU8/%RU8\n",
892	corbRp, corbWp, rirbWp, pThis->u16RespIntCnt, cIntCnt));
893
894	HDA_REG(pThis, CORBRP) = corbRp;
895	HDA_REG(pThis, RIRBWP) = rirbWp;
896
897	rc = hdaR3CmdSync(pThis, false /* Sync to guest */);
898	AssertRCReturn(rc, rc);
899
900	if (RT_FAILURE(rc))
901	AssertRCReturn(rc, rc);
902
903	return rc;
904	}
905
906	#endif /* IN_RING3 */
907
908	/* Register access handlers. */
909
910	static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
911	{
912	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg);
913	*pu32Value = 0;
914	return VINF_SUCCESS;
915	}
916
917	static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
918	{
919	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
920	return VINF_SUCCESS;
921	}
922
923	/* U8 */
924	static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
925	{
926	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
927	return hdaRegReadU32(pThis, iReg, pu32Value);
928	}
929
930	static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
931	{
932	Assert((u32Value & 0xffffff00) == 0);
933	return hdaRegWriteU32(pThis, iReg, u32Value);
934	}
935
936	/* U16 */
937	static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
938	{
939	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
940	return hdaRegReadU32(pThis, iReg, pu32Value);
941	}
942
943	static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
944	{
945	Assert((u32Value & 0xffff0000) == 0);
946	return hdaRegWriteU32(pThis, iReg, u32Value);
947	}
948
949	/* U24 */
950	static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
951	{
952	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
953	return hdaRegReadU32(pThis, iReg, pu32Value);
954	}
955
956	#ifdef IN_RING3
957	static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
958	{
959	Assert((u32Value & 0xff000000) == 0);
960	return hdaRegWriteU32(pThis, iReg, u32Value);
961	}
962	#endif
963
964	/* U32 */
965	static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
966	{
967	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
968
969	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
970
971	*pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
972
973	DEVHDA_UNLOCK(pThis);
974	return VINF_SUCCESS;
975	}
976
977	static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
978	{
979	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
980
981	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
982
983	pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
984	\| (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
985	DEVHDA_UNLOCK(pThis);
986	return VINF_SUCCESS;
987	}
988
989	static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
990	{
991	RT_NOREF_PV(iReg);
992	#ifdef IN_RING3
993	DEVHDA_LOCK(pThis);
994	#else
995	if (!(u32Value & HDA_GCTL_CRST))
996	return VINF_IOM_R3_MMIO_WRITE;
997	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
998	#endif
999
1000	if (u32Value & HDA_GCTL_CRST)
1001	{
1002	/* Set the CRST bit to indicate that we're leaving reset mode. */
1003	HDA_REG(pThis, GCTL) \|= HDA_GCTL_CRST;
1004	LogFunc(("Guest leaving HDA reset\n"));
1005	}
1006	else
1007	{
1008	#ifdef IN_RING3
1009	/* Enter reset state. */
1010	LogFunc(("Guest entering HDA reset with DMA(RIRB:%s, CORB:%s)\n",
1011	HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA ? "on" : "off",
1012	HDA_REG(pThis, RIRBCTL) & HDA_RIRBCTL_RDMAEN ? "on" : "off"));
1013
1014	/* Clear the CRST bit to indicate that we're in reset state. */
1015	HDA_REG(pThis, GCTL) &= ~HDA_GCTL_CRST;
1016
1017	hdaR3GCTLReset(pThis);
1018	#else
1019	AssertFailedReturnStmt(DEVHDA_UNLOCK(pThis), VINF_IOM_R3_MMIO_WRITE);
1020	#endif
1021	}
1022
1023	if (u32Value & HDA_GCTL_FCNTRL)
1024	{
1025	/* Flush: GSTS:1 set, see 6.2.6. */
1026	HDA_REG(pThis, GSTS) \|= HDA_GSTS_FSTS; /* Set the flush status. */
1027	/* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
1028	}
1029
1030	DEVHDA_UNLOCK(pThis);
1031	return VINF_SUCCESS;
1032	}
1033
1034	static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1035	{
1036	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1037
1038	uint32_t v = HDA_REG_IND(pThis, iReg);
1039	uint32_t nv = u32Value & HDA_STATESTS_SCSF_MASK;
1040
1041	HDA_REG(pThis, STATESTS) &= ~(v & nv); /* Write of 1 clears corresponding bit. */
1042
1043	DEVHDA_UNLOCK(pThis);
1044	return VINF_SUCCESS;
1045	}
1046
1047	static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1048	{
1049	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
1050
1051	const uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
1052	uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, uSD);
1053	#ifdef LOG_ENABLED
1054	const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, uSD);
1055	LogFlowFunc(("[SD%RU8] LPIB=%RU32, CBL=%RU32\n", uSD, u32LPIB, u32CBL));
1056	#endif
1057
1058	*pu32Value = u32LPIB;
1059
1060	DEVHDA_UNLOCK(pThis);
1061	return VINF_SUCCESS;
1062	}
1063
1064	#ifdef IN_RING3
1065	/**
1066	* Returns the current maximum value the wall clock counter can be set to.
1067	* This maximum value depends on all currently handled HDA streams and their own current timing.
1068	*
1069	* @return Current maximum value the wall clock counter can be set to.
1070	* @param pThis HDA state.
1071	*
1072	* @remark Does not actually set the wall clock counter.
1073	*/
1074	static uint64_t hdaR3WalClkGetMax(PHDASTATE pThis)
1075	{
1076	const uint64_t u64WalClkCur = ASMAtomicReadU64(&pThis->u64WalClk);
1077	const uint64_t u64FrontAbsWalClk = pThis->SinkFront.pStream
1078	? hdaR3StreamPeriodGetAbsElapsedWalClk(&pThis->SinkFront.pStream->State.Period) : 0;
1079	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1080	# error "Implement me!"
1081	# endif
1082	const uint64_t u64LineInAbsWalClk = pThis->SinkLineIn.pStream
1083	? hdaR3StreamPeriodGetAbsElapsedWalClk(&pThis->SinkLineIn.pStream->State.Period) : 0;
1084	# ifdef VBOX_WITH_HDA_MIC_IN
1085	const uint64_t u64MicInAbsWalClk = pThis->SinkMicIn.pStream
1086	? hdaR3StreamPeriodGetAbsElapsedWalClk(&pThis->SinkMicIn.pStream->State.Period) : 0;
1087	# endif
1088
1089	uint64_t u64WalClkNew = RT_MAX(u64WalClkCur, u64FrontAbsWalClk);
1090	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1091	# error "Implement me!"
1092	# endif
1093	u64WalClkNew = RT_MAX(u64WalClkNew, u64LineInAbsWalClk);
1094	# ifdef VBOX_WITH_HDA_MIC_IN
1095	u64WalClkNew = RT_MAX(u64WalClkNew, u64MicInAbsWalClk);
1096	# endif
1097
1098	Log3Func(("%RU64 -> Front=%RU64, LineIn=%RU64 -> %RU64\n",
1099	u64WalClkCur, u64FrontAbsWalClk, u64LineInAbsWalClk, u64WalClkNew));
1100
1101	return u64WalClkNew;
1102	}
1103	#endif /* IN_RING3 */
1104
1105	static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1106	{
1107	#ifdef IN_RING3
1108	RT_NOREF(iReg);
1109
1110	DEVHDA_LOCK(pThis);
1111
1112	*pu32Value = RT_LO_U32(ASMAtomicReadU64(&pThis->u64WalClk));
1113
1114	Log3Func(("%RU32 (max @ %RU64)\n",*pu32Value, hdaR3WalClkGetMax(pThis)));
1115
1116	DEVHDA_UNLOCK(pThis);
1117	return VINF_SUCCESS;
1118	#else
1119	RT_NOREF(pThis, iReg, pu32Value);
1120	return VINF_IOM_R3_MMIO_READ;
1121	#endif
1122	}
1123
1124	static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1125	{
1126	RT_NOREF(iReg);
1127	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1128
1129	if (u32Value & HDA_CORBRP_RST)
1130	{
1131	/* Do a CORB reset. */
1132	if (pThis->cbCorbBuf)
1133	{
1134	#ifdef IN_RING3
1135	Assert(pThis->pu32CorbBuf);
1136	RT_BZERO((void *)pThis->pu32CorbBuf, pThis->cbCorbBuf);
1137	#else
1138	DEVHDA_UNLOCK(pThis);
1139	return VINF_IOM_R3_MMIO_WRITE;
1140	#endif
1141	}
1142
1143	LogRel2(("HDA: CORB reset\n"));
1144
1145	HDA_REG(pThis, CORBRP) = HDA_CORBRP_RST; /* Clears the pointer. */
1146	}
1147	else
1148	HDA_REG(pThis, CORBRP) &= ~HDA_CORBRP_RST; /* Only CORBRP_RST bit is writable. */
1149
1150	DEVHDA_UNLOCK(pThis);
1151	return VINF_SUCCESS;
1152	}
1153
1154	static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1155	{
1156	#ifdef IN_RING3
1157	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1158
1159	int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1160	AssertRC(rc);
1161
1162	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Start DMA engine. */
1163	{
1164	rc = hdaR3CORBCmdProcess(pThis);
1165	}
1166	else
1167	LogFunc(("CORB DMA not running, skipping\n"));
1168
1169	DEVHDA_UNLOCK(pThis);
1170	return rc;
1171	#else
1172	RT_NOREF(pThis, iReg, u32Value);
1173	return VINF_IOM_R3_MMIO_WRITE;
1174	#endif
1175	}
1176
1177	static int hdaRegWriteCORBSIZE(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1178	{
1179	#ifdef IN_RING3
1180	RT_NOREF(iReg);
1181	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1182
1183	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
1184	{
1185	LogFunc(("CORB DMA is (still) running, skipping\n"));
1186
1187	DEVHDA_UNLOCK(pThis);
1188	return VINF_SUCCESS;
1189	}
1190
1191	u32Value = (u32Value & HDA_CORBSIZE_SZ);
1192
1193	uint16_t cEntries = HDA_CORB_SIZE; /* Set default. */
1194
1195	switch (u32Value)
1196	{
1197	case 0: /* 8 byte; 2 entries. */
1198	cEntries = 2;
1199	break;
1200
1201	case 1: /* 64 byte; 16 entries. */
1202	cEntries = 16;
1203	break;
1204
1205	case 2: /* 1 KB; 256 entries. */
1206	/* Use default size. */
1207	break;
1208
1209	default:
1210	LogRel(("HDA: Guest tried to set an invalid CORB size (0x%x), keeping default\n", u32Value));
1211	u32Value = 2;
1212	/* Use default size. */
1213	break;
1214	}
1215
1216	uint32_t cbCorbBuf = cEntries * HDA_CORB_ELEMENT_SIZE;
1217	Assert(cbCorbBuf <= HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE); /* Paranoia. */
1218
1219	if (cbCorbBuf != pThis->cbCorbBuf)
1220	{
1221	RT_BZERO(pThis->pu32CorbBuf, HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE); /* Clear CORB when setting a new size. */
1222	pThis->cbCorbBuf = cbCorbBuf;
1223	}
1224
1225	LogFunc(("CORB buffer size is now %RU32 bytes (%u entries)\n", pThis->cbCorbBuf, pThis->cbCorbBuf / HDA_CORB_ELEMENT_SIZE));
1226
1227	HDA_REG(pThis, CORBSIZE) = u32Value;
1228
1229	DEVHDA_UNLOCK(pThis);
1230	return VINF_SUCCESS;
1231	#else
1232	RT_NOREF(pThis, iReg, u32Value);
1233	return VINF_IOM_R3_MMIO_WRITE;
1234	#endif
1235	}
1236
1237	static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1238	{
1239	RT_NOREF_PV(iReg);
1240	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1241
1242	uint32_t v = HDA_REG(pThis, CORBSTS);
1243	HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1244
1245	DEVHDA_UNLOCK(pThis);
1246	return VINF_SUCCESS;
1247	}
1248
1249	static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1250	{
1251	#ifdef IN_RING3
1252	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1253
1254	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
1255	AssertRCSuccess(rc);
1256
1257	rc = hdaR3CORBCmdProcess(pThis);
1258
1259	DEVHDA_UNLOCK(pThis);
1260	return rc;
1261	#else
1262	RT_NOREF(pThis, iReg, u32Value);
1263	return VINF_IOM_R3_MMIO_WRITE;
1264	#endif
1265	}
1266
1267	static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1268	{
1269	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1270
1271	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, CBL, iReg));
1272	if (pStream)
1273	{
1274	pStream->u32CBL = u32Value;
1275	LogFlowFunc(("[SD%RU8] CBL=%RU32\n", pStream->u8SD, u32Value));
1276	}
1277	else
1278	LogFunc(("[SD%RU8] Warning: Changing SDCBL on non-attached stream (0x%x)\n",
1279	HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
1280
1281	int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1282	AssertRCSuccess(rc);
1283
1284	DEVHDA_UNLOCK(pThis);
1285	return rc;
1286	}
1287
1288	static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1289	{
1290	#ifdef IN_RING3
1291	/* Get the stream descriptor. */
1292	const uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
1293
1294	DEVHDA_LOCK_BOTH_RETURN(pThis, uSD, VINF_IOM_R3_MMIO_WRITE);
1295
1296	/*
1297	* Some guests write too much (that is, 32-bit with the top 8 bit being junk)
1298	* instead of 24-bit required for SDCTL. So just mask this here to be safe.
1299	*/
1300	u32Value &= 0x00ffffff;
1301
1302	bool fRun = RT_BOOL(u32Value & HDA_SDCTL_RUN);
1303	bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_SDCTL_RUN);
1304
1305	bool fReset = RT_BOOL(u32Value & HDA_SDCTL_SRST);
1306	bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_SDCTL_SRST);
1307
1308	LogFunc(("[SD%RU8] fRun=%RTbool, fInRun=%RTbool, fReset=%RTbool, fInReset=%RTbool, %R[sdctl]\n",
1309	uSD, fRun, fInRun, fReset, fInReset, u32Value));
1310
1311	/*
1312	* Extract the stream tag the guest wants to use for this specific
1313	* stream descriptor (SDn). This only can happen if the stream is in a non-running
1314	* state, so we're doing the lookup and assignment here.
1315	*
1316	* So depending on the guest OS, SD3 can use stream tag 4, for example.
1317	*/
1318	uint8_t uTag = (u32Value >> HDA_SDCTL_NUM_SHIFT) & HDA_SDCTL_NUM_MASK;
1319	if (uTag > HDA_MAX_TAGS)
1320	{
1321	LogFunc(("[SD%RU8] Warning: Invalid stream tag %RU8 specified!\n", uSD, uTag));
1322
1323	int rc = hdaRegWriteU24(pThis, iReg, u32Value);
1324	DEVHDA_UNLOCK_BOTH(pThis, uSD);
1325	return rc;
1326	}
1327
1328	PHDATAG pTag = &pThis->aTags[uTag];
1329	AssertPtr(pTag);
1330
1331	LogFunc(("[SD%RU8] Using stream tag=%RU8\n", uSD, uTag));
1332
1333	/* Assign new values. */
1334	pTag->uTag = uTag;
1335	pTag->pStream = hdaGetStreamFromSD(pThis, uSD);
1336
1337	PHDASTREAM pStream = pTag->pStream;
1338	AssertPtr(pStream);
1339
1340	if (fInReset)
1341	{
1342	Assert(!fReset);
1343	Assert(!fInRun && !fRun);
1344
1345	/* Exit reset state. */
1346	ASMAtomicXchgBool(&pStream->State.fInReset, false);
1347
1348	/* Report that we're done resetting this stream by clearing SRST. */
1349	HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_SRST;
1350
1351	LogFunc(("[SD%RU8] Reset exit\n", uSD));
1352	}
1353	else if (fReset)
1354	{
1355	/* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
1356	Assert(!fInRun && !fRun);
1357
1358	LogFunc(("[SD%RU8] Reset enter\n", uSD));
1359
1360	hdaR3StreamLock(pStream);
1361
1362	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1363	hdaR3StreamAsyncIOLock(pStream);
1364	# endif
1365	/* Make sure to remove the run bit before doing the actual stream reset. */
1366	HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_RUN;
1367
1368	hdaR3StreamReset(pThis, pStream, pStream->u8SD);
1369
1370	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1371	hdaR3StreamAsyncIOUnlock(pStream);
1372	# endif
1373	hdaR3StreamUnlock(pStream);
1374	}
1375	else
1376	{
1377	/*
1378	* We enter here to change DMA states only.
1379	*/
1380	if (fInRun != fRun)
1381	{
1382	Assert(!fReset && !fInReset);
1383	LogFunc(("[SD%RU8] State changed (fRun=%RTbool)\n", uSD, fRun));
1384
1385	hdaR3StreamLock(pStream);
1386
1387	int rc2;
1388
1389	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1390	if (fRun)
1391	rc2 = hdaR3StreamAsyncIOCreate(pStream);
1392
1393	hdaR3StreamAsyncIOLock(pStream);
1394	# endif
1395	if (fRun)
1396	{
1397	/* (Re-)initialize the stream with current values. */
1398	rc2 = hdaR3StreamInit(pStream, pStream->u8SD);
1399	AssertRC(rc2);
1400
1401	/* Remove the old stream from the device setup. */
1402	hdaR3RemoveStream(pThis, &pStream->State.Cfg);
1403
1404	/* Add the stream to the device setup. */
1405	rc2 = hdaR3AddStream(pThis, &pStream->State.Cfg);
1406	AssertRC(rc2);
1407	}
1408
1409	/* Enable/disable the stream. */
1410	rc2 = hdaR3StreamEnable(pStream, fRun /* fEnable */);
1411	AssertRC(rc2);
1412
1413	if (fRun)
1414	{
1415	/* Keep track of running streams. */
1416	pThis->cStreamsActive++;
1417
1418	/* (Re-)init the stream's period. */
1419	hdaR3StreamPeriodInit(&pStream->State.Period,
1420	pStream->u8SD, pStream->u16LVI, pStream->u32CBL, &pStream->State.Cfg);
1421
1422	/* Begin a new period for this stream. */
1423	rc2 = hdaR3StreamPeriodBegin(&pStream->State.Period, hdaWalClkGetCurrent(pThis)/* Use current wall clock time */);
1424	AssertRC(rc2);
1425
1426	rc2 = hdaR3TimerSet(pThis, pStream, TMTimerGet(pThis->pTimer[pStream->u8SD]) + pStream->State.cTransferTicks, false /* fForce */);
1427	AssertRC(rc2);
1428	}
1429	else
1430	{
1431	/* Keep track of running streams. */
1432	Assert(pThis->cStreamsActive);
1433	if (pThis->cStreamsActive)
1434	pThis->cStreamsActive--;
1435
1436	/* Make sure to (re-)schedule outstanding (delayed) interrupts. */
1437	hdaR3ReschedulePendingInterrupts(pThis);
1438
1439	/* Reset the period. */
1440	hdaR3StreamPeriodReset(&pStream->State.Period);
1441	}
1442
1443	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1444	hdaR3StreamAsyncIOUnlock(pStream);
1445	# endif
1446	/* Make sure to leave the lock before (eventually) starting the timer. */
1447	hdaR3StreamUnlock(pStream);
1448	}
1449	}
1450
1451	int rc2 = hdaRegWriteU24(pThis, iReg, u32Value);
1452	AssertRC(rc2);
1453
1454	DEVHDA_UNLOCK_BOTH(pThis, uSD);
1455	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1456	#else /* !IN_RING3 */
1457	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
1458	return VINF_IOM_R3_MMIO_WRITE;
1459	#endif /* IN_RING3 */
1460	}
1461
1462	static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1463	{
1464	#ifdef IN_RING3
1465	const uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, STS, iReg);
1466
1467	DEVHDA_LOCK_BOTH_RETURN(pThis, uSD, VINF_IOM_R3_MMIO_WRITE);
1468
1469	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
1470	if (!pStream)
1471	{
1472	AssertMsgFailed(("[SD%RU8] Warning: Writing SDSTS on non-attached stream (0x%x)\n",
1473	HDA_SD_NUM_FROM_REG(pThis, STS, iReg), u32Value));
1474
1475	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
1476	DEVHDA_UNLOCK_BOTH(pThis, uSD);
1477	return rc;
1478	}
1479
1480	hdaR3StreamLock(pStream);
1481
1482	uint32_t v = HDA_REG_IND(pThis, iReg);
1483
1484	/* Clear (zero) FIFOE, DESE and BCIS bits when writing 1 to it (6.2.33). */
1485	HDA_REG_IND(pThis, iReg) &= ~(u32Value & v);
1486
1487	/* Some guests tend to write SDnSTS even if the stream is not running.
1488	* So make sure to check if the RUN bit is set first. */
1489	const bool fRunning = pStream->State.fRunning;
1490
1491	Log3Func(("[SD%RU8] fRunning=%RTbool %R[sdsts]\n", pStream->u8SD, fRunning, v));
1492
1493	PHDASTREAMPERIOD pPeriod = &pStream->State.Period;
1494
1495	if (hdaR3StreamPeriodLock(pPeriod))
1496	{
1497	const bool fNeedsInterrupt = hdaR3StreamPeriodNeedsInterrupt(pPeriod);
1498	if (fNeedsInterrupt)
1499	hdaR3StreamPeriodReleaseInterrupt(pPeriod);
1500
1501	if (hdaR3StreamPeriodIsComplete(pPeriod))
1502	{
1503	/* Make sure to try to update the WALCLK register if a period is complete.
1504	* Use the maximum WALCLK value all (active) streams agree to. */
1505	const uint64_t uWalClkMax = hdaR3WalClkGetMax(pThis);
1506	if (uWalClkMax > hdaWalClkGetCurrent(pThis))
1507	hdaR3WalClkSet(pThis, uWalClkMax, false /* fForce */);
1508
1509	hdaR3StreamPeriodEnd(pPeriod);
1510
1511	if (fRunning)
1512	hdaR3StreamPeriodBegin(pPeriod, hdaWalClkGetCurrent(pThis) /* Use current wall clock time */);
1513	}
1514
1515	hdaR3StreamPeriodUnlock(pPeriod); /* Unlock before processing interrupt. */
1516	}
1517
1518	# ifndef LOG_ENABLED
1519	hdaProcessInterrupt(pThis);
1520	# else
1521	hdaProcessInterrupt(pThis, __FUNCTION__);
1522	# endif
1523
1524	const uint64_t tsNow = TMTimerGet(pThis->pTimer[uSD]);
1525	Assert(tsNow >= pStream->State.tsTransferLast);
1526
1527	const uint64_t cTicksElapsed = tsNow - pStream->State.tsTransferLast;
1528	# ifdef LOG_ENABLED
1529	const uint64_t cTicksTransferred = pStream->State.cbTransferProcessed * pStream->State.cTicksPerByte;
1530	# endif
1531
1532	uint64_t cTicksToNext = pStream->State.cTransferTicks;
1533	if (cTicksToNext) /* Only do any calculations if the stream currently is set up for transfers. */
1534	{
1535	Log3Func(("[SD%RU8] cTicksElapsed=%RU64, cTicksTransferred=%RU64, cTicksToNext=%RU64\n",
1536	pStream->u8SD, cTicksElapsed, cTicksTransferred, cTicksToNext));
1537
1538	Log3Func(("[SD%RU8] cbTransferProcessed=%RU32, cbTransferChunk=%RU32, cbTransferSize=%RU32\n",
1539	pStream->u8SD, pStream->State.cbTransferProcessed, pStream->State.cbTransferChunk, pStream->State.cbTransferSize));
1540
1541	if (cTicksElapsed <= cTicksToNext)
1542	{
1543	cTicksToNext = cTicksToNext - cTicksElapsed;
1544	}
1545	else /* Catch up. */
1546	{
1547	Log3Func(("[SD%RU8] Warning: Lagging behind (%RU64 ticks elapsed, maximum allowed is %RU64)\n",
1548	pStream->u8SD, cTicksElapsed, cTicksToNext));
1549
1550	LogRelMax2(64, ("HDA: Stream #%RU8 interrupt lagging behind (expected %uus, got %uus), trying to catch up ...\n",
1551	pStream->u8SD,
1552	(TMTimerGetFreq(pThis->pTimer[pStream->u8SD]) / pThis->u16TimerHz) / 1000,(tsNow - pStream->State.tsTransferLast) / 1000));
1553
1554	cTicksToNext = 0;
1555	}
1556
1557	Log3Func(("[SD%RU8] -> cTicksToNext=%RU64\n", pStream->u8SD, cTicksToNext));
1558
1559	/* Reset processed data counter. */
1560	pStream->State.cbTransferProcessed = 0;
1561	pStream->State.tsTransferNext = tsNow + cTicksToNext;
1562
1563	/* Only re-arm the timer if there were pending transfer interrupts left
1564	* -- it could happen that we land in here if a guest writes to SDnSTS
1565	* unconditionally. */
1566	if (pStream->State.cTransferPendingInterrupts)
1567	{
1568	pStream->State.cTransferPendingInterrupts--;
1569
1570	/* Re-arm the timer. */
1571	LogFunc(("Timer set SD%RU8\n", pStream->u8SD));
1572	hdaR3TimerSet(pThis, pStream, tsNow + cTicksToNext, false /* fForce */);
1573	}
1574	}
1575
1576	hdaR3StreamUnlock(pStream);
1577
1578	DEVHDA_UNLOCK_BOTH(pThis, uSD);
1579	return VINF_SUCCESS;
1580	#else /* IN_RING3 */
1581	RT_NOREF(pThis, iReg, u32Value);
1582	return VINF_IOM_R3_MMIO_WRITE;
1583	#endif /* !IN_RING3 */
1584	}
1585
1586	static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1587	{
1588	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1589
1590	if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
1591	{ /* nothing to do */ }
1592	else
1593	{
1594	uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, LVI, iReg);
1595	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
1596	if (pStream)
1597	{
1598	/** @todo Validate LVI. */
1599	pStream->u16LVI = u32Value;
1600	LogFunc(("[SD%RU8] Updating LVI to %RU16\n", uSD, pStream->u16LVI));
1601
1602	#ifdef HDA_USE_DMA_ACCESS_HANDLER
1603	if (hdaGetDirFromSD(uSD) == PDMAUDIODIR_OUT)
1604	{
1605	/* Try registering the DMA handlers.
1606	* As we can't be sure in which order LVI + BDL base are set, try registering in both routines. */
1607	if (hdaR3StreamRegisterDMAHandlers(pThis, pStream))
1608	LogFunc(("[SD%RU8] DMA logging enabled\n", pStream->u8SD));
1609	}
1610	#endif
1611	}
1612	else
1613	AssertMsgFailed(("[SD%RU8] Warning: Changing SDLVI on non-attached stream (0x%x)\n", uSD, u32Value));
1614
1615	int rc2 = hdaRegWriteU16(pThis, iReg, u32Value);
1616	AssertRC(rc2);
1617	}
1618
1619	DEVHDA_UNLOCK(pThis);
1620	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1621	}
1622
1623	static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1624	{
1625	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1626
1627	uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg);
1628
1629	if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_IN) /* FIFOW for input streams only. */
1630	{
1631	#ifndef IN_RING0
1632	LogRel(("HDA: Warning: Guest tried to write read-only FIFOW to output stream #%RU8, ignoring\n", uSD));
1633	DEVHDA_UNLOCK(pThis);
1634	return VINF_SUCCESS;
1635	#else
1636	DEVHDA_UNLOCK(pThis);
1637	return VINF_IOM_R3_MMIO_WRITE;
1638	#endif
1639	}
1640
1641	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg));
1642	if (!pStream)
1643	{
1644	AssertMsgFailed(("[SD%RU8] Warning: Changing FIFOW on non-attached stream (0x%x)\n", uSD, u32Value));
1645
1646	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
1647	DEVHDA_UNLOCK(pThis);
1648	return rc;
1649	}
1650
1651	uint32_t u32FIFOW = 0;
1652
1653	switch (u32Value)
1654	{
1655	case HDA_SDFIFOW_8B:
1656	case HDA_SDFIFOW_16B:
1657	case HDA_SDFIFOW_32B:
1658	u32FIFOW = u32Value;
1659	break;
1660	default:
1661	ASSERT_GUEST_LOGREL_MSG_FAILED(("Guest tried write unsupported FIFOW (0x%x) to stream #%RU8, defaulting to 32 bytes\n",
1662	u32Value, uSD));
1663	u32FIFOW = HDA_SDFIFOW_32B;
1664	break;
1665	}
1666
1667	if (u32FIFOW)
1668	{
1669	pStream->u16FIFOW = hdaSDFIFOWToBytes(u32FIFOW);
1670	LogFunc(("[SD%RU8] Updating FIFOW to %RU32 bytes\n", uSD, pStream->u16FIFOW));
1671
1672	int rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOW);
1673	AssertRC(rc2);
1674	}
1675
1676	DEVHDA_UNLOCK(pThis);
1677	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1678	}
1679
1680	/**
1681	* @note This method could be called for changing value on Output Streams only (ICH6 datasheet 18.2.39).
1682	*/
1683	static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1684	{
1685	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1686
1687	uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOS, iReg);
1688
1689	if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_OUT) /* FIFOS for output streams only. */
1690	{
1691	LogRel(("HDA: Warning: Guest tried to write read-only FIFOS to input stream #%RU8, ignoring\n", uSD));
1692
1693	DEVHDA_UNLOCK(pThis);
1694	return VINF_SUCCESS;
1695	}
1696
1697	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
1698	if (!pStream)
1699	{
1700	AssertMsgFailed(("[SD%RU8] Warning: Changing FIFOS on non-attached stream (0x%x)\n", uSD, u32Value));
1701
1702	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
1703	DEVHDA_UNLOCK(pThis);
1704	return rc;
1705	}
1706
1707	uint32_t u32FIFOS = 0;
1708
1709	switch(u32Value)
1710	{
1711	case HDA_SDOFIFO_16B:
1712	case HDA_SDOFIFO_32B:
1713	case HDA_SDOFIFO_64B:
1714	case HDA_SDOFIFO_128B:
1715	case HDA_SDOFIFO_192B:
1716	case HDA_SDOFIFO_256B:
1717	u32FIFOS = u32Value;
1718	break;
1719
1720	default:
1721	ASSERT_GUEST_LOGREL_MSG_FAILED(("Guest tried write unsupported FIFOS (0x%x) to stream #%RU8, defaulting to 192 bytes\n",
1722	u32Value, uSD));
1723	u32FIFOS = HDA_SDOFIFO_192B;
1724	break;
1725	}
1726
1727	if (u32FIFOS)
1728	{
1729	pStream->u16FIFOS = u32FIFOS + 1;
1730	LogFunc(("[SD%RU8] Updating FIFOS to %RU32 bytes\n", uSD, pStream->u16FIFOS));
1731
1732	int rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOS);
1733	AssertRC(rc2);
1734	}
1735
1736	DEVHDA_UNLOCK(pThis);
1737	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1738	}
1739
1740	#ifdef IN_RING3
1741
1742	/**
1743	* Adds an audio output stream to the device setup using the given configuration.
1744	*
1745	* @returns IPRT status code.
1746	* @param pThis Device state.
1747	* @param pCfg Stream configuration to use for adding a stream.
1748	*/
1749	static int hdaR3AddStreamOut(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1750	{
1751	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1752	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1753
1754	AssertReturn(pCfg->enmDir == PDMAUDIODIR_OUT, VERR_INVALID_PARAMETER);
1755
1756	LogFlowFunc(("Stream=%s\n", pCfg->szName));
1757
1758	int rc = VINF_SUCCESS;
1759
1760	bool fUseFront = true; /* Always use front out by default. */
1761	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1762	bool fUseRear;
1763	bool fUseCenter;
1764	bool fUseLFE;
1765
1766	fUseRear = fUseCenter = fUseLFE = false;
1767
1768	/*
1769	* Use commonly used setups for speaker configurations.
1770	*/
1771
1772	/** @todo Make the following configurable through mixer API and/or CFGM? */
1773	switch (pCfg->Props.cChannels)
1774	{
1775	case 3: /* 2.1: Front (Stereo) + LFE. */
1776	{
1777	fUseLFE = true;
1778	break;
1779	}
1780
1781	case 4: /* Quadrophonic: Front (Stereo) + Rear (Stereo). */
1782	{
1783	fUseRear = true;
1784	break;
1785	}
1786
1787	case 5: /* 4.1: Front (Stereo) + Rear (Stereo) + LFE. */
1788	{
1789	fUseRear = true;
1790	fUseLFE = true;
1791	break;
1792	}
1793
1794	case 6: /* 5.1: Front (Stereo) + Rear (Stereo) + Center/LFE. */
1795	{
1796	fUseRear = true;
1797	fUseCenter = true;
1798	fUseLFE = true;
1799	break;
1800	}
1801
1802	default: /* Unknown; fall back to 2 front channels (stereo). */
1803	{
1804	rc = VERR_NOT_SUPPORTED;
1805	break;
1806	}
1807	}
1808	# else /* !VBOX_WITH_AUDIO_HDA_51_SURROUND */
1809	/* Only support mono or stereo channels. */
1810	if ( pCfg->Props.cChannels != 1 /* Mono */
1811	&& pCfg->Props.cChannels != 2 /* Stereo */)
1812	{
1813	rc = VERR_NOT_SUPPORTED;
1814	}
1815	# endif /* !VBOX_WITH_AUDIO_HDA_51_SURROUND */
1816
1817	if (rc == VERR_NOT_SUPPORTED)
1818	{
1819	LogRel2(("HDA: Warning: Unsupported channel count (%RU8), falling back to stereo channels (2)\n", pCfg->Props.cChannels));
1820
1821	/* Fall back to 2 channels (see below in fUseFront block). */
1822	rc = VINF_SUCCESS;
1823	}
1824
1825	do
1826	{
1827	if (RT_FAILURE(rc))
1828	break;
1829
1830	if (fUseFront)
1831	{
1832	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Front");
1833
1834	pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_FRONT;
1835	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1836
1837	pCfg->Props.cChannels = 2;
1838	pCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pCfg->Props.cBytes, pCfg->Props.cChannels);
1839
1840	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT, pCfg);
1841	}
1842
1843	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1844	if ( RT_SUCCESS(rc)
1845	&& (fUseCenter \|\| fUseLFE))
1846	{
1847	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Center/LFE");
1848
1849	pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_CENTER_LFE;
1850	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1851
1852	pCfg->Props.cChannels = (fUseCenter && fUseLFE) ? 2 : 1;
1853	pCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pCfg->Props.cBits, pCfg->Props.cChannels);
1854
1855	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE, pCfg);
1856	}
1857
1858	if ( RT_SUCCESS(rc)
1859	&& fUseRear)
1860	{
1861	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Rear");
1862
1863	pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_REAR;
1864	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1865
1866	pCfg->Props.cChannels = 2;
1867	pCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pCfg->Props.cBits, pCfg->Props.cChannels);
1868
1869	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR, pCfg);
1870	}
1871	# endif /* VBOX_WITH_AUDIO_HDA_51_SURROUND */
1872
1873	} while (0);
1874
1875	LogFlowFuncLeaveRC(rc);
1876	return rc;
1877	}
1878
1879	/**
1880	* Adds an audio input stream to the device setup using the given configuration.
1881	*
1882	* @returns IPRT status code.
1883	* @param pThis Device state.
1884	* @param pCfg Stream configuration to use for adding a stream.
1885	*/
1886	static int hdaR3AddStreamIn(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1887	{
1888	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1889	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1890
1891	AssertReturn(pCfg->enmDir == PDMAUDIODIR_IN, VERR_INVALID_PARAMETER);
1892
1893	LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Source));
1894
1895	int rc;
1896
1897	switch (pCfg->DestSource.Source)
1898	{
1899	case PDMAUDIORECSOURCE_LINE:
1900	{
1901	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN, pCfg);
1902	break;
1903	}
1904	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
1905	case PDMAUDIORECSOURCE_MIC:
1906	{
1907	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN, pCfg);
1908	break;
1909	}
1910	# endif
1911	default:
1912	rc = VERR_NOT_SUPPORTED;
1913	break;
1914	}
1915
1916	LogFlowFuncLeaveRC(rc);
1917	return rc;
1918	}
1919
1920	/**
1921	* Adds an audio stream to the device setup using the given configuration.
1922	*
1923	* @returns IPRT status code.
1924	* @param pThis Device state.
1925	* @param pCfg Stream configuration to use for adding a stream.
1926	*/
1927	static int hdaR3AddStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1928	{
1929	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1930	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1931
1932	int rc;
1933
1934	LogFlowFuncEnter();
1935
1936	switch (pCfg->enmDir)
1937	{
1938	case PDMAUDIODIR_OUT:
1939	rc = hdaR3AddStreamOut(pThis, pCfg);
1940	break;
1941
1942	case PDMAUDIODIR_IN:
1943	rc = hdaR3AddStreamIn(pThis, pCfg);
1944	break;
1945
1946	default:
1947	rc = VERR_NOT_SUPPORTED;
1948	AssertFailed();
1949	break;
1950	}
1951
1952	LogFlowFunc(("Returning %Rrc\n", rc));
1953
1954	return rc;
1955	}
1956
1957	/**
1958	* Removes an audio stream from the device setup using the given configuration.
1959	*
1960	* @returns IPRT status code.
1961	* @param pThis Device state.
1962	* @param pCfg Stream configuration to use for removing a stream.
1963	*/
1964	static int hdaR3RemoveStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1965	{
1966	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1967	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1968
1969	int rc = VINF_SUCCESS;
1970
1971	PDMAUDIOMIXERCTL enmMixerCtl = PDMAUDIOMIXERCTL_UNKNOWN;
1972	switch (pCfg->enmDir)
1973	{
1974	case PDMAUDIODIR_IN:
1975	{
1976	LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Source));
1977
1978	switch (pCfg->DestSource.Source)
1979	{
1980	case PDMAUDIORECSOURCE_LINE: enmMixerCtl = PDMAUDIOMIXERCTL_LINE_IN; break;
1981	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
1982	case PDMAUDIORECSOURCE_MIC: enmMixerCtl = PDMAUDIOMIXERCTL_MIC_IN; break;
1983	# endif
1984	default:
1985	rc = VERR_NOT_SUPPORTED;
1986	break;
1987	}
1988
1989	break;
1990	}
1991
1992	case PDMAUDIODIR_OUT:
1993	{
1994	LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Dest));
1995
1996	switch (pCfg->DestSource.Dest)
1997	{
1998	case PDMAUDIOPLAYBACKDEST_FRONT: enmMixerCtl = PDMAUDIOMIXERCTL_FRONT; break;
1999	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2000	case PDMAUDIOPLAYBACKDEST_CENTER_LFE: enmMixerCtl = PDMAUDIOMIXERCTL_CENTER_LFE; break;
2001	case PDMAUDIOPLAYBACKDEST_REAR: enmMixerCtl = PDMAUDIOMIXERCTL_REAR; break;
2002	# endif
2003	default:
2004	rc = VERR_NOT_SUPPORTED;
2005	break;
2006	}
2007	break;
2008	}
2009
2010	default:
2011	rc = VERR_NOT_SUPPORTED;
2012	break;
2013	}
2014
2015	if (RT_SUCCESS(rc))
2016	rc = hdaCodecRemoveStream(pThis->pCodec, enmMixerCtl);
2017
2018	LogFlowFuncLeaveRC(rc);
2019	return rc;
2020	}
2021	#endif /* IN_RING3 */
2022
2023	static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2024	{
2025	DEVHDA_LOCK(pThis);
2026
2027	# ifdef LOG_ENABLED
2028	if (!hdaGetStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FMT, iReg)))
2029	LogFunc(("[SD%RU8] Warning: Changing SDFMT on non-attached stream (0x%x)\n",
2030	HDA_SD_NUM_FROM_REG(pThis, FMT, iReg), u32Value));
2031	# endif
2032
2033
2034	/* Write the wanted stream format into the register in any case.
2035	*
2036	* This is important for e.g. MacOS guests, as those try to initialize streams which are not reported
2037	* by the device emulation (wants 4 channels, only have 2 channels at the moment).
2038	*
2039	* When ignoring those (invalid) formats, this leads to MacOS thinking that the device is malfunctioning
2040	* and therefore disabling the device completely. */
2041	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
2042	AssertRC(rc);
2043
2044	DEVHDA_UNLOCK(pThis);
2045	return VINF_SUCCESS; /* Never return failure. */
2046	}
2047
2048	/* Note: Will be called for both, BDPL and BDPU, registers. */
2049	DECLINLINE(int) hdaRegWriteSDBDPX(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value, uint8_t uSD)
2050	{
2051	#ifdef IN_RING3
2052	DEVHDA_LOCK(pThis);
2053
2054	int rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2055	AssertRC(rc2);
2056
2057	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
2058	if (!pStream)
2059	{
2060	DEVHDA_UNLOCK(pThis);
2061	return VINF_SUCCESS;
2062	}
2063
2064	/* Update BDL base. */
2065	pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, uSD),
2066	HDA_STREAM_REG(pThis, BDPU, uSD));
2067
2068	# ifdef HDA_USE_DMA_ACCESS_HANDLER
2069	if (hdaGetDirFromSD(uSD) == PDMAUDIODIR_OUT)
2070	{
2071	/* Try registering the DMA handlers.
2072	* As we can't be sure in which order LVI + BDL base are set, try registering in both routines. */
2073	if (hdaR3StreamRegisterDMAHandlers(pThis, pStream))
2074	LogFunc(("[SD%RU8] DMA logging enabled\n", pStream->u8SD));
2075	}
2076	# endif
2077
2078	LogFlowFunc(("[SD%RU8] BDLBase=0x%x\n", pStream->u8SD, pStream->u64BDLBase));
2079
2080	DEVHDA_UNLOCK(pThis);
2081	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2082	#else /* !IN_RING3 */
2083	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value); RT_NOREF_PV(uSD);
2084	return VINF_IOM_R3_MMIO_WRITE;
2085	#endif /* IN_RING3 */
2086	}
2087
2088	static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2089	{
2090	return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPL, iReg));
2091	}
2092
2093	static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2094	{
2095	return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPU, iReg));
2096	}
2097
2098	static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2099	{
2100	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
2101
2102	/* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
2103	if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2104	\|\| (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA))
2105	{
2106	HDA_REG(pThis, IRS) = HDA_IRS_ICB; /* busy */
2107	}
2108
2109	int rc = hdaRegReadU32(pThis, iReg, pu32Value);
2110	DEVHDA_UNLOCK(pThis);
2111
2112	return rc;
2113	}
2114
2115	static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2116	{
2117	RT_NOREF_PV(iReg);
2118	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2119
2120	/*
2121	* If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
2122	* write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
2123	*/
2124	if ( (u32Value & HDA_IRS_ICB)
2125	&& !(HDA_REG(pThis, IRS) & HDA_IRS_ICB))
2126	{
2127	#ifdef IN_RING3
2128	uint32_t uCmd = HDA_REG(pThis, IC);
2129
2130	if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
2131	{
2132	DEVHDA_UNLOCK(pThis);
2133
2134	/*
2135	* 3.4.3: Defines behavior of immediate Command status register.
2136	*/
2137	LogRel(("HDA: Guest attempted process immediate verb (%x) with active CORB\n", uCmd));
2138	return VINF_SUCCESS;
2139	}
2140
2141	HDA_REG(pThis, IRS) = HDA_IRS_ICB; /* busy */
2142
2143	uint64_t uResp;
2144	int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec,
2145	HDA_CODEC_CMD(uCmd, 0 /* LUN */), &uResp);
2146	if (RT_FAILURE(rc2))
2147	LogFunc(("Codec lookup failed with rc2=%Rrc\n", rc2));
2148
2149	HDA_REG(pThis, IR) = (uint32_t)uResp; /** @todo r=andy Do we need a 64-bit response? */
2150	HDA_REG(pThis, IRS) = HDA_IRS_IRV; /* result is ready */
2151	/** @todo r=michaln We just set the IRS value, why are we clearing unset bits? */
2152	HDA_REG(pThis, IRS) &= ~HDA_IRS_ICB; /* busy is clear */
2153
2154	DEVHDA_UNLOCK(pThis);
2155	return VINF_SUCCESS;
2156	#else /* !IN_RING3 */
2157	DEVHDA_UNLOCK(pThis);
2158	return VINF_IOM_R3_MMIO_WRITE;
2159	#endif /* !IN_RING3 */
2160	}
2161
2162	/*
2163	* Once the guest read the response, it should clear the IRV bit of the IRS register.
2164	*/
2165	HDA_REG(pThis, IRS) &= ~(u32Value & HDA_IRS_IRV);
2166
2167	DEVHDA_UNLOCK(pThis);
2168	return VINF_SUCCESS;
2169	}
2170
2171	static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2172	{
2173	RT_NOREF(iReg);
2174	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2175
2176	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
2177	{
2178	LogFunc(("CORB DMA (still) running, skipping\n"));
2179
2180	DEVHDA_UNLOCK(pThis);
2181	return VINF_SUCCESS;
2182	}
2183
2184	if (u32Value & HDA_RIRBWP_RST)
2185	{
2186	/* Do a RIRB reset. */
2187	if (pThis->cbRirbBuf)
2188	{
2189	Assert(pThis->pu64RirbBuf);
2190	RT_BZERO((void *)pThis->pu64RirbBuf, pThis->cbRirbBuf);
2191	}
2192
2193	LogRel2(("HDA: RIRB reset\n"));
2194
2195	HDA_REG(pThis, RIRBWP) = 0;
2196	}
2197
2198	/* The remaining bits are O, see 6.2.22. */
2199
2200	DEVHDA_UNLOCK(pThis);
2201	return VINF_SUCCESS;
2202	}
2203
2204	static int hdaRegWriteRINTCNT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2205	{
2206	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2207
2208	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
2209	{
2210	LogFunc(("CORB DMA is (still) running, skipping\n"));
2211
2212	DEVHDA_UNLOCK(pThis);
2213	return VINF_SUCCESS;
2214	}
2215
2216	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
2217	AssertRC(rc);
2218
2219	LogFunc(("Response interrupt count is now %RU8\n", HDA_REG(pThis, RINTCNT) & 0xFF));
2220
2221	DEVHDA_UNLOCK(pThis);
2222	return rc;
2223	}
2224
2225	static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2226	{
2227	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2228	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2229
2230	int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2231	AssertRCSuccess(rc);
2232
2233	switch (iReg)
2234	{
2235	case HDA_REG_CORBLBASE:
2236	pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
2237	pThis->u64CORBBase \|= pThis->au32Regs[iRegMem];
2238	break;
2239	case HDA_REG_CORBUBASE:
2240	pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
2241	pThis->u64CORBBase \|= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2242	break;
2243	case HDA_REG_RIRBLBASE:
2244	pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
2245	pThis->u64RIRBBase \|= pThis->au32Regs[iRegMem];
2246	break;
2247	case HDA_REG_RIRBUBASE:
2248	pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
2249	pThis->u64RIRBBase \|= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2250	break;
2251	case HDA_REG_DPLBASE:
2252	{
2253	pThis->u64DPBase = pThis->au32Regs[iRegMem] & DPBASE_ADDR_MASK;
2254	Assert(pThis->u64DPBase % 128 == 0); /* Must be 128-byte aligned. */
2255
2256	/* Also make sure to handle the DMA position enable bit. */
2257	pThis->fDMAPosition = pThis->au32Regs[iRegMem] & RT_BIT_32(0);
2258	LogRel(("HDA: %s DMA position buffer\n", pThis->fDMAPosition ? "Enabled" : "Disabled"));
2259	break;
2260	}
2261	case HDA_REG_DPUBASE:
2262	pThis->u64DPBase = RT_MAKE_U64(RT_LO_U32(pThis->u64DPBase) & DPBASE_ADDR_MASK, pThis->au32Regs[iRegMem]);
2263	break;
2264	default:
2265	AssertMsgFailed(("Invalid index\n"));
2266	break;
2267	}
2268
2269	LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
2270	pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
2271
2272	DEVHDA_UNLOCK(pThis);
2273	return rc;
2274	}
2275
2276	static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2277	{
2278	RT_NOREF_PV(iReg);
2279	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2280
2281	uint8_t v = HDA_REG(pThis, RIRBSTS);
2282	HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
2283
2284	#ifndef LOG_ENABLED
2285	int rc = hdaProcessInterrupt(pThis);
2286	#else
2287	int rc = hdaProcessInterrupt(pThis, __FUNCTION__);
2288	#endif
2289
2290	DEVHDA_UNLOCK(pThis);
2291	return rc;
2292	}
2293
2294	#ifdef IN_RING3
2295
2296	/**
2297	* Retrieves a corresponding sink for a given mixer control.
2298	* Returns NULL if no sink is found.
2299	*
2300	* @return PHDAMIXERSINK
2301	* @param pThis HDA state.
2302	* @param enmMixerCtl Mixer control to get the corresponding sink for.
2303	*/
2304	static PHDAMIXERSINK hdaR3MixerControlToSink(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
2305	{
2306	PHDAMIXERSINK pSink;
2307
2308	switch (enmMixerCtl)
2309	{
2310	case PDMAUDIOMIXERCTL_VOLUME_MASTER:
2311	/* Fall through is intentional. */
2312	case PDMAUDIOMIXERCTL_FRONT:
2313	pSink = &pThis->SinkFront;
2314	break;
2315	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2316	case PDMAUDIOMIXERCTL_CENTER_LFE:
2317	pSink = &pThis->SinkCenterLFE;
2318	break;
2319	case PDMAUDIOMIXERCTL_REAR:
2320	pSink = &pThis->SinkRear;
2321	break;
2322	# endif
2323	case PDMAUDIOMIXERCTL_LINE_IN:
2324	pSink = &pThis->SinkLineIn;
2325	break;
2326	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2327	case PDMAUDIOMIXERCTL_MIC_IN:
2328	pSink = &pThis->SinkMicIn;
2329	break;
2330	# endif
2331	default:
2332	pSink = NULL;
2333	AssertMsgFailed(("Unhandled mixer control\n"));
2334	break;
2335	}
2336
2337	return pSink;
2338	}
2339
2340	/**
2341	* Adds a specific HDA driver to the driver chain.
2342	*
2343	* @return IPRT status code.
2344	* @param pThis HDA state.
2345	* @param pDrv HDA driver to add.
2346	*/
2347	static int hdaR3MixerAddDrv(PHDASTATE pThis, PHDADRIVER pDrv)
2348	{
2349	int rc = VINF_SUCCESS;
2350
2351	PHDASTREAM pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkLineIn);
2352	if ( pStream
2353	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2354	{
2355	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkLineIn.pMixSink, &pStream->State.Cfg, pDrv);
2356	if (RT_SUCCESS(rc))
2357	rc = rc2;
2358	}
2359
2360	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2361	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkMicIn);
2362	if ( pStream
2363	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2364	{
2365	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkMicIn.pMixSink, &pStream->State.Cfg, pDrv);
2366	if (RT_SUCCESS(rc))
2367	rc = rc2;
2368	}
2369	# endif
2370
2371	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkFront);
2372	if ( pStream
2373	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2374	{
2375	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkFront.pMixSink, &pStream->State.Cfg, pDrv);
2376	if (RT_SUCCESS(rc))
2377	rc = rc2;
2378	}
2379
2380	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2381	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkCenterLFE);
2382	if ( pStream
2383	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2384	{
2385	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkCenterLFE.pMixSink, &pStream->State.Cfg, pDrv);
2386	if (RT_SUCCESS(rc))
2387	rc = rc2;
2388	}
2389
2390	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkRear);
2391	if ( pStream
2392	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2393	{
2394	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkRear.pMixSink, &pStream->State.Cfg, pDrv);
2395	if (RT_SUCCESS(rc))
2396	rc = rc2;
2397	}
2398	# endif
2399
2400	return rc;
2401	}
2402
2403	/**
2404	* Removes a specific HDA driver from the driver chain and destroys its
2405	* associated streams.
2406	*
2407	* @param pThis HDA state.
2408	* @param pDrv HDA driver to remove.
2409	*/
2410	static void hdaR3MixerRemoveDrv(PHDASTATE pThis, PHDADRIVER pDrv)
2411	{
2412	AssertPtrReturnVoid(pThis);
2413	AssertPtrReturnVoid(pDrv);
2414
2415	if (pDrv->LineIn.pMixStrm)
2416	{
2417	if (AudioMixerSinkGetRecordingSource(pThis->SinkLineIn.pMixSink) == pDrv->LineIn.pMixStrm)
2418	AudioMixerSinkSetRecordingSource(pThis->SinkLineIn.pMixSink, NULL);
2419
2420	AudioMixerSinkRemoveStream(pThis->SinkLineIn.pMixSink, pDrv->LineIn.pMixStrm);
2421	AudioMixerStreamDestroy(pDrv->LineIn.pMixStrm);
2422	pDrv->LineIn.pMixStrm = NULL;
2423	}
2424
2425	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2426	if (pDrv->MicIn.pMixStrm)
2427	{
2428	if (AudioMixerSinkGetRecordingSource(pThis->SinkMicIn.pMixSink) == pDrv->MicIn.pMixStrm)
2429	AudioMixerSinkSetRecordingSource(&pThis->SinkMicIn.pMixSink, NULL);
2430
2431	AudioMixerSinkRemoveStream(pThis->SinkMicIn.pMixSink, pDrv->MicIn.pMixStrm);
2432	AudioMixerStreamDestroy(pDrv->MicIn.pMixStrm);
2433	pDrv->MicIn.pMixStrm = NULL;
2434	}
2435	# endif
2436
2437	if (pDrv->Front.pMixStrm)
2438	{
2439	AudioMixerSinkRemoveStream(pThis->SinkFront.pMixSink, pDrv->Front.pMixStrm);
2440	AudioMixerStreamDestroy(pDrv->Front.pMixStrm);
2441	pDrv->Front.pMixStrm = NULL;
2442	}
2443
2444	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2445	if (pDrv->CenterLFE.pMixStrm)
2446	{
2447	AudioMixerSinkRemoveStream(pThis->SinkCenterLFE.pMixSink, pDrv->CenterLFE.pMixStrm);
2448	AudioMixerStreamDestroy(pDrv->CenterLFE.pMixStrm);
2449	pDrv->CenterLFE.pMixStrm = NULL;
2450	}
2451
2452	if (pDrv->Rear.pMixStrm)
2453	{
2454	AudioMixerSinkRemoveStream(pThis->SinkRear.pMixSink, pDrv->Rear.pMixStrm);
2455	AudioMixerStreamDestroy(pDrv->Rear.pMixStrm);
2456	pDrv->Rear.pMixStrm = NULL;
2457	}
2458	# endif
2459
2460	RTListNodeRemove(&pDrv->Node);
2461	}
2462
2463	/**
2464	* Adds a driver stream to a specific mixer sink.
2465	*
2466	* @returns IPRT status code (ignored by caller).
2467	* @param pThis HDA state.
2468	* @param pMixSink Audio mixer sink to add audio streams to.
2469	* @param pCfg Audio stream configuration to use for the audio streams to add.
2470	* @param pDrv Driver stream to add.
2471	*/
2472	static int hdaR3MixerAddDrvStream(PHDASTATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg, PHDADRIVER pDrv)
2473	{
2474	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2475	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
2476	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2477
2478	LogFunc(("Sink=%s, Stream=%s\n", pMixSink->pszName, pCfg->szName));
2479
2480	PPDMAUDIOSTREAMCFG pStreamCfg = DrvAudioHlpStreamCfgDup(pCfg);
2481	if (!pStreamCfg)
2482	return VERR_NO_MEMORY;
2483
2484	LogFunc(("[LUN#%RU8] %s\n", pDrv->uLUN, pStreamCfg->szName));
2485
2486	int rc = VINF_SUCCESS;
2487
2488	PHDADRIVERSTREAM pDrvStream = NULL;
2489
2490	if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
2491	{
2492	LogFunc(("enmRecSource=%d\n", pStreamCfg->DestSource.Source));
2493
2494	switch (pStreamCfg->DestSource.Source)
2495	{
2496	case PDMAUDIORECSOURCE_LINE:
2497	pDrvStream = &pDrv->LineIn;
2498	break;
2499	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2500	case PDMAUDIORECSOURCE_MIC:
2501	pDrvStream = &pDrv->MicIn;
2502	break;
2503	# endif
2504	default:
2505	rc = VERR_NOT_SUPPORTED;
2506	break;
2507	}
2508	}
2509	else if (pStreamCfg->enmDir == PDMAUDIODIR_OUT)
2510	{
2511	LogFunc(("enmPlaybackDest=%d\n", pStreamCfg->DestSource.Dest));
2512
2513	switch (pStreamCfg->DestSource.Dest)
2514	{
2515	case PDMAUDIOPLAYBACKDEST_FRONT:
2516	pDrvStream = &pDrv->Front;
2517	break;
2518	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2519	case PDMAUDIOPLAYBACKDEST_CENTER_LFE:
2520	pDrvStream = &pDrv->CenterLFE;
2521	break;
2522	case PDMAUDIOPLAYBACKDEST_REAR:
2523	pDrvStream = &pDrv->Rear;
2524	break;
2525	# endif
2526	default:
2527	rc = VERR_NOT_SUPPORTED;
2528	break;
2529	}
2530	}
2531	else
2532	rc = VERR_NOT_SUPPORTED;
2533
2534	if (RT_SUCCESS(rc))
2535	{
2536	AssertPtr(pDrvStream);
2537	AssertMsg(pDrvStream->pMixStrm == NULL, ("[LUN#%RU8] Driver stream already present when it must not\n", pDrv->uLUN));
2538
2539	PAUDMIXSTREAM pMixStrm;
2540	rc = AudioMixerSinkCreateStream(pMixSink, pDrv->pConnector, pStreamCfg, 0 /* fFlags */, &pMixStrm);
2541	LogFlowFunc(("LUN#%RU8: Created stream \"%s\" for sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
2542	if (RT_SUCCESS(rc))
2543	{
2544	rc = AudioMixerSinkAddStream(pMixSink, pMixStrm);
2545	LogFlowFunc(("LUN#%RU8: Added stream \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
2546	if (RT_SUCCESS(rc))
2547	{
2548	/* If this is an input stream, always set the latest (added) stream
2549	* as the recording source.
2550	* @todo Make the recording source dynamic (CFGM?). */
2551	if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
2552	{
2553	PDMAUDIOBACKENDCFG Cfg;
2554	rc = pDrv->pConnector->pfnGetConfig(pDrv->pConnector, &Cfg);
2555	if (RT_SUCCESS(rc))
2556	{
2557	if (Cfg.cMaxStreamsIn) /* At least one input source available? */
2558	{
2559	rc = AudioMixerSinkSetRecordingSource(pMixSink, pMixStrm);
2560	LogFlowFunc(("LUN#%RU8: Recording source for '%s' -> '%s', rc=%Rrc\n",
2561	pDrv->uLUN, pStreamCfg->szName, Cfg.szName, rc));
2562
2563	if (RT_SUCCESS(rc))
2564	LogRel(("HDA: Set recording source for '%s' to '%s'\n",
2565	pStreamCfg->szName, Cfg.szName));
2566	}
2567	else
2568	LogRel(("HDA: Backend '%s' currently is not offering any recording source for '%s'\n",
2569	Cfg.szName, pStreamCfg->szName));
2570	}
2571	else if (RT_FAILURE(rc))
2572	LogFunc(("LUN#%RU8: Unable to retrieve backend configuration for '%s', rc=%Rrc\n",
2573	pDrv->uLUN, pStreamCfg->szName, rc));
2574	}
2575	}
2576	}
2577
2578	if (RT_SUCCESS(rc))
2579	pDrvStream->pMixStrm = pMixStrm;
2580	}
2581
2582	if (pStreamCfg)
2583	{
2584	RTMemFree(pStreamCfg);
2585	pStreamCfg = NULL;
2586	}
2587
2588	LogFlowFuncLeaveRC(rc);
2589	return rc;
2590	}
2591
2592	/**
2593	* Adds all current driver streams to a specific mixer sink.
2594	*
2595	* @returns IPRT status code.
2596	* @param pThis HDA state.
2597	* @param pMixSink Audio mixer sink to add stream to.
2598	* @param pCfg Audio stream configuration to use for the audio streams to add.
2599	*/
2600	static int hdaR3MixerAddDrvStreams(PHDASTATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg)
2601	{
2602	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2603	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
2604	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2605
2606	LogFunc(("Sink=%s, Stream=%s\n", pMixSink->pszName, pCfg->szName));
2607
2608	if (!DrvAudioHlpStreamCfgIsValid(pCfg))
2609	return VERR_INVALID_PARAMETER;
2610
2611	int rc = AudioMixerSinkSetFormat(pMixSink, &pCfg->Props);
2612	if (RT_FAILURE(rc))
2613	return rc;
2614
2615	PHDADRIVER pDrv;
2616	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2617	{
2618	int rc2 = hdaR3MixerAddDrvStream(pThis, pMixSink, pCfg, pDrv);
2619	if (RT_FAILURE(rc2))
2620	LogFunc(("Attaching stream failed with %Rrc\n", rc2));
2621
2622	/* Do not pass failure to rc here, as there might be drivers which aren't
2623	* configured / ready yet. */
2624	}
2625
2626	return rc;
2627	}
2628
2629	/**
2630	* @interface_method_impl{HDACODEC,pfnCbMixerAddStream}
2631	*
2632	* Adds a new audio stream to a specific mixer control.
2633	*
2634	* Depending on the mixer control the stream then gets assigned to one of the internal
2635	* mixer sinks, which in turn then handle the mixing of all connected streams to that sink.
2636	*
2637	* @return IPRT status code.
2638	* @param pThis HDA state.
2639	* @param enmMixerCtl Mixer control to assign new stream to.
2640	* @param pCfg Stream configuration for the new stream.
2641	*/
2642	static DECLCALLBACK(int) hdaR3MixerAddStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOSTREAMCFG pCfg)
2643	{
2644	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2645	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2646
2647	int rc;
2648
2649	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2650	if (pSink)
2651	{
2652	rc = hdaR3MixerAddDrvStreams(pThis, pSink->pMixSink, pCfg);
2653
2654	AssertPtr(pSink->pMixSink);
2655	LogFlowFunc(("Sink=%s, Mixer control=%s\n", pSink->pMixSink->pszName, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl)));
2656	}
2657	else
2658	rc = VERR_NOT_FOUND;
2659
2660	LogFlowFuncLeaveRC(rc);
2661	return rc;
2662	}
2663
2664	/**
2665	* @interface_method_impl{HDACODEC,pfnCbMixerRemoveStream}
2666	*
2667	* Removes a specified mixer control from the HDA's mixer.
2668	*
2669	* @return IPRT status code.
2670	* @param pThis HDA state.
2671	* @param enmMixerCtl Mixer control to remove.
2672	*
2673	* @remarks Can be called as a callback by the HDA codec.
2674	*/
2675	static DECLCALLBACK(int) hdaR3MixerRemoveStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
2676	{
2677	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2678
2679	int rc;
2680
2681	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2682	if (pSink)
2683	{
2684	PHDADRIVER pDrv;
2685	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2686	{
2687	PAUDMIXSTREAM pMixStream = NULL;
2688	switch (enmMixerCtl)
2689	{
2690	/*
2691	* Input.
2692	*/
2693	case PDMAUDIOMIXERCTL_LINE_IN:
2694	pMixStream = pDrv->LineIn.pMixStrm;
2695	pDrv->LineIn.pMixStrm = NULL;
2696	break;
2697	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2698	case PDMAUDIOMIXERCTL_MIC_IN:
2699	pMixStream = pDrv->MicIn.pMixStrm;
2700	pDrv->MicIn.pMixStrm = NULL;
2701	break;
2702	# endif
2703	/*
2704	* Output.
2705	*/
2706	case PDMAUDIOMIXERCTL_FRONT:
2707	pMixStream = pDrv->Front.pMixStrm;
2708	pDrv->Front.pMixStrm = NULL;
2709	break;
2710	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2711	case PDMAUDIOMIXERCTL_CENTER_LFE:
2712	pMixStream = pDrv->CenterLFE.pMixStrm;
2713	pDrv->CenterLFE.pMixStrm = NULL;
2714	break;
2715	case PDMAUDIOMIXERCTL_REAR:
2716	pMixStream = pDrv->Rear.pMixStrm;
2717	pDrv->Rear.pMixStrm = NULL;
2718	break;
2719	# endif
2720	default:
2721	AssertMsgFailed(("Mixer control %d not implemented\n", enmMixerCtl));
2722	break;
2723	}
2724
2725	if (pMixStream)
2726	{
2727	AudioMixerSinkRemoveStream(pSink->pMixSink, pMixStream);
2728	AudioMixerStreamDestroy(pMixStream);
2729
2730	pMixStream = NULL;
2731	}
2732	}
2733
2734	AudioMixerSinkRemoveAllStreams(pSink->pMixSink);
2735	rc = VINF_SUCCESS;
2736	}
2737	else
2738	rc = VERR_NOT_FOUND;
2739
2740	LogFunc(("Mixer control=%s, rc=%Rrc\n", DrvAudioHlpAudMixerCtlToStr(enmMixerCtl), rc));
2741	return rc;
2742	}
2743
2744	/**
2745	* @interface_method_impl{HDACODEC,pfnCbMixerControl}
2746	*
2747	* Controls an input / output converter widget, that is, which converter is connected
2748	* to which stream (and channel).
2749	*
2750	* @returns IPRT status code.
2751	* @param pThis HDA State.
2752	* @param enmMixerCtl Mixer control to set SD stream number and channel for.
2753	* @param uSD SD stream number (number + 1) to set. Set to 0 for unassign.
2754	* @param uChannel Channel to set. Only valid if a valid SD stream number is specified.
2755	*
2756	* @remarks Can be called as a callback by the HDA codec.
2757	*/
2758	static DECLCALLBACK(int) hdaR3MixerControl(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, uint8_t uSD, uint8_t uChannel)
2759	{
2760	LogFunc(("enmMixerCtl=%s, uSD=%RU8, uChannel=%RU8\n", DrvAudioHlpAudMixerCtlToStr(enmMixerCtl), uSD, uChannel));
2761
2762	if (uSD == 0) /* Stream number 0 is reserved. */
2763	{
2764	Log2Func(("Invalid SDn (%RU8) number for mixer control '%s', ignoring\n", uSD, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl)));
2765	return VINF_SUCCESS;
2766	}
2767	/* uChannel is optional. */
2768
2769	/* SDn0 starts as 1. */
2770	Assert(uSD);
2771	uSD--;
2772
2773	# ifndef VBOX_WITH_AUDIO_HDA_MIC_IN
2774	/* Only SDI0 (Line-In) is supported. */
2775	if ( hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN
2776	&& uSD >= 1)
2777	{
2778	LogRel2(("HDA: Dedicated Mic-In support not imlpemented / built-in (stream #%RU8), using Line-In (stream #0) instead\n", uSD));
2779	uSD = 0;
2780	}
2781	# endif
2782
2783	int rc = VINF_SUCCESS;
2784
2785	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2786	if (pSink)
2787	{
2788	AssertPtr(pSink->pMixSink);
2789
2790	/* If this an output stream, determine the correct SD#. */
2791	if ( (uSD < HDA_MAX_SDI)
2792	&& AudioMixerSinkGetDir(pSink->pMixSink) == AUDMIXSINKDIR_OUTPUT)
2793	{
2794	uSD += HDA_MAX_SDI;
2795	}
2796
2797	/* Detach the existing stream from the sink. */
2798	if ( pSink->pStream
2799	&& ( pSink->pStream->u8SD != uSD
2800	\|\| pSink->pStream->u8Channel != uChannel)
2801	)
2802	{
2803	LogFunc(("Sink '%s' was assigned to stream #%RU8 (channel %RU8) before\n",
2804	pSink->pMixSink->pszName, pSink->pStream->u8SD, pSink->pStream->u8Channel));
2805
2806	hdaR3StreamLock(pSink->pStream);
2807
2808	/* Only disable the stream if the stream descriptor # has changed. */
2809	if (pSink->pStream->u8SD != uSD)
2810	hdaR3StreamEnable(pSink->pStream, false);
2811
2812	pSink->pStream->pMixSink = NULL;
2813
2814	hdaR3StreamUnlock(pSink->pStream);
2815
2816	pSink->pStream = NULL;
2817	}
2818
2819	Assert(uSD < HDA_MAX_STREAMS);
2820
2821	/* Attach the new stream to the sink.
2822	* Enabling the stream will be done by the gust via a separate SDnCTL call then. */
2823	if (pSink->pStream == NULL)
2824	{
2825	LogRel2(("HDA: Setting sink '%s' to stream #%RU8 (channel %RU8), mixer control=%s\n",
2826	pSink->pMixSink->pszName, uSD, uChannel, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl)));
2827
2828	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
2829	if (pStream)
2830	{
2831	hdaR3StreamLock(pStream);
2832
2833	pSink->pStream = pStream;
2834
2835	pStream->u8Channel = uChannel;
2836	pStream->pMixSink = pSink;
2837
2838	hdaR3StreamUnlock(pStream);
2839
2840	rc = VINF_SUCCESS;
2841	}
2842	else
2843	rc = VERR_NOT_IMPLEMENTED;
2844	}
2845	}
2846	else
2847	rc = VERR_NOT_FOUND;
2848
2849	if (RT_FAILURE(rc))
2850	LogRel(("HDA: Converter control for stream #%RU8 (channel %RU8) / mixer control '%s' failed with %Rrc, skipping\n",
2851	uSD, uChannel, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl), rc));
2852
2853	LogFlowFuncLeaveRC(rc);
2854	return rc;
2855	}
2856
2857	/**
2858	* @interface_method_impl{HDACODEC,pfnCbMixerSetVolume}
2859	*
2860	* Sets the volume of a specified mixer control.
2861	*
2862	* @return IPRT status code.
2863	* @param pThis HDA State.
2864	* @param enmMixerCtl Mixer control to set volume for.
2865	* @param pVol Pointer to volume data to set.
2866	*
2867	* @remarks Can be called as a callback by the HDA codec.
2868	*/
2869	static DECLCALLBACK(int) hdaR3MixerSetVolume(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOVOLUME pVol)
2870	{
2871	int rc;
2872
2873	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2874	if ( pSink
2875	&& pSink->pMixSink)
2876	{
2877	LogRel2(("HDA: Setting volume for mixer sink '%s' to %RU8/%RU8 (%s)\n",
2878	pSink->pMixSink->pszName, pVol->uLeft, pVol->uRight, pVol->fMuted ? "Muted" : "Unmuted"));
2879
2880	/* Set the volume.
2881	* We assume that the codec already converted it to the correct range. */
2882	rc = AudioMixerSinkSetVolume(pSink->pMixSink, pVol);
2883	}
2884	else
2885	rc = VERR_NOT_FOUND;
2886
2887	LogFlowFuncLeaveRC(rc);
2888	return rc;
2889	}
2890
2891	/**
2892	* Main routine for the stream's timer.
2893	*
2894	* @param pDevIns Device instance.
2895	* @param pTimer Timer this callback was called for.
2896	* @param pvUser Pointer to associated HDASTREAM.
2897	*/
2898	static DECLCALLBACK(void) hdaR3Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2899	{
2900	RT_NOREF(pDevIns, pTimer);
2901
2902	PHDASTREAM pStream = (PHDASTREAM)pvUser;
2903	AssertPtr(pStream);
2904
2905	PHDASTATE pThis = pStream->pHDAState;
2906
2907	DEVHDA_LOCK_BOTH_RETURN_VOID(pStream->pHDAState, pStream->u8SD);
2908
2909	hdaR3StreamUpdate(pStream, true /* fInTimer */);
2910
2911	/* Flag indicating whether to kick the timer again for a
2912	* new data processing round. */
2913	const bool fSinkActive = AudioMixerSinkIsActive(pStream->pMixSink->pMixSink);
2914	if (fSinkActive)
2915	{
2916	const bool fTimerScheduled = hdaR3StreamTransferIsScheduled(pStream);
2917	Log3Func(("fSinksActive=%RTbool, fTimerScheduled=%RTbool\n", fSinkActive, fTimerScheduled));
2918	if (!fTimerScheduled)
2919	hdaR3TimerSet(pThis, pStream,
2920	TMTimerGet(pThis->pTimer[pStream->u8SD])
2921	+ TMTimerGetFreq(pThis->pTimer[pStream->u8SD]) / pStream->pHDAState->u16TimerHz,
2922	true /* fForce */);
2923	}
2924	else
2925	Log3Func(("fSinksActive=%RTbool\n", fSinkActive));
2926
2927	DEVHDA_UNLOCK_BOTH(pThis, pStream->u8SD);
2928	}
2929
2930	# ifdef HDA_USE_DMA_ACCESS_HANDLER
2931	/**
2932	* HC access handler for the FIFO.
2933	*
2934	* @returns VINF_SUCCESS if the handler have carried out the operation.
2935	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2936	* @param pVM VM Handle.
2937	* @param pVCpu The cross context CPU structure for the calling EMT.
2938	* @param GCPhys The physical address the guest is writing to.
2939	* @param pvPhys The HC mapping of that address.
2940	* @param pvBuf What the guest is reading/writing.
2941	* @param cbBuf How much it's reading/writing.
2942	* @param enmAccessType The access type.
2943	* @param enmOrigin Who is making the access.
2944	* @param pvUser User argument.
2945	*/
2946	static DECLCALLBACK(VBOXSTRICTRC) hdaR3DMAAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys,
2947	void *pvBuf, size_t cbBuf,
2948	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2949	{
2950	RT_NOREF(pVM, pVCpu, pvPhys, pvBuf, enmOrigin);
2951
2952	PHDADMAACCESSHANDLER pHandler = (PHDADMAACCESSHANDLER)pvUser;
2953	AssertPtr(pHandler);
2954
2955	PHDASTREAM pStream = pHandler->pStream;
2956	AssertPtr(pStream);
2957
2958	Assert(GCPhys >= pHandler->GCPhysFirst);
2959	Assert(GCPhys <= pHandler->GCPhysLast);
2960	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
2961
2962	/* Not within BDLE range? Bail out. */
2963	if ( (GCPhys < pHandler->BDLEAddr)
2964	\|\| (GCPhys + cbBuf > pHandler->BDLEAddr + pHandler->BDLESize))
2965	{
2966	return VINF_PGM_HANDLER_DO_DEFAULT;
2967	}
2968
2969	switch(enmAccessType)
2970	{
2971	case PGMACCESSTYPE_WRITE:
2972	{
2973	# ifdef DEBUG
2974	PHDASTREAMDBGINFO pStreamDbg = &pStream->Dbg;
2975
2976	const uint64_t tsNowNs = RTTimeNanoTS();
2977	const uint32_t tsElapsedMs = (tsNowNs - pStreamDbg->tsWriteSlotBegin) / 1000 / 1000;
2978
2979	uint64_t cWritesHz = ASMAtomicReadU64(&pStreamDbg->cWritesHz);
2980	uint64_t cbWrittenHz = ASMAtomicReadU64(&pStreamDbg->cbWrittenHz);
2981
2982	if (tsElapsedMs >= (1000 / HDA_TIMER_HZ_DEFAULT))
2983	{
2984	LogFunc(("[SD%RU8] %RU32ms elapsed, cbWritten=%RU64, cWritten=%RU64 -- %RU32 bytes on average per time slot (%zums)\n",
2985	pStream->u8SD, tsElapsedMs, cbWrittenHz, cWritesHz,
2986	ASMDivU64ByU32RetU32(cbWrittenHz, cWritesHz ? cWritesHz : 1), 1000 / HDA_TIMER_HZ_DEFAULT));
2987
2988	pStreamDbg->tsWriteSlotBegin = tsNowNs;
2989
2990	cWritesHz = 0;
2991	cbWrittenHz = 0;
2992	}
2993
2994	cWritesHz += 1;
2995	cbWrittenHz += cbBuf;
2996
2997	ASMAtomicIncU64(&pStreamDbg->cWritesTotal);
2998	ASMAtomicAddU64(&pStreamDbg->cbWrittenTotal, cbBuf);
2999
3000	ASMAtomicWriteU64(&pStreamDbg->cWritesHz, cWritesHz);
3001	ASMAtomicWriteU64(&pStreamDbg->cbWrittenHz, cbWrittenHz);
3002
3003	LogFunc(("[SD%RU8] Writing %3zu @ 0x%x (off %zu)\n",
3004	pStream->u8SD, cbBuf, GCPhys, GCPhys - pHandler->BDLEAddr));
3005
3006	LogFunc(("[SD%RU8] cWrites=%RU64, cbWritten=%RU64 -> %RU32 bytes on average\n",
3007	pStream->u8SD, pStreamDbg->cWritesTotal, pStreamDbg->cbWrittenTotal,
3008	ASMDivU64ByU32RetU32(pStreamDbg->cbWrittenTotal, pStreamDbg->cWritesTotal)));
3009	# endif
3010
3011	if (pThis->fDebugEnabled)
3012	{
3013	RTFILE fh;
3014	RTFileOpen(&fh, VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH "hdaDMAAccessWrite.pcm",
3015	RTFILE_O_OPEN_CREATE \| RTFILE_O_APPEND \| RTFILE_O_WRITE \| RTFILE_O_DENY_NONE);
3016	RTFileWrite(fh, pvBuf, cbBuf, NULL);
3017	RTFileClose(fh);
3018	}
3019
3020	# ifdef HDA_USE_DMA_ACCESS_HANDLER_WRITING
3021	PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
3022	AssertPtr(pCircBuf);
3023
3024	uint8_t pbBuf = (uint8_t )pvBuf;
3025	while (cbBuf)
3026	{
3027	/* Make sure we only copy as much as the stream's FIFO can hold (SDFIFOS, 18.2.39). */
3028	void *pvChunk;
3029	size_t cbChunk;
3030	RTCircBufAcquireWriteBlock(pCircBuf, cbBuf, &pvChunk, &cbChunk);
3031
3032	if (cbChunk)
3033	{
3034	memcpy(pvChunk, pbBuf, cbChunk);
3035
3036	pbBuf += cbChunk;
3037	Assert(cbBuf >= cbChunk);
3038	cbBuf -= cbChunk;
3039	}
3040	else
3041	{
3042	//AssertMsg(RTCircBufFree(pCircBuf), ("No more space but still %zu bytes to write\n", cbBuf));
3043	break;
3044	}
3045
3046	LogFunc(("[SD%RU8] cbChunk=%zu\n", pStream->u8SD, cbChunk));
3047
3048	RTCircBufReleaseWriteBlock(pCircBuf, cbChunk);
3049	}
3050	# endif /* HDA_USE_DMA_ACCESS_HANDLER_WRITING */
3051	break;
3052	}
3053
3054	default:
3055	AssertMsgFailed(("Access type not implemented\n"));
3056	break;
3057	}
3058
3059	return VINF_PGM_HANDLER_DO_DEFAULT;
3060	}
3061	# endif /* HDA_USE_DMA_ACCESS_HANDLER */
3062
3063	/**
3064	* Soft reset of the device triggered via GCTL.
3065	*
3066	* @param pThis HDA state.
3067	*
3068	*/
3069	static void hdaR3GCTLReset(PHDASTATE pThis)
3070	{
3071	LogFlowFuncEnter();
3072
3073	pThis->cStreamsActive = 0;
3074
3075	HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(HDA_MAX_SDO, HDA_MAX_SDI, 0, 0, 1); /* see 6.2.1 */
3076	HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
3077	HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
3078	HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
3079	HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
3080	HDA_REG(pThis, CORBSIZE) = 0x42; /* Up to 256 CORB entries see 6.2.1 */
3081	HDA_REG(pThis, RIRBSIZE) = 0x42; /* Up to 256 RIRB entries see 6.2.1 */
3082	HDA_REG(pThis, CORBRP) = 0x0;
3083	HDA_REG(pThis, CORBWP) = 0x0;
3084	HDA_REG(pThis, RIRBWP) = 0x0;
3085	/* Some guests (like Haiku) don't set RINTCNT explicitly but expect an interrupt after each
3086	* RIRB response -- so initialize RINTCNT to 1 by default. */
3087	HDA_REG(pThis, RINTCNT) = 0x1;
3088
3089	/*
3090	* Stop any audio currently playing and/or recording.
3091	*/
3092	pThis->SinkFront.pStream = NULL;
3093	if (pThis->SinkFront.pMixSink)
3094	AudioMixerSinkReset(pThis->SinkFront.pMixSink);
3095	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3096	pThis->SinkMicIn.pStream = NULL;
3097	if (pThis->SinkMicIn.pMixSink)
3098	AudioMixerSinkReset(pThis->SinkMicIn.pMixSink);
3099	# endif
3100	pThis->SinkLineIn.pStream = NULL;
3101	if (pThis->SinkLineIn.pMixSink)
3102	AudioMixerSinkReset(pThis->SinkLineIn.pMixSink);
3103	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3104	pThis->SinkCenterLFE = NULL;
3105	if (pThis->SinkCenterLFE.pMixSink)
3106	AudioMixerSinkReset(pThis->SinkCenterLFE.pMixSink);
3107	pThis->SinkRear.pStream = NULL;
3108	if (pThis->SinkRear.pMixSink)
3109	AudioMixerSinkReset(pThis->SinkRear.pMixSink);
3110	# endif
3111
3112	/*
3113	* Reset the codec.
3114	*/
3115	if ( pThis->pCodec
3116	&& pThis->pCodec->pfnReset)
3117	{
3118	pThis->pCodec->pfnReset(pThis->pCodec);
3119	}
3120
3121	/*
3122	* Set some sensible defaults for which HDA sinks
3123	* are connected to which stream number.
3124	*
3125	* We use SD0 for input and SD4 for output by default.
3126	* These stream numbers can be changed by the guest dynamically lateron.
3127	*/
3128	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3129	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_MIC_IN , 1 /* SD0 /, 0 / Channel */);
3130	# endif
3131	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_LINE_IN , 1 /* SD0 /, 0 / Channel */);
3132
3133	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_FRONT , 5 /* SD4 /, 0 / Channel */);
3134	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3135	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_CENTER_LFE, 5 /* SD4 /, 0 / Channel */);
3136	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_REAR , 5 /* SD4 /, 0 / Channel */);
3137	# endif
3138
3139	/* Reset CORB. */
3140	pThis->cbCorbBuf = HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE;
3141	RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
3142
3143	/* Reset RIRB. */
3144	pThis->cbRirbBuf = HDA_RIRB_SIZE * HDA_RIRB_ELEMENT_SIZE;
3145	RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
3146
3147	/* Clear our internal response interrupt counter. */
3148	pThis->u16RespIntCnt = 0;
3149
3150	for (uint8_t uSD = 0; uSD < HDA_MAX_STREAMS; ++uSD)
3151	{
3152	int rc2 = hdaR3StreamEnable(&pThis->aStreams[uSD], false /* fEnable */);
3153	if (RT_SUCCESS(rc2))
3154	{
3155	/* Remove the RUN bit from SDnCTL in case the stream was in a running state before. */
3156	HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_RUN;
3157	hdaR3StreamReset(pThis, &pThis->aStreams[uSD], uSD);
3158	}
3159	}
3160
3161	/* Clear stream tags <-> objects mapping table. */
3162	RT_ZERO(pThis->aTags);
3163
3164	/* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
3165	HDA_REG(pThis, STATESTS) = 0x1;
3166
3167	LogFlowFuncLeave();
3168	LogRel(("HDA: Reset\n"));
3169	}
3170
3171	#endif /* IN_RING3 */
3172
3173	/* MMIO callbacks */
3174
3175	/**
3176	* @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
3177	*
3178	* @note During implementation, we discovered so-called "forgotten" or "hole"
3179	* registers whose description is not listed in the RPM, datasheet, or
3180	* spec.
3181	*/
3182	PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
3183	{
3184	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3185	int rc;
3186	RT_NOREF_PV(pvUser);
3187	Assert(pThis->uAlignmentCheckMagic == HDASTATE_ALIGNMENT_CHECK_MAGIC);
3188
3189	/*
3190	* Look up and log.
3191	*/
3192	uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3193	int idxRegDsc = hdaRegLookup(offReg); /* Register descriptor index. */
3194	#ifdef LOG_ENABLED
3195	unsigned const cbLog = cb;
3196	uint32_t offRegLog = offReg;
3197	#endif
3198
3199	Log3Func(("offReg=%#x cb=%#x\n", offReg, cb));
3200	Assert(cb == 4); Assert((offReg & 3) == 0);
3201
3202	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
3203
3204	if (!(HDA_REG(pThis, GCTL) & HDA_GCTL_CRST) && idxRegDsc != HDA_REG_GCTL)
3205	LogFunc(("Access to registers except GCTL is blocked while reset\n"));
3206
3207	if (idxRegDsc == -1)
3208	LogRel(("HDA: Invalid read access @0x%x (bytes=%u)\n", offReg, cb));
3209
3210	if (idxRegDsc != -1)
3211	{
3212	/* Leave lock before calling read function. */
3213	DEVHDA_UNLOCK(pThis);
3214
3215	/* ASSUMES gapless DWORD at end of map. */
3216	if (g_aHdaRegMap[idxRegDsc].size == 4)
3217	{
3218	/*
3219	* Straight forward DWORD access.
3220	*/
3221	rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
3222	Log3Func(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, (uint32_t )pv, rc));
3223	}
3224	else
3225	{
3226	/*
3227	* Multi register read (unless there are trailing gaps).
3228	* ASSUMES that only DWORD reads have sideeffects.
3229	*/
3230	#ifdef IN_RING3
3231	uint32_t u32Value = 0;
3232	unsigned cbLeft = 4;
3233	do
3234	{
3235	uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
3236	uint32_t u32Tmp = 0;
3237
3238	rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
3239	Log3Func(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
3240	if (rc != VINF_SUCCESS)
3241	break;
3242	u32Value \|= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
3243
3244	cbLeft -= cbReg;
3245	offReg += cbReg;
3246	idxRegDsc++;
3247	} while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
3248
3249	if (rc == VINF_SUCCESS)
3250	(uint32_t )pv = u32Value;
3251	else
3252	Assert(!IOM_SUCCESS(rc));
3253	#else /* !IN_RING3 */
3254	/* Take the easy way out. */
3255	rc = VINF_IOM_R3_MMIO_READ;
3256	#endif /* !IN_RING3 */
3257	}
3258	}
3259	else
3260	{
3261	DEVHDA_UNLOCK(pThis);
3262
3263	rc = VINF_IOM_MMIO_UNUSED_FF;
3264	Log3Func(("\tHole at %x is accessed for read\n", offReg));
3265	}
3266
3267	/*
3268	* Log the outcome.
3269	*/
3270	#ifdef LOG_ENABLED
3271	if (cbLog == 4)
3272	Log3Func(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, (uint32_t )pv, rc));
3273	else if (cbLog == 2)
3274	Log3Func(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, (uint16_t )pv, rc));
3275	else if (cbLog == 1)
3276	Log3Func(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, (uint8_t )pv, rc));
3277	#endif
3278	return rc;
3279	}
3280
3281
3282	DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
3283	{
3284	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
3285
3286	if (!(HDA_REG(pThis, GCTL) & HDA_GCTL_CRST) && idxRegDsc != HDA_REG_GCTL)
3287	{
3288	Log(("hdaWriteReg: Warning: Access to %s is blocked while controller is in reset mode\n", g_aHdaRegMap[idxRegDsc].abbrev));
3289	LogRel2(("HDA: Warning: Access to register %s is blocked while controller is in reset mode\n",
3290	g_aHdaRegMap[idxRegDsc].abbrev));
3291
3292	DEVHDA_UNLOCK(pThis);
3293	return VINF_SUCCESS;
3294	}
3295
3296	/*
3297	* Handle RD (register description) flags.
3298	*/
3299
3300	/* For SDI / SDO: Check if writes to those registers are allowed while SDCTL's RUN bit is set. */
3301	if (idxRegDsc >= HDA_NUM_GENERAL_REGS)
3302	{
3303	const uint32_t uSDCTL = HDA_STREAM_REG(pThis, CTL, HDA_SD_NUM_FROM_REG(pThis, CTL, idxRegDsc));
3304
3305	/*
3306	* Some OSes (like Win 10 AU) violate the spec by writing stuff to registers which are not supposed to be be touched
3307	* while SDCTL's RUN bit is set. So just ignore those values.
3308	*/
3309
3310	/* Is the RUN bit currently set? */
3311	if ( RT_BOOL(uSDCTL & HDA_SDCTL_RUN)
3312	/* Are writes to the register denied if RUN bit is set? */
3313	&& !(g_aHdaRegMap[idxRegDsc].fFlags & HDA_RD_FLAG_SD_WRITE_RUN))
3314	{
3315	Log(("hdaWriteReg: Warning: Access to %s is blocked! %R[sdctl]\n", g_aHdaRegMap[idxRegDsc].abbrev, uSDCTL));
3316	LogRel2(("HDA: Warning: Access to register %s is blocked while the stream's RUN bit is set\n",
3317	g_aHdaRegMap[idxRegDsc].abbrev));
3318
3319	DEVHDA_UNLOCK(pThis);
3320	return VINF_SUCCESS;
3321	}
3322	}
3323
3324	/* Leave the lock before calling write function. */
3325	/** @todo r=bird: Why do we need to do that?? There is no
3326	* explanation why this is necessary here...
3327	*
3328	* More or less all write functions retake the lock, so why not let
3329	* those who need to drop the lock or take additional locks release
3330	* it? See, releasing a lock you already got always runs the risk
3331	* of someone else grabbing it and forcing you to wait, better to
3332	* do the two-three things a write handle needs to do than enter
3333	* and exit the lock all the time. */
3334	DEVHDA_UNLOCK(pThis);
3335
3336	#ifdef LOG_ENABLED
3337	uint32_t const idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3338	uint32_t const u32OldValue = pThis->au32Regs[idxRegMem];
3339	#endif
3340	int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
3341	Log3Func(("Written value %#x to %s[%d byte]; %x => %x%s, rc=%d\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
3342	g_aHdaRegMap[idxRegDsc].size, u32OldValue, pThis->au32Regs[idxRegMem], pszLog, rc));
3343	RT_NOREF(pszLog);
3344	return rc;
3345	}
3346
3347
3348	/**
3349	* @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
3350	*/
3351	PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
3352	{
3353	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3354	int rc;
3355	RT_NOREF_PV(pvUser);
3356	Assert(pThis->uAlignmentCheckMagic == HDASTATE_ALIGNMENT_CHECK_MAGIC);
3357
3358	/*
3359	* The behavior of accesses that aren't aligned on natural boundraries is
3360	* undefined. Just reject them outright.
3361	*/
3362	/** @todo IOM could check this, it could also split the 8 byte accesses for us. */
3363	Assert(cb == 1 \|\| cb == 2 \|\| cb == 4 \|\| cb == 8);
3364	if (GCPhysAddr & (cb - 1))
3365	return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
3366
3367	/*
3368	* Look up and log the access.
3369	*/
3370	uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3371	int idxRegDsc = hdaRegLookup(offReg);
3372	#if defined(IN_RING3) \|\| defined(LOG_ENABLED)
3373	uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
3374	#endif
3375	uint64_t u64Value;
3376	if (cb == 4) u64Value = (uint32_t const )pv;
3377	else if (cb == 2) u64Value = (uint16_t const )pv;
3378	else if (cb == 1) u64Value = (uint8_t const )pv;
3379	else if (cb == 8) u64Value = (uint64_t const )pv;
3380	else
3381	{
3382	u64Value = 0; /* shut up gcc. */
3383	AssertReleaseMsgFailed(("%u\n", cb));
3384	}
3385
3386	#ifdef LOG_ENABLED
3387	uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
3388	if (idxRegDsc == -1)
3389	Log3Func(("@%#05x u32=%#010x cb=%d\n", offReg, (uint32_t const )pv, cb));
3390	else if (cb == 4)
3391	Log3Func(("@%#05x u32=%#010x %s\n", offReg, (uint32_t )pv, g_aHdaRegMap[idxRegDsc].abbrev));
3392	else if (cb == 2)
3393	Log3Func(("@%#05x u16=%#06x (%#010x) %s\n", offReg, (uint16_t )pv, (uint32_t )pv, g_aHdaRegMap[idxRegDsc].abbrev));
3394	else if (cb == 1)
3395	Log3Func(("@%#05x u8=%#04x (%#010x) %s\n", offReg, (uint8_t )pv, (uint32_t )pv, g_aHdaRegMap[idxRegDsc].abbrev));
3396
3397	if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
3398	Log3Func(("\tsize=%RU32 != cb=%u!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
3399	#endif
3400
3401	/*
3402	* Try for a direct hit first.
3403	*/
3404	if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
3405	{
3406	rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
3407	Log3Func(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
3408	}
3409	/*
3410	* Partial or multiple register access, loop thru the requested memory.
3411	*/
3412	else
3413	{
3414	#ifdef IN_RING3
3415	/*
3416	* If it's an access beyond the start of the register, shift the input
3417	* value and fill in missing bits. Natural alignment rules means we
3418	* will only see 1 or 2 byte accesses of this kind, so no risk of
3419	* shifting out input values.
3420	*/
3421	if (idxRegDsc == -1 && (idxRegDsc = hdaR3RegLookupWithin(offReg)) != -1)
3422	{
3423	uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
3424	offReg -= cbBefore;
3425	idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3426	u64Value <<= cbBefore * 8;
3427	u64Value \|= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
3428	Log3Func(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
3429	cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
3430	}
3431
3432	/* Loop thru the write area, it may cover multiple registers. */
3433	rc = VINF_SUCCESS;
3434	for (;;)
3435	{
3436	uint32_t cbReg;
3437	if (idxRegDsc != -1)
3438	{
3439	idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3440	cbReg = g_aHdaRegMap[idxRegDsc].size;
3441	if (cb < cbReg)
3442	{
3443	u64Value \|= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
3444	Log3Func(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
3445	g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
3446	}
3447	# ifdef LOG_ENABLED
3448	uint32_t uLogOldVal = pThis->au32Regs[idxRegMem];
3449	# endif
3450	rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
3451	Log3Func(("\t%#x -> %#x\n", uLogOldVal, pThis->au32Regs[idxRegMem]));
3452	}
3453	else
3454	{
3455	LogRel(("HDA: Invalid write access @0x%x\n", offReg));
3456	cbReg = 1;
3457	}
3458	if (rc != VINF_SUCCESS)
3459	break;
3460	if (cbReg >= cb)
3461	break;
3462
3463	/* Advance. */
3464	offReg += cbReg;
3465	cb -= cbReg;
3466	u64Value >>= cbReg * 8;
3467	if (idxRegDsc == -1)
3468	idxRegDsc = hdaRegLookup(offReg);
3469	else
3470	{
3471	idxRegDsc++;
3472	if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
3473	\|\| g_aHdaRegMap[idxRegDsc].offset != offReg)
3474	{
3475	idxRegDsc = -1;
3476	}
3477	}
3478	}
3479
3480	#else /* !IN_RING3 */
3481	/* Take the simple way out. */
3482	rc = VINF_IOM_R3_MMIO_WRITE;
3483	#endif /* !IN_RING3 */
3484	}
3485
3486	return rc;
3487	}
3488
3489
3490	/* PCI callback. */
3491
3492	#ifdef IN_RING3
3493	/**
3494	* @callback_method_impl{FNPCIIOREGIONMAP}
3495	*/
3496	static DECLCALLBACK(int) hdaR3PciIoRegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3497	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
3498	{
3499	RT_NOREF(iRegion, enmType);
3500	PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
3501
3502	/*
3503	* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
3504	*
3505	* Let IOM talk DWORDs when reading, saves a lot of complications. On
3506	* writing though, we have to do it all ourselves because of sideeffects.
3507	*/
3508	Assert(enmType == PCI_ADDRESS_SPACE_MEM);
3509	int rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /pvUser/,
3510	IOMMMIO_FLAGS_READ_DWORD
3511	\| IOMMMIO_FLAGS_WRITE_PASSTHRU,
3512	hdaMMIOWrite, hdaMMIORead, "HDA");
3513
3514	if (RT_FAILURE(rc))
3515	return rc;
3516
3517	if (pThis->fRZEnabled)
3518	{
3519	rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /pvUser/,
3520	"hdaMMIOWrite", "hdaMMIORead");
3521	if (RT_FAILURE(rc))
3522	return rc;
3523
3524	rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /pvUser/,
3525	"hdaMMIOWrite", "hdaMMIORead");
3526	if (RT_FAILURE(rc))
3527	return rc;
3528	}
3529
3530	pThis->MMIOBaseAddr = GCPhysAddress;
3531	return VINF_SUCCESS;
3532	}
3533
3534
3535	/* Saved state workers and callbacks. */
3536
3537	static int hdaR3SaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStream)
3538	{
3539	RT_NOREF(pDevIns);
3540	#ifdef VBOX_STRICT
3541	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3542	#endif
3543
3544	Log2Func(("[SD%RU8]\n", pStream->u8SD));
3545
3546	/* Save stream ID. */
3547	int rc = SSMR3PutU8(pSSM, pStream->u8SD);
3548	AssertRCReturn(rc, rc);
3549	Assert(pStream->u8SD < HDA_MAX_STREAMS);
3550
3551	rc = SSMR3PutStructEx(pSSM, &pStream->State, sizeof(HDASTREAMSTATE), 0 /fFlags/, g_aSSMStreamStateFields7, NULL);
3552	AssertRCReturn(rc, rc);
3553
3554	#ifdef VBOX_STRICT /* Sanity checks. */
3555	uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
3556	HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
3557	uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
3558	uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
3559
3560	Assert(u64BaseDMA == pStream->u64BDLBase);
3561	Assert(u16LVI == pStream->u16LVI);
3562	Assert(u32CBL == pStream->u32CBL);
3563	#endif
3564
3565	rc = SSMR3PutStructEx(pSSM, &pStream->State.BDLE.Desc, sizeof(HDABDLEDESC),
3566	0 /fFlags/, g_aSSMBDLEDescFields7, NULL);
3567	AssertRCReturn(rc, rc);
3568
3569	rc = SSMR3PutStructEx(pSSM, &pStream->State.BDLE.State, sizeof(HDABDLESTATE),
3570	0 /fFlags/, g_aSSMBDLEStateFields7, NULL);
3571	AssertRCReturn(rc, rc);
3572
3573	rc = SSMR3PutStructEx(pSSM, &pStream->State.Period, sizeof(HDASTREAMPERIOD),
3574	0 /* fFlags */, g_aSSMStreamPeriodFields7, NULL);
3575	AssertRCReturn(rc, rc);
3576
3577	#ifdef VBOX_STRICT /* Sanity checks. */
3578	PHDABDLE pBDLE = &pStream->State.BDLE;
3579	if (u64BaseDMA)
3580	{
3581	Assert(pStream->State.uCurBDLE <= u16LVI + 1);
3582
3583	HDABDLE curBDLE;
3584	rc = hdaR3BDLEFetch(pThis, &curBDLE, u64BaseDMA, pStream->State.uCurBDLE);
3585	AssertRC(rc);
3586
3587	Assert(curBDLE.Desc.u32BufSize == pBDLE->Desc.u32BufSize);
3588	Assert(curBDLE.Desc.u64BufAdr == pBDLE->Desc.u64BufAdr);
3589	Assert(curBDLE.Desc.fFlags == pBDLE->Desc.fFlags);
3590	}
3591	else
3592	{
3593	Assert(pBDLE->Desc.u64BufAdr == 0);
3594	Assert(pBDLE->Desc.u32BufSize == 0);
3595	}
3596	#endif
3597
3598	uint32_t cbCircBufSize = 0;
3599	uint32_t cbCircBufUsed = 0;
3600
3601	if (pStream->State.pCircBuf)
3602	{
3603	cbCircBufSize = (uint32_t)RTCircBufSize(pStream->State.pCircBuf);
3604	cbCircBufUsed = (uint32_t)RTCircBufUsed(pStream->State.pCircBuf);
3605	}
3606
3607	rc = SSMR3PutU32(pSSM, cbCircBufSize);
3608	AssertRCReturn(rc, rc);
3609
3610	rc = SSMR3PutU32(pSSM, cbCircBufUsed);
3611	AssertRCReturn(rc, rc);
3612
3613	if (cbCircBufUsed)
3614	{
3615	/*
3616	* We now need to get the circular buffer's data without actually modifying
3617	* the internal read / used offsets -- otherwise we would end up with broken audio
3618	* data after saving the state.
3619	*
3620	* So get the current read offset and serialize the buffer data manually based on that.
3621	*/
3622	size_t cbCircBufOffRead = RTCircBufOffsetRead(pStream->State.pCircBuf);
3623
3624	void *pvBuf;
3625	size_t cbBuf;
3626	RTCircBufAcquireReadBlock(pStream->State.pCircBuf, cbCircBufUsed, &pvBuf, &cbBuf);
3627
3628	if (cbBuf)
3629	{
3630	size_t cbToRead = cbCircBufUsed;
3631	size_t cbEnd = 0;
3632
3633	if (cbCircBufUsed > cbCircBufOffRead)
3634	cbEnd = cbCircBufUsed - cbCircBufOffRead;
3635
3636	if (cbEnd) /* Save end of buffer first. */
3637	{
3638	rc = SSMR3PutMem(pSSM, (uint8_t )pvBuf + cbCircBufSize - cbEnd / End of buffer */, cbEnd);
3639	AssertRCReturn(rc, rc);
3640
3641	Assert(cbToRead >= cbEnd);
3642	cbToRead -= cbEnd;
3643	}
3644
3645	if (cbToRead) /* Save remaining stuff at start of buffer (if any). */
3646	{
3647	rc = SSMR3PutMem(pSSM, (uint8_t )pvBuf - cbCircBufUsed / Start of buffer */, cbToRead);
3648	AssertRCReturn(rc, rc);
3649	}
3650	}
3651
3652	RTCircBufReleaseReadBlock(pStream->State.pCircBuf, 0 /* Don't advance read pointer -- see comment above */);
3653	}
3654
3655	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n",
3656	pStream->u8SD,
3657	HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), HDA_STREAM_REG(pThis, CBL, pStream->u8SD), HDA_STREAM_REG(pThis, LVI, pStream->u8SD)));
3658
3659	#ifdef LOG_ENABLED
3660	hdaR3BDLEDumpAll(pThis, pStream->u64BDLBase, pStream->u16LVI + 1);
3661	#endif
3662
3663	return rc;
3664	}
3665
3666	/**
3667	* @callback_method_impl{FNSSMDEVSAVEEXEC}
3668	*/
3669	static DECLCALLBACK(int) hdaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3670	{
3671	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3672
3673	/* Save Codec nodes states. */
3674	hdaCodecSaveState(pThis->pCodec, pSSM);
3675
3676	/* Save MMIO registers. */
3677	SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3678	SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3679
3680	/* Save controller-specifc internals. */
3681	SSMR3PutU64(pSSM, pThis->u64WalClk);
3682	SSMR3PutU8(pSSM, pThis->u8IRQL);
3683
3684	/* Save number of streams. */
3685	SSMR3PutU32(pSSM, HDA_MAX_STREAMS);
3686
3687	/* Save stream states. */
3688	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
3689	{
3690	int rc = hdaR3SaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
3691	AssertRCReturn(rc, rc);
3692	}
3693
3694	return VINF_SUCCESS;
3695	}
3696
3697	/**
3698	* Does required post processing when loading a saved state.
3699	*
3700	* @param pThis Pointer to HDA state.
3701	*/
3702	static int hdaR3LoadExecPost(PHDASTATE pThis)
3703	{
3704	int rc = VINF_SUCCESS;
3705
3706	/*
3707	* Enable all previously active streams.
3708	*/
3709	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
3710	{
3711	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, i);
3712	if (pStream)
3713	{
3714	int rc2;
3715
3716	bool fActive = RT_BOOL(HDA_STREAM_REG(pThis, CTL, i) & HDA_SDCTL_RUN);
3717	if (fActive)
3718	{
3719	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
3720	/* Make sure to also create the async I/O thread before actually enabling the stream. */
3721	rc2 = hdaR3StreamAsyncIOCreate(pStream);
3722	AssertRC(rc2);
3723
3724	/* ... and enabling it. */
3725	hdaR3StreamAsyncIOEnable(pStream, true /* fEnable */);
3726	#endif
3727	/* Resume the stream's period. */
3728	hdaR3StreamPeriodResume(&pStream->State.Period);
3729
3730	/* (Re-)enable the stream. */
3731	rc2 = hdaR3StreamEnable(pStream, true /* fEnable */);
3732	AssertRC(rc2);
3733
3734	/* Add the stream to the device setup. */
3735	rc2 = hdaR3AddStream(pThis, &pStream->State.Cfg);
3736	AssertRC(rc2);
3737
3738	#ifdef HDA_USE_DMA_ACCESS_HANDLER
3739	/* (Re-)install the DMA handler. */
3740	hdaR3StreamRegisterDMAHandlers(pThis, pStream);
3741	#endif
3742	if (hdaR3StreamTransferIsScheduled(pStream))
3743	hdaR3TimerSet(pThis, pStream, hdaR3StreamTransferGetNext(pStream), true /* fForce */);
3744
3745	/* Also keep track of the currently active streams. */
3746	pThis->cStreamsActive++;
3747	}
3748	}
3749	}
3750
3751	LogFlowFuncLeaveRC(rc);
3752	return rc;
3753	}
3754
3755
3756	/**
3757	* Handles loading of all saved state versions older than the current one.
3758	*
3759	* @param pThis Pointer to HDA state.
3760	* @param pSSM Pointer to SSM handle.
3761	* @param uVersion Saved state version to load.
3762	* @param uPass Loading stage to handle.
3763	*/
3764	static int hdaR3LoadExecLegacy(PHDASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3765	{
3766	RT_NOREF(uPass);
3767
3768	int rc = VINF_SUCCESS;
3769
3770	/*
3771	* Load MMIO registers.
3772	*/
3773	uint32_t cRegs;
3774	switch (uVersion)
3775	{
3776	case HDA_SSM_VERSION_1:
3777	/* Starting with r71199, we would save 112 instead of 113
3778	registers due to some code cleanups. This only affected trunk
3779	builds in the 4.1 development period. */
3780	cRegs = 113;
3781	if (SSMR3HandleRevision(pSSM) >= 71199)
3782	{
3783	uint32_t uVer = SSMR3HandleVersion(pSSM);
3784	if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3785	&& VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3786	&& VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3787	cRegs = 112;
3788	}
3789	break;
3790
3791	case HDA_SSM_VERSION_2:
3792	case HDA_SSM_VERSION_3:
3793	cRegs = 112;
3794	AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= 112);
3795	break;
3796
3797	/* Since version 4 we store the register count to stay flexible. */
3798	case HDA_SSM_VERSION_4:
3799	case HDA_SSM_VERSION_5:
3800	case HDA_SSM_VERSION_6:
3801	rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3802	if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3803	LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3804	break;
3805
3806	default:
3807	LogRel(("HDA: Warning: Unsupported / too new saved state version (%RU32)\n", uVersion));
3808	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3809	}
3810
3811	if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3812	{
3813	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3814	SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3815	}
3816	else
3817	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3818
3819	/* Make sure to update the base addresses first before initializing any streams down below. */
3820	pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3821	pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3822	pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE) & DPBASE_ADDR_MASK, HDA_REG(pThis, DPUBASE));
3823
3824	/* Also make sure to update the DMA position bit if this was enabled when saving the state. */
3825	pThis->fDMAPosition = RT_BOOL(HDA_REG(pThis, DPLBASE) & RT_BIT_32(0));
3826
3827	/*
3828	* Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
3829	* every BDLE state, whereas it only needs to be stored
3830	* once for every stream. Most of the BDLE state we can
3831	* get out of the registers anyway, so just ignore those values.
3832	*
3833	* Also, only the current BDLE was saved, regardless whether
3834	* there were more than one (and there are at least two entries,
3835	* according to the spec).
3836	*/
3837	#define HDA_SSM_LOAD_BDLE_STATE_PRE_V5(v, x) \
3838	{ \
3839	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */ \
3840	AssertRCReturn(rc, rc); \
3841	rc = SSMR3GetU64(pSSM, &x.Desc.u64BufAdr); /* u64BdleCviAddr */ \
3842	AssertRCReturn(rc, rc); \
3843	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleMaxCvi */ \
3844	AssertRCReturn(rc, rc); \
3845	rc = SSMR3GetU32(pSSM, &x.State.u32BDLIndex); /* u32BdleCvi */ \
3846	AssertRCReturn(rc, rc); \
3847	rc = SSMR3GetU32(pSSM, &x.Desc.u32BufSize); /* u32BdleCviLen */ \
3848	AssertRCReturn(rc, rc); \
3849	rc = SSMR3GetU32(pSSM, &x.State.u32BufOff); /* u32BdleCviPos */ \
3850	AssertRCReturn(rc, rc); \
3851	bool fIOC; \
3852	rc = SSMR3GetBool(pSSM, &fIOC); /* fBdleCviIoc */ \
3853	AssertRCReturn(rc, rc); \
3854	x.Desc.fFlags = fIOC ? HDA_BDLE_FLAG_IOC : 0; \
3855	rc = SSMR3GetU32(pSSM, &x.State.cbBelowFIFOW); /* cbUnderFifoW */ \
3856	AssertRCReturn(rc, rc); \
3857	rc = SSMR3Skip(pSSM, sizeof(uint8_t) * 256); /* FIFO */ \
3858	AssertRCReturn(rc, rc); \
3859	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */ \
3860	AssertRCReturn(rc, rc); \
3861	}
3862
3863	/*
3864	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3865	*/
3866	switch (uVersion)
3867	{
3868	case HDA_SSM_VERSION_1:
3869	case HDA_SSM_VERSION_2:
3870	case HDA_SSM_VERSION_3:
3871	case HDA_SSM_VERSION_4:
3872	{
3873	/* Only load the internal states.
3874	* The rest will be initialized from the saved registers later. */
3875
3876	/* Note 1: Only the current BDLE for a stream was saved! */
3877	/* Note 2: The stream's saving order is/was fixed, so don't touch! */
3878
3879	/* Output */
3880	PHDASTREAM pStream = &pThis->aStreams[4];
3881	rc = hdaR3StreamInit(pStream, 4 /* Stream descriptor, hardcoded */);
3882	if (RT_FAILURE(rc))
3883	break;
3884	HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
3885	pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
3886
3887	/* Microphone-In */
3888	pStream = &pThis->aStreams[2];
3889	rc = hdaR3StreamInit(pStream, 2 /* Stream descriptor, hardcoded */);
3890	if (RT_FAILURE(rc))
3891	break;
3892	HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
3893	pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
3894
3895	/* Line-In */
3896	pStream = &pThis->aStreams[0];
3897	rc = hdaR3StreamInit(pStream, 0 /* Stream descriptor, hardcoded */);
3898	if (RT_FAILURE(rc))
3899	break;
3900	HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
3901	pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
3902	break;
3903	}
3904
3905	#undef HDA_SSM_LOAD_BDLE_STATE_PRE_V5
3906
3907	default: /* Since v5 we support flexible stream and BDLE counts. */
3908	{
3909	uint32_t cStreams;
3910	rc = SSMR3GetU32(pSSM, &cStreams);
3911	if (RT_FAILURE(rc))
3912	break;
3913
3914	if (cStreams > HDA_MAX_STREAMS)
3915	cStreams = HDA_MAX_STREAMS; /* Sanity. */
3916
3917	/* Load stream states. */
3918	for (uint32_t i = 0; i < cStreams; i++)
3919	{
3920	uint8_t uStreamID;
3921	rc = SSMR3GetU8(pSSM, &uStreamID);
3922	if (RT_FAILURE(rc))
3923	break;
3924
3925	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uStreamID);
3926	HDASTREAM StreamDummy;
3927
3928	if (!pStream)
3929	{
3930	pStream = &StreamDummy;
3931	LogRel2(("HDA: Warning: Stream ID=%RU32 not supported, skipping to load ...\n", uStreamID));
3932	}
3933
3934	rc = hdaR3StreamInit(pStream, uStreamID);
3935	if (RT_FAILURE(rc))
3936	{
3937	LogRel(("HDA: Stream #%RU32: Initialization of stream %RU8 failed, rc=%Rrc\n", i, uStreamID, rc));
3938	break;
3939	}
3940
3941	/*
3942	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3943	*/
3944
3945	if (uVersion == HDA_SSM_VERSION_5)
3946	{
3947	/* Get the current BDLE entry and skip the rest. */
3948	uint16_t cBDLE;
3949
3950	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
3951	AssertRC(rc);
3952	rc = SSMR3GetU16(pSSM, &cBDLE); /* cBDLE */
3953	AssertRC(rc);
3954	rc = SSMR3GetU16(pSSM, &pStream->State.uCurBDLE); /* uCurBDLE */
3955	AssertRC(rc);
3956	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
3957	AssertRC(rc);
3958
3959	uint32_t u32BDLEIndex;
3960	for (uint16_t a = 0; a < cBDLE; a++)
3961	{
3962	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
3963	AssertRC(rc);
3964	rc = SSMR3GetU32(pSSM, &u32BDLEIndex); /* u32BDLIndex */
3965	AssertRC(rc);
3966
3967	/* Does the current BDLE index match the current BDLE to process? */
3968	if (u32BDLEIndex == pStream->State.uCurBDLE)
3969	{
3970	rc = SSMR3GetU32(pSSM, &pStream->State.BDLE.State.cbBelowFIFOW); /* cbBelowFIFOW */
3971	AssertRC(rc);
3972	rc = SSMR3Skip(pSSM, sizeof(uint8_t) * 256); /* FIFO, deprecated */
3973	AssertRC(rc);
3974	rc = SSMR3GetU32(pSSM, &pStream->State.BDLE.State.u32BufOff); /* u32BufOff */
3975	AssertRC(rc);
3976	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
3977	AssertRC(rc);
3978	}
3979	else /* Skip not current BDLEs. */
3980	{
3981	rc = SSMR3Skip(pSSM, sizeof(uint32_t) /* cbBelowFIFOW */
3982	+ sizeof(uint8_t) * 256 /* au8FIFO */
3983	+ sizeof(uint32_t) /* u32BufOff */
3984	+ sizeof(uint32_t)); /* End marker */
3985	AssertRC(rc);
3986	}
3987	}
3988	}
3989	else
3990	{
3991	rc = SSMR3GetStructEx(pSSM, &pStream->State, sizeof(HDASTREAMSTATE),
3992	0 /* fFlags */, g_aSSMStreamStateFields6, NULL);
3993	if (RT_FAILURE(rc))
3994	break;
3995
3996	/* Get HDABDLEDESC. */
3997	uint32_t uMarker;
3998	rc = SSMR3GetU32(pSSM, &uMarker); /* Begin marker. */
3999	AssertRC(rc);
4000	Assert(uMarker == UINT32_C(0x19200102) /* SSMR3STRUCT_BEGIN */);
4001	rc = SSMR3GetU64(pSSM, &pStream->State.BDLE.Desc.u64BufAdr);
4002	AssertRC(rc);
4003	rc = SSMR3GetU32(pSSM, &pStream->State.BDLE.Desc.u32BufSize);
4004	AssertRC(rc);
4005	bool fFlags = false;
4006	rc = SSMR3GetBool(pSSM, &fFlags); /* Saved states < v7 only stored the IOC as boolean flag. */
4007	AssertRC(rc);
4008	pStream->State.BDLE.Desc.fFlags = fFlags ? HDA_BDLE_FLAG_IOC : 0;
4009	rc = SSMR3GetU32(pSSM, &uMarker); /* End marker. */
4010	AssertRC(rc);
4011	Assert(uMarker == UINT32_C(0x19920406) /* SSMR3STRUCT_END */);
4012
4013	rc = SSMR3GetStructEx(pSSM, &pStream->State.BDLE.State, sizeof(HDABDLESTATE),
4014	0 /* fFlags */, g_aSSMBDLEStateFields6, NULL);
4015	if (RT_FAILURE(rc))
4016	break;
4017
4018	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n",
4019	uStreamID,
4020	HDA_STREAM_REG(pThis, LPIB, uStreamID), HDA_STREAM_REG(pThis, CBL, uStreamID), HDA_STREAM_REG(pThis, LVI, uStreamID)));
4021	#ifdef LOG_ENABLED
4022	hdaR3BDLEDumpAll(pThis, pStream->u64BDLBase, pStream->u16LVI + 1);
4023	#endif
4024	}
4025
4026	} /* for cStreams */
4027	break;
4028	} /* default */
4029	}
4030
4031	return rc;
4032	}
4033
4034	/**
4035	* @callback_method_impl{FNSSMDEVLOADEXEC}
4036	*/
4037	static DECLCALLBACK(int) hdaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4038	{
4039	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4040
4041	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
4042
4043	LogRel2(("hdaR3LoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
4044
4045	/*
4046	* Load Codec nodes states.
4047	*/
4048	int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
4049	if (RT_FAILURE(rc))
4050	{
4051	LogRel(("HDA: Failed loading codec state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
4052	return rc;
4053	}
4054
4055	if (uVersion < HDA_SSM_VERSION) /* Handle older saved states? */
4056	{
4057	rc = hdaR3LoadExecLegacy(pThis, pSSM, uVersion, uPass);
4058	if (RT_SUCCESS(rc))
4059	rc = hdaR3LoadExecPost(pThis);
4060
4061	return rc;
4062	}
4063
4064	/*
4065	* Load MMIO registers.
4066	*/
4067	uint32_t cRegs;
4068	rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
4069	if (cRegs != RT_ELEMENTS(pThis->au32Regs))
4070	LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
4071
4072	if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
4073	{
4074	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
4075	SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
4076	}
4077	else
4078	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
4079
4080	/* Make sure to update the base addresses first before initializing any streams down below. */
4081	pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
4082	pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
4083	pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE) & DPBASE_ADDR_MASK, HDA_REG(pThis, DPUBASE));
4084
4085	/* Also make sure to update the DMA position bit if this was enabled when saving the state. */
4086	pThis->fDMAPosition = RT_BOOL(HDA_REG(pThis, DPLBASE) & RT_BIT_32(0));
4087
4088	/*
4089	* Load controller-specifc internals.
4090	* Don't annoy other team mates (forgot this for state v7).
4091	*/
4092	if ( SSMR3HandleRevision(pSSM) >= 116273
4093	\|\| SSMR3HandleVersion(pSSM) >= VBOX_FULL_VERSION_MAKE(5, 2, 0))
4094	{
4095	rc = SSMR3GetU64(pSSM, &pThis->u64WalClk);
4096	AssertRC(rc);
4097
4098	rc = SSMR3GetU8(pSSM, &pThis->u8IRQL);
4099	AssertRC(rc);
4100	}
4101
4102	/*
4103	* Load streams.
4104	*/
4105	uint32_t cStreams;
4106	rc = SSMR3GetU32(pSSM, &cStreams);
4107	AssertRC(rc);
4108
4109	if (cStreams > HDA_MAX_STREAMS)
4110	cStreams = HDA_MAX_STREAMS; /* Sanity. */
4111
4112	Log2Func(("cStreams=%RU32\n", cStreams));
4113
4114	/* Load stream states. */
4115	for (uint32_t i = 0; i < cStreams; i++)
4116	{
4117	uint8_t uStreamID;
4118	rc = SSMR3GetU8(pSSM, &uStreamID);
4119	AssertRC(rc);
4120
4121	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uStreamID);
4122	HDASTREAM StreamDummy;
4123
4124	if (!pStream)
4125	{
4126	pStream = &StreamDummy;
4127	LogRel2(("HDA: Warning: Loading of stream #%RU8 not supported, skipping to load ...\n", uStreamID));
4128	}
4129
4130	rc = hdaR3StreamInit(pStream, uStreamID);
4131	if (RT_FAILURE(rc))
4132	{
4133	LogRel(("HDA: Stream #%RU8: Loading initialization failed, rc=%Rrc\n", uStreamID, rc));
4134	/* Continue. */
4135	}
4136
4137	rc = SSMR3GetStructEx(pSSM, &pStream->State, sizeof(HDASTREAMSTATE),
4138	0 /* fFlags */, g_aSSMStreamStateFields7,
4139	NULL);
4140	AssertRC(rc);
4141
4142	/*
4143	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
4144	*/
4145	rc = SSMR3GetStructEx(pSSM, &pStream->State.BDLE.Desc, sizeof(HDABDLEDESC),
4146	0 /* fFlags */, g_aSSMBDLEDescFields7, NULL);
4147	AssertRC(rc);
4148
4149	rc = SSMR3GetStructEx(pSSM, &pStream->State.BDLE.State, sizeof(HDABDLESTATE),
4150	0 /* fFlags */, g_aSSMBDLEStateFields7, NULL);
4151	AssertRC(rc);
4152
4153	Log2Func(("[SD%RU8] %R[bdle]\n", pStream->u8SD, &pStream->State.BDLE));
4154
4155	/*
4156	* Load period state.
4157	* Don't annoy other team mates (forgot this for state v7).
4158	*/
4159	hdaR3StreamPeriodInit(&pStream->State.Period,
4160	pStream->u8SD, pStream->u16LVI, pStream->u32CBL, &pStream->State.Cfg);
4161
4162	if ( SSMR3HandleRevision(pSSM) >= 116273
4163	\|\| SSMR3HandleVersion(pSSM) >= VBOX_FULL_VERSION_MAKE(5, 2, 0))
4164	{
4165	rc = SSMR3GetStructEx(pSSM, &pStream->State.Period, sizeof(HDASTREAMPERIOD),
4166	0 /* fFlags */, g_aSSMStreamPeriodFields7, NULL);
4167	AssertRC(rc);
4168	}
4169
4170	/*
4171	* Load internal (FIFO) buffer.
4172	*/
4173	uint32_t cbCircBufSize = 0;
4174	rc = SSMR3GetU32(pSSM, &cbCircBufSize); /* cbCircBuf */
4175	AssertRC(rc);
4176
4177	uint32_t cbCircBufUsed = 0;
4178	rc = SSMR3GetU32(pSSM, &cbCircBufUsed); /* cbCircBuf */
4179	AssertRC(rc);
4180
4181	if (cbCircBufSize) /* If 0, skip the buffer. */
4182	{
4183	/* Paranoia. */
4184	AssertReleaseMsg(cbCircBufSize <= _1M,
4185	("HDA: Saved state contains bogus DMA buffer size (%RU32) for stream #%RU8",
4186	cbCircBufSize, uStreamID));
4187	AssertReleaseMsg(cbCircBufUsed <= cbCircBufSize,
4188	("HDA: Saved state contains invalid DMA buffer usage (%RU32/%RU32) for stream #%RU8",
4189	cbCircBufUsed, cbCircBufSize, uStreamID));
4190	AssertPtr(pStream->State.pCircBuf);
4191
4192	/* Do we need to cre-create the circular buffer do fit the data size? */
4193	if (cbCircBufSize != (uint32_t)RTCircBufSize(pStream->State.pCircBuf))
4194	{
4195	RTCircBufDestroy(pStream->State.pCircBuf);
4196	pStream->State.pCircBuf = NULL;
4197
4198	rc = RTCircBufCreate(&pStream->State.pCircBuf, cbCircBufSize);
4199	AssertRC(rc);
4200	}
4201
4202	if ( RT_SUCCESS(rc)
4203	&& cbCircBufUsed)
4204	{
4205	void *pvBuf;
4206	size_t cbBuf;
4207
4208	RTCircBufAcquireWriteBlock(pStream->State.pCircBuf, cbCircBufUsed, &pvBuf, &cbBuf);
4209
4210	if (cbBuf)
4211	{
4212	rc = SSMR3GetMem(pSSM, pvBuf, cbBuf);
4213	AssertRC(rc);
4214	}
4215
4216	RTCircBufReleaseWriteBlock(pStream->State.pCircBuf, cbBuf);
4217
4218	Assert(cbBuf == cbCircBufUsed);
4219	}
4220	}
4221
4222	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n",
4223	uStreamID,
4224	HDA_STREAM_REG(pThis, LPIB, uStreamID), HDA_STREAM_REG(pThis, CBL, uStreamID), HDA_STREAM_REG(pThis, LVI, uStreamID)));
4225	#ifdef LOG_ENABLED
4226	hdaR3BDLEDumpAll(pThis, pStream->u64BDLBase, pStream->u16LVI + 1);
4227	#endif
4228	/** @todo (Re-)initialize active periods? */
4229
4230	} /* for cStreams */
4231
4232	rc = hdaR3LoadExecPost(pThis);
4233	AssertRC(rc);
4234
4235	LogFlowFuncLeaveRC(rc);
4236	return rc;
4237	}
4238
4239	/* IPRT format type handlers. */
4240
4241	/**
4242	* @callback_method_impl{FNRTSTRFORMATTYPE}
4243	*/
4244	static DECLCALLBACK(size_t) hdaR3StrFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4245	const char pszType, void const pvValue,
4246	int cchWidth, int cchPrecision, unsigned fFlags,
4247	void *pvUser)
4248	{
4249	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4250	PHDABDLE pBDLE = (PHDABDLE)pvValue;
4251	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4252	"BDLE(idx:%RU32, off:%RU32, fifow:%RU32, IOC:%RTbool, DMA[%RU32 bytes @ 0x%x])",
4253	pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW,
4254	pBDLE->Desc.fFlags & HDA_BDLE_FLAG_IOC, pBDLE->Desc.u32BufSize, pBDLE->Desc.u64BufAdr);
4255	}
4256
4257	/**
4258	* @callback_method_impl{FNRTSTRFORMATTYPE}
4259	*/
4260	static DECLCALLBACK(size_t) hdaR3StrFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4261	const char pszType, void const pvValue,
4262	int cchWidth, int cchPrecision, unsigned fFlags,
4263	void *pvUser)
4264	{
4265	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4266	uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
4267	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4268	"SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
4269	uSDCTL,
4270	uSDCTL & HDA_SDCTL_DIR ? "OUT" : "IN",
4271	RT_BOOL(uSDCTL & HDA_SDCTL_TP),
4272	(uSDCTL & HDA_SDCTL_STRIPE_MASK) >> HDA_SDCTL_STRIPE_SHIFT,
4273	RT_BOOL(uSDCTL & HDA_SDCTL_DEIE),
4274	RT_BOOL(uSDCTL & HDA_SDCTL_FEIE),
4275	RT_BOOL(uSDCTL & HDA_SDCTL_IOCE),
4276	RT_BOOL(uSDCTL & HDA_SDCTL_RUN),
4277	RT_BOOL(uSDCTL & HDA_SDCTL_SRST));
4278	}
4279
4280	/**
4281	* @callback_method_impl{FNRTSTRFORMATTYPE}
4282	*/
4283	static DECLCALLBACK(size_t) hdaR3StrFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4284	const char pszType, void const pvValue,
4285	int cchWidth, int cchPrecision, unsigned fFlags,
4286	void *pvUser)
4287	{
4288	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4289	uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
4290	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, uSDFIFOS ? uSDFIFOS + 1 : 0);
4291	}
4292
4293	/**
4294	* @callback_method_impl{FNRTSTRFORMATTYPE}
4295	*/
4296	static DECLCALLBACK(size_t) hdaR3StrFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4297	const char pszType, void const pvValue,
4298	int cchWidth, int cchPrecision, unsigned fFlags,
4299	void *pvUser)
4300	{
4301	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4302	uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
4303	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
4304	}
4305
4306	/**
4307	* @callback_method_impl{FNRTSTRFORMATTYPE}
4308	*/
4309	static DECLCALLBACK(size_t) hdaR3StrFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4310	const char pszType, void const pvValue,
4311	int cchWidth, int cchPrecision, unsigned fFlags,
4312	void *pvUser)
4313	{
4314	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4315	uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
4316	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4317	"SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
4318	uSdSts,
4319	RT_BOOL(uSdSts & HDA_SDSTS_FIFORDY),
4320	RT_BOOL(uSdSts & HDA_SDSTS_DESE),
4321	RT_BOOL(uSdSts & HDA_SDSTS_FIFOE),
4322	RT_BOOL(uSdSts & HDA_SDSTS_BCIS));
4323	}
4324
4325	/* Debug info dumpers */
4326
4327	static int hdaR3DbgLookupRegByName(const char *pszArgs)
4328	{
4329	int iReg = 0;
4330	for (; iReg < HDA_NUM_REGS; ++iReg)
4331	if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
4332	return iReg;
4333	return -1;
4334	}
4335
4336
4337	static void hdaR3DbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
4338	{
4339	Assert( pThis
4340	&& iHdaIndex >= 0
4341	&& iHdaIndex < HDA_NUM_REGS);
4342	pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
4343	}
4344
4345	/**
4346	* @callback_method_impl{FNDBGFHANDLERDEV}
4347	*/
4348	static DECLCALLBACK(void) hdaR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4349	{
4350	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4351	int iHdaRegisterIndex = hdaR3DbgLookupRegByName(pszArgs);
4352	if (iHdaRegisterIndex != -1)
4353	hdaR3DbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
4354	else
4355	{
4356	for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NUM_REGS; ++iHdaRegisterIndex)
4357	hdaR3DbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
4358	}
4359	}
4360
4361	static void hdaR3DbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
4362	{
4363	Assert( pThis
4364	&& iIdx >= 0
4365	&& iIdx < HDA_MAX_STREAMS);
4366
4367	const PHDASTREAM pStream = &pThis->aStreams[iIdx];
4368
4369	pHlp->pfnPrintf(pHlp, "Stream #%d:\n", iIdx);
4370	pHlp->pfnPrintf(pHlp, "\tSD%dCTL : %R[sdctl]\n", iIdx, HDA_STREAM_REG(pThis, CTL, iIdx));
4371	pHlp->pfnPrintf(pHlp, "\tSD%dCTS : %R[sdsts]\n", iIdx, HDA_STREAM_REG(pThis, STS, iIdx));
4372	pHlp->pfnPrintf(pHlp, "\tSD%dFIFOS: %R[sdfifos]\n", iIdx, HDA_STREAM_REG(pThis, FIFOS, iIdx));
4373	pHlp->pfnPrintf(pHlp, "\tSD%dFIFOW: %R[sdfifow]\n", iIdx, HDA_STREAM_REG(pThis, FIFOW, iIdx));
4374	pHlp->pfnPrintf(pHlp, "\tBDLE : %R[bdle]\n", &pStream->State.BDLE);
4375	}
4376
4377	static void hdaR3DbgPrintBDLE(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
4378	{
4379	Assert( pThis
4380	&& iIdx >= 0
4381	&& iIdx < HDA_MAX_STREAMS);
4382
4383	const PHDASTREAM pStream = &pThis->aStreams[iIdx];
4384	const PHDABDLE pBDLE = &pStream->State.BDLE;
4385
4386	pHlp->pfnPrintf(pHlp, "Stream #%d BDLE:\n", iIdx);
4387
4388	uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, iIdx),
4389	HDA_STREAM_REG(pThis, BDPU, iIdx));
4390	uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, iIdx);
4391	uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, iIdx);
4392
4393	if (!u64BaseDMA)
4394	return;
4395
4396	pHlp->pfnPrintf(pHlp, "\tCurrent: %R[bdle]\n\n", pBDLE);
4397
4398	pHlp->pfnPrintf(pHlp, "\tMemory:\n");
4399
4400	uint32_t cbBDLE = 0;
4401	for (uint16_t i = 0; i < u16LVI + 1; i++)
4402	{
4403	HDABDLEDESC bd;
4404	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i * sizeof(HDABDLEDESC), &bd, sizeof(bd));
4405
4406	pHlp->pfnPrintf(pHlp, "\t\t%s #%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
4407	pBDLE->State.u32BDLIndex == i ? "*" : " ", i, bd.u64BufAdr, bd.u32BufSize, bd.fFlags & HDA_BDLE_FLAG_IOC);
4408
4409	cbBDLE += bd.u32BufSize;
4410	}
4411
4412	pHlp->pfnPrintf(pHlp, "Total: %RU32 bytes\n", cbBDLE);
4413
4414	if (cbBDLE != u32CBL)
4415	pHlp->pfnPrintf(pHlp, "Warning: %RU32 bytes does not match CBL (%RU32)!\n", cbBDLE, u32CBL);
4416
4417	pHlp->pfnPrintf(pHlp, "DMA counters (base @ 0x%llx):\n", u64BaseDMA);
4418	if (!u64BaseDMA) /* No DMA base given? Bail out. */
4419	{
4420	pHlp->pfnPrintf(pHlp, "\tNo counters found\n");
4421	return;
4422	}
4423
4424	for (int i = 0; i < u16LVI + 1; i++)
4425	{
4426	uint32_t uDMACnt;
4427	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
4428	&uDMACnt, sizeof(uDMACnt));
4429
4430	pHlp->pfnPrintf(pHlp, "\t#%03d DMA @ 0x%x\n", i , uDMACnt);
4431	}
4432	}
4433
4434	static int hdaR3DbgLookupStrmIdx(PHDASTATE pThis, const char *pszArgs)
4435	{
4436	RT_NOREF(pThis, pszArgs);
4437	/** @todo Add args parsing. */
4438	return -1;
4439	}
4440
4441	/**
4442	* @callback_method_impl{FNDBGFHANDLERDEV}
4443	*/
4444	static DECLCALLBACK(void) hdaR3DbgInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4445	{
4446	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4447	int iHdaStreamdex = hdaR3DbgLookupStrmIdx(pThis, pszArgs);
4448	if (iHdaStreamdex != -1)
4449	hdaR3DbgPrintStream(pThis, pHlp, iHdaStreamdex);
4450	else
4451	for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
4452	hdaR3DbgPrintStream(pThis, pHlp, iHdaStreamdex);
4453	}
4454
4455	/**
4456	* @callback_method_impl{FNDBGFHANDLERDEV}
4457	*/
4458	static DECLCALLBACK(void) hdaR3DbgInfoBDLE(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4459	{
4460	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4461	int iHdaStreamdex = hdaR3DbgLookupStrmIdx(pThis, pszArgs);
4462	if (iHdaStreamdex != -1)
4463	hdaR3DbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
4464	else
4465	for (iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
4466	hdaR3DbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
4467	}
4468
4469	/**
4470	* @callback_method_impl{FNDBGFHANDLERDEV}
4471	*/
4472	static DECLCALLBACK(void) hdaR3DbgInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4473	{
4474	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4475
4476	if (pThis->pCodec->pfnDbgListNodes)
4477	pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
4478	else
4479	pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
4480	}
4481
4482	/**
4483	* @callback_method_impl{FNDBGFHANDLERDEV}
4484	*/
4485	static DECLCALLBACK(void) hdaR3DbgInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4486	{
4487	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4488
4489	if (pThis->pCodec->pfnDbgSelector)
4490	pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
4491	else
4492	pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
4493	}
4494
4495	/**
4496	* @callback_method_impl{FNDBGFHANDLERDEV}
4497	*/
4498	static DECLCALLBACK(void) hdaR3DbgInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4499	{
4500	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4501
4502	if (pThis->pMixer)
4503	AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
4504	else
4505	pHlp->pfnPrintf(pHlp, "Mixer not available\n");
4506	}
4507
4508
4509	/* PDMIBASE */
4510
4511	/**
4512	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
4513	*/
4514	static DECLCALLBACK(void ) hdaR3QueryInterface(struct PDMIBASE pInterface, const char *pszIID)
4515	{
4516	PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
4517	Assert(&pThis->IBase == pInterface);
4518
4519	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
4520	return NULL;
4521	}
4522
4523
4524	/* PDMDEVREG */
4525
4526	/**
4527	* Attach command, internal version.
4528	*
4529	* This is called to let the device attach to a driver for a specified LUN
4530	* during runtime. This is not called during VM construction, the device
4531	* constructor has to attach to all the available drivers.
4532	*
4533	* @returns VBox status code.
4534	* @param pThis HDA state.
4535	* @param uLUN The logical unit which is being detached.
4536	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4537	* @param ppDrv Attached driver instance on success. Optional.
4538	*/
4539	static int hdaR3AttachInternal(PHDASTATE pThis, unsigned uLUN, uint32_t fFlags, PHDADRIVER *ppDrv)
4540	{
4541	RT_NOREF(fFlags);
4542
4543	/*
4544	* Attach driver.
4545	*/
4546	char *pszDesc;
4547	if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
4548	AssertLogRelFailedReturn(VERR_NO_MEMORY);
4549
4550	PPDMIBASE pDrvBase;
4551	int rc = PDMDevHlpDriverAttach(pThis->pDevInsR3, uLUN,
4552	&pThis->IBase, &pDrvBase, pszDesc);
4553	if (RT_SUCCESS(rc))
4554	{
4555	PHDADRIVER pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
4556	if (pDrv)
4557	{
4558	pDrv->pDrvBase = pDrvBase;
4559	pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
4560	AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
4561	pDrv->pHDAState = pThis;
4562	pDrv->uLUN = uLUN;
4563
4564	/*
4565	* For now we always set the driver at LUN 0 as our primary
4566	* host backend. This might change in the future.
4567	*/
4568	if (pDrv->uLUN == 0)
4569	pDrv->fFlags \|= PDMAUDIODRVFLAGS_PRIMARY;
4570
4571	LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->fFlags));
4572
4573	/* Attach to driver list if not attached yet. */
4574	if (!pDrv->fAttached)
4575	{
4576	RTListAppend(&pThis->lstDrv, &pDrv->Node);
4577	pDrv->fAttached = true;
4578	}
4579
4580	if (ppDrv)
4581	*ppDrv = pDrv;
4582	}
4583	else
4584	rc = VERR_NO_MEMORY;
4585	}
4586	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4587	LogFunc(("No attached driver for LUN #%u\n", uLUN));
4588
4589	if (RT_FAILURE(rc))
4590	{
4591	/* Only free this string on failure;
4592	* must remain valid for the live of the driver instance. */
4593	RTStrFree(pszDesc);
4594	}
4595
4596	LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
4597	return rc;
4598	}
4599
4600	/**
4601	* Detach command, internal version.
4602	*
4603	* This is called to let the device detach from a driver for a specified LUN
4604	* during runtime.
4605	*
4606	* @returns VBox status code.
4607	* @param pThis HDA state.
4608	* @param pDrv Driver to detach from device.
4609	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4610	*/
4611	static int hdaR3DetachInternal(PHDASTATE pThis, PHDADRIVER pDrv, uint32_t fFlags)
4612	{
4613	RT_NOREF(fFlags);
4614
4615	/* First, remove the driver from our list and destory it's associated streams.
4616	* This also will un-set the driver as a recording source (if associated). */
4617	hdaR3MixerRemoveDrv(pThis, pDrv);
4618
4619	/* Next, search backwards for a capable (attached) driver which now will be the
4620	* new recording source. */
4621	PHDADRIVER pDrvCur;
4622	RTListForEachReverse(&pThis->lstDrv, pDrvCur, HDADRIVER, Node)
4623	{
4624	if (!pDrvCur->pConnector)
4625	continue;
4626
4627	PDMAUDIOBACKENDCFG Cfg;
4628	int rc2 = pDrvCur->pConnector->pfnGetConfig(pDrvCur->pConnector, &Cfg);
4629	if (RT_FAILURE(rc2))
4630	continue;
4631
4632	PHDADRIVERSTREAM pDrvStrm;
4633	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
4634	pDrvStrm = &pDrvCur->MicIn;
4635	if ( pDrvStrm
4636	&& pDrvStrm->pMixStrm)
4637	{
4638	rc2 = AudioMixerSinkSetRecordingSource(pThis->SinkMicIn.pMixSink, pDrvStrm->pMixStrm);
4639	if (RT_SUCCESS(rc2))
4640	LogRel2(("HDA: Set new recording source for 'Mic In' to '%s'\n", Cfg.szName));
4641	}
4642	# endif
4643	pDrvStrm = &pDrvCur->LineIn;
4644	if ( pDrvStrm
4645	&& pDrvStrm->pMixStrm)
4646	{
4647	rc2 = AudioMixerSinkSetRecordingSource(pThis->SinkLineIn.pMixSink, pDrvStrm->pMixStrm);
4648	if (RT_SUCCESS(rc2))
4649	LogRel2(("HDA: Set new recording source for 'Line In' to '%s'\n", Cfg.szName));
4650	}
4651	}
4652
4653	LogFunc(("uLUN=%u, fFlags=0x%x\n", pDrv->uLUN, fFlags));
4654	return VINF_SUCCESS;
4655	}
4656
4657	/**
4658	* @interface_method_impl{PDMDEVREG,pfnAttach}
4659	*/
4660	static DECLCALLBACK(int) hdaR3Attach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4661	{
4662	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4663
4664	DEVHDA_LOCK_RETURN(pThis, VERR_IGNORED);
4665
4666	LogFunc(("uLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
4667
4668	PHDADRIVER pDrv;
4669	int rc2 = hdaR3AttachInternal(pThis, uLUN, fFlags, &pDrv);
4670	if (RT_SUCCESS(rc2))
4671	rc2 = hdaR3MixerAddDrv(pThis, pDrv);
4672
4673	if (RT_FAILURE(rc2))
4674	LogFunc(("Failed with %Rrc\n", rc2));
4675
4676	DEVHDA_UNLOCK(pThis);
4677
4678	return VINF_SUCCESS;
4679	}
4680
4681	/**
4682	* @interface_method_impl{PDMDEVREG,pfnDetach}
4683	*/
4684	static DECLCALLBACK(void) hdaR3Detach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4685	{
4686	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4687
4688	DEVHDA_LOCK(pThis);
4689
4690	LogFunc(("uLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
4691
4692	PHDADRIVER pDrv, pDrvNext;
4693	RTListForEachSafe(&pThis->lstDrv, pDrv, pDrvNext, HDADRIVER, Node)
4694	{
4695	if (pDrv->uLUN == uLUN)
4696	{
4697	int rc2 = hdaR3DetachInternal(pThis, pDrv, fFlags);
4698	if (RT_SUCCESS(rc2))
4699	{
4700	RTMemFree(pDrv);
4701	pDrv = NULL;
4702	}
4703
4704	break;
4705	}
4706	}
4707
4708	DEVHDA_UNLOCK(pThis);
4709	}
4710
4711	/**
4712	* Powers off the device.
4713	*
4714	* @param pDevIns Device instance to power off.
4715	*/
4716	static DECLCALLBACK(void) hdaR3PowerOff(PPDMDEVINS pDevIns)
4717	{
4718	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4719
4720	DEVHDA_LOCK_RETURN_VOID(pThis);
4721
4722	LogRel2(("HDA: Powering off ...\n"));
4723
4724	/* Ditto goes for the codec, which in turn uses the mixer. */
4725	hdaCodecPowerOff(pThis->pCodec);
4726
4727	/*
4728	* Note: Destroy the mixer while powering off and not in hdaR3Destruct,
4729	* giving the mixer the chance to release any references held to
4730	* PDM audio streams it maintains.
4731	*/
4732	if (pThis->pMixer)
4733	{
4734	AudioMixerDestroy(pThis->pMixer);
4735	pThis->pMixer = NULL;
4736	}
4737
4738	DEVHDA_UNLOCK(pThis);
4739	}
4740
4741
4742	/**
4743	* Re-attaches (replaces) a driver with a new driver.
4744	*
4745	* This is only used by to attach the Null driver when it failed to attach the
4746	* one that was configured.
4747	*
4748	* @returns VBox status code.
4749	* @param pThis Device instance to re-attach driver to.
4750	* @param pDrv Driver instance used for attaching to.
4751	* If NULL is specified, a new driver will be created and appended
4752	* to the driver list.
4753	* @param uLUN The logical unit which is being re-detached.
4754	* @param pszDriver New driver name to attach.
4755	*/
4756	static int hdaR3ReattachInternal(PHDASTATE pThis, PHDADRIVER pDrv, uint8_t uLUN, const char *pszDriver)
4757	{
4758	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
4759	AssertPtrReturn(pszDriver, VERR_INVALID_POINTER);
4760
4761	int rc;
4762
4763	if (pDrv)
4764	{
4765	rc = hdaR3DetachInternal(pThis, pDrv, 0 /* fFlags */);
4766	if (RT_SUCCESS(rc))
4767	rc = PDMDevHlpDriverDetach(pThis->pDevInsR3, PDMIBASE_2_PDMDRV(pDrv->pDrvBase), 0 /* fFlags */);
4768
4769	if (RT_FAILURE(rc))
4770	return rc;
4771
4772	pDrv = NULL;
4773	}
4774
4775	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
4776	PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
4777	PCFGMNODE pDev0 = CFGMR3GetChild(pRoot, "Devices/hda/0/");
4778
4779	/* Remove LUN branch. */
4780	CFGMR3RemoveNode(CFGMR3GetChildF(pDev0, "LUN#%u/", uLUN));
4781
4782	#define RC_CHECK() if (RT_FAILURE(rc)) { AssertReleaseRC(rc); break; }
4783
4784	do
4785	{
4786	PCFGMNODE pLunL0;
4787	rc = CFGMR3InsertNodeF(pDev0, &pLunL0, "LUN#%u/", uLUN); RC_CHECK();
4788	rc = CFGMR3InsertString(pLunL0, "Driver", "AUDIO"); RC_CHECK();
4789	rc = CFGMR3InsertNode(pLunL0, "Config/", NULL); RC_CHECK();
4790
4791	PCFGMNODE pLunL1, pLunL2;
4792	rc = CFGMR3InsertNode (pLunL0, "AttachedDriver/", &pLunL1); RC_CHECK();
4793	rc = CFGMR3InsertNode (pLunL1, "Config/", &pLunL2); RC_CHECK();
4794	rc = CFGMR3InsertString(pLunL1, "Driver", pszDriver); RC_CHECK();
4795
4796	rc = CFGMR3InsertString(pLunL2, "AudioDriver", pszDriver); RC_CHECK();
4797
4798	} while (0);
4799
4800	if (RT_SUCCESS(rc))
4801	rc = hdaR3AttachInternal(pThis, uLUN, 0 /* fFlags /, NULL / ppDrv */);
4802
4803	LogFunc(("pThis=%p, uLUN=%u, pszDriver=%s, rc=%Rrc\n", pThis, uLUN, pszDriver, rc));
4804
4805	#undef RC_CHECK
4806
4807	return rc;
4808	}
4809
4810
4811	/**
4812	* @interface_method_impl{PDMDEVREG,pfnReset}
4813	*/
4814	static DECLCALLBACK(void) hdaR3Reset(PPDMDEVINS pDevIns)
4815	{
4816	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4817
4818	LogFlowFuncEnter();
4819
4820	DEVHDA_LOCK_RETURN_VOID(pThis);
4821
4822	/*
4823	* 18.2.6,7 defines that values of this registers might be cleared on power on/reset
4824	* hdaR3Reset shouldn't affects these registers.
4825	*/
4826	HDA_REG(pThis, WAKEEN) = 0x0;
4827
4828	hdaR3GCTLReset(pThis);
4829
4830	/* Indicate that HDA is not in reset. The firmware is supposed to (un)reset HDA,
4831	* but we can take a shortcut.
4832	*/
4833	HDA_REG(pThis, GCTL) = HDA_GCTL_CRST;
4834
4835	DEVHDA_UNLOCK(pThis);
4836	}
4837
4838
4839	/**
4840	* @interface_method_impl{PDMDEVREG,pfnRelocate}
4841	*/
4842	static DECLCALLBACK(void) hdaR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
4843	{
4844	NOREF(offDelta);
4845	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4846	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4847	}
4848
4849
4850	/**
4851	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4852	*/
4853	static DECLCALLBACK(int) hdaR3Destruct(PPDMDEVINS pDevIns)
4854	{
4855	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns); /* this shall come first */
4856	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4857	DEVHDA_LOCK(pThis); /** @todo r=bird: this will fail on early constructor failure. */
4858
4859	PHDADRIVER pDrv;
4860	while (!RTListIsEmpty(&pThis->lstDrv))
4861	{
4862	pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
4863
4864	RTListNodeRemove(&pDrv->Node);
4865	RTMemFree(pDrv);
4866	}
4867
4868	if (pThis->pCodec)
4869	{
4870	hdaCodecDestruct(pThis->pCodec);
4871
4872	RTMemFree(pThis->pCodec);
4873	pThis->pCodec = NULL;
4874	}
4875
4876	RTMemFree(pThis->pu32CorbBuf);
4877	pThis->pu32CorbBuf = NULL;
4878
4879	RTMemFree(pThis->pu64RirbBuf);
4880	pThis->pu64RirbBuf = NULL;
4881
4882	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
4883	hdaR3StreamDestroy(&pThis->aStreams[i]);
4884
4885	DEVHDA_UNLOCK(pThis);
4886	return VINF_SUCCESS;
4887	}
4888
4889
4890	/**
4891	* @interface_method_impl{PDMDEVREG,pfnConstruct}
4892	*/
4893	static DECLCALLBACK(int) hdaR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4894	{
4895	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); /* this shall come first */
4896	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4897	Assert(iInstance == 0); RT_NOREF(iInstance);
4898
4899	/*
4900	* Initialize the state sufficently to make the destructor work.
4901	*/
4902	pThis->uAlignmentCheckMagic = HDASTATE_ALIGNMENT_CHECK_MAGIC;
4903	RTListInit(&pThis->lstDrv);
4904	/** @todo r=bird: There are probably other things which should be
4905	* initialized here before we start failing. */
4906
4907	/*
4908	* Validations.
4909	*/
4910	if (!CFGMR3AreValuesValid(pCfg, "RZEnabled\0"
4911	"TimerHz\0"
4912	"PosAdjustEnabled\0"
4913	"PosAdjustFrames\0"
4914	"DebugEnabled\0"
4915	"DebugPathOut\0"))
4916	{
4917	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4918	N_ ("Invalid configuration for the Intel HDA device"));
4919	}
4920
4921	int rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pThis->fRZEnabled, true);
4922	if (RT_FAILURE(rc))
4923	return PDMDEV_SET_ERROR(pDevIns, rc,
4924	N_("HDA configuration error: failed to read RCEnabled as boolean"));
4925
4926
4927	rc = CFGMR3QueryU16Def(pCfg, "TimerHz", &pThis->u16TimerHz, HDA_TIMER_HZ_DEFAULT /* Default value, if not set. */);
4928	if (RT_FAILURE(rc))
4929	return PDMDEV_SET_ERROR(pDevIns, rc,
4930	N_("HDA configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
4931
4932	if (pThis->u16TimerHz != HDA_TIMER_HZ_DEFAULT)
4933	LogRel(("HDA: Using custom device timer rate (%RU16Hz)\n", pThis->u16TimerHz));
4934
4935	rc = CFGMR3QueryBoolDef(pCfg, "PosAdjustEnabled", &pThis->fPosAdjustEnabled, true);
4936	if (RT_FAILURE(rc))
4937	return PDMDEV_SET_ERROR(pDevIns, rc,
4938	N_("HDA configuration error: failed to read position adjustment enabled as boolean"));
4939
4940	if (!pThis->fPosAdjustEnabled)
4941	LogRel(("HDA: Position adjustment is disabled\n"));
4942
4943	rc = CFGMR3QueryU16Def(pCfg, "PosAdjustFrames", &pThis->cPosAdjustFrames, HDA_POS_ADJUST_DEFAULT);
4944	if (RT_FAILURE(rc))
4945	return PDMDEV_SET_ERROR(pDevIns, rc,
4946	N_("HDA configuration error: failed to read position adjustment frames as unsigned integer"));
4947
4948	if (pThis->cPosAdjustFrames)
4949	LogRel(("HDA: Using custom position adjustment (%RU16 audio frames)\n", pThis->cPosAdjustFrames));
4950
4951	rc = CFGMR3QueryBoolDef(pCfg, "DebugEnabled", &pThis->Dbg.fEnabled, false);
4952	if (RT_FAILURE(rc))
4953	return PDMDEV_SET_ERROR(pDevIns, rc,
4954	N_("HDA configuration error: failed to read debugging enabled flag as boolean"));
4955
4956	rc = CFGMR3QueryStringDef(pCfg, "DebugPathOut", pThis->Dbg.szOutPath, sizeof(pThis->Dbg.szOutPath),
4957	VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH);
4958	if (RT_FAILURE(rc))
4959	return PDMDEV_SET_ERROR(pDevIns, rc,
4960	N_("HDA configuration error: failed to read debugging output path flag as string"));
4961
4962	if (!strlen(pThis->Dbg.szOutPath))
4963	RTStrPrintf(pThis->Dbg.szOutPath, sizeof(pThis->Dbg.szOutPath), VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH);
4964
4965	if (pThis->Dbg.fEnabled)
4966	LogRel2(("HDA: Debug output will be saved to '%s'\n", pThis->Dbg.szOutPath));
4967
4968	/*
4969	* Use an own critical section for the device instead of the default
4970	* one provided by PDM. This allows fine-grained locking in combination
4971	* with TM when timer-specific stuff is being called in e.g. the MMIO handlers.
4972	*/
4973	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "HDA");
4974	AssertRCReturn(rc, rc);
4975
4976	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4977	AssertRCReturn(rc, rc);
4978
4979	/*
4980	* Initialize data (most of it anyway).
4981	*/
4982	pThis->pDevInsR3 = pDevIns;
4983	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
4984	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4985	/* IBase */
4986	pThis->IBase.pfnQueryInterface = hdaR3QueryInterface;
4987
4988	/* PCI Device */
4989	PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
4990	PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
4991
4992	PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
4993	PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
4994	PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
4995	PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
4996	PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
4997	PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
4998	PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
4999	PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
5000	false /* fIoSpace /, false / fPrefetchable /, true / f64Bit */, 0x00000000);
5001	PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
5002	PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
5003
5004	#if defined(HDA_AS_PCI_EXPRESS)
5005	PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
5006	#elif defined(VBOX_WITH_MSI_DEVICES)
5007	PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
5008	#else
5009	PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
5010	#endif
5011
5012	/// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
5013	/// of these values needs to be properly documented!
5014	/* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
5015	PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
5016
5017	/* Power Management */
5018	PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
5019	PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
5020	PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI \| 0x02 /* version, PM1.1 */ );
5021
5022	#ifdef HDA_AS_PCI_EXPRESS
5023	/* PCI Express */
5024	PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
5025	PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
5026	/* Device flags */
5027	PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
5028	/* version */ 0x1 \|
5029	/* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) \|
5030	/* MSI */ (100) << 9 );
5031	/* Device capabilities */
5032	PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
5033	/* Device control */
5034	PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
5035	/* Device status */
5036	PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
5037	/* Link caps */
5038	PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
5039	/* Link control */
5040	PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
5041	/* Link status */
5042	PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
5043	/* Slot capabilities */
5044	PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
5045	/* Slot control */
5046	PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
5047	/* Slot status */
5048	PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
5049	/* Root control */
5050	PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
5051	/* Root capabilities */
5052	PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
5053	/* Root status */
5054	PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
5055	/* Device capabilities 2 */
5056	PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
5057	/* Device control 2 */
5058	PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
5059	/* Link control 2 */
5060	PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
5061	/* Slot control 2 */
5062	PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
5063	#endif
5064
5065	/*
5066	* Register the PCI device.
5067	*/
5068	rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
5069	if (RT_FAILURE(rc))
5070	return rc;
5071
5072	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaR3PciIoRegionMap);
5073	if (RT_FAILURE(rc))
5074	return rc;
5075
5076	#ifdef VBOX_WITH_MSI_DEVICES
5077	PDMMSIREG MsiReg;
5078	RT_ZERO(MsiReg);
5079	MsiReg.cMsiVectors = 1;
5080	MsiReg.iMsiCapOffset = 0x60;
5081	MsiReg.iMsiNextOffset = 0x50;
5082	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5083	if (RT_FAILURE(rc))
5084	{
5085	/* That's OK, we can work without MSI */
5086	PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
5087	}
5088	#endif
5089
5090	rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaR3SaveExec, hdaR3LoadExec);
5091	if (RT_FAILURE(rc))
5092	return rc;
5093
5094	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
5095	LogRel(("HDA: Asynchronous I/O enabled\n"));
5096	#endif
5097
5098	uint8_t uLUN;
5099	for (uLUN = 0; uLUN < UINT8_MAX; ++uLUN)
5100	{
5101	LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
5102	rc = hdaR3AttachInternal(pThis, uLUN, 0 /* fFlags /, NULL / ppDrv */);
5103	if (RT_FAILURE(rc))
5104	{
5105	if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5106	rc = VINF_SUCCESS;
5107	else if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
5108	{
5109	hdaR3ReattachInternal(pThis, NULL /* pDrv */, uLUN, "NullAudio");
5110	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
5111	N_("Host audio backend initialization has failed. Selecting the NULL audio backend "
5112	"with the consequence that no sound is audible"));
5113	/* Attaching to the NULL audio backend will never fail. */
5114	rc = VINF_SUCCESS;
5115	}
5116	break;
5117	}
5118	}
5119
5120	LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
5121
5122	if (RT_SUCCESS(rc))
5123	{
5124	rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
5125	if (RT_SUCCESS(rc))
5126	{
5127	/*
5128	* Add mixer output sinks.
5129	*/
5130	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
5131	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Front",
5132	AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
5133	AssertRC(rc);
5134	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Center / Subwoofer",
5135	AUDMIXSINKDIR_OUTPUT, &pThis->SinkCenterLFE.pMixSink);
5136	AssertRC(rc);
5137	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Rear",
5138	AUDMIXSINKDIR_OUTPUT, &pThis->SinkRear.pMixSink);
5139	AssertRC(rc);
5140	#else
5141	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] PCM Output",
5142	AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
5143	AssertRC(rc);
5144	#endif
5145	/*
5146	* Add mixer input sinks.
5147	*/
5148	rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Line In",
5149	AUDMIXSINKDIR_INPUT, &pThis->SinkLineIn.pMixSink);
5150	AssertRC(rc);
5151	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5152	rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Microphone In",
5153	AUDMIXSINKDIR_INPUT, &pThis->SinkMicIn.pMixSink);
5154	AssertRC(rc);
5155	#endif
5156	/* There is no master volume control. Set the master to max. */
5157	PDMAUDIOVOLUME vol = { false, 255, 255 };
5158	rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
5159	AssertRC(rc);
5160	}
5161	}
5162
5163	if (RT_SUCCESS(rc))
5164	{
5165	/* Allocate CORB buffer. */
5166	pThis->cbCorbBuf = HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE;
5167	pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
5168	if (pThis->pu32CorbBuf)
5169	{
5170	/* Allocate RIRB buffer. */
5171	pThis->cbRirbBuf = HDA_RIRB_SIZE * HDA_RIRB_ELEMENT_SIZE;
5172	pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
5173	if (pThis->pu64RirbBuf)
5174	{
5175	/* Allocate codec. */
5176	pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
5177	if (!pThis->pCodec)
5178	rc = PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
5179	}
5180	else
5181	rc = PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating RIRB"));
5182	}
5183	else
5184	rc = PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating CORB"));
5185
5186	if (RT_SUCCESS(rc))
5187	{
5188	/* Set codec callbacks to this controller. */
5189	pThis->pCodec->pfnCbMixerAddStream = hdaR3MixerAddStream;
5190	pThis->pCodec->pfnCbMixerRemoveStream = hdaR3MixerRemoveStream;
5191	pThis->pCodec->pfnCbMixerControl = hdaR3MixerControl;
5192	pThis->pCodec->pfnCbMixerSetVolume = hdaR3MixerSetVolume;
5193
5194	pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
5195
5196	/* Construct the codec. */
5197	rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfg);
5198	if (RT_FAILURE(rc))
5199	AssertRCReturn(rc, rc);
5200
5201	/* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
5202	verb F20 should provide device/codec recognition. */
5203	Assert(pThis->pCodec->u16VendorId);
5204	Assert(pThis->pCodec->u16DeviceId);
5205	PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
5206	PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
5207	}
5208	}
5209
5210	if (RT_SUCCESS(rc))
5211	{
5212	/*
5213	* Create all hardware streams.
5214	*/
5215	for (uint8_t i = 0; i < HDA_MAX_STREAMS; ++i)
5216	{
5217	/* Create the emulation timer (per stream).
5218	*
5219	* Note: Use TMCLOCK_VIRTUAL_SYNC here, as the guest's HDA driver
5220	* relies on exact (virtual) DMA timing and uses DMA Position Buffers
5221	* instead of the LPIB registers.
5222	*/
5223	char szTimer[16];
5224	RTStrPrintf2(szTimer, sizeof(szTimer), "HDA SD%RU8", i);
5225
5226	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, hdaR3Timer, &pThis->aStreams[i],
5227	TMTIMER_FLAGS_NO_CRIT_SECT, szTimer, &pThis->pTimer[i]);
5228	AssertRCReturn(rc, rc);
5229
5230	/* Use our own critcal section for the device timer.
5231	* That way we can control more fine-grained when to lock what. */
5232	rc = TMR3TimerSetCritSect(pThis->pTimer[i], &pThis->CritSect);
5233	AssertRCReturn(rc, rc);
5234
5235	rc = hdaR3StreamCreate(&pThis->aStreams[i], pThis, i /* u8SD */);
5236	AssertRC(rc);
5237	}
5238
5239	#ifdef VBOX_WITH_AUDIO_HDA_ONETIME_INIT
5240	/*
5241	* Initialize the driver chain.
5242	*/
5243	PHDADRIVER pDrv;
5244	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
5245	{
5246	/*
5247	* Only primary drivers are critical for the VM to run. Everything else
5248	* might not worth showing an own error message box in the GUI.
5249	*/
5250	if (!(pDrv->fFlags & PDMAUDIODRVFLAGS_PRIMARY))
5251	continue;
5252
5253	PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
5254	AssertPtr(pCon);
5255
5256	bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
5257	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5258	bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
5259	# endif
5260	bool fValidOut = AudioMixerStreamIsValid(pDrv->Front.pMixStrm);
5261	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
5262	/** @todo Anything to do here? */
5263	# endif
5264
5265	if ( !fValidLineIn
5266	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5267	&& !fValidMicIn
5268	# endif
5269	&& !fValidOut)
5270	{
5271	LogRel(("HDA: Falling back to NULL backend (no sound audible)\n"));
5272
5273	hdaR3Reset(pDevIns);
5274	hdaR3ReattachInternal(pThis, pDrv, pDrv->uLUN, "NullAudio");
5275
5276	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
5277	N_("No audio devices could be opened. Selecting the NULL audio backend "
5278	"with the consequence that no sound is audible"));
5279	}
5280	else
5281	{
5282	bool fWarn = false;
5283
5284	PDMAUDIOBACKENDCFG backendCfg;
5285	int rc2 = pCon->pfnGetConfig(pCon, &backendCfg);
5286	if (RT_SUCCESS(rc2))
5287	{
5288	if (backendCfg.cMaxStreamsIn)
5289	{
5290	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5291	/* If the audio backend supports two or more input streams at once,
5292	* warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
5293	if (backendCfg.cMaxStreamsIn >= 2)
5294	fWarn = !fValidLineIn \|\| !fValidMicIn;
5295	/* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
5296	* not ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
5297	* One of the two simply is not in use then. */
5298	else if (backendCfg.cMaxStreamsIn == 1)
5299	fWarn = !fValidLineIn && !fValidMicIn;
5300	/* Don't warn if our backend is not able of supporting any input streams at all. */
5301	# else /* !VBOX_WITH_AUDIO_HDA_MIC_IN */
5302	/* We only have line-in as input source. */
5303	fWarn = !fValidLineIn;
5304	# endif /* VBOX_WITH_AUDIO_HDA_MIC_IN */
5305	}
5306
5307	if ( !fWarn
5308	&& backendCfg.cMaxStreamsOut)
5309	{
5310	fWarn = !fValidOut;
5311	}
5312	}
5313	else
5314	{
5315	LogRel(("HDA: Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
5316	fWarn = true;
5317	}
5318
5319	if (fWarn)
5320	{
5321	char szMissingStreams[255];
5322	size_t len = 0;
5323	if (!fValidLineIn)
5324	{
5325	LogRel(("HDA: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
5326	len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
5327	}
5328	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5329	if (!fValidMicIn)
5330	{
5331	LogRel(("HDA: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
5332	len += RTStrPrintf(szMissingStreams + len,
5333	sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
5334	}
5335	# endif /* VBOX_WITH_AUDIO_HDA_MIC_IN */
5336	if (!fValidOut)
5337	{
5338	LogRel(("HDA: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
5339	len += RTStrPrintf(szMissingStreams + len,
5340	sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
5341	}
5342
5343	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
5344	N_("Some HDA audio streams (%s) could not be opened. Guest applications generating audio "
5345	"output or depending on audio input may hang. Make sure your host audio device "
5346	"is working properly. Check the logfile for error messages of the audio "
5347	"subsystem"), szMissingStreams);
5348	}
5349	}
5350	}
5351	#endif /* VBOX_WITH_AUDIO_HDA_ONETIME_INIT */
5352	}
5353
5354	if (RT_SUCCESS(rc))
5355	{
5356	hdaR3Reset(pDevIns);
5357
5358	/*
5359	* Debug and string formatter types.
5360	*/
5361	PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaR3DbgInfo);
5362	PDMDevHlpDBGFInfoRegister(pDevIns, "hdabdle", "HDA stream BDLE info. (hdabdle [stream number])", hdaR3DbgInfoBDLE);
5363	PDMDevHlpDBGFInfoRegister(pDevIns, "hdastream", "HDA stream info. (hdastream [stream number])", hdaR3DbgInfoStream);
5364	PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaR3DbgInfoCodecNodes);
5365	PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaR3DbgInfoCodecSelector);
5366	PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaR3DbgInfoMixer);
5367
5368	rc = RTStrFormatTypeRegister("bdle", hdaR3StrFmtBDLE, NULL);
5369	AssertRC(rc);
5370	rc = RTStrFormatTypeRegister("sdctl", hdaR3StrFmtSDCTL, NULL);
5371	AssertRC(rc);
5372	rc = RTStrFormatTypeRegister("sdsts", hdaR3StrFmtSDSTS, NULL);
5373	AssertRC(rc);
5374	rc = RTStrFormatTypeRegister("sdfifos", hdaR3StrFmtSDFIFOS, NULL);
5375	AssertRC(rc);
5376	rc = RTStrFormatTypeRegister("sdfifow", hdaR3StrFmtSDFIFOW, NULL);
5377	AssertRC(rc);
5378
5379	/*
5380	* Some debug assertions.
5381	*/
5382	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
5383	{
5384	struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
5385	struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
5386
5387	/* binary search order. */
5388	AssertReleaseMsg(!pNextReg \|\| pReg->offset + pReg->size <= pNextReg->offset,
5389	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5390	i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
5391
5392	/* alignment. */
5393	AssertReleaseMsg( pReg->size == 1
5394	\|\| (pReg->size == 2 && (pReg->offset & 1) == 0)
5395	\|\| (pReg->size == 3 && (pReg->offset & 3) == 0)
5396	\|\| (pReg->size == 4 && (pReg->offset & 3) == 0),
5397	("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5398
5399	/* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
5400	AssertRelease(((pReg->offset + pReg->size) & 3) == 0 \|\| pNextReg);
5401	if (pReg->offset & 3)
5402	{
5403	struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
5404	AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5405	if (pPrevReg)
5406	AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
5407	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5408	i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
5409	}
5410	#if 0
5411	if ((pReg->offset + pReg->size) & 3)
5412	{
5413	AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5414	if (pNextReg)
5415	AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
5416	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5417	i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
5418	}
5419	#endif
5420	/* The final entry is a full DWORD, no gaps! Allows shortcuts. */
5421	AssertReleaseMsg(pNextReg \|\| ((pReg->offset + pReg->size) & 3) == 0,
5422	("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5423	}
5424	}
5425
5426	# ifdef VBOX_WITH_STATISTICS
5427	if (RT_SUCCESS(rc))
5428	{
5429	/*
5430	* Register statistics.
5431	*/
5432	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaR3Timer.");
5433	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIn, STAMTYPE_PROFILE, "/Devices/HDA/Input", STAMUNIT_TICKS_PER_CALL, "Profiling input.");
5434	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatOut, STAMTYPE_PROFILE, "/Devices/HDA/Output", STAMUNIT_TICKS_PER_CALL, "Profiling output.");
5435	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
5436	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
5437	}
5438	# endif
5439
5440	LogFlowFuncLeaveRC(rc);
5441	return rc;
5442	}
5443
5444	/**
5445	* The device registration structure.
5446	*/
5447	const PDMDEVREG g_DeviceHDA =
5448	{
5449	/* u32Version */
5450	PDM_DEVREG_VERSION,
5451	/* szName */
5452	"hda",
5453	/* szRCMod */
5454	"VBoxDDRC.rc",
5455	/* szR0Mod */
5456	"VBoxDDR0.r0",
5457	/* pszDescription */
5458	"Intel HD Audio Controller",
5459	/* fFlags */
5460	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
5461	/* fClass */
5462	PDM_DEVREG_CLASS_AUDIO,
5463	/* cMaxInstances */
5464	1,
5465	/* cbInstance */
5466	sizeof(HDASTATE),
5467	/* pfnConstruct */
5468	hdaR3Construct,
5469	/* pfnDestruct */
5470	hdaR3Destruct,
5471	/* pfnRelocate */
5472	hdaR3Relocate,
5473	/* pfnMemSetup */
5474	NULL,
5475	/* pfnPowerOn */
5476	NULL,
5477	/* pfnReset */
5478	hdaR3Reset,
5479	/* pfnSuspend */
5480	NULL,
5481	/* pfnResume */
5482	NULL,
5483	/* pfnAttach */
5484	hdaR3Attach,
5485	/* pfnDetach */
5486	hdaR3Detach,
5487	/* pfnQueryInterface. */
5488	NULL,
5489	/* pfnInitComplete */
5490	NULL,
5491	/* pfnPowerOff */
5492	hdaR3PowerOff,
5493	/* pfnSoftReset */
5494	NULL,
5495	/* u32VersionEnd */
5496	PDM_DEVREG_VERSION
5497	};
5498
5499	#endif /* IN_RING3 */
5500	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5501

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source: vbox/trunk/src/VBox/Devices/Audio/DevHDA.cpp@ 74518

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