DevHDA.cpp@ 75864

Last change on this file since 75864 was 75864, checked in by vboxsync, 6 years ago
DevHDA: Fix for crash saving circular stream buffers.
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1	/* $Id: DevHDA.cpp 75864 2018-12-02 01:03:43Z vboxsync $ */
2	/** @file
3	* DevHDA.cpp - VBox Intel HD Audio Controller.
4	*
5	* Implemented against the specifications found in "High Definition Audio
6	* Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7	* HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8	*/
9
10	/*
11	* Copyright (C) 2006-2018 Oracle Corporation
12	*
13	* This file is part of VirtualBox Open Source Edition (OSE), as
14	* available from http://www.virtualbox.org. This file is free software;
15	* you can redistribute it and/or modify it under the terms of the GNU
16	* General Public License (GPL) as published by the Free Software
17	* Foundation, in version 2 as it comes in the "COPYING" file of the
18	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20	*/
21
22
23	/*********************************************************************************************************************************
24	* Header Files *
25	*********************************************************************************************************************************/
26	#ifdef DEBUG_bird
27	# define RT_NO_STRICT /* I'm tried of this crap asserting on save and restore of Maverics guests. */
28	#endif
29	#define LOG_GROUP LOG_GROUP_DEV_HDA
30	#include <VBox/log.h>
31
32	#include <VBox/vmm/pdmdev.h>
33	#include <VBox/vmm/pdmaudioifs.h>
34	#include <VBox/version.h>
35	#include <VBox/AssertGuest.h>
36
37	#include <iprt/assert.h>
38	#include <iprt/asm.h>
39	#include <iprt/asm-math.h>
40	#include <iprt/file.h>
41	#include <iprt/list.h>
42	#ifdef IN_RING3
43	# include <iprt/mem.h>
44	# include <iprt/semaphore.h>
45	# include <iprt/string.h>
46	# include <iprt/uuid.h>
47	#endif
48
49	#include "VBoxDD.h"
50
51	#include "AudioMixBuffer.h"
52	#include "AudioMixer.h"
53
54	#include "DevHDA.h"
55	#include "DevHDACommon.h"
56
57	#include "HDACodec.h"
58	#include "HDAStream.h"
59	# if defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT) \|\| defined(VBOX_WITH_AUDIO_HDA_51_SURROUND)
60	# include "HDAStreamChannel.h"
61	# endif
62	#include "HDAStreamMap.h"
63	#include "HDAStreamPeriod.h"
64
65	#include "DrvAudio.h"
66
67
68	/*********************************************************************************************************************************
69	* Defined Constants And Macros *
70	*********************************************************************************************************************************/
71	//#define HDA_AS_PCI_EXPRESS
72
73	/* Installs a DMA access handler (via PGM callback) to monitor
74	* HDA's DMA operations, that is, writing / reading audio stream data.
75	*
76	* !!! Note: Certain guests are that timing sensitive that when enabling !!!
77	* !!! such a handler will mess up audio completely (e.g. Windows 7). !!! */
78	//#define HDA_USE_DMA_ACCESS_HANDLER
79	#ifdef HDA_USE_DMA_ACCESS_HANDLER
80	# include <VBox/vmm/pgm.h>
81	#endif
82
83	/* Uses the DMA access handler to read the written DMA audio (output) data.
84	* Only valid if HDA_USE_DMA_ACCESS_HANDLER is set.
85	*
86	* Also see the note / warning for HDA_USE_DMA_ACCESS_HANDLER. */
87	//# define HDA_USE_DMA_ACCESS_HANDLER_WRITING
88
89	/* Useful to debug the device' timing. */
90	//#define HDA_DEBUG_TIMING
91
92	/* To debug silence coming from the guest in form of audio gaps.
93	* Very crude implementation for now. */
94	//#define HDA_DEBUG_SILENCE
95
96	#if defined(VBOX_WITH_HP_HDA)
97	/* HP Pavilion dv4t-1300 */
98	# define HDA_PCI_VENDOR_ID 0x103c
99	# define HDA_PCI_DEVICE_ID 0x30f7
100	#elif defined(VBOX_WITH_INTEL_HDA)
101	/* Intel HDA controller */
102	# define HDA_PCI_VENDOR_ID 0x8086
103	# define HDA_PCI_DEVICE_ID 0x2668
104	#elif defined(VBOX_WITH_NVIDIA_HDA)
105	/* nVidia HDA controller */
106	# define HDA_PCI_VENDOR_ID 0x10de
107	# define HDA_PCI_DEVICE_ID 0x0ac0
108	#else
109	# error "Please specify your HDA device vendor/device IDs"
110	#endif
111
112	/* Make sure that interleaving streams support is enabled if the 5.1 surround code is being used. */
113	#if defined (VBOX_WITH_AUDIO_HDA_51_SURROUND) && !defined(VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT)
114	# define VBOX_WITH_HDA_AUDIO_INTERLEAVING_STREAMS_SUPPORT
115	#endif
116
117	/**
118	* Acquires the HDA lock.
119	*/
120	#define DEVHDA_LOCK(a_pThis) \
121	do { \
122	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
123	AssertRC(rcLock); \
124	} while (0)
125
126	/**
127	* Acquires the HDA lock or returns.
128	*/
129	# define DEVHDA_LOCK_RETURN(a_pThis, a_rcBusy) \
130	do { \
131	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, a_rcBusy); \
132	if (rcLock != VINF_SUCCESS) \
133	{ \
134	AssertRC(rcLock); \
135	return rcLock; \
136	} \
137	} while (0)
138
139	/**
140	* Acquires the HDA lock or returns.
141	*/
142	# define DEVHDA_LOCK_RETURN_VOID(a_pThis) \
143	do { \
144	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
145	if (rcLock != VINF_SUCCESS) \
146	{ \
147	AssertRC(rcLock); \
148	return; \
149	} \
150	} while (0)
151
152	/**
153	* Releases the HDA lock.
154	*/
155	#define DEVHDA_UNLOCK(a_pThis) \
156	do { PDMCritSectLeave(&(a_pThis)->CritSect); } while (0)
157
158	/**
159	* Acquires the TM lock and HDA lock, returns on failure.
160	*/
161	#define DEVHDA_LOCK_BOTH_RETURN_VOID(a_pThis, a_SD) \
162	do { \
163	int rcLock = TMTimerLock((a_pThis)->pTimer[a_SD], VERR_IGNORED); \
164	if (rcLock != VINF_SUCCESS) \
165	{ \
166	AssertRC(rcLock); \
167	return; \
168	} \
169	rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
170	if (rcLock != VINF_SUCCESS) \
171	{ \
172	AssertRC(rcLock); \
173	TMTimerUnlock((a_pThis)->pTimer[a_SD]); \
174	return; \
175	} \
176	} while (0)
177
178	/**
179	* Acquires the TM lock and HDA lock, returns on failure.
180	*/
181	#define DEVHDA_LOCK_BOTH_RETURN(a_pThis, a_SD, a_rcBusy) \
182	do { \
183	int rcLock = TMTimerLock((a_pThis)->pTimer[a_SD], (a_rcBusy)); \
184	if (rcLock != VINF_SUCCESS) \
185	return rcLock; \
186	rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, (a_rcBusy)); \
187	if (rcLock != VINF_SUCCESS) \
188	{ \
189	AssertRC(rcLock); \
190	TMTimerUnlock((a_pThis)->pTimer[a_SD]); \
191	return rcLock; \
192	} \
193	} while (0)
194
195	/**
196	* Releases the HDA lock and TM lock.
197	*/
198	#define DEVHDA_UNLOCK_BOTH(a_pThis, a_SD) \
199	do { \
200	PDMCritSectLeave(&(a_pThis)->CritSect); \
201	TMTimerUnlock((a_pThis)->pTimer[a_SD]); \
202	} while (0)
203
204
205	/*********************************************************************************************************************************
206	* Structures and Typedefs *
207	*********************************************************************************************************************************/
208
209	/**
210	* Structure defining a (host backend) driver stream.
211	* Each driver has its own instances of audio mixer streams, which then
212	* can go into the same (or even different) audio mixer sinks.
213	*/
214	typedef struct HDADRIVERSTREAM
215	{
216	/** Associated mixer handle. */
217	R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
218	} HDADRIVERSTREAM, *PHDADRIVERSTREAM;
219
220	#ifdef HDA_USE_DMA_ACCESS_HANDLER
221	/**
222	* Struct for keeping an HDA DMA access handler context.
223	*/
224	typedef struct HDADMAACCESSHANDLER
225	{
226	/** Node for storing this handler in our list in HDASTREAMSTATE. */
227	RTLISTNODER3 Node;
228	/** Pointer to stream to which this access handler is assigned to. */
229	R3PTRTYPE(PHDASTREAM) pStream;
230	/** Access handler type handle. */
231	PGMPHYSHANDLERTYPE hAccessHandlerType;
232	/** First address this handler uses. */
233	RTGCPHYS GCPhysFirst;
234	/** Last address this handler uses. */
235	RTGCPHYS GCPhysLast;
236	/** Actual BDLE address to handle. */
237	RTGCPHYS BDLEAddr;
238	/** Actual BDLE buffer size to handle. */
239	RTGCPHYS BDLESize;
240	/** Whether the access handler has been registered or not. */
241	bool fRegistered;
242	uint8_t Padding[3];
243	} HDADMAACCESSHANDLER, *PHDADMAACCESSHANDLER;
244	#endif
245
246	/**
247	* Struct for maintaining a host backend driver.
248	* This driver must be associated to one, and only one,
249	* HDA codec. The HDA controller does the actual multiplexing
250	* of HDA codec data to various host backend drivers then.
251	*
252	* This HDA device uses a timer in order to synchronize all
253	* read/write accesses across all attached LUNs / backends.
254	*/
255	typedef struct HDADRIVER
256	{
257	/** Node for storing this driver in our device driver list of HDASTATE. */
258	RTLISTNODER3 Node;
259	/** Pointer to HDA controller (state). */
260	R3PTRTYPE(PHDASTATE) pHDAState;
261	/** Driver flags. */
262	PDMAUDIODRVFLAGS fFlags;
263	uint8_t u32Padding0[2];
264	/** LUN to which this driver has been assigned. */
265	uint8_t uLUN;
266	/** Whether this driver is in an attached state or not. */
267	bool fAttached;
268	/** Pointer to attached driver base interface. */
269	R3PTRTYPE(PPDMIBASE) pDrvBase;
270	/** Audio connector interface to the underlying host backend. */
271	R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
272	/** Mixer stream for line input. */
273	HDADRIVERSTREAM LineIn;
274	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
275	/** Mixer stream for mic input. */
276	HDADRIVERSTREAM MicIn;
277	#endif
278	/** Mixer stream for front output. */
279	HDADRIVERSTREAM Front;
280	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
281	/** Mixer stream for center/LFE output. */
282	HDADRIVERSTREAM CenterLFE;
283	/** Mixer stream for rear output. */
284	HDADRIVERSTREAM Rear;
285	#endif
286	} HDADRIVER;
287
288
289	/*********************************************************************************************************************************
290	* Internal Functions *
291	*********************************************************************************************************************************/
292	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
293	#ifdef IN_RING3
294	static void hdaR3GCTLReset(PHDASTATE pThis);
295	#endif
296
297	/** @name Register read/write stubs.
298	* @{
299	*/
300	static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
301	static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
302	/** @} */
303
304	/** @name Global register set read/write functions.
305	* @{
306	*/
307	static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
308	static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
309	static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
310	static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
311	static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
312	static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
313	static int hdaRegWriteCORBSIZE(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
314	static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
315	static int hdaRegWriteRINTCNT(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
316	static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
317	static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
318	static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
319	static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
320	static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
321	static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
322	/** @} */
323
324	/** @name {IOB}SDn write functions.
325	* @{
326	*/
327	static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
328	static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
329	static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
330	static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
331	static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
332	static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
333	static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
334	static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
335	static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
336	/** @} */
337
338	/** @name Generic register read/write functions.
339	* @{
340	*/
341	static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
342	static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
343	static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
344	#ifdef IN_RING3
345	static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
346	#endif
347	static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
348	static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
349	static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
350	static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
351	/** @} */
352
353	/** @name HDA device functions.
354	* @{
355	*/
356	#ifdef IN_RING3
357	static int hdaR3AddStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg);
358	static int hdaR3RemoveStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg);
359	# ifdef HDA_USE_DMA_ACCESS_HANDLER
360	static DECLCALLBACK(VBOXSTRICTRC) hdaR3DMAAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys,
361	void *pvBuf, size_t cbBuf,
362	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser);
363	# endif
364	#endif /* IN_RING3 */
365	/** @} */
366
367	/** @name HDA mixer functions.
368	* @{
369	*/
370	#ifdef IN_RING3
371	static int hdaR3MixerAddDrvStream(PHDASTATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg, PHDADRIVER pDrv);
372	#endif
373	/** @} */
374
375
376	/*********************************************************************************************************************************
377	* Global Variables *
378	*********************************************************************************************************************************/
379
380	/** No register description (RD) flags defined. */
381	#define HDA_RD_FLAG_NONE 0
382	/** Writes to SD are allowed while RUN bit is set. */
383	#define HDA_RD_FLAG_SD_WRITE_RUN RT_BIT(0)
384
385	/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
386	#define HDA_REG_MAP_STRM(offset, name) \
387	/* offset size read mask write mask flags read callback write callback index + abbrev description */ \
388	/* ------- ------- ---------- ---------- ------------------------- -------------- ----------------- ----------------------------- ----------- */ \
389	/* Offset 0x80 (SD0) */ \
390	{ offset, 0x00003, 0x00FF001F, 0x00F0001F, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL) , #name " Stream Descriptor Control" }, \
391	/* Offset 0x83 (SD0) */ \
392	{ offset + 0x3, 0x00001, 0x0000003C, 0x0000001C, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU8 , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS) , #name " Status" }, \
393	/* Offset 0x84 (SD0) */ \
394	{ offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadLPIB, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
395	/* Offset 0x88 (SD0) */ \
396	{ offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDCBL , HDA_REG_IDX_STRM(name, CBL) , #name " Cyclic Buffer Length" }, \
397	/* Offset 0x8C (SD0) */ \
398	{ offset + 0xC, 0x00002, 0x0000FFFF, 0x0000FFFF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDLVI , HDA_REG_IDX_STRM(name, LVI) , #name " Last Valid Index" }, \
399	/* Reserved: FIFO Watermark. ** @todo Document this! */ \
400	{ offset + 0xE, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
401	/* Offset 0x90 (SD0) */ \
402	{ offset + 0x10, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
403	/* Offset 0x92 (SD0) */ \
404	{ offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFMT , HDA_REG_IDX_STRM(name, FMT) , #name " Stream Format" }, \
405	/* Reserved: 0x94 - 0x98. */ \
406	/* Offset 0x98 (SD0) */ \
407	{ offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
408	/* Offset 0x9C (SD0) */ \
409	{ offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
410
411	/** Defines a single audio stream register set (e.g. OSD0). */
412	#define HDA_REG_MAP_DEF_STREAM(index, name) \
413	HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
414
415	/* See 302349 p 6.2. */
416	const HDAREGDESC g_aHdaRegMap[HDA_NUM_REGS] =
417	{
418	/* offset size read mask write mask flags read callback write callback index + abbrev */
419	/------- ------- ---------- ---------- ----------------- ---------------- ------------------- ------------------------ /
420	{ 0x00000, 0x00002, 0x0000FFFB, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(GCAP) }, /* Global Capabilities */
421	{ 0x00002, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMIN) }, /* Minor Version */
422	{ 0x00003, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMAJ) }, /* Major Version */
423	{ 0x00004, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTPAY) }, /* Output Payload Capabilities */
424	{ 0x00006, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INPAY) }, /* Input Payload Capabilities */
425	{ 0x00008, 0x00004, 0x00000103, 0x00000103, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteGCTL , HDA_REG_IDX(GCTL) }, /* Global Control */
426	{ 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(WAKEEN) }, /* Wake Enable */
427	{ 0x0000e, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteSTATESTS, HDA_REG_IDX(STATESTS) }, /* State Change Status */
428	{ 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadUnimpl, hdaRegWriteUnimpl , HDA_REG_IDX(GSTS) }, /* Global Status */
429	{ 0x00018, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTSTRMPAY) }, /* Output Stream Payload Capability */
430	{ 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INSTRMPAY) }, /* Input Stream Payload Capability */
431	{ 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */
432	{ 0x00024, 0x00004, 0xC00000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */
433	{ 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadWALCLK, hdaRegWriteUnimpl , HDA_REG_IDX_NOMEM(WALCLK) }, /* Wall Clock Counter */
434	{ 0x00034, 0x00004, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */
435	{ 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
436	{ 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBUBASE) }, /* CORB Upper Base Address */
437	{ 0x00048, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteCORBWP , HDA_REG_IDX(CORBWP) }, /* CORB Write Pointer */
438	{ 0x0004A, 0x00002, 0x000080FF, 0x00008000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteCORBRP , HDA_REG_IDX(CORBRP) }, /* CORB Read Pointer */
439	{ 0x0004C, 0x00001, 0x00000003, 0x00000003, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL) }, /* CORB Control */
440	{ 0x0004D, 0x00001, 0x00000001, 0x00000001, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS) }, /* CORB Status */
441	{ 0x0004E, 0x00001, 0x000000F3, 0x00000003, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBSIZE, HDA_REG_IDX(CORBSIZE) }, /* CORB Size */
442	{ 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBLBASE) }, /* RIRB Lower Base Address */
443	{ 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBUBASE) }, /* RIRB Upper Base Address */
444	{ 0x00058, 0x00002, 0x000000FF, 0x00008000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteRIRBWP , HDA_REG_IDX(RIRBWP) }, /* RIRB Write Pointer */
445	{ 0x0005A, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteRINTCNT , HDA_REG_IDX(RINTCNT) }, /* Response Interrupt Count */
446	{ 0x0005C, 0x00001, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteU8 , HDA_REG_IDX(RIRBCTL) }, /* RIRB Control */
447	{ 0x0005D, 0x00001, 0x00000005, 0x00000005, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS) }, /* RIRB Status */
448	{ 0x0005E, 0x00001, 0x000000F3, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(RIRBSIZE) }, /* RIRB Size */
449	{ 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(IC) }, /* Immediate Command */
450	{ 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(IR) }, /* Immediate Response */
451	{ 0x00068, 0x00002, 0x00000002, 0x00000002, HDA_RD_FLAG_NONE, hdaRegReadIRS , hdaRegWriteIRS , HDA_REG_IDX(IRS) }, /* Immediate Command Status */
452	{ 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPLBASE) }, /* DMA Position Lower Base */
453	{ 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPUBASE) }, /* DMA Position Upper Base */
454	/* 4 Serial Data In (SDI). */
455	HDA_REG_MAP_DEF_STREAM(0, SD0),
456	HDA_REG_MAP_DEF_STREAM(1, SD1),
457	HDA_REG_MAP_DEF_STREAM(2, SD2),
458	HDA_REG_MAP_DEF_STREAM(3, SD3),
459	/* 4 Serial Data Out (SDO). */
460	HDA_REG_MAP_DEF_STREAM(4, SD4),
461	HDA_REG_MAP_DEF_STREAM(5, SD5),
462	HDA_REG_MAP_DEF_STREAM(6, SD6),
463	HDA_REG_MAP_DEF_STREAM(7, SD7)
464	};
465
466	const HDAREGALIAS g_aHdaRegAliases[] =
467	{
468	{ 0x2084, HDA_REG_SD0LPIB },
469	{ 0x20a4, HDA_REG_SD1LPIB },
470	{ 0x20c4, HDA_REG_SD2LPIB },
471	{ 0x20e4, HDA_REG_SD3LPIB },
472	{ 0x2104, HDA_REG_SD4LPIB },
473	{ 0x2124, HDA_REG_SD5LPIB },
474	{ 0x2144, HDA_REG_SD6LPIB },
475	{ 0x2164, HDA_REG_SD7LPIB }
476	};
477
478	#ifdef IN_RING3
479
480	/** HDABDLEDESC field descriptors for the v7 saved state. */
481	static SSMFIELD const g_aSSMBDLEDescFields7[] =
482	{
483	SSMFIELD_ENTRY(HDABDLEDESC, u64BufAdr),
484	SSMFIELD_ENTRY(HDABDLEDESC, u32BufSize),
485	SSMFIELD_ENTRY(HDABDLEDESC, fFlags),
486	SSMFIELD_ENTRY_TERM()
487	};
488
489	/** HDABDLESTATE field descriptors for the v6+ saved state. */
490	static SSMFIELD const g_aSSMBDLEStateFields6[] =
491	{
492	SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
493	SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
494	SSMFIELD_ENTRY_OLD(FIFO, HDA_FIFO_MAX), /* Deprecated; now is handled in the stream's circular buffer. */
495	SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
496	SSMFIELD_ENTRY_TERM()
497	};
498
499	/** HDABDLESTATE field descriptors for the v7 saved state. */
500	static SSMFIELD const g_aSSMBDLEStateFields7[] =
501	{
502	SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
503	SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
504	SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
505	SSMFIELD_ENTRY_TERM()
506	};
507
508	/** HDASTREAMSTATE field descriptors for the v6 saved state. */
509	static SSMFIELD const g_aSSMStreamStateFields6[] =
510	{
511	SSMFIELD_ENTRY_OLD(cBDLE, sizeof(uint16_t)), /* Deprecated. */
512	SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
513	SSMFIELD_ENTRY_OLD(fStop, 1), /* Deprecated; see SSMR3PutBool(). */
514	SSMFIELD_ENTRY_OLD(fRunning, 1), /* Deprecated; using the HDA_SDCTL_RUN bit is sufficient. */
515	SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
516	SSMFIELD_ENTRY_TERM()
517	};
518
519	/** HDASTREAMSTATE field descriptors for the v7 saved state. */
520	static SSMFIELD const g_aSSMStreamStateFields7[] =
521	{
522	SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
523	SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
524	SSMFIELD_ENTRY(HDASTREAMSTATE, tsTransferNext),
525	SSMFIELD_ENTRY_TERM()
526	};
527
528	/** HDASTREAMPERIOD field descriptors for the v7 saved state. */
529	static SSMFIELD const g_aSSMStreamPeriodFields7[] =
530	{
531	SSMFIELD_ENTRY(HDASTREAMPERIOD, u64StartWalClk),
532	SSMFIELD_ENTRY(HDASTREAMPERIOD, u64ElapsedWalClk),
533	SSMFIELD_ENTRY(HDASTREAMPERIOD, framesTransferred),
534	SSMFIELD_ENTRY(HDASTREAMPERIOD, cIntPending),
535	SSMFIELD_ENTRY_TERM()
536	};
537
538	/**
539	* 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
540	*/
541	static uint32_t const g_afMasks[5] =
542	{
543	UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
544	};
545
546	#endif /* IN_RING3 */
547
548
549
550	/**
551	* Retrieves the number of bytes of a FIFOW register.
552	*
553	* @return Number of bytes of a given FIFOW register.
554	*/
555	DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
556	{
557	uint32_t cb;
558	switch (u32RegFIFOW)
559	{
560	case HDA_SDFIFOW_8B: cb = 8; break;
561	case HDA_SDFIFOW_16B: cb = 16; break;
562	case HDA_SDFIFOW_32B: cb = 32; break;
563	default: cb = 0; break;
564	}
565
566	Assert(RT_IS_POWER_OF_TWO(cb));
567	return cb;
568	}
569
570	#ifdef IN_RING3
571	/**
572	* Reschedules pending interrupts for all audio streams which have complete
573	* audio periods but did not have the chance to issue their (pending) interrupts yet.
574	*
575	* @param pThis The HDA device state.
576	*/
577	static void hdaR3ReschedulePendingInterrupts(PHDASTATE pThis)
578	{
579	bool fInterrupt = false;
580
581	for (uint8_t i = 0; i < HDA_MAX_STREAMS; ++i)
582	{
583	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, i);
584	if (!pStream)
585	continue;
586
587	if ( hdaR3StreamPeriodIsComplete (&pStream->State.Period)
588	&& hdaR3StreamPeriodNeedsInterrupt(&pStream->State.Period)
589	&& hdaR3WalClkSet(pThis, hdaR3StreamPeriodGetAbsElapsedWalClk(&pStream->State.Period), false /* fForce */))
590	{
591	fInterrupt = true;
592	break;
593	}
594	}
595
596	LogFunc(("fInterrupt=%RTbool\n", fInterrupt));
597
598	# ifndef LOG_ENABLED
599	hdaProcessInterrupt(pThis);
600	# else
601	hdaProcessInterrupt(pThis, __FUNCTION__);
602	# endif
603	}
604	#endif /* IN_RING3 */
605
606	/**
607	* Looks up a register at the exact offset given by @a offReg.
608	*
609	* @returns Register index on success, -1 if not found.
610	* @param offReg The register offset.
611	*/
612	static int hdaRegLookup(uint32_t offReg)
613	{
614	/*
615	* Aliases.
616	*/
617	if (offReg >= g_aHdaRegAliases[0].offReg)
618	{
619	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
620	if (offReg == g_aHdaRegAliases[i].offReg)
621	return g_aHdaRegAliases[i].idxAlias;
622	Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
623	return -1;
624	}
625
626	/*
627	* Binary search the
628	*/
629	int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
630	int idxLow = 0;
631	for (;;)
632	{
633	int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
634	if (offReg < g_aHdaRegMap[idxMiddle].offset)
635	{
636	if (idxLow == idxMiddle)
637	break;
638	idxEnd = idxMiddle;
639	}
640	else if (offReg > g_aHdaRegMap[idxMiddle].offset)
641	{
642	idxLow = idxMiddle + 1;
643	if (idxLow >= idxEnd)
644	break;
645	}
646	else
647	return idxMiddle;
648	}
649
650	#ifdef RT_STRICT
651	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
652	Assert(g_aHdaRegMap[i].offset != offReg);
653	#endif
654	return -1;
655	}
656
657	#ifdef IN_RING3
658
659	/**
660	* Looks up a register covering the offset given by @a offReg.
661	*
662	* @returns Register index on success, -1 if not found.
663	* @param offReg The register offset.
664	*/
665	static int hdaR3RegLookupWithin(uint32_t offReg)
666	{
667	/*
668	* Aliases.
669	*/
670	if (offReg >= g_aHdaRegAliases[0].offReg)
671	{
672	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
673	{
674	uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
675	if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
676	return g_aHdaRegAliases[i].idxAlias;
677	}
678	Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
679	return -1;
680	}
681
682	/*
683	* Binary search the register map.
684	*/
685	int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
686	int idxLow = 0;
687	for (;;)
688	{
689	int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
690	if (offReg < g_aHdaRegMap[idxMiddle].offset)
691	{
692	if (idxLow == idxMiddle)
693	break;
694	idxEnd = idxMiddle;
695	}
696	else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
697	{
698	idxLow = idxMiddle + 1;
699	if (idxLow >= idxEnd)
700	break;
701	}
702	else
703	return idxMiddle;
704	}
705
706	# ifdef RT_STRICT
707	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
708	Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
709	# endif
710	return -1;
711	}
712
713
714	/**
715	* Synchronizes the CORB / RIRB buffers between internal <-> device state.
716	*
717	* @returns IPRT status code.
718	* @param pThis HDA state.
719	* @param fLocal Specify true to synchronize HDA state's CORB buffer with the device state,
720	* or false to synchronize the device state's RIRB buffer with the HDA state.
721	*
722	* @todo r=andy Break this up into two functions?
723	*/
724	static int hdaR3CmdSync(PHDASTATE pThis, bool fLocal)
725	{
726	int rc = VINF_SUCCESS;
727	if (fLocal)
728	{
729	if (pThis->u64CORBBase)
730	{
731	AssertPtr(pThis->pu32CorbBuf);
732	Assert(pThis->cbCorbBuf);
733
734	/** @todo r=bird: An explanation is required why PDMDevHlpPhysRead is used with
735	* the CORB and PDMDevHlpPCIPhysWrite with RIRB below. There are
736	* similar unexplained inconsistencies in DevHDACommon.cpp. */
737	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
738	Log(("hdaR3CmdSync/CORB: read %RGp LB %#x (%Rrc)\n", pThis->u64CORBBase, pThis->cbCorbBuf, rc));
739	AssertRCReturn(rc, rc);
740	}
741	}
742	else
743	{
744	if (pThis->u64RIRBBase)
745	{
746	AssertPtr(pThis->pu64RirbBuf);
747	Assert(pThis->cbRirbBuf);
748
749	rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
750	Log(("hdaR3CmdSync/RIRB: phys read %RGp LB %#x (%Rrc)\n", pThis->u64RIRBBase, pThis->pu64RirbBuf, rc));
751	AssertRCReturn(rc, rc);
752	}
753	}
754
755	# ifdef DEBUG_CMD_BUFFER
756	LogFunc(("fLocal=%RTbool\n", fLocal));
757
758	uint8_t i = 0;
759	do
760	{
761	LogFunc(("CORB%02x: ", i));
762	uint8_t j = 0;
763	do
764	{
765	const char *pszPrefix;
766	if ((i + j) == HDA_REG(pThis, CORBRP))
767	pszPrefix = "[R]";
768	else if ((i + j) == HDA_REG(pThis, CORBWP))
769	pszPrefix = "[W]";
770	else
771	pszPrefix = " "; /* three spaces */
772	Log((" %s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
773	j++;
774	} while (j < 8);
775	Log(("\n"));
776	i += 8;
777	} while(i != 0);
778
779	do
780	{
781	LogFunc(("RIRB%02x: ", i));
782	uint8_t j = 0;
783	do
784	{
785	const char *prefix;
786	if ((i + j) == HDA_REG(pThis, RIRBWP))
787	prefix = "[W]";
788	else
789	prefix = " ";
790	Log((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
791	} while (++j < 8);
792	Log(("\n"));
793	i += 8;
794	} while (i != 0);
795	# endif
796	return rc;
797	}
798
799	/**
800	* Processes the next CORB buffer command in the queue.
801	*
802	* This will invoke the HDA codec verb dispatcher.
803	*
804	* @returns IPRT status code.
805	* @param pThis HDA state.
806	*/
807	static int hdaR3CORBCmdProcess(PHDASTATE pThis)
808	{
809	uint8_t corbRp = HDA_REG(pThis, CORBRP);
810	uint8_t corbWp = HDA_REG(pThis, CORBWP);
811	uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
812
813	Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", corbRp, corbWp, rirbWp));
814
815	if (!(HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA))
816	{
817	LogFunc(("CORB DMA not active, skipping\n"));
818	return VINF_SUCCESS;
819	}
820
821	Assert(pThis->cbCorbBuf);
822
823	int rc = hdaR3CmdSync(pThis, true /* Sync from guest */);
824	AssertRCReturn(rc, rc);
825
826	uint16_t cIntCnt = HDA_REG(pThis, RINTCNT) & 0xff;
827
828	if (!cIntCnt) /* 0 means 256 interrupts. */
829	cIntCnt = HDA_MAX_RINTCNT;
830
831	Log3Func(("START CORB(RP:%x, WP:%x) RIRBWP:%x, RINTCNT:%RU8/%RU8\n",
832	corbRp, corbWp, rirbWp, pThis->u16RespIntCnt, cIntCnt));
833
834	while (corbRp != corbWp)
835	{
836	corbRp = (corbRp + 1) % (pThis->cbCorbBuf / HDA_CORB_ELEMENT_SIZE); /* Advance +1 as the first command(s) are at CORBWP + 1. */
837
838	uint32_t uCmd = pThis->pu32CorbBuf[corbRp];
839	uint64_t uResp = 0;
840
841	rc = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(uCmd, 0 /* Codec index */), &uResp);
842	if (RT_FAILURE(rc))
843	LogFunc(("Codec lookup failed with rc=%Rrc\n", rc));
844
845	Log3Func(("Codec verb %08x -> response %016lx\n", uCmd, uResp));
846
847	if ( (uResp & CODEC_RESPONSE_UNSOLICITED)
848	&& !(HDA_REG(pThis, GCTL) & HDA_GCTL_UNSOL))
849	{
850	LogFunc(("Unexpected unsolicited response.\n"));
851	HDA_REG(pThis, CORBRP) = corbRp;
852
853	/** @todo r=andy No CORB/RIRB syncing to guest required in that case? */
854	return rc;
855	}
856
857	rirbWp = (rirbWp + 1) % HDA_RIRB_SIZE;
858
859	pThis->pu64RirbBuf[rirbWp] = uResp;
860
861	pThis->u16RespIntCnt++;
862
863	bool fSendInterrupt = false;
864
865	if (pThis->u16RespIntCnt == cIntCnt) /* Response interrupt count reached? */
866	{
867	pThis->u16RespIntCnt = 0; /* Reset internal interrupt response counter. */
868
869	Log3Func(("Response interrupt count reached (%RU16)\n", pThis->u16RespIntCnt));
870	fSendInterrupt = true;
871
872	}
873	else if (corbRp == corbWp) /* Did we reach the end of the current command buffer? */
874	{
875	Log3Func(("Command buffer empty\n"));
876	fSendInterrupt = true;
877	}
878
879	if (fSendInterrupt)
880	{
881	if (HDA_REG(pThis, RIRBCTL) & HDA_RIRBCTL_RINTCTL) /* Response Interrupt Control (RINTCTL) enabled? */
882	{
883	HDA_REG(pThis, RIRBSTS) \|= HDA_RIRBSTS_RINTFL;
884
885	# ifndef LOG_ENABLED
886	rc = hdaProcessInterrupt(pThis);
887	# else
888	rc = hdaProcessInterrupt(pThis, __FUNCTION__);
889	# endif
890	}
891	}
892	}
893
894	Log3Func(("END CORB(RP:%x, WP:%x) RIRBWP:%x, RINTCNT:%RU8/%RU8\n",
895	corbRp, corbWp, rirbWp, pThis->u16RespIntCnt, cIntCnt));
896
897	HDA_REG(pThis, CORBRP) = corbRp;
898	HDA_REG(pThis, RIRBWP) = rirbWp;
899
900	rc = hdaR3CmdSync(pThis, false /* Sync to guest */);
901	AssertRCReturn(rc, rc);
902
903	if (RT_FAILURE(rc))
904	AssertRCReturn(rc, rc);
905
906	return rc;
907	}
908
909	#endif /* IN_RING3 */
910
911	/* Register access handlers. */
912
913	static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
914	{
915	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg);
916	*pu32Value = 0;
917	return VINF_SUCCESS;
918	}
919
920	static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
921	{
922	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
923	return VINF_SUCCESS;
924	}
925
926	/* U8 */
927	static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
928	{
929	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
930	return hdaRegReadU32(pThis, iReg, pu32Value);
931	}
932
933	static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
934	{
935	Assert((u32Value & 0xffffff00) == 0);
936	return hdaRegWriteU32(pThis, iReg, u32Value);
937	}
938
939	/* U16 */
940	static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
941	{
942	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
943	return hdaRegReadU32(pThis, iReg, pu32Value);
944	}
945
946	static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
947	{
948	Assert((u32Value & 0xffff0000) == 0);
949	return hdaRegWriteU32(pThis, iReg, u32Value);
950	}
951
952	/* U24 */
953	static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
954	{
955	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
956	return hdaRegReadU32(pThis, iReg, pu32Value);
957	}
958
959	#ifdef IN_RING3
960	static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
961	{
962	Assert((u32Value & 0xff000000) == 0);
963	return hdaRegWriteU32(pThis, iReg, u32Value);
964	}
965	#endif
966
967	/* U32 */
968	static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
969	{
970	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
971
972	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
973
974	*pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
975
976	DEVHDA_UNLOCK(pThis);
977	return VINF_SUCCESS;
978	}
979
980	static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
981	{
982	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
983
984	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
985
986	pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
987	\| (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
988	DEVHDA_UNLOCK(pThis);
989	return VINF_SUCCESS;
990	}
991
992	static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
993	{
994	RT_NOREF_PV(iReg);
995	#ifdef IN_RING3
996	DEVHDA_LOCK(pThis);
997	#else
998	if (!(u32Value & HDA_GCTL_CRST))
999	return VINF_IOM_R3_MMIO_WRITE;
1000	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1001	#endif
1002
1003	if (u32Value & HDA_GCTL_CRST)
1004	{
1005	/* Set the CRST bit to indicate that we're leaving reset mode. */
1006	HDA_REG(pThis, GCTL) \|= HDA_GCTL_CRST;
1007	LogFunc(("Guest leaving HDA reset\n"));
1008	}
1009	else
1010	{
1011	#ifdef IN_RING3
1012	/* Enter reset state. */
1013	LogFunc(("Guest entering HDA reset with DMA(RIRB:%s, CORB:%s)\n",
1014	HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA ? "on" : "off",
1015	HDA_REG(pThis, RIRBCTL) & HDA_RIRBCTL_RDMAEN ? "on" : "off"));
1016
1017	/* Clear the CRST bit to indicate that we're in reset state. */
1018	HDA_REG(pThis, GCTL) &= ~HDA_GCTL_CRST;
1019
1020	hdaR3GCTLReset(pThis);
1021	#else
1022	AssertFailedReturnStmt(DEVHDA_UNLOCK(pThis), VINF_IOM_R3_MMIO_WRITE);
1023	#endif
1024	}
1025
1026	if (u32Value & HDA_GCTL_FCNTRL)
1027	{
1028	/* Flush: GSTS:1 set, see 6.2.6. */
1029	HDA_REG(pThis, GSTS) \|= HDA_GSTS_FSTS; /* Set the flush status. */
1030	/* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
1031	}
1032
1033	DEVHDA_UNLOCK(pThis);
1034	return VINF_SUCCESS;
1035	}
1036
1037	static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1038	{
1039	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1040
1041	uint32_t v = HDA_REG_IND(pThis, iReg);
1042	uint32_t nv = u32Value & HDA_STATESTS_SCSF_MASK;
1043
1044	HDA_REG(pThis, STATESTS) &= ~(v & nv); /* Write of 1 clears corresponding bit. */
1045
1046	DEVHDA_UNLOCK(pThis);
1047	return VINF_SUCCESS;
1048	}
1049
1050	static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1051	{
1052	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
1053
1054	const uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
1055	uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, uSD);
1056	#ifdef LOG_ENABLED
1057	const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, uSD);
1058	LogFlowFunc(("[SD%RU8] LPIB=%RU32, CBL=%RU32\n", uSD, u32LPIB, u32CBL));
1059	#endif
1060
1061	*pu32Value = u32LPIB;
1062
1063	DEVHDA_UNLOCK(pThis);
1064	return VINF_SUCCESS;
1065	}
1066
1067	#ifdef IN_RING3
1068	/**
1069	* Returns the current maximum value the wall clock counter can be set to.
1070	* This maximum value depends on all currently handled HDA streams and their own current timing.
1071	*
1072	* @return Current maximum value the wall clock counter can be set to.
1073	* @param pThis HDA state.
1074	*
1075	* @remark Does not actually set the wall clock counter.
1076	*/
1077	static uint64_t hdaR3WalClkGetMax(PHDASTATE pThis)
1078	{
1079	const uint64_t u64WalClkCur = ASMAtomicReadU64(&pThis->u64WalClk);
1080	const uint64_t u64FrontAbsWalClk = pThis->SinkFront.pStream
1081	? hdaR3StreamPeriodGetAbsElapsedWalClk(&pThis->SinkFront.pStream->State.Period) : 0;
1082	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1083	# error "Implement me!"
1084	# endif
1085	const uint64_t u64LineInAbsWalClk = pThis->SinkLineIn.pStream
1086	? hdaR3StreamPeriodGetAbsElapsedWalClk(&pThis->SinkLineIn.pStream->State.Period) : 0;
1087	# ifdef VBOX_WITH_HDA_MIC_IN
1088	const uint64_t u64MicInAbsWalClk = pThis->SinkMicIn.pStream
1089	? hdaR3StreamPeriodGetAbsElapsedWalClk(&pThis->SinkMicIn.pStream->State.Period) : 0;
1090	# endif
1091
1092	uint64_t u64WalClkNew = RT_MAX(u64WalClkCur, u64FrontAbsWalClk);
1093	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1094	# error "Implement me!"
1095	# endif
1096	u64WalClkNew = RT_MAX(u64WalClkNew, u64LineInAbsWalClk);
1097	# ifdef VBOX_WITH_HDA_MIC_IN
1098	u64WalClkNew = RT_MAX(u64WalClkNew, u64MicInAbsWalClk);
1099	# endif
1100
1101	Log3Func(("%RU64 -> Front=%RU64, LineIn=%RU64 -> %RU64\n",
1102	u64WalClkCur, u64FrontAbsWalClk, u64LineInAbsWalClk, u64WalClkNew));
1103
1104	return u64WalClkNew;
1105	}
1106	#endif /* IN_RING3 */
1107
1108	static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1109	{
1110	#ifdef IN_RING3
1111	RT_NOREF(iReg);
1112
1113	DEVHDA_LOCK(pThis);
1114
1115	*pu32Value = RT_LO_U32(ASMAtomicReadU64(&pThis->u64WalClk));
1116
1117	Log3Func(("%RU32 (max @ %RU64)\n",*pu32Value, hdaR3WalClkGetMax(pThis)));
1118
1119	DEVHDA_UNLOCK(pThis);
1120	return VINF_SUCCESS;
1121	#else
1122	RT_NOREF(pThis, iReg, pu32Value);
1123	return VINF_IOM_R3_MMIO_READ;
1124	#endif
1125	}
1126
1127	static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1128	{
1129	RT_NOREF(iReg);
1130	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1131
1132	if (u32Value & HDA_CORBRP_RST)
1133	{
1134	/* Do a CORB reset. */
1135	if (pThis->cbCorbBuf)
1136	{
1137	#ifdef IN_RING3
1138	Assert(pThis->pu32CorbBuf);
1139	RT_BZERO((void *)pThis->pu32CorbBuf, pThis->cbCorbBuf);
1140	#else
1141	DEVHDA_UNLOCK(pThis);
1142	return VINF_IOM_R3_MMIO_WRITE;
1143	#endif
1144	}
1145
1146	LogRel2(("HDA: CORB reset\n"));
1147
1148	HDA_REG(pThis, CORBRP) = HDA_CORBRP_RST; /* Clears the pointer. */
1149	}
1150	else
1151	HDA_REG(pThis, CORBRP) &= ~HDA_CORBRP_RST; /* Only CORBRP_RST bit is writable. */
1152
1153	DEVHDA_UNLOCK(pThis);
1154	return VINF_SUCCESS;
1155	}
1156
1157	static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1158	{
1159	#ifdef IN_RING3
1160	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1161
1162	int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1163	AssertRC(rc);
1164
1165	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Start DMA engine. */
1166	{
1167	rc = hdaR3CORBCmdProcess(pThis);
1168	}
1169	else
1170	LogFunc(("CORB DMA not running, skipping\n"));
1171
1172	DEVHDA_UNLOCK(pThis);
1173	return rc;
1174	#else
1175	RT_NOREF(pThis, iReg, u32Value);
1176	return VINF_IOM_R3_MMIO_WRITE;
1177	#endif
1178	}
1179
1180	static int hdaRegWriteCORBSIZE(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1181	{
1182	#ifdef IN_RING3
1183	RT_NOREF(iReg);
1184	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1185
1186	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
1187	{
1188	LogFunc(("CORB DMA is (still) running, skipping\n"));
1189
1190	DEVHDA_UNLOCK(pThis);
1191	return VINF_SUCCESS;
1192	}
1193
1194	u32Value = (u32Value & HDA_CORBSIZE_SZ);
1195
1196	uint16_t cEntries = HDA_CORB_SIZE; /* Set default. */
1197
1198	switch (u32Value)
1199	{
1200	case 0: /* 8 byte; 2 entries. */
1201	cEntries = 2;
1202	break;
1203
1204	case 1: /* 64 byte; 16 entries. */
1205	cEntries = 16;
1206	break;
1207
1208	case 2: /* 1 KB; 256 entries. */
1209	/* Use default size. */
1210	break;
1211
1212	default:
1213	LogRel(("HDA: Guest tried to set an invalid CORB size (0x%x), keeping default\n", u32Value));
1214	u32Value = 2;
1215	/* Use default size. */
1216	break;
1217	}
1218
1219	uint32_t cbCorbBuf = cEntries * HDA_CORB_ELEMENT_SIZE;
1220	Assert(cbCorbBuf <= HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE); /* Paranoia. */
1221
1222	if (cbCorbBuf != pThis->cbCorbBuf)
1223	{
1224	RT_BZERO(pThis->pu32CorbBuf, HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE); /* Clear CORB when setting a new size. */
1225	pThis->cbCorbBuf = cbCorbBuf;
1226	}
1227
1228	LogFunc(("CORB buffer size is now %RU32 bytes (%u entries)\n", pThis->cbCorbBuf, pThis->cbCorbBuf / HDA_CORB_ELEMENT_SIZE));
1229
1230	HDA_REG(pThis, CORBSIZE) = u32Value;
1231
1232	DEVHDA_UNLOCK(pThis);
1233	return VINF_SUCCESS;
1234	#else
1235	RT_NOREF(pThis, iReg, u32Value);
1236	return VINF_IOM_R3_MMIO_WRITE;
1237	#endif
1238	}
1239
1240	static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1241	{
1242	RT_NOREF_PV(iReg);
1243	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1244
1245	uint32_t v = HDA_REG(pThis, CORBSTS);
1246	HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1247
1248	DEVHDA_UNLOCK(pThis);
1249	return VINF_SUCCESS;
1250	}
1251
1252	static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1253	{
1254	#ifdef IN_RING3
1255	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1256
1257	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
1258	AssertRCSuccess(rc);
1259
1260	rc = hdaR3CORBCmdProcess(pThis);
1261
1262	DEVHDA_UNLOCK(pThis);
1263	return rc;
1264	#else
1265	RT_NOREF(pThis, iReg, u32Value);
1266	return VINF_IOM_R3_MMIO_WRITE;
1267	#endif
1268	}
1269
1270	static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1271	{
1272	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1273
1274	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, CBL, iReg));
1275	if (pStream)
1276	{
1277	pStream->u32CBL = u32Value;
1278	LogFlowFunc(("[SD%RU8] CBL=%RU32\n", pStream->u8SD, u32Value));
1279	}
1280	else
1281	LogFunc(("[SD%RU8] Warning: Changing SDCBL on non-attached stream (0x%x)\n",
1282	HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
1283
1284	int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1285	AssertRCSuccess(rc);
1286
1287	DEVHDA_UNLOCK(pThis);
1288	return rc;
1289	}
1290
1291	static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1292	{
1293	#ifdef IN_RING3
1294	/* Get the stream descriptor. */
1295	const uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
1296
1297	DEVHDA_LOCK_BOTH_RETURN(pThis, uSD, VINF_IOM_R3_MMIO_WRITE);
1298
1299	/*
1300	* Some guests write too much (that is, 32-bit with the top 8 bit being junk)
1301	* instead of 24-bit required for SDCTL. So just mask this here to be safe.
1302	*/
1303	u32Value &= 0x00ffffff;
1304
1305	bool fRun = RT_BOOL(u32Value & HDA_SDCTL_RUN);
1306	bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_SDCTL_RUN);
1307
1308	bool fReset = RT_BOOL(u32Value & HDA_SDCTL_SRST);
1309	bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_SDCTL_SRST);
1310
1311	LogFunc(("[SD%RU8] fRun=%RTbool, fInRun=%RTbool, fReset=%RTbool, fInReset=%RTbool, %R[sdctl]\n",
1312	uSD, fRun, fInRun, fReset, fInReset, u32Value));
1313
1314	/*
1315	* Extract the stream tag the guest wants to use for this specific
1316	* stream descriptor (SDn). This only can happen if the stream is in a non-running
1317	* state, so we're doing the lookup and assignment here.
1318	*
1319	* So depending on the guest OS, SD3 can use stream tag 4, for example.
1320	*/
1321	uint8_t uTag = (u32Value >> HDA_SDCTL_NUM_SHIFT) & HDA_SDCTL_NUM_MASK;
1322	if (uTag > HDA_MAX_TAGS)
1323	{
1324	LogFunc(("[SD%RU8] Warning: Invalid stream tag %RU8 specified!\n", uSD, uTag));
1325
1326	int rc = hdaRegWriteU24(pThis, iReg, u32Value);
1327	DEVHDA_UNLOCK_BOTH(pThis, uSD);
1328	return rc;
1329	}
1330
1331	PHDATAG pTag = &pThis->aTags[uTag];
1332	AssertPtr(pTag);
1333
1334	LogFunc(("[SD%RU8] Using stream tag=%RU8\n", uSD, uTag));
1335
1336	/* Assign new values. */
1337	pTag->uTag = uTag;
1338	pTag->pStream = hdaGetStreamFromSD(pThis, uSD);
1339
1340	PHDASTREAM pStream = pTag->pStream;
1341	AssertPtr(pStream);
1342
1343	if (fInReset)
1344	{
1345	Assert(!fReset);
1346	Assert(!fInRun && !fRun);
1347
1348	/* Exit reset state. */
1349	ASMAtomicXchgBool(&pStream->State.fInReset, false);
1350
1351	/* Report that we're done resetting this stream by clearing SRST. */
1352	HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_SRST;
1353
1354	LogFunc(("[SD%RU8] Reset exit\n", uSD));
1355	}
1356	else if (fReset)
1357	{
1358	/* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
1359	Assert(!fInRun && !fRun);
1360
1361	LogFunc(("[SD%RU8] Reset enter\n", uSD));
1362
1363	hdaR3StreamLock(pStream);
1364
1365	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1366	hdaR3StreamAsyncIOLock(pStream);
1367	# endif
1368	/* Make sure to remove the run bit before doing the actual stream reset. */
1369	HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_RUN;
1370
1371	hdaR3StreamReset(pThis, pStream, pStream->u8SD);
1372
1373	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1374	hdaR3StreamAsyncIOUnlock(pStream);
1375	# endif
1376	hdaR3StreamUnlock(pStream);
1377	}
1378	else
1379	{
1380	/*
1381	* We enter here to change DMA states only.
1382	*/
1383	if (fInRun != fRun)
1384	{
1385	Assert(!fReset && !fInReset);
1386	LogFunc(("[SD%RU8] State changed (fRun=%RTbool)\n", uSD, fRun));
1387
1388	hdaR3StreamLock(pStream);
1389
1390	int rc2;
1391
1392	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1393	if (fRun)
1394	rc2 = hdaR3StreamAsyncIOCreate(pStream);
1395
1396	hdaR3StreamAsyncIOLock(pStream);
1397	# endif
1398	if (fRun)
1399	{
1400	/* (Re-)initialize the stream with current values. */
1401	rc2 = hdaR3StreamInit(pStream, pStream->u8SD);
1402	AssertRC(rc2);
1403
1404	/* Remove the old stream from the device setup. */
1405	rc2 = hdaR3RemoveStream(pThis, &pStream->State.Cfg);
1406	AssertRC(rc2);
1407
1408	/* Add the stream to the device setup. */
1409	rc2 = hdaR3AddStream(pThis, &pStream->State.Cfg);
1410	AssertRC(rc2);
1411	}
1412
1413	/* Enable/disable the stream. */
1414	rc2 = hdaR3StreamEnable(pStream, fRun /* fEnable */);
1415	AssertRC(rc2);
1416
1417	if (fRun)
1418	{
1419	/* Keep track of running streams. */
1420	pThis->cStreamsActive++;
1421
1422	/* (Re-)init the stream's period. */
1423	hdaR3StreamPeriodInit(&pStream->State.Period,
1424	pStream->u8SD, pStream->u16LVI, pStream->u32CBL, &pStream->State.Cfg);
1425
1426	/* Begin a new period for this stream. */
1427	rc2 = hdaR3StreamPeriodBegin(&pStream->State.Period, hdaWalClkGetCurrent(pThis)/* Use current wall clock time */);
1428	AssertRC(rc2);
1429
1430	rc2 = hdaR3TimerSet(pThis, pStream, TMTimerGet(pThis->pTimer[pStream->u8SD]) + pStream->State.cTransferTicks, false /* fForce */);
1431	AssertRC(rc2);
1432	}
1433	else
1434	{
1435	/* Keep track of running streams. */
1436	Assert(pThis->cStreamsActive);
1437	if (pThis->cStreamsActive)
1438	pThis->cStreamsActive--;
1439
1440	/* Make sure to (re-)schedule outstanding (delayed) interrupts. */
1441	hdaR3ReschedulePendingInterrupts(pThis);
1442
1443	/* Reset the period. */
1444	hdaR3StreamPeriodReset(&pStream->State.Period);
1445	}
1446
1447	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1448	hdaR3StreamAsyncIOUnlock(pStream);
1449	# endif
1450	/* Make sure to leave the lock before (eventually) starting the timer. */
1451	hdaR3StreamUnlock(pStream);
1452	}
1453	}
1454
1455	int rc2 = hdaRegWriteU24(pThis, iReg, u32Value);
1456	AssertRC(rc2);
1457
1458	DEVHDA_UNLOCK_BOTH(pThis, uSD);
1459	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1460	#else /* !IN_RING3 */
1461	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
1462	return VINF_IOM_R3_MMIO_WRITE;
1463	#endif /* IN_RING3 */
1464	}
1465
1466	static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1467	{
1468	#ifdef IN_RING3
1469	const uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, STS, iReg);
1470
1471	DEVHDA_LOCK_BOTH_RETURN(pThis, uSD, VINF_IOM_R3_MMIO_WRITE);
1472
1473	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
1474	if (!pStream)
1475	{
1476	AssertMsgFailed(("[SD%RU8] Warning: Writing SDSTS on non-attached stream (0x%x)\n",
1477	HDA_SD_NUM_FROM_REG(pThis, STS, iReg), u32Value));
1478
1479	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
1480	DEVHDA_UNLOCK_BOTH(pThis, uSD);
1481	return rc;
1482	}
1483
1484	hdaR3StreamLock(pStream);
1485
1486	uint32_t v = HDA_REG_IND(pThis, iReg);
1487
1488	/* Clear (zero) FIFOE, DESE and BCIS bits when writing 1 to it (6.2.33). */
1489	HDA_REG_IND(pThis, iReg) &= ~(u32Value & v);
1490
1491	/* Some guests tend to write SDnSTS even if the stream is not running.
1492	* So make sure to check if the RUN bit is set first. */
1493	const bool fRunning = pStream->State.fRunning;
1494
1495	Log3Func(("[SD%RU8] fRunning=%RTbool %R[sdsts]\n", pStream->u8SD, fRunning, v));
1496
1497	PHDASTREAMPERIOD pPeriod = &pStream->State.Period;
1498
1499	if (hdaR3StreamPeriodLock(pPeriod))
1500	{
1501	const bool fNeedsInterrupt = hdaR3StreamPeriodNeedsInterrupt(pPeriod);
1502	if (fNeedsInterrupt)
1503	hdaR3StreamPeriodReleaseInterrupt(pPeriod);
1504
1505	if (hdaR3StreamPeriodIsComplete(pPeriod))
1506	{
1507	/* Make sure to try to update the WALCLK register if a period is complete.
1508	* Use the maximum WALCLK value all (active) streams agree to. */
1509	const uint64_t uWalClkMax = hdaR3WalClkGetMax(pThis);
1510	if (uWalClkMax > hdaWalClkGetCurrent(pThis))
1511	hdaR3WalClkSet(pThis, uWalClkMax, false /* fForce */);
1512
1513	hdaR3StreamPeriodEnd(pPeriod);
1514
1515	if (fRunning)
1516	hdaR3StreamPeriodBegin(pPeriod, hdaWalClkGetCurrent(pThis) /* Use current wall clock time */);
1517	}
1518
1519	hdaR3StreamPeriodUnlock(pPeriod); /* Unlock before processing interrupt. */
1520	}
1521
1522	# ifndef LOG_ENABLED
1523	hdaProcessInterrupt(pThis);
1524	# else
1525	hdaProcessInterrupt(pThis, __FUNCTION__);
1526	# endif
1527
1528	const uint64_t tsNow = TMTimerGet(pThis->pTimer[uSD]);
1529	Assert(tsNow >= pStream->State.tsTransferLast);
1530
1531	const uint64_t cTicksElapsed = tsNow - pStream->State.tsTransferLast;
1532	# ifdef LOG_ENABLED
1533	const uint64_t cTicksTransferred = pStream->State.cbTransferProcessed * pStream->State.cTicksPerByte;
1534	# endif
1535
1536	uint64_t cTicksToNext = pStream->State.cTransferTicks;
1537	if (cTicksToNext) /* Only do any calculations if the stream currently is set up for transfers. */
1538	{
1539	Log3Func(("[SD%RU8] cTicksElapsed=%RU64, cTicksTransferred=%RU64, cTicksToNext=%RU64\n",
1540	pStream->u8SD, cTicksElapsed, cTicksTransferred, cTicksToNext));
1541
1542	Log3Func(("[SD%RU8] cbTransferProcessed=%RU32, cbTransferChunk=%RU32, cbTransferSize=%RU32\n",
1543	pStream->u8SD, pStream->State.cbTransferProcessed, pStream->State.cbTransferChunk, pStream->State.cbTransferSize));
1544
1545	if (cTicksElapsed <= cTicksToNext)
1546	{
1547	cTicksToNext = cTicksToNext - cTicksElapsed;
1548	}
1549	else /* Catch up. */
1550	{
1551	Log3Func(("[SD%RU8] Warning: Lagging behind (%RU64 ticks elapsed, maximum allowed is %RU64)\n",
1552	pStream->u8SD, cTicksElapsed, cTicksToNext));
1553
1554	LogRelMax2(64, ("HDA: Stream #%RU8 interrupt lagging behind (expected %uus, got %uus), trying to catch up ...\n",
1555	pStream->u8SD,
1556	(TMTimerGetFreq(pThis->pTimer[pStream->u8SD]) / pThis->uTimerHz) / 1000,(tsNow - pStream->State.tsTransferLast) / 1000));
1557
1558	cTicksToNext = 0;
1559	}
1560
1561	Log3Func(("[SD%RU8] -> cTicksToNext=%RU64\n", pStream->u8SD, cTicksToNext));
1562
1563	/* Reset processed data counter. */
1564	pStream->State.cbTransferProcessed = 0;
1565	pStream->State.tsTransferNext = tsNow + cTicksToNext;
1566
1567	/* Only re-arm the timer if there were pending transfer interrupts left
1568	* -- it could happen that we land in here if a guest writes to SDnSTS
1569	* unconditionally. */
1570	if (pStream->State.cTransferPendingInterrupts)
1571	{
1572	pStream->State.cTransferPendingInterrupts--;
1573
1574	/* Re-arm the timer. */
1575	LogFunc(("Timer set SD%RU8\n", pStream->u8SD));
1576	hdaR3TimerSet(pThis, pStream, tsNow + cTicksToNext, false /* fForce */);
1577	}
1578	}
1579
1580	hdaR3StreamUnlock(pStream);
1581
1582	DEVHDA_UNLOCK_BOTH(pThis, uSD);
1583	return VINF_SUCCESS;
1584	#else /* IN_RING3 */
1585	RT_NOREF(pThis, iReg, u32Value);
1586	return VINF_IOM_R3_MMIO_WRITE;
1587	#endif /* !IN_RING3 */
1588	}
1589
1590	static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1591	{
1592	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1593
1594	if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
1595	{ /* nothing to do */ }
1596	else
1597	{
1598	uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, LVI, iReg);
1599	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
1600	if (pStream)
1601	{
1602	/** @todo Validate LVI. */
1603	pStream->u16LVI = u32Value;
1604	LogFunc(("[SD%RU8] Updating LVI to %RU16\n", uSD, pStream->u16LVI));
1605
1606	#ifdef HDA_USE_DMA_ACCESS_HANDLER
1607	if (hdaGetDirFromSD(uSD) == PDMAUDIODIR_OUT)
1608	{
1609	/* Try registering the DMA handlers.
1610	* As we can't be sure in which order LVI + BDL base are set, try registering in both routines. */
1611	if (hdaR3StreamRegisterDMAHandlers(pThis, pStream))
1612	LogFunc(("[SD%RU8] DMA logging enabled\n", pStream->u8SD));
1613	}
1614	#endif
1615	}
1616	else
1617	AssertMsgFailed(("[SD%RU8] Warning: Changing SDLVI on non-attached stream (0x%x)\n", uSD, u32Value));
1618
1619	int rc2 = hdaRegWriteU16(pThis, iReg, u32Value);
1620	AssertRC(rc2);
1621	}
1622
1623	DEVHDA_UNLOCK(pThis);
1624	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1625	}
1626
1627	static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1628	{
1629	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1630
1631	uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg);
1632
1633	if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_IN) /* FIFOW for input streams only. */
1634	{
1635	#ifndef IN_RING0
1636	LogRel(("HDA: Warning: Guest tried to write read-only FIFOW to output stream #%RU8, ignoring\n", uSD));
1637	DEVHDA_UNLOCK(pThis);
1638	return VINF_SUCCESS;
1639	#else
1640	DEVHDA_UNLOCK(pThis);
1641	return VINF_IOM_R3_MMIO_WRITE;
1642	#endif
1643	}
1644
1645	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg));
1646	if (!pStream)
1647	{
1648	AssertMsgFailed(("[SD%RU8] Warning: Changing FIFOW on non-attached stream (0x%x)\n", uSD, u32Value));
1649
1650	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
1651	DEVHDA_UNLOCK(pThis);
1652	return rc;
1653	}
1654
1655	uint32_t u32FIFOW = 0;
1656
1657	switch (u32Value)
1658	{
1659	case HDA_SDFIFOW_8B:
1660	case HDA_SDFIFOW_16B:
1661	case HDA_SDFIFOW_32B:
1662	u32FIFOW = u32Value;
1663	break;
1664	default:
1665	ASSERT_GUEST_LOGREL_MSG_FAILED(("Guest tried write unsupported FIFOW (0x%x) to stream #%RU8, defaulting to 32 bytes\n",
1666	u32Value, uSD));
1667	u32FIFOW = HDA_SDFIFOW_32B;
1668	break;
1669	}
1670
1671	if (u32FIFOW)
1672	{
1673	pStream->u16FIFOW = hdaSDFIFOWToBytes(u32FIFOW);
1674	LogFunc(("[SD%RU8] Updating FIFOW to %RU32 bytes\n", uSD, pStream->u16FIFOW));
1675
1676	int rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOW);
1677	AssertRC(rc2);
1678	}
1679
1680	DEVHDA_UNLOCK(pThis);
1681	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1682	}
1683
1684	/**
1685	* @note This method could be called for changing value on Output Streams only (ICH6 datasheet 18.2.39).
1686	*/
1687	static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1688	{
1689	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1690
1691	uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOS, iReg);
1692
1693	if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_OUT) /* FIFOS for output streams only. */
1694	{
1695	LogRel(("HDA: Warning: Guest tried to write read-only FIFOS to input stream #%RU8, ignoring\n", uSD));
1696
1697	DEVHDA_UNLOCK(pThis);
1698	return VINF_SUCCESS;
1699	}
1700
1701	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
1702	if (!pStream)
1703	{
1704	AssertMsgFailed(("[SD%RU8] Warning: Changing FIFOS on non-attached stream (0x%x)\n", uSD, u32Value));
1705
1706	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
1707	DEVHDA_UNLOCK(pThis);
1708	return rc;
1709	}
1710
1711	uint32_t u32FIFOS = 0;
1712
1713	switch(u32Value)
1714	{
1715	case HDA_SDOFIFO_16B:
1716	case HDA_SDOFIFO_32B:
1717	case HDA_SDOFIFO_64B:
1718	case HDA_SDOFIFO_128B:
1719	case HDA_SDOFIFO_192B:
1720	case HDA_SDOFIFO_256B:
1721	u32FIFOS = u32Value;
1722	break;
1723
1724	default:
1725	ASSERT_GUEST_LOGREL_MSG_FAILED(("Guest tried write unsupported FIFOS (0x%x) to stream #%RU8, defaulting to 192 bytes\n",
1726	u32Value, uSD));
1727	u32FIFOS = HDA_SDOFIFO_192B;
1728	break;
1729	}
1730
1731	if (u32FIFOS)
1732	{
1733	pStream->u16FIFOS = u32FIFOS + 1;
1734	LogFunc(("[SD%RU8] Updating FIFOS to %RU32 bytes\n", uSD, pStream->u16FIFOS));
1735
1736	int rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOS);
1737	AssertRC(rc2);
1738	}
1739
1740	DEVHDA_UNLOCK(pThis);
1741	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1742	}
1743
1744	#ifdef IN_RING3
1745
1746	/**
1747	* Adds an audio output stream to the device setup using the given configuration.
1748	*
1749	* @returns IPRT status code.
1750	* @param pThis Device state.
1751	* @param pCfg Stream configuration to use for adding a stream.
1752	*/
1753	static int hdaR3AddStreamOut(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1754	{
1755	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1756	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1757
1758	AssertReturn(pCfg->enmDir == PDMAUDIODIR_OUT, VERR_INVALID_PARAMETER);
1759
1760	LogFlowFunc(("Stream=%s\n", pCfg->szName));
1761
1762	int rc = VINF_SUCCESS;
1763
1764	bool fUseFront = true; /* Always use front out by default. */
1765	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1766	bool fUseRear;
1767	bool fUseCenter;
1768	bool fUseLFE;
1769
1770	fUseRear = fUseCenter = fUseLFE = false;
1771
1772	/*
1773	* Use commonly used setups for speaker configurations.
1774	*/
1775
1776	/** @todo Make the following configurable through mixer API and/or CFGM? */
1777	switch (pCfg->Props.cChannels)
1778	{
1779	case 3: /* 2.1: Front (Stereo) + LFE. */
1780	{
1781	fUseLFE = true;
1782	break;
1783	}
1784
1785	case 4: /* Quadrophonic: Front (Stereo) + Rear (Stereo). */
1786	{
1787	fUseRear = true;
1788	break;
1789	}
1790
1791	case 5: /* 4.1: Front (Stereo) + Rear (Stereo) + LFE. */
1792	{
1793	fUseRear = true;
1794	fUseLFE = true;
1795	break;
1796	}
1797
1798	case 6: /* 5.1: Front (Stereo) + Rear (Stereo) + Center/LFE. */
1799	{
1800	fUseRear = true;
1801	fUseCenter = true;
1802	fUseLFE = true;
1803	break;
1804	}
1805
1806	default: /* Unknown; fall back to 2 front channels (stereo). */
1807	{
1808	rc = VERR_NOT_SUPPORTED;
1809	break;
1810	}
1811	}
1812	# else /* !VBOX_WITH_AUDIO_HDA_51_SURROUND */
1813	/* Only support mono or stereo channels. */
1814	if ( pCfg->Props.cChannels != 1 /* Mono */
1815	&& pCfg->Props.cChannels != 2 /* Stereo */)
1816	{
1817	rc = VERR_NOT_SUPPORTED;
1818	}
1819	# endif /* !VBOX_WITH_AUDIO_HDA_51_SURROUND */
1820
1821	if (rc == VERR_NOT_SUPPORTED)
1822	{
1823	LogRel2(("HDA: Warning: Unsupported channel count (%RU8), falling back to stereo channels (2)\n", pCfg->Props.cChannels));
1824
1825	/* Fall back to 2 channels (see below in fUseFront block). */
1826	rc = VINF_SUCCESS;
1827	}
1828
1829	do
1830	{
1831	if (RT_FAILURE(rc))
1832	break;
1833
1834	if (fUseFront)
1835	{
1836	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Front");
1837
1838	pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_FRONT;
1839	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1840
1841	pCfg->Props.cChannels = 2;
1842	pCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pCfg->Props.cBytes, pCfg->Props.cChannels);
1843
1844	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT, pCfg);
1845	}
1846
1847	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1848	if ( RT_SUCCESS(rc)
1849	&& (fUseCenter \|\| fUseLFE))
1850	{
1851	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Center/LFE");
1852
1853	pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_CENTER_LFE;
1854	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1855
1856	pCfg->Props.cChannels = (fUseCenter && fUseLFE) ? 2 : 1;
1857	pCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pCfg->Props.cBits, pCfg->Props.cChannels);
1858
1859	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE, pCfg);
1860	}
1861
1862	if ( RT_SUCCESS(rc)
1863	&& fUseRear)
1864	{
1865	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Rear");
1866
1867	pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_REAR;
1868	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1869
1870	pCfg->Props.cChannels = 2;
1871	pCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pCfg->Props.cBits, pCfg->Props.cChannels);
1872
1873	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR, pCfg);
1874	}
1875	# endif /* VBOX_WITH_AUDIO_HDA_51_SURROUND */
1876
1877	} while (0);
1878
1879	LogFlowFuncLeaveRC(rc);
1880	return rc;
1881	}
1882
1883	/**
1884	* Adds an audio input stream to the device setup using the given configuration.
1885	*
1886	* @returns IPRT status code.
1887	* @param pThis Device state.
1888	* @param pCfg Stream configuration to use for adding a stream.
1889	*/
1890	static int hdaR3AddStreamIn(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1891	{
1892	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1893	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1894
1895	AssertReturn(pCfg->enmDir == PDMAUDIODIR_IN, VERR_INVALID_PARAMETER);
1896
1897	LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Source));
1898
1899	int rc;
1900
1901	switch (pCfg->DestSource.Source)
1902	{
1903	case PDMAUDIORECSOURCE_LINE:
1904	{
1905	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN, pCfg);
1906	break;
1907	}
1908	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
1909	case PDMAUDIORECSOURCE_MIC:
1910	{
1911	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN, pCfg);
1912	break;
1913	}
1914	# endif
1915	default:
1916	rc = VERR_NOT_SUPPORTED;
1917	break;
1918	}
1919
1920	LogFlowFuncLeaveRC(rc);
1921	return rc;
1922	}
1923
1924	/**
1925	* Adds an audio stream to the device setup using the given configuration.
1926	*
1927	* @returns IPRT status code.
1928	* @param pThis Device state.
1929	* @param pCfg Stream configuration to use for adding a stream.
1930	*/
1931	static int hdaR3AddStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1932	{
1933	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1934	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1935
1936	int rc;
1937
1938	LogFlowFuncEnter();
1939
1940	switch (pCfg->enmDir)
1941	{
1942	case PDMAUDIODIR_OUT:
1943	rc = hdaR3AddStreamOut(pThis, pCfg);
1944	break;
1945
1946	case PDMAUDIODIR_IN:
1947	rc = hdaR3AddStreamIn(pThis, pCfg);
1948	break;
1949
1950	default:
1951	rc = VERR_NOT_SUPPORTED;
1952	AssertFailed();
1953	break;
1954	}
1955
1956	LogFlowFunc(("Returning %Rrc\n", rc));
1957
1958	return rc;
1959	}
1960
1961	/**
1962	* Removes an audio stream from the device setup using the given configuration.
1963	*
1964	* @returns IPRT status code.
1965	* @param pThis Device state.
1966	* @param pCfg Stream configuration to use for removing a stream.
1967	*/
1968	static int hdaR3RemoveStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1969	{
1970	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1971	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1972
1973	int rc = VINF_SUCCESS;
1974
1975	PDMAUDIOMIXERCTL enmMixerCtl = PDMAUDIOMIXERCTL_UNKNOWN;
1976	switch (pCfg->enmDir)
1977	{
1978	case PDMAUDIODIR_IN:
1979	{
1980	LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Source));
1981
1982	switch (pCfg->DestSource.Source)
1983	{
1984	case PDMAUDIORECSOURCE_UNKNOWN: break;
1985	case PDMAUDIORECSOURCE_LINE: enmMixerCtl = PDMAUDIOMIXERCTL_LINE_IN; break;
1986	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
1987	case PDMAUDIORECSOURCE_MIC: enmMixerCtl = PDMAUDIOMIXERCTL_MIC_IN; break;
1988	# endif
1989	default:
1990	rc = VERR_NOT_SUPPORTED;
1991	break;
1992	}
1993
1994	break;
1995	}
1996
1997	case PDMAUDIODIR_OUT:
1998	{
1999	LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Dest));
2000
2001	switch (pCfg->DestSource.Dest)
2002	{
2003	case PDMAUDIOPLAYBACKDEST_UNKNOWN: break;
2004	case PDMAUDIOPLAYBACKDEST_FRONT: enmMixerCtl = PDMAUDIOMIXERCTL_FRONT; break;
2005	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2006	case PDMAUDIOPLAYBACKDEST_CENTER_LFE: enmMixerCtl = PDMAUDIOMIXERCTL_CENTER_LFE; break;
2007	case PDMAUDIOPLAYBACKDEST_REAR: enmMixerCtl = PDMAUDIOMIXERCTL_REAR; break;
2008	# endif
2009	default:
2010	rc = VERR_NOT_SUPPORTED;
2011	break;
2012	}
2013	break;
2014	}
2015
2016	default:
2017	rc = VERR_NOT_SUPPORTED;
2018	break;
2019	}
2020
2021	if ( RT_SUCCESS(rc)
2022	&& enmMixerCtl != PDMAUDIOMIXERCTL_UNKNOWN)
2023	{
2024	rc = hdaCodecRemoveStream(pThis->pCodec, enmMixerCtl);
2025	}
2026
2027	LogFlowFuncLeaveRC(rc);
2028	return rc;
2029	}
2030	#endif /* IN_RING3 */
2031
2032	static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2033	{
2034	DEVHDA_LOCK(pThis);
2035
2036	# ifdef LOG_ENABLED
2037	if (!hdaGetStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FMT, iReg)))
2038	LogFunc(("[SD%RU8] Warning: Changing SDFMT on non-attached stream (0x%x)\n",
2039	HDA_SD_NUM_FROM_REG(pThis, FMT, iReg), u32Value));
2040	# endif
2041
2042
2043	/* Write the wanted stream format into the register in any case.
2044	*
2045	* This is important for e.g. MacOS guests, as those try to initialize streams which are not reported
2046	* by the device emulation (wants 4 channels, only have 2 channels at the moment).
2047	*
2048	* When ignoring those (invalid) formats, this leads to MacOS thinking that the device is malfunctioning
2049	* and therefore disabling the device completely. */
2050	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
2051	AssertRC(rc);
2052
2053	DEVHDA_UNLOCK(pThis);
2054	return VINF_SUCCESS; /* Never return failure. */
2055	}
2056
2057	/* Note: Will be called for both, BDPL and BDPU, registers. */
2058	DECLINLINE(int) hdaRegWriteSDBDPX(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value, uint8_t uSD)
2059	{
2060	#ifdef IN_RING3
2061	DEVHDA_LOCK(pThis);
2062
2063	int rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2064	AssertRC(rc2);
2065
2066	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
2067	if (!pStream)
2068	{
2069	DEVHDA_UNLOCK(pThis);
2070	return VINF_SUCCESS;
2071	}
2072
2073	/* Update BDL base. */
2074	pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, uSD),
2075	HDA_STREAM_REG(pThis, BDPU, uSD));
2076
2077	# ifdef HDA_USE_DMA_ACCESS_HANDLER
2078	if (hdaGetDirFromSD(uSD) == PDMAUDIODIR_OUT)
2079	{
2080	/* Try registering the DMA handlers.
2081	* As we can't be sure in which order LVI + BDL base are set, try registering in both routines. */
2082	if (hdaR3StreamRegisterDMAHandlers(pThis, pStream))
2083	LogFunc(("[SD%RU8] DMA logging enabled\n", pStream->u8SD));
2084	}
2085	# endif
2086
2087	LogFlowFunc(("[SD%RU8] BDLBase=0x%x\n", pStream->u8SD, pStream->u64BDLBase));
2088
2089	DEVHDA_UNLOCK(pThis);
2090	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2091	#else /* !IN_RING3 */
2092	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value); RT_NOREF_PV(uSD);
2093	return VINF_IOM_R3_MMIO_WRITE;
2094	#endif /* IN_RING3 */
2095	}
2096
2097	static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2098	{
2099	return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPL, iReg));
2100	}
2101
2102	static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2103	{
2104	return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPU, iReg));
2105	}
2106
2107	static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2108	{
2109	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
2110
2111	/* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
2112	if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2113	\|\| (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA))
2114	{
2115	HDA_REG(pThis, IRS) = HDA_IRS_ICB; /* busy */
2116	}
2117
2118	int rc = hdaRegReadU32(pThis, iReg, pu32Value);
2119	DEVHDA_UNLOCK(pThis);
2120
2121	return rc;
2122	}
2123
2124	static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2125	{
2126	RT_NOREF_PV(iReg);
2127	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2128
2129	/*
2130	* If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
2131	* write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
2132	*/
2133	if ( (u32Value & HDA_IRS_ICB)
2134	&& !(HDA_REG(pThis, IRS) & HDA_IRS_ICB))
2135	{
2136	#ifdef IN_RING3
2137	uint32_t uCmd = HDA_REG(pThis, IC);
2138
2139	if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
2140	{
2141	DEVHDA_UNLOCK(pThis);
2142
2143	/*
2144	* 3.4.3: Defines behavior of immediate Command status register.
2145	*/
2146	LogRel(("HDA: Guest attempted process immediate verb (%x) with active CORB\n", uCmd));
2147	return VINF_SUCCESS;
2148	}
2149
2150	HDA_REG(pThis, IRS) = HDA_IRS_ICB; /* busy */
2151
2152	uint64_t uResp;
2153	int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec,
2154	HDA_CODEC_CMD(uCmd, 0 /* LUN */), &uResp);
2155	if (RT_FAILURE(rc2))
2156	LogFunc(("Codec lookup failed with rc2=%Rrc\n", rc2));
2157
2158	HDA_REG(pThis, IR) = (uint32_t)uResp; /** @todo r=andy Do we need a 64-bit response? */
2159	HDA_REG(pThis, IRS) = HDA_IRS_IRV; /* result is ready */
2160	/** @todo r=michaln We just set the IRS value, why are we clearing unset bits? */
2161	HDA_REG(pThis, IRS) &= ~HDA_IRS_ICB; /* busy is clear */
2162
2163	DEVHDA_UNLOCK(pThis);
2164	return VINF_SUCCESS;
2165	#else /* !IN_RING3 */
2166	DEVHDA_UNLOCK(pThis);
2167	return VINF_IOM_R3_MMIO_WRITE;
2168	#endif /* !IN_RING3 */
2169	}
2170
2171	/*
2172	* Once the guest read the response, it should clear the IRV bit of the IRS register.
2173	*/
2174	HDA_REG(pThis, IRS) &= ~(u32Value & HDA_IRS_IRV);
2175
2176	DEVHDA_UNLOCK(pThis);
2177	return VINF_SUCCESS;
2178	}
2179
2180	static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2181	{
2182	RT_NOREF(iReg);
2183	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2184
2185	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
2186	{
2187	LogFunc(("CORB DMA (still) running, skipping\n"));
2188
2189	DEVHDA_UNLOCK(pThis);
2190	return VINF_SUCCESS;
2191	}
2192
2193	if (u32Value & HDA_RIRBWP_RST)
2194	{
2195	/* Do a RIRB reset. */
2196	if (pThis->cbRirbBuf)
2197	{
2198	Assert(pThis->pu64RirbBuf);
2199	RT_BZERO((void *)pThis->pu64RirbBuf, pThis->cbRirbBuf);
2200	}
2201
2202	LogRel2(("HDA: RIRB reset\n"));
2203
2204	HDA_REG(pThis, RIRBWP) = 0;
2205	}
2206
2207	/* The remaining bits are O, see 6.2.22. */
2208
2209	DEVHDA_UNLOCK(pThis);
2210	return VINF_SUCCESS;
2211	}
2212
2213	static int hdaRegWriteRINTCNT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2214	{
2215	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2216
2217	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
2218	{
2219	LogFunc(("CORB DMA is (still) running, skipping\n"));
2220
2221	DEVHDA_UNLOCK(pThis);
2222	return VINF_SUCCESS;
2223	}
2224
2225	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
2226	AssertRC(rc);
2227
2228	LogFunc(("Response interrupt count is now %RU8\n", HDA_REG(pThis, RINTCNT) & 0xFF));
2229
2230	DEVHDA_UNLOCK(pThis);
2231	return rc;
2232	}
2233
2234	static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2235	{
2236	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2237	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2238
2239	int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2240	AssertRCSuccess(rc);
2241
2242	switch (iReg)
2243	{
2244	case HDA_REG_CORBLBASE:
2245	pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
2246	pThis->u64CORBBase \|= pThis->au32Regs[iRegMem];
2247	break;
2248	case HDA_REG_CORBUBASE:
2249	pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
2250	pThis->u64CORBBase \|= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2251	break;
2252	case HDA_REG_RIRBLBASE:
2253	pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
2254	pThis->u64RIRBBase \|= pThis->au32Regs[iRegMem];
2255	break;
2256	case HDA_REG_RIRBUBASE:
2257	pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
2258	pThis->u64RIRBBase \|= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2259	break;
2260	case HDA_REG_DPLBASE:
2261	{
2262	pThis->u64DPBase = pThis->au32Regs[iRegMem] & DPBASE_ADDR_MASK;
2263	Assert(pThis->u64DPBase % 128 == 0); /* Must be 128-byte aligned. */
2264
2265	/* Also make sure to handle the DMA position enable bit. */
2266	pThis->fDMAPosition = pThis->au32Regs[iRegMem] & RT_BIT_32(0);
2267	LogRel(("HDA: %s DMA position buffer\n", pThis->fDMAPosition ? "Enabled" : "Disabled"));
2268	break;
2269	}
2270	case HDA_REG_DPUBASE:
2271	pThis->u64DPBase = RT_MAKE_U64(RT_LO_U32(pThis->u64DPBase) & DPBASE_ADDR_MASK, pThis->au32Regs[iRegMem]);
2272	break;
2273	default:
2274	AssertMsgFailed(("Invalid index\n"));
2275	break;
2276	}
2277
2278	LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
2279	pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
2280
2281	DEVHDA_UNLOCK(pThis);
2282	return rc;
2283	}
2284
2285	static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2286	{
2287	RT_NOREF_PV(iReg);
2288	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2289
2290	uint8_t v = HDA_REG(pThis, RIRBSTS);
2291	HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
2292
2293	#ifndef LOG_ENABLED
2294	int rc = hdaProcessInterrupt(pThis);
2295	#else
2296	int rc = hdaProcessInterrupt(pThis, __FUNCTION__);
2297	#endif
2298
2299	DEVHDA_UNLOCK(pThis);
2300	return rc;
2301	}
2302
2303	#ifdef IN_RING3
2304
2305	/**
2306	* Retrieves a corresponding sink for a given mixer control.
2307	* Returns NULL if no sink is found.
2308	*
2309	* @return PHDAMIXERSINK
2310	* @param pThis HDA state.
2311	* @param enmMixerCtl Mixer control to get the corresponding sink for.
2312	*/
2313	static PHDAMIXERSINK hdaR3MixerControlToSink(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
2314	{
2315	PHDAMIXERSINK pSink;
2316
2317	switch (enmMixerCtl)
2318	{
2319	case PDMAUDIOMIXERCTL_VOLUME_MASTER:
2320	/* Fall through is intentional. */
2321	case PDMAUDIOMIXERCTL_FRONT:
2322	pSink = &pThis->SinkFront;
2323	break;
2324	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2325	case PDMAUDIOMIXERCTL_CENTER_LFE:
2326	pSink = &pThis->SinkCenterLFE;
2327	break;
2328	case PDMAUDIOMIXERCTL_REAR:
2329	pSink = &pThis->SinkRear;
2330	break;
2331	# endif
2332	case PDMAUDIOMIXERCTL_LINE_IN:
2333	pSink = &pThis->SinkLineIn;
2334	break;
2335	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2336	case PDMAUDIOMIXERCTL_MIC_IN:
2337	pSink = &pThis->SinkMicIn;
2338	break;
2339	# endif
2340	default:
2341	pSink = NULL;
2342	AssertMsgFailed(("Unhandled mixer control\n"));
2343	break;
2344	}
2345
2346	return pSink;
2347	}
2348
2349	/**
2350	* Adds a specific HDA driver to the driver chain.
2351	*
2352	* @return IPRT status code.
2353	* @param pThis HDA state.
2354	* @param pDrv HDA driver to add.
2355	*/
2356	static int hdaR3MixerAddDrv(PHDASTATE pThis, PHDADRIVER pDrv)
2357	{
2358	int rc = VINF_SUCCESS;
2359
2360	PHDASTREAM pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkLineIn);
2361	if ( pStream
2362	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2363	{
2364	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkLineIn.pMixSink, &pStream->State.Cfg, pDrv);
2365	if (RT_SUCCESS(rc))
2366	rc = rc2;
2367	}
2368
2369	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2370	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkMicIn);
2371	if ( pStream
2372	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2373	{
2374	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkMicIn.pMixSink, &pStream->State.Cfg, pDrv);
2375	if (RT_SUCCESS(rc))
2376	rc = rc2;
2377	}
2378	# endif
2379
2380	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkFront);
2381	if ( pStream
2382	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2383	{
2384	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkFront.pMixSink, &pStream->State.Cfg, pDrv);
2385	if (RT_SUCCESS(rc))
2386	rc = rc2;
2387	}
2388
2389	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2390	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkCenterLFE);
2391	if ( pStream
2392	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2393	{
2394	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkCenterLFE.pMixSink, &pStream->State.Cfg, pDrv);
2395	if (RT_SUCCESS(rc))
2396	rc = rc2;
2397	}
2398
2399	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkRear);
2400	if ( pStream
2401	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2402	{
2403	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkRear.pMixSink, &pStream->State.Cfg, pDrv);
2404	if (RT_SUCCESS(rc))
2405	rc = rc2;
2406	}
2407	# endif
2408
2409	return rc;
2410	}
2411
2412	/**
2413	* Removes a specific HDA driver from the driver chain and destroys its
2414	* associated streams.
2415	*
2416	* @param pThis HDA state.
2417	* @param pDrv HDA driver to remove.
2418	*/
2419	static void hdaR3MixerRemoveDrv(PHDASTATE pThis, PHDADRIVER pDrv)
2420	{
2421	AssertPtrReturnVoid(pThis);
2422	AssertPtrReturnVoid(pDrv);
2423
2424	if (pDrv->LineIn.pMixStrm)
2425	{
2426	if (AudioMixerSinkGetRecordingSource(pThis->SinkLineIn.pMixSink) == pDrv->LineIn.pMixStrm)
2427	AudioMixerSinkSetRecordingSource(pThis->SinkLineIn.pMixSink, NULL);
2428
2429	AudioMixerSinkRemoveStream(pThis->SinkLineIn.pMixSink, pDrv->LineIn.pMixStrm);
2430	AudioMixerStreamDestroy(pDrv->LineIn.pMixStrm);
2431	pDrv->LineIn.pMixStrm = NULL;
2432	}
2433
2434	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2435	if (pDrv->MicIn.pMixStrm)
2436	{
2437	if (AudioMixerSinkGetRecordingSource(pThis->SinkMicIn.pMixSink) == pDrv->MicIn.pMixStrm)
2438	AudioMixerSinkSetRecordingSource(&pThis->SinkMicIn.pMixSink, NULL);
2439
2440	AudioMixerSinkRemoveStream(pThis->SinkMicIn.pMixSink, pDrv->MicIn.pMixStrm);
2441	AudioMixerStreamDestroy(pDrv->MicIn.pMixStrm);
2442	pDrv->MicIn.pMixStrm = NULL;
2443	}
2444	# endif
2445
2446	if (pDrv->Front.pMixStrm)
2447	{
2448	AudioMixerSinkRemoveStream(pThis->SinkFront.pMixSink, pDrv->Front.pMixStrm);
2449	AudioMixerStreamDestroy(pDrv->Front.pMixStrm);
2450	pDrv->Front.pMixStrm = NULL;
2451	}
2452
2453	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2454	if (pDrv->CenterLFE.pMixStrm)
2455	{
2456	AudioMixerSinkRemoveStream(pThis->SinkCenterLFE.pMixSink, pDrv->CenterLFE.pMixStrm);
2457	AudioMixerStreamDestroy(pDrv->CenterLFE.pMixStrm);
2458	pDrv->CenterLFE.pMixStrm = NULL;
2459	}
2460
2461	if (pDrv->Rear.pMixStrm)
2462	{
2463	AudioMixerSinkRemoveStream(pThis->SinkRear.pMixSink, pDrv->Rear.pMixStrm);
2464	AudioMixerStreamDestroy(pDrv->Rear.pMixStrm);
2465	pDrv->Rear.pMixStrm = NULL;
2466	}
2467	# endif
2468
2469	RTListNodeRemove(&pDrv->Node);
2470	}
2471
2472	/**
2473	* Adds a driver stream to a specific mixer sink.
2474	*
2475	* @returns IPRT status code (ignored by caller).
2476	* @param pThis HDA state.
2477	* @param pMixSink Audio mixer sink to add audio streams to.
2478	* @param pCfg Audio stream configuration to use for the audio streams to add.
2479	* @param pDrv Driver stream to add.
2480	*/
2481	static int hdaR3MixerAddDrvStream(PHDASTATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg, PHDADRIVER pDrv)
2482	{
2483	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2484	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
2485	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2486
2487	LogFunc(("Sink=%s, Stream=%s\n", pMixSink->pszName, pCfg->szName));
2488
2489	PPDMAUDIOSTREAMCFG pStreamCfg = DrvAudioHlpStreamCfgDup(pCfg);
2490	if (!pStreamCfg)
2491	return VERR_NO_MEMORY;
2492
2493	LogFunc(("[LUN#%RU8] %s\n", pDrv->uLUN, pStreamCfg->szName));
2494
2495	int rc = VINF_SUCCESS;
2496
2497	PHDADRIVERSTREAM pDrvStream = NULL;
2498
2499	if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
2500	{
2501	LogFunc(("enmRecSource=%d\n", pStreamCfg->DestSource.Source));
2502
2503	switch (pStreamCfg->DestSource.Source)
2504	{
2505	case PDMAUDIORECSOURCE_LINE:
2506	pDrvStream = &pDrv->LineIn;
2507	break;
2508	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2509	case PDMAUDIORECSOURCE_MIC:
2510	pDrvStream = &pDrv->MicIn;
2511	break;
2512	# endif
2513	default:
2514	rc = VERR_NOT_SUPPORTED;
2515	break;
2516	}
2517	}
2518	else if (pStreamCfg->enmDir == PDMAUDIODIR_OUT)
2519	{
2520	LogFunc(("enmPlaybackDest=%d\n", pStreamCfg->DestSource.Dest));
2521
2522	switch (pStreamCfg->DestSource.Dest)
2523	{
2524	case PDMAUDIOPLAYBACKDEST_FRONT:
2525	pDrvStream = &pDrv->Front;
2526	break;
2527	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2528	case PDMAUDIOPLAYBACKDEST_CENTER_LFE:
2529	pDrvStream = &pDrv->CenterLFE;
2530	break;
2531	case PDMAUDIOPLAYBACKDEST_REAR:
2532	pDrvStream = &pDrv->Rear;
2533	break;
2534	# endif
2535	default:
2536	rc = VERR_NOT_SUPPORTED;
2537	break;
2538	}
2539	}
2540	else
2541	rc = VERR_NOT_SUPPORTED;
2542
2543	if (RT_SUCCESS(rc))
2544	{
2545	AssertPtr(pDrvStream);
2546	AssertMsg(pDrvStream->pMixStrm == NULL, ("[LUN#%RU8] Driver stream already present when it must not\n", pDrv->uLUN));
2547
2548	PAUDMIXSTREAM pMixStrm;
2549	rc = AudioMixerSinkCreateStream(pMixSink, pDrv->pConnector, pStreamCfg, 0 /* fFlags */, &pMixStrm);
2550	LogFlowFunc(("LUN#%RU8: Created stream \"%s\" for sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
2551	if (RT_SUCCESS(rc))
2552	{
2553	rc = AudioMixerSinkAddStream(pMixSink, pMixStrm);
2554	LogFlowFunc(("LUN#%RU8: Added stream \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
2555	if (RT_SUCCESS(rc))
2556	{
2557	/* If this is an input stream, always set the latest (added) stream
2558	* as the recording source.
2559	* @todo Make the recording source dynamic (CFGM?). */
2560	if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
2561	{
2562	PDMAUDIOBACKENDCFG Cfg;
2563	rc = pDrv->pConnector->pfnGetConfig(pDrv->pConnector, &Cfg);
2564	if (RT_SUCCESS(rc))
2565	{
2566	if (Cfg.cMaxStreamsIn) /* At least one input source available? */
2567	{
2568	rc = AudioMixerSinkSetRecordingSource(pMixSink, pMixStrm);
2569	LogFlowFunc(("LUN#%RU8: Recording source for '%s' -> '%s', rc=%Rrc\n",
2570	pDrv->uLUN, pStreamCfg->szName, Cfg.szName, rc));
2571
2572	if (RT_SUCCESS(rc))
2573	LogRel(("HDA: Set recording source for '%s' to '%s'\n",
2574	pStreamCfg->szName, Cfg.szName));
2575	}
2576	else
2577	LogRel(("HDA: Backend '%s' currently is not offering any recording source for '%s'\n",
2578	Cfg.szName, pStreamCfg->szName));
2579	}
2580	else if (RT_FAILURE(rc))
2581	LogFunc(("LUN#%RU8: Unable to retrieve backend configuration for '%s', rc=%Rrc\n",
2582	pDrv->uLUN, pStreamCfg->szName, rc));
2583	}
2584	}
2585	}
2586
2587	if (RT_SUCCESS(rc))
2588	pDrvStream->pMixStrm = pMixStrm;
2589	}
2590
2591	if (pStreamCfg)
2592	{
2593	RTMemFree(pStreamCfg);
2594	pStreamCfg = NULL;
2595	}
2596
2597	LogFlowFuncLeaveRC(rc);
2598	return rc;
2599	}
2600
2601	/**
2602	* Adds all current driver streams to a specific mixer sink.
2603	*
2604	* @returns IPRT status code.
2605	* @param pThis HDA state.
2606	* @param pMixSink Audio mixer sink to add stream to.
2607	* @param pCfg Audio stream configuration to use for the audio streams to add.
2608	*/
2609	static int hdaR3MixerAddDrvStreams(PHDASTATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg)
2610	{
2611	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2612	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
2613	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2614
2615	LogFunc(("Sink=%s, Stream=%s\n", pMixSink->pszName, pCfg->szName));
2616
2617	if (!DrvAudioHlpStreamCfgIsValid(pCfg))
2618	return VERR_INVALID_PARAMETER;
2619
2620	int rc = AudioMixerSinkSetFormat(pMixSink, &pCfg->Props);
2621	if (RT_FAILURE(rc))
2622	return rc;
2623
2624	PHDADRIVER pDrv;
2625	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2626	{
2627	int rc2 = hdaR3MixerAddDrvStream(pThis, pMixSink, pCfg, pDrv);
2628	if (RT_FAILURE(rc2))
2629	LogFunc(("Attaching stream failed with %Rrc\n", rc2));
2630
2631	/* Do not pass failure to rc here, as there might be drivers which aren't
2632	* configured / ready yet. */
2633	}
2634
2635	return rc;
2636	}
2637
2638	/**
2639	* @interface_method_impl{HDACODEC,pfnCbMixerAddStream}
2640	*
2641	* Adds a new audio stream to a specific mixer control.
2642	*
2643	* Depending on the mixer control the stream then gets assigned to one of the internal
2644	* mixer sinks, which in turn then handle the mixing of all connected streams to that sink.
2645	*
2646	* @return IPRT status code.
2647	* @param pThis HDA state.
2648	* @param enmMixerCtl Mixer control to assign new stream to.
2649	* @param pCfg Stream configuration for the new stream.
2650	*/
2651	static DECLCALLBACK(int) hdaR3MixerAddStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOSTREAMCFG pCfg)
2652	{
2653	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2654	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2655
2656	int rc;
2657
2658	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2659	if (pSink)
2660	{
2661	rc = hdaR3MixerAddDrvStreams(pThis, pSink->pMixSink, pCfg);
2662
2663	AssertPtr(pSink->pMixSink);
2664	LogFlowFunc(("Sink=%s, Mixer control=%s\n", pSink->pMixSink->pszName, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl)));
2665	}
2666	else
2667	rc = VERR_NOT_FOUND;
2668
2669	LogFlowFuncLeaveRC(rc);
2670	return rc;
2671	}
2672
2673	/**
2674	* @interface_method_impl{HDACODEC,pfnCbMixerRemoveStream}
2675	*
2676	* Removes a specified mixer control from the HDA's mixer.
2677	*
2678	* @return IPRT status code.
2679	* @param pThis HDA state.
2680	* @param enmMixerCtl Mixer control to remove.
2681	*
2682	* @remarks Can be called as a callback by the HDA codec.
2683	*/
2684	static DECLCALLBACK(int) hdaR3MixerRemoveStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
2685	{
2686	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2687
2688	int rc;
2689
2690	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2691	if (pSink)
2692	{
2693	PHDADRIVER pDrv;
2694	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2695	{
2696	PAUDMIXSTREAM pMixStream = NULL;
2697	switch (enmMixerCtl)
2698	{
2699	/*
2700	* Input.
2701	*/
2702	case PDMAUDIOMIXERCTL_LINE_IN:
2703	pMixStream = pDrv->LineIn.pMixStrm;
2704	pDrv->LineIn.pMixStrm = NULL;
2705	break;
2706	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2707	case PDMAUDIOMIXERCTL_MIC_IN:
2708	pMixStream = pDrv->MicIn.pMixStrm;
2709	pDrv->MicIn.pMixStrm = NULL;
2710	break;
2711	# endif
2712	/*
2713	* Output.
2714	*/
2715	case PDMAUDIOMIXERCTL_FRONT:
2716	pMixStream = pDrv->Front.pMixStrm;
2717	pDrv->Front.pMixStrm = NULL;
2718	break;
2719	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2720	case PDMAUDIOMIXERCTL_CENTER_LFE:
2721	pMixStream = pDrv->CenterLFE.pMixStrm;
2722	pDrv->CenterLFE.pMixStrm = NULL;
2723	break;
2724	case PDMAUDIOMIXERCTL_REAR:
2725	pMixStream = pDrv->Rear.pMixStrm;
2726	pDrv->Rear.pMixStrm = NULL;
2727	break;
2728	# endif
2729	default:
2730	AssertMsgFailed(("Mixer control %d not implemented\n", enmMixerCtl));
2731	break;
2732	}
2733
2734	if (pMixStream)
2735	{
2736	AudioMixerSinkRemoveStream(pSink->pMixSink, pMixStream);
2737	AudioMixerStreamDestroy(pMixStream);
2738
2739	pMixStream = NULL;
2740	}
2741	}
2742
2743	AudioMixerSinkRemoveAllStreams(pSink->pMixSink);
2744	rc = VINF_SUCCESS;
2745	}
2746	else
2747	rc = VERR_NOT_FOUND;
2748
2749	LogFunc(("Mixer control=%s, rc=%Rrc\n", DrvAudioHlpAudMixerCtlToStr(enmMixerCtl), rc));
2750	return rc;
2751	}
2752
2753	/**
2754	* @interface_method_impl{HDACODEC,pfnCbMixerControl}
2755	*
2756	* Controls an input / output converter widget, that is, which converter is connected
2757	* to which stream (and channel).
2758	*
2759	* @returns IPRT status code.
2760	* @param pThis HDA State.
2761	* @param enmMixerCtl Mixer control to set SD stream number and channel for.
2762	* @param uSD SD stream number (number + 1) to set. Set to 0 for unassign.
2763	* @param uChannel Channel to set. Only valid if a valid SD stream number is specified.
2764	*
2765	* @remarks Can be called as a callback by the HDA codec.
2766	*/
2767	static DECLCALLBACK(int) hdaR3MixerControl(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, uint8_t uSD, uint8_t uChannel)
2768	{
2769	LogFunc(("enmMixerCtl=%s, uSD=%RU8, uChannel=%RU8\n", DrvAudioHlpAudMixerCtlToStr(enmMixerCtl), uSD, uChannel));
2770
2771	if (uSD == 0) /* Stream number 0 is reserved. */
2772	{
2773	Log2Func(("Invalid SDn (%RU8) number for mixer control '%s', ignoring\n", uSD, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl)));
2774	return VINF_SUCCESS;
2775	}
2776	/* uChannel is optional. */
2777
2778	/* SDn0 starts as 1. */
2779	Assert(uSD);
2780	uSD--;
2781
2782	# ifndef VBOX_WITH_AUDIO_HDA_MIC_IN
2783	/* Only SDI0 (Line-In) is supported. */
2784	if ( hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN
2785	&& uSD >= 1)
2786	{
2787	LogRel2(("HDA: Dedicated Mic-In support not imlpemented / built-in (stream #%RU8), using Line-In (stream #0) instead\n", uSD));
2788	uSD = 0;
2789	}
2790	# endif
2791
2792	int rc = VINF_SUCCESS;
2793
2794	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2795	if (pSink)
2796	{
2797	AssertPtr(pSink->pMixSink);
2798
2799	/* If this an output stream, determine the correct SD#. */
2800	if ( (uSD < HDA_MAX_SDI)
2801	&& AudioMixerSinkGetDir(pSink->pMixSink) == AUDMIXSINKDIR_OUTPUT)
2802	{
2803	uSD += HDA_MAX_SDI;
2804	}
2805
2806	/* Detach the existing stream from the sink. */
2807	if ( pSink->pStream
2808	&& ( pSink->pStream->u8SD != uSD
2809	\|\| pSink->pStream->u8Channel != uChannel)
2810	)
2811	{
2812	LogFunc(("Sink '%s' was assigned to stream #%RU8 (channel %RU8) before\n",
2813	pSink->pMixSink->pszName, pSink->pStream->u8SD, pSink->pStream->u8Channel));
2814
2815	hdaR3StreamLock(pSink->pStream);
2816
2817	/* Only disable the stream if the stream descriptor # has changed. */
2818	if (pSink->pStream->u8SD != uSD)
2819	hdaR3StreamEnable(pSink->pStream, false);
2820
2821	pSink->pStream->pMixSink = NULL;
2822
2823	hdaR3StreamUnlock(pSink->pStream);
2824
2825	pSink->pStream = NULL;
2826	}
2827
2828	Assert(uSD < HDA_MAX_STREAMS);
2829
2830	/* Attach the new stream to the sink.
2831	* Enabling the stream will be done by the gust via a separate SDnCTL call then. */
2832	if (pSink->pStream == NULL)
2833	{
2834	LogRel2(("HDA: Setting sink '%s' to stream #%RU8 (channel %RU8), mixer control=%s\n",
2835	pSink->pMixSink->pszName, uSD, uChannel, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl)));
2836
2837	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
2838	if (pStream)
2839	{
2840	hdaR3StreamLock(pStream);
2841
2842	pSink->pStream = pStream;
2843
2844	pStream->u8Channel = uChannel;
2845	pStream->pMixSink = pSink;
2846
2847	hdaR3StreamUnlock(pStream);
2848
2849	rc = VINF_SUCCESS;
2850	}
2851	else
2852	rc = VERR_NOT_IMPLEMENTED;
2853	}
2854	}
2855	else
2856	rc = VERR_NOT_FOUND;
2857
2858	if (RT_FAILURE(rc))
2859	LogRel(("HDA: Converter control for stream #%RU8 (channel %RU8) / mixer control '%s' failed with %Rrc, skipping\n",
2860	uSD, uChannel, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl), rc));
2861
2862	LogFlowFuncLeaveRC(rc);
2863	return rc;
2864	}
2865
2866	/**
2867	* @interface_method_impl{HDACODEC,pfnCbMixerSetVolume}
2868	*
2869	* Sets the volume of a specified mixer control.
2870	*
2871	* @return IPRT status code.
2872	* @param pThis HDA State.
2873	* @param enmMixerCtl Mixer control to set volume for.
2874	* @param pVol Pointer to volume data to set.
2875	*
2876	* @remarks Can be called as a callback by the HDA codec.
2877	*/
2878	static DECLCALLBACK(int) hdaR3MixerSetVolume(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOVOLUME pVol)
2879	{
2880	int rc;
2881
2882	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2883	if ( pSink
2884	&& pSink->pMixSink)
2885	{
2886	LogRel2(("HDA: Setting volume for mixer sink '%s' to %RU8/%RU8 (%s)\n",
2887	pSink->pMixSink->pszName, pVol->uLeft, pVol->uRight, pVol->fMuted ? "Muted" : "Unmuted"));
2888
2889	/* Set the volume.
2890	* We assume that the codec already converted it to the correct range. */
2891	rc = AudioMixerSinkSetVolume(pSink->pMixSink, pVol);
2892	}
2893	else
2894	rc = VERR_NOT_FOUND;
2895
2896	LogFlowFuncLeaveRC(rc);
2897	return rc;
2898	}
2899
2900	/**
2901	* Main routine for the stream's timer.
2902	*
2903	* @param pDevIns Device instance.
2904	* @param pTimer Timer this callback was called for.
2905	* @param pvUser Pointer to associated HDASTREAM.
2906	*/
2907	static DECLCALLBACK(void) hdaR3Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2908	{
2909	RT_NOREF(pDevIns, pTimer);
2910
2911	PHDASTREAM pStream = (PHDASTREAM)pvUser;
2912	AssertPtr(pStream);
2913
2914	PHDASTATE pThis = pStream->pHDAState;
2915
2916	DEVHDA_LOCK_BOTH_RETURN_VOID(pStream->pHDAState, pStream->u8SD);
2917
2918	hdaR3StreamUpdate(pStream, true /* fInTimer */);
2919
2920	/* Flag indicating whether to kick the timer again for a new data processing round. */
2921	bool fSinkActive = false;
2922	if (pStream->pMixSink)
2923	fSinkActive = AudioMixerSinkIsActive(pStream->pMixSink->pMixSink);
2924
2925	if (fSinkActive)
2926	{
2927	const bool fTimerScheduled = hdaR3StreamTransferIsScheduled(pStream);
2928	Log3Func(("fSinksActive=%RTbool, fTimerScheduled=%RTbool\n", fSinkActive, fTimerScheduled));
2929	if (!fTimerScheduled)
2930	hdaR3TimerSet(pThis, pStream,
2931	TMTimerGet(pThis->pTimer[pStream->u8SD])
2932	+ TMTimerGetFreq(pThis->pTimer[pStream->u8SD]) / pStream->pHDAState->uTimerHz,
2933	true /* fForce */);
2934	}
2935	else
2936	Log3Func(("fSinksActive=%RTbool\n", fSinkActive));
2937
2938	DEVHDA_UNLOCK_BOTH(pThis, pStream->u8SD);
2939	}
2940
2941	# ifdef HDA_USE_DMA_ACCESS_HANDLER
2942	/**
2943	* HC access handler for the FIFO.
2944	*
2945	* @returns VINF_SUCCESS if the handler have carried out the operation.
2946	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2947	* @param pVM VM Handle.
2948	* @param pVCpu The cross context CPU structure for the calling EMT.
2949	* @param GCPhys The physical address the guest is writing to.
2950	* @param pvPhys The HC mapping of that address.
2951	* @param pvBuf What the guest is reading/writing.
2952	* @param cbBuf How much it's reading/writing.
2953	* @param enmAccessType The access type.
2954	* @param enmOrigin Who is making the access.
2955	* @param pvUser User argument.
2956	*/
2957	static DECLCALLBACK(VBOXSTRICTRC) hdaR3DMAAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys,
2958	void *pvBuf, size_t cbBuf,
2959	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2960	{
2961	RT_NOREF(pVM, pVCpu, pvPhys, pvBuf, enmOrigin);
2962
2963	PHDADMAACCESSHANDLER pHandler = (PHDADMAACCESSHANDLER)pvUser;
2964	AssertPtr(pHandler);
2965
2966	PHDASTREAM pStream = pHandler->pStream;
2967	AssertPtr(pStream);
2968
2969	Assert(GCPhys >= pHandler->GCPhysFirst);
2970	Assert(GCPhys <= pHandler->GCPhysLast);
2971	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
2972
2973	/* Not within BDLE range? Bail out. */
2974	if ( (GCPhys < pHandler->BDLEAddr)
2975	\|\| (GCPhys + cbBuf > pHandler->BDLEAddr + pHandler->BDLESize))
2976	{
2977	return VINF_PGM_HANDLER_DO_DEFAULT;
2978	}
2979
2980	switch(enmAccessType)
2981	{
2982	case PGMACCESSTYPE_WRITE:
2983	{
2984	# ifdef DEBUG
2985	PHDASTREAMDBGINFO pStreamDbg = &pStream->Dbg;
2986
2987	const uint64_t tsNowNs = RTTimeNanoTS();
2988	const uint32_t tsElapsedMs = (tsNowNs - pStreamDbg->tsWriteSlotBegin) / 1000 / 1000;
2989
2990	uint64_t cWritesHz = ASMAtomicReadU64(&pStreamDbg->cWritesHz);
2991	uint64_t cbWrittenHz = ASMAtomicReadU64(&pStreamDbg->cbWrittenHz);
2992
2993	if (tsElapsedMs >= (1000 / HDA_TIMER_HZ_DEFAULT))
2994	{
2995	LogFunc(("[SD%RU8] %RU32ms elapsed, cbWritten=%RU64, cWritten=%RU64 -- %RU32 bytes on average per time slot (%zums)\n",
2996	pStream->u8SD, tsElapsedMs, cbWrittenHz, cWritesHz,
2997	ASMDivU64ByU32RetU32(cbWrittenHz, cWritesHz ? cWritesHz : 1), 1000 / HDA_TIMER_HZ_DEFAULT));
2998
2999	pStreamDbg->tsWriteSlotBegin = tsNowNs;
3000
3001	cWritesHz = 0;
3002	cbWrittenHz = 0;
3003	}
3004
3005	cWritesHz += 1;
3006	cbWrittenHz += cbBuf;
3007
3008	ASMAtomicIncU64(&pStreamDbg->cWritesTotal);
3009	ASMAtomicAddU64(&pStreamDbg->cbWrittenTotal, cbBuf);
3010
3011	ASMAtomicWriteU64(&pStreamDbg->cWritesHz, cWritesHz);
3012	ASMAtomicWriteU64(&pStreamDbg->cbWrittenHz, cbWrittenHz);
3013
3014	LogFunc(("[SD%RU8] Writing %3zu @ 0x%x (off %zu)\n",
3015	pStream->u8SD, cbBuf, GCPhys, GCPhys - pHandler->BDLEAddr));
3016
3017	LogFunc(("[SD%RU8] cWrites=%RU64, cbWritten=%RU64 -> %RU32 bytes on average\n",
3018	pStream->u8SD, pStreamDbg->cWritesTotal, pStreamDbg->cbWrittenTotal,
3019	ASMDivU64ByU32RetU32(pStreamDbg->cbWrittenTotal, pStreamDbg->cWritesTotal)));
3020	# endif
3021
3022	if (pThis->fDebugEnabled)
3023	{
3024	RTFILE fh;
3025	RTFileOpen(&fh, VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH "hdaDMAAccessWrite.pcm",
3026	RTFILE_O_OPEN_CREATE \| RTFILE_O_APPEND \| RTFILE_O_WRITE \| RTFILE_O_DENY_NONE);
3027	RTFileWrite(fh, pvBuf, cbBuf, NULL);
3028	RTFileClose(fh);
3029	}
3030
3031	# ifdef HDA_USE_DMA_ACCESS_HANDLER_WRITING
3032	PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
3033	AssertPtr(pCircBuf);
3034
3035	uint8_t pbBuf = (uint8_t )pvBuf;
3036	while (cbBuf)
3037	{
3038	/* Make sure we only copy as much as the stream's FIFO can hold (SDFIFOS, 18.2.39). */
3039	void *pvChunk;
3040	size_t cbChunk;
3041	RTCircBufAcquireWriteBlock(pCircBuf, cbBuf, &pvChunk, &cbChunk);
3042
3043	if (cbChunk)
3044	{
3045	memcpy(pvChunk, pbBuf, cbChunk);
3046
3047	pbBuf += cbChunk;
3048	Assert(cbBuf >= cbChunk);
3049	cbBuf -= cbChunk;
3050	}
3051	else
3052	{
3053	//AssertMsg(RTCircBufFree(pCircBuf), ("No more space but still %zu bytes to write\n", cbBuf));
3054	break;
3055	}
3056
3057	LogFunc(("[SD%RU8] cbChunk=%zu\n", pStream->u8SD, cbChunk));
3058
3059	RTCircBufReleaseWriteBlock(pCircBuf, cbChunk);
3060	}
3061	# endif /* HDA_USE_DMA_ACCESS_HANDLER_WRITING */
3062	break;
3063	}
3064
3065	default:
3066	AssertMsgFailed(("Access type not implemented\n"));
3067	break;
3068	}
3069
3070	return VINF_PGM_HANDLER_DO_DEFAULT;
3071	}
3072	# endif /* HDA_USE_DMA_ACCESS_HANDLER */
3073
3074	/**
3075	* Soft reset of the device triggered via GCTL.
3076	*
3077	* @param pThis HDA state.
3078	*
3079	*/
3080	static void hdaR3GCTLReset(PHDASTATE pThis)
3081	{
3082	LogFlowFuncEnter();
3083
3084	pThis->cStreamsActive = 0;
3085
3086	HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(HDA_MAX_SDO, HDA_MAX_SDI, 0, 0, 1); /* see 6.2.1 */
3087	HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
3088	HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
3089	HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
3090	HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
3091	HDA_REG(pThis, CORBSIZE) = 0x42; /* Up to 256 CORB entries see 6.2.1 */
3092	HDA_REG(pThis, RIRBSIZE) = 0x42; /* Up to 256 RIRB entries see 6.2.1 */
3093	HDA_REG(pThis, CORBRP) = 0x0;
3094	HDA_REG(pThis, CORBWP) = 0x0;
3095	HDA_REG(pThis, RIRBWP) = 0x0;
3096	/* Some guests (like Haiku) don't set RINTCNT explicitly but expect an interrupt after each
3097	* RIRB response -- so initialize RINTCNT to 1 by default. */
3098	HDA_REG(pThis, RINTCNT) = 0x1;
3099
3100	/*
3101	* Stop any audio currently playing and/or recording.
3102	*/
3103	pThis->SinkFront.pStream = NULL;
3104	if (pThis->SinkFront.pMixSink)
3105	AudioMixerSinkReset(pThis->SinkFront.pMixSink);
3106	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3107	pThis->SinkMicIn.pStream = NULL;
3108	if (pThis->SinkMicIn.pMixSink)
3109	AudioMixerSinkReset(pThis->SinkMicIn.pMixSink);
3110	# endif
3111	pThis->SinkLineIn.pStream = NULL;
3112	if (pThis->SinkLineIn.pMixSink)
3113	AudioMixerSinkReset(pThis->SinkLineIn.pMixSink);
3114	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3115	pThis->SinkCenterLFE = NULL;
3116	if (pThis->SinkCenterLFE.pMixSink)
3117	AudioMixerSinkReset(pThis->SinkCenterLFE.pMixSink);
3118	pThis->SinkRear.pStream = NULL;
3119	if (pThis->SinkRear.pMixSink)
3120	AudioMixerSinkReset(pThis->SinkRear.pMixSink);
3121	# endif
3122
3123	/*
3124	* Reset the codec.
3125	*/
3126	if ( pThis->pCodec
3127	&& pThis->pCodec->pfnReset)
3128	{
3129	pThis->pCodec->pfnReset(pThis->pCodec);
3130	}
3131
3132	/*
3133	* Set some sensible defaults for which HDA sinks
3134	* are connected to which stream number.
3135	*
3136	* We use SD0 for input and SD4 for output by default.
3137	* These stream numbers can be changed by the guest dynamically lateron.
3138	*/
3139	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3140	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_MIC_IN , 1 /* SD0 /, 0 / Channel */);
3141	# endif
3142	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_LINE_IN , 1 /* SD0 /, 0 / Channel */);
3143
3144	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_FRONT , 5 /* SD4 /, 0 / Channel */);
3145	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3146	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_CENTER_LFE, 5 /* SD4 /, 0 / Channel */);
3147	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_REAR , 5 /* SD4 /, 0 / Channel */);
3148	# endif
3149
3150	/* Reset CORB. */
3151	pThis->cbCorbBuf = HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE;
3152	RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
3153
3154	/* Reset RIRB. */
3155	pThis->cbRirbBuf = HDA_RIRB_SIZE * HDA_RIRB_ELEMENT_SIZE;
3156	RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
3157
3158	/* Clear our internal response interrupt counter. */
3159	pThis->u16RespIntCnt = 0;
3160
3161	for (uint8_t uSD = 0; uSD < HDA_MAX_STREAMS; ++uSD)
3162	{
3163	int rc2 = hdaR3StreamEnable(&pThis->aStreams[uSD], false /* fEnable */);
3164	if (RT_SUCCESS(rc2))
3165	{
3166	/* Remove the RUN bit from SDnCTL in case the stream was in a running state before. */
3167	HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_RUN;
3168	hdaR3StreamReset(pThis, &pThis->aStreams[uSD], uSD);
3169	}
3170	}
3171
3172	/* Clear stream tags <-> objects mapping table. */
3173	RT_ZERO(pThis->aTags);
3174
3175	/* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
3176	HDA_REG(pThis, STATESTS) = 0x1;
3177
3178	LogFlowFuncLeave();
3179	LogRel(("HDA: Reset\n"));
3180	}
3181
3182	#endif /* IN_RING3 */
3183
3184	/* MMIO callbacks */
3185
3186	/**
3187	* @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
3188	*
3189	* @note During implementation, we discovered so-called "forgotten" or "hole"
3190	* registers whose description is not listed in the RPM, datasheet, or
3191	* spec.
3192	*/
3193	PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
3194	{
3195	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3196	int rc;
3197	RT_NOREF_PV(pvUser);
3198	Assert(pThis->uAlignmentCheckMagic == HDASTATE_ALIGNMENT_CHECK_MAGIC);
3199
3200	/*
3201	* Look up and log.
3202	*/
3203	uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3204	int idxRegDsc = hdaRegLookup(offReg); /* Register descriptor index. */
3205	#ifdef LOG_ENABLED
3206	unsigned const cbLog = cb;
3207	uint32_t offRegLog = offReg;
3208	#endif
3209
3210	Log3Func(("offReg=%#x cb=%#x\n", offReg, cb));
3211	Assert(cb == 4); Assert((offReg & 3) == 0);
3212
3213	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
3214
3215	if (!(HDA_REG(pThis, GCTL) & HDA_GCTL_CRST) && idxRegDsc != HDA_REG_GCTL)
3216	LogFunc(("Access to registers except GCTL is blocked while reset\n"));
3217
3218	if (idxRegDsc == -1)
3219	LogRel(("HDA: Invalid read access @0x%x (bytes=%u)\n", offReg, cb));
3220
3221	if (idxRegDsc != -1)
3222	{
3223	/* Leave lock before calling read function. */
3224	DEVHDA_UNLOCK(pThis);
3225
3226	/* ASSUMES gapless DWORD at end of map. */
3227	if (g_aHdaRegMap[idxRegDsc].size == 4)
3228	{
3229	/*
3230	* Straight forward DWORD access.
3231	*/
3232	rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
3233	Log3Func(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, (uint32_t )pv, rc));
3234	}
3235	else
3236	{
3237	/*
3238	* Multi register read (unless there are trailing gaps).
3239	* ASSUMES that only DWORD reads have sideeffects.
3240	*/
3241	#ifdef IN_RING3
3242	uint32_t u32Value = 0;
3243	unsigned cbLeft = 4;
3244	do
3245	{
3246	uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
3247	uint32_t u32Tmp = 0;
3248
3249	rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
3250	Log3Func(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
3251	if (rc != VINF_SUCCESS)
3252	break;
3253	u32Value \|= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
3254
3255	cbLeft -= cbReg;
3256	offReg += cbReg;
3257	idxRegDsc++;
3258	} while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
3259
3260	if (rc == VINF_SUCCESS)
3261	(uint32_t )pv = u32Value;
3262	else
3263	Assert(!IOM_SUCCESS(rc));
3264	#else /* !IN_RING3 */
3265	/* Take the easy way out. */
3266	rc = VINF_IOM_R3_MMIO_READ;
3267	#endif /* !IN_RING3 */
3268	}
3269	}
3270	else
3271	{
3272	DEVHDA_UNLOCK(pThis);
3273
3274	rc = VINF_IOM_MMIO_UNUSED_FF;
3275	Log3Func(("\tHole at %x is accessed for read\n", offReg));
3276	}
3277
3278	/*
3279	* Log the outcome.
3280	*/
3281	#ifdef LOG_ENABLED
3282	if (cbLog == 4)
3283	Log3Func(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, (uint32_t )pv, rc));
3284	else if (cbLog == 2)
3285	Log3Func(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, (uint16_t )pv, rc));
3286	else if (cbLog == 1)
3287	Log3Func(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, (uint8_t )pv, rc));
3288	#endif
3289	return rc;
3290	}
3291
3292
3293	DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
3294	{
3295	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
3296
3297	if (!(HDA_REG(pThis, GCTL) & HDA_GCTL_CRST) && idxRegDsc != HDA_REG_GCTL)
3298	{
3299	Log(("hdaWriteReg: Warning: Access to %s is blocked while controller is in reset mode\n", g_aHdaRegMap[idxRegDsc].abbrev));
3300	LogRel2(("HDA: Warning: Access to register %s is blocked while controller is in reset mode\n",
3301	g_aHdaRegMap[idxRegDsc].abbrev));
3302
3303	DEVHDA_UNLOCK(pThis);
3304	return VINF_SUCCESS;
3305	}
3306
3307	/*
3308	* Handle RD (register description) flags.
3309	*/
3310
3311	/* For SDI / SDO: Check if writes to those registers are allowed while SDCTL's RUN bit is set. */
3312	if (idxRegDsc >= HDA_NUM_GENERAL_REGS)
3313	{
3314	const uint32_t uSDCTL = HDA_STREAM_REG(pThis, CTL, HDA_SD_NUM_FROM_REG(pThis, CTL, idxRegDsc));
3315
3316	/*
3317	* Some OSes (like Win 10 AU) violate the spec by writing stuff to registers which are not supposed to be be touched
3318	* while SDCTL's RUN bit is set. So just ignore those values.
3319	*/
3320
3321	/* Is the RUN bit currently set? */
3322	if ( RT_BOOL(uSDCTL & HDA_SDCTL_RUN)
3323	/* Are writes to the register denied if RUN bit is set? */
3324	&& !(g_aHdaRegMap[idxRegDsc].fFlags & HDA_RD_FLAG_SD_WRITE_RUN))
3325	{
3326	Log(("hdaWriteReg: Warning: Access to %s is blocked! %R[sdctl]\n", g_aHdaRegMap[idxRegDsc].abbrev, uSDCTL));
3327	LogRel2(("HDA: Warning: Access to register %s is blocked while the stream's RUN bit is set\n",
3328	g_aHdaRegMap[idxRegDsc].abbrev));
3329
3330	DEVHDA_UNLOCK(pThis);
3331	return VINF_SUCCESS;
3332	}
3333	}
3334
3335	/* Leave the lock before calling write function. */
3336	/** @todo r=bird: Why do we need to do that?? There is no
3337	* explanation why this is necessary here...
3338	*
3339	* More or less all write functions retake the lock, so why not let
3340	* those who need to drop the lock or take additional locks release
3341	* it? See, releasing a lock you already got always runs the risk
3342	* of someone else grabbing it and forcing you to wait, better to
3343	* do the two-three things a write handle needs to do than enter
3344	* and exit the lock all the time. */
3345	DEVHDA_UNLOCK(pThis);
3346
3347	#ifdef LOG_ENABLED
3348	uint32_t const idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3349	uint32_t const u32OldValue = pThis->au32Regs[idxRegMem];
3350	#endif
3351	int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
3352	Log3Func(("Written value %#x to %s[%d byte]; %x => %x%s, rc=%d\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
3353	g_aHdaRegMap[idxRegDsc].size, u32OldValue, pThis->au32Regs[idxRegMem], pszLog, rc));
3354	RT_NOREF(pszLog);
3355	return rc;
3356	}
3357
3358
3359	/**
3360	* @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
3361	*/
3362	PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
3363	{
3364	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3365	int rc;
3366	RT_NOREF_PV(pvUser);
3367	Assert(pThis->uAlignmentCheckMagic == HDASTATE_ALIGNMENT_CHECK_MAGIC);
3368
3369	/*
3370	* The behavior of accesses that aren't aligned on natural boundraries is
3371	* undefined. Just reject them outright.
3372	*/
3373	/** @todo IOM could check this, it could also split the 8 byte accesses for us. */
3374	Assert(cb == 1 \|\| cb == 2 \|\| cb == 4 \|\| cb == 8);
3375	if (GCPhysAddr & (cb - 1))
3376	return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
3377
3378	/*
3379	* Look up and log the access.
3380	*/
3381	uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3382	int idxRegDsc = hdaRegLookup(offReg);
3383	#if defined(IN_RING3) \|\| defined(LOG_ENABLED)
3384	uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
3385	#endif
3386	uint64_t u64Value;
3387	if (cb == 4) u64Value = (uint32_t const )pv;
3388	else if (cb == 2) u64Value = (uint16_t const )pv;
3389	else if (cb == 1) u64Value = (uint8_t const )pv;
3390	else if (cb == 8) u64Value = (uint64_t const )pv;
3391	else
3392	{
3393	u64Value = 0; /* shut up gcc. */
3394	AssertReleaseMsgFailed(("%u\n", cb));
3395	}
3396
3397	#ifdef LOG_ENABLED
3398	uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
3399	if (idxRegDsc == -1)
3400	Log3Func(("@%#05x u32=%#010x cb=%d\n", offReg, (uint32_t const )pv, cb));
3401	else if (cb == 4)
3402	Log3Func(("@%#05x u32=%#010x %s\n", offReg, (uint32_t )pv, g_aHdaRegMap[idxRegDsc].abbrev));
3403	else if (cb == 2)
3404	Log3Func(("@%#05x u16=%#06x (%#010x) %s\n", offReg, (uint16_t )pv, (uint32_t )pv, g_aHdaRegMap[idxRegDsc].abbrev));
3405	else if (cb == 1)
3406	Log3Func(("@%#05x u8=%#04x (%#010x) %s\n", offReg, (uint8_t )pv, (uint32_t )pv, g_aHdaRegMap[idxRegDsc].abbrev));
3407
3408	if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
3409	Log3Func(("\tsize=%RU32 != cb=%u!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
3410	#endif
3411
3412	/*
3413	* Try for a direct hit first.
3414	*/
3415	if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
3416	{
3417	rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
3418	Log3Func(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
3419	}
3420	/*
3421	* Partial or multiple register access, loop thru the requested memory.
3422	*/
3423	else
3424	{
3425	#ifdef IN_RING3
3426	/*
3427	* If it's an access beyond the start of the register, shift the input
3428	* value and fill in missing bits. Natural alignment rules means we
3429	* will only see 1 or 2 byte accesses of this kind, so no risk of
3430	* shifting out input values.
3431	*/
3432	if (idxRegDsc == -1 && (idxRegDsc = hdaR3RegLookupWithin(offReg)) != -1)
3433	{
3434	uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
3435	offReg -= cbBefore;
3436	idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3437	u64Value <<= cbBefore * 8;
3438	u64Value \|= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
3439	Log3Func(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
3440	cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
3441	}
3442
3443	/* Loop thru the write area, it may cover multiple registers. */
3444	rc = VINF_SUCCESS;
3445	for (;;)
3446	{
3447	uint32_t cbReg;
3448	if (idxRegDsc != -1)
3449	{
3450	idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3451	cbReg = g_aHdaRegMap[idxRegDsc].size;
3452	if (cb < cbReg)
3453	{
3454	u64Value \|= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
3455	Log3Func(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
3456	g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
3457	}
3458	# ifdef LOG_ENABLED
3459	uint32_t uLogOldVal = pThis->au32Regs[idxRegMem];
3460	# endif
3461	rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
3462	Log3Func(("\t%#x -> %#x\n", uLogOldVal, pThis->au32Regs[idxRegMem]));
3463	}
3464	else
3465	{
3466	LogRel(("HDA: Invalid write access @0x%x\n", offReg));
3467	cbReg = 1;
3468	}
3469	if (rc != VINF_SUCCESS)
3470	break;
3471	if (cbReg >= cb)
3472	break;
3473
3474	/* Advance. */
3475	offReg += cbReg;
3476	cb -= cbReg;
3477	u64Value >>= cbReg * 8;
3478	if (idxRegDsc == -1)
3479	idxRegDsc = hdaRegLookup(offReg);
3480	else
3481	{
3482	idxRegDsc++;
3483	if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
3484	\|\| g_aHdaRegMap[idxRegDsc].offset != offReg)
3485	{
3486	idxRegDsc = -1;
3487	}
3488	}
3489	}
3490
3491	#else /* !IN_RING3 */
3492	/* Take the simple way out. */
3493	rc = VINF_IOM_R3_MMIO_WRITE;
3494	#endif /* !IN_RING3 */
3495	}
3496
3497	return rc;
3498	}
3499
3500
3501	/* PCI callback. */
3502
3503	#ifdef IN_RING3
3504	/**
3505	* @callback_method_impl{FNPCIIOREGIONMAP}
3506	*/
3507	static DECLCALLBACK(int) hdaR3PciIoRegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3508	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
3509	{
3510	RT_NOREF(iRegion, enmType);
3511	PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
3512
3513	/*
3514	* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
3515	*
3516	* Let IOM talk DWORDs when reading, saves a lot of complications. On
3517	* writing though, we have to do it all ourselves because of sideeffects.
3518	*/
3519	Assert(enmType == PCI_ADDRESS_SPACE_MEM);
3520	int rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /pvUser/,
3521	IOMMMIO_FLAGS_READ_DWORD
3522	\| IOMMMIO_FLAGS_WRITE_PASSTHRU,
3523	hdaMMIOWrite, hdaMMIORead, "HDA");
3524
3525	if (RT_FAILURE(rc))
3526	return rc;
3527
3528	if (pThis->fRZEnabled)
3529	{
3530	rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /pvUser/,
3531	"hdaMMIOWrite", "hdaMMIORead");
3532	if (RT_FAILURE(rc))
3533	return rc;
3534
3535	rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /pvUser/,
3536	"hdaMMIOWrite", "hdaMMIORead");
3537	if (RT_FAILURE(rc))
3538	return rc;
3539	}
3540
3541	pThis->MMIOBaseAddr = GCPhysAddress;
3542	return VINF_SUCCESS;
3543	}
3544
3545
3546	/* Saved state workers and callbacks. */
3547
3548	static int hdaR3SaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStream)
3549	{
3550	RT_NOREF(pDevIns);
3551	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
3552	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3553	#endif
3554
3555	Log2Func(("[SD%RU8]\n", pStream->u8SD));
3556
3557	/* Save stream ID. */
3558	int rc = SSMR3PutU8(pSSM, pStream->u8SD);
3559	AssertRCReturn(rc, rc);
3560	Assert(pStream->u8SD < HDA_MAX_STREAMS);
3561
3562	rc = SSMR3PutStructEx(pSSM, &pStream->State, sizeof(HDASTREAMSTATE), 0 /fFlags/, g_aSSMStreamStateFields7, NULL);
3563	AssertRCReturn(rc, rc);
3564
3565	#ifdef VBOX_STRICT
3566	uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
3567	HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
3568	uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
3569	uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
3570
3571	Assert(u64BaseDMA == pStream->u64BDLBase);
3572	Assert(u16LVI == pStream->u16LVI);
3573	Assert(u32CBL == pStream->u32CBL);
3574	#endif
3575
3576	rc = SSMR3PutStructEx(pSSM, &pStream->State.BDLE.Desc, sizeof(HDABDLEDESC),
3577	0 /fFlags/, g_aSSMBDLEDescFields7, NULL);
3578	AssertRCReturn(rc, rc);
3579
3580	rc = SSMR3PutStructEx(pSSM, &pStream->State.BDLE.State, sizeof(HDABDLESTATE),
3581	0 /fFlags/, g_aSSMBDLEStateFields7, NULL);
3582	AssertRCReturn(rc, rc);
3583
3584	rc = SSMR3PutStructEx(pSSM, &pStream->State.Period, sizeof(HDASTREAMPERIOD),
3585	0 /* fFlags */, g_aSSMStreamPeriodFields7, NULL);
3586	AssertRCReturn(rc, rc);
3587
3588	#ifdef VBOX_STRICT /* Sanity checks. */
3589	PHDABDLE pBDLE = &pStream->State.BDLE;
3590	if (u64BaseDMA)
3591	{
3592	Assert(pStream->State.uCurBDLE <= u16LVI + 1);
3593
3594	HDABDLE curBDLE;
3595	rc = hdaR3BDLEFetch(pThis, &curBDLE, u64BaseDMA, pStream->State.uCurBDLE);
3596	AssertRC(rc);
3597
3598	Assert(curBDLE.Desc.u32BufSize == pBDLE->Desc.u32BufSize);
3599	Assert(curBDLE.Desc.u64BufAdr == pBDLE->Desc.u64BufAdr);
3600	Assert(curBDLE.Desc.fFlags == pBDLE->Desc.fFlags);
3601	}
3602	else
3603	{
3604	Assert(pBDLE->Desc.u64BufAdr == 0);
3605	Assert(pBDLE->Desc.u32BufSize == 0);
3606	}
3607	#endif
3608
3609	uint32_t cbCircBufSize = 0;
3610	uint32_t cbCircBufUsed = 0;
3611
3612	if (pStream->State.pCircBuf)
3613	{
3614	cbCircBufSize = (uint32_t)RTCircBufSize(pStream->State.pCircBuf);
3615	cbCircBufUsed = (uint32_t)RTCircBufUsed(pStream->State.pCircBuf);
3616	}
3617
3618	rc = SSMR3PutU32(pSSM, cbCircBufSize);
3619	AssertRCReturn(rc, rc);
3620
3621	rc = SSMR3PutU32(pSSM, cbCircBufUsed);
3622	AssertRCReturn(rc, rc);
3623
3624	if (cbCircBufUsed)
3625	{
3626	/*
3627	* We now need to get the circular buffer's data without actually modifying
3628	* the internal read / used offsets -- otherwise we would end up with broken audio
3629	* data after saving the state.
3630	*
3631	* So get the current read offset and serialize the buffer data manually based on that.
3632	*/
3633	size_t const offBuf = RTCircBufOffsetRead(pStream->State.pCircBuf);
3634	void *pvBuf;
3635	size_t cbBuf;
3636	RTCircBufAcquireReadBlock(pStream->State.pCircBuf, cbCircBufUsed, &pvBuf, &cbBuf);
3637	#if 0 /** @todo r=bird: The disabled code crashes on me. The #else case contains something that seems
3638	* to make more sense to me. I'm not say this is correct code. Please review, fix, and remove. */
3639
3640	if (cbBuf)
3641	{
3642	size_t cbToRead = cbCircBufUsed;
3643	size_t cbEnd = 0;
3644
3645	if (cbCircBufUsed > offBuf)
3646	cbEnd = cbCircBufUsed - offBuf;
3647
3648	if (cbEnd) /* Save end of buffer first. */
3649	{
3650	rc = SSMR3PutMem(pSSM, (uint8_t )pvBuf + cbCircBufSize - cbEnd / End of buffer */, cbEnd);
3651	AssertRCReturn(rc, rc);
3652
3653	Assert(cbToRead >= cbEnd);
3654	cbToRead -= cbEnd;
3655	}
3656
3657	if (cbToRead) /* Save remaining stuff at start of buffer (if any). */
3658	{
3659	rc = SSMR3PutMem(pSSM, (uint8_t )pvBuf - cbCircBufUsed / Start of buffer */, cbToRead);
3660	AssertRCReturn(rc, rc);
3661	}
3662	}
3663	#else
3664	Assert(cbBuf);
3665	rc = SSMR3PutMem(pSSM, pvBuf, cbBuf);
3666	if (cbBuf < cbCircBufUsed)
3667	rc = SSMR3PutMem(pSSM, (uint8_t *)pvBuf - offBuf, cbCircBufUsed - cbBuf);
3668	#endif
3669
3670	RTCircBufReleaseReadBlock(pStream->State.pCircBuf, 0 /* Don't advance read pointer -- see comment above */);
3671	}
3672
3673	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n",
3674	pStream->u8SD,
3675	HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), HDA_STREAM_REG(pThis, CBL, pStream->u8SD), HDA_STREAM_REG(pThis, LVI, pStream->u8SD)));
3676
3677	#ifdef LOG_ENABLED
3678	hdaR3BDLEDumpAll(pThis, pStream->u64BDLBase, pStream->u16LVI + 1);
3679	#endif
3680
3681	return rc;
3682	}
3683
3684	/**
3685	* @callback_method_impl{FNSSMDEVSAVEEXEC}
3686	*/
3687	static DECLCALLBACK(int) hdaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3688	{
3689	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3690
3691	/* Save Codec nodes states. */
3692	hdaCodecSaveState(pThis->pCodec, pSSM);
3693
3694	/* Save MMIO registers. */
3695	SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3696	SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3697
3698	/* Save controller-specifc internals. */
3699	SSMR3PutU64(pSSM, pThis->u64WalClk);
3700	SSMR3PutU8(pSSM, pThis->u8IRQL);
3701
3702	/* Save number of streams. */
3703	SSMR3PutU32(pSSM, HDA_MAX_STREAMS);
3704
3705	/* Save stream states. */
3706	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
3707	{
3708	int rc = hdaR3SaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
3709	AssertRCReturn(rc, rc);
3710	}
3711
3712	return VINF_SUCCESS;
3713	}
3714
3715	/**
3716	* Does required post processing when loading a saved state.
3717	*
3718	* @param pThis Pointer to HDA state.
3719	*/
3720	static int hdaR3LoadExecPost(PHDASTATE pThis)
3721	{
3722	int rc = VINF_SUCCESS;
3723
3724	/*
3725	* Enable all previously active streams.
3726	*/
3727	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
3728	{
3729	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, i);
3730	if (pStream)
3731	{
3732	int rc2;
3733
3734	bool fActive = RT_BOOL(HDA_STREAM_REG(pThis, CTL, i) & HDA_SDCTL_RUN);
3735	if (fActive)
3736	{
3737	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
3738	/* Make sure to also create the async I/O thread before actually enabling the stream. */
3739	rc2 = hdaR3StreamAsyncIOCreate(pStream);
3740	AssertRC(rc2);
3741
3742	/* ... and enabling it. */
3743	hdaR3StreamAsyncIOEnable(pStream, true /* fEnable */);
3744	#endif
3745	/* Resume the stream's period. */
3746	hdaR3StreamPeriodResume(&pStream->State.Period);
3747
3748	/* (Re-)enable the stream. */
3749	rc2 = hdaR3StreamEnable(pStream, true /* fEnable */);
3750	AssertRC(rc2);
3751
3752	/* Add the stream to the device setup. */
3753	rc2 = hdaR3AddStream(pThis, &pStream->State.Cfg);
3754	AssertRC(rc2);
3755
3756	#ifdef HDA_USE_DMA_ACCESS_HANDLER
3757	/* (Re-)install the DMA handler. */
3758	hdaR3StreamRegisterDMAHandlers(pThis, pStream);
3759	#endif
3760	if (hdaR3StreamTransferIsScheduled(pStream))
3761	hdaR3TimerSet(pThis, pStream, hdaR3StreamTransferGetNext(pStream), true /* fForce */);
3762
3763	/* Also keep track of the currently active streams. */
3764	pThis->cStreamsActive++;
3765	}
3766	}
3767	}
3768
3769	LogFlowFuncLeaveRC(rc);
3770	return rc;
3771	}
3772
3773
3774	/**
3775	* Handles loading of all saved state versions older than the current one.
3776	*
3777	* @param pThis Pointer to HDA state.
3778	* @param pSSM Pointer to SSM handle.
3779	* @param uVersion Saved state version to load.
3780	* @param uPass Loading stage to handle.
3781	*/
3782	static int hdaR3LoadExecLegacy(PHDASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3783	{
3784	RT_NOREF(uPass);
3785
3786	int rc = VINF_SUCCESS;
3787
3788	/*
3789	* Load MMIO registers.
3790	*/
3791	uint32_t cRegs;
3792	switch (uVersion)
3793	{
3794	case HDA_SSM_VERSION_1:
3795	/* Starting with r71199, we would save 112 instead of 113
3796	registers due to some code cleanups. This only affected trunk
3797	builds in the 4.1 development period. */
3798	cRegs = 113;
3799	if (SSMR3HandleRevision(pSSM) >= 71199)
3800	{
3801	uint32_t uVer = SSMR3HandleVersion(pSSM);
3802	if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3803	&& VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3804	&& VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3805	cRegs = 112;
3806	}
3807	break;
3808
3809	case HDA_SSM_VERSION_2:
3810	case HDA_SSM_VERSION_3:
3811	cRegs = 112;
3812	AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= 112);
3813	break;
3814
3815	/* Since version 4 we store the register count to stay flexible. */
3816	case HDA_SSM_VERSION_4:
3817	case HDA_SSM_VERSION_5:
3818	case HDA_SSM_VERSION_6:
3819	rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3820	if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3821	LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3822	break;
3823
3824	default:
3825	LogRel(("HDA: Warning: Unsupported / too new saved state version (%RU32)\n", uVersion));
3826	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3827	}
3828
3829	if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3830	{
3831	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3832	SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3833	}
3834	else
3835	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3836
3837	/* Make sure to update the base addresses first before initializing any streams down below. */
3838	pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3839	pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3840	pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE) & DPBASE_ADDR_MASK, HDA_REG(pThis, DPUBASE));
3841
3842	/* Also make sure to update the DMA position bit if this was enabled when saving the state. */
3843	pThis->fDMAPosition = RT_BOOL(HDA_REG(pThis, DPLBASE) & RT_BIT_32(0));
3844
3845	/*
3846	* Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
3847	* every BDLE state, whereas it only needs to be stored
3848	* once for every stream. Most of the BDLE state we can
3849	* get out of the registers anyway, so just ignore those values.
3850	*
3851	* Also, only the current BDLE was saved, regardless whether
3852	* there were more than one (and there are at least two entries,
3853	* according to the spec).
3854	*/
3855	#define HDA_SSM_LOAD_BDLE_STATE_PRE_V5(v, x) \
3856	{ \
3857	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */ \
3858	AssertRCReturn(rc, rc); \
3859	rc = SSMR3GetU64(pSSM, &x.Desc.u64BufAdr); /* u64BdleCviAddr */ \
3860	AssertRCReturn(rc, rc); \
3861	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleMaxCvi */ \
3862	AssertRCReturn(rc, rc); \
3863	rc = SSMR3GetU32(pSSM, &x.State.u32BDLIndex); /* u32BdleCvi */ \
3864	AssertRCReturn(rc, rc); \
3865	rc = SSMR3GetU32(pSSM, &x.Desc.u32BufSize); /* u32BdleCviLen */ \
3866	AssertRCReturn(rc, rc); \
3867	rc = SSMR3GetU32(pSSM, &x.State.u32BufOff); /* u32BdleCviPos */ \
3868	AssertRCReturn(rc, rc); \
3869	bool fIOC; \
3870	rc = SSMR3GetBool(pSSM, &fIOC); /* fBdleCviIoc */ \
3871	AssertRCReturn(rc, rc); \
3872	x.Desc.fFlags = fIOC ? HDA_BDLE_FLAG_IOC : 0; \
3873	rc = SSMR3GetU32(pSSM, &x.State.cbBelowFIFOW); /* cbUnderFifoW */ \
3874	AssertRCReturn(rc, rc); \
3875	rc = SSMR3Skip(pSSM, sizeof(uint8_t) * 256); /* FIFO */ \
3876	AssertRCReturn(rc, rc); \
3877	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */ \
3878	AssertRCReturn(rc, rc); \
3879	}
3880
3881	/*
3882	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3883	*/
3884	switch (uVersion)
3885	{
3886	case HDA_SSM_VERSION_1:
3887	case HDA_SSM_VERSION_2:
3888	case HDA_SSM_VERSION_3:
3889	case HDA_SSM_VERSION_4:
3890	{
3891	/* Only load the internal states.
3892	* The rest will be initialized from the saved registers later. */
3893
3894	/* Note 1: Only the current BDLE for a stream was saved! */
3895	/* Note 2: The stream's saving order is/was fixed, so don't touch! */
3896
3897	/* Output */
3898	PHDASTREAM pStream = &pThis->aStreams[4];
3899	rc = hdaR3StreamInit(pStream, 4 /* Stream descriptor, hardcoded */);
3900	if (RT_FAILURE(rc))
3901	break;
3902	HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
3903	pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
3904
3905	/* Microphone-In */
3906	pStream = &pThis->aStreams[2];
3907	rc = hdaR3StreamInit(pStream, 2 /* Stream descriptor, hardcoded */);
3908	if (RT_FAILURE(rc))
3909	break;
3910	HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
3911	pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
3912
3913	/* Line-In */
3914	pStream = &pThis->aStreams[0];
3915	rc = hdaR3StreamInit(pStream, 0 /* Stream descriptor, hardcoded */);
3916	if (RT_FAILURE(rc))
3917	break;
3918	HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
3919	pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
3920	break;
3921	}
3922
3923	#undef HDA_SSM_LOAD_BDLE_STATE_PRE_V5
3924
3925	default: /* Since v5 we support flexible stream and BDLE counts. */
3926	{
3927	uint32_t cStreams;
3928	rc = SSMR3GetU32(pSSM, &cStreams);
3929	if (RT_FAILURE(rc))
3930	break;
3931
3932	if (cStreams > HDA_MAX_STREAMS)
3933	cStreams = HDA_MAX_STREAMS; /* Sanity. */
3934
3935	/* Load stream states. */
3936	for (uint32_t i = 0; i < cStreams; i++)
3937	{
3938	uint8_t uStreamID;
3939	rc = SSMR3GetU8(pSSM, &uStreamID);
3940	if (RT_FAILURE(rc))
3941	break;
3942
3943	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uStreamID);
3944	HDASTREAM StreamDummy;
3945
3946	if (!pStream)
3947	{
3948	pStream = &StreamDummy;
3949	LogRel2(("HDA: Warning: Stream ID=%RU32 not supported, skipping to load ...\n", uStreamID));
3950	}
3951
3952	rc = hdaR3StreamInit(pStream, uStreamID);
3953	if (RT_FAILURE(rc))
3954	{
3955	LogRel(("HDA: Stream #%RU32: Initialization of stream %RU8 failed, rc=%Rrc\n", i, uStreamID, rc));
3956	break;
3957	}
3958
3959	/*
3960	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3961	*/
3962
3963	if (uVersion == HDA_SSM_VERSION_5)
3964	{
3965	/* Get the current BDLE entry and skip the rest. */
3966	uint16_t cBDLE;
3967
3968	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
3969	AssertRC(rc);
3970	rc = SSMR3GetU16(pSSM, &cBDLE); /* cBDLE */
3971	AssertRC(rc);
3972	rc = SSMR3GetU16(pSSM, &pStream->State.uCurBDLE); /* uCurBDLE */
3973	AssertRC(rc);
3974	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
3975	AssertRC(rc);
3976
3977	uint32_t u32BDLEIndex;
3978	for (uint16_t a = 0; a < cBDLE; a++)
3979	{
3980	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
3981	AssertRC(rc);
3982	rc = SSMR3GetU32(pSSM, &u32BDLEIndex); /* u32BDLIndex */
3983	AssertRC(rc);
3984
3985	/* Does the current BDLE index match the current BDLE to process? */
3986	if (u32BDLEIndex == pStream->State.uCurBDLE)
3987	{
3988	rc = SSMR3GetU32(pSSM, &pStream->State.BDLE.State.cbBelowFIFOW); /* cbBelowFIFOW */
3989	AssertRC(rc);
3990	rc = SSMR3Skip(pSSM, sizeof(uint8_t) * 256); /* FIFO, deprecated */
3991	AssertRC(rc);
3992	rc = SSMR3GetU32(pSSM, &pStream->State.BDLE.State.u32BufOff); /* u32BufOff */
3993	AssertRC(rc);
3994	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
3995	AssertRC(rc);
3996	}
3997	else /* Skip not current BDLEs. */
3998	{
3999	rc = SSMR3Skip(pSSM, sizeof(uint32_t) /* cbBelowFIFOW */
4000	+ sizeof(uint8_t) * 256 /* au8FIFO */
4001	+ sizeof(uint32_t) /* u32BufOff */
4002	+ sizeof(uint32_t)); /* End marker */
4003	AssertRC(rc);
4004	}
4005	}
4006	}
4007	else
4008	{
4009	rc = SSMR3GetStructEx(pSSM, &pStream->State, sizeof(HDASTREAMSTATE),
4010	0 /* fFlags */, g_aSSMStreamStateFields6, NULL);
4011	if (RT_FAILURE(rc))
4012	break;
4013
4014	/* Get HDABDLEDESC. */
4015	uint32_t uMarker;
4016	rc = SSMR3GetU32(pSSM, &uMarker); /* Begin marker. */
4017	AssertRC(rc);
4018	Assert(uMarker == UINT32_C(0x19200102) /* SSMR3STRUCT_BEGIN */);
4019	rc = SSMR3GetU64(pSSM, &pStream->State.BDLE.Desc.u64BufAdr);
4020	AssertRC(rc);
4021	rc = SSMR3GetU32(pSSM, &pStream->State.BDLE.Desc.u32BufSize);
4022	AssertRC(rc);
4023	bool fFlags = false;
4024	rc = SSMR3GetBool(pSSM, &fFlags); /* Saved states < v7 only stored the IOC as boolean flag. */
4025	AssertRC(rc);
4026	pStream->State.BDLE.Desc.fFlags = fFlags ? HDA_BDLE_FLAG_IOC : 0;
4027	rc = SSMR3GetU32(pSSM, &uMarker); /* End marker. */
4028	AssertRC(rc);
4029	Assert(uMarker == UINT32_C(0x19920406) /* SSMR3STRUCT_END */);
4030
4031	rc = SSMR3GetStructEx(pSSM, &pStream->State.BDLE.State, sizeof(HDABDLESTATE),
4032	0 /* fFlags */, g_aSSMBDLEStateFields6, NULL);
4033	if (RT_FAILURE(rc))
4034	break;
4035
4036	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n",
4037	uStreamID,
4038	HDA_STREAM_REG(pThis, LPIB, uStreamID), HDA_STREAM_REG(pThis, CBL, uStreamID), HDA_STREAM_REG(pThis, LVI, uStreamID)));
4039	#ifdef LOG_ENABLED
4040	hdaR3BDLEDumpAll(pThis, pStream->u64BDLBase, pStream->u16LVI + 1);
4041	#endif
4042	}
4043
4044	} /* for cStreams */
4045	break;
4046	} /* default */
4047	}
4048
4049	return rc;
4050	}
4051
4052	/**
4053	* @callback_method_impl{FNSSMDEVLOADEXEC}
4054	*/
4055	static DECLCALLBACK(int) hdaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4056	{
4057	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4058
4059	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
4060
4061	LogRel2(("hdaR3LoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
4062
4063	/*
4064	* Load Codec nodes states.
4065	*/
4066	int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
4067	if (RT_FAILURE(rc))
4068	{
4069	LogRel(("HDA: Failed loading codec state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
4070	return rc;
4071	}
4072
4073	if (uVersion < HDA_SSM_VERSION) /* Handle older saved states? */
4074	{
4075	rc = hdaR3LoadExecLegacy(pThis, pSSM, uVersion, uPass);
4076	if (RT_SUCCESS(rc))
4077	rc = hdaR3LoadExecPost(pThis);
4078
4079	return rc;
4080	}
4081
4082	/*
4083	* Load MMIO registers.
4084	*/
4085	uint32_t cRegs;
4086	rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
4087	if (cRegs != RT_ELEMENTS(pThis->au32Regs))
4088	LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
4089
4090	if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
4091	{
4092	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
4093	SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
4094	}
4095	else
4096	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
4097
4098	/* Make sure to update the base addresses first before initializing any streams down below. */
4099	pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
4100	pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
4101	pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE) & DPBASE_ADDR_MASK, HDA_REG(pThis, DPUBASE));
4102
4103	/* Also make sure to update the DMA position bit if this was enabled when saving the state. */
4104	pThis->fDMAPosition = RT_BOOL(HDA_REG(pThis, DPLBASE) & RT_BIT_32(0));
4105
4106	/*
4107	* Load controller-specifc internals.
4108	* Don't annoy other team mates (forgot this for state v7).
4109	*/
4110	if ( SSMR3HandleRevision(pSSM) >= 116273
4111	\|\| SSMR3HandleVersion(pSSM) >= VBOX_FULL_VERSION_MAKE(5, 2, 0))
4112	{
4113	rc = SSMR3GetU64(pSSM, &pThis->u64WalClk);
4114	AssertRC(rc);
4115
4116	rc = SSMR3GetU8(pSSM, &pThis->u8IRQL);
4117	AssertRC(rc);
4118	}
4119
4120	/*
4121	* Load streams.
4122	*/
4123	uint32_t cStreams;
4124	rc = SSMR3GetU32(pSSM, &cStreams);
4125	AssertRC(rc);
4126
4127	if (cStreams > HDA_MAX_STREAMS)
4128	cStreams = HDA_MAX_STREAMS; /* Sanity. */
4129
4130	Log2Func(("cStreams=%RU32\n", cStreams));
4131
4132	/* Load stream states. */
4133	for (uint32_t i = 0; i < cStreams; i++)
4134	{
4135	uint8_t uStreamID;
4136	rc = SSMR3GetU8(pSSM, &uStreamID);
4137	AssertRC(rc);
4138
4139	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uStreamID);
4140	HDASTREAM StreamDummy;
4141
4142	if (!pStream)
4143	{
4144	pStream = &StreamDummy;
4145	LogRel2(("HDA: Warning: Loading of stream #%RU8 not supported, skipping to load ...\n", uStreamID));
4146	}
4147
4148	rc = hdaR3StreamInit(pStream, uStreamID);
4149	if (RT_FAILURE(rc))
4150	{
4151	LogRel(("HDA: Stream #%RU8: Loading initialization failed, rc=%Rrc\n", uStreamID, rc));
4152	/* Continue. */
4153	}
4154
4155	rc = SSMR3GetStructEx(pSSM, &pStream->State, sizeof(HDASTREAMSTATE),
4156	0 /* fFlags */, g_aSSMStreamStateFields7,
4157	NULL);
4158	AssertRC(rc);
4159
4160	/*
4161	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
4162	*/
4163	rc = SSMR3GetStructEx(pSSM, &pStream->State.BDLE.Desc, sizeof(HDABDLEDESC),
4164	0 /* fFlags */, g_aSSMBDLEDescFields7, NULL);
4165	AssertRC(rc);
4166
4167	rc = SSMR3GetStructEx(pSSM, &pStream->State.BDLE.State, sizeof(HDABDLESTATE),
4168	0 /* fFlags */, g_aSSMBDLEStateFields7, NULL);
4169	AssertRC(rc);
4170
4171	Log2Func(("[SD%RU8] %R[bdle]\n", pStream->u8SD, &pStream->State.BDLE));
4172
4173	/*
4174	* Load period state.
4175	* Don't annoy other team mates (forgot this for state v7).
4176	*/
4177	hdaR3StreamPeriodInit(&pStream->State.Period,
4178	pStream->u8SD, pStream->u16LVI, pStream->u32CBL, &pStream->State.Cfg);
4179
4180	if ( SSMR3HandleRevision(pSSM) >= 116273
4181	\|\| SSMR3HandleVersion(pSSM) >= VBOX_FULL_VERSION_MAKE(5, 2, 0))
4182	{
4183	rc = SSMR3GetStructEx(pSSM, &pStream->State.Period, sizeof(HDASTREAMPERIOD),
4184	0 /* fFlags */, g_aSSMStreamPeriodFields7, NULL);
4185	AssertRC(rc);
4186	}
4187
4188	/*
4189	* Load internal (FIFO) buffer.
4190	*/
4191	uint32_t cbCircBufSize = 0;
4192	rc = SSMR3GetU32(pSSM, &cbCircBufSize); /* cbCircBuf */
4193	AssertRC(rc);
4194
4195	uint32_t cbCircBufUsed = 0;
4196	rc = SSMR3GetU32(pSSM, &cbCircBufUsed); /* cbCircBuf */
4197	AssertRC(rc);
4198
4199	if (cbCircBufSize) /* If 0, skip the buffer. */
4200	{
4201	/* Paranoia. */
4202	AssertReleaseMsg(cbCircBufSize <= _1M,
4203	("HDA: Saved state contains bogus DMA buffer size (%RU32) for stream #%RU8",
4204	cbCircBufSize, uStreamID));
4205	AssertReleaseMsg(cbCircBufUsed <= cbCircBufSize,
4206	("HDA: Saved state contains invalid DMA buffer usage (%RU32/%RU32) for stream #%RU8",
4207	cbCircBufUsed, cbCircBufSize, uStreamID));
4208	AssertPtr(pStream->State.pCircBuf);
4209
4210	/* Do we need to cre-create the circular buffer do fit the data size? */
4211	if (cbCircBufSize != (uint32_t)RTCircBufSize(pStream->State.pCircBuf))
4212	{
4213	RTCircBufDestroy(pStream->State.pCircBuf);
4214	pStream->State.pCircBuf = NULL;
4215
4216	rc = RTCircBufCreate(&pStream->State.pCircBuf, cbCircBufSize);
4217	AssertRC(rc);
4218	}
4219
4220	if ( RT_SUCCESS(rc)
4221	&& cbCircBufUsed)
4222	{
4223	void *pvBuf;
4224	size_t cbBuf;
4225
4226	RTCircBufAcquireWriteBlock(pStream->State.pCircBuf, cbCircBufUsed, &pvBuf, &cbBuf);
4227
4228	if (cbBuf)
4229	{
4230	rc = SSMR3GetMem(pSSM, pvBuf, cbBuf);
4231	AssertRC(rc);
4232	}
4233
4234	RTCircBufReleaseWriteBlock(pStream->State.pCircBuf, cbBuf);
4235
4236	Assert(cbBuf == cbCircBufUsed);
4237	}
4238	}
4239
4240	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n",
4241	uStreamID,
4242	HDA_STREAM_REG(pThis, LPIB, uStreamID), HDA_STREAM_REG(pThis, CBL, uStreamID), HDA_STREAM_REG(pThis, LVI, uStreamID)));
4243	#ifdef LOG_ENABLED
4244	hdaR3BDLEDumpAll(pThis, pStream->u64BDLBase, pStream->u16LVI + 1);
4245	#endif
4246	/** @todo (Re-)initialize active periods? */
4247
4248	} /* for cStreams */
4249
4250	rc = hdaR3LoadExecPost(pThis);
4251	AssertRC(rc);
4252
4253	LogFlowFuncLeaveRC(rc);
4254	return rc;
4255	}
4256
4257	/* IPRT format type handlers. */
4258
4259	/**
4260	* @callback_method_impl{FNRTSTRFORMATTYPE}
4261	*/
4262	static DECLCALLBACK(size_t) hdaR3StrFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4263	const char pszType, void const pvValue,
4264	int cchWidth, int cchPrecision, unsigned fFlags,
4265	void *pvUser)
4266	{
4267	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4268	PHDABDLE pBDLE = (PHDABDLE)pvValue;
4269	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4270	"BDLE(idx:%RU32, off:%RU32, fifow:%RU32, IOC:%RTbool, DMA[%RU32 bytes @ 0x%x])",
4271	pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW,
4272	pBDLE->Desc.fFlags & HDA_BDLE_FLAG_IOC, pBDLE->Desc.u32BufSize, pBDLE->Desc.u64BufAdr);
4273	}
4274
4275	/**
4276	* @callback_method_impl{FNRTSTRFORMATTYPE}
4277	*/
4278	static DECLCALLBACK(size_t) hdaR3StrFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4279	const char pszType, void const pvValue,
4280	int cchWidth, int cchPrecision, unsigned fFlags,
4281	void *pvUser)
4282	{
4283	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4284	uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
4285	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4286	"SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
4287	uSDCTL,
4288	uSDCTL & HDA_SDCTL_DIR ? "OUT" : "IN",
4289	RT_BOOL(uSDCTL & HDA_SDCTL_TP),
4290	(uSDCTL & HDA_SDCTL_STRIPE_MASK) >> HDA_SDCTL_STRIPE_SHIFT,
4291	RT_BOOL(uSDCTL & HDA_SDCTL_DEIE),
4292	RT_BOOL(uSDCTL & HDA_SDCTL_FEIE),
4293	RT_BOOL(uSDCTL & HDA_SDCTL_IOCE),
4294	RT_BOOL(uSDCTL & HDA_SDCTL_RUN),
4295	RT_BOOL(uSDCTL & HDA_SDCTL_SRST));
4296	}
4297
4298	/**
4299	* @callback_method_impl{FNRTSTRFORMATTYPE}
4300	*/
4301	static DECLCALLBACK(size_t) hdaR3StrFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4302	const char pszType, void const pvValue,
4303	int cchWidth, int cchPrecision, unsigned fFlags,
4304	void *pvUser)
4305	{
4306	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4307	uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
4308	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, uSDFIFOS ? uSDFIFOS + 1 : 0);
4309	}
4310
4311	/**
4312	* @callback_method_impl{FNRTSTRFORMATTYPE}
4313	*/
4314	static DECLCALLBACK(size_t) hdaR3StrFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4315	const char pszType, void const pvValue,
4316	int cchWidth, int cchPrecision, unsigned fFlags,
4317	void *pvUser)
4318	{
4319	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4320	uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
4321	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
4322	}
4323
4324	/**
4325	* @callback_method_impl{FNRTSTRFORMATTYPE}
4326	*/
4327	static DECLCALLBACK(size_t) hdaR3StrFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4328	const char pszType, void const pvValue,
4329	int cchWidth, int cchPrecision, unsigned fFlags,
4330	void *pvUser)
4331	{
4332	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4333	uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
4334	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4335	"SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
4336	uSdSts,
4337	RT_BOOL(uSdSts & HDA_SDSTS_FIFORDY),
4338	RT_BOOL(uSdSts & HDA_SDSTS_DESE),
4339	RT_BOOL(uSdSts & HDA_SDSTS_FIFOE),
4340	RT_BOOL(uSdSts & HDA_SDSTS_BCIS));
4341	}
4342
4343	/* Debug info dumpers */
4344
4345	static int hdaR3DbgLookupRegByName(const char *pszArgs)
4346	{
4347	int iReg = 0;
4348	for (; iReg < HDA_NUM_REGS; ++iReg)
4349	if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
4350	return iReg;
4351	return -1;
4352	}
4353
4354
4355	static void hdaR3DbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
4356	{
4357	Assert( pThis
4358	&& iHdaIndex >= 0
4359	&& iHdaIndex < HDA_NUM_REGS);
4360	pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
4361	}
4362
4363	/**
4364	* @callback_method_impl{FNDBGFHANDLERDEV}
4365	*/
4366	static DECLCALLBACK(void) hdaR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4367	{
4368	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4369	int iHdaRegisterIndex = hdaR3DbgLookupRegByName(pszArgs);
4370	if (iHdaRegisterIndex != -1)
4371	hdaR3DbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
4372	else
4373	{
4374	for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NUM_REGS; ++iHdaRegisterIndex)
4375	hdaR3DbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
4376	}
4377	}
4378
4379	static void hdaR3DbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
4380	{
4381	Assert( pThis
4382	&& iIdx >= 0
4383	&& iIdx < HDA_MAX_STREAMS);
4384
4385	const PHDASTREAM pStream = &pThis->aStreams[iIdx];
4386
4387	pHlp->pfnPrintf(pHlp, "Stream #%d:\n", iIdx);
4388	pHlp->pfnPrintf(pHlp, "\tSD%dCTL : %R[sdctl]\n", iIdx, HDA_STREAM_REG(pThis, CTL, iIdx));
4389	pHlp->pfnPrintf(pHlp, "\tSD%dCTS : %R[sdsts]\n", iIdx, HDA_STREAM_REG(pThis, STS, iIdx));
4390	pHlp->pfnPrintf(pHlp, "\tSD%dFIFOS: %R[sdfifos]\n", iIdx, HDA_STREAM_REG(pThis, FIFOS, iIdx));
4391	pHlp->pfnPrintf(pHlp, "\tSD%dFIFOW: %R[sdfifow]\n", iIdx, HDA_STREAM_REG(pThis, FIFOW, iIdx));
4392	pHlp->pfnPrintf(pHlp, "\tBDLE : %R[bdle]\n", &pStream->State.BDLE);
4393	}
4394
4395	static void hdaR3DbgPrintBDLE(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
4396	{
4397	Assert( pThis
4398	&& iIdx >= 0
4399	&& iIdx < HDA_MAX_STREAMS);
4400
4401	const PHDASTREAM pStream = &pThis->aStreams[iIdx];
4402	const PHDABDLE pBDLE = &pStream->State.BDLE;
4403
4404	pHlp->pfnPrintf(pHlp, "Stream #%d BDLE:\n", iIdx);
4405
4406	uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, iIdx),
4407	HDA_STREAM_REG(pThis, BDPU, iIdx));
4408	uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, iIdx);
4409	uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, iIdx);
4410
4411	if (!u64BaseDMA)
4412	return;
4413
4414	pHlp->pfnPrintf(pHlp, "\tCurrent: %R[bdle]\n\n", pBDLE);
4415
4416	pHlp->pfnPrintf(pHlp, "\tMemory:\n");
4417
4418	uint32_t cbBDLE = 0;
4419	for (uint16_t i = 0; i < u16LVI + 1; i++)
4420	{
4421	HDABDLEDESC bd;
4422	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i * sizeof(HDABDLEDESC), &bd, sizeof(bd));
4423
4424	pHlp->pfnPrintf(pHlp, "\t\t%s #%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
4425	pBDLE->State.u32BDLIndex == i ? "*" : " ", i, bd.u64BufAdr, bd.u32BufSize, bd.fFlags & HDA_BDLE_FLAG_IOC);
4426
4427	cbBDLE += bd.u32BufSize;
4428	}
4429
4430	pHlp->pfnPrintf(pHlp, "Total: %RU32 bytes\n", cbBDLE);
4431
4432	if (cbBDLE != u32CBL)
4433	pHlp->pfnPrintf(pHlp, "Warning: %RU32 bytes does not match CBL (%RU32)!\n", cbBDLE, u32CBL);
4434
4435	pHlp->pfnPrintf(pHlp, "DMA counters (base @ 0x%llx):\n", u64BaseDMA);
4436	if (!u64BaseDMA) /* No DMA base given? Bail out. */
4437	{
4438	pHlp->pfnPrintf(pHlp, "\tNo counters found\n");
4439	return;
4440	}
4441
4442	for (int i = 0; i < u16LVI + 1; i++)
4443	{
4444	uint32_t uDMACnt;
4445	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
4446	&uDMACnt, sizeof(uDMACnt));
4447
4448	pHlp->pfnPrintf(pHlp, "\t#%03d DMA @ 0x%x\n", i , uDMACnt);
4449	}
4450	}
4451
4452	static int hdaR3DbgLookupStrmIdx(PHDASTATE pThis, const char *pszArgs)
4453	{
4454	RT_NOREF(pThis, pszArgs);
4455	/** @todo Add args parsing. */
4456	return -1;
4457	}
4458
4459	/**
4460	* @callback_method_impl{FNDBGFHANDLERDEV}
4461	*/
4462	static DECLCALLBACK(void) hdaR3DbgInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4463	{
4464	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4465	int iHdaStreamdex = hdaR3DbgLookupStrmIdx(pThis, pszArgs);
4466	if (iHdaStreamdex != -1)
4467	hdaR3DbgPrintStream(pThis, pHlp, iHdaStreamdex);
4468	else
4469	for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
4470	hdaR3DbgPrintStream(pThis, pHlp, iHdaStreamdex);
4471	}
4472
4473	/**
4474	* @callback_method_impl{FNDBGFHANDLERDEV}
4475	*/
4476	static DECLCALLBACK(void) hdaR3DbgInfoBDLE(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4477	{
4478	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4479	int iHdaStreamdex = hdaR3DbgLookupStrmIdx(pThis, pszArgs);
4480	if (iHdaStreamdex != -1)
4481	hdaR3DbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
4482	else
4483	for (iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
4484	hdaR3DbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
4485	}
4486
4487	/**
4488	* @callback_method_impl{FNDBGFHANDLERDEV}
4489	*/
4490	static DECLCALLBACK(void) hdaR3DbgInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4491	{
4492	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4493
4494	if (pThis->pCodec->pfnDbgListNodes)
4495	pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
4496	else
4497	pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
4498	}
4499
4500	/**
4501	* @callback_method_impl{FNDBGFHANDLERDEV}
4502	*/
4503	static DECLCALLBACK(void) hdaR3DbgInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4504	{
4505	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4506
4507	if (pThis->pCodec->pfnDbgSelector)
4508	pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
4509	else
4510	pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
4511	}
4512
4513	/**
4514	* @callback_method_impl{FNDBGFHANDLERDEV}
4515	*/
4516	static DECLCALLBACK(void) hdaR3DbgInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4517	{
4518	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4519
4520	if (pThis->pMixer)
4521	AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
4522	else
4523	pHlp->pfnPrintf(pHlp, "Mixer not available\n");
4524	}
4525
4526
4527	/* PDMIBASE */
4528
4529	/**
4530	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
4531	*/
4532	static DECLCALLBACK(void ) hdaR3QueryInterface(struct PDMIBASE pInterface, const char *pszIID)
4533	{
4534	PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
4535	Assert(&pThis->IBase == pInterface);
4536
4537	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
4538	return NULL;
4539	}
4540
4541
4542	/* PDMDEVREG */
4543
4544	/**
4545	* Attach command, internal version.
4546	*
4547	* This is called to let the device attach to a driver for a specified LUN
4548	* during runtime. This is not called during VM construction, the device
4549	* constructor has to attach to all the available drivers.
4550	*
4551	* @returns VBox status code.
4552	* @param pThis HDA state.
4553	* @param uLUN The logical unit which is being detached.
4554	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4555	* @param ppDrv Attached driver instance on success. Optional.
4556	*/
4557	static int hdaR3AttachInternal(PHDASTATE pThis, unsigned uLUN, uint32_t fFlags, PHDADRIVER *ppDrv)
4558	{
4559	RT_NOREF(fFlags);
4560
4561	/*
4562	* Attach driver.
4563	*/
4564	char *pszDesc;
4565	if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
4566	AssertLogRelFailedReturn(VERR_NO_MEMORY);
4567
4568	PPDMIBASE pDrvBase;
4569	int rc = PDMDevHlpDriverAttach(pThis->pDevInsR3, uLUN,
4570	&pThis->IBase, &pDrvBase, pszDesc);
4571	if (RT_SUCCESS(rc))
4572	{
4573	PHDADRIVER pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
4574	if (pDrv)
4575	{
4576	pDrv->pDrvBase = pDrvBase;
4577	pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
4578	AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
4579	pDrv->pHDAState = pThis;
4580	pDrv->uLUN = uLUN;
4581
4582	/*
4583	* For now we always set the driver at LUN 0 as our primary
4584	* host backend. This might change in the future.
4585	*/
4586	if (pDrv->uLUN == 0)
4587	pDrv->fFlags \|= PDMAUDIODRVFLAGS_PRIMARY;
4588
4589	LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->fFlags));
4590
4591	/* Attach to driver list if not attached yet. */
4592	if (!pDrv->fAttached)
4593	{
4594	RTListAppend(&pThis->lstDrv, &pDrv->Node);
4595	pDrv->fAttached = true;
4596	}
4597
4598	if (ppDrv)
4599	*ppDrv = pDrv;
4600	}
4601	else
4602	rc = VERR_NO_MEMORY;
4603	}
4604	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4605	LogFunc(("No attached driver for LUN #%u\n", uLUN));
4606
4607	if (RT_FAILURE(rc))
4608	{
4609	/* Only free this string on failure;
4610	* must remain valid for the live of the driver instance. */
4611	RTStrFree(pszDesc);
4612	}
4613
4614	LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
4615	return rc;
4616	}
4617
4618	/**
4619	* Detach command, internal version.
4620	*
4621	* This is called to let the device detach from a driver for a specified LUN
4622	* during runtime.
4623	*
4624	* @returns VBox status code.
4625	* @param pThis HDA state.
4626	* @param pDrv Driver to detach from device.
4627	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4628	*/
4629	static int hdaR3DetachInternal(PHDASTATE pThis, PHDADRIVER pDrv, uint32_t fFlags)
4630	{
4631	RT_NOREF(fFlags);
4632
4633	/* First, remove the driver from our list and destory it's associated streams.
4634	* This also will un-set the driver as a recording source (if associated). */
4635	hdaR3MixerRemoveDrv(pThis, pDrv);
4636
4637	/* Next, search backwards for a capable (attached) driver which now will be the
4638	* new recording source. */
4639	PHDADRIVER pDrvCur;
4640	RTListForEachReverse(&pThis->lstDrv, pDrvCur, HDADRIVER, Node)
4641	{
4642	if (!pDrvCur->pConnector)
4643	continue;
4644
4645	PDMAUDIOBACKENDCFG Cfg;
4646	int rc2 = pDrvCur->pConnector->pfnGetConfig(pDrvCur->pConnector, &Cfg);
4647	if (RT_FAILURE(rc2))
4648	continue;
4649
4650	PHDADRIVERSTREAM pDrvStrm;
4651	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
4652	pDrvStrm = &pDrvCur->MicIn;
4653	if ( pDrvStrm
4654	&& pDrvStrm->pMixStrm)
4655	{
4656	rc2 = AudioMixerSinkSetRecordingSource(pThis->SinkMicIn.pMixSink, pDrvStrm->pMixStrm);
4657	if (RT_SUCCESS(rc2))
4658	LogRel2(("HDA: Set new recording source for 'Mic In' to '%s'\n", Cfg.szName));
4659	}
4660	# endif
4661	pDrvStrm = &pDrvCur->LineIn;
4662	if ( pDrvStrm
4663	&& pDrvStrm->pMixStrm)
4664	{
4665	rc2 = AudioMixerSinkSetRecordingSource(pThis->SinkLineIn.pMixSink, pDrvStrm->pMixStrm);
4666	if (RT_SUCCESS(rc2))
4667	LogRel2(("HDA: Set new recording source for 'Line In' to '%s'\n", Cfg.szName));
4668	}
4669	}
4670
4671	LogFunc(("uLUN=%u, fFlags=0x%x\n", pDrv->uLUN, fFlags));
4672	return VINF_SUCCESS;
4673	}
4674
4675	/**
4676	* @interface_method_impl{PDMDEVREG,pfnAttach}
4677	*/
4678	static DECLCALLBACK(int) hdaR3Attach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4679	{
4680	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4681
4682	DEVHDA_LOCK_RETURN(pThis, VERR_IGNORED);
4683
4684	LogFunc(("uLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
4685
4686	PHDADRIVER pDrv;
4687	int rc2 = hdaR3AttachInternal(pThis, uLUN, fFlags, &pDrv);
4688	if (RT_SUCCESS(rc2))
4689	rc2 = hdaR3MixerAddDrv(pThis, pDrv);
4690
4691	if (RT_FAILURE(rc2))
4692	LogFunc(("Failed with %Rrc\n", rc2));
4693
4694	DEVHDA_UNLOCK(pThis);
4695
4696	return VINF_SUCCESS;
4697	}
4698
4699	/**
4700	* @interface_method_impl{PDMDEVREG,pfnDetach}
4701	*/
4702	static DECLCALLBACK(void) hdaR3Detach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4703	{
4704	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4705
4706	DEVHDA_LOCK(pThis);
4707
4708	LogFunc(("uLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
4709
4710	PHDADRIVER pDrv, pDrvNext;
4711	RTListForEachSafe(&pThis->lstDrv, pDrv, pDrvNext, HDADRIVER, Node)
4712	{
4713	if (pDrv->uLUN == uLUN)
4714	{
4715	int rc2 = hdaR3DetachInternal(pThis, pDrv, fFlags);
4716	if (RT_SUCCESS(rc2))
4717	{
4718	RTMemFree(pDrv);
4719	pDrv = NULL;
4720	}
4721
4722	break;
4723	}
4724	}
4725
4726	DEVHDA_UNLOCK(pThis);
4727	}
4728
4729	/**
4730	* Powers off the device.
4731	*
4732	* @param pDevIns Device instance to power off.
4733	*/
4734	static DECLCALLBACK(void) hdaR3PowerOff(PPDMDEVINS pDevIns)
4735	{
4736	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4737
4738	DEVHDA_LOCK_RETURN_VOID(pThis);
4739
4740	LogRel2(("HDA: Powering off ...\n"));
4741
4742	/* Ditto goes for the codec, which in turn uses the mixer. */
4743	hdaCodecPowerOff(pThis->pCodec);
4744
4745	/*
4746	* Note: Destroy the mixer while powering off and not in hdaR3Destruct,
4747	* giving the mixer the chance to release any references held to
4748	* PDM audio streams it maintains.
4749	*/
4750	if (pThis->pMixer)
4751	{
4752	AudioMixerDestroy(pThis->pMixer);
4753	pThis->pMixer = NULL;
4754	}
4755
4756	DEVHDA_UNLOCK(pThis);
4757	}
4758
4759
4760	/**
4761	* Re-attaches (replaces) a driver with a new driver.
4762	*
4763	* This is only used by to attach the Null driver when it failed to attach the
4764	* one that was configured.
4765	*
4766	* @returns VBox status code.
4767	* @param pThis Device instance to re-attach driver to.
4768	* @param pDrv Driver instance used for attaching to.
4769	* If NULL is specified, a new driver will be created and appended
4770	* to the driver list.
4771	* @param uLUN The logical unit which is being re-detached.
4772	* @param pszDriver New driver name to attach.
4773	*/
4774	static int hdaR3ReattachInternal(PHDASTATE pThis, PHDADRIVER pDrv, uint8_t uLUN, const char *pszDriver)
4775	{
4776	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
4777	AssertPtrReturn(pszDriver, VERR_INVALID_POINTER);
4778
4779	int rc;
4780
4781	if (pDrv)
4782	{
4783	rc = hdaR3DetachInternal(pThis, pDrv, 0 /* fFlags */);
4784	if (RT_SUCCESS(rc))
4785	rc = PDMDevHlpDriverDetach(pThis->pDevInsR3, PDMIBASE_2_PDMDRV(pDrv->pDrvBase), 0 /* fFlags */);
4786
4787	if (RT_FAILURE(rc))
4788	return rc;
4789
4790	pDrv = NULL;
4791	}
4792
4793	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
4794	PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
4795	PCFGMNODE pDev0 = CFGMR3GetChild(pRoot, "Devices/hda/0/");
4796
4797	/* Remove LUN branch. */
4798	CFGMR3RemoveNode(CFGMR3GetChildF(pDev0, "LUN#%u/", uLUN));
4799
4800	#define RC_CHECK() if (RT_FAILURE(rc)) { AssertReleaseRC(rc); break; }
4801
4802	do
4803	{
4804	PCFGMNODE pLunL0;
4805	rc = CFGMR3InsertNodeF(pDev0, &pLunL0, "LUN#%u/", uLUN); RC_CHECK();
4806	rc = CFGMR3InsertString(pLunL0, "Driver", "AUDIO"); RC_CHECK();
4807	rc = CFGMR3InsertNode(pLunL0, "Config/", NULL); RC_CHECK();
4808
4809	PCFGMNODE pLunL1, pLunL2;
4810	rc = CFGMR3InsertNode (pLunL0, "AttachedDriver/", &pLunL1); RC_CHECK();
4811	rc = CFGMR3InsertNode (pLunL1, "Config/", &pLunL2); RC_CHECK();
4812	rc = CFGMR3InsertString(pLunL1, "Driver", pszDriver); RC_CHECK();
4813
4814	rc = CFGMR3InsertString(pLunL2, "AudioDriver", pszDriver); RC_CHECK();
4815
4816	} while (0);
4817
4818	if (RT_SUCCESS(rc))
4819	rc = hdaR3AttachInternal(pThis, uLUN, 0 /* fFlags /, NULL / ppDrv */);
4820
4821	LogFunc(("pThis=%p, uLUN=%u, pszDriver=%s, rc=%Rrc\n", pThis, uLUN, pszDriver, rc));
4822
4823	#undef RC_CHECK
4824
4825	return rc;
4826	}
4827
4828
4829	/**
4830	* @interface_method_impl{PDMDEVREG,pfnReset}
4831	*/
4832	static DECLCALLBACK(void) hdaR3Reset(PPDMDEVINS pDevIns)
4833	{
4834	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4835
4836	LogFlowFuncEnter();
4837
4838	DEVHDA_LOCK_RETURN_VOID(pThis);
4839
4840	/*
4841	* 18.2.6,7 defines that values of this registers might be cleared on power on/reset
4842	* hdaR3Reset shouldn't affects these registers.
4843	*/
4844	HDA_REG(pThis, WAKEEN) = 0x0;
4845
4846	hdaR3GCTLReset(pThis);
4847
4848	/* Indicate that HDA is not in reset. The firmware is supposed to (un)reset HDA,
4849	* but we can take a shortcut.
4850	*/
4851	HDA_REG(pThis, GCTL) = HDA_GCTL_CRST;
4852
4853	DEVHDA_UNLOCK(pThis);
4854	}
4855
4856
4857	/**
4858	* @interface_method_impl{PDMDEVREG,pfnRelocate}
4859	*/
4860	static DECLCALLBACK(void) hdaR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
4861	{
4862	NOREF(offDelta);
4863	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4864	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4865	}
4866
4867
4868	/**
4869	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4870	*/
4871	static DECLCALLBACK(int) hdaR3Destruct(PPDMDEVINS pDevIns)
4872	{
4873	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns); /* this shall come first */
4874	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4875	DEVHDA_LOCK(pThis); /** @todo r=bird: this will fail on early constructor failure. */
4876
4877	PHDADRIVER pDrv;
4878	while (!RTListIsEmpty(&pThis->lstDrv))
4879	{
4880	pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
4881
4882	RTListNodeRemove(&pDrv->Node);
4883	RTMemFree(pDrv);
4884	}
4885
4886	if (pThis->pCodec)
4887	{
4888	hdaCodecDestruct(pThis->pCodec);
4889
4890	RTMemFree(pThis->pCodec);
4891	pThis->pCodec = NULL;
4892	}
4893
4894	RTMemFree(pThis->pu32CorbBuf);
4895	pThis->pu32CorbBuf = NULL;
4896
4897	RTMemFree(pThis->pu64RirbBuf);
4898	pThis->pu64RirbBuf = NULL;
4899
4900	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
4901	hdaR3StreamDestroy(&pThis->aStreams[i]);
4902
4903	DEVHDA_UNLOCK(pThis);
4904	return VINF_SUCCESS;
4905	}
4906
4907
4908	/**
4909	* @interface_method_impl{PDMDEVREG,pfnConstruct}
4910	*/
4911	static DECLCALLBACK(int) hdaR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4912	{
4913	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); /* this shall come first */
4914	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4915	Assert(iInstance == 0); RT_NOREF(iInstance);
4916
4917	/*
4918	* Initialize the state sufficently to make the destructor work.
4919	*/
4920	pThis->uAlignmentCheckMagic = HDASTATE_ALIGNMENT_CHECK_MAGIC;
4921	RTListInit(&pThis->lstDrv);
4922	/** @todo r=bird: There are probably other things which should be
4923	* initialized here before we start failing. */
4924
4925	/*
4926	* Validations.
4927	*/
4928	if (!CFGMR3AreValuesValid(pCfg, "RZEnabled\0"
4929	"TimerHz\0"
4930	"PosAdjustEnabled\0"
4931	"PosAdjustFrames\0"
4932	"DebugEnabled\0"
4933	"DebugPathOut\0"))
4934	{
4935	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4936	N_ ("Invalid configuration for the Intel HDA device"));
4937	}
4938
4939	int rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pThis->fRZEnabled, true);
4940	if (RT_FAILURE(rc))
4941	return PDMDEV_SET_ERROR(pDevIns, rc,
4942	N_("HDA configuration error: failed to read RCEnabled as boolean"));
4943
4944
4945	rc = CFGMR3QueryU16Def(pCfg, "TimerHz", &pThis->uTimerHz, HDA_TIMER_HZ_DEFAULT /* Default value, if not set. */);
4946	if (RT_FAILURE(rc))
4947	return PDMDEV_SET_ERROR(pDevIns, rc,
4948	N_("HDA configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
4949
4950	if (pThis->uTimerHz != HDA_TIMER_HZ_DEFAULT)
4951	LogRel(("HDA: Using custom device timer rate (%RU16Hz)\n", pThis->uTimerHz));
4952
4953	rc = CFGMR3QueryBoolDef(pCfg, "PosAdjustEnabled", &pThis->fPosAdjustEnabled, true);
4954	if (RT_FAILURE(rc))
4955	return PDMDEV_SET_ERROR(pDevIns, rc,
4956	N_("HDA configuration error: failed to read position adjustment enabled as boolean"));
4957
4958	if (!pThis->fPosAdjustEnabled)
4959	LogRel(("HDA: Position adjustment is disabled\n"));
4960
4961	rc = CFGMR3QueryU16Def(pCfg, "PosAdjustFrames", &pThis->cPosAdjustFrames, HDA_POS_ADJUST_DEFAULT);
4962	if (RT_FAILURE(rc))
4963	return PDMDEV_SET_ERROR(pDevIns, rc,
4964	N_("HDA configuration error: failed to read position adjustment frames as unsigned integer"));
4965
4966	if (pThis->cPosAdjustFrames)
4967	LogRel(("HDA: Using custom position adjustment (%RU16 audio frames)\n", pThis->cPosAdjustFrames));
4968
4969	rc = CFGMR3QueryBoolDef(pCfg, "DebugEnabled", &pThis->Dbg.fEnabled, false);
4970	if (RT_FAILURE(rc))
4971	return PDMDEV_SET_ERROR(pDevIns, rc,
4972	N_("HDA configuration error: failed to read debugging enabled flag as boolean"));
4973
4974	rc = CFGMR3QueryStringDef(pCfg, "DebugPathOut", pThis->Dbg.szOutPath, sizeof(pThis->Dbg.szOutPath),
4975	VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH);
4976	if (RT_FAILURE(rc))
4977	return PDMDEV_SET_ERROR(pDevIns, rc,
4978	N_("HDA configuration error: failed to read debugging output path flag as string"));
4979
4980	if (!strlen(pThis->Dbg.szOutPath))
4981	RTStrPrintf(pThis->Dbg.szOutPath, sizeof(pThis->Dbg.szOutPath), VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH);
4982
4983	if (pThis->Dbg.fEnabled)
4984	LogRel2(("HDA: Debug output will be saved to '%s'\n", pThis->Dbg.szOutPath));
4985
4986	/*
4987	* Use an own critical section for the device instead of the default
4988	* one provided by PDM. This allows fine-grained locking in combination
4989	* with TM when timer-specific stuff is being called in e.g. the MMIO handlers.
4990	*/
4991	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "HDA");
4992	AssertRCReturn(rc, rc);
4993
4994	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4995	AssertRCReturn(rc, rc);
4996
4997	/*
4998	* Initialize data (most of it anyway).
4999	*/
5000	pThis->pDevInsR3 = pDevIns;
5001	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
5002	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5003	/* IBase */
5004	pThis->IBase.pfnQueryInterface = hdaR3QueryInterface;
5005
5006	/* PCI Device */
5007	PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
5008	PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
5009
5010	PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
5011	PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
5012	PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
5013	PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
5014	PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
5015	PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
5016	PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
5017	PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
5018	false /* fIoSpace /, false / fPrefetchable /, true / f64Bit */, 0x00000000);
5019	PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
5020	PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
5021
5022	#if defined(HDA_AS_PCI_EXPRESS)
5023	PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
5024	#elif defined(VBOX_WITH_MSI_DEVICES)
5025	PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
5026	#else
5027	PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
5028	#endif
5029
5030	/// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
5031	/// of these values needs to be properly documented!
5032	/* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
5033	PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
5034
5035	/* Power Management */
5036	PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
5037	PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
5038	PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI \| 0x02 /* version, PM1.1 */ );
5039
5040	#ifdef HDA_AS_PCI_EXPRESS
5041	/* PCI Express */
5042	PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
5043	PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
5044	/* Device flags */
5045	PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
5046	/* version */ 0x1 \|
5047	/* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) \|
5048	/* MSI */ (100) << 9 );
5049	/* Device capabilities */
5050	PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
5051	/* Device control */
5052	PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
5053	/* Device status */
5054	PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
5055	/* Link caps */
5056	PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
5057	/* Link control */
5058	PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
5059	/* Link status */
5060	PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
5061	/* Slot capabilities */
5062	PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
5063	/* Slot control */
5064	PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
5065	/* Slot status */
5066	PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
5067	/* Root control */
5068	PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
5069	/* Root capabilities */
5070	PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
5071	/* Root status */
5072	PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
5073	/* Device capabilities 2 */
5074	PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
5075	/* Device control 2 */
5076	PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
5077	/* Link control 2 */
5078	PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
5079	/* Slot control 2 */
5080	PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
5081	#endif
5082
5083	/*
5084	* Register the PCI device.
5085	*/
5086	rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
5087	if (RT_FAILURE(rc))
5088	return rc;
5089
5090	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaR3PciIoRegionMap);
5091	if (RT_FAILURE(rc))
5092	return rc;
5093
5094	#ifdef VBOX_WITH_MSI_DEVICES
5095	PDMMSIREG MsiReg;
5096	RT_ZERO(MsiReg);
5097	MsiReg.cMsiVectors = 1;
5098	MsiReg.iMsiCapOffset = 0x60;
5099	MsiReg.iMsiNextOffset = 0x50;
5100	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5101	if (RT_FAILURE(rc))
5102	{
5103	/* That's OK, we can work without MSI */
5104	PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
5105	}
5106	#endif
5107
5108	rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaR3SaveExec, hdaR3LoadExec);
5109	if (RT_FAILURE(rc))
5110	return rc;
5111
5112	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
5113	LogRel(("HDA: Asynchronous I/O enabled\n"));
5114	#endif
5115
5116	uint8_t uLUN;
5117	for (uLUN = 0; uLUN < UINT8_MAX; ++uLUN)
5118	{
5119	LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
5120	rc = hdaR3AttachInternal(pThis, uLUN, 0 /* fFlags /, NULL / ppDrv */);
5121	if (RT_FAILURE(rc))
5122	{
5123	if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5124	rc = VINF_SUCCESS;
5125	else if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
5126	{
5127	hdaR3ReattachInternal(pThis, NULL /* pDrv */, uLUN, "NullAudio");
5128	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
5129	N_("Host audio backend initialization has failed. Selecting the NULL audio backend "
5130	"with the consequence that no sound is audible"));
5131	/* Attaching to the NULL audio backend will never fail. */
5132	rc = VINF_SUCCESS;
5133	}
5134	break;
5135	}
5136	}
5137
5138	LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
5139
5140	if (RT_SUCCESS(rc))
5141	{
5142	rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
5143	if (RT_SUCCESS(rc))
5144	{
5145	/*
5146	* Add mixer output sinks.
5147	*/
5148	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
5149	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Front",
5150	AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
5151	AssertRC(rc);
5152	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Center / Subwoofer",
5153	AUDMIXSINKDIR_OUTPUT, &pThis->SinkCenterLFE.pMixSink);
5154	AssertRC(rc);
5155	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Rear",
5156	AUDMIXSINKDIR_OUTPUT, &pThis->SinkRear.pMixSink);
5157	AssertRC(rc);
5158	#else
5159	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] PCM Output",
5160	AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
5161	AssertRC(rc);
5162	#endif
5163	/*
5164	* Add mixer input sinks.
5165	*/
5166	rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Line In",
5167	AUDMIXSINKDIR_INPUT, &pThis->SinkLineIn.pMixSink);
5168	AssertRC(rc);
5169	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5170	rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Microphone In",
5171	AUDMIXSINKDIR_INPUT, &pThis->SinkMicIn.pMixSink);
5172	AssertRC(rc);
5173	#endif
5174	/* There is no master volume control. Set the master to max. */
5175	PDMAUDIOVOLUME vol = { false, 255, 255 };
5176	rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
5177	AssertRC(rc);
5178	}
5179	}
5180
5181	if (RT_SUCCESS(rc))
5182	{
5183	/* Allocate CORB buffer. */
5184	pThis->cbCorbBuf = HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE;
5185	pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
5186	if (pThis->pu32CorbBuf)
5187	{
5188	/* Allocate RIRB buffer. */
5189	pThis->cbRirbBuf = HDA_RIRB_SIZE * HDA_RIRB_ELEMENT_SIZE;
5190	pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
5191	if (pThis->pu64RirbBuf)
5192	{
5193	/* Allocate codec. */
5194	pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
5195	if (!pThis->pCodec)
5196	rc = PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
5197	}
5198	else
5199	rc = PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating RIRB"));
5200	}
5201	else
5202	rc = PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating CORB"));
5203
5204	if (RT_SUCCESS(rc))
5205	{
5206	/* Set codec callbacks to this controller. */
5207	pThis->pCodec->pfnCbMixerAddStream = hdaR3MixerAddStream;
5208	pThis->pCodec->pfnCbMixerRemoveStream = hdaR3MixerRemoveStream;
5209	pThis->pCodec->pfnCbMixerControl = hdaR3MixerControl;
5210	pThis->pCodec->pfnCbMixerSetVolume = hdaR3MixerSetVolume;
5211
5212	pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
5213
5214	/* Construct the codec. */
5215	rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfg);
5216	if (RT_FAILURE(rc))
5217	AssertRCReturn(rc, rc);
5218
5219	/* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
5220	verb F20 should provide device/codec recognition. */
5221	Assert(pThis->pCodec->u16VendorId);
5222	Assert(pThis->pCodec->u16DeviceId);
5223	PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
5224	PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
5225	}
5226	}
5227
5228	if (RT_SUCCESS(rc))
5229	{
5230	/*
5231	* Create all hardware streams.
5232	*/
5233	static const char * const s_apszNames[] =
5234	{
5235	"HDA SD0", "HDA SD1", "HDA SD2", "HDA SD3",
5236	"HDA SD4", "HDA SD5", "HDA SD6", "HDA SD7",
5237	};
5238	AssertCompile(RT_ELEMENTS(s_apszNames) == HDA_MAX_STREAMS);
5239	for (uint8_t i = 0; i < HDA_MAX_STREAMS; ++i)
5240	{
5241	/* Create the emulation timer (per stream).
5242	*
5243	* Note: Use TMCLOCK_VIRTUAL_SYNC here, as the guest's HDA driver
5244	* relies on exact (virtual) DMA timing and uses DMA Position Buffers
5245	* instead of the LPIB registers.
5246	*/
5247	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, hdaR3Timer, &pThis->aStreams[i],
5248	TMTIMER_FLAGS_NO_CRIT_SECT, s_apszNames[i], &pThis->pTimer[i]);
5249	AssertRCReturn(rc, rc);
5250
5251	/* Use our own critcal section for the device timer.
5252	* That way we can control more fine-grained when to lock what. */
5253	rc = TMR3TimerSetCritSect(pThis->pTimer[i], &pThis->CritSect);
5254	AssertRCReturn(rc, rc);
5255
5256	rc = hdaR3StreamCreate(&pThis->aStreams[i], pThis, i /* u8SD */);
5257	AssertRC(rc);
5258	}
5259
5260	#ifdef VBOX_WITH_AUDIO_HDA_ONETIME_INIT
5261	/*
5262	* Initialize the driver chain.
5263	*/
5264	PHDADRIVER pDrv;
5265	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
5266	{
5267	/*
5268	* Only primary drivers are critical for the VM to run. Everything else
5269	* might not worth showing an own error message box in the GUI.
5270	*/
5271	if (!(pDrv->fFlags & PDMAUDIODRVFLAGS_PRIMARY))
5272	continue;
5273
5274	PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
5275	AssertPtr(pCon);
5276
5277	bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
5278	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5279	bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
5280	# endif
5281	bool fValidOut = AudioMixerStreamIsValid(pDrv->Front.pMixStrm);
5282	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
5283	/** @todo Anything to do here? */
5284	# endif
5285
5286	if ( !fValidLineIn
5287	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5288	&& !fValidMicIn
5289	# endif
5290	&& !fValidOut)
5291	{
5292	LogRel(("HDA: Falling back to NULL backend (no sound audible)\n"));
5293
5294	hdaR3Reset(pDevIns);
5295	hdaR3ReattachInternal(pThis, pDrv, pDrv->uLUN, "NullAudio");
5296
5297	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
5298	N_("No audio devices could be opened. Selecting the NULL audio backend "
5299	"with the consequence that no sound is audible"));
5300	}
5301	else
5302	{
5303	bool fWarn = false;
5304
5305	PDMAUDIOBACKENDCFG backendCfg;
5306	int rc2 = pCon->pfnGetConfig(pCon, &backendCfg);
5307	if (RT_SUCCESS(rc2))
5308	{
5309	if (backendCfg.cMaxStreamsIn)
5310	{
5311	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5312	/* If the audio backend supports two or more input streams at once,
5313	* warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
5314	if (backendCfg.cMaxStreamsIn >= 2)
5315	fWarn = !fValidLineIn \|\| !fValidMicIn;
5316	/* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
5317	* not ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
5318	* One of the two simply is not in use then. */
5319	else if (backendCfg.cMaxStreamsIn == 1)
5320	fWarn = !fValidLineIn && !fValidMicIn;
5321	/* Don't warn if our backend is not able of supporting any input streams at all. */
5322	# else /* !VBOX_WITH_AUDIO_HDA_MIC_IN */
5323	/* We only have line-in as input source. */
5324	fWarn = !fValidLineIn;
5325	# endif /* VBOX_WITH_AUDIO_HDA_MIC_IN */
5326	}
5327
5328	if ( !fWarn
5329	&& backendCfg.cMaxStreamsOut)
5330	{
5331	fWarn = !fValidOut;
5332	}
5333	}
5334	else
5335	{
5336	LogRel(("HDA: Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
5337	fWarn = true;
5338	}
5339
5340	if (fWarn)
5341	{
5342	char szMissingStreams[255];
5343	size_t len = 0;
5344	if (!fValidLineIn)
5345	{
5346	LogRel(("HDA: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
5347	len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
5348	}
5349	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5350	if (!fValidMicIn)
5351	{
5352	LogRel(("HDA: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
5353	len += RTStrPrintf(szMissingStreams + len,
5354	sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
5355	}
5356	# endif /* VBOX_WITH_AUDIO_HDA_MIC_IN */
5357	if (!fValidOut)
5358	{
5359	LogRel(("HDA: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
5360	len += RTStrPrintf(szMissingStreams + len,
5361	sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
5362	}
5363
5364	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
5365	N_("Some HDA audio streams (%s) could not be opened. Guest applications generating audio "
5366	"output or depending on audio input may hang. Make sure your host audio device "
5367	"is working properly. Check the logfile for error messages of the audio "
5368	"subsystem"), szMissingStreams);
5369	}
5370	}
5371	}
5372	#endif /* VBOX_WITH_AUDIO_HDA_ONETIME_INIT */
5373	}
5374
5375	if (RT_SUCCESS(rc))
5376	{
5377	hdaR3Reset(pDevIns);
5378
5379	/*
5380	* Debug and string formatter types.
5381	*/
5382	PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaR3DbgInfo);
5383	PDMDevHlpDBGFInfoRegister(pDevIns, "hdabdle", "HDA stream BDLE info. (hdabdle [stream number])", hdaR3DbgInfoBDLE);
5384	PDMDevHlpDBGFInfoRegister(pDevIns, "hdastream", "HDA stream info. (hdastream [stream number])", hdaR3DbgInfoStream);
5385	PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaR3DbgInfoCodecNodes);
5386	PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaR3DbgInfoCodecSelector);
5387	PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaR3DbgInfoMixer);
5388
5389	rc = RTStrFormatTypeRegister("bdle", hdaR3StrFmtBDLE, NULL);
5390	AssertRC(rc);
5391	rc = RTStrFormatTypeRegister("sdctl", hdaR3StrFmtSDCTL, NULL);
5392	AssertRC(rc);
5393	rc = RTStrFormatTypeRegister("sdsts", hdaR3StrFmtSDSTS, NULL);
5394	AssertRC(rc);
5395	rc = RTStrFormatTypeRegister("sdfifos", hdaR3StrFmtSDFIFOS, NULL);
5396	AssertRC(rc);
5397	rc = RTStrFormatTypeRegister("sdfifow", hdaR3StrFmtSDFIFOW, NULL);
5398	AssertRC(rc);
5399
5400	/*
5401	* Some debug assertions.
5402	*/
5403	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
5404	{
5405	struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
5406	struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
5407
5408	/* binary search order. */
5409	AssertReleaseMsg(!pNextReg \|\| pReg->offset + pReg->size <= pNextReg->offset,
5410	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5411	i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
5412
5413	/* alignment. */
5414	AssertReleaseMsg( pReg->size == 1
5415	\|\| (pReg->size == 2 && (pReg->offset & 1) == 0)
5416	\|\| (pReg->size == 3 && (pReg->offset & 3) == 0)
5417	\|\| (pReg->size == 4 && (pReg->offset & 3) == 0),
5418	("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5419
5420	/* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
5421	AssertRelease(((pReg->offset + pReg->size) & 3) == 0 \|\| pNextReg);
5422	if (pReg->offset & 3)
5423	{
5424	struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
5425	AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5426	if (pPrevReg)
5427	AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
5428	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5429	i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
5430	}
5431	#if 0
5432	if ((pReg->offset + pReg->size) & 3)
5433	{
5434	AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5435	if (pNextReg)
5436	AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
5437	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5438	i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
5439	}
5440	#endif
5441	/* The final entry is a full DWORD, no gaps! Allows shortcuts. */
5442	AssertReleaseMsg(pNextReg \|\| ((pReg->offset + pReg->size) & 3) == 0,
5443	("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5444	}
5445	}
5446
5447	# ifdef VBOX_WITH_STATISTICS
5448	if (RT_SUCCESS(rc))
5449	{
5450	/*
5451	* Register statistics.
5452	*/
5453	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaR3Timer.");
5454	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIn, STAMTYPE_PROFILE, "/Devices/HDA/Input", STAMUNIT_TICKS_PER_CALL, "Profiling input.");
5455	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatOut, STAMTYPE_PROFILE, "/Devices/HDA/Output", STAMUNIT_TICKS_PER_CALL, "Profiling output.");
5456	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
5457	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
5458	}
5459	# endif
5460
5461	LogFlowFuncLeaveRC(rc);
5462	return rc;
5463	}
5464
5465	/**
5466	* The device registration structure.
5467	*/
5468	const PDMDEVREG g_DeviceHDA =
5469	{
5470	/* u32Version */
5471	PDM_DEVREG_VERSION,
5472	/* szName */
5473	"hda",
5474	/* szRCMod */
5475	"VBoxDDRC.rc",
5476	/* szR0Mod */
5477	"VBoxDDR0.r0",
5478	/* pszDescription */
5479	"Intel HD Audio Controller",
5480	/* fFlags */
5481	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
5482	/* fClass */
5483	PDM_DEVREG_CLASS_AUDIO,
5484	/* cMaxInstances */
5485	1,
5486	/* cbInstance */
5487	sizeof(HDASTATE),
5488	/* pfnConstruct */
5489	hdaR3Construct,
5490	/* pfnDestruct */
5491	hdaR3Destruct,
5492	/* pfnRelocate */
5493	hdaR3Relocate,
5494	/* pfnMemSetup */
5495	NULL,
5496	/* pfnPowerOn */
5497	NULL,
5498	/* pfnReset */
5499	hdaR3Reset,
5500	/* pfnSuspend */
5501	NULL,
5502	/* pfnResume */
5503	NULL,
5504	/* pfnAttach */
5505	hdaR3Attach,
5506	/* pfnDetach */
5507	hdaR3Detach,
5508	/* pfnQueryInterface. */
5509	NULL,
5510	/* pfnInitComplete */
5511	NULL,
5512	/* pfnPowerOff */
5513	hdaR3PowerOff,
5514	/* pfnSoftReset */
5515	NULL,
5516	/* u32VersionEnd */
5517	PDM_DEVREG_VERSION
5518	};
5519
5520	#endif /* IN_RING3 */
5521	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5522

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source: vbox/trunk/src/VBox/Devices/Audio/DevHDA.cpp@ 75864

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