DevHDA.cpp@ 75980

Last change on this file since 75980 was 75980, checked in by vboxsync, 6 years ago
Audio/HDA: Optimized stream creation / startup time a lot by re-using the existing mixer / driver chain if the stream's hardware parameters did not change. No need to completely remove and add the same stream again, going through all the PDM interfaces, LUNs and backends.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 196.3 KB

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1	/* $Id: DevHDA.cpp 75980 2018-12-05 15:56:13Z vboxsync $ */
2	/** @file
3	* DevHDA.cpp - VBox Intel HD Audio Controller.
4	*
5	* Implemented against the specifications found in "High Definition Audio
6	* Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7	* HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8	*/
9
10	/*
11	* Copyright (C) 2006-2018 Oracle Corporation
12	*
13	* This file is part of VirtualBox Open Source Edition (OSE), as
14	* available from http://www.virtualbox.org. This file is free software;
15	* you can redistribute it and/or modify it under the terms of the GNU
16	* General Public License (GPL) as published by the Free Software
17	* Foundation, in version 2 as it comes in the "COPYING" file of the
18	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20	*/
21
22
23	/*********************************************************************************************************************************
24	* Header Files *
25	*********************************************************************************************************************************/
26	#ifdef DEBUG_bird
27	# define RT_NO_STRICT /* I'm tried of this crap asserting on save and restore of Maverics guests. */
28	#endif
29	#define LOG_GROUP LOG_GROUP_DEV_HDA
30	#include <VBox/log.h>
31
32	#include <VBox/vmm/pdmdev.h>
33	#include <VBox/vmm/pdmaudioifs.h>
34	#include <VBox/version.h>
35	#include <VBox/AssertGuest.h>
36
37	#include <iprt/assert.h>
38	#include <iprt/asm.h>
39	#include <iprt/asm-math.h>
40	#include <iprt/file.h>
41	#include <iprt/list.h>
42	#ifdef IN_RING3
43	# include <iprt/mem.h>
44	# include <iprt/semaphore.h>
45	# include <iprt/string.h>
46	# include <iprt/uuid.h>
47	#endif
48
49	#include "VBoxDD.h"
50
51	#include "AudioMixBuffer.h"
52	#include "AudioMixer.h"
53
54	#include "DevHDA.h"
55	#include "DevHDACommon.h"
56
57	#include "HDACodec.h"
58	#include "HDAStream.h"
59	#include "HDAStreamMap.h"
60	#include "HDAStreamPeriod.h"
61
62	#include "DrvAudio.h"
63
64
65	/*********************************************************************************************************************************
66	* Defined Constants And Macros *
67	*********************************************************************************************************************************/
68	//#define HDA_AS_PCI_EXPRESS
69
70	/* Installs a DMA access handler (via PGM callback) to monitor
71	* HDA's DMA operations, that is, writing / reading audio stream data.
72	*
73	* !!! Note: Certain guests are that timing sensitive that when enabling !!!
74	* !!! such a handler will mess up audio completely (e.g. Windows 7). !!! */
75	//#define HDA_USE_DMA_ACCESS_HANDLER
76	#ifdef HDA_USE_DMA_ACCESS_HANDLER
77	# include <VBox/vmm/pgm.h>
78	#endif
79
80	/* Uses the DMA access handler to read the written DMA audio (output) data.
81	* Only valid if HDA_USE_DMA_ACCESS_HANDLER is set.
82	*
83	* Also see the note / warning for HDA_USE_DMA_ACCESS_HANDLER. */
84	//# define HDA_USE_DMA_ACCESS_HANDLER_WRITING
85
86	/* Useful to debug the device' timing. */
87	//#define HDA_DEBUG_TIMING
88
89	/* To debug silence coming from the guest in form of audio gaps.
90	* Very crude implementation for now. */
91	//#define HDA_DEBUG_SILENCE
92
93	#if defined(VBOX_WITH_HP_HDA)
94	/* HP Pavilion dv4t-1300 */
95	# define HDA_PCI_VENDOR_ID 0x103c
96	# define HDA_PCI_DEVICE_ID 0x30f7
97	#elif defined(VBOX_WITH_INTEL_HDA)
98	/* Intel HDA controller */
99	# define HDA_PCI_VENDOR_ID 0x8086
100	# define HDA_PCI_DEVICE_ID 0x2668
101	#elif defined(VBOX_WITH_NVIDIA_HDA)
102	/* nVidia HDA controller */
103	# define HDA_PCI_VENDOR_ID 0x10de
104	# define HDA_PCI_DEVICE_ID 0x0ac0
105	#else
106	# error "Please specify your HDA device vendor/device IDs"
107	#endif
108
109	/**
110	* Acquires the HDA lock.
111	*/
112	#define DEVHDA_LOCK(a_pThis) \
113	do { \
114	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
115	AssertRC(rcLock); \
116	} while (0)
117
118	/**
119	* Acquires the HDA lock or returns.
120	*/
121	# define DEVHDA_LOCK_RETURN(a_pThis, a_rcBusy) \
122	do { \
123	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, a_rcBusy); \
124	if (rcLock != VINF_SUCCESS) \
125	{ \
126	AssertRC(rcLock); \
127	return rcLock; \
128	} \
129	} while (0)
130
131	/**
132	* Acquires the HDA lock or returns.
133	*/
134	# define DEVHDA_LOCK_RETURN_VOID(a_pThis) \
135	do { \
136	int rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
137	if (rcLock != VINF_SUCCESS) \
138	{ \
139	AssertRC(rcLock); \
140	return; \
141	} \
142	} while (0)
143
144	/**
145	* Releases the HDA lock.
146	*/
147	#define DEVHDA_UNLOCK(a_pThis) \
148	do { PDMCritSectLeave(&(a_pThis)->CritSect); } while (0)
149
150	/**
151	* Acquires the TM lock and HDA lock, returns on failure.
152	*/
153	#define DEVHDA_LOCK_BOTH_RETURN_VOID(a_pThis, a_SD) \
154	do { \
155	int rcLock = TMTimerLock((a_pThis)->pTimer[a_SD], VERR_IGNORED); \
156	if (rcLock != VINF_SUCCESS) \
157	{ \
158	AssertRC(rcLock); \
159	return; \
160	} \
161	rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, VERR_IGNORED); \
162	if (rcLock != VINF_SUCCESS) \
163	{ \
164	AssertRC(rcLock); \
165	TMTimerUnlock((a_pThis)->pTimer[a_SD]); \
166	return; \
167	} \
168	} while (0)
169
170	/**
171	* Acquires the TM lock and HDA lock, returns on failure.
172	*/
173	#define DEVHDA_LOCK_BOTH_RETURN(a_pThis, a_SD, a_rcBusy) \
174	do { \
175	int rcLock = TMTimerLock((a_pThis)->pTimer[a_SD], (a_rcBusy)); \
176	if (rcLock != VINF_SUCCESS) \
177	return rcLock; \
178	rcLock = PDMCritSectEnter(&(a_pThis)->CritSect, (a_rcBusy)); \
179	if (rcLock != VINF_SUCCESS) \
180	{ \
181	AssertRC(rcLock); \
182	TMTimerUnlock((a_pThis)->pTimer[a_SD]); \
183	return rcLock; \
184	} \
185	} while (0)
186
187	/**
188	* Releases the HDA lock and TM lock.
189	*/
190	#define DEVHDA_UNLOCK_BOTH(a_pThis, a_SD) \
191	do { \
192	PDMCritSectLeave(&(a_pThis)->CritSect); \
193	TMTimerUnlock((a_pThis)->pTimer[a_SD]); \
194	} while (0)
195
196
197	/*********************************************************************************************************************************
198	* Structures and Typedefs *
199	*********************************************************************************************************************************/
200
201	/**
202	* Structure defining a (host backend) driver stream.
203	* Each driver has its own instances of audio mixer streams, which then
204	* can go into the same (or even different) audio mixer sinks.
205	*/
206	typedef struct HDADRIVERSTREAM
207	{
208	/** Associated mixer handle. */
209	R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
210	} HDADRIVERSTREAM, *PHDADRIVERSTREAM;
211
212	#ifdef HDA_USE_DMA_ACCESS_HANDLER
213	/**
214	* Struct for keeping an HDA DMA access handler context.
215	*/
216	typedef struct HDADMAACCESSHANDLER
217	{
218	/** Node for storing this handler in our list in HDASTREAMSTATE. */
219	RTLISTNODER3 Node;
220	/** Pointer to stream to which this access handler is assigned to. */
221	R3PTRTYPE(PHDASTREAM) pStream;
222	/** Access handler type handle. */
223	PGMPHYSHANDLERTYPE hAccessHandlerType;
224	/** First address this handler uses. */
225	RTGCPHYS GCPhysFirst;
226	/** Last address this handler uses. */
227	RTGCPHYS GCPhysLast;
228	/** Actual BDLE address to handle. */
229	RTGCPHYS BDLEAddr;
230	/** Actual BDLE buffer size to handle. */
231	RTGCPHYS BDLESize;
232	/** Whether the access handler has been registered or not. */
233	bool fRegistered;
234	uint8_t Padding[3];
235	} HDADMAACCESSHANDLER, *PHDADMAACCESSHANDLER;
236	#endif
237
238	/**
239	* Struct for maintaining a host backend driver.
240	* This driver must be associated to one, and only one,
241	* HDA codec. The HDA controller does the actual multiplexing
242	* of HDA codec data to various host backend drivers then.
243	*
244	* This HDA device uses a timer in order to synchronize all
245	* read/write accesses across all attached LUNs / backends.
246	*/
247	typedef struct HDADRIVER
248	{
249	/** Node for storing this driver in our device driver list of HDASTATE. */
250	RTLISTNODER3 Node;
251	/** Pointer to HDA controller (state). */
252	R3PTRTYPE(PHDASTATE) pHDAState;
253	/** Driver flags. */
254	PDMAUDIODRVFLAGS fFlags;
255	uint8_t u32Padding0[2];
256	/** LUN to which this driver has been assigned. */
257	uint8_t uLUN;
258	/** Whether this driver is in an attached state or not. */
259	bool fAttached;
260	/** Pointer to attached driver base interface. */
261	R3PTRTYPE(PPDMIBASE) pDrvBase;
262	/** Audio connector interface to the underlying host backend. */
263	R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
264	/** Mixer stream for line input. */
265	HDADRIVERSTREAM LineIn;
266	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
267	/** Mixer stream for mic input. */
268	HDADRIVERSTREAM MicIn;
269	#endif
270	/** Mixer stream for front output. */
271	HDADRIVERSTREAM Front;
272	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
273	/** Mixer stream for center/LFE output. */
274	HDADRIVERSTREAM CenterLFE;
275	/** Mixer stream for rear output. */
276	HDADRIVERSTREAM Rear;
277	#endif
278	} HDADRIVER;
279
280
281	/*********************************************************************************************************************************
282	* Internal Functions *
283	*********************************************************************************************************************************/
284	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
285	#ifdef IN_RING3
286	static void hdaR3GCTLReset(PHDASTATE pThis);
287	#endif
288
289	/** @name Register read/write stubs.
290	* @{
291	*/
292	static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
293	static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
294	/** @} */
295
296	/** @name Global register set read/write functions.
297	* @{
298	*/
299	static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
300	static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
301	static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
302	static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
303	static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
304	static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
305	static int hdaRegWriteCORBSIZE(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
306	static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
307	static int hdaRegWriteRINTCNT(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
308	static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
309	static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
310	static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
311	static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
312	static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
313	static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
314	/** @} */
315
316	/** @name {IOB}SDn write functions.
317	* @{
318	*/
319	static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
320	static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
321	static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
322	static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
323	static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
324	static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
325	static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
326	static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
327	static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
328	/** @} */
329
330	/** @name Generic register read/write functions.
331	* @{
332	*/
333	static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
334	static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
335	static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
336	#ifdef IN_RING3
337	static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
338	#endif
339	static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
340	static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
341	static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
342	static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
343	/** @} */
344
345	/** @name HDA device functions.
346	* @{
347	*/
348	#ifdef IN_RING3
349	static int hdaR3AddStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg);
350	static int hdaR3RemoveStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg);
351	# ifdef HDA_USE_DMA_ACCESS_HANDLER
352	static DECLCALLBACK(VBOXSTRICTRC) hdaR3DMAAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys,
353	void *pvBuf, size_t cbBuf,
354	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser);
355	# endif
356	#endif /* IN_RING3 */
357	/** @} */
358
359	/** @name HDA mixer functions.
360	* @{
361	*/
362	#ifdef IN_RING3
363	static int hdaR3MixerAddDrvStream(PHDASTATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg, PHDADRIVER pDrv);
364	#endif
365	/** @} */
366
367
368	/*********************************************************************************************************************************
369	* Global Variables *
370	*********************************************************************************************************************************/
371
372	/** No register description (RD) flags defined. */
373	#define HDA_RD_FLAG_NONE 0
374	/** Writes to SD are allowed while RUN bit is set. */
375	#define HDA_RD_FLAG_SD_WRITE_RUN RT_BIT(0)
376
377	/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
378	#define HDA_REG_MAP_STRM(offset, name) \
379	/* offset size read mask write mask flags read callback write callback index + abbrev description */ \
380	/* ------- ------- ---------- ---------- ------------------------- -------------- ----------------- ----------------------------- ----------- */ \
381	/* Offset 0x80 (SD0) */ \
382	{ offset, 0x00003, 0x00FF001F, 0x00F0001F, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL) , #name " Stream Descriptor Control" }, \
383	/* Offset 0x83 (SD0) */ \
384	{ offset + 0x3, 0x00001, 0x0000003C, 0x0000001C, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU8 , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS) , #name " Status" }, \
385	/* Offset 0x84 (SD0) */ \
386	{ offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadLPIB, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
387	/* Offset 0x88 (SD0) */ \
388	{ offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDCBL , HDA_REG_IDX_STRM(name, CBL) , #name " Cyclic Buffer Length" }, \
389	/* Offset 0x8C (SD0) */ \
390	{ offset + 0xC, 0x00002, 0x0000FFFF, 0x0000FFFF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDLVI , HDA_REG_IDX_STRM(name, LVI) , #name " Last Valid Index" }, \
391	/* Reserved: FIFO Watermark. ** @todo Document this! */ \
392	{ offset + 0xE, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
393	/* Offset 0x90 (SD0) */ \
394	{ offset + 0x10, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
395	/* Offset 0x92 (SD0) */ \
396	{ offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFMT , HDA_REG_IDX_STRM(name, FMT) , #name " Stream Format" }, \
397	/* Reserved: 0x94 - 0x98. */ \
398	/* Offset 0x98 (SD0) */ \
399	{ offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
400	/* Offset 0x9C (SD0) */ \
401	{ offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
402
403	/** Defines a single audio stream register set (e.g. OSD0). */
404	#define HDA_REG_MAP_DEF_STREAM(index, name) \
405	HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
406
407	/* See 302349 p 6.2. */
408	const HDAREGDESC g_aHdaRegMap[HDA_NUM_REGS] =
409	{
410	/* offset size read mask write mask flags read callback write callback index + abbrev */
411	/------- ------- ---------- ---------- ----------------- ---------------- ------------------- ------------------------ /
412	{ 0x00000, 0x00002, 0x0000FFFB, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(GCAP) }, /* Global Capabilities */
413	{ 0x00002, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMIN) }, /* Minor Version */
414	{ 0x00003, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMAJ) }, /* Major Version */
415	{ 0x00004, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTPAY) }, /* Output Payload Capabilities */
416	{ 0x00006, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INPAY) }, /* Input Payload Capabilities */
417	{ 0x00008, 0x00004, 0x00000103, 0x00000103, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteGCTL , HDA_REG_IDX(GCTL) }, /* Global Control */
418	{ 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(WAKEEN) }, /* Wake Enable */
419	{ 0x0000e, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteSTATESTS, HDA_REG_IDX(STATESTS) }, /* State Change Status */
420	{ 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadUnimpl, hdaRegWriteUnimpl , HDA_REG_IDX(GSTS) }, /* Global Status */
421	{ 0x00018, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTSTRMPAY) }, /* Output Stream Payload Capability */
422	{ 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INSTRMPAY) }, /* Input Stream Payload Capability */
423	{ 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */
424	{ 0x00024, 0x00004, 0xC00000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */
425	{ 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadWALCLK, hdaRegWriteUnimpl , HDA_REG_IDX_NOMEM(WALCLK) }, /* Wall Clock Counter */
426	{ 0x00034, 0x00004, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */
427	{ 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
428	{ 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBUBASE) }, /* CORB Upper Base Address */
429	{ 0x00048, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteCORBWP , HDA_REG_IDX(CORBWP) }, /* CORB Write Pointer */
430	{ 0x0004A, 0x00002, 0x000080FF, 0x00008000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteCORBRP , HDA_REG_IDX(CORBRP) }, /* CORB Read Pointer */
431	{ 0x0004C, 0x00001, 0x00000003, 0x00000003, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL) }, /* CORB Control */
432	{ 0x0004D, 0x00001, 0x00000001, 0x00000001, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS) }, /* CORB Status */
433	{ 0x0004E, 0x00001, 0x000000F3, 0x00000003, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBSIZE, HDA_REG_IDX(CORBSIZE) }, /* CORB Size */
434	{ 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBLBASE) }, /* RIRB Lower Base Address */
435	{ 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBUBASE) }, /* RIRB Upper Base Address */
436	{ 0x00058, 0x00002, 0x000000FF, 0x00008000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteRIRBWP , HDA_REG_IDX(RIRBWP) }, /* RIRB Write Pointer */
437	{ 0x0005A, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteRINTCNT , HDA_REG_IDX(RINTCNT) }, /* Response Interrupt Count */
438	{ 0x0005C, 0x00001, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteU8 , HDA_REG_IDX(RIRBCTL) }, /* RIRB Control */
439	{ 0x0005D, 0x00001, 0x00000005, 0x00000005, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS) }, /* RIRB Status */
440	{ 0x0005E, 0x00001, 0x000000F3, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(RIRBSIZE) }, /* RIRB Size */
441	{ 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(IC) }, /* Immediate Command */
442	{ 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(IR) }, /* Immediate Response */
443	{ 0x00068, 0x00002, 0x00000002, 0x00000002, HDA_RD_FLAG_NONE, hdaRegReadIRS , hdaRegWriteIRS , HDA_REG_IDX(IRS) }, /* Immediate Command Status */
444	{ 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPLBASE) }, /* DMA Position Lower Base */
445	{ 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPUBASE) }, /* DMA Position Upper Base */
446	/* 4 Serial Data In (SDI). */
447	HDA_REG_MAP_DEF_STREAM(0, SD0),
448	HDA_REG_MAP_DEF_STREAM(1, SD1),
449	HDA_REG_MAP_DEF_STREAM(2, SD2),
450	HDA_REG_MAP_DEF_STREAM(3, SD3),
451	/* 4 Serial Data Out (SDO). */
452	HDA_REG_MAP_DEF_STREAM(4, SD4),
453	HDA_REG_MAP_DEF_STREAM(5, SD5),
454	HDA_REG_MAP_DEF_STREAM(6, SD6),
455	HDA_REG_MAP_DEF_STREAM(7, SD7)
456	};
457
458	const HDAREGALIAS g_aHdaRegAliases[] =
459	{
460	{ 0x2084, HDA_REG_SD0LPIB },
461	{ 0x20a4, HDA_REG_SD1LPIB },
462	{ 0x20c4, HDA_REG_SD2LPIB },
463	{ 0x20e4, HDA_REG_SD3LPIB },
464	{ 0x2104, HDA_REG_SD4LPIB },
465	{ 0x2124, HDA_REG_SD5LPIB },
466	{ 0x2144, HDA_REG_SD6LPIB },
467	{ 0x2164, HDA_REG_SD7LPIB }
468	};
469
470	#ifdef IN_RING3
471
472	/** HDABDLEDESC field descriptors for the v7 saved state. */
473	static SSMFIELD const g_aSSMBDLEDescFields7[] =
474	{
475	SSMFIELD_ENTRY(HDABDLEDESC, u64BufAddr),
476	SSMFIELD_ENTRY(HDABDLEDESC, u32BufSize),
477	SSMFIELD_ENTRY(HDABDLEDESC, fFlags),
478	SSMFIELD_ENTRY_TERM()
479	};
480
481	/** HDABDLESTATE field descriptors for the v6+ saved state. */
482	static SSMFIELD const g_aSSMBDLEStateFields6[] =
483	{
484	SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
485	SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
486	SSMFIELD_ENTRY_OLD(FIFO, HDA_FIFO_MAX), /* Deprecated; now is handled in the stream's circular buffer. */
487	SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
488	SSMFIELD_ENTRY_TERM()
489	};
490
491	/** HDABDLESTATE field descriptors for the v7 saved state. */
492	static SSMFIELD const g_aSSMBDLEStateFields7[] =
493	{
494	SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
495	SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
496	SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
497	SSMFIELD_ENTRY_TERM()
498	};
499
500	/** HDASTREAMSTATE field descriptors for the v6 saved state. */
501	static SSMFIELD const g_aSSMStreamStateFields6[] =
502	{
503	SSMFIELD_ENTRY_OLD(cBDLE, sizeof(uint16_t)), /* Deprecated. */
504	SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
505	SSMFIELD_ENTRY_OLD(fStop, 1), /* Deprecated; see SSMR3PutBool(). */
506	SSMFIELD_ENTRY_OLD(fRunning, 1), /* Deprecated; using the HDA_SDCTL_RUN bit is sufficient. */
507	SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
508	SSMFIELD_ENTRY_TERM()
509	};
510
511	/** HDASTREAMSTATE field descriptors for the v7 saved state. */
512	static SSMFIELD const g_aSSMStreamStateFields7[] =
513	{
514	SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
515	SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
516	SSMFIELD_ENTRY(HDASTREAMSTATE, tsTransferNext),
517	SSMFIELD_ENTRY_TERM()
518	};
519
520	/** HDASTREAMPERIOD field descriptors for the v7 saved state. */
521	static SSMFIELD const g_aSSMStreamPeriodFields7[] =
522	{
523	SSMFIELD_ENTRY(HDASTREAMPERIOD, u64StartWalClk),
524	SSMFIELD_ENTRY(HDASTREAMPERIOD, u64ElapsedWalClk),
525	SSMFIELD_ENTRY(HDASTREAMPERIOD, framesTransferred),
526	SSMFIELD_ENTRY(HDASTREAMPERIOD, cIntPending),
527	SSMFIELD_ENTRY_TERM()
528	};
529
530	/**
531	* 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
532	*/
533	static uint32_t const g_afMasks[5] =
534	{
535	UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
536	};
537
538	#endif /* IN_RING3 */
539
540
541
542	/**
543	* Retrieves the number of bytes of a FIFOW register.
544	*
545	* @return Number of bytes of a given FIFOW register.
546	*/
547	DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
548	{
549	uint32_t cb;
550	switch (u32RegFIFOW)
551	{
552	case HDA_SDFIFOW_8B: cb = 8; break;
553	case HDA_SDFIFOW_16B: cb = 16; break;
554	case HDA_SDFIFOW_32B: cb = 32; break;
555	default: cb = 0; break;
556	}
557
558	Assert(RT_IS_POWER_OF_TWO(cb));
559	return cb;
560	}
561
562	#ifdef IN_RING3
563	/**
564	* Reschedules pending interrupts for all audio streams which have complete
565	* audio periods but did not have the chance to issue their (pending) interrupts yet.
566	*
567	* @param pThis The HDA device state.
568	*/
569	static void hdaR3ReschedulePendingInterrupts(PHDASTATE pThis)
570	{
571	bool fInterrupt = false;
572
573	for (uint8_t i = 0; i < HDA_MAX_STREAMS; ++i)
574	{
575	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, i);
576	if (!pStream)
577	continue;
578
579	if ( hdaR3StreamPeriodIsComplete (&pStream->State.Period)
580	&& hdaR3StreamPeriodNeedsInterrupt(&pStream->State.Period)
581	&& hdaR3WalClkSet(pThis, hdaR3StreamPeriodGetAbsElapsedWalClk(&pStream->State.Period), false /* fForce */))
582	{
583	fInterrupt = true;
584	break;
585	}
586	}
587
588	LogFunc(("fInterrupt=%RTbool\n", fInterrupt));
589
590	# ifndef LOG_ENABLED
591	hdaProcessInterrupt(pThis);
592	# else
593	hdaProcessInterrupt(pThis, __FUNCTION__);
594	# endif
595	}
596	#endif /* IN_RING3 */
597
598	/**
599	* Looks up a register at the exact offset given by @a offReg.
600	*
601	* @returns Register index on success, -1 if not found.
602	* @param offReg The register offset.
603	*/
604	static int hdaRegLookup(uint32_t offReg)
605	{
606	/*
607	* Aliases.
608	*/
609	if (offReg >= g_aHdaRegAliases[0].offReg)
610	{
611	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
612	if (offReg == g_aHdaRegAliases[i].offReg)
613	return g_aHdaRegAliases[i].idxAlias;
614	Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
615	return -1;
616	}
617
618	/*
619	* Binary search the
620	*/
621	int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
622	int idxLow = 0;
623	for (;;)
624	{
625	int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
626	if (offReg < g_aHdaRegMap[idxMiddle].offset)
627	{
628	if (idxLow == idxMiddle)
629	break;
630	idxEnd = idxMiddle;
631	}
632	else if (offReg > g_aHdaRegMap[idxMiddle].offset)
633	{
634	idxLow = idxMiddle + 1;
635	if (idxLow >= idxEnd)
636	break;
637	}
638	else
639	return idxMiddle;
640	}
641
642	#ifdef RT_STRICT
643	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
644	Assert(g_aHdaRegMap[i].offset != offReg);
645	#endif
646	return -1;
647	}
648
649	#ifdef IN_RING3
650
651	/**
652	* Looks up a register covering the offset given by @a offReg.
653	*
654	* @returns Register index on success, -1 if not found.
655	* @param offReg The register offset.
656	*/
657	static int hdaR3RegLookupWithin(uint32_t offReg)
658	{
659	/*
660	* Aliases.
661	*/
662	if (offReg >= g_aHdaRegAliases[0].offReg)
663	{
664	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
665	{
666	uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
667	if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
668	return g_aHdaRegAliases[i].idxAlias;
669	}
670	Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
671	return -1;
672	}
673
674	/*
675	* Binary search the register map.
676	*/
677	int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
678	int idxLow = 0;
679	for (;;)
680	{
681	int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
682	if (offReg < g_aHdaRegMap[idxMiddle].offset)
683	{
684	if (idxLow == idxMiddle)
685	break;
686	idxEnd = idxMiddle;
687	}
688	else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
689	{
690	idxLow = idxMiddle + 1;
691	if (idxLow >= idxEnd)
692	break;
693	}
694	else
695	return idxMiddle;
696	}
697
698	# ifdef RT_STRICT
699	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
700	Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
701	# endif
702	return -1;
703	}
704
705
706	/**
707	* Synchronizes the CORB / RIRB buffers between internal <-> device state.
708	*
709	* @returns IPRT status code.
710	* @param pThis HDA state.
711	* @param fLocal Specify true to synchronize HDA state's CORB buffer with the device state,
712	* or false to synchronize the device state's RIRB buffer with the HDA state.
713	*
714	* @todo r=andy Break this up into two functions?
715	*/
716	static int hdaR3CmdSync(PHDASTATE pThis, bool fLocal)
717	{
718	int rc = VINF_SUCCESS;
719	if (fLocal)
720	{
721	if (pThis->u64CORBBase)
722	{
723	AssertPtr(pThis->pu32CorbBuf);
724	Assert(pThis->cbCorbBuf);
725
726	/** @todo r=bird: An explanation is required why PDMDevHlpPhysRead is used with
727	* the CORB and PDMDevHlpPCIPhysWrite with RIRB below. There are
728	* similar unexplained inconsistencies in DevHDACommon.cpp. */
729	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
730	Log(("hdaR3CmdSync/CORB: read %RGp LB %#x (%Rrc)\n", pThis->u64CORBBase, pThis->cbCorbBuf, rc));
731	AssertRCReturn(rc, rc);
732	}
733	}
734	else
735	{
736	if (pThis->u64RIRBBase)
737	{
738	AssertPtr(pThis->pu64RirbBuf);
739	Assert(pThis->cbRirbBuf);
740
741	rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
742	Log(("hdaR3CmdSync/RIRB: phys read %RGp LB %#x (%Rrc)\n", pThis->u64RIRBBase, pThis->pu64RirbBuf, rc));
743	AssertRCReturn(rc, rc);
744	}
745	}
746
747	# ifdef DEBUG_CMD_BUFFER
748	LogFunc(("fLocal=%RTbool\n", fLocal));
749
750	uint8_t i = 0;
751	do
752	{
753	LogFunc(("CORB%02x: ", i));
754	uint8_t j = 0;
755	do
756	{
757	const char *pszPrefix;
758	if ((i + j) == HDA_REG(pThis, CORBRP))
759	pszPrefix = "[R]";
760	else if ((i + j) == HDA_REG(pThis, CORBWP))
761	pszPrefix = "[W]";
762	else
763	pszPrefix = " "; /* three spaces */
764	Log((" %s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
765	j++;
766	} while (j < 8);
767	Log(("\n"));
768	i += 8;
769	} while(i != 0);
770
771	do
772	{
773	LogFunc(("RIRB%02x: ", i));
774	uint8_t j = 0;
775	do
776	{
777	const char *prefix;
778	if ((i + j) == HDA_REG(pThis, RIRBWP))
779	prefix = "[W]";
780	else
781	prefix = " ";
782	Log((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
783	} while (++j < 8);
784	Log(("\n"));
785	i += 8;
786	} while (i != 0);
787	# endif
788	return rc;
789	}
790
791	/**
792	* Processes the next CORB buffer command in the queue.
793	*
794	* This will invoke the HDA codec verb dispatcher.
795	*
796	* @returns IPRT status code.
797	* @param pThis HDA state.
798	*/
799	static int hdaR3CORBCmdProcess(PHDASTATE pThis)
800	{
801	uint8_t corbRp = HDA_REG(pThis, CORBRP);
802	uint8_t corbWp = HDA_REG(pThis, CORBWP);
803	uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
804
805	Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", corbRp, corbWp, rirbWp));
806
807	if (!(HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA))
808	{
809	LogFunc(("CORB DMA not active, skipping\n"));
810	return VINF_SUCCESS;
811	}
812
813	Assert(pThis->cbCorbBuf);
814
815	int rc = hdaR3CmdSync(pThis, true /* Sync from guest */);
816	AssertRCReturn(rc, rc);
817
818	uint16_t cIntCnt = HDA_REG(pThis, RINTCNT) & 0xff;
819
820	if (!cIntCnt) /* 0 means 256 interrupts. */
821	cIntCnt = HDA_MAX_RINTCNT;
822
823	Log3Func(("START CORB(RP:%x, WP:%x) RIRBWP:%x, RINTCNT:%RU8/%RU8\n",
824	corbRp, corbWp, rirbWp, pThis->u16RespIntCnt, cIntCnt));
825
826	while (corbRp != corbWp)
827	{
828	corbRp = (corbRp + 1) % (pThis->cbCorbBuf / HDA_CORB_ELEMENT_SIZE); /* Advance +1 as the first command(s) are at CORBWP + 1. */
829
830	uint32_t uCmd = pThis->pu32CorbBuf[corbRp];
831	uint64_t uResp = 0;
832
833	rc = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(uCmd, 0 /* Codec index */), &uResp);
834	if (RT_FAILURE(rc))
835	LogFunc(("Codec lookup failed with rc=%Rrc\n", rc));
836
837	Log3Func(("Codec verb %08x -> response %016lx\n", uCmd, uResp));
838
839	if ( (uResp & CODEC_RESPONSE_UNSOLICITED)
840	&& !(HDA_REG(pThis, GCTL) & HDA_GCTL_UNSOL))
841	{
842	LogFunc(("Unexpected unsolicited response.\n"));
843	HDA_REG(pThis, CORBRP) = corbRp;
844
845	/** @todo r=andy No CORB/RIRB syncing to guest required in that case? */
846	return rc;
847	}
848
849	rirbWp = (rirbWp + 1) % HDA_RIRB_SIZE;
850
851	pThis->pu64RirbBuf[rirbWp] = uResp;
852
853	pThis->u16RespIntCnt++;
854
855	bool fSendInterrupt = false;
856
857	if (pThis->u16RespIntCnt == cIntCnt) /* Response interrupt count reached? */
858	{
859	pThis->u16RespIntCnt = 0; /* Reset internal interrupt response counter. */
860
861	Log3Func(("Response interrupt count reached (%RU16)\n", pThis->u16RespIntCnt));
862	fSendInterrupt = true;
863
864	}
865	else if (corbRp == corbWp) /* Did we reach the end of the current command buffer? */
866	{
867	Log3Func(("Command buffer empty\n"));
868	fSendInterrupt = true;
869	}
870
871	if (fSendInterrupt)
872	{
873	if (HDA_REG(pThis, RIRBCTL) & HDA_RIRBCTL_RINTCTL) /* Response Interrupt Control (RINTCTL) enabled? */
874	{
875	HDA_REG(pThis, RIRBSTS) \|= HDA_RIRBSTS_RINTFL;
876
877	# ifndef LOG_ENABLED
878	rc = hdaProcessInterrupt(pThis);
879	# else
880	rc = hdaProcessInterrupt(pThis, __FUNCTION__);
881	# endif
882	}
883	}
884	}
885
886	Log3Func(("END CORB(RP:%x, WP:%x) RIRBWP:%x, RINTCNT:%RU8/%RU8\n",
887	corbRp, corbWp, rirbWp, pThis->u16RespIntCnt, cIntCnt));
888
889	HDA_REG(pThis, CORBRP) = corbRp;
890	HDA_REG(pThis, RIRBWP) = rirbWp;
891
892	rc = hdaR3CmdSync(pThis, false /* Sync to guest */);
893	AssertRCReturn(rc, rc);
894
895	if (RT_FAILURE(rc))
896	AssertRCReturn(rc, rc);
897
898	return rc;
899	}
900
901	#endif /* IN_RING3 */
902
903	/* Register access handlers. */
904
905	static int hdaRegReadUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
906	{
907	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg);
908	*pu32Value = 0;
909	return VINF_SUCCESS;
910	}
911
912	static int hdaRegWriteUnimpl(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
913	{
914	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
915	return VINF_SUCCESS;
916	}
917
918	/* U8 */
919	static int hdaRegReadU8(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
920	{
921	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
922	return hdaRegReadU32(pThis, iReg, pu32Value);
923	}
924
925	static int hdaRegWriteU8(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
926	{
927	Assert((u32Value & 0xffffff00) == 0);
928	return hdaRegWriteU32(pThis, iReg, u32Value);
929	}
930
931	/* U16 */
932	static int hdaRegReadU16(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
933	{
934	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
935	return hdaRegReadU32(pThis, iReg, pu32Value);
936	}
937
938	static int hdaRegWriteU16(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
939	{
940	Assert((u32Value & 0xffff0000) == 0);
941	return hdaRegWriteU32(pThis, iReg, u32Value);
942	}
943
944	/* U24 */
945	static int hdaRegReadU24(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
946	{
947	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
948	return hdaRegReadU32(pThis, iReg, pu32Value);
949	}
950
951	#ifdef IN_RING3
952	static int hdaRegWriteU24(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
953	{
954	Assert((u32Value & 0xff000000) == 0);
955	return hdaRegWriteU32(pThis, iReg, u32Value);
956	}
957	#endif
958
959	/* U32 */
960	static int hdaRegReadU32(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
961	{
962	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
963
964	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
965
966	*pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
967
968	DEVHDA_UNLOCK(pThis);
969	return VINF_SUCCESS;
970	}
971
972	static int hdaRegWriteU32(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
973	{
974	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
975
976	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
977
978	pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
979	\| (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
980	DEVHDA_UNLOCK(pThis);
981	return VINF_SUCCESS;
982	}
983
984	static int hdaRegWriteGCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
985	{
986	RT_NOREF_PV(iReg);
987	#ifdef IN_RING3
988	DEVHDA_LOCK(pThis);
989	#else
990	if (!(u32Value & HDA_GCTL_CRST))
991	return VINF_IOM_R3_MMIO_WRITE;
992	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
993	#endif
994
995	if (u32Value & HDA_GCTL_CRST)
996	{
997	/* Set the CRST bit to indicate that we're leaving reset mode. */
998	HDA_REG(pThis, GCTL) \|= HDA_GCTL_CRST;
999	LogFunc(("Guest leaving HDA reset\n"));
1000	}
1001	else
1002	{
1003	#ifdef IN_RING3
1004	/* Enter reset state. */
1005	LogFunc(("Guest entering HDA reset with DMA(RIRB:%s, CORB:%s)\n",
1006	HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA ? "on" : "off",
1007	HDA_REG(pThis, RIRBCTL) & HDA_RIRBCTL_RDMAEN ? "on" : "off"));
1008
1009	/* Clear the CRST bit to indicate that we're in reset state. */
1010	HDA_REG(pThis, GCTL) &= ~HDA_GCTL_CRST;
1011
1012	hdaR3GCTLReset(pThis);
1013	#else
1014	AssertFailedReturnStmt(DEVHDA_UNLOCK(pThis), VINF_IOM_R3_MMIO_WRITE);
1015	#endif
1016	}
1017
1018	if (u32Value & HDA_GCTL_FCNTRL)
1019	{
1020	/* Flush: GSTS:1 set, see 6.2.6. */
1021	HDA_REG(pThis, GSTS) \|= HDA_GSTS_FSTS; /* Set the flush status. */
1022	/* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
1023	}
1024
1025	DEVHDA_UNLOCK(pThis);
1026	return VINF_SUCCESS;
1027	}
1028
1029	static int hdaRegWriteSTATESTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1030	{
1031	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1032
1033	uint32_t v = HDA_REG_IND(pThis, iReg);
1034	uint32_t nv = u32Value & HDA_STATESTS_SCSF_MASK;
1035
1036	HDA_REG(pThis, STATESTS) &= ~(v & nv); /* Write of 1 clears corresponding bit. */
1037
1038	DEVHDA_UNLOCK(pThis);
1039	return VINF_SUCCESS;
1040	}
1041
1042	static int hdaRegReadLPIB(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1043	{
1044	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
1045
1046	const uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
1047	uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, uSD);
1048	#ifdef LOG_ENABLED
1049	const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, uSD);
1050	LogFlowFunc(("[SD%RU8] LPIB=%RU32, CBL=%RU32\n", uSD, u32LPIB, u32CBL));
1051	#endif
1052
1053	*pu32Value = u32LPIB;
1054
1055	DEVHDA_UNLOCK(pThis);
1056	return VINF_SUCCESS;
1057	}
1058
1059	#ifdef IN_RING3
1060	/**
1061	* Returns the current maximum value the wall clock counter can be set to.
1062	* This maximum value depends on all currently handled HDA streams and their own current timing.
1063	*
1064	* @return Current maximum value the wall clock counter can be set to.
1065	* @param pThis HDA state.
1066	*
1067	* @remark Does not actually set the wall clock counter.
1068	*/
1069	static uint64_t hdaR3WalClkGetMax(PHDASTATE pThis)
1070	{
1071	const uint64_t u64WalClkCur = ASMAtomicReadU64(&pThis->u64WalClk);
1072	const uint64_t u64FrontAbsWalClk = pThis->SinkFront.pStream
1073	? hdaR3StreamPeriodGetAbsElapsedWalClk(&pThis->SinkFront.pStream->State.Period) : 0;
1074	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1075	# error "Implement me!"
1076	# endif
1077	const uint64_t u64LineInAbsWalClk = pThis->SinkLineIn.pStream
1078	? hdaR3StreamPeriodGetAbsElapsedWalClk(&pThis->SinkLineIn.pStream->State.Period) : 0;
1079	# ifdef VBOX_WITH_HDA_MIC_IN
1080	const uint64_t u64MicInAbsWalClk = pThis->SinkMicIn.pStream
1081	? hdaR3StreamPeriodGetAbsElapsedWalClk(&pThis->SinkMicIn.pStream->State.Period) : 0;
1082	# endif
1083
1084	uint64_t u64WalClkNew = RT_MAX(u64WalClkCur, u64FrontAbsWalClk);
1085	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1086	# error "Implement me!"
1087	# endif
1088	u64WalClkNew = RT_MAX(u64WalClkNew, u64LineInAbsWalClk);
1089	# ifdef VBOX_WITH_HDA_MIC_IN
1090	u64WalClkNew = RT_MAX(u64WalClkNew, u64MicInAbsWalClk);
1091	# endif
1092
1093	Log3Func(("%RU64 -> Front=%RU64, LineIn=%RU64 -> %RU64\n",
1094	u64WalClkCur, u64FrontAbsWalClk, u64LineInAbsWalClk, u64WalClkNew));
1095
1096	return u64WalClkNew;
1097	}
1098	#endif /* IN_RING3 */
1099
1100	static int hdaRegReadWALCLK(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1101	{
1102	#ifdef IN_RING3
1103	RT_NOREF(iReg);
1104
1105	DEVHDA_LOCK(pThis);
1106
1107	*pu32Value = RT_LO_U32(ASMAtomicReadU64(&pThis->u64WalClk));
1108
1109	Log3Func(("%RU32 (max @ %RU64)\n",*pu32Value, hdaR3WalClkGetMax(pThis)));
1110
1111	DEVHDA_UNLOCK(pThis);
1112	return VINF_SUCCESS;
1113	#else
1114	RT_NOREF(pThis, iReg, pu32Value);
1115	return VINF_IOM_R3_MMIO_READ;
1116	#endif
1117	}
1118
1119	static int hdaRegWriteCORBRP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1120	{
1121	RT_NOREF(iReg);
1122	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1123
1124	if (u32Value & HDA_CORBRP_RST)
1125	{
1126	/* Do a CORB reset. */
1127	if (pThis->cbCorbBuf)
1128	{
1129	#ifdef IN_RING3
1130	Assert(pThis->pu32CorbBuf);
1131	RT_BZERO((void *)pThis->pu32CorbBuf, pThis->cbCorbBuf);
1132	#else
1133	DEVHDA_UNLOCK(pThis);
1134	return VINF_IOM_R3_MMIO_WRITE;
1135	#endif
1136	}
1137
1138	LogRel2(("HDA: CORB reset\n"));
1139
1140	HDA_REG(pThis, CORBRP) = HDA_CORBRP_RST; /* Clears the pointer. */
1141	}
1142	else
1143	HDA_REG(pThis, CORBRP) &= ~HDA_CORBRP_RST; /* Only CORBRP_RST bit is writable. */
1144
1145	DEVHDA_UNLOCK(pThis);
1146	return VINF_SUCCESS;
1147	}
1148
1149	static int hdaRegWriteCORBCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1150	{
1151	#ifdef IN_RING3
1152	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1153
1154	int rc = hdaRegWriteU8(pThis, iReg, u32Value);
1155	AssertRC(rc);
1156
1157	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Start DMA engine. */
1158	{
1159	rc = hdaR3CORBCmdProcess(pThis);
1160	}
1161	else
1162	LogFunc(("CORB DMA not running, skipping\n"));
1163
1164	DEVHDA_UNLOCK(pThis);
1165	return rc;
1166	#else
1167	RT_NOREF(pThis, iReg, u32Value);
1168	return VINF_IOM_R3_MMIO_WRITE;
1169	#endif
1170	}
1171
1172	static int hdaRegWriteCORBSIZE(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1173	{
1174	#ifdef IN_RING3
1175	RT_NOREF(iReg);
1176	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1177
1178	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
1179	{
1180	LogFunc(("CORB DMA is (still) running, skipping\n"));
1181
1182	DEVHDA_UNLOCK(pThis);
1183	return VINF_SUCCESS;
1184	}
1185
1186	u32Value = (u32Value & HDA_CORBSIZE_SZ);
1187
1188	uint16_t cEntries = HDA_CORB_SIZE; /* Set default. */
1189
1190	switch (u32Value)
1191	{
1192	case 0: /* 8 byte; 2 entries. */
1193	cEntries = 2;
1194	break;
1195
1196	case 1: /* 64 byte; 16 entries. */
1197	cEntries = 16;
1198	break;
1199
1200	case 2: /* 1 KB; 256 entries. */
1201	/* Use default size. */
1202	break;
1203
1204	default:
1205	LogRel(("HDA: Guest tried to set an invalid CORB size (0x%x), keeping default\n", u32Value));
1206	u32Value = 2;
1207	/* Use default size. */
1208	break;
1209	}
1210
1211	uint32_t cbCorbBuf = cEntries * HDA_CORB_ELEMENT_SIZE;
1212	Assert(cbCorbBuf <= HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE); /* Paranoia. */
1213
1214	if (cbCorbBuf != pThis->cbCorbBuf)
1215	{
1216	RT_BZERO(pThis->pu32CorbBuf, HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE); /* Clear CORB when setting a new size. */
1217	pThis->cbCorbBuf = cbCorbBuf;
1218	}
1219
1220	LogFunc(("CORB buffer size is now %RU32 bytes (%u entries)\n", pThis->cbCorbBuf, pThis->cbCorbBuf / HDA_CORB_ELEMENT_SIZE));
1221
1222	HDA_REG(pThis, CORBSIZE) = u32Value;
1223
1224	DEVHDA_UNLOCK(pThis);
1225	return VINF_SUCCESS;
1226	#else
1227	RT_NOREF(pThis, iReg, u32Value);
1228	return VINF_IOM_R3_MMIO_WRITE;
1229	#endif
1230	}
1231
1232	static int hdaRegWriteCORBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1233	{
1234	RT_NOREF_PV(iReg);
1235	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1236
1237	uint32_t v = HDA_REG(pThis, CORBSTS);
1238	HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1239
1240	DEVHDA_UNLOCK(pThis);
1241	return VINF_SUCCESS;
1242	}
1243
1244	static int hdaRegWriteCORBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1245	{
1246	#ifdef IN_RING3
1247	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1248
1249	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
1250	AssertRCSuccess(rc);
1251
1252	rc = hdaR3CORBCmdProcess(pThis);
1253
1254	DEVHDA_UNLOCK(pThis);
1255	return rc;
1256	#else
1257	RT_NOREF(pThis, iReg, u32Value);
1258	return VINF_IOM_R3_MMIO_WRITE;
1259	#endif
1260	}
1261
1262	static int hdaRegWriteSDCBL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1263	{
1264	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1265
1266	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, CBL, iReg));
1267	if (pStream)
1268	{
1269	pStream->u32CBL = u32Value;
1270	LogFlowFunc(("[SD%RU8] CBL=%RU32\n", pStream->u8SD, u32Value));
1271	}
1272	else
1273	LogFunc(("[SD%RU8] Warning: Changing SDCBL on non-attached stream (0x%x)\n",
1274	HDA_SD_NUM_FROM_REG(pThis, CTL, iReg), u32Value));
1275
1276	int rc = hdaRegWriteU32(pThis, iReg, u32Value);
1277	AssertRCSuccess(rc);
1278
1279	DEVHDA_UNLOCK(pThis);
1280	return rc;
1281	}
1282
1283	static int hdaRegWriteSDCTL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1284	{
1285	#ifdef IN_RING3
1286	/* Get the stream descriptor. */
1287	const uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
1288
1289	DEVHDA_LOCK_BOTH_RETURN(pThis, uSD, VINF_IOM_R3_MMIO_WRITE);
1290
1291	/*
1292	* Some guests write too much (that is, 32-bit with the top 8 bit being junk)
1293	* instead of 24-bit required for SDCTL. So just mask this here to be safe.
1294	*/
1295	u32Value &= 0x00ffffff;
1296
1297	const bool fRun = RT_BOOL(u32Value & HDA_SDCTL_RUN);
1298	const bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_SDCTL_RUN);
1299
1300	const bool fReset = RT_BOOL(u32Value & HDA_SDCTL_SRST);
1301	const bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_SDCTL_SRST);
1302
1303	/*LogFunc(("[SD%RU8] fRun=%RTbool, fInRun=%RTbool, fReset=%RTbool, fInReset=%RTbool, %R[sdctl]\n",
1304	uSD, fRun, fInRun, fReset, fInReset, u32Value));*/
1305
1306	/*
1307	* Extract the stream tag the guest wants to use for this specific
1308	* stream descriptor (SDn). This only can happen if the stream is in a non-running
1309	* state, so we're doing the lookup and assignment here.
1310	*
1311	* So depending on the guest OS, SD3 can use stream tag 4, for example.
1312	*/
1313	uint8_t uTag = (u32Value >> HDA_SDCTL_NUM_SHIFT) & HDA_SDCTL_NUM_MASK;
1314	if (uTag > HDA_MAX_TAGS)
1315	{
1316	LogFunc(("[SD%RU8] Warning: Invalid stream tag %RU8 specified!\n", uSD, uTag));
1317
1318	int rc = hdaRegWriteU24(pThis, iReg, u32Value);
1319	DEVHDA_UNLOCK_BOTH(pThis, uSD);
1320	return rc;
1321	}
1322
1323	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
1324	AssertPtr(pStream);
1325
1326	if (fInReset)
1327	{
1328	Assert(!fReset);
1329	Assert(!fInRun && !fRun);
1330
1331	/* Exit reset state. */
1332	ASMAtomicXchgBool(&pStream->State.fInReset, false);
1333
1334	/* Report that we're done resetting this stream by clearing SRST. */
1335	HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_SRST;
1336
1337	LogFunc(("[SD%RU8] Reset exit\n", uSD));
1338	}
1339	else if (fReset)
1340	{
1341	/* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
1342	Assert(!fInRun && !fRun);
1343
1344	LogFunc(("[SD%RU8] Reset enter\n", uSD));
1345
1346	hdaR3StreamLock(pStream);
1347
1348	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1349	hdaR3StreamAsyncIOLock(pStream);
1350	# endif
1351	/* Make sure to remove the run bit before doing the actual stream reset. */
1352	HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_RUN;
1353
1354	hdaR3StreamReset(pThis, pStream, pStream->u8SD);
1355
1356	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1357	hdaR3StreamAsyncIOUnlock(pStream);
1358	# endif
1359	hdaR3StreamUnlock(pStream);
1360	}
1361	else
1362	{
1363	/*
1364	* We enter here to change DMA states only.
1365	*/
1366	if (fInRun != fRun)
1367	{
1368	Assert(!fReset && !fInReset);
1369	LogFunc(("[SD%RU8] State changed (fRun=%RTbool)\n", uSD, fRun));
1370
1371	hdaR3StreamLock(pStream);
1372
1373	int rc2;
1374
1375	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1376	if (fRun)
1377	rc2 = hdaR3StreamAsyncIOCreate(pStream);
1378
1379	hdaR3StreamAsyncIOLock(pStream);
1380	# endif
1381	if (fRun)
1382	{
1383	if (hdaGetDirFromSD(uSD) == PDMAUDIODIR_OUT)
1384	{
1385	const uint8_t uStripeCtl = ((u32Value >> HDA_SDCTL_STRIPE_SHIFT) & HDA_SDCTL_STRIPE_MASK) + 1;
1386	LogFunc(("[SD%RU8] Using %RU8 SDOs (stripe control)\n", uSD, uStripeCtl));
1387	if (uStripeCtl > 1)
1388	LogRel2(("HDA: Warning: Striping output over more than one SDO for stream #%RU8 currently is not implemented " \
1389	"(%RU8 SDOs requested)\n", uSD, uStripeCtl));
1390	}
1391
1392	PHDATAG pTag = &pThis->aTags[uTag];
1393	AssertPtr(pTag);
1394
1395	LogFunc(("[SD%RU8] Using stream tag=%RU8\n", uSD, uTag));
1396
1397	/* Assign new values. */
1398	pTag->uTag = uTag;
1399	pTag->pStream = hdaGetStreamFromSD(pThis, uSD);
1400
1401	# ifdef LOG_ENABLED
1402	PDMAUDIOPCMPROPS Props;
1403	rc2 = hdaR3SDFMTToPCMProps(HDA_STREAM_REG(pThis, FMT, pStream->u8SD), &Props);
1404	AssertRC(rc2);
1405	LogFunc(("[SD%RU8] %RU32Hz, %RU8bit, %RU8 channel(s)\n",
1406	pStream->u8SD, Props.uHz, Props.cBytes * 8 /* Bit */, Props.cChannels));
1407	# endif
1408	/* (Re-)initialize the stream with current values. */
1409	rc2 = hdaR3StreamInit(pStream, pStream->u8SD);
1410	if ( RT_SUCCESS(rc2)
1411	/* Any vital stream change occurred so that we need to (re-)add the stream to our setup?
1412	* Otherwise just skip this, as this costs a lot of performance. */
1413	&& rc2 != VINF_NO_CHANGE)
1414	{
1415	/* Remove the old stream from the device setup. */
1416	rc2 = hdaR3RemoveStream(pThis, &pStream->State.Cfg);
1417	AssertRC(rc2);
1418
1419	/* Add the stream to the device setup. */
1420	rc2 = hdaR3AddStream(pThis, &pStream->State.Cfg);
1421	AssertRC(rc2);
1422	}
1423	}
1424
1425	/* Enable/disable the stream. */
1426	rc2 = hdaR3StreamEnable(pStream, fRun /* fEnable */);
1427	AssertRC(rc2);
1428
1429	if (fRun)
1430	{
1431	/* Keep track of running streams. */
1432	pThis->cStreamsActive++;
1433
1434	/* (Re-)init the stream's period. */
1435	hdaR3StreamPeriodInit(&pStream->State.Period,
1436	pStream->u8SD, pStream->u16LVI, pStream->u32CBL, &pStream->State.Cfg);
1437
1438	/* Begin a new period for this stream. */
1439	rc2 = hdaR3StreamPeriodBegin(&pStream->State.Period, hdaWalClkGetCurrent(pThis)/* Use current wall clock time */);
1440	AssertRC(rc2);
1441
1442	rc2 = hdaR3TimerSet(pThis, pStream, TMTimerGet(pThis->pTimer[pStream->u8SD]) + pStream->State.cTransferTicks, false /* fForce */);
1443	AssertRC(rc2);
1444	}
1445	else
1446	{
1447	/* Keep track of running streams. */
1448	Assert(pThis->cStreamsActive);
1449	if (pThis->cStreamsActive)
1450	pThis->cStreamsActive--;
1451
1452	/* Make sure to (re-)schedule outstanding (delayed) interrupts. */
1453	hdaR3ReschedulePendingInterrupts(pThis);
1454
1455	/* Reset the period. */
1456	hdaR3StreamPeriodReset(&pStream->State.Period);
1457	}
1458
1459	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1460	hdaR3StreamAsyncIOUnlock(pStream);
1461	# endif
1462	/* Make sure to leave the lock before (eventually) starting the timer. */
1463	hdaR3StreamUnlock(pStream);
1464	}
1465	}
1466
1467	int rc2 = hdaRegWriteU24(pThis, iReg, u32Value);
1468	AssertRC(rc2);
1469
1470	DEVHDA_UNLOCK_BOTH(pThis, uSD);
1471	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1472	#else /* !IN_RING3 */
1473	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value);
1474	return VINF_IOM_R3_MMIO_WRITE;
1475	#endif /* IN_RING3 */
1476	}
1477
1478	static int hdaRegWriteSDSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1479	{
1480	#ifdef IN_RING3
1481	const uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, STS, iReg);
1482
1483	DEVHDA_LOCK_BOTH_RETURN(pThis, uSD, VINF_IOM_R3_MMIO_WRITE);
1484
1485	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
1486	if (!pStream)
1487	{
1488	AssertMsgFailed(("[SD%RU8] Warning: Writing SDSTS on non-attached stream (0x%x)\n",
1489	HDA_SD_NUM_FROM_REG(pThis, STS, iReg), u32Value));
1490
1491	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
1492	DEVHDA_UNLOCK_BOTH(pThis, uSD);
1493	return rc;
1494	}
1495
1496	hdaR3StreamLock(pStream);
1497
1498	uint32_t v = HDA_REG_IND(pThis, iReg);
1499
1500	/* Clear (zero) FIFOE, DESE and BCIS bits when writing 1 to it (6.2.33). */
1501	HDA_REG_IND(pThis, iReg) &= ~(u32Value & v);
1502
1503	/* Some guests tend to write SDnSTS even if the stream is not running.
1504	* So make sure to check if the RUN bit is set first. */
1505	const bool fRunning = pStream->State.fRunning;
1506
1507	Log3Func(("[SD%RU8] fRunning=%RTbool %R[sdsts]\n", pStream->u8SD, fRunning, v));
1508
1509	PHDASTREAMPERIOD pPeriod = &pStream->State.Period;
1510
1511	if (hdaR3StreamPeriodLock(pPeriod))
1512	{
1513	const bool fNeedsInterrupt = hdaR3StreamPeriodNeedsInterrupt(pPeriod);
1514	if (fNeedsInterrupt)
1515	hdaR3StreamPeriodReleaseInterrupt(pPeriod);
1516
1517	if (hdaR3StreamPeriodIsComplete(pPeriod))
1518	{
1519	/* Make sure to try to update the WALCLK register if a period is complete.
1520	* Use the maximum WALCLK value all (active) streams agree to. */
1521	const uint64_t uWalClkMax = hdaR3WalClkGetMax(pThis);
1522	if (uWalClkMax > hdaWalClkGetCurrent(pThis))
1523	hdaR3WalClkSet(pThis, uWalClkMax, false /* fForce */);
1524
1525	hdaR3StreamPeriodEnd(pPeriod);
1526
1527	if (fRunning)
1528	hdaR3StreamPeriodBegin(pPeriod, hdaWalClkGetCurrent(pThis) /* Use current wall clock time */);
1529	}
1530
1531	hdaR3StreamPeriodUnlock(pPeriod); /* Unlock before processing interrupt. */
1532	}
1533
1534	# ifndef LOG_ENABLED
1535	hdaProcessInterrupt(pThis);
1536	# else
1537	hdaProcessInterrupt(pThis, __FUNCTION__);
1538	# endif
1539
1540	const uint64_t tsNow = TMTimerGet(pThis->pTimer[uSD]);
1541	Assert(tsNow >= pStream->State.tsTransferLast);
1542
1543	const uint64_t cTicksElapsed = tsNow - pStream->State.tsTransferLast;
1544	# ifdef LOG_ENABLED
1545	const uint64_t cTicksTransferred = pStream->State.cbTransferProcessed * pStream->State.cTicksPerByte;
1546	# endif
1547
1548	uint64_t cTicksToNext = pStream->State.cTransferTicks;
1549	if (cTicksToNext) /* Only do any calculations if the stream currently is set up for transfers. */
1550	{
1551	Log3Func(("[SD%RU8] cTicksElapsed=%RU64, cTicksTransferred=%RU64, cTicksToNext=%RU64\n",
1552	pStream->u8SD, cTicksElapsed, cTicksTransferred, cTicksToNext));
1553
1554	Log3Func(("[SD%RU8] cbTransferProcessed=%RU32, cbTransferChunk=%RU32, cbTransferSize=%RU32\n",
1555	pStream->u8SD, pStream->State.cbTransferProcessed, pStream->State.cbTransferChunk, pStream->State.cbTransferSize));
1556
1557	if (cTicksElapsed <= cTicksToNext)
1558	{
1559	cTicksToNext = cTicksToNext - cTicksElapsed;
1560	}
1561	else /* Catch up. */
1562	{
1563	Log3Func(("[SD%RU8] Warning: Lagging behind (%RU64 ticks elapsed, maximum allowed is %RU64)\n",
1564	pStream->u8SD, cTicksElapsed, cTicksToNext));
1565
1566	LogRelMax2(64, ("HDA: Stream #%RU8 interrupt lagging behind (expected %uus, got %uus), trying to catch up ...\n",
1567	pStream->u8SD,
1568	(TMTimerGetFreq(pThis->pTimer[pStream->u8SD]) / pThis->uTimerHz) / 1000,(tsNow - pStream->State.tsTransferLast) / 1000));
1569
1570	cTicksToNext = 0;
1571	}
1572
1573	Log3Func(("[SD%RU8] -> cTicksToNext=%RU64\n", pStream->u8SD, cTicksToNext));
1574
1575	/* Reset processed data counter. */
1576	pStream->State.cbTransferProcessed = 0;
1577	pStream->State.tsTransferNext = tsNow + cTicksToNext;
1578
1579	/* Only re-arm the timer if there were pending transfer interrupts left
1580	* -- it could happen that we land in here if a guest writes to SDnSTS
1581	* unconditionally. */
1582	if (pStream->State.cTransferPendingInterrupts)
1583	{
1584	pStream->State.cTransferPendingInterrupts--;
1585
1586	/* Re-arm the timer. */
1587	LogFunc(("Timer set SD%RU8\n", pStream->u8SD));
1588	hdaR3TimerSet(pThis, pStream, tsNow + cTicksToNext, false /* fForce */);
1589	}
1590	}
1591
1592	hdaR3StreamUnlock(pStream);
1593
1594	DEVHDA_UNLOCK_BOTH(pThis, uSD);
1595	return VINF_SUCCESS;
1596	#else /* IN_RING3 */
1597	RT_NOREF(pThis, iReg, u32Value);
1598	return VINF_IOM_R3_MMIO_WRITE;
1599	#endif /* !IN_RING3 */
1600	}
1601
1602	static int hdaRegWriteSDLVI(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1603	{
1604	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1605
1606	if (HDA_REG_IND(pThis, iReg) == u32Value) /* Value already set? */
1607	{ /* nothing to do */ }
1608	else
1609	{
1610	uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, LVI, iReg);
1611	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
1612	if (pStream)
1613	{
1614	/** @todo Validate LVI. */
1615	pStream->u16LVI = u32Value;
1616	LogFunc(("[SD%RU8] Updating LVI to %RU16\n", uSD, pStream->u16LVI));
1617
1618	#ifdef HDA_USE_DMA_ACCESS_HANDLER
1619	if (hdaGetDirFromSD(uSD) == PDMAUDIODIR_OUT)
1620	{
1621	/* Try registering the DMA handlers.
1622	* As we can't be sure in which order LVI + BDL base are set, try registering in both routines. */
1623	if (hdaR3StreamRegisterDMAHandlers(pThis, pStream))
1624	LogFunc(("[SD%RU8] DMA logging enabled\n", pStream->u8SD));
1625	}
1626	#endif
1627	}
1628	else
1629	AssertMsgFailed(("[SD%RU8] Warning: Changing SDLVI on non-attached stream (0x%x)\n", uSD, u32Value));
1630
1631	int rc2 = hdaRegWriteU16(pThis, iReg, u32Value);
1632	AssertRC(rc2);
1633	}
1634
1635	DEVHDA_UNLOCK(pThis);
1636	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1637	}
1638
1639	static int hdaRegWriteSDFIFOW(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1640	{
1641	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1642
1643	uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg);
1644
1645	if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_IN) /* FIFOW for input streams only. */
1646	{
1647	#ifndef IN_RING0
1648	LogRel(("HDA: Warning: Guest tried to write read-only FIFOW to output stream #%RU8, ignoring\n", uSD));
1649	DEVHDA_UNLOCK(pThis);
1650	return VINF_SUCCESS;
1651	#else
1652	DEVHDA_UNLOCK(pThis);
1653	return VINF_IOM_R3_MMIO_WRITE;
1654	#endif
1655	}
1656
1657	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg));
1658	if (!pStream)
1659	{
1660	AssertMsgFailed(("[SD%RU8] Warning: Changing FIFOW on non-attached stream (0x%x)\n", uSD, u32Value));
1661
1662	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
1663	DEVHDA_UNLOCK(pThis);
1664	return rc;
1665	}
1666
1667	uint32_t u32FIFOW = 0;
1668
1669	switch (u32Value)
1670	{
1671	case HDA_SDFIFOW_8B:
1672	case HDA_SDFIFOW_16B:
1673	case HDA_SDFIFOW_32B:
1674	u32FIFOW = u32Value;
1675	break;
1676	default:
1677	ASSERT_GUEST_LOGREL_MSG_FAILED(("Guest tried write unsupported FIFOW (0x%x) to stream #%RU8, defaulting to 32 bytes\n",
1678	u32Value, uSD));
1679	u32FIFOW = HDA_SDFIFOW_32B;
1680	break;
1681	}
1682
1683	if (u32FIFOW)
1684	{
1685	pStream->u16FIFOW = hdaSDFIFOWToBytes(u32FIFOW);
1686	LogFunc(("[SD%RU8] Updating FIFOW to %RU32 bytes\n", uSD, pStream->u16FIFOW));
1687
1688	int rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOW);
1689	AssertRC(rc2);
1690	}
1691
1692	DEVHDA_UNLOCK(pThis);
1693	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1694	}
1695
1696	/**
1697	* @note This method could be called for changing value on Output Streams only (ICH6 datasheet 18.2.39).
1698	*/
1699	static int hdaRegWriteSDFIFOS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1700	{
1701	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
1702
1703	uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOS, iReg);
1704
1705	if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_OUT) /* FIFOS for output streams only. */
1706	{
1707	LogRel(("HDA: Warning: Guest tried to write read-only FIFOS to input stream #%RU8, ignoring\n", uSD));
1708
1709	DEVHDA_UNLOCK(pThis);
1710	return VINF_SUCCESS;
1711	}
1712
1713	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
1714	if (!pStream)
1715	{
1716	AssertMsgFailed(("[SD%RU8] Warning: Changing FIFOS on non-attached stream (0x%x)\n", uSD, u32Value));
1717
1718	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
1719	DEVHDA_UNLOCK(pThis);
1720	return rc;
1721	}
1722
1723	uint32_t u32FIFOS = 0;
1724
1725	switch(u32Value)
1726	{
1727	case HDA_SDOFIFO_16B:
1728	case HDA_SDOFIFO_32B:
1729	case HDA_SDOFIFO_64B:
1730	case HDA_SDOFIFO_128B:
1731	case HDA_SDOFIFO_192B:
1732	case HDA_SDOFIFO_256B:
1733	u32FIFOS = u32Value;
1734	break;
1735
1736	default:
1737	ASSERT_GUEST_LOGREL_MSG_FAILED(("Guest tried write unsupported FIFOS (0x%x) to stream #%RU8, defaulting to 192 bytes\n",
1738	u32Value, uSD));
1739	u32FIFOS = HDA_SDOFIFO_192B;
1740	break;
1741	}
1742
1743	if (u32FIFOS)
1744	{
1745	pStream->u16FIFOS = u32FIFOS + 1;
1746	LogFunc(("[SD%RU8] Updating FIFOS to %RU32 bytes\n", uSD, pStream->u16FIFOS));
1747
1748	int rc2 = hdaRegWriteU16(pThis, iReg, u32FIFOS);
1749	AssertRC(rc2);
1750	}
1751
1752	DEVHDA_UNLOCK(pThis);
1753	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1754	}
1755
1756	#ifdef IN_RING3
1757
1758	/**
1759	* Adds an audio output stream to the device setup using the given configuration.
1760	*
1761	* @returns IPRT status code.
1762	* @param pThis Device state.
1763	* @param pCfg Stream configuration to use for adding a stream.
1764	*/
1765	static int hdaR3AddStreamOut(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1766	{
1767	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1768	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1769
1770	AssertReturn(pCfg->enmDir == PDMAUDIODIR_OUT, VERR_INVALID_PARAMETER);
1771
1772	LogFlowFunc(("Stream=%s\n", pCfg->szName));
1773
1774	int rc = VINF_SUCCESS;
1775
1776	bool fUseFront = true; /* Always use front out by default. */
1777	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1778	bool fUseRear;
1779	bool fUseCenter;
1780	bool fUseLFE;
1781
1782	fUseRear = fUseCenter = fUseLFE = false;
1783
1784	/*
1785	* Use commonly used setups for speaker configurations.
1786	*/
1787
1788	/** @todo Make the following configurable through mixer API and/or CFGM? */
1789	switch (pCfg->Props.cChannels)
1790	{
1791	case 3: /* 2.1: Front (Stereo) + LFE. */
1792	{
1793	fUseLFE = true;
1794	break;
1795	}
1796
1797	case 4: /* Quadrophonic: Front (Stereo) + Rear (Stereo). */
1798	{
1799	fUseRear = true;
1800	break;
1801	}
1802
1803	case 5: /* 4.1: Front (Stereo) + Rear (Stereo) + LFE. */
1804	{
1805	fUseRear = true;
1806	fUseLFE = true;
1807	break;
1808	}
1809
1810	case 6: /* 5.1: Front (Stereo) + Rear (Stereo) + Center/LFE. */
1811	{
1812	fUseRear = true;
1813	fUseCenter = true;
1814	fUseLFE = true;
1815	break;
1816	}
1817
1818	default: /* Unknown; fall back to 2 front channels (stereo). */
1819	{
1820	rc = VERR_NOT_SUPPORTED;
1821	break;
1822	}
1823	}
1824	# endif /* !VBOX_WITH_AUDIO_HDA_51_SURROUND */
1825
1826	if (rc == VERR_NOT_SUPPORTED)
1827	{
1828	LogRel2(("HDA: Warning: Unsupported channel count (%RU8), falling back to stereo channels (2)\n", pCfg->Props.cChannels));
1829
1830	/* Fall back to 2 channels (see below in fUseFront block). */
1831	rc = VINF_SUCCESS;
1832	}
1833
1834	do
1835	{
1836	if (RT_FAILURE(rc))
1837	break;
1838
1839	if (fUseFront)
1840	{
1841	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Front");
1842
1843	pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_FRONT;
1844	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1845
1846	pCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pCfg->Props.cBytes, pCfg->Props.cChannels);
1847
1848	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT, pCfg);
1849	}
1850
1851	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1852	if ( RT_SUCCESS(rc)
1853	&& (fUseCenter \|\| fUseLFE))
1854	{
1855	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Center/LFE");
1856
1857	pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_CENTER_LFE;
1858	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1859
1860	pCfg->Props.cChannels = (fUseCenter && fUseLFE) ? 2 : 1;
1861	pCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pCfg->Props.cBytes, pCfg->Props.cChannels);
1862
1863	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE, pCfg);
1864	}
1865
1866	if ( RT_SUCCESS(rc)
1867	&& fUseRear)
1868	{
1869	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Rear");
1870
1871	pCfg->DestSource.Dest = PDMAUDIOPLAYBACKDEST_REAR;
1872	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1873
1874	pCfg->Props.cChannels = 2;
1875	pCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pCfg->Props.cBytes, pCfg->Props.cChannels);
1876
1877	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR, pCfg);
1878	}
1879	# endif /* VBOX_WITH_AUDIO_HDA_51_SURROUND */
1880
1881	} while (0);
1882
1883	LogFlowFuncLeaveRC(rc);
1884	return rc;
1885	}
1886
1887	/**
1888	* Adds an audio input stream to the device setup using the given configuration.
1889	*
1890	* @returns IPRT status code.
1891	* @param pThis Device state.
1892	* @param pCfg Stream configuration to use for adding a stream.
1893	*/
1894	static int hdaR3AddStreamIn(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1895	{
1896	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1897	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1898
1899	AssertReturn(pCfg->enmDir == PDMAUDIODIR_IN, VERR_INVALID_PARAMETER);
1900
1901	LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Source));
1902
1903	int rc;
1904
1905	switch (pCfg->DestSource.Source)
1906	{
1907	case PDMAUDIORECSOURCE_LINE:
1908	{
1909	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN, pCfg);
1910	break;
1911	}
1912	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
1913	case PDMAUDIORECSOURCE_MIC:
1914	{
1915	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN, pCfg);
1916	break;
1917	}
1918	# endif
1919	default:
1920	rc = VERR_NOT_SUPPORTED;
1921	break;
1922	}
1923
1924	LogFlowFuncLeaveRC(rc);
1925	return rc;
1926	}
1927
1928	/**
1929	* Adds an audio stream to the device setup using the given configuration.
1930	*
1931	* @returns IPRT status code.
1932	* @param pThis Device state.
1933	* @param pCfg Stream configuration to use for adding a stream.
1934	*/
1935	static int hdaR3AddStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1936	{
1937	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1938	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1939
1940	int rc;
1941
1942	LogFlowFuncEnter();
1943
1944	switch (pCfg->enmDir)
1945	{
1946	case PDMAUDIODIR_OUT:
1947	rc = hdaR3AddStreamOut(pThis, pCfg);
1948	break;
1949
1950	case PDMAUDIODIR_IN:
1951	rc = hdaR3AddStreamIn(pThis, pCfg);
1952	break;
1953
1954	default:
1955	rc = VERR_NOT_SUPPORTED;
1956	AssertFailed();
1957	break;
1958	}
1959
1960	LogFlowFunc(("Returning %Rrc\n", rc));
1961
1962	return rc;
1963	}
1964
1965	/**
1966	* Removes an audio stream from the device setup using the given configuration.
1967	*
1968	* @returns IPRT status code.
1969	* @param pThis Device state.
1970	* @param pCfg Stream configuration to use for removing a stream.
1971	*/
1972	static int hdaR3RemoveStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1973	{
1974	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1975	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1976
1977	int rc = VINF_SUCCESS;
1978
1979	PDMAUDIOMIXERCTL enmMixerCtl = PDMAUDIOMIXERCTL_UNKNOWN;
1980	switch (pCfg->enmDir)
1981	{
1982	case PDMAUDIODIR_IN:
1983	{
1984	LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Source));
1985
1986	switch (pCfg->DestSource.Source)
1987	{
1988	case PDMAUDIORECSOURCE_UNKNOWN: break;
1989	case PDMAUDIORECSOURCE_LINE: enmMixerCtl = PDMAUDIOMIXERCTL_LINE_IN; break;
1990	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
1991	case PDMAUDIORECSOURCE_MIC: enmMixerCtl = PDMAUDIOMIXERCTL_MIC_IN; break;
1992	# endif
1993	default:
1994	rc = VERR_NOT_SUPPORTED;
1995	break;
1996	}
1997
1998	break;
1999	}
2000
2001	case PDMAUDIODIR_OUT:
2002	{
2003	LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->DestSource.Dest));
2004
2005	switch (pCfg->DestSource.Dest)
2006	{
2007	case PDMAUDIOPLAYBACKDEST_UNKNOWN: break;
2008	case PDMAUDIOPLAYBACKDEST_FRONT: enmMixerCtl = PDMAUDIOMIXERCTL_FRONT; break;
2009	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2010	case PDMAUDIOPLAYBACKDEST_CENTER_LFE: enmMixerCtl = PDMAUDIOMIXERCTL_CENTER_LFE; break;
2011	case PDMAUDIOPLAYBACKDEST_REAR: enmMixerCtl = PDMAUDIOMIXERCTL_REAR; break;
2012	# endif
2013	default:
2014	rc = VERR_NOT_SUPPORTED;
2015	break;
2016	}
2017	break;
2018	}
2019
2020	default:
2021	rc = VERR_NOT_SUPPORTED;
2022	break;
2023	}
2024
2025	if ( RT_SUCCESS(rc)
2026	&& enmMixerCtl != PDMAUDIOMIXERCTL_UNKNOWN)
2027	{
2028	rc = hdaCodecRemoveStream(pThis->pCodec, enmMixerCtl);
2029	}
2030
2031	LogFlowFuncLeaveRC(rc);
2032	return rc;
2033	}
2034	#endif /* IN_RING3 */
2035
2036	static int hdaRegWriteSDFMT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2037	{
2038	DEVHDA_LOCK(pThis);
2039
2040	# ifdef LOG_ENABLED
2041	if (!hdaGetStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FMT, iReg)))
2042	LogFunc(("[SD%RU8] Warning: Changing SDFMT on non-attached stream (0x%x)\n",
2043	HDA_SD_NUM_FROM_REG(pThis, FMT, iReg), u32Value));
2044	# endif
2045
2046
2047	/* Write the wanted stream format into the register in any case.
2048	*
2049	* This is important for e.g. MacOS guests, as those try to initialize streams which are not reported
2050	* by the device emulation (wants 4 channels, only have 2 channels at the moment).
2051	*
2052	* When ignoring those (invalid) formats, this leads to MacOS thinking that the device is malfunctioning
2053	* and therefore disabling the device completely. */
2054	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
2055	AssertRC(rc);
2056
2057	DEVHDA_UNLOCK(pThis);
2058	return VINF_SUCCESS; /* Never return failure. */
2059	}
2060
2061	/* Note: Will be called for both, BDPL and BDPU, registers. */
2062	DECLINLINE(int) hdaRegWriteSDBDPX(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value, uint8_t uSD)
2063	{
2064	#ifdef IN_RING3
2065	DEVHDA_LOCK(pThis);
2066
2067	int rc2 = hdaRegWriteU32(pThis, iReg, u32Value);
2068	AssertRC(rc2);
2069
2070	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
2071	if (!pStream)
2072	{
2073	DEVHDA_UNLOCK(pThis);
2074	return VINF_SUCCESS;
2075	}
2076
2077	/* Update BDL base. */
2078	pStream->u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, uSD),
2079	HDA_STREAM_REG(pThis, BDPU, uSD));
2080
2081	# ifdef HDA_USE_DMA_ACCESS_HANDLER
2082	if (hdaGetDirFromSD(uSD) == PDMAUDIODIR_OUT)
2083	{
2084	/* Try registering the DMA handlers.
2085	* As we can't be sure in which order LVI + BDL base are set, try registering in both routines. */
2086	if (hdaR3StreamRegisterDMAHandlers(pThis, pStream))
2087	LogFunc(("[SD%RU8] DMA logging enabled\n", pStream->u8SD));
2088	}
2089	# endif
2090
2091	LogFlowFunc(("[SD%RU8] BDLBase=0x%x\n", pStream->u8SD, pStream->u64BDLBase));
2092
2093	DEVHDA_UNLOCK(pThis);
2094	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2095	#else /* !IN_RING3 */
2096	RT_NOREF_PV(pThis); RT_NOREF_PV(iReg); RT_NOREF_PV(u32Value); RT_NOREF_PV(uSD);
2097	return VINF_IOM_R3_MMIO_WRITE;
2098	#endif /* IN_RING3 */
2099	}
2100
2101	static int hdaRegWriteSDBDPL(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2102	{
2103	return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPL, iReg));
2104	}
2105
2106	static int hdaRegWriteSDBDPU(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2107	{
2108	return hdaRegWriteSDBDPX(pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPU, iReg));
2109	}
2110
2111	static int hdaRegReadIRS(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2112	{
2113	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
2114
2115	/* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
2116	if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2117	\|\| (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA))
2118	{
2119	HDA_REG(pThis, IRS) = HDA_IRS_ICB; /* busy */
2120	}
2121
2122	int rc = hdaRegReadU32(pThis, iReg, pu32Value);
2123	DEVHDA_UNLOCK(pThis);
2124
2125	return rc;
2126	}
2127
2128	static int hdaRegWriteIRS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2129	{
2130	RT_NOREF_PV(iReg);
2131	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2132
2133	/*
2134	* If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
2135	* write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
2136	*/
2137	if ( (u32Value & HDA_IRS_ICB)
2138	&& !(HDA_REG(pThis, IRS) & HDA_IRS_ICB))
2139	{
2140	#ifdef IN_RING3
2141	uint32_t uCmd = HDA_REG(pThis, IC);
2142
2143	if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
2144	{
2145	DEVHDA_UNLOCK(pThis);
2146
2147	/*
2148	* 3.4.3: Defines behavior of immediate Command status register.
2149	*/
2150	LogRel(("HDA: Guest attempted process immediate verb (%x) with active CORB\n", uCmd));
2151	return VINF_SUCCESS;
2152	}
2153
2154	HDA_REG(pThis, IRS) = HDA_IRS_ICB; /* busy */
2155
2156	uint64_t uResp;
2157	int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec,
2158	HDA_CODEC_CMD(uCmd, 0 /* LUN */), &uResp);
2159	if (RT_FAILURE(rc2))
2160	LogFunc(("Codec lookup failed with rc2=%Rrc\n", rc2));
2161
2162	HDA_REG(pThis, IR) = (uint32_t)uResp; /** @todo r=andy Do we need a 64-bit response? */
2163	HDA_REG(pThis, IRS) = HDA_IRS_IRV; /* result is ready */
2164	/** @todo r=michaln We just set the IRS value, why are we clearing unset bits? */
2165	HDA_REG(pThis, IRS) &= ~HDA_IRS_ICB; /* busy is clear */
2166
2167	DEVHDA_UNLOCK(pThis);
2168	return VINF_SUCCESS;
2169	#else /* !IN_RING3 */
2170	DEVHDA_UNLOCK(pThis);
2171	return VINF_IOM_R3_MMIO_WRITE;
2172	#endif /* !IN_RING3 */
2173	}
2174
2175	/*
2176	* Once the guest read the response, it should clear the IRV bit of the IRS register.
2177	*/
2178	HDA_REG(pThis, IRS) &= ~(u32Value & HDA_IRS_IRV);
2179
2180	DEVHDA_UNLOCK(pThis);
2181	return VINF_SUCCESS;
2182	}
2183
2184	static int hdaRegWriteRIRBWP(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2185	{
2186	RT_NOREF(iReg);
2187	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2188
2189	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
2190	{
2191	LogFunc(("CORB DMA (still) running, skipping\n"));
2192
2193	DEVHDA_UNLOCK(pThis);
2194	return VINF_SUCCESS;
2195	}
2196
2197	if (u32Value & HDA_RIRBWP_RST)
2198	{
2199	/* Do a RIRB reset. */
2200	if (pThis->cbRirbBuf)
2201	{
2202	Assert(pThis->pu64RirbBuf);
2203	RT_BZERO((void *)pThis->pu64RirbBuf, pThis->cbRirbBuf);
2204	}
2205
2206	LogRel2(("HDA: RIRB reset\n"));
2207
2208	HDA_REG(pThis, RIRBWP) = 0;
2209	}
2210
2211	/* The remaining bits are O, see 6.2.22. */
2212
2213	DEVHDA_UNLOCK(pThis);
2214	return VINF_SUCCESS;
2215	}
2216
2217	static int hdaRegWriteRINTCNT(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2218	{
2219	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2220
2221	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
2222	{
2223	LogFunc(("CORB DMA is (still) running, skipping\n"));
2224
2225	DEVHDA_UNLOCK(pThis);
2226	return VINF_SUCCESS;
2227	}
2228
2229	int rc = hdaRegWriteU16(pThis, iReg, u32Value);
2230	AssertRC(rc);
2231
2232	LogFunc(("Response interrupt count is now %RU8\n", HDA_REG(pThis, RINTCNT) & 0xFF));
2233
2234	DEVHDA_UNLOCK(pThis);
2235	return rc;
2236	}
2237
2238	static int hdaRegWriteBase(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2239	{
2240	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2241	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2242
2243	int rc = hdaRegWriteU32(pThis, iReg, u32Value);
2244	AssertRCSuccess(rc);
2245
2246	switch (iReg)
2247	{
2248	case HDA_REG_CORBLBASE:
2249	pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
2250	pThis->u64CORBBase \|= pThis->au32Regs[iRegMem];
2251	break;
2252	case HDA_REG_CORBUBASE:
2253	pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
2254	pThis->u64CORBBase \|= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2255	break;
2256	case HDA_REG_RIRBLBASE:
2257	pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
2258	pThis->u64RIRBBase \|= pThis->au32Regs[iRegMem];
2259	break;
2260	case HDA_REG_RIRBUBASE:
2261	pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
2262	pThis->u64RIRBBase \|= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2263	break;
2264	case HDA_REG_DPLBASE:
2265	{
2266	pThis->u64DPBase = pThis->au32Regs[iRegMem] & DPBASE_ADDR_MASK;
2267	Assert(pThis->u64DPBase % 128 == 0); /* Must be 128-byte aligned. */
2268
2269	/* Also make sure to handle the DMA position enable bit. */
2270	pThis->fDMAPosition = pThis->au32Regs[iRegMem] & RT_BIT_32(0);
2271	LogRel(("HDA: %s DMA position buffer\n", pThis->fDMAPosition ? "Enabled" : "Disabled"));
2272	break;
2273	}
2274	case HDA_REG_DPUBASE:
2275	pThis->u64DPBase = RT_MAKE_U64(RT_LO_U32(pThis->u64DPBase) & DPBASE_ADDR_MASK, pThis->au32Regs[iRegMem]);
2276	break;
2277	default:
2278	AssertMsgFailed(("Invalid index\n"));
2279	break;
2280	}
2281
2282	LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
2283	pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
2284
2285	DEVHDA_UNLOCK(pThis);
2286	return rc;
2287	}
2288
2289	static int hdaRegWriteRIRBSTS(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2290	{
2291	RT_NOREF_PV(iReg);
2292	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
2293
2294	uint8_t v = HDA_REG(pThis, RIRBSTS);
2295	HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
2296
2297	#ifndef LOG_ENABLED
2298	int rc = hdaProcessInterrupt(pThis);
2299	#else
2300	int rc = hdaProcessInterrupt(pThis, __FUNCTION__);
2301	#endif
2302
2303	DEVHDA_UNLOCK(pThis);
2304	return rc;
2305	}
2306
2307	#ifdef IN_RING3
2308
2309	/**
2310	* Retrieves a corresponding sink for a given mixer control.
2311	* Returns NULL if no sink is found.
2312	*
2313	* @return PHDAMIXERSINK
2314	* @param pThis HDA state.
2315	* @param enmMixerCtl Mixer control to get the corresponding sink for.
2316	*/
2317	static PHDAMIXERSINK hdaR3MixerControlToSink(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
2318	{
2319	PHDAMIXERSINK pSink;
2320
2321	switch (enmMixerCtl)
2322	{
2323	case PDMAUDIOMIXERCTL_VOLUME_MASTER:
2324	/* Fall through is intentional. */
2325	case PDMAUDIOMIXERCTL_FRONT:
2326	pSink = &pThis->SinkFront;
2327	break;
2328	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2329	case PDMAUDIOMIXERCTL_CENTER_LFE:
2330	pSink = &pThis->SinkCenterLFE;
2331	break;
2332	case PDMAUDIOMIXERCTL_REAR:
2333	pSink = &pThis->SinkRear;
2334	break;
2335	# endif
2336	case PDMAUDIOMIXERCTL_LINE_IN:
2337	pSink = &pThis->SinkLineIn;
2338	break;
2339	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2340	case PDMAUDIOMIXERCTL_MIC_IN:
2341	pSink = &pThis->SinkMicIn;
2342	break;
2343	# endif
2344	default:
2345	pSink = NULL;
2346	AssertMsgFailed(("Unhandled mixer control\n"));
2347	break;
2348	}
2349
2350	return pSink;
2351	}
2352
2353	/**
2354	* Adds a specific HDA driver to the driver chain.
2355	*
2356	* @return IPRT status code.
2357	* @param pThis HDA state.
2358	* @param pDrv HDA driver to add.
2359	*/
2360	static int hdaR3MixerAddDrv(PHDASTATE pThis, PHDADRIVER pDrv)
2361	{
2362	int rc = VINF_SUCCESS;
2363
2364	PHDASTREAM pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkLineIn);
2365	if ( pStream
2366	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2367	{
2368	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkLineIn.pMixSink, &pStream->State.Cfg, pDrv);
2369	if (RT_SUCCESS(rc))
2370	rc = rc2;
2371	}
2372
2373	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2374	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkMicIn);
2375	if ( pStream
2376	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2377	{
2378	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkMicIn.pMixSink, &pStream->State.Cfg, pDrv);
2379	if (RT_SUCCESS(rc))
2380	rc = rc2;
2381	}
2382	# endif
2383
2384	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkFront);
2385	if ( pStream
2386	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2387	{
2388	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkFront.pMixSink, &pStream->State.Cfg, pDrv);
2389	if (RT_SUCCESS(rc))
2390	rc = rc2;
2391	}
2392
2393	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2394	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkCenterLFE);
2395	if ( pStream
2396	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2397	{
2398	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkCenterLFE.pMixSink, &pStream->State.Cfg, pDrv);
2399	if (RT_SUCCESS(rc))
2400	rc = rc2;
2401	}
2402
2403	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkRear);
2404	if ( pStream
2405	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2406	{
2407	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkRear.pMixSink, &pStream->State.Cfg, pDrv);
2408	if (RT_SUCCESS(rc))
2409	rc = rc2;
2410	}
2411	# endif
2412
2413	return rc;
2414	}
2415
2416	/**
2417	* Removes a specific HDA driver from the driver chain and destroys its
2418	* associated streams.
2419	*
2420	* @param pThis HDA state.
2421	* @param pDrv HDA driver to remove.
2422	*/
2423	static void hdaR3MixerRemoveDrv(PHDASTATE pThis, PHDADRIVER pDrv)
2424	{
2425	AssertPtrReturnVoid(pThis);
2426	AssertPtrReturnVoid(pDrv);
2427
2428	if (pDrv->LineIn.pMixStrm)
2429	{
2430	if (AudioMixerSinkGetRecordingSource(pThis->SinkLineIn.pMixSink) == pDrv->LineIn.pMixStrm)
2431	AudioMixerSinkSetRecordingSource(pThis->SinkLineIn.pMixSink, NULL);
2432
2433	AudioMixerSinkRemoveStream(pThis->SinkLineIn.pMixSink, pDrv->LineIn.pMixStrm);
2434	AudioMixerStreamDestroy(pDrv->LineIn.pMixStrm);
2435	pDrv->LineIn.pMixStrm = NULL;
2436	}
2437
2438	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2439	if (pDrv->MicIn.pMixStrm)
2440	{
2441	if (AudioMixerSinkGetRecordingSource(pThis->SinkMicIn.pMixSink) == pDrv->MicIn.pMixStrm)
2442	AudioMixerSinkSetRecordingSource(&pThis->SinkMicIn.pMixSink, NULL);
2443
2444	AudioMixerSinkRemoveStream(pThis->SinkMicIn.pMixSink, pDrv->MicIn.pMixStrm);
2445	AudioMixerStreamDestroy(pDrv->MicIn.pMixStrm);
2446	pDrv->MicIn.pMixStrm = NULL;
2447	}
2448	# endif
2449
2450	if (pDrv->Front.pMixStrm)
2451	{
2452	AudioMixerSinkRemoveStream(pThis->SinkFront.pMixSink, pDrv->Front.pMixStrm);
2453	AudioMixerStreamDestroy(pDrv->Front.pMixStrm);
2454	pDrv->Front.pMixStrm = NULL;
2455	}
2456
2457	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2458	if (pDrv->CenterLFE.pMixStrm)
2459	{
2460	AudioMixerSinkRemoveStream(pThis->SinkCenterLFE.pMixSink, pDrv->CenterLFE.pMixStrm);
2461	AudioMixerStreamDestroy(pDrv->CenterLFE.pMixStrm);
2462	pDrv->CenterLFE.pMixStrm = NULL;
2463	}
2464
2465	if (pDrv->Rear.pMixStrm)
2466	{
2467	AudioMixerSinkRemoveStream(pThis->SinkRear.pMixSink, pDrv->Rear.pMixStrm);
2468	AudioMixerStreamDestroy(pDrv->Rear.pMixStrm);
2469	pDrv->Rear.pMixStrm = NULL;
2470	}
2471	# endif
2472
2473	RTListNodeRemove(&pDrv->Node);
2474	}
2475
2476	/**
2477	* Adds a driver stream to a specific mixer sink.
2478	*
2479	* @returns IPRT status code (ignored by caller).
2480	* @param pThis HDA state.
2481	* @param pMixSink Audio mixer sink to add audio streams to.
2482	* @param pCfg Audio stream configuration to use for the audio streams to add.
2483	* @param pDrv Driver stream to add.
2484	*/
2485	static int hdaR3MixerAddDrvStream(PHDASTATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg, PHDADRIVER pDrv)
2486	{
2487	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2488	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
2489	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2490
2491	LogFunc(("szSink=%s, szStream=%s, cChannels=%RU8\n", pMixSink->pszName, pCfg->szName, pCfg->Props.cChannels));
2492
2493	PPDMAUDIOSTREAMCFG pStreamCfg = DrvAudioHlpStreamCfgDup(pCfg);
2494	if (!pStreamCfg)
2495	return VERR_NO_MEMORY;
2496
2497	LogFunc(("[LUN#%RU8] %s\n", pDrv->uLUN, pStreamCfg->szName));
2498
2499	int rc = VINF_SUCCESS;
2500
2501	PHDADRIVERSTREAM pDrvStream = NULL;
2502
2503	if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
2504	{
2505	LogFunc(("enmRecSource=%d\n", pStreamCfg->DestSource.Source));
2506
2507	switch (pStreamCfg->DestSource.Source)
2508	{
2509	case PDMAUDIORECSOURCE_LINE:
2510	pDrvStream = &pDrv->LineIn;
2511	break;
2512	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2513	case PDMAUDIORECSOURCE_MIC:
2514	pDrvStream = &pDrv->MicIn;
2515	break;
2516	# endif
2517	default:
2518	rc = VERR_NOT_SUPPORTED;
2519	break;
2520	}
2521	}
2522	else if (pStreamCfg->enmDir == PDMAUDIODIR_OUT)
2523	{
2524	LogFunc(("enmPlaybackDest=%d\n", pStreamCfg->DestSource.Dest));
2525
2526	switch (pStreamCfg->DestSource.Dest)
2527	{
2528	case PDMAUDIOPLAYBACKDEST_FRONT:
2529	pDrvStream = &pDrv->Front;
2530	break;
2531	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2532	case PDMAUDIOPLAYBACKDEST_CENTER_LFE:
2533	pDrvStream = &pDrv->CenterLFE;
2534	break;
2535	case PDMAUDIOPLAYBACKDEST_REAR:
2536	pDrvStream = &pDrv->Rear;
2537	break;
2538	# endif
2539	default:
2540	rc = VERR_NOT_SUPPORTED;
2541	break;
2542	}
2543	}
2544	else
2545	rc = VERR_NOT_SUPPORTED;
2546
2547	if (RT_SUCCESS(rc))
2548	{
2549	AssertPtr(pDrvStream);
2550	AssertMsg(pDrvStream->pMixStrm == NULL, ("[LUN#%RU8] Driver stream already present when it must not\n", pDrv->uLUN));
2551
2552	PAUDMIXSTREAM pMixStrm;
2553	rc = AudioMixerSinkCreateStream(pMixSink, pDrv->pConnector, pStreamCfg, 0 /* fFlags */, &pMixStrm);
2554	LogFlowFunc(("LUN#%RU8: Created stream \"%s\" for sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
2555	if (RT_SUCCESS(rc))
2556	{
2557	rc = AudioMixerSinkAddStream(pMixSink, pMixStrm);
2558	LogFlowFunc(("LUN#%RU8: Added stream \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
2559	if (RT_SUCCESS(rc))
2560	{
2561	/* If this is an input stream, always set the latest (added) stream
2562	* as the recording source.
2563	* @todo Make the recording source dynamic (CFGM?). */
2564	if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
2565	{
2566	PDMAUDIOBACKENDCFG Cfg;
2567	rc = pDrv->pConnector->pfnGetConfig(pDrv->pConnector, &Cfg);
2568	if (RT_SUCCESS(rc))
2569	{
2570	if (Cfg.cMaxStreamsIn) /* At least one input source available? */
2571	{
2572	rc = AudioMixerSinkSetRecordingSource(pMixSink, pMixStrm);
2573	LogFlowFunc(("LUN#%RU8: Recording source for '%s' -> '%s', rc=%Rrc\n",
2574	pDrv->uLUN, pStreamCfg->szName, Cfg.szName, rc));
2575
2576	if (RT_SUCCESS(rc))
2577	LogRel(("HDA: Set recording source for '%s' to '%s'\n",
2578	pStreamCfg->szName, Cfg.szName));
2579	}
2580	else
2581	LogRel(("HDA: Backend '%s' currently is not offering any recording source for '%s'\n",
2582	Cfg.szName, pStreamCfg->szName));
2583	}
2584	else if (RT_FAILURE(rc))
2585	LogFunc(("LUN#%RU8: Unable to retrieve backend configuration for '%s', rc=%Rrc\n",
2586	pDrv->uLUN, pStreamCfg->szName, rc));
2587	}
2588	}
2589	}
2590
2591	if (RT_SUCCESS(rc))
2592	pDrvStream->pMixStrm = pMixStrm;
2593	}
2594
2595	if (pStreamCfg)
2596	{
2597	RTMemFree(pStreamCfg);
2598	pStreamCfg = NULL;
2599	}
2600
2601	LogFlowFuncLeaveRC(rc);
2602	return rc;
2603	}
2604
2605	/**
2606	* Adds all current driver streams to a specific mixer sink.
2607	*
2608	* @returns IPRT status code.
2609	* @param pThis HDA state.
2610	* @param pMixSink Audio mixer sink to add stream to.
2611	* @param pCfg Audio stream configuration to use for the audio streams to add.
2612	*/
2613	static int hdaR3MixerAddDrvStreams(PHDASTATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg)
2614	{
2615	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2616	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
2617	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2618
2619	LogFunc(("Sink=%s, Stream=%s\n", pMixSink->pszName, pCfg->szName));
2620
2621	if (!DrvAudioHlpStreamCfgIsValid(pCfg))
2622	return VERR_INVALID_PARAMETER;
2623
2624	int rc = AudioMixerSinkSetFormat(pMixSink, &pCfg->Props);
2625	if (RT_FAILURE(rc))
2626	return rc;
2627
2628	PHDADRIVER pDrv;
2629	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2630	{
2631	int rc2 = hdaR3MixerAddDrvStream(pThis, pMixSink, pCfg, pDrv);
2632	if (RT_FAILURE(rc2))
2633	LogFunc(("Attaching stream failed with %Rrc\n", rc2));
2634
2635	/* Do not pass failure to rc here, as there might be drivers which aren't
2636	* configured / ready yet. */
2637	}
2638
2639	return rc;
2640	}
2641
2642	/**
2643	* @interface_method_impl{HDACODEC,pfnCbMixerAddStream}
2644	*
2645	* Adds a new audio stream to a specific mixer control.
2646	*
2647	* Depending on the mixer control the stream then gets assigned to one of the internal
2648	* mixer sinks, which in turn then handle the mixing of all connected streams to that sink.
2649	*
2650	* @return IPRT status code.
2651	* @param pThis HDA state.
2652	* @param enmMixerCtl Mixer control to assign new stream to.
2653	* @param pCfg Stream configuration for the new stream.
2654	*/
2655	static DECLCALLBACK(int) hdaR3MixerAddStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOSTREAMCFG pCfg)
2656	{
2657	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2658	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2659
2660	int rc;
2661
2662	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2663	if (pSink)
2664	{
2665	rc = hdaR3MixerAddDrvStreams(pThis, pSink->pMixSink, pCfg);
2666
2667	AssertPtr(pSink->pMixSink);
2668	LogFlowFunc(("Sink=%s, Mixer control=%s\n", pSink->pMixSink->pszName, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl)));
2669	}
2670	else
2671	rc = VERR_NOT_FOUND;
2672
2673	LogFlowFuncLeaveRC(rc);
2674	return rc;
2675	}
2676
2677	/**
2678	* @interface_method_impl{HDACODEC,pfnCbMixerRemoveStream}
2679	*
2680	* Removes a specified mixer control from the HDA's mixer.
2681	*
2682	* @return IPRT status code.
2683	* @param pThis HDA state.
2684	* @param enmMixerCtl Mixer control to remove.
2685	*
2686	* @remarks Can be called as a callback by the HDA codec.
2687	*/
2688	static DECLCALLBACK(int) hdaR3MixerRemoveStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
2689	{
2690	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2691
2692	int rc;
2693
2694	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2695	if (pSink)
2696	{
2697	PHDADRIVER pDrv;
2698	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2699	{
2700	PAUDMIXSTREAM pMixStream = NULL;
2701	switch (enmMixerCtl)
2702	{
2703	/*
2704	* Input.
2705	*/
2706	case PDMAUDIOMIXERCTL_LINE_IN:
2707	pMixStream = pDrv->LineIn.pMixStrm;
2708	pDrv->LineIn.pMixStrm = NULL;
2709	break;
2710	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2711	case PDMAUDIOMIXERCTL_MIC_IN:
2712	pMixStream = pDrv->MicIn.pMixStrm;
2713	pDrv->MicIn.pMixStrm = NULL;
2714	break;
2715	# endif
2716	/*
2717	* Output.
2718	*/
2719	case PDMAUDIOMIXERCTL_FRONT:
2720	pMixStream = pDrv->Front.pMixStrm;
2721	pDrv->Front.pMixStrm = NULL;
2722	break;
2723	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2724	case PDMAUDIOMIXERCTL_CENTER_LFE:
2725	pMixStream = pDrv->CenterLFE.pMixStrm;
2726	pDrv->CenterLFE.pMixStrm = NULL;
2727	break;
2728	case PDMAUDIOMIXERCTL_REAR:
2729	pMixStream = pDrv->Rear.pMixStrm;
2730	pDrv->Rear.pMixStrm = NULL;
2731	break;
2732	# endif
2733	default:
2734	AssertMsgFailed(("Mixer control %d not implemented\n", enmMixerCtl));
2735	break;
2736	}
2737
2738	if (pMixStream)
2739	{
2740	AudioMixerSinkRemoveStream(pSink->pMixSink, pMixStream);
2741	AudioMixerStreamDestroy(pMixStream);
2742
2743	pMixStream = NULL;
2744	}
2745	}
2746
2747	AudioMixerSinkRemoveAllStreams(pSink->pMixSink);
2748	rc = VINF_SUCCESS;
2749	}
2750	else
2751	rc = VERR_NOT_FOUND;
2752
2753	LogFunc(("Mixer control=%s, rc=%Rrc\n", DrvAudioHlpAudMixerCtlToStr(enmMixerCtl), rc));
2754	return rc;
2755	}
2756
2757	/**
2758	* @interface_method_impl{HDACODEC,pfnCbMixerControl}
2759	*
2760	* Controls an input / output converter widget, that is, which converter is connected
2761	* to which stream (and channel).
2762	*
2763	* @returns IPRT status code.
2764	* @param pThis HDA State.
2765	* @param enmMixerCtl Mixer control to set SD stream number and channel for.
2766	* @param uSD SD stream number (number + 1) to set. Set to 0 for unassign.
2767	* @param uChannel Channel to set. Only valid if a valid SD stream number is specified.
2768	*
2769	* @remarks Can be called as a callback by the HDA codec.
2770	*/
2771	static DECLCALLBACK(int) hdaR3MixerControl(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, uint8_t uSD, uint8_t uChannel)
2772	{
2773	LogFunc(("enmMixerCtl=%s, uSD=%RU8, uChannel=%RU8\n", DrvAudioHlpAudMixerCtlToStr(enmMixerCtl), uSD, uChannel));
2774
2775	if (uSD == 0) /* Stream number 0 is reserved. */
2776	{
2777	Log2Func(("Invalid SDn (%RU8) number for mixer control '%s', ignoring\n", uSD, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl)));
2778	return VINF_SUCCESS;
2779	}
2780	/* uChannel is optional. */
2781
2782	/* SDn0 starts as 1. */
2783	Assert(uSD);
2784	uSD--;
2785
2786	# ifndef VBOX_WITH_AUDIO_HDA_MIC_IN
2787	/* Only SDI0 (Line-In) is supported. */
2788	if ( hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN
2789	&& uSD >= 1)
2790	{
2791	LogRel2(("HDA: Dedicated Mic-In support not imlpemented / built-in (stream #%RU8), using Line-In (stream #0) instead\n", uSD));
2792	uSD = 0;
2793	}
2794	# endif
2795
2796	int rc = VINF_SUCCESS;
2797
2798	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2799	if (pSink)
2800	{
2801	AssertPtr(pSink->pMixSink);
2802
2803	/* If this an output stream, determine the correct SD#. */
2804	if ( (uSD < HDA_MAX_SDI)
2805	&& AudioMixerSinkGetDir(pSink->pMixSink) == AUDMIXSINKDIR_OUTPUT)
2806	{
2807	uSD += HDA_MAX_SDI;
2808	}
2809
2810	/* Detach the existing stream from the sink. */
2811	if ( pSink->pStream
2812	&& ( pSink->pStream->u8SD != uSD
2813	\|\| pSink->pStream->u8Channel != uChannel)
2814	)
2815	{
2816	LogFunc(("Sink '%s' was assigned to stream #%RU8 (channel %RU8) before\n",
2817	pSink->pMixSink->pszName, pSink->pStream->u8SD, pSink->pStream->u8Channel));
2818
2819	hdaR3StreamLock(pSink->pStream);
2820
2821	/* Only disable the stream if the stream descriptor # has changed. */
2822	if (pSink->pStream->u8SD != uSD)
2823	hdaR3StreamEnable(pSink->pStream, false);
2824
2825	pSink->pStream->pMixSink = NULL;
2826
2827	hdaR3StreamUnlock(pSink->pStream);
2828
2829	pSink->pStream = NULL;
2830	}
2831
2832	Assert(uSD < HDA_MAX_STREAMS);
2833
2834	/* Attach the new stream to the sink.
2835	* Enabling the stream will be done by the gust via a separate SDnCTL call then. */
2836	if (pSink->pStream == NULL)
2837	{
2838	LogRel2(("HDA: Setting sink '%s' to stream #%RU8 (channel %RU8), mixer control=%s\n",
2839	pSink->pMixSink->pszName, uSD, uChannel, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl)));
2840
2841	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
2842	if (pStream)
2843	{
2844	hdaR3StreamLock(pStream);
2845
2846	pSink->pStream = pStream;
2847
2848	pStream->u8Channel = uChannel;
2849	pStream->pMixSink = pSink;
2850
2851	hdaR3StreamUnlock(pStream);
2852
2853	rc = VINF_SUCCESS;
2854	}
2855	else
2856	rc = VERR_NOT_IMPLEMENTED;
2857	}
2858	}
2859	else
2860	rc = VERR_NOT_FOUND;
2861
2862	if (RT_FAILURE(rc))
2863	LogRel(("HDA: Converter control for stream #%RU8 (channel %RU8) / mixer control '%s' failed with %Rrc, skipping\n",
2864	uSD, uChannel, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl), rc));
2865
2866	LogFlowFuncLeaveRC(rc);
2867	return rc;
2868	}
2869
2870	/**
2871	* @interface_method_impl{HDACODEC,pfnCbMixerSetVolume}
2872	*
2873	* Sets the volume of a specified mixer control.
2874	*
2875	* @return IPRT status code.
2876	* @param pThis HDA State.
2877	* @param enmMixerCtl Mixer control to set volume for.
2878	* @param pVol Pointer to volume data to set.
2879	*
2880	* @remarks Can be called as a callback by the HDA codec.
2881	*/
2882	static DECLCALLBACK(int) hdaR3MixerSetVolume(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOVOLUME pVol)
2883	{
2884	int rc;
2885
2886	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2887	if ( pSink
2888	&& pSink->pMixSink)
2889	{
2890	LogRel2(("HDA: Setting volume for mixer sink '%s' to %RU8/%RU8 (%s)\n",
2891	pSink->pMixSink->pszName, pVol->uLeft, pVol->uRight, pVol->fMuted ? "Muted" : "Unmuted"));
2892
2893	/* Set the volume.
2894	* We assume that the codec already converted it to the correct range. */
2895	rc = AudioMixerSinkSetVolume(pSink->pMixSink, pVol);
2896	}
2897	else
2898	rc = VERR_NOT_FOUND;
2899
2900	LogFlowFuncLeaveRC(rc);
2901	return rc;
2902	}
2903
2904	/**
2905	* Main routine for the stream's timer.
2906	*
2907	* @param pDevIns Device instance.
2908	* @param pTimer Timer this callback was called for.
2909	* @param pvUser Pointer to associated HDASTREAM.
2910	*/
2911	static DECLCALLBACK(void) hdaR3Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2912	{
2913	RT_NOREF(pDevIns, pTimer);
2914
2915	PHDASTREAM pStream = (PHDASTREAM)pvUser;
2916	AssertPtr(pStream);
2917
2918	PHDASTATE pThis = pStream->pHDAState;
2919
2920	DEVHDA_LOCK_BOTH_RETURN_VOID(pStream->pHDAState, pStream->u8SD);
2921
2922	hdaR3StreamUpdate(pStream, true /* fInTimer */);
2923
2924	/* Flag indicating whether to kick the timer again for a new data processing round. */
2925	bool fSinkActive = false;
2926	if (pStream->pMixSink)
2927	fSinkActive = AudioMixerSinkIsActive(pStream->pMixSink->pMixSink);
2928
2929	if (fSinkActive)
2930	{
2931	const bool fTimerScheduled = hdaR3StreamTransferIsScheduled(pStream);
2932	Log3Func(("fSinksActive=%RTbool, fTimerScheduled=%RTbool\n", fSinkActive, fTimerScheduled));
2933	if (!fTimerScheduled)
2934	hdaR3TimerSet(pThis, pStream,
2935	TMTimerGet(pThis->pTimer[pStream->u8SD])
2936	+ TMTimerGetFreq(pThis->pTimer[pStream->u8SD]) / pStream->pHDAState->uTimerHz,
2937	true /* fForce */);
2938	}
2939	else
2940	Log3Func(("fSinksActive=%RTbool\n", fSinkActive));
2941
2942	DEVHDA_UNLOCK_BOTH(pThis, pStream->u8SD);
2943	}
2944
2945	# ifdef HDA_USE_DMA_ACCESS_HANDLER
2946	/**
2947	* HC access handler for the FIFO.
2948	*
2949	* @returns VINF_SUCCESS if the handler have carried out the operation.
2950	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2951	* @param pVM VM Handle.
2952	* @param pVCpu The cross context CPU structure for the calling EMT.
2953	* @param GCPhys The physical address the guest is writing to.
2954	* @param pvPhys The HC mapping of that address.
2955	* @param pvBuf What the guest is reading/writing.
2956	* @param cbBuf How much it's reading/writing.
2957	* @param enmAccessType The access type.
2958	* @param enmOrigin Who is making the access.
2959	* @param pvUser User argument.
2960	*/
2961	static DECLCALLBACK(VBOXSTRICTRC) hdaR3DMAAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys,
2962	void *pvBuf, size_t cbBuf,
2963	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2964	{
2965	RT_NOREF(pVM, pVCpu, pvPhys, pvBuf, enmOrigin);
2966
2967	PHDADMAACCESSHANDLER pHandler = (PHDADMAACCESSHANDLER)pvUser;
2968	AssertPtr(pHandler);
2969
2970	PHDASTREAM pStream = pHandler->pStream;
2971	AssertPtr(pStream);
2972
2973	Assert(GCPhys >= pHandler->GCPhysFirst);
2974	Assert(GCPhys <= pHandler->GCPhysLast);
2975	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
2976
2977	/* Not within BDLE range? Bail out. */
2978	if ( (GCPhys < pHandler->BDLEAddr)
2979	\|\| (GCPhys + cbBuf > pHandler->BDLEAddr + pHandler->BDLESize))
2980	{
2981	return VINF_PGM_HANDLER_DO_DEFAULT;
2982	}
2983
2984	switch(enmAccessType)
2985	{
2986	case PGMACCESSTYPE_WRITE:
2987	{
2988	# ifdef DEBUG
2989	PHDASTREAMDBGINFO pStreamDbg = &pStream->Dbg;
2990
2991	const uint64_t tsNowNs = RTTimeNanoTS();
2992	const uint32_t tsElapsedMs = (tsNowNs - pStreamDbg->tsWriteSlotBegin) / 1000 / 1000;
2993
2994	uint64_t cWritesHz = ASMAtomicReadU64(&pStreamDbg->cWritesHz);
2995	uint64_t cbWrittenHz = ASMAtomicReadU64(&pStreamDbg->cbWrittenHz);
2996
2997	if (tsElapsedMs >= (1000 / HDA_TIMER_HZ_DEFAULT))
2998	{
2999	LogFunc(("[SD%RU8] %RU32ms elapsed, cbWritten=%RU64, cWritten=%RU64 -- %RU32 bytes on average per time slot (%zums)\n",
3000	pStream->u8SD, tsElapsedMs, cbWrittenHz, cWritesHz,
3001	ASMDivU64ByU32RetU32(cbWrittenHz, cWritesHz ? cWritesHz : 1), 1000 / HDA_TIMER_HZ_DEFAULT));
3002
3003	pStreamDbg->tsWriteSlotBegin = tsNowNs;
3004
3005	cWritesHz = 0;
3006	cbWrittenHz = 0;
3007	}
3008
3009	cWritesHz += 1;
3010	cbWrittenHz += cbBuf;
3011
3012	ASMAtomicIncU64(&pStreamDbg->cWritesTotal);
3013	ASMAtomicAddU64(&pStreamDbg->cbWrittenTotal, cbBuf);
3014
3015	ASMAtomicWriteU64(&pStreamDbg->cWritesHz, cWritesHz);
3016	ASMAtomicWriteU64(&pStreamDbg->cbWrittenHz, cbWrittenHz);
3017
3018	LogFunc(("[SD%RU8] Writing %3zu @ 0x%x (off %zu)\n",
3019	pStream->u8SD, cbBuf, GCPhys, GCPhys - pHandler->BDLEAddr));
3020
3021	LogFunc(("[SD%RU8] cWrites=%RU64, cbWritten=%RU64 -> %RU32 bytes on average\n",
3022	pStream->u8SD, pStreamDbg->cWritesTotal, pStreamDbg->cbWrittenTotal,
3023	ASMDivU64ByU32RetU32(pStreamDbg->cbWrittenTotal, pStreamDbg->cWritesTotal)));
3024	# endif
3025
3026	if (pThis->fDebugEnabled)
3027	{
3028	RTFILE fh;
3029	RTFileOpen(&fh, VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH "hdaDMAAccessWrite.pcm",
3030	RTFILE_O_OPEN_CREATE \| RTFILE_O_APPEND \| RTFILE_O_WRITE \| RTFILE_O_DENY_NONE);
3031	RTFileWrite(fh, pvBuf, cbBuf, NULL);
3032	RTFileClose(fh);
3033	}
3034
3035	# ifdef HDA_USE_DMA_ACCESS_HANDLER_WRITING
3036	PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
3037	AssertPtr(pCircBuf);
3038
3039	uint8_t pbBuf = (uint8_t )pvBuf;
3040	while (cbBuf)
3041	{
3042	/* Make sure we only copy as much as the stream's FIFO can hold (SDFIFOS, 18.2.39). */
3043	void *pvChunk;
3044	size_t cbChunk;
3045	RTCircBufAcquireWriteBlock(pCircBuf, cbBuf, &pvChunk, &cbChunk);
3046
3047	if (cbChunk)
3048	{
3049	memcpy(pvChunk, pbBuf, cbChunk);
3050
3051	pbBuf += cbChunk;
3052	Assert(cbBuf >= cbChunk);
3053	cbBuf -= cbChunk;
3054	}
3055	else
3056	{
3057	//AssertMsg(RTCircBufFree(pCircBuf), ("No more space but still %zu bytes to write\n", cbBuf));
3058	break;
3059	}
3060
3061	LogFunc(("[SD%RU8] cbChunk=%zu\n", pStream->u8SD, cbChunk));
3062
3063	RTCircBufReleaseWriteBlock(pCircBuf, cbChunk);
3064	}
3065	# endif /* HDA_USE_DMA_ACCESS_HANDLER_WRITING */
3066	break;
3067	}
3068
3069	default:
3070	AssertMsgFailed(("Access type not implemented\n"));
3071	break;
3072	}
3073
3074	return VINF_PGM_HANDLER_DO_DEFAULT;
3075	}
3076	# endif /* HDA_USE_DMA_ACCESS_HANDLER */
3077
3078	/**
3079	* Soft reset of the device triggered via GCTL.
3080	*
3081	* @param pThis HDA state.
3082	*
3083	*/
3084	static void hdaR3GCTLReset(PHDASTATE pThis)
3085	{
3086	LogFlowFuncEnter();
3087
3088	pThis->cStreamsActive = 0;
3089
3090	HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(HDA_MAX_SDO, HDA_MAX_SDI, 0, 0, 1); /* see 6.2.1 */
3091	HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
3092	HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
3093	HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
3094	HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
3095	HDA_REG(pThis, CORBSIZE) = 0x42; /* Up to 256 CORB entries see 6.2.1 */
3096	HDA_REG(pThis, RIRBSIZE) = 0x42; /* Up to 256 RIRB entries see 6.2.1 */
3097	HDA_REG(pThis, CORBRP) = 0x0;
3098	HDA_REG(pThis, CORBWP) = 0x0;
3099	HDA_REG(pThis, RIRBWP) = 0x0;
3100	/* Some guests (like Haiku) don't set RINTCNT explicitly but expect an interrupt after each
3101	* RIRB response -- so initialize RINTCNT to 1 by default. */
3102	HDA_REG(pThis, RINTCNT) = 0x1;
3103
3104	/*
3105	* Stop any audio currently playing and/or recording.
3106	*/
3107	pThis->SinkFront.pStream = NULL;
3108	if (pThis->SinkFront.pMixSink)
3109	AudioMixerSinkReset(pThis->SinkFront.pMixSink);
3110	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3111	pThis->SinkMicIn.pStream = NULL;
3112	if (pThis->SinkMicIn.pMixSink)
3113	AudioMixerSinkReset(pThis->SinkMicIn.pMixSink);
3114	# endif
3115	pThis->SinkLineIn.pStream = NULL;
3116	if (pThis->SinkLineIn.pMixSink)
3117	AudioMixerSinkReset(pThis->SinkLineIn.pMixSink);
3118	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3119	pThis->SinkCenterLFE = NULL;
3120	if (pThis->SinkCenterLFE.pMixSink)
3121	AudioMixerSinkReset(pThis->SinkCenterLFE.pMixSink);
3122	pThis->SinkRear.pStream = NULL;
3123	if (pThis->SinkRear.pMixSink)
3124	AudioMixerSinkReset(pThis->SinkRear.pMixSink);
3125	# endif
3126
3127	/*
3128	* Reset the codec.
3129	*/
3130	if ( pThis->pCodec
3131	&& pThis->pCodec->pfnReset)
3132	{
3133	pThis->pCodec->pfnReset(pThis->pCodec);
3134	}
3135
3136	/*
3137	* Set some sensible defaults for which HDA sinks
3138	* are connected to which stream number.
3139	*
3140	* We use SD0 for input and SD4 for output by default.
3141	* These stream numbers can be changed by the guest dynamically lateron.
3142	*/
3143	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3144	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_MIC_IN , 1 /* SD0 /, 0 / Channel */);
3145	# endif
3146	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_LINE_IN , 1 /* SD0 /, 0 / Channel */);
3147
3148	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_FRONT , 5 /* SD4 /, 0 / Channel */);
3149	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3150	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_CENTER_LFE, 5 /* SD4 /, 0 / Channel */);
3151	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_REAR , 5 /* SD4 /, 0 / Channel */);
3152	# endif
3153
3154	/* Reset CORB. */
3155	pThis->cbCorbBuf = HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE;
3156	RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
3157
3158	/* Reset RIRB. */
3159	pThis->cbRirbBuf = HDA_RIRB_SIZE * HDA_RIRB_ELEMENT_SIZE;
3160	RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
3161
3162	/* Clear our internal response interrupt counter. */
3163	pThis->u16RespIntCnt = 0;
3164
3165	for (uint8_t uSD = 0; uSD < HDA_MAX_STREAMS; ++uSD)
3166	{
3167	int rc2 = hdaR3StreamEnable(&pThis->aStreams[uSD], false /* fEnable */);
3168	if (RT_SUCCESS(rc2))
3169	{
3170	/* Remove the RUN bit from SDnCTL in case the stream was in a running state before. */
3171	HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_RUN;
3172	hdaR3StreamReset(pThis, &pThis->aStreams[uSD], uSD);
3173	}
3174	}
3175
3176	/* Clear stream tags <-> objects mapping table. */
3177	RT_ZERO(pThis->aTags);
3178
3179	/* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
3180	HDA_REG(pThis, STATESTS) = 0x1;
3181
3182	LogFlowFuncLeave();
3183	LogRel(("HDA: Reset\n"));
3184	}
3185
3186	#endif /* IN_RING3 */
3187
3188	/* MMIO callbacks */
3189
3190	/**
3191	* @callback_method_impl{FNIOMMMIOREAD, Looks up and calls the appropriate handler.}
3192	*
3193	* @note During implementation, we discovered so-called "forgotten" or "hole"
3194	* registers whose description is not listed in the RPM, datasheet, or
3195	* spec.
3196	*/
3197	PDMBOTHCBDECL(int) hdaMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void pv, unsigned cb)
3198	{
3199	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3200	int rc;
3201	RT_NOREF_PV(pvUser);
3202	Assert(pThis->uAlignmentCheckMagic == HDASTATE_ALIGNMENT_CHECK_MAGIC);
3203
3204	/*
3205	* Look up and log.
3206	*/
3207	uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3208	int idxRegDsc = hdaRegLookup(offReg); /* Register descriptor index. */
3209	#ifdef LOG_ENABLED
3210	unsigned const cbLog = cb;
3211	uint32_t offRegLog = offReg;
3212	#endif
3213
3214	Log3Func(("offReg=%#x cb=%#x\n", offReg, cb));
3215	Assert(cb == 4); Assert((offReg & 3) == 0);
3216
3217	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_READ);
3218
3219	if (!(HDA_REG(pThis, GCTL) & HDA_GCTL_CRST) && idxRegDsc != HDA_REG_GCTL)
3220	LogFunc(("Access to registers except GCTL is blocked while reset\n"));
3221
3222	if (idxRegDsc == -1)
3223	LogRel(("HDA: Invalid read access @0x%x (bytes=%u)\n", offReg, cb));
3224
3225	if (idxRegDsc != -1)
3226	{
3227	/* Leave lock before calling read function. */
3228	DEVHDA_UNLOCK(pThis);
3229
3230	/* ASSUMES gapless DWORD at end of map. */
3231	if (g_aHdaRegMap[idxRegDsc].size == 4)
3232	{
3233	/*
3234	* Straight forward DWORD access.
3235	*/
3236	rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, (uint32_t *)pv);
3237	Log3Func(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, (uint32_t )pv, rc));
3238	}
3239	else
3240	{
3241	/*
3242	* Multi register read (unless there are trailing gaps).
3243	* ASSUMES that only DWORD reads have sideeffects.
3244	*/
3245	#ifdef IN_RING3
3246	uint32_t u32Value = 0;
3247	unsigned cbLeft = 4;
3248	do
3249	{
3250	uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
3251	uint32_t u32Tmp = 0;
3252
3253	rc = g_aHdaRegMap[idxRegDsc].pfnRead(pThis, idxRegDsc, &u32Tmp);
3254	Log3Func(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
3255	if (rc != VINF_SUCCESS)
3256	break;
3257	u32Value \|= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
3258
3259	cbLeft -= cbReg;
3260	offReg += cbReg;
3261	idxRegDsc++;
3262	} while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == offReg);
3263
3264	if (rc == VINF_SUCCESS)
3265	(uint32_t )pv = u32Value;
3266	else
3267	Assert(!IOM_SUCCESS(rc));
3268	#else /* !IN_RING3 */
3269	/* Take the easy way out. */
3270	rc = VINF_IOM_R3_MMIO_READ;
3271	#endif /* !IN_RING3 */
3272	}
3273	}
3274	else
3275	{
3276	DEVHDA_UNLOCK(pThis);
3277
3278	rc = VINF_IOM_MMIO_UNUSED_FF;
3279	Log3Func(("\tHole at %x is accessed for read\n", offReg));
3280	}
3281
3282	/*
3283	* Log the outcome.
3284	*/
3285	#ifdef LOG_ENABLED
3286	if (cbLog == 4)
3287	Log3Func(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, (uint32_t )pv, rc));
3288	else if (cbLog == 2)
3289	Log3Func(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, (uint16_t )pv, rc));
3290	else if (cbLog == 1)
3291	Log3Func(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, (uint8_t )pv, rc));
3292	#endif
3293	return rc;
3294	}
3295
3296
3297	DECLINLINE(int) hdaWriteReg(PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
3298	{
3299	DEVHDA_LOCK_RETURN(pThis, VINF_IOM_R3_MMIO_WRITE);
3300
3301	if (!(HDA_REG(pThis, GCTL) & HDA_GCTL_CRST) && idxRegDsc != HDA_REG_GCTL)
3302	{
3303	Log(("hdaWriteReg: Warning: Access to %s is blocked while controller is in reset mode\n", g_aHdaRegMap[idxRegDsc].abbrev));
3304	LogRel2(("HDA: Warning: Access to register %s is blocked while controller is in reset mode\n",
3305	g_aHdaRegMap[idxRegDsc].abbrev));
3306
3307	DEVHDA_UNLOCK(pThis);
3308	return VINF_SUCCESS;
3309	}
3310
3311	/*
3312	* Handle RD (register description) flags.
3313	*/
3314
3315	/* For SDI / SDO: Check if writes to those registers are allowed while SDCTL's RUN bit is set. */
3316	if (idxRegDsc >= HDA_NUM_GENERAL_REGS)
3317	{
3318	const uint32_t uSDCTL = HDA_STREAM_REG(pThis, CTL, HDA_SD_NUM_FROM_REG(pThis, CTL, idxRegDsc));
3319
3320	/*
3321	* Some OSes (like Win 10 AU) violate the spec by writing stuff to registers which are not supposed to be be touched
3322	* while SDCTL's RUN bit is set. So just ignore those values.
3323	*/
3324
3325	/* Is the RUN bit currently set? */
3326	if ( RT_BOOL(uSDCTL & HDA_SDCTL_RUN)
3327	/* Are writes to the register denied if RUN bit is set? */
3328	&& !(g_aHdaRegMap[idxRegDsc].fFlags & HDA_RD_FLAG_SD_WRITE_RUN))
3329	{
3330	Log(("hdaWriteReg: Warning: Access to %s is blocked! %R[sdctl]\n", g_aHdaRegMap[idxRegDsc].abbrev, uSDCTL));
3331	LogRel2(("HDA: Warning: Access to register %s is blocked while the stream's RUN bit is set\n",
3332	g_aHdaRegMap[idxRegDsc].abbrev));
3333
3334	DEVHDA_UNLOCK(pThis);
3335	return VINF_SUCCESS;
3336	}
3337	}
3338
3339	/* Leave the lock before calling write function. */
3340	/** @todo r=bird: Why do we need to do that?? There is no
3341	* explanation why this is necessary here...
3342	*
3343	* More or less all write functions retake the lock, so why not let
3344	* those who need to drop the lock or take additional locks release
3345	* it? See, releasing a lock you already got always runs the risk
3346	* of someone else grabbing it and forcing you to wait, better to
3347	* do the two-three things a write handle needs to do than enter
3348	* and exit the lock all the time. */
3349	DEVHDA_UNLOCK(pThis);
3350
3351	#ifdef LOG_ENABLED
3352	uint32_t const idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3353	uint32_t const u32OldValue = pThis->au32Regs[idxRegMem];
3354	#endif
3355	int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pThis, idxRegDsc, u32Value);
3356	Log3Func(("Written value %#x to %s[%d byte]; %x => %x%s, rc=%d\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
3357	g_aHdaRegMap[idxRegDsc].size, u32OldValue, pThis->au32Regs[idxRegMem], pszLog, rc));
3358	RT_NOREF(pszLog);
3359	return rc;
3360	}
3361
3362
3363	/**
3364	* @callback_method_impl{FNIOMMMIOWRITE, Looks up and calls the appropriate handler.}
3365	*/
3366	PDMBOTHCBDECL(int) hdaMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS GCPhysAddr, void const pv, unsigned cb)
3367	{
3368	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3369	int rc;
3370	RT_NOREF_PV(pvUser);
3371	Assert(pThis->uAlignmentCheckMagic == HDASTATE_ALIGNMENT_CHECK_MAGIC);
3372
3373	/*
3374	* The behavior of accesses that aren't aligned on natural boundraries is
3375	* undefined. Just reject them outright.
3376	*/
3377	/** @todo IOM could check this, it could also split the 8 byte accesses for us. */
3378	Assert(cb == 1 \|\| cb == 2 \|\| cb == 4 \|\| cb == 8);
3379	if (GCPhysAddr & (cb - 1))
3380	return PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: GCPhysAddr=%RGp cb=%u\n", GCPhysAddr, cb);
3381
3382	/*
3383	* Look up and log the access.
3384	*/
3385	uint32_t offReg = GCPhysAddr - pThis->MMIOBaseAddr;
3386	int idxRegDsc = hdaRegLookup(offReg);
3387	#if defined(IN_RING3) \|\| defined(LOG_ENABLED)
3388	uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
3389	#endif
3390	uint64_t u64Value;
3391	if (cb == 4) u64Value = (uint32_t const )pv;
3392	else if (cb == 2) u64Value = (uint16_t const )pv;
3393	else if (cb == 1) u64Value = (uint8_t const )pv;
3394	else if (cb == 8) u64Value = (uint64_t const )pv;
3395	else
3396	{
3397	u64Value = 0; /* shut up gcc. */
3398	AssertReleaseMsgFailed(("%u\n", cb));
3399	}
3400
3401	#ifdef LOG_ENABLED
3402	uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
3403	if (idxRegDsc == -1)
3404	Log3Func(("@%#05x u32=%#010x cb=%d\n", offReg, (uint32_t const )pv, cb));
3405	else if (cb == 4)
3406	Log3Func(("@%#05x u32=%#010x %s\n", offReg, (uint32_t )pv, g_aHdaRegMap[idxRegDsc].abbrev));
3407	else if (cb == 2)
3408	Log3Func(("@%#05x u16=%#06x (%#010x) %s\n", offReg, (uint16_t )pv, (uint32_t )pv, g_aHdaRegMap[idxRegDsc].abbrev));
3409	else if (cb == 1)
3410	Log3Func(("@%#05x u8=%#04x (%#010x) %s\n", offReg, (uint8_t )pv, (uint32_t )pv, g_aHdaRegMap[idxRegDsc].abbrev));
3411
3412	if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
3413	Log3Func(("\tsize=%RU32 != cb=%u!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
3414	#endif
3415
3416	/*
3417	* Try for a direct hit first.
3418	*/
3419	if (idxRegDsc != -1 && g_aHdaRegMap[idxRegDsc].size == cb)
3420	{
3421	rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "");
3422	Log3Func(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
3423	}
3424	/*
3425	* Partial or multiple register access, loop thru the requested memory.
3426	*/
3427	else
3428	{
3429	#ifdef IN_RING3
3430	/*
3431	* If it's an access beyond the start of the register, shift the input
3432	* value and fill in missing bits. Natural alignment rules means we
3433	* will only see 1 or 2 byte accesses of this kind, so no risk of
3434	* shifting out input values.
3435	*/
3436	if (idxRegDsc == -1 && (idxRegDsc = hdaR3RegLookupWithin(offReg)) != -1)
3437	{
3438	uint32_t const cbBefore = offReg - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
3439	offReg -= cbBefore;
3440	idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3441	u64Value <<= cbBefore * 8;
3442	u64Value \|= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
3443	Log3Func(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
3444	cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
3445	}
3446
3447	/* Loop thru the write area, it may cover multiple registers. */
3448	rc = VINF_SUCCESS;
3449	for (;;)
3450	{
3451	uint32_t cbReg;
3452	if (idxRegDsc != -1)
3453	{
3454	idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3455	cbReg = g_aHdaRegMap[idxRegDsc].size;
3456	if (cb < cbReg)
3457	{
3458	u64Value \|= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
3459	Log3Func(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
3460	g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
3461	}
3462	# ifdef LOG_ENABLED
3463	uint32_t uLogOldVal = pThis->au32Regs[idxRegMem];
3464	# endif
3465	rc = hdaWriteReg(pThis, idxRegDsc, u64Value, "*");
3466	Log3Func(("\t%#x -> %#x\n", uLogOldVal, pThis->au32Regs[idxRegMem]));
3467	}
3468	else
3469	{
3470	LogRel(("HDA: Invalid write access @0x%x\n", offReg));
3471	cbReg = 1;
3472	}
3473	if (rc != VINF_SUCCESS)
3474	break;
3475	if (cbReg >= cb)
3476	break;
3477
3478	/* Advance. */
3479	offReg += cbReg;
3480	cb -= cbReg;
3481	u64Value >>= cbReg * 8;
3482	if (idxRegDsc == -1)
3483	idxRegDsc = hdaRegLookup(offReg);
3484	else
3485	{
3486	idxRegDsc++;
3487	if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
3488	\|\| g_aHdaRegMap[idxRegDsc].offset != offReg)
3489	{
3490	idxRegDsc = -1;
3491	}
3492	}
3493	}
3494
3495	#else /* !IN_RING3 */
3496	/* Take the simple way out. */
3497	rc = VINF_IOM_R3_MMIO_WRITE;
3498	#endif /* !IN_RING3 */
3499	}
3500
3501	return rc;
3502	}
3503
3504
3505	/* PCI callback. */
3506
3507	#ifdef IN_RING3
3508	/**
3509	* @callback_method_impl{FNPCIIOREGIONMAP}
3510	*/
3511	static DECLCALLBACK(int) hdaR3PciIoRegionMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
3512	RTGCPHYS GCPhysAddress, RTGCPHYS cb, PCIADDRESSSPACE enmType)
3513	{
3514	RT_NOREF(iRegion, enmType);
3515	PHDASTATE pThis = RT_FROM_MEMBER(pPciDev, HDASTATE, PciDev);
3516
3517	/*
3518	* 18.2 of the ICH6 datasheet defines the valid access widths as byte, word, and double word.
3519	*
3520	* Let IOM talk DWORDs when reading, saves a lot of complications. On
3521	* writing though, we have to do it all ourselves because of sideeffects.
3522	*/
3523	Assert(enmType == PCI_ADDRESS_SPACE_MEM);
3524	int rc = PDMDevHlpMMIORegister(pDevIns, GCPhysAddress, cb, NULL /pvUser/,
3525	IOMMMIO_FLAGS_READ_DWORD
3526	\| IOMMMIO_FLAGS_WRITE_PASSTHRU,
3527	hdaMMIOWrite, hdaMMIORead, "HDA");
3528
3529	if (RT_FAILURE(rc))
3530	return rc;
3531
3532	if (pThis->fRZEnabled)
3533	{
3534	rc = PDMDevHlpMMIORegisterR0(pDevIns, GCPhysAddress, cb, NIL_RTR0PTR /pvUser/,
3535	"hdaMMIOWrite", "hdaMMIORead");
3536	if (RT_FAILURE(rc))
3537	return rc;
3538
3539	rc = PDMDevHlpMMIORegisterRC(pDevIns, GCPhysAddress, cb, NIL_RTRCPTR /pvUser/,
3540	"hdaMMIOWrite", "hdaMMIORead");
3541	if (RT_FAILURE(rc))
3542	return rc;
3543	}
3544
3545	pThis->MMIOBaseAddr = GCPhysAddress;
3546	return VINF_SUCCESS;
3547	}
3548
3549
3550	/* Saved state workers and callbacks. */
3551
3552	static int hdaR3SaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStream)
3553	{
3554	RT_NOREF(pDevIns);
3555	#if defined(VBOX_STRICT) \|\| defined(LOG_ENABLED)
3556	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3557	#endif
3558
3559	Log2Func(("[SD%RU8]\n", pStream->u8SD));
3560
3561	/* Save stream ID. */
3562	int rc = SSMR3PutU8(pSSM, pStream->u8SD);
3563	AssertRCReturn(rc, rc);
3564	Assert(pStream->u8SD < HDA_MAX_STREAMS);
3565
3566	rc = SSMR3PutStructEx(pSSM, &pStream->State, sizeof(HDASTREAMSTATE), 0 /fFlags/, g_aSSMStreamStateFields7, NULL);
3567	AssertRCReturn(rc, rc);
3568
3569	#ifdef VBOX_STRICT
3570	uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, pStream->u8SD),
3571	HDA_STREAM_REG(pThis, BDPU, pStream->u8SD));
3572	uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, pStream->u8SD);
3573	uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, pStream->u8SD);
3574
3575	Assert(u64BaseDMA == pStream->u64BDLBase);
3576	Assert(u16LVI == pStream->u16LVI);
3577	Assert(u32CBL == pStream->u32CBL);
3578	#endif
3579
3580	rc = SSMR3PutStructEx(pSSM, &pStream->State.BDLE.Desc, sizeof(HDABDLEDESC),
3581	0 /fFlags/, g_aSSMBDLEDescFields7, NULL);
3582	AssertRCReturn(rc, rc);
3583
3584	rc = SSMR3PutStructEx(pSSM, &pStream->State.BDLE.State, sizeof(HDABDLESTATE),
3585	0 /fFlags/, g_aSSMBDLEStateFields7, NULL);
3586	AssertRCReturn(rc, rc);
3587
3588	rc = SSMR3PutStructEx(pSSM, &pStream->State.Period, sizeof(HDASTREAMPERIOD),
3589	0 /* fFlags */, g_aSSMStreamPeriodFields7, NULL);
3590	AssertRCReturn(rc, rc);
3591
3592	#ifdef VBOX_STRICT /* Sanity checks. */
3593	PHDABDLE pBDLE = &pStream->State.BDLE;
3594	if (u64BaseDMA)
3595	{
3596	Assert(pStream->State.uCurBDLE <= u16LVI + 1);
3597
3598	HDABDLE curBDLE;
3599	rc = hdaR3BDLEFetch(pThis, &curBDLE, u64BaseDMA, pStream->State.uCurBDLE);
3600	AssertRC(rc);
3601
3602	Assert(curBDLE.Desc.u32BufSize == pBDLE->Desc.u32BufSize);
3603	Assert(curBDLE.Desc.u64BufAddr == pBDLE->Desc.u64BufAddr);
3604	Assert(curBDLE.Desc.fFlags == pBDLE->Desc.fFlags);
3605	}
3606	else
3607	{
3608	Assert(pBDLE->Desc.u64BufAddr == 0);
3609	Assert(pBDLE->Desc.u32BufSize == 0);
3610	}
3611	#endif
3612
3613	uint32_t cbCircBufSize = 0;
3614	uint32_t cbCircBufUsed = 0;
3615
3616	if (pStream->State.pCircBuf)
3617	{
3618	cbCircBufSize = (uint32_t)RTCircBufSize(pStream->State.pCircBuf);
3619	cbCircBufUsed = (uint32_t)RTCircBufUsed(pStream->State.pCircBuf);
3620	}
3621
3622	rc = SSMR3PutU32(pSSM, cbCircBufSize);
3623	AssertRCReturn(rc, rc);
3624
3625	rc = SSMR3PutU32(pSSM, cbCircBufUsed);
3626	AssertRCReturn(rc, rc);
3627
3628	if (cbCircBufUsed)
3629	{
3630	/*
3631	* We now need to get the circular buffer's data without actually modifying
3632	* the internal read / used offsets -- otherwise we would end up with broken audio
3633	* data after saving the state.
3634	*
3635	* So get the current read offset and serialize the buffer data manually based on that.
3636	*/
3637	size_t const offBuf = RTCircBufOffsetRead(pStream->State.pCircBuf);
3638	void *pvBuf;
3639	size_t cbBuf;
3640	RTCircBufAcquireReadBlock(pStream->State.pCircBuf, cbCircBufUsed, &pvBuf, &cbBuf);
3641	#if 0 /** @todo r=bird: The disabled code crashes on me. The #else case contains something that seems
3642	* to make more sense to me. I'm not saying this is necessarily correct, so please review, fix, and remove. */
3643
3644	if (cbBuf)
3645	{
3646	size_t cbToRead = cbCircBufUsed;
3647	size_t cbEnd = 0;
3648
3649	if (cbCircBufUsed > offBuf)
3650	cbEnd = cbCircBufUsed - offBuf;
3651
3652	if (cbEnd) /* Save end of buffer first. */
3653	{
3654	rc = SSMR3PutMem(pSSM, (uint8_t )pvBuf + cbCircBufSize - cbEnd / End of buffer */, cbEnd);
3655	AssertRCReturn(rc, rc);
3656
3657	Assert(cbToRead >= cbEnd);
3658	cbToRead -= cbEnd;
3659	}
3660
3661	if (cbToRead) /* Save remaining stuff at start of buffer (if any). */
3662	{
3663	rc = SSMR3PutMem(pSSM, (uint8_t )pvBuf - cbCircBufUsed / Start of buffer */, cbToRead);
3664	AssertRCReturn(rc, rc);
3665	}
3666	}
3667
3668	#else
3669	Assert(cbBuf);
3670	rc = SSMR3PutMem(pSSM, pvBuf, cbBuf);
3671	if (cbBuf < cbCircBufUsed)
3672	rc = SSMR3PutMem(pSSM, (uint8_t *)pvBuf - offBuf, cbCircBufUsed - cbBuf);
3673	#endif
3674	RTCircBufReleaseReadBlock(pStream->State.pCircBuf, 0 /* Don't advance read pointer -- see comment above */);
3675	}
3676
3677	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n",
3678	pStream->u8SD,
3679	HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), HDA_STREAM_REG(pThis, CBL, pStream->u8SD), HDA_STREAM_REG(pThis, LVI, pStream->u8SD)));
3680
3681	#ifdef LOG_ENABLED
3682	hdaR3BDLEDumpAll(pThis, pStream->u64BDLBase, pStream->u16LVI + 1);
3683	#endif
3684
3685	return rc;
3686	}
3687
3688	/**
3689	* @callback_method_impl{FNSSMDEVSAVEEXEC}
3690	*/
3691	static DECLCALLBACK(int) hdaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3692	{
3693	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
3694
3695	/* Save Codec nodes states. */
3696	hdaCodecSaveState(pThis->pCodec, pSSM);
3697
3698	/* Save MMIO registers. */
3699	SSMR3PutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3700	SSMR3PutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3701
3702	/* Save controller-specifc internals. */
3703	SSMR3PutU64(pSSM, pThis->u64WalClk);
3704	SSMR3PutU8(pSSM, pThis->u8IRQL);
3705
3706	/* Save number of streams. */
3707	SSMR3PutU32(pSSM, HDA_MAX_STREAMS);
3708
3709	/* Save stream states. */
3710	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
3711	{
3712	int rc = hdaR3SaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
3713	AssertRCReturn(rc, rc);
3714	}
3715
3716	return VINF_SUCCESS;
3717	}
3718
3719	/**
3720	* Does required post processing when loading a saved state.
3721	*
3722	* @param pThis Pointer to HDA state.
3723	*/
3724	static int hdaR3LoadExecPost(PHDASTATE pThis)
3725	{
3726	int rc = VINF_SUCCESS;
3727
3728	/*
3729	* Enable all previously active streams.
3730	*/
3731	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
3732	{
3733	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, i);
3734	if (pStream)
3735	{
3736	int rc2;
3737
3738	bool fActive = RT_BOOL(HDA_STREAM_REG(pThis, CTL, i) & HDA_SDCTL_RUN);
3739	if (fActive)
3740	{
3741	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
3742	/* Make sure to also create the async I/O thread before actually enabling the stream. */
3743	rc2 = hdaR3StreamAsyncIOCreate(pStream);
3744	AssertRC(rc2);
3745
3746	/* ... and enabling it. */
3747	hdaR3StreamAsyncIOEnable(pStream, true /* fEnable */);
3748	#endif
3749	/* Resume the stream's period. */
3750	hdaR3StreamPeriodResume(&pStream->State.Period);
3751
3752	/* (Re-)enable the stream. */
3753	rc2 = hdaR3StreamEnable(pStream, true /* fEnable */);
3754	AssertRC(rc2);
3755
3756	/* Add the stream to the device setup. */
3757	rc2 = hdaR3AddStream(pThis, &pStream->State.Cfg);
3758	AssertRC(rc2);
3759
3760	#ifdef HDA_USE_DMA_ACCESS_HANDLER
3761	/* (Re-)install the DMA handler. */
3762	hdaR3StreamRegisterDMAHandlers(pThis, pStream);
3763	#endif
3764	if (hdaR3StreamTransferIsScheduled(pStream))
3765	hdaR3TimerSet(pThis, pStream, hdaR3StreamTransferGetNext(pStream), true /* fForce */);
3766
3767	/* Also keep track of the currently active streams. */
3768	pThis->cStreamsActive++;
3769	}
3770	}
3771	}
3772
3773	LogFlowFuncLeaveRC(rc);
3774	return rc;
3775	}
3776
3777
3778	/**
3779	* Handles loading of all saved state versions older than the current one.
3780	*
3781	* @param pThis Pointer to HDA state.
3782	* @param pSSM Pointer to SSM handle.
3783	* @param uVersion Saved state version to load.
3784	* @param uPass Loading stage to handle.
3785	*/
3786	static int hdaR3LoadExecLegacy(PHDASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3787	{
3788	RT_NOREF(uPass);
3789
3790	int rc = VINF_SUCCESS;
3791
3792	/*
3793	* Load MMIO registers.
3794	*/
3795	uint32_t cRegs;
3796	switch (uVersion)
3797	{
3798	case HDA_SSM_VERSION_1:
3799	/* Starting with r71199, we would save 112 instead of 113
3800	registers due to some code cleanups. This only affected trunk
3801	builds in the 4.1 development period. */
3802	cRegs = 113;
3803	if (SSMR3HandleRevision(pSSM) >= 71199)
3804	{
3805	uint32_t uVer = SSMR3HandleVersion(pSSM);
3806	if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3807	&& VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3808	&& VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3809	cRegs = 112;
3810	}
3811	break;
3812
3813	case HDA_SSM_VERSION_2:
3814	case HDA_SSM_VERSION_3:
3815	cRegs = 112;
3816	AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= 112);
3817	break;
3818
3819	/* Since version 4 we store the register count to stay flexible. */
3820	case HDA_SSM_VERSION_4:
3821	case HDA_SSM_VERSION_5:
3822	case HDA_SSM_VERSION_6:
3823	rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3824	if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3825	LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3826	break;
3827
3828	default:
3829	LogRel(("HDA: Warning: Unsupported / too new saved state version (%RU32)\n", uVersion));
3830	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3831	}
3832
3833	if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3834	{
3835	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3836	SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3837	}
3838	else
3839	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3840
3841	/* Make sure to update the base addresses first before initializing any streams down below. */
3842	pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3843	pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3844	pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE) & DPBASE_ADDR_MASK, HDA_REG(pThis, DPUBASE));
3845
3846	/* Also make sure to update the DMA position bit if this was enabled when saving the state. */
3847	pThis->fDMAPosition = RT_BOOL(HDA_REG(pThis, DPLBASE) & RT_BIT_32(0));
3848
3849	/*
3850	* Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
3851	* every BDLE state, whereas it only needs to be stored
3852	* once for every stream. Most of the BDLE state we can
3853	* get out of the registers anyway, so just ignore those values.
3854	*
3855	* Also, only the current BDLE was saved, regardless whether
3856	* there were more than one (and there are at least two entries,
3857	* according to the spec).
3858	*/
3859	#define HDA_SSM_LOAD_BDLE_STATE_PRE_V5(v, x) \
3860	{ \
3861	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */ \
3862	AssertRCReturn(rc, rc); \
3863	rc = SSMR3GetU64(pSSM, &x.Desc.u64BufAddr); /* u64BdleCviAddr */ \
3864	AssertRCReturn(rc, rc); \
3865	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* u32BdleMaxCvi */ \
3866	AssertRCReturn(rc, rc); \
3867	rc = SSMR3GetU32(pSSM, &x.State.u32BDLIndex); /* u32BdleCvi */ \
3868	AssertRCReturn(rc, rc); \
3869	rc = SSMR3GetU32(pSSM, &x.Desc.u32BufSize); /* u32BdleCviLen */ \
3870	AssertRCReturn(rc, rc); \
3871	rc = SSMR3GetU32(pSSM, &x.State.u32BufOff); /* u32BdleCviPos */ \
3872	AssertRCReturn(rc, rc); \
3873	bool fIOC; \
3874	rc = SSMR3GetBool(pSSM, &fIOC); /* fBdleCviIoc */ \
3875	AssertRCReturn(rc, rc); \
3876	x.Desc.fFlags = fIOC ? HDA_BDLE_FLAG_IOC : 0; \
3877	rc = SSMR3GetU32(pSSM, &x.State.cbBelowFIFOW); /* cbUnderFifoW */ \
3878	AssertRCReturn(rc, rc); \
3879	rc = SSMR3Skip(pSSM, sizeof(uint8_t) * 256); /* FIFO */ \
3880	AssertRCReturn(rc, rc); \
3881	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */ \
3882	AssertRCReturn(rc, rc); \
3883	}
3884
3885	/*
3886	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3887	*/
3888	switch (uVersion)
3889	{
3890	case HDA_SSM_VERSION_1:
3891	case HDA_SSM_VERSION_2:
3892	case HDA_SSM_VERSION_3:
3893	case HDA_SSM_VERSION_4:
3894	{
3895	/* Only load the internal states.
3896	* The rest will be initialized from the saved registers later. */
3897
3898	/* Note 1: Only the current BDLE for a stream was saved! */
3899	/* Note 2: The stream's saving order is/was fixed, so don't touch! */
3900
3901	/* Output */
3902	PHDASTREAM pStream = &pThis->aStreams[4];
3903	rc = hdaR3StreamInit(pStream, 4 /* Stream descriptor, hardcoded */);
3904	if (RT_FAILURE(rc))
3905	break;
3906	HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
3907	pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
3908
3909	/* Microphone-In */
3910	pStream = &pThis->aStreams[2];
3911	rc = hdaR3StreamInit(pStream, 2 /* Stream descriptor, hardcoded */);
3912	if (RT_FAILURE(rc))
3913	break;
3914	HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
3915	pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
3916
3917	/* Line-In */
3918	pStream = &pThis->aStreams[0];
3919	rc = hdaR3StreamInit(pStream, 0 /* Stream descriptor, hardcoded */);
3920	if (RT_FAILURE(rc))
3921	break;
3922	HDA_SSM_LOAD_BDLE_STATE_PRE_V5(uVersion, pStream->State.BDLE);
3923	pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
3924	break;
3925	}
3926
3927	#undef HDA_SSM_LOAD_BDLE_STATE_PRE_V5
3928
3929	default: /* Since v5 we support flexible stream and BDLE counts. */
3930	{
3931	uint32_t cStreams;
3932	rc = SSMR3GetU32(pSSM, &cStreams);
3933	if (RT_FAILURE(rc))
3934	break;
3935
3936	if (cStreams > HDA_MAX_STREAMS)
3937	cStreams = HDA_MAX_STREAMS; /* Sanity. */
3938
3939	/* Load stream states. */
3940	for (uint32_t i = 0; i < cStreams; i++)
3941	{
3942	uint8_t uStreamID;
3943	rc = SSMR3GetU8(pSSM, &uStreamID);
3944	if (RT_FAILURE(rc))
3945	break;
3946
3947	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uStreamID);
3948	HDASTREAM StreamDummy;
3949
3950	if (!pStream)
3951	{
3952	pStream = &StreamDummy;
3953	LogRel2(("HDA: Warning: Stream ID=%RU32 not supported, skipping to load ...\n", uStreamID));
3954	}
3955
3956	rc = hdaR3StreamInit(pStream, uStreamID);
3957	if (RT_FAILURE(rc))
3958	{
3959	LogRel(("HDA: Stream #%RU32: Initialization of stream %RU8 failed, rc=%Rrc\n", i, uStreamID, rc));
3960	break;
3961	}
3962
3963	/*
3964	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3965	*/
3966
3967	if (uVersion == HDA_SSM_VERSION_5)
3968	{
3969	/* Get the current BDLE entry and skip the rest. */
3970	uint16_t cBDLE;
3971
3972	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
3973	AssertRC(rc);
3974	rc = SSMR3GetU16(pSSM, &cBDLE); /* cBDLE */
3975	AssertRC(rc);
3976	rc = SSMR3GetU16(pSSM, &pStream->State.uCurBDLE); /* uCurBDLE */
3977	AssertRC(rc);
3978	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
3979	AssertRC(rc);
3980
3981	uint32_t u32BDLEIndex;
3982	for (uint16_t a = 0; a < cBDLE; a++)
3983	{
3984	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* Begin marker */
3985	AssertRC(rc);
3986	rc = SSMR3GetU32(pSSM, &u32BDLEIndex); /* u32BDLIndex */
3987	AssertRC(rc);
3988
3989	/* Does the current BDLE index match the current BDLE to process? */
3990	if (u32BDLEIndex == pStream->State.uCurBDLE)
3991	{
3992	rc = SSMR3GetU32(pSSM, &pStream->State.BDLE.State.cbBelowFIFOW); /* cbBelowFIFOW */
3993	AssertRC(rc);
3994	rc = SSMR3Skip(pSSM, sizeof(uint8_t) * 256); /* FIFO, deprecated */
3995	AssertRC(rc);
3996	rc = SSMR3GetU32(pSSM, &pStream->State.BDLE.State.u32BufOff); /* u32BufOff */
3997	AssertRC(rc);
3998	rc = SSMR3Skip(pSSM, sizeof(uint32_t)); /* End marker */
3999	AssertRC(rc);
4000	}
4001	else /* Skip not current BDLEs. */
4002	{
4003	rc = SSMR3Skip(pSSM, sizeof(uint32_t) /* cbBelowFIFOW */
4004	+ sizeof(uint8_t) * 256 /* au8FIFO */
4005	+ sizeof(uint32_t) /* u32BufOff */
4006	+ sizeof(uint32_t)); /* End marker */
4007	AssertRC(rc);
4008	}
4009	}
4010	}
4011	else
4012	{
4013	rc = SSMR3GetStructEx(pSSM, &pStream->State, sizeof(HDASTREAMSTATE),
4014	0 /* fFlags */, g_aSSMStreamStateFields6, NULL);
4015	if (RT_FAILURE(rc))
4016	break;
4017
4018	/* Get HDABDLEDESC. */
4019	uint32_t uMarker;
4020	rc = SSMR3GetU32(pSSM, &uMarker); /* Begin marker. */
4021	AssertRC(rc);
4022	Assert(uMarker == UINT32_C(0x19200102) /* SSMR3STRUCT_BEGIN */);
4023	rc = SSMR3GetU64(pSSM, &pStream->State.BDLE.Desc.u64BufAddr);
4024	AssertRC(rc);
4025	rc = SSMR3GetU32(pSSM, &pStream->State.BDLE.Desc.u32BufSize);
4026	AssertRC(rc);
4027	bool fFlags = false;
4028	rc = SSMR3GetBool(pSSM, &fFlags); /* Saved states < v7 only stored the IOC as boolean flag. */
4029	AssertRC(rc);
4030	pStream->State.BDLE.Desc.fFlags = fFlags ? HDA_BDLE_FLAG_IOC : 0;
4031	rc = SSMR3GetU32(pSSM, &uMarker); /* End marker. */
4032	AssertRC(rc);
4033	Assert(uMarker == UINT32_C(0x19920406) /* SSMR3STRUCT_END */);
4034
4035	rc = SSMR3GetStructEx(pSSM, &pStream->State.BDLE.State, sizeof(HDABDLESTATE),
4036	0 /* fFlags */, g_aSSMBDLEStateFields6, NULL);
4037	if (RT_FAILURE(rc))
4038	break;
4039
4040	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n",
4041	uStreamID,
4042	HDA_STREAM_REG(pThis, LPIB, uStreamID), HDA_STREAM_REG(pThis, CBL, uStreamID), HDA_STREAM_REG(pThis, LVI, uStreamID)));
4043	#ifdef LOG_ENABLED
4044	hdaR3BDLEDumpAll(pThis, pStream->u64BDLBase, pStream->u16LVI + 1);
4045	#endif
4046	}
4047
4048	} /* for cStreams */
4049	break;
4050	} /* default */
4051	}
4052
4053	return rc;
4054	}
4055
4056	/**
4057	* @callback_method_impl{FNSSMDEVLOADEXEC}
4058	*/
4059	static DECLCALLBACK(int) hdaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
4060	{
4061	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4062
4063	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
4064
4065	LogRel2(("hdaR3LoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
4066
4067	/*
4068	* Load Codec nodes states.
4069	*/
4070	int rc = hdaCodecLoadState(pThis->pCodec, pSSM, uVersion);
4071	if (RT_FAILURE(rc))
4072	{
4073	LogRel(("HDA: Failed loading codec state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
4074	return rc;
4075	}
4076
4077	if (uVersion < HDA_SSM_VERSION) /* Handle older saved states? */
4078	{
4079	rc = hdaR3LoadExecLegacy(pThis, pSSM, uVersion, uPass);
4080	if (RT_SUCCESS(rc))
4081	rc = hdaR3LoadExecPost(pThis);
4082
4083	return rc;
4084	}
4085
4086	/*
4087	* Load MMIO registers.
4088	*/
4089	uint32_t cRegs;
4090	rc = SSMR3GetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
4091	if (cRegs != RT_ELEMENTS(pThis->au32Regs))
4092	LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
4093
4094	if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
4095	{
4096	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
4097	SSMR3Skip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
4098	}
4099	else
4100	SSMR3GetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
4101
4102	/* Make sure to update the base addresses first before initializing any streams down below. */
4103	pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
4104	pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
4105	pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE) & DPBASE_ADDR_MASK, HDA_REG(pThis, DPUBASE));
4106
4107	/* Also make sure to update the DMA position bit if this was enabled when saving the state. */
4108	pThis->fDMAPosition = RT_BOOL(HDA_REG(pThis, DPLBASE) & RT_BIT_32(0));
4109
4110	/*
4111	* Load controller-specifc internals.
4112	* Don't annoy other team mates (forgot this for state v7).
4113	*/
4114	if ( SSMR3HandleRevision(pSSM) >= 116273
4115	\|\| SSMR3HandleVersion(pSSM) >= VBOX_FULL_VERSION_MAKE(5, 2, 0))
4116	{
4117	rc = SSMR3GetU64(pSSM, &pThis->u64WalClk);
4118	AssertRC(rc);
4119
4120	rc = SSMR3GetU8(pSSM, &pThis->u8IRQL);
4121	AssertRC(rc);
4122	}
4123
4124	/*
4125	* Load streams.
4126	*/
4127	uint32_t cStreams;
4128	rc = SSMR3GetU32(pSSM, &cStreams);
4129	AssertRC(rc);
4130
4131	if (cStreams > HDA_MAX_STREAMS)
4132	cStreams = HDA_MAX_STREAMS; /* Sanity. */
4133
4134	Log2Func(("cStreams=%RU32\n", cStreams));
4135
4136	/* Load stream states. */
4137	for (uint32_t i = 0; i < cStreams; i++)
4138	{
4139	uint8_t uStreamID;
4140	rc = SSMR3GetU8(pSSM, &uStreamID);
4141	AssertRC(rc);
4142
4143	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uStreamID);
4144	HDASTREAM StreamDummy;
4145
4146	if (!pStream)
4147	{
4148	pStream = &StreamDummy;
4149	LogRel2(("HDA: Warning: Loading of stream #%RU8 not supported, skipping to load ...\n", uStreamID));
4150	}
4151
4152	rc = hdaR3StreamInit(pStream, uStreamID);
4153	if (RT_FAILURE(rc))
4154	{
4155	LogRel(("HDA: Stream #%RU8: Loading initialization failed, rc=%Rrc\n", uStreamID, rc));
4156	/* Continue. */
4157	}
4158
4159	rc = SSMR3GetStructEx(pSSM, &pStream->State, sizeof(HDASTREAMSTATE),
4160	0 /* fFlags */, g_aSSMStreamStateFields7,
4161	NULL);
4162	AssertRC(rc);
4163
4164	/*
4165	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
4166	*/
4167	rc = SSMR3GetStructEx(pSSM, &pStream->State.BDLE.Desc, sizeof(HDABDLEDESC),
4168	0 /* fFlags */, g_aSSMBDLEDescFields7, NULL);
4169	AssertRC(rc);
4170
4171	rc = SSMR3GetStructEx(pSSM, &pStream->State.BDLE.State, sizeof(HDABDLESTATE),
4172	0 /* fFlags */, g_aSSMBDLEStateFields7, NULL);
4173	AssertRC(rc);
4174
4175	Log2Func(("[SD%RU8] %R[bdle]\n", pStream->u8SD, &pStream->State.BDLE));
4176
4177	/*
4178	* Load period state.
4179	* Don't annoy other team mates (forgot this for state v7).
4180	*/
4181	hdaR3StreamPeriodInit(&pStream->State.Period,
4182	pStream->u8SD, pStream->u16LVI, pStream->u32CBL, &pStream->State.Cfg);
4183
4184	if ( SSMR3HandleRevision(pSSM) >= 116273
4185	\|\| SSMR3HandleVersion(pSSM) >= VBOX_FULL_VERSION_MAKE(5, 2, 0))
4186	{
4187	rc = SSMR3GetStructEx(pSSM, &pStream->State.Period, sizeof(HDASTREAMPERIOD),
4188	0 /* fFlags */, g_aSSMStreamPeriodFields7, NULL);
4189	AssertRC(rc);
4190	}
4191
4192	/*
4193	* Load internal (FIFO) buffer.
4194	*/
4195	uint32_t cbCircBufSize = 0;
4196	rc = SSMR3GetU32(pSSM, &cbCircBufSize); /* cbCircBuf */
4197	AssertRC(rc);
4198
4199	uint32_t cbCircBufUsed = 0;
4200	rc = SSMR3GetU32(pSSM, &cbCircBufUsed); /* cbCircBuf */
4201	AssertRC(rc);
4202
4203	if (cbCircBufSize) /* If 0, skip the buffer. */
4204	{
4205	/* Paranoia. */
4206	AssertReleaseMsg(cbCircBufSize <= _1M,
4207	("HDA: Saved state contains bogus DMA buffer size (%RU32) for stream #%RU8",
4208	cbCircBufSize, uStreamID));
4209	AssertReleaseMsg(cbCircBufUsed <= cbCircBufSize,
4210	("HDA: Saved state contains invalid DMA buffer usage (%RU32/%RU32) for stream #%RU8",
4211	cbCircBufUsed, cbCircBufSize, uStreamID));
4212
4213	/* Do we need to cre-create the circular buffer do fit the data size? */
4214	if ( pStream->State.pCircBuf
4215	&& cbCircBufSize != (uint32_t)RTCircBufSize(pStream->State.pCircBuf))
4216	{
4217	RTCircBufDestroy(pStream->State.pCircBuf);
4218	pStream->State.pCircBuf = NULL;
4219	}
4220
4221	rc = RTCircBufCreate(&pStream->State.pCircBuf, cbCircBufSize);
4222	AssertRC(rc);
4223
4224	if ( RT_SUCCESS(rc)
4225	&& cbCircBufUsed)
4226	{
4227	void *pvBuf;
4228	size_t cbBuf;
4229
4230	RTCircBufAcquireWriteBlock(pStream->State.pCircBuf, cbCircBufUsed, &pvBuf, &cbBuf);
4231
4232	if (cbBuf)
4233	{
4234	rc = SSMR3GetMem(pSSM, pvBuf, cbBuf);
4235	AssertRC(rc);
4236	}
4237
4238	RTCircBufReleaseWriteBlock(pStream->State.pCircBuf, cbBuf);
4239
4240	Assert(cbBuf == cbCircBufUsed);
4241	}
4242	}
4243
4244	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n",
4245	uStreamID,
4246	HDA_STREAM_REG(pThis, LPIB, uStreamID), HDA_STREAM_REG(pThis, CBL, uStreamID), HDA_STREAM_REG(pThis, LVI, uStreamID)));
4247	#ifdef LOG_ENABLED
4248	hdaR3BDLEDumpAll(pThis, pStream->u64BDLBase, pStream->u16LVI + 1);
4249	#endif
4250	/** @todo (Re-)initialize active periods? */
4251
4252	} /* for cStreams */
4253
4254	rc = hdaR3LoadExecPost(pThis);
4255	AssertRC(rc);
4256
4257	LogFlowFuncLeaveRC(rc);
4258	return rc;
4259	}
4260
4261	/* IPRT format type handlers. */
4262
4263	/**
4264	* @callback_method_impl{FNRTSTRFORMATTYPE}
4265	*/
4266	static DECLCALLBACK(size_t) hdaR3StrFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4267	const char pszType, void const pvValue,
4268	int cchWidth, int cchPrecision, unsigned fFlags,
4269	void *pvUser)
4270	{
4271	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4272	PHDABDLE pBDLE = (PHDABDLE)pvValue;
4273	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4274	"BDLE(idx:%RU32, off:%RU32, fifow:%RU32, IOC:%RTbool, DMA[%RU32 bytes @ 0x%x])",
4275	pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW,
4276	pBDLE->Desc.fFlags & HDA_BDLE_FLAG_IOC, pBDLE->Desc.u32BufSize, pBDLE->Desc.u64BufAddr);
4277	}
4278
4279	/**
4280	* @callback_method_impl{FNRTSTRFORMATTYPE}
4281	*/
4282	static DECLCALLBACK(size_t) hdaR3StrFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4283	const char pszType, void const pvValue,
4284	int cchWidth, int cchPrecision, unsigned fFlags,
4285	void *pvUser)
4286	{
4287	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4288	uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
4289	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4290	"SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
4291	uSDCTL,
4292	uSDCTL & HDA_SDCTL_DIR ? "OUT" : "IN",
4293	RT_BOOL(uSDCTL & HDA_SDCTL_TP),
4294	(uSDCTL & HDA_SDCTL_STRIPE_MASK) >> HDA_SDCTL_STRIPE_SHIFT,
4295	RT_BOOL(uSDCTL & HDA_SDCTL_DEIE),
4296	RT_BOOL(uSDCTL & HDA_SDCTL_FEIE),
4297	RT_BOOL(uSDCTL & HDA_SDCTL_IOCE),
4298	RT_BOOL(uSDCTL & HDA_SDCTL_RUN),
4299	RT_BOOL(uSDCTL & HDA_SDCTL_SRST));
4300	}
4301
4302	/**
4303	* @callback_method_impl{FNRTSTRFORMATTYPE}
4304	*/
4305	static DECLCALLBACK(size_t) hdaR3StrFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4306	const char pszType, void const pvValue,
4307	int cchWidth, int cchPrecision, unsigned fFlags,
4308	void *pvUser)
4309	{
4310	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4311	uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
4312	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, uSDFIFOS ? uSDFIFOS + 1 : 0);
4313	}
4314
4315	/**
4316	* @callback_method_impl{FNRTSTRFORMATTYPE}
4317	*/
4318	static DECLCALLBACK(size_t) hdaR3StrFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4319	const char pszType, void const pvValue,
4320	int cchWidth, int cchPrecision, unsigned fFlags,
4321	void *pvUser)
4322	{
4323	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4324	uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
4325	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
4326	}
4327
4328	/**
4329	* @callback_method_impl{FNRTSTRFORMATTYPE}
4330	*/
4331	static DECLCALLBACK(size_t) hdaR3StrFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4332	const char pszType, void const pvValue,
4333	int cchWidth, int cchPrecision, unsigned fFlags,
4334	void *pvUser)
4335	{
4336	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4337	uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
4338	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4339	"SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
4340	uSdSts,
4341	RT_BOOL(uSdSts & HDA_SDSTS_FIFORDY),
4342	RT_BOOL(uSdSts & HDA_SDSTS_DESE),
4343	RT_BOOL(uSdSts & HDA_SDSTS_FIFOE),
4344	RT_BOOL(uSdSts & HDA_SDSTS_BCIS));
4345	}
4346
4347	/* Debug info dumpers */
4348
4349	static int hdaR3DbgLookupRegByName(const char *pszArgs)
4350	{
4351	int iReg = 0;
4352	for (; iReg < HDA_NUM_REGS; ++iReg)
4353	if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
4354	return iReg;
4355	return -1;
4356	}
4357
4358
4359	static void hdaR3DbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
4360	{
4361	Assert( pThis
4362	&& iHdaIndex >= 0
4363	&& iHdaIndex < HDA_NUM_REGS);
4364	pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
4365	}
4366
4367	/**
4368	* @callback_method_impl{FNDBGFHANDLERDEV}
4369	*/
4370	static DECLCALLBACK(void) hdaR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4371	{
4372	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4373	int iHdaRegisterIndex = hdaR3DbgLookupRegByName(pszArgs);
4374	if (iHdaRegisterIndex != -1)
4375	hdaR3DbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
4376	else
4377	{
4378	for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NUM_REGS; ++iHdaRegisterIndex)
4379	hdaR3DbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
4380	}
4381	}
4382
4383	static void hdaR3DbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
4384	{
4385	Assert( pThis
4386	&& iIdx >= 0
4387	&& iIdx < HDA_MAX_STREAMS);
4388
4389	const PHDASTREAM pStream = &pThis->aStreams[iIdx];
4390
4391	pHlp->pfnPrintf(pHlp, "Stream #%d:\n", iIdx);
4392	pHlp->pfnPrintf(pHlp, "\tSD%dCTL : %R[sdctl]\n", iIdx, HDA_STREAM_REG(pThis, CTL, iIdx));
4393	pHlp->pfnPrintf(pHlp, "\tSD%dCTS : %R[sdsts]\n", iIdx, HDA_STREAM_REG(pThis, STS, iIdx));
4394	pHlp->pfnPrintf(pHlp, "\tSD%dFIFOS: %R[sdfifos]\n", iIdx, HDA_STREAM_REG(pThis, FIFOS, iIdx));
4395	pHlp->pfnPrintf(pHlp, "\tSD%dFIFOW: %R[sdfifow]\n", iIdx, HDA_STREAM_REG(pThis, FIFOW, iIdx));
4396	pHlp->pfnPrintf(pHlp, "\tBDLE : %R[bdle]\n", &pStream->State.BDLE);
4397	}
4398
4399	static void hdaR3DbgPrintBDLE(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
4400	{
4401	Assert( pThis
4402	&& iIdx >= 0
4403	&& iIdx < HDA_MAX_STREAMS);
4404
4405	const PHDASTREAM pStream = &pThis->aStreams[iIdx];
4406	const PHDABDLE pBDLE = &pStream->State.BDLE;
4407
4408	pHlp->pfnPrintf(pHlp, "Stream #%d BDLE:\n", iIdx);
4409
4410	uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, iIdx),
4411	HDA_STREAM_REG(pThis, BDPU, iIdx));
4412	uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, iIdx);
4413	uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, iIdx);
4414
4415	if (!u64BaseDMA)
4416	return;
4417
4418	pHlp->pfnPrintf(pHlp, "\tCurrent: %R[bdle]\n\n", pBDLE);
4419
4420	pHlp->pfnPrintf(pHlp, "\tMemory:\n");
4421
4422	uint32_t cbBDLE = 0;
4423	for (uint16_t i = 0; i < u16LVI + 1; i++)
4424	{
4425	HDABDLEDESC bd;
4426	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i * sizeof(HDABDLEDESC), &bd, sizeof(bd));
4427
4428	pHlp->pfnPrintf(pHlp, "\t\t%s #%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
4429	pBDLE->State.u32BDLIndex == i ? "*" : " ", i, bd.u64BufAddr, bd.u32BufSize, bd.fFlags & HDA_BDLE_FLAG_IOC);
4430
4431	cbBDLE += bd.u32BufSize;
4432	}
4433
4434	pHlp->pfnPrintf(pHlp, "Total: %RU32 bytes\n", cbBDLE);
4435
4436	if (cbBDLE != u32CBL)
4437	pHlp->pfnPrintf(pHlp, "Warning: %RU32 bytes does not match CBL (%RU32)!\n", cbBDLE, u32CBL);
4438
4439	pHlp->pfnPrintf(pHlp, "DMA counters (base @ 0x%llx):\n", u64BaseDMA);
4440	if (!u64BaseDMA) /* No DMA base given? Bail out. */
4441	{
4442	pHlp->pfnPrintf(pHlp, "\tNo counters found\n");
4443	return;
4444	}
4445
4446	for (int i = 0; i < u16LVI + 1; i++)
4447	{
4448	uint32_t uDMACnt;
4449	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
4450	&uDMACnt, sizeof(uDMACnt));
4451
4452	pHlp->pfnPrintf(pHlp, "\t#%03d DMA @ 0x%x\n", i , uDMACnt);
4453	}
4454	}
4455
4456	static int hdaR3DbgLookupStrmIdx(PHDASTATE pThis, const char *pszArgs)
4457	{
4458	RT_NOREF(pThis, pszArgs);
4459	/** @todo Add args parsing. */
4460	return -1;
4461	}
4462
4463	/**
4464	* @callback_method_impl{FNDBGFHANDLERDEV}
4465	*/
4466	static DECLCALLBACK(void) hdaR3DbgInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4467	{
4468	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4469	int iHdaStreamdex = hdaR3DbgLookupStrmIdx(pThis, pszArgs);
4470	if (iHdaStreamdex != -1)
4471	hdaR3DbgPrintStream(pThis, pHlp, iHdaStreamdex);
4472	else
4473	for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
4474	hdaR3DbgPrintStream(pThis, pHlp, iHdaStreamdex);
4475	}
4476
4477	/**
4478	* @callback_method_impl{FNDBGFHANDLERDEV}
4479	*/
4480	static DECLCALLBACK(void) hdaR3DbgInfoBDLE(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4481	{
4482	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4483	int iHdaStreamdex = hdaR3DbgLookupStrmIdx(pThis, pszArgs);
4484	if (iHdaStreamdex != -1)
4485	hdaR3DbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
4486	else
4487	for (iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
4488	hdaR3DbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
4489	}
4490
4491	/**
4492	* @callback_method_impl{FNDBGFHANDLERDEV}
4493	*/
4494	static DECLCALLBACK(void) hdaR3DbgInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4495	{
4496	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4497
4498	if (pThis->pCodec->pfnDbgListNodes)
4499	pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
4500	else
4501	pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
4502	}
4503
4504	/**
4505	* @callback_method_impl{FNDBGFHANDLERDEV}
4506	*/
4507	static DECLCALLBACK(void) hdaR3DbgInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4508	{
4509	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4510
4511	if (pThis->pCodec->pfnDbgSelector)
4512	pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
4513	else
4514	pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
4515	}
4516
4517	/**
4518	* @callback_method_impl{FNDBGFHANDLERDEV}
4519	*/
4520	static DECLCALLBACK(void) hdaR3DbgInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4521	{
4522	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4523
4524	if (pThis->pMixer)
4525	AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
4526	else
4527	pHlp->pfnPrintf(pHlp, "Mixer not available\n");
4528	}
4529
4530
4531	/* PDMIBASE */
4532
4533	/**
4534	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
4535	*/
4536	static DECLCALLBACK(void ) hdaR3QueryInterface(struct PDMIBASE pInterface, const char *pszIID)
4537	{
4538	PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
4539	Assert(&pThis->IBase == pInterface);
4540
4541	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
4542	return NULL;
4543	}
4544
4545
4546	/* PDMDEVREG */
4547
4548	/**
4549	* Attach command, internal version.
4550	*
4551	* This is called to let the device attach to a driver for a specified LUN
4552	* during runtime. This is not called during VM construction, the device
4553	* constructor has to attach to all the available drivers.
4554	*
4555	* @returns VBox status code.
4556	* @param pThis HDA state.
4557	* @param uLUN The logical unit which is being detached.
4558	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4559	* @param ppDrv Attached driver instance on success. Optional.
4560	*/
4561	static int hdaR3AttachInternal(PHDASTATE pThis, unsigned uLUN, uint32_t fFlags, PHDADRIVER *ppDrv)
4562	{
4563	RT_NOREF(fFlags);
4564
4565	/*
4566	* Attach driver.
4567	*/
4568	char *pszDesc;
4569	if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
4570	AssertLogRelFailedReturn(VERR_NO_MEMORY);
4571
4572	PPDMIBASE pDrvBase;
4573	int rc = PDMDevHlpDriverAttach(pThis->pDevInsR3, uLUN,
4574	&pThis->IBase, &pDrvBase, pszDesc);
4575	if (RT_SUCCESS(rc))
4576	{
4577	PHDADRIVER pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
4578	if (pDrv)
4579	{
4580	pDrv->pDrvBase = pDrvBase;
4581	pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
4582	AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
4583	pDrv->pHDAState = pThis;
4584	pDrv->uLUN = uLUN;
4585
4586	/*
4587	* For now we always set the driver at LUN 0 as our primary
4588	* host backend. This might change in the future.
4589	*/
4590	if (pDrv->uLUN == 0)
4591	pDrv->fFlags \|= PDMAUDIODRVFLAGS_PRIMARY;
4592
4593	LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->fFlags));
4594
4595	/* Attach to driver list if not attached yet. */
4596	if (!pDrv->fAttached)
4597	{
4598	RTListAppend(&pThis->lstDrv, &pDrv->Node);
4599	pDrv->fAttached = true;
4600	}
4601
4602	if (ppDrv)
4603	*ppDrv = pDrv;
4604	}
4605	else
4606	rc = VERR_NO_MEMORY;
4607	}
4608	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4609	LogFunc(("No attached driver for LUN #%u\n", uLUN));
4610
4611	if (RT_FAILURE(rc))
4612	{
4613	/* Only free this string on failure;
4614	* must remain valid for the live of the driver instance. */
4615	RTStrFree(pszDesc);
4616	}
4617
4618	LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
4619	return rc;
4620	}
4621
4622	/**
4623	* Detach command, internal version.
4624	*
4625	* This is called to let the device detach from a driver for a specified LUN
4626	* during runtime.
4627	*
4628	* @returns VBox status code.
4629	* @param pThis HDA state.
4630	* @param pDrv Driver to detach from device.
4631	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4632	*/
4633	static int hdaR3DetachInternal(PHDASTATE pThis, PHDADRIVER pDrv, uint32_t fFlags)
4634	{
4635	RT_NOREF(fFlags);
4636
4637	/* First, remove the driver from our list and destory it's associated streams.
4638	* This also will un-set the driver as a recording source (if associated). */
4639	hdaR3MixerRemoveDrv(pThis, pDrv);
4640
4641	/* Next, search backwards for a capable (attached) driver which now will be the
4642	* new recording source. */
4643	PHDADRIVER pDrvCur;
4644	RTListForEachReverse(&pThis->lstDrv, pDrvCur, HDADRIVER, Node)
4645	{
4646	if (!pDrvCur->pConnector)
4647	continue;
4648
4649	PDMAUDIOBACKENDCFG Cfg;
4650	int rc2 = pDrvCur->pConnector->pfnGetConfig(pDrvCur->pConnector, &Cfg);
4651	if (RT_FAILURE(rc2))
4652	continue;
4653
4654	PHDADRIVERSTREAM pDrvStrm;
4655	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
4656	pDrvStrm = &pDrvCur->MicIn;
4657	if ( pDrvStrm
4658	&& pDrvStrm->pMixStrm)
4659	{
4660	rc2 = AudioMixerSinkSetRecordingSource(pThis->SinkMicIn.pMixSink, pDrvStrm->pMixStrm);
4661	if (RT_SUCCESS(rc2))
4662	LogRel2(("HDA: Set new recording source for 'Mic In' to '%s'\n", Cfg.szName));
4663	}
4664	# endif
4665	pDrvStrm = &pDrvCur->LineIn;
4666	if ( pDrvStrm
4667	&& pDrvStrm->pMixStrm)
4668	{
4669	rc2 = AudioMixerSinkSetRecordingSource(pThis->SinkLineIn.pMixSink, pDrvStrm->pMixStrm);
4670	if (RT_SUCCESS(rc2))
4671	LogRel2(("HDA: Set new recording source for 'Line In' to '%s'\n", Cfg.szName));
4672	}
4673	}
4674
4675	LogFunc(("uLUN=%u, fFlags=0x%x\n", pDrv->uLUN, fFlags));
4676	return VINF_SUCCESS;
4677	}
4678
4679	/**
4680	* @interface_method_impl{PDMDEVREG,pfnAttach}
4681	*/
4682	static DECLCALLBACK(int) hdaR3Attach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4683	{
4684	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4685
4686	DEVHDA_LOCK_RETURN(pThis, VERR_IGNORED);
4687
4688	LogFunc(("uLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
4689
4690	PHDADRIVER pDrv;
4691	int rc2 = hdaR3AttachInternal(pThis, uLUN, fFlags, &pDrv);
4692	if (RT_SUCCESS(rc2))
4693	rc2 = hdaR3MixerAddDrv(pThis, pDrv);
4694
4695	if (RT_FAILURE(rc2))
4696	LogFunc(("Failed with %Rrc\n", rc2));
4697
4698	DEVHDA_UNLOCK(pThis);
4699
4700	return VINF_SUCCESS;
4701	}
4702
4703	/**
4704	* @interface_method_impl{PDMDEVREG,pfnDetach}
4705	*/
4706	static DECLCALLBACK(void) hdaR3Detach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4707	{
4708	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4709
4710	DEVHDA_LOCK(pThis);
4711
4712	LogFunc(("uLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
4713
4714	PHDADRIVER pDrv, pDrvNext;
4715	RTListForEachSafe(&pThis->lstDrv, pDrv, pDrvNext, HDADRIVER, Node)
4716	{
4717	if (pDrv->uLUN == uLUN)
4718	{
4719	int rc2 = hdaR3DetachInternal(pThis, pDrv, fFlags);
4720	if (RT_SUCCESS(rc2))
4721	{
4722	RTMemFree(pDrv);
4723	pDrv = NULL;
4724	}
4725
4726	break;
4727	}
4728	}
4729
4730	DEVHDA_UNLOCK(pThis);
4731	}
4732
4733	/**
4734	* Powers off the device.
4735	*
4736	* @param pDevIns Device instance to power off.
4737	*/
4738	static DECLCALLBACK(void) hdaR3PowerOff(PPDMDEVINS pDevIns)
4739	{
4740	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4741
4742	DEVHDA_LOCK_RETURN_VOID(pThis);
4743
4744	LogRel2(("HDA: Powering off ...\n"));
4745
4746	/* Ditto goes for the codec, which in turn uses the mixer. */
4747	hdaCodecPowerOff(pThis->pCodec);
4748
4749	/*
4750	* Note: Destroy the mixer while powering off and not in hdaR3Destruct,
4751	* giving the mixer the chance to release any references held to
4752	* PDM audio streams it maintains.
4753	*/
4754	if (pThis->pMixer)
4755	{
4756	AudioMixerDestroy(pThis->pMixer);
4757	pThis->pMixer = NULL;
4758	}
4759
4760	DEVHDA_UNLOCK(pThis);
4761	}
4762
4763
4764	/**
4765	* Re-attaches (replaces) a driver with a new driver.
4766	*
4767	* This is only used by to attach the Null driver when it failed to attach the
4768	* one that was configured.
4769	*
4770	* @returns VBox status code.
4771	* @param pThis Device instance to re-attach driver to.
4772	* @param pDrv Driver instance used for attaching to.
4773	* If NULL is specified, a new driver will be created and appended
4774	* to the driver list.
4775	* @param uLUN The logical unit which is being re-detached.
4776	* @param pszDriver New driver name to attach.
4777	*/
4778	static int hdaR3ReattachInternal(PHDASTATE pThis, PHDADRIVER pDrv, uint8_t uLUN, const char *pszDriver)
4779	{
4780	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
4781	AssertPtrReturn(pszDriver, VERR_INVALID_POINTER);
4782
4783	int rc;
4784
4785	if (pDrv)
4786	{
4787	rc = hdaR3DetachInternal(pThis, pDrv, 0 /* fFlags */);
4788	if (RT_SUCCESS(rc))
4789	rc = PDMDevHlpDriverDetach(pThis->pDevInsR3, PDMIBASE_2_PDMDRV(pDrv->pDrvBase), 0 /* fFlags */);
4790
4791	if (RT_FAILURE(rc))
4792	return rc;
4793
4794	pDrv = NULL;
4795	}
4796
4797	PVM pVM = PDMDevHlpGetVM(pThis->pDevInsR3);
4798	PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
4799	PCFGMNODE pDev0 = CFGMR3GetChild(pRoot, "Devices/hda/0/");
4800
4801	/* Remove LUN branch. */
4802	CFGMR3RemoveNode(CFGMR3GetChildF(pDev0, "LUN#%u/", uLUN));
4803
4804	#define RC_CHECK() if (RT_FAILURE(rc)) { AssertReleaseRC(rc); break; }
4805
4806	do
4807	{
4808	PCFGMNODE pLunL0;
4809	rc = CFGMR3InsertNodeF(pDev0, &pLunL0, "LUN#%u/", uLUN); RC_CHECK();
4810	rc = CFGMR3InsertString(pLunL0, "Driver", "AUDIO"); RC_CHECK();
4811	rc = CFGMR3InsertNode(pLunL0, "Config/", NULL); RC_CHECK();
4812
4813	PCFGMNODE pLunL1, pLunL2;
4814	rc = CFGMR3InsertNode (pLunL0, "AttachedDriver/", &pLunL1); RC_CHECK();
4815	rc = CFGMR3InsertNode (pLunL1, "Config/", &pLunL2); RC_CHECK();
4816	rc = CFGMR3InsertString(pLunL1, "Driver", pszDriver); RC_CHECK();
4817
4818	rc = CFGMR3InsertString(pLunL2, "AudioDriver", pszDriver); RC_CHECK();
4819
4820	} while (0);
4821
4822	if (RT_SUCCESS(rc))
4823	rc = hdaR3AttachInternal(pThis, uLUN, 0 /* fFlags /, NULL / ppDrv */);
4824
4825	LogFunc(("pThis=%p, uLUN=%u, pszDriver=%s, rc=%Rrc\n", pThis, uLUN, pszDriver, rc));
4826
4827	#undef RC_CHECK
4828
4829	return rc;
4830	}
4831
4832
4833	/**
4834	* @interface_method_impl{PDMDEVREG,pfnReset}
4835	*/
4836	static DECLCALLBACK(void) hdaR3Reset(PPDMDEVINS pDevIns)
4837	{
4838	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4839
4840	LogFlowFuncEnter();
4841
4842	DEVHDA_LOCK_RETURN_VOID(pThis);
4843
4844	/*
4845	* 18.2.6,7 defines that values of this registers might be cleared on power on/reset
4846	* hdaR3Reset shouldn't affects these registers.
4847	*/
4848	HDA_REG(pThis, WAKEEN) = 0x0;
4849
4850	hdaR3GCTLReset(pThis);
4851
4852	/* Indicate that HDA is not in reset. The firmware is supposed to (un)reset HDA,
4853	* but we can take a shortcut.
4854	*/
4855	HDA_REG(pThis, GCTL) = HDA_GCTL_CRST;
4856
4857	DEVHDA_UNLOCK(pThis);
4858	}
4859
4860
4861	/**
4862	* @interface_method_impl{PDMDEVREG,pfnRelocate}
4863	*/
4864	static DECLCALLBACK(void) hdaR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
4865	{
4866	NOREF(offDelta);
4867	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4868	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
4869	}
4870
4871
4872	/**
4873	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4874	*/
4875	static DECLCALLBACK(int) hdaR3Destruct(PPDMDEVINS pDevIns)
4876	{
4877	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns); /* this shall come first */
4878	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4879	DEVHDA_LOCK(pThis); /** @todo r=bird: this will fail on early constructor failure. */
4880
4881	PHDADRIVER pDrv;
4882	while (!RTListIsEmpty(&pThis->lstDrv))
4883	{
4884	pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
4885
4886	RTListNodeRemove(&pDrv->Node);
4887	RTMemFree(pDrv);
4888	}
4889
4890	if (pThis->pCodec)
4891	{
4892	hdaCodecDestruct(pThis->pCodec);
4893
4894	RTMemFree(pThis->pCodec);
4895	pThis->pCodec = NULL;
4896	}
4897
4898	RTMemFree(pThis->pu32CorbBuf);
4899	pThis->pu32CorbBuf = NULL;
4900
4901	RTMemFree(pThis->pu64RirbBuf);
4902	pThis->pu64RirbBuf = NULL;
4903
4904	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
4905	hdaR3StreamDestroy(&pThis->aStreams[i]);
4906
4907	DEVHDA_UNLOCK(pThis);
4908	return VINF_SUCCESS;
4909	}
4910
4911
4912	/**
4913	* @interface_method_impl{PDMDEVREG,pfnConstruct}
4914	*/
4915	static DECLCALLBACK(int) hdaR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4916	{
4917	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); /* this shall come first */
4918	PHDASTATE pThis = PDMINS_2_DATA(pDevIns, PHDASTATE);
4919	Assert(iInstance == 0); RT_NOREF(iInstance);
4920
4921	/*
4922	* Initialize the state sufficently to make the destructor work.
4923	*/
4924	pThis->uAlignmentCheckMagic = HDASTATE_ALIGNMENT_CHECK_MAGIC;
4925	RTListInit(&pThis->lstDrv);
4926	/** @todo r=bird: There are probably other things which should be
4927	* initialized here before we start failing. */
4928
4929	/*
4930	* Validations.
4931	*/
4932	if (!CFGMR3AreValuesValid(pCfg, "RZEnabled\0"
4933	"TimerHz\0"
4934	"PosAdjustEnabled\0"
4935	"PosAdjustFrames\0"
4936	"DebugEnabled\0"
4937	"DebugPathOut\0"))
4938	{
4939	return PDMDEV_SET_ERROR(pDevIns, VERR_PDM_DEVINS_UNKNOWN_CFG_VALUES,
4940	N_ ("Invalid configuration for the Intel HDA device"));
4941	}
4942
4943	int rc = CFGMR3QueryBoolDef(pCfg, "RZEnabled", &pThis->fRZEnabled, true);
4944	if (RT_FAILURE(rc))
4945	return PDMDEV_SET_ERROR(pDevIns, rc,
4946	N_("HDA configuration error: failed to read RCEnabled as boolean"));
4947
4948
4949	rc = CFGMR3QueryU16Def(pCfg, "TimerHz", &pThis->uTimerHz, HDA_TIMER_HZ_DEFAULT /* Default value, if not set. */);
4950	if (RT_FAILURE(rc))
4951	return PDMDEV_SET_ERROR(pDevIns, rc,
4952	N_("HDA configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
4953
4954	if (pThis->uTimerHz != HDA_TIMER_HZ_DEFAULT)
4955	LogRel(("HDA: Using custom device timer rate (%RU16Hz)\n", pThis->uTimerHz));
4956
4957	rc = CFGMR3QueryBoolDef(pCfg, "PosAdjustEnabled", &pThis->fPosAdjustEnabled, true);
4958	if (RT_FAILURE(rc))
4959	return PDMDEV_SET_ERROR(pDevIns, rc,
4960	N_("HDA configuration error: failed to read position adjustment enabled as boolean"));
4961
4962	if (!pThis->fPosAdjustEnabled)
4963	LogRel(("HDA: Position adjustment is disabled\n"));
4964
4965	rc = CFGMR3QueryU16Def(pCfg, "PosAdjustFrames", &pThis->cPosAdjustFrames, HDA_POS_ADJUST_DEFAULT);
4966	if (RT_FAILURE(rc))
4967	return PDMDEV_SET_ERROR(pDevIns, rc,
4968	N_("HDA configuration error: failed to read position adjustment frames as unsigned integer"));
4969
4970	if (pThis->cPosAdjustFrames)
4971	LogRel(("HDA: Using custom position adjustment (%RU16 audio frames)\n", pThis->cPosAdjustFrames));
4972
4973	rc = CFGMR3QueryBoolDef(pCfg, "DebugEnabled", &pThis->Dbg.fEnabled, false);
4974	if (RT_FAILURE(rc))
4975	return PDMDEV_SET_ERROR(pDevIns, rc,
4976	N_("HDA configuration error: failed to read debugging enabled flag as boolean"));
4977
4978	rc = CFGMR3QueryStringDef(pCfg, "DebugPathOut", pThis->Dbg.szOutPath, sizeof(pThis->Dbg.szOutPath),
4979	VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH);
4980	if (RT_FAILURE(rc))
4981	return PDMDEV_SET_ERROR(pDevIns, rc,
4982	N_("HDA configuration error: failed to read debugging output path flag as string"));
4983
4984	if (!strlen(pThis->Dbg.szOutPath))
4985	RTStrPrintf(pThis->Dbg.szOutPath, sizeof(pThis->Dbg.szOutPath), VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH);
4986
4987	if (pThis->Dbg.fEnabled)
4988	LogRel2(("HDA: Debug output will be saved to '%s'\n", pThis->Dbg.szOutPath));
4989
4990	/*
4991	* Use an own critical section for the device instead of the default
4992	* one provided by PDM. This allows fine-grained locking in combination
4993	* with TM when timer-specific stuff is being called in e.g. the MMIO handlers.
4994	*/
4995	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "HDA");
4996	AssertRCReturn(rc, rc);
4997
4998	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4999	AssertRCReturn(rc, rc);
5000
5001	/*
5002	* Initialize data (most of it anyway).
5003	*/
5004	pThis->pDevInsR3 = pDevIns;
5005	pThis->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
5006	pThis->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
5007	/* IBase */
5008	pThis->IBase.pfnQueryInterface = hdaR3QueryInterface;
5009
5010	/* PCI Device */
5011	PCIDevSetVendorId (&pThis->PciDev, HDA_PCI_VENDOR_ID); /* nVidia */
5012	PCIDevSetDeviceId (&pThis->PciDev, HDA_PCI_DEVICE_ID); /* HDA */
5013
5014	PCIDevSetCommand (&pThis->PciDev, 0x0000); /* 04 rw,ro - pcicmd. */
5015	PCIDevSetStatus (&pThis->PciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
5016	PCIDevSetRevisionId (&pThis->PciDev, 0x01); /* 08 ro - rid. */
5017	PCIDevSetClassProg (&pThis->PciDev, 0x00); /* 09 ro - pi. */
5018	PCIDevSetClassSub (&pThis->PciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
5019	PCIDevSetClassBase (&pThis->PciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
5020	PCIDevSetHeaderType (&pThis->PciDev, 0x00); /* 0e ro - headtyp. */
5021	PCIDevSetBaseAddress (&pThis->PciDev, 0, /* 10 rw - MMIO */
5022	false /* fIoSpace /, false / fPrefetchable /, true / f64Bit */, 0x00000000);
5023	PCIDevSetInterruptLine (&pThis->PciDev, 0x00); /* 3c rw. */
5024	PCIDevSetInterruptPin (&pThis->PciDev, 0x01); /* 3d ro - INTA#. */
5025
5026	#if defined(HDA_AS_PCI_EXPRESS)
5027	PCIDevSetCapabilityList (&pThis->PciDev, 0x80);
5028	#elif defined(VBOX_WITH_MSI_DEVICES)
5029	PCIDevSetCapabilityList (&pThis->PciDev, 0x60);
5030	#else
5031	PCIDevSetCapabilityList (&pThis->PciDev, 0x50); /* ICH6 datasheet 18.1.16 */
5032	#endif
5033
5034	/// @todo r=michaln: If there are really no PCIDevSetXx for these, the meaning
5035	/// of these values needs to be properly documented!
5036	/* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
5037	PCIDevSetByte(&pThis->PciDev, 0x40, 0x01);
5038
5039	/* Power Management */
5040	PCIDevSetByte(&pThis->PciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
5041	PCIDevSetByte(&pThis->PciDev, 0x50 + 1, 0x0); /* next */
5042	PCIDevSetWord(&pThis->PciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI \| 0x02 /* version, PM1.1 */ );
5043
5044	#ifdef HDA_AS_PCI_EXPRESS
5045	/* PCI Express */
5046	PCIDevSetByte(&pThis->PciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
5047	PCIDevSetByte(&pThis->PciDev, 0x80 + 1, 0x60); /* next */
5048	/* Device flags */
5049	PCIDevSetWord(&pThis->PciDev, 0x80 + 2,
5050	/* version */ 0x1 \|
5051	/* Root Complex Integrated Endpoint */ (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) \|
5052	/* MSI */ (100) << 9 );
5053	/* Device capabilities */
5054	PCIDevSetDWord(&pThis->PciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
5055	/* Device control */
5056	PCIDevSetWord( &pThis->PciDev, 0x80 + 8, 0);
5057	/* Device status */
5058	PCIDevSetWord( &pThis->PciDev, 0x80 + 10, 0);
5059	/* Link caps */
5060	PCIDevSetDWord(&pThis->PciDev, 0x80 + 12, 0);
5061	/* Link control */
5062	PCIDevSetWord( &pThis->PciDev, 0x80 + 16, 0);
5063	/* Link status */
5064	PCIDevSetWord( &pThis->PciDev, 0x80 + 18, 0);
5065	/* Slot capabilities */
5066	PCIDevSetDWord(&pThis->PciDev, 0x80 + 20, 0);
5067	/* Slot control */
5068	PCIDevSetWord( &pThis->PciDev, 0x80 + 24, 0);
5069	/* Slot status */
5070	PCIDevSetWord( &pThis->PciDev, 0x80 + 26, 0);
5071	/* Root control */
5072	PCIDevSetWord( &pThis->PciDev, 0x80 + 28, 0);
5073	/* Root capabilities */
5074	PCIDevSetWord( &pThis->PciDev, 0x80 + 30, 0);
5075	/* Root status */
5076	PCIDevSetDWord(&pThis->PciDev, 0x80 + 32, 0);
5077	/* Device capabilities 2 */
5078	PCIDevSetDWord(&pThis->PciDev, 0x80 + 36, 0);
5079	/* Device control 2 */
5080	PCIDevSetQWord(&pThis->PciDev, 0x80 + 40, 0);
5081	/* Link control 2 */
5082	PCIDevSetQWord(&pThis->PciDev, 0x80 + 48, 0);
5083	/* Slot control 2 */
5084	PCIDevSetWord( &pThis->PciDev, 0x80 + 56, 0);
5085	#endif
5086
5087	/*
5088	* Register the PCI device.
5089	*/
5090	rc = PDMDevHlpPCIRegister(pDevIns, &pThis->PciDev);
5091	if (RT_FAILURE(rc))
5092	return rc;
5093
5094	rc = PDMDevHlpPCIIORegionRegister(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaR3PciIoRegionMap);
5095	if (RT_FAILURE(rc))
5096	return rc;
5097
5098	#ifdef VBOX_WITH_MSI_DEVICES
5099	PDMMSIREG MsiReg;
5100	RT_ZERO(MsiReg);
5101	MsiReg.cMsiVectors = 1;
5102	MsiReg.iMsiCapOffset = 0x60;
5103	MsiReg.iMsiNextOffset = 0x50;
5104	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5105	if (RT_FAILURE(rc))
5106	{
5107	/* That's OK, we can work without MSI */
5108	PCIDevSetCapabilityList(&pThis->PciDev, 0x50);
5109	}
5110	#endif
5111
5112	rc = PDMDevHlpSSMRegister(pDevIns, HDA_SSM_VERSION, sizeof(*pThis), hdaR3SaveExec, hdaR3LoadExec);
5113	if (RT_FAILURE(rc))
5114	return rc;
5115
5116	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
5117	LogRel(("HDA: Asynchronous I/O enabled\n"));
5118	#endif
5119
5120	uint8_t uLUN;
5121	for (uLUN = 0; uLUN < UINT8_MAX; ++uLUN)
5122	{
5123	LogFunc(("Trying to attach driver for LUN #%RU32 ...\n", uLUN));
5124	rc = hdaR3AttachInternal(pThis, uLUN, 0 /* fFlags /, NULL / ppDrv */);
5125	if (RT_FAILURE(rc))
5126	{
5127	if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5128	rc = VINF_SUCCESS;
5129	else if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
5130	{
5131	hdaR3ReattachInternal(pThis, NULL /* pDrv */, uLUN, "NullAudio");
5132	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
5133	N_("Host audio backend initialization has failed. Selecting the NULL audio backend "
5134	"with the consequence that no sound is audible"));
5135	/* Attaching to the NULL audio backend will never fail. */
5136	rc = VINF_SUCCESS;
5137	}
5138	break;
5139	}
5140	}
5141
5142	LogFunc(("cLUNs=%RU8, rc=%Rrc\n", uLUN, rc));
5143
5144	if (RT_SUCCESS(rc))
5145	{
5146	rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
5147	if (RT_SUCCESS(rc))
5148	{
5149	/*
5150	* Add mixer output sinks.
5151	*/
5152	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
5153	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Front",
5154	AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
5155	AssertRC(rc);
5156	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Center / Subwoofer",
5157	AUDMIXSINKDIR_OUTPUT, &pThis->SinkCenterLFE.pMixSink);
5158	AssertRC(rc);
5159	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Rear",
5160	AUDMIXSINKDIR_OUTPUT, &pThis->SinkRear.pMixSink);
5161	AssertRC(rc);
5162	#else
5163	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] PCM Output",
5164	AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
5165	AssertRC(rc);
5166	#endif
5167	/*
5168	* Add mixer input sinks.
5169	*/
5170	rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Line In",
5171	AUDMIXSINKDIR_INPUT, &pThis->SinkLineIn.pMixSink);
5172	AssertRC(rc);
5173	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5174	rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Microphone In",
5175	AUDMIXSINKDIR_INPUT, &pThis->SinkMicIn.pMixSink);
5176	AssertRC(rc);
5177	#endif
5178	/* There is no master volume control. Set the master to max. */
5179	PDMAUDIOVOLUME vol = { false, 255, 255 };
5180	rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
5181	AssertRC(rc);
5182	}
5183	}
5184
5185	if (RT_SUCCESS(rc))
5186	{
5187	/* Allocate CORB buffer. */
5188	pThis->cbCorbBuf = HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE;
5189	pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
5190	if (pThis->pu32CorbBuf)
5191	{
5192	/* Allocate RIRB buffer. */
5193	pThis->cbRirbBuf = HDA_RIRB_SIZE * HDA_RIRB_ELEMENT_SIZE;
5194	pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
5195	if (pThis->pu64RirbBuf)
5196	{
5197	/* Allocate codec. */
5198	pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
5199	if (!pThis->pCodec)
5200	rc = PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating HDA codec state"));
5201	}
5202	else
5203	rc = PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating RIRB"));
5204	}
5205	else
5206	rc = PDMDEV_SET_ERROR(pDevIns, VERR_NO_MEMORY, N_("Out of memory allocating CORB"));
5207
5208	if (RT_SUCCESS(rc))
5209	{
5210	/* Set codec callbacks to this controller. */
5211	pThis->pCodec->pfnCbMixerAddStream = hdaR3MixerAddStream;
5212	pThis->pCodec->pfnCbMixerRemoveStream = hdaR3MixerRemoveStream;
5213	pThis->pCodec->pfnCbMixerControl = hdaR3MixerControl;
5214	pThis->pCodec->pfnCbMixerSetVolume = hdaR3MixerSetVolume;
5215
5216	pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
5217
5218	/* Construct the codec. */
5219	rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfg);
5220	if (RT_FAILURE(rc))
5221	AssertRCReturn(rc, rc);
5222
5223	/* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
5224	verb F20 should provide device/codec recognition. */
5225	Assert(pThis->pCodec->u16VendorId);
5226	Assert(pThis->pCodec->u16DeviceId);
5227	PCIDevSetSubSystemVendorId(&pThis->PciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
5228	PCIDevSetSubSystemId( &pThis->PciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
5229	}
5230	}
5231
5232	if (RT_SUCCESS(rc))
5233	{
5234	/*
5235	* Create all hardware streams.
5236	*/
5237	static const char * const s_apszNames[] =
5238	{
5239	"HDA SD0", "HDA SD1", "HDA SD2", "HDA SD3",
5240	"HDA SD4", "HDA SD5", "HDA SD6", "HDA SD7",
5241	};
5242	AssertCompile(RT_ELEMENTS(s_apszNames) == HDA_MAX_STREAMS);
5243	for (uint8_t i = 0; i < HDA_MAX_STREAMS; ++i)
5244	{
5245	/* Create the emulation timer (per stream).
5246	*
5247	* Note: Use TMCLOCK_VIRTUAL_SYNC here, as the guest's HDA driver
5248	* relies on exact (virtual) DMA timing and uses DMA Position Buffers
5249	* instead of the LPIB registers.
5250	*/
5251	rc = PDMDevHlpTMTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, hdaR3Timer, &pThis->aStreams[i],
5252	TMTIMER_FLAGS_NO_CRIT_SECT, s_apszNames[i], &pThis->pTimer[i]);
5253	AssertRCReturn(rc, rc);
5254
5255	/* Use our own critcal section for the device timer.
5256	* That way we can control more fine-grained when to lock what. */
5257	rc = TMR3TimerSetCritSect(pThis->pTimer[i], &pThis->CritSect);
5258	AssertRCReturn(rc, rc);
5259
5260	rc = hdaR3StreamCreate(&pThis->aStreams[i], pThis, i /* u8SD */);
5261	AssertRC(rc);
5262	}
5263
5264	#ifdef VBOX_WITH_AUDIO_HDA_ONETIME_INIT
5265	/*
5266	* Initialize the driver chain.
5267	*/
5268	PHDADRIVER pDrv;
5269	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
5270	{
5271	/*
5272	* Only primary drivers are critical for the VM to run. Everything else
5273	* might not worth showing an own error message box in the GUI.
5274	*/
5275	if (!(pDrv->fFlags & PDMAUDIODRVFLAGS_PRIMARY))
5276	continue;
5277
5278	PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
5279	AssertPtr(pCon);
5280
5281	bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
5282	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5283	bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
5284	# endif
5285	bool fValidOut = AudioMixerStreamIsValid(pDrv->Front.pMixStrm);
5286	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
5287	/** @todo Anything to do here? */
5288	# endif
5289
5290	if ( !fValidLineIn
5291	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5292	&& !fValidMicIn
5293	# endif
5294	&& !fValidOut)
5295	{
5296	LogRel(("HDA: Falling back to NULL backend (no sound audible)\n"));
5297
5298	hdaR3Reset(pDevIns);
5299	hdaR3ReattachInternal(pThis, pDrv, pDrv->uLUN, "NullAudio");
5300
5301	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
5302	N_("No audio devices could be opened. Selecting the NULL audio backend "
5303	"with the consequence that no sound is audible"));
5304	}
5305	else
5306	{
5307	bool fWarn = false;
5308
5309	PDMAUDIOBACKENDCFG backendCfg;
5310	int rc2 = pCon->pfnGetConfig(pCon, &backendCfg);
5311	if (RT_SUCCESS(rc2))
5312	{
5313	if (backendCfg.cMaxStreamsIn)
5314	{
5315	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5316	/* If the audio backend supports two or more input streams at once,
5317	* warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
5318	if (backendCfg.cMaxStreamsIn >= 2)
5319	fWarn = !fValidLineIn \|\| !fValidMicIn;
5320	/* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
5321	* not ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
5322	* One of the two simply is not in use then. */
5323	else if (backendCfg.cMaxStreamsIn == 1)
5324	fWarn = !fValidLineIn && !fValidMicIn;
5325	/* Don't warn if our backend is not able of supporting any input streams at all. */
5326	# else /* !VBOX_WITH_AUDIO_HDA_MIC_IN */
5327	/* We only have line-in as input source. */
5328	fWarn = !fValidLineIn;
5329	# endif /* VBOX_WITH_AUDIO_HDA_MIC_IN */
5330	}
5331
5332	if ( !fWarn
5333	&& backendCfg.cMaxStreamsOut)
5334	{
5335	fWarn = !fValidOut;
5336	}
5337	}
5338	else
5339	{
5340	LogRel(("HDA: Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
5341	fWarn = true;
5342	}
5343
5344	if (fWarn)
5345	{
5346	char szMissingStreams[255];
5347	size_t len = 0;
5348	if (!fValidLineIn)
5349	{
5350	LogRel(("HDA: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
5351	len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
5352	}
5353	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5354	if (!fValidMicIn)
5355	{
5356	LogRel(("HDA: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
5357	len += RTStrPrintf(szMissingStreams + len,
5358	sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
5359	}
5360	# endif /* VBOX_WITH_AUDIO_HDA_MIC_IN */
5361	if (!fValidOut)
5362	{
5363	LogRel(("HDA: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
5364	len += RTStrPrintf(szMissingStreams + len,
5365	sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
5366	}
5367
5368	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
5369	N_("Some HDA audio streams (%s) could not be opened. Guest applications generating audio "
5370	"output or depending on audio input may hang. Make sure your host audio device "
5371	"is working properly. Check the logfile for error messages of the audio "
5372	"subsystem"), szMissingStreams);
5373	}
5374	}
5375	}
5376	#endif /* VBOX_WITH_AUDIO_HDA_ONETIME_INIT */
5377	}
5378
5379	if (RT_SUCCESS(rc))
5380	{
5381	hdaR3Reset(pDevIns);
5382
5383	/*
5384	* Debug and string formatter types.
5385	*/
5386	PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaR3DbgInfo);
5387	PDMDevHlpDBGFInfoRegister(pDevIns, "hdabdle", "HDA stream BDLE info. (hdabdle [stream number])", hdaR3DbgInfoBDLE);
5388	PDMDevHlpDBGFInfoRegister(pDevIns, "hdastream", "HDA stream info. (hdastream [stream number])", hdaR3DbgInfoStream);
5389	PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaR3DbgInfoCodecNodes);
5390	PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaR3DbgInfoCodecSelector);
5391	PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaR3DbgInfoMixer);
5392
5393	rc = RTStrFormatTypeRegister("bdle", hdaR3StrFmtBDLE, NULL);
5394	AssertRC(rc);
5395	rc = RTStrFormatTypeRegister("sdctl", hdaR3StrFmtSDCTL, NULL);
5396	AssertRC(rc);
5397	rc = RTStrFormatTypeRegister("sdsts", hdaR3StrFmtSDSTS, NULL);
5398	AssertRC(rc);
5399	rc = RTStrFormatTypeRegister("sdfifos", hdaR3StrFmtSDFIFOS, NULL);
5400	AssertRC(rc);
5401	rc = RTStrFormatTypeRegister("sdfifow", hdaR3StrFmtSDFIFOW, NULL);
5402	AssertRC(rc);
5403
5404	/*
5405	* Some debug assertions.
5406	*/
5407	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
5408	{
5409	struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
5410	struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
5411
5412	/* binary search order. */
5413	AssertReleaseMsg(!pNextReg \|\| pReg->offset + pReg->size <= pNextReg->offset,
5414	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5415	i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
5416
5417	/* alignment. */
5418	AssertReleaseMsg( pReg->size == 1
5419	\|\| (pReg->size == 2 && (pReg->offset & 1) == 0)
5420	\|\| (pReg->size == 3 && (pReg->offset & 3) == 0)
5421	\|\| (pReg->size == 4 && (pReg->offset & 3) == 0),
5422	("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5423
5424	/* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
5425	AssertRelease(((pReg->offset + pReg->size) & 3) == 0 \|\| pNextReg);
5426	if (pReg->offset & 3)
5427	{
5428	struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
5429	AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5430	if (pPrevReg)
5431	AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
5432	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5433	i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
5434	}
5435	#if 0
5436	if ((pReg->offset + pReg->size) & 3)
5437	{
5438	AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5439	if (pNextReg)
5440	AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
5441	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5442	i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
5443	}
5444	#endif
5445	/* The final entry is a full DWORD, no gaps! Allows shortcuts. */
5446	AssertReleaseMsg(pNextReg \|\| ((pReg->offset + pReg->size) & 3) == 0,
5447	("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5448	}
5449	}
5450
5451	# ifdef VBOX_WITH_STATISTICS
5452	if (RT_SUCCESS(rc))
5453	{
5454	/*
5455	* Register statistics.
5456	*/
5457	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaR3Timer.");
5458	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIn, STAMTYPE_PROFILE, "/Devices/HDA/Input", STAMUNIT_TICKS_PER_CALL, "Profiling input.");
5459	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatOut, STAMTYPE_PROFILE, "/Devices/HDA/Output", STAMUNIT_TICKS_PER_CALL, "Profiling output.");
5460	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
5461	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
5462	}
5463	# endif
5464
5465	LogFlowFuncLeaveRC(rc);
5466	return rc;
5467	}
5468
5469	/**
5470	* The device registration structure.
5471	*/
5472	const PDMDEVREG g_DeviceHDA =
5473	{
5474	/* u32Version */
5475	PDM_DEVREG_VERSION,
5476	/* szName */
5477	"hda",
5478	/* szRCMod */
5479	"VBoxDDRC.rc",
5480	/* szR0Mod */
5481	"VBoxDDR0.r0",
5482	/* pszDescription */
5483	"Intel HD Audio Controller",
5484	/* fFlags */
5485	PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0,
5486	/* fClass */
5487	PDM_DEVREG_CLASS_AUDIO,
5488	/* cMaxInstances */
5489	1,
5490	/* cbInstance */
5491	sizeof(HDASTATE),
5492	/* pfnConstruct */
5493	hdaR3Construct,
5494	/* pfnDestruct */
5495	hdaR3Destruct,
5496	/* pfnRelocate */
5497	hdaR3Relocate,
5498	/* pfnMemSetup */
5499	NULL,
5500	/* pfnPowerOn */
5501	NULL,
5502	/* pfnReset */
5503	hdaR3Reset,
5504	/* pfnSuspend */
5505	NULL,
5506	/* pfnResume */
5507	NULL,
5508	/* pfnAttach */
5509	hdaR3Attach,
5510	/* pfnDetach */
5511	hdaR3Detach,
5512	/* pfnQueryInterface. */
5513	NULL,
5514	/* pfnInitComplete */
5515	NULL,
5516	/* pfnPowerOff */
5517	hdaR3PowerOff,
5518	/* pfnSoftReset */
5519	NULL,
5520	/* u32VersionEnd */
5521	PDM_DEVREG_VERSION
5522	};
5523
5524	#endif /* IN_RING3 */
5525	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5526

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source: vbox/trunk/src/VBox/Devices/Audio/DevHDA.cpp@ 75980

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