DevHDA.cpp@ 82362

Last change on this file since 82362 was 82345, checked in by vboxsync, 5 years ago
DevHDA,DevIchAc97: Moved the per-stream timers into the stream structures, dropping the ahTimers arrays in the device state structures. This eliminates bunch of unnecessary indexing and pThis parameter passing. bugref:9218
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1	/* $Id: DevHDA.cpp 82345 2019-12-03 14:40:21Z vboxsync $ */
2	/** @file
3	* DevHDA.cpp - VBox Intel HD Audio Controller.
4	*
5	* Implemented against the specifications found in "High Definition Audio
6	* Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7	* HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8	*/
9
10	/*
11	* Copyright (C) 2006-2019 Oracle Corporation
12	*
13	* This file is part of VirtualBox Open Source Edition (OSE), as
14	* available from http://www.virtualbox.org. This file is free software;
15	* you can redistribute it and/or modify it under the terms of the GNU
16	* General Public License (GPL) as published by the Free Software
17	* Foundation, in version 2 as it comes in the "COPYING" file of the
18	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20	*/
21
22
23	/*********************************************************************************************************************************
24	* Header Files *
25	*********************************************************************************************************************************/
26	#ifdef DEBUG_bird
27	# define RT_NO_STRICT /* I'm tried of this crap asserting on save and restore of Maverics guests. */
28	#endif
29	#define LOG_GROUP LOG_GROUP_DEV_HDA
30	#include <VBox/log.h>
31
32	#include <VBox/vmm/pdmdev.h>
33	#include <VBox/vmm/pdmaudioifs.h>
34	#include <VBox/version.h>
35	#include <VBox/AssertGuest.h>
36
37	#include <iprt/assert.h>
38	#include <iprt/asm.h>
39	#include <iprt/asm-math.h>
40	#include <iprt/file.h>
41	#include <iprt/list.h>
42	# include <iprt/string.h>
43	#ifdef IN_RING3
44	# include <iprt/mem.h>
45	# include <iprt/semaphore.h>
46	# include <iprt/uuid.h>
47	#endif
48
49	#include "VBoxDD.h"
50
51	#include "AudioMixBuffer.h"
52	#include "AudioMixer.h"
53
54	#include "DevHDA.h"
55	#include "DevHDACommon.h"
56
57	#include "HDACodec.h"
58	#include "HDAStream.h"
59	#include "HDAStreamMap.h"
60	#include "HDAStreamPeriod.h"
61
62	#include "DrvAudio.h"
63
64
65	/*********************************************************************************************************************************
66	* Defined Constants And Macros *
67	*********************************************************************************************************************************/
68	//#define HDA_AS_PCI_EXPRESS
69
70	/* Installs a DMA access handler (via PGM callback) to monitor
71	* HDA's DMA operations, that is, writing / reading audio stream data.
72	*
73	* !!! Note: Certain guests are that timing sensitive that when enabling !!!
74	* !!! such a handler will mess up audio completely (e.g. Windows 7). !!! */
75	//#define HDA_USE_DMA_ACCESS_HANDLER
76	#ifdef HDA_USE_DMA_ACCESS_HANDLER
77	# include <VBox/vmm/pgm.h>
78	#endif
79
80	/* Uses the DMA access handler to read the written DMA audio (output) data.
81	* Only valid if HDA_USE_DMA_ACCESS_HANDLER is set.
82	*
83	* Also see the note / warning for HDA_USE_DMA_ACCESS_HANDLER. */
84	//# define HDA_USE_DMA_ACCESS_HANDLER_WRITING
85
86	/* Useful to debug the device' timing. */
87	//#define HDA_DEBUG_TIMING
88
89	/* To debug silence coming from the guest in form of audio gaps.
90	* Very crude implementation for now. */
91	//#define HDA_DEBUG_SILENCE
92
93	#if defined(VBOX_WITH_HP_HDA)
94	/* HP Pavilion dv4t-1300 */
95	# define HDA_PCI_VENDOR_ID 0x103c
96	# define HDA_PCI_DEVICE_ID 0x30f7
97	#elif defined(VBOX_WITH_INTEL_HDA)
98	/* Intel HDA controller */
99	# define HDA_PCI_VENDOR_ID 0x8086
100	# define HDA_PCI_DEVICE_ID 0x2668
101	#elif defined(VBOX_WITH_NVIDIA_HDA)
102	/* nVidia HDA controller */
103	# define HDA_PCI_VENDOR_ID 0x10de
104	# define HDA_PCI_DEVICE_ID 0x0ac0
105	#else
106	# error "Please specify your HDA device vendor/device IDs"
107	#endif
108
109	/**
110	* Acquires the HDA lock.
111	*/
112	#define DEVHDA_LOCK(a_pDevIns, a_pThis) \
113	do { \
114	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
115	AssertRC(rcLock); \
116	} while (0)
117
118	/**
119	* Acquires the HDA lock or returns.
120	*/
121	#define DEVHDA_LOCK_RETURN(a_pDevIns, a_pThis, a_rcBusy) \
122	do { \
123	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, a_rcBusy); \
124	if (rcLock == VINF_SUCCESS) \
125	{ /* likely */ } \
126	else \
127	{ \
128	AssertRC(rcLock); \
129	return rcLock; \
130	} \
131	} while (0)
132
133	/**
134	* Acquires the HDA lock or returns.
135	*/
136	# define DEVHDA_LOCK_RETURN_VOID(a_pDevIns, a_pThis) \
137	do { \
138	int rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
139	if (rcLock == VINF_SUCCESS) \
140	{ /* likely */ } \
141	else \
142	{ \
143	AssertRC(rcLock); \
144	return; \
145	} \
146	} while (0)
147
148	/**
149	* Releases the HDA lock.
150	*/
151	#define DEVHDA_UNLOCK(a_pDevIns, a_pThis) \
152	do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
153
154	/**
155	* Acquires the TM lock and HDA lock, returns on failure.
156	*/
157	#define DEVHDA_LOCK_BOTH_RETURN(a_pDevIns, a_pThis, a_pStream, a_rcBusy) \
158	do { \
159	VBOXSTRICTRC rcLock = PDMDevHlpTimerLockClock2(pDevIns, (a_pStream)->hTimer, &(a_pThis)->CritSect, (a_rcBusy)); \
160	if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
161	{ /* likely */ } \
162	else \
163	return VBOXSTRICTRC_TODO(rcLock); \
164	} while (0)
165
166	/**
167	* Releases the HDA lock and TM lock.
168	*/
169	#define DEVHDA_UNLOCK_BOTH(a_pDevIns, a_pThis, a_pStream) \
170	PDMDevHlpTimerUnlockClock2(pDevIns, (a_pStream)->hTimer, &(a_pThis)->CritSect)
171
172
173	/*********************************************************************************************************************************
174	* Structures and Typedefs *
175	*********************************************************************************************************************************/
176
177	/**
178	* Structure defining a (host backend) driver stream.
179	* Each driver has its own instances of audio mixer streams, which then
180	* can go into the same (or even different) audio mixer sinks.
181	*/
182	typedef struct HDADRIVERSTREAM
183	{
184	/** Associated mixer handle. */
185	R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
186	} HDADRIVERSTREAM, *PHDADRIVERSTREAM;
187
188	#ifdef HDA_USE_DMA_ACCESS_HANDLER
189	/**
190	* Struct for keeping an HDA DMA access handler context.
191	*/
192	typedef struct HDADMAACCESSHANDLER
193	{
194	/** Node for storing this handler in our list in HDASTREAMSTATE. */
195	RTLISTNODER3 Node;
196	/** Pointer to stream to which this access handler is assigned to. */
197	R3PTRTYPE(PHDASTREAM) pStream;
198	/** Access handler type handle. */
199	PGMPHYSHANDLERTYPE hAccessHandlerType;
200	/** First address this handler uses. */
201	RTGCPHYS GCPhysFirst;
202	/** Last address this handler uses. */
203	RTGCPHYS GCPhysLast;
204	/** Actual BDLE address to handle. */
205	RTGCPHYS BDLEAddr;
206	/** Actual BDLE buffer size to handle. */
207	RTGCPHYS BDLESize;
208	/** Whether the access handler has been registered or not. */
209	bool fRegistered;
210	uint8_t Padding[3];
211	} HDADMAACCESSHANDLER, *PHDADMAACCESSHANDLER;
212	#endif
213
214	/**
215	* Struct for maintaining a host backend driver.
216	* This driver must be associated to one, and only one,
217	* HDA codec. The HDA controller does the actual multiplexing
218	* of HDA codec data to various host backend drivers then.
219	*
220	* This HDA device uses a timer in order to synchronize all
221	* read/write accesses across all attached LUNs / backends.
222	*/
223	typedef struct HDADRIVER
224	{
225	/** Node for storing this driver in our device driver list of HDASTATE. */
226	RTLISTNODER3 Node;
227	/** Pointer to HDA controller (state). */
228	R3PTRTYPE(PHDASTATE) pHDAState;
229	/** Driver flags. */
230	PDMAUDIODRVFLAGS fFlags;
231	uint8_t u32Padding0[2];
232	/** LUN to which this driver has been assigned. */
233	uint8_t uLUN;
234	/** Whether this driver is in an attached state or not. */
235	bool fAttached;
236	/** Pointer to attached driver base interface. */
237	R3PTRTYPE(PPDMIBASE) pDrvBase;
238	/** Audio connector interface to the underlying host backend. */
239	R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
240	/** Mixer stream for line input. */
241	HDADRIVERSTREAM LineIn;
242	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
243	/** Mixer stream for mic input. */
244	HDADRIVERSTREAM MicIn;
245	#endif
246	/** Mixer stream for front output. */
247	HDADRIVERSTREAM Front;
248	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
249	/** Mixer stream for center/LFE output. */
250	HDADRIVERSTREAM CenterLFE;
251	/** Mixer stream for rear output. */
252	HDADRIVERSTREAM Rear;
253	#endif
254	} HDADRIVER;
255
256
257	/*********************************************************************************************************************************
258	* Internal Functions *
259	*********************************************************************************************************************************/
260	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
261	#ifdef IN_RING3
262	static void hdaR3GCTLReset(PHDASTATE pThis);
263	#endif
264
265	/** @name Register read/write stubs.
266	* @{
267	*/
268	static int hdaRegReadUnimpl(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
269	static int hdaRegWriteUnimpl(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
270	/** @} */
271
272	/** @name Global register set read/write functions.
273	* @{
274	*/
275	static int hdaRegWriteGCTL(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
276	static int hdaRegReadLPIB(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
277	static int hdaRegReadWALCLK(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
278	static int hdaRegWriteCORBWP(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
279	static int hdaRegWriteCORBRP(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
280	static int hdaRegWriteCORBCTL(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
281	static int hdaRegWriteCORBSIZE(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
282	static int hdaRegWriteCORBSTS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
283	static int hdaRegWriteRINTCNT(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
284	static int hdaRegWriteRIRBWP(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
285	static int hdaRegWriteRIRBSTS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
286	static int hdaRegWriteSTATESTS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
287	static int hdaRegWriteIRS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
288	static int hdaRegReadIRS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
289	static int hdaRegWriteBase(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
290	/** @} */
291
292	/** @name {IOB}SDn write functions.
293	* @{
294	*/
295	static int hdaRegWriteSDCBL(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
296	static int hdaRegWriteSDCTL(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
297	static int hdaRegWriteSDSTS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
298	static int hdaRegWriteSDLVI(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
299	static int hdaRegWriteSDFIFOW(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
300	static int hdaRegWriteSDFIFOS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
301	static int hdaRegWriteSDFMT(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
302	static int hdaRegWriteSDBDPL(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
303	static int hdaRegWriteSDBDPU(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
304	/** @} */
305
306	/** @name Generic register read/write functions.
307	* @{
308	*/
309	static int hdaRegReadU32(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
310	static int hdaRegWriteU32(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
311	static int hdaRegReadU24(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
312	#ifdef IN_RING3
313	static int hdaRegWriteU24(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
314	#endif
315	static int hdaRegReadU16(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
316	static int hdaRegWriteU16(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
317	static int hdaRegReadU8(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
318	static int hdaRegWriteU8(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
319	/** @} */
320
321	/** @name HDA device functions.
322	* @{
323	*/
324	#ifdef IN_RING3
325	static int hdaR3AddStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg);
326	static int hdaR3RemoveStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg);
327	# ifdef HDA_USE_DMA_ACCESS_HANDLER
328	static DECLCALLBACK(VBOXSTRICTRC) hdaR3DMAAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys,
329	void *pvBuf, size_t cbBuf,
330	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser);
331	# endif
332	#endif /* IN_RING3 */
333	/** @} */
334
335	/** @name HDA mixer functions.
336	* @{
337	*/
338	#ifdef IN_RING3
339	static int hdaR3MixerAddDrvStream(PHDASTATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg, PHDADRIVER pDrv);
340	#endif
341	/** @} */
342
343	#ifdef IN_RING3
344	static FNSSMFIELDGETPUT hdaR3GetPutTrans_HDABDLEDESC_fFlags_6;
345	static FNSSMFIELDGETPUT hdaR3GetPutTrans_HDABDLE_Desc_fFlags_1thru4;
346	#endif
347
348
349	/*********************************************************************************************************************************
350	* Global Variables *
351	*********************************************************************************************************************************/
352
353	/** No register description (RD) flags defined. */
354	#define HDA_RD_FLAG_NONE 0
355	/** Writes to SD are allowed while RUN bit is set. */
356	#define HDA_RD_FLAG_SD_WRITE_RUN RT_BIT(0)
357
358	/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
359	#define HDA_REG_MAP_STRM(offset, name) \
360	/* offset size read mask write mask flags read callback write callback index + abbrev description */ \
361	/* ------- ------- ---------- ---------- ------------------------- -------------- ----------------- ----------------------------- ----------- */ \
362	/* Offset 0x80 (SD0) */ \
363	{ offset, 0x00003, 0x00FF001F, 0x00F0001F, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU24 , hdaRegWriteSDCTL , HDA_REG_IDX_STRM(name, CTL) , #name " Stream Descriptor Control" }, \
364	/* Offset 0x83 (SD0) */ \
365	{ offset + 0x3, 0x00001, 0x0000003C, 0x0000001C, HDA_RD_FLAG_SD_WRITE_RUN, hdaRegReadU8 , hdaRegWriteSDSTS , HDA_REG_IDX_STRM(name, STS) , #name " Status" }, \
366	/* Offset 0x84 (SD0) */ \
367	{ offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadLPIB, hdaRegWriteU32 , HDA_REG_IDX_STRM(name, LPIB) , #name " Link Position In Buffer" }, \
368	/* Offset 0x88 (SD0) */ \
369	{ offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDCBL , HDA_REG_IDX_STRM(name, CBL) , #name " Cyclic Buffer Length" }, \
370	/* Offset 0x8C (SD0) -- upper 8 bits are reserved */ \
371	{ offset + 0xC, 0x00002, 0x0000FFFF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDLVI , HDA_REG_IDX_STRM(name, LVI) , #name " Last Valid Index" }, \
372	/* Reserved: FIFO Watermark. ** @todo Document this! */ \
373	{ offset + 0xE, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFIFOW, HDA_REG_IDX_STRM(name, FIFOW), #name " FIFO Watermark" }, \
374	/* Offset 0x90 (SD0) */ \
375	{ offset + 0x10, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFIFOS, HDA_REG_IDX_STRM(name, FIFOS), #name " FIFO Size" }, \
376	/* Offset 0x92 (SD0) */ \
377	{ offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteSDFMT , HDA_REG_IDX_STRM(name, FMT) , #name " Stream Format" }, \
378	/* Reserved: 0x94 - 0x98. */ \
379	/* Offset 0x98 (SD0) */ \
380	{ offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDBDPL , HDA_REG_IDX_STRM(name, BDPL) , #name " Buffer Descriptor List Pointer-Lower Base Address" }, \
381	/* Offset 0x9C (SD0) */ \
382	{ offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteSDBDPU , HDA_REG_IDX_STRM(name, BDPU) , #name " Buffer Descriptor List Pointer-Upper Base Address" }
383
384	/** Defines a single audio stream register set (e.g. OSD0). */
385	#define HDA_REG_MAP_DEF_STREAM(index, name) \
386	HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
387
388	/* See 302349 p 6.2. */
389	const HDAREGDESC g_aHdaRegMap[HDA_NUM_REGS] =
390	{
391	/* offset size read mask write mask flags read callback write callback index + abbrev */
392	/------- ------- ---------- ---------- ----------------- ---------------- ------------------- ------------------------ /
393	{ 0x00000, 0x00002, 0x0000FFFB, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(GCAP) }, /* Global Capabilities */
394	{ 0x00002, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMIN) }, /* Minor Version */
395	{ 0x00003, 0x00001, 0x000000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(VMAJ) }, /* Major Version */
396	{ 0x00004, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTPAY) }, /* Output Payload Capabilities */
397	{ 0x00006, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INPAY) }, /* Input Payload Capabilities */
398	{ 0x00008, 0x00004, 0x00000103, 0x00000103, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteGCTL , HDA_REG_IDX(GCTL) }, /* Global Control */
399	{ 0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(WAKEEN) }, /* Wake Enable */
400	{ 0x0000e, 0x00002, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteSTATESTS, HDA_REG_IDX(STATESTS) }, /* State Change Status */
401	{ 0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadUnimpl, hdaRegWriteUnimpl , HDA_REG_IDX(GSTS) }, /* Global Status */
402	{ 0x00018, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteU16 , HDA_REG_IDX(OUTSTRMPAY) }, /* Output Stream Payload Capability */
403	{ 0x0001A, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , HDA_REG_IDX(INSTRMPAY) }, /* Input Stream Payload Capability */
404	{ 0x00020, 0x00004, 0xC00000FF, 0xC00000FF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(INTCTL) }, /* Interrupt Control */
405	{ 0x00024, 0x00004, 0xC00000FF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(INTSTS) }, /* Interrupt Status */
406	{ 0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadWALCLK, hdaRegWriteUnimpl , HDA_REG_IDX_NOMEM(WALCLK) }, /* Wall Clock Counter */
407	{ 0x00034, 0x00004, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(SSYNC) }, /* Stream Synchronization */
408	{ 0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBLBASE) }, /* CORB Lower Base Address */
409	{ 0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(CORBUBASE) }, /* CORB Upper Base Address */
410	{ 0x00048, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteCORBWP , HDA_REG_IDX(CORBWP) }, /* CORB Write Pointer */
411	{ 0x0004A, 0x00002, 0x000080FF, 0x00008000, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteCORBRP , HDA_REG_IDX(CORBRP) }, /* CORB Read Pointer */
412	{ 0x0004C, 0x00001, 0x00000003, 0x00000003, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBCTL , HDA_REG_IDX(CORBCTL) }, /* CORB Control */
413	{ 0x0004D, 0x00001, 0x00000001, 0x00000001, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBSTS , HDA_REG_IDX(CORBSTS) }, /* CORB Status */
414	{ 0x0004E, 0x00001, 0x000000F3, 0x00000003, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteCORBSIZE, HDA_REG_IDX(CORBSIZE) }, /* CORB Size */
415	{ 0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBLBASE) }, /* RIRB Lower Base Address */
416	{ 0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(RIRBUBASE) }, /* RIRB Upper Base Address */
417	{ 0x00058, 0x00002, 0x000000FF, 0x00008000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteRIRBWP , HDA_REG_IDX(RIRBWP) }, /* RIRB Write Pointer */
418	{ 0x0005A, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_FLAG_NONE, hdaRegReadU16 , hdaRegWriteRINTCNT , HDA_REG_IDX(RINTCNT) }, /* Response Interrupt Count */
419	{ 0x0005C, 0x00001, 0x00000007, 0x00000007, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteU8 , HDA_REG_IDX(RIRBCTL) }, /* RIRB Control */
420	{ 0x0005D, 0x00001, 0x00000005, 0x00000005, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteRIRBSTS , HDA_REG_IDX(RIRBSTS) }, /* RIRB Status */
421	{ 0x0005E, 0x00001, 0x000000F3, 0x00000000, HDA_RD_FLAG_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , HDA_REG_IDX(RIRBSIZE) }, /* RIRB Size */
422	{ 0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteU32 , HDA_REG_IDX(IC) }, /* Immediate Command */
423	{ 0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , HDA_REG_IDX(IR) }, /* Immediate Response */
424	{ 0x00068, 0x00002, 0x00000002, 0x00000002, HDA_RD_FLAG_NONE, hdaRegReadIRS , hdaRegWriteIRS , HDA_REG_IDX(IRS) }, /* Immediate Command Status */
425	{ 0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPLBASE) }, /* DMA Position Lower Base */
426	{ 0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_FLAG_NONE, hdaRegReadU32 , hdaRegWriteBase , HDA_REG_IDX(DPUBASE) }, /* DMA Position Upper Base */
427	/* 4 Serial Data In (SDI). */
428	HDA_REG_MAP_DEF_STREAM(0, SD0),
429	HDA_REG_MAP_DEF_STREAM(1, SD1),
430	HDA_REG_MAP_DEF_STREAM(2, SD2),
431	HDA_REG_MAP_DEF_STREAM(3, SD3),
432	/* 4 Serial Data Out (SDO). */
433	HDA_REG_MAP_DEF_STREAM(4, SD4),
434	HDA_REG_MAP_DEF_STREAM(5, SD5),
435	HDA_REG_MAP_DEF_STREAM(6, SD6),
436	HDA_REG_MAP_DEF_STREAM(7, SD7)
437	};
438
439	const HDAREGALIAS g_aHdaRegAliases[] =
440	{
441	{ 0x2084, HDA_REG_SD0LPIB },
442	{ 0x20a4, HDA_REG_SD1LPIB },
443	{ 0x20c4, HDA_REG_SD2LPIB },
444	{ 0x20e4, HDA_REG_SD3LPIB },
445	{ 0x2104, HDA_REG_SD4LPIB },
446	{ 0x2124, HDA_REG_SD5LPIB },
447	{ 0x2144, HDA_REG_SD6LPIB },
448	{ 0x2164, HDA_REG_SD7LPIB }
449	};
450
451	#ifdef IN_RING3
452
453	/** HDABDLEDESC field descriptors for the v7 saved state. */
454	static SSMFIELD const g_aSSMBDLEDescFields7[] =
455	{
456	SSMFIELD_ENTRY(HDABDLEDESC, u64BufAddr),
457	SSMFIELD_ENTRY(HDABDLEDESC, u32BufSize),
458	SSMFIELD_ENTRY(HDABDLEDESC, fFlags),
459	SSMFIELD_ENTRY_TERM()
460	};
461
462	/** HDABDLEDESC field descriptors for the v6 saved states. */
463	static SSMFIELD const g_aSSMBDLEDescFields6[] =
464	{
465	SSMFIELD_ENTRY(HDABDLEDESC, u64BufAddr),
466	SSMFIELD_ENTRY(HDABDLEDESC, u32BufSize),
467	SSMFIELD_ENTRY_CALLBACK(HDABDLEDESC, fFlags, hdaR3GetPutTrans_HDABDLEDESC_fFlags_6),
468	SSMFIELD_ENTRY_TERM()
469	};
470
471	/** HDABDLESTATE field descriptors for the v6+ saved state. */
472	static SSMFIELD const g_aSSMBDLEStateFields6[] =
473	{
474	SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
475	SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
476	SSMFIELD_ENTRY_OLD(FIFO, HDA_FIFO_MAX), /* Deprecated; now is handled in the stream's circular buffer. */
477	SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
478	SSMFIELD_ENTRY_TERM()
479	};
480
481	/** HDABDLESTATE field descriptors for the v7 saved state. */
482	static SSMFIELD const g_aSSMBDLEStateFields7[] =
483	{
484	SSMFIELD_ENTRY(HDABDLESTATE, u32BDLIndex),
485	SSMFIELD_ENTRY(HDABDLESTATE, cbBelowFIFOW),
486	SSMFIELD_ENTRY(HDABDLESTATE, u32BufOff),
487	SSMFIELD_ENTRY_TERM()
488	};
489
490	/** HDASTREAMSTATE field descriptors for the v6 saved state. */
491	static SSMFIELD const g_aSSMStreamStateFields6[] =
492	{
493	SSMFIELD_ENTRY_OLD(cBDLE, sizeof(uint16_t)), /* Deprecated. */
494	SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
495	SSMFIELD_ENTRY_OLD(fStop, 1), /* Deprecated; see SSMR3PutBool(). */
496	SSMFIELD_ENTRY_OLD(fRunning, 1), /* Deprecated; using the HDA_SDCTL_RUN bit is sufficient. */
497	SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
498	SSMFIELD_ENTRY_TERM()
499	};
500
501	/** HDASTREAMSTATE field descriptors for the v7 saved state. */
502	static SSMFIELD const g_aSSMStreamStateFields7[] =
503	{
504	SSMFIELD_ENTRY(HDASTREAMSTATE, uCurBDLE),
505	SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
506	SSMFIELD_ENTRY(HDASTREAMSTATE, tsTransferNext),
507	SSMFIELD_ENTRY_TERM()
508	};
509
510	/** HDASTREAMPERIOD field descriptors for the v7 saved state. */
511	static SSMFIELD const g_aSSMStreamPeriodFields7[] =
512	{
513	SSMFIELD_ENTRY(HDASTREAMPERIOD, u64StartWalClk),
514	SSMFIELD_ENTRY(HDASTREAMPERIOD, u64ElapsedWalClk),
515	SSMFIELD_ENTRY(HDASTREAMPERIOD, framesTransferred),
516	SSMFIELD_ENTRY(HDASTREAMPERIOD, cIntPending),
517	SSMFIELD_ENTRY_TERM()
518	};
519
520	/** HDABDLE field descriptors for the v1 thru v4 saved states. */
521	static SSMFIELD const g_aSSMStreamBdleFields1234[] =
522	{
523	SSMFIELD_ENTRY(HDABDLE, Desc.u64BufAddr), /* u64BdleCviAddr */
524	SSMFIELD_ENTRY_OLD(u32BdleMaxCvi, sizeof(uint32_t)), /* u32BdleMaxCvi */
525	SSMFIELD_ENTRY(HDABDLE, State.u32BDLIndex), /* u32BdleCvi */
526	SSMFIELD_ENTRY(HDABDLE, Desc.u32BufSize), /* u32BdleCviLen */
527	SSMFIELD_ENTRY(HDABDLE, State.u32BufOff), /* u32BdleCviPos */
528	SSMFIELD_ENTRY_CALLBACK(HDABDLE, Desc.fFlags, hdaR3GetPutTrans_HDABDLE_Desc_fFlags_1thru4), /* fBdleCviIoc */
529	SSMFIELD_ENTRY(HDABDLE, State.cbBelowFIFOW), /* cbUnderFifoW */
530	SSMFIELD_ENTRY_OLD(au8FIFO, 256), /* au8FIFO */
531	SSMFIELD_ENTRY_TERM()
532	};
533
534	/**
535	* 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
536	*/
537	static uint32_t const g_afMasks[5] =
538	{
539	UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
540	};
541
542	#endif /* IN_RING3 */
543
544
545
546	/**
547	* Retrieves the number of bytes of a FIFOW register.
548	*
549	* @return Number of bytes of a given FIFOW register.
550	*/
551	DECLINLINE(uint8_t) hdaSDFIFOWToBytes(uint32_t u32RegFIFOW)
552	{
553	uint32_t cb;
554	switch (u32RegFIFOW)
555	{
556	case HDA_SDFIFOW_8B: cb = 8; break;
557	case HDA_SDFIFOW_16B: cb = 16; break;
558	case HDA_SDFIFOW_32B: cb = 32; break;
559	default: cb = 0; break;
560	}
561
562	Assert(RT_IS_POWER_OF_TWO(cb));
563	return cb;
564	}
565
566	#ifdef IN_RING3
567	/**
568	* Reschedules pending interrupts for all audio streams which have complete
569	* audio periods but did not have the chance to issue their (pending) interrupts yet.
570	*
571	* @param pThis The HDA device state.
572	*/
573	static void hdaR3ReschedulePendingInterrupts(PHDASTATE pThis)
574	{
575	bool fInterrupt = false;
576
577	for (uint8_t i = 0; i < HDA_MAX_STREAMS; ++i)
578	{
579	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, i);
580	if (!pStream)
581	continue;
582
583	if ( hdaR3StreamPeriodIsComplete (&pStream->State.Period)
584	&& hdaR3StreamPeriodNeedsInterrupt(&pStream->State.Period)
585	&& hdaR3WalClkSet(pThis, hdaR3StreamPeriodGetAbsElapsedWalClk(&pStream->State.Period), false /* fForce */))
586	{
587	fInterrupt = true;
588	break;
589	}
590	}
591
592	LogFunc(("fInterrupt=%RTbool\n", fInterrupt));
593
594	HDA_PROCESS_INTERRUPT(pThis->pDevInsR3, pThis);
595	}
596	#endif /* IN_RING3 */
597
598	/**
599	* Looks up a register at the exact offset given by @a offReg.
600	*
601	* @returns Register index on success, -1 if not found.
602	* @param offReg The register offset.
603	*/
604	static int hdaRegLookup(uint32_t offReg)
605	{
606	/*
607	* Aliases.
608	*/
609	if (offReg >= g_aHdaRegAliases[0].offReg)
610	{
611	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
612	if (offReg == g_aHdaRegAliases[i].offReg)
613	return g_aHdaRegAliases[i].idxAlias;
614	Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
615	return -1;
616	}
617
618	/*
619	* Binary search the
620	*/
621	int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
622	int idxLow = 0;
623	for (;;)
624	{
625	int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
626	if (offReg < g_aHdaRegMap[idxMiddle].offset)
627	{
628	if (idxLow == idxMiddle)
629	break;
630	idxEnd = idxMiddle;
631	}
632	else if (offReg > g_aHdaRegMap[idxMiddle].offset)
633	{
634	idxLow = idxMiddle + 1;
635	if (idxLow >= idxEnd)
636	break;
637	}
638	else
639	return idxMiddle;
640	}
641
642	#ifdef RT_STRICT
643	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
644	Assert(g_aHdaRegMap[i].offset != offReg);
645	#endif
646	return -1;
647	}
648
649	#ifdef IN_RING3
650
651	/**
652	* Looks up a register covering the offset given by @a offReg.
653	*
654	* @returns Register index on success, -1 if not found.
655	* @param offReg The register offset.
656	*/
657	static int hdaR3RegLookupWithin(uint32_t offReg)
658	{
659	/*
660	* Aliases.
661	*/
662	if (offReg >= g_aHdaRegAliases[0].offReg)
663	{
664	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
665	{
666	uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
667	if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].size)
668	return g_aHdaRegAliases[i].idxAlias;
669	}
670	Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].offset < offReg);
671	return -1;
672	}
673
674	/*
675	* Binary search the register map.
676	*/
677	int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
678	int idxLow = 0;
679	for (;;)
680	{
681	int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
682	if (offReg < g_aHdaRegMap[idxMiddle].offset)
683	{
684	if (idxLow == idxMiddle)
685	break;
686	idxEnd = idxMiddle;
687	}
688	else if (offReg >= g_aHdaRegMap[idxMiddle].offset + g_aHdaRegMap[idxMiddle].size)
689	{
690	idxLow = idxMiddle + 1;
691	if (idxLow >= idxEnd)
692	break;
693	}
694	else
695	return idxMiddle;
696	}
697
698	# ifdef RT_STRICT
699	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
700	Assert(offReg - g_aHdaRegMap[i].offset >= g_aHdaRegMap[i].size);
701	# endif
702	return -1;
703	}
704
705
706	/**
707	* Synchronizes the CORB / RIRB buffers between internal <-> device state.
708	*
709	* @returns IPRT status code.
710	* @param pThis HDA state.
711	* @param fLocal Specify true to synchronize HDA state's CORB buffer with the device state,
712	* or false to synchronize the device state's RIRB buffer with the HDA state.
713	*
714	* @todo r=andy Break this up into two functions?
715	*/
716	static int hdaR3CmdSync(PHDASTATE pThis, bool fLocal)
717	{
718	int rc = VINF_SUCCESS;
719	if (fLocal)
720	{
721	if (pThis->u64CORBBase)
722	{
723	AssertPtr(pThis->pu32CorbBuf);
724	Assert(pThis->cbCorbBuf);
725
726	/** @todo r=bird: An explanation is required why PDMDevHlpPhysRead is used with
727	* the CORB and PDMDevHlpPCIPhysWrite with RIRB below. There are
728	* similar unexplained inconsistencies in DevHDACommon.cpp. */
729	rc = PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), pThis->u64CORBBase, pThis->pu32CorbBuf, pThis->cbCorbBuf);
730	Log(("hdaR3CmdSync/CORB: read %RGp LB %#x (%Rrc)\n", pThis->u64CORBBase, pThis->cbCorbBuf, rc));
731	AssertRCReturn(rc, rc);
732	}
733	}
734	else
735	{
736	if (pThis->u64RIRBBase)
737	{
738	AssertPtr(pThis->pu64RirbBuf);
739	Assert(pThis->cbRirbBuf);
740
741	rc = PDMDevHlpPCIPhysWrite(pThis->CTX_SUFF(pDevIns), pThis->u64RIRBBase, pThis->pu64RirbBuf, pThis->cbRirbBuf);
742	Log(("hdaR3CmdSync/RIRB: phys read %RGp LB %#x (%Rrc)\n", pThis->u64RIRBBase, pThis->pu64RirbBuf, rc));
743	AssertRCReturn(rc, rc);
744	}
745	}
746
747	# ifdef DEBUG_CMD_BUFFER
748	LogFunc(("fLocal=%RTbool\n", fLocal));
749
750	uint8_t i = 0;
751	do
752	{
753	LogFunc(("CORB%02x: ", i));
754	uint8_t j = 0;
755	do
756	{
757	const char *pszPrefix;
758	if ((i + j) == HDA_REG(pThis, CORBRP))
759	pszPrefix = "[R]";
760	else if ((i + j) == HDA_REG(pThis, CORBWP))
761	pszPrefix = "[W]";
762	else
763	pszPrefix = " "; /* three spaces */
764	Log((" %s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
765	j++;
766	} while (j < 8);
767	Log(("\n"));
768	i += 8;
769	} while(i != 0);
770
771	do
772	{
773	LogFunc(("RIRB%02x: ", i));
774	uint8_t j = 0;
775	do
776	{
777	const char *prefix;
778	if ((i + j) == HDA_REG(pThis, RIRBWP))
779	prefix = "[W]";
780	else
781	prefix = " ";
782	Log((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
783	} while (++j < 8);
784	Log(("\n"));
785	i += 8;
786	} while (i != 0);
787	# endif
788	return rc;
789	}
790
791	/**
792	* Processes the next CORB buffer command in the queue.
793	*
794	* This will invoke the HDA codec verb dispatcher.
795	*
796	* @returns IPRT status code.
797	* @param pThis HDA state.
798	*/
799	static int hdaR3CORBCmdProcess(PHDASTATE pThis)
800	{
801	uint8_t corbRp = HDA_REG(pThis, CORBRP);
802	uint8_t corbWp = HDA_REG(pThis, CORBWP);
803	uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
804
805	Log3Func(("CORB(RP:%x, WP:%x) RIRBWP:%x\n", corbRp, corbWp, rirbWp));
806
807	if (!(HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA))
808	{
809	LogFunc(("CORB DMA not active, skipping\n"));
810	return VINF_SUCCESS;
811	}
812
813	Assert(pThis->cbCorbBuf);
814
815	int rc = hdaR3CmdSync(pThis, true /* Sync from guest */);
816	AssertRCReturn(rc, rc);
817
818	uint16_t cIntCnt = HDA_REG(pThis, RINTCNT) & 0xff;
819
820	if (!cIntCnt) /* 0 means 256 interrupts. */
821	cIntCnt = HDA_MAX_RINTCNT;
822
823	Log3Func(("START CORB(RP:%x, WP:%x) RIRBWP:%x, RINTCNT:%RU8/%RU8\n",
824	corbRp, corbWp, rirbWp, pThis->u16RespIntCnt, cIntCnt));
825
826	while (corbRp != corbWp)
827	{
828	corbRp = (corbRp + 1) % (pThis->cbCorbBuf / HDA_CORB_ELEMENT_SIZE); /* Advance +1 as the first command(s) are at CORBWP + 1. */
829
830	uint32_t uCmd = pThis->pu32CorbBuf[corbRp];
831	uint64_t uResp = 0;
832
833	rc = pThis->pCodec->pfnLookup(pThis->pCodec, HDA_CODEC_CMD(uCmd, 0 /* Codec index */), &uResp);
834	if (RT_FAILURE(rc))
835	LogFunc(("Codec lookup failed with rc=%Rrc\n", rc));
836
837	Log3Func(("Codec verb %08x -> response %016lx\n", uCmd, uResp));
838
839	if ( (uResp & CODEC_RESPONSE_UNSOLICITED)
840	&& !(HDA_REG(pThis, GCTL) & HDA_GCTL_UNSOL))
841	{
842	LogFunc(("Unexpected unsolicited response.\n"));
843	HDA_REG(pThis, CORBRP) = corbRp;
844
845	/** @todo r=andy No CORB/RIRB syncing to guest required in that case? */
846	return rc;
847	}
848
849	rirbWp = (rirbWp + 1) % HDA_RIRB_SIZE;
850
851	pThis->pu64RirbBuf[rirbWp] = uResp;
852
853	pThis->u16RespIntCnt++;
854
855	bool fSendInterrupt = false;
856
857	if (pThis->u16RespIntCnt == cIntCnt) /* Response interrupt count reached? */
858	{
859	pThis->u16RespIntCnt = 0; /* Reset internal interrupt response counter. */
860
861	Log3Func(("Response interrupt count reached (%RU16)\n", pThis->u16RespIntCnt));
862	fSendInterrupt = true;
863
864	}
865	else if (corbRp == corbWp) /* Did we reach the end of the current command buffer? */
866	{
867	Log3Func(("Command buffer empty\n"));
868	fSendInterrupt = true;
869	}
870
871	if (fSendInterrupt)
872	{
873	if (HDA_REG(pThis, RIRBCTL) & HDA_RIRBCTL_RINTCTL) /* Response Interrupt Control (RINTCTL) enabled? */
874	{
875	HDA_REG(pThis, RIRBSTS) \|= HDA_RIRBSTS_RINTFL;
876
877	rc = HDA_PROCESS_INTERRUPT(pThis->pDevInsR3, pThis);
878	}
879	}
880	}
881
882	Log3Func(("END CORB(RP:%x, WP:%x) RIRBWP:%x, RINTCNT:%RU8/%RU8\n",
883	corbRp, corbWp, rirbWp, pThis->u16RespIntCnt, cIntCnt));
884
885	HDA_REG(pThis, CORBRP) = corbRp;
886	HDA_REG(pThis, RIRBWP) = rirbWp;
887
888	rc = hdaR3CmdSync(pThis, false /* Sync to guest */);
889	AssertRCReturn(rc, rc);
890
891	if (RT_FAILURE(rc))
892	AssertRCReturn(rc, rc);
893
894	return rc;
895	}
896
897	#endif /* IN_RING3 */
898
899	/* Register access handlers. */
900
901	static int hdaRegReadUnimpl(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
902	{
903	RT_NOREF(pDevIns, pThis, iReg);
904	*pu32Value = 0;
905	return VINF_SUCCESS;
906	}
907
908	static int hdaRegWriteUnimpl(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
909	{
910	RT_NOREF(pDevIns, pThis, iReg, u32Value);
911	return VINF_SUCCESS;
912	}
913
914	/* U8 */
915	static int hdaRegReadU8(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
916	{
917	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffffff00) == 0);
918	return hdaRegReadU32(pDevIns, pThis, iReg, pu32Value);
919	}
920
921	static int hdaRegWriteU8(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
922	{
923	Assert((u32Value & 0xffffff00) == 0);
924	return hdaRegWriteU32(pDevIns, pThis, iReg, u32Value);
925	}
926
927	/* U16 */
928	static int hdaRegReadU16(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
929	{
930	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xffff0000) == 0);
931	return hdaRegReadU32(pDevIns, pThis, iReg, pu32Value);
932	}
933
934	static int hdaRegWriteU16(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
935	{
936	Assert((u32Value & 0xffff0000) == 0);
937	return hdaRegWriteU32(pDevIns, pThis, iReg, u32Value);
938	}
939
940	/* U24 */
941	static int hdaRegReadU24(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
942	{
943	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].mem_idx] & g_aHdaRegMap[iReg].readable) & 0xff000000) == 0);
944	return hdaRegReadU32(pDevIns, pThis, iReg, pu32Value);
945	}
946
947	#ifdef IN_RING3
948	static int hdaRegWriteU24(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
949	{
950	Assert((u32Value & 0xff000000) == 0);
951	return hdaRegWriteU32(pDevIns, pThis, iReg, u32Value);
952	}
953	#endif
954
955	/* U32 */
956	static int hdaRegReadU32(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
957	{
958	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
959
960	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_READ);
961
962	*pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].readable;
963
964	DEVHDA_UNLOCK(pDevIns, pThis);
965	return VINF_SUCCESS;
966	}
967
968	static int hdaRegWriteU32(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
969	{
970	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
971
972	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE);
973
974	pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].writable)
975	\| (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].writable);
976	DEVHDA_UNLOCK(pDevIns, pThis);
977	return VINF_SUCCESS;
978	}
979
980	static int hdaRegWriteGCTL(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
981	{
982	RT_NOREF_PV(iReg);
983	#ifdef IN_RING3
984	DEVHDA_LOCK(pDevIns, pThis);
985	#else
986	if (!(u32Value & HDA_GCTL_CRST))
987	return VINF_IOM_R3_MMIO_WRITE;
988	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE);
989	#endif
990
991	if (u32Value & HDA_GCTL_CRST)
992	{
993	/* Set the CRST bit to indicate that we're leaving reset mode. */
994	HDA_REG(pThis, GCTL) \|= HDA_GCTL_CRST;
995	LogFunc(("Guest leaving HDA reset\n"));
996	}
997	else
998	{
999	#ifdef IN_RING3
1000	/* Enter reset state. */
1001	LogFunc(("Guest entering HDA reset with DMA(RIRB:%s, CORB:%s)\n",
1002	HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA ? "on" : "off",
1003	HDA_REG(pThis, RIRBCTL) & HDA_RIRBCTL_RDMAEN ? "on" : "off"));
1004
1005	/* Clear the CRST bit to indicate that we're in reset state. */
1006	HDA_REG(pThis, GCTL) &= ~HDA_GCTL_CRST;
1007
1008	hdaR3GCTLReset(pThis);
1009	#else
1010	AssertFailedReturnStmt(DEVHDA_UNLOCK(pDevIns, pThis), VINF_IOM_R3_MMIO_WRITE);
1011	#endif
1012	}
1013
1014	if (u32Value & HDA_GCTL_FCNTRL)
1015	{
1016	/* Flush: GSTS:1 set, see 6.2.6. */
1017	HDA_REG(pThis, GSTS) \|= HDA_GSTS_FSTS; /* Set the flush status. */
1018	/* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
1019	}
1020
1021	DEVHDA_UNLOCK(pDevIns, pThis);
1022	return VINF_SUCCESS;
1023	}
1024
1025	static int hdaRegWriteSTATESTS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1026	{
1027	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE);
1028
1029	uint32_t v = HDA_REG_IND(pThis, iReg);
1030	uint32_t nv = u32Value & HDA_STATESTS_SCSF_MASK;
1031
1032	HDA_REG(pThis, STATESTS) &= ~(v & nv); /* Write of 1 clears corresponding bit. */
1033
1034	DEVHDA_UNLOCK(pDevIns, pThis);
1035	return VINF_SUCCESS;
1036	}
1037
1038	static int hdaRegReadLPIB(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1039	{
1040	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_READ);
1041
1042	const uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
1043	uint32_t u32LPIB = HDA_STREAM_REG(pThis, LPIB, uSD);
1044	#ifdef LOG_ENABLED
1045	const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, uSD);
1046	LogFlowFunc(("[SD%RU8] LPIB=%RU32, CBL=%RU32\n", uSD, u32LPIB, u32CBL));
1047	#endif
1048
1049	*pu32Value = u32LPIB;
1050
1051	DEVHDA_UNLOCK(pDevIns, pThis);
1052	return VINF_SUCCESS;
1053	}
1054
1055	#ifdef IN_RING3
1056	/**
1057	* Returns the current maximum value the wall clock counter can be set to.
1058	* This maximum value depends on all currently handled HDA streams and their own current timing.
1059	*
1060	* @return Current maximum value the wall clock counter can be set to.
1061	* @param pThis HDA state.
1062	*
1063	* @remark Does not actually set the wall clock counter.
1064	*/
1065	static uint64_t hdaR3WalClkGetMax(PHDASTATE pThis)
1066	{
1067	const uint64_t u64WalClkCur = ASMAtomicReadU64(&pThis->u64WalClk);
1068	const uint64_t u64FrontAbsWalClk = pThis->SinkFront.pStream
1069	? hdaR3StreamPeriodGetAbsElapsedWalClk(&pThis->SinkFront.pStream->State.Period) : 0;
1070	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1071	# error "Implement me!"
1072	# endif
1073	const uint64_t u64LineInAbsWalClk = pThis->SinkLineIn.pStream
1074	? hdaR3StreamPeriodGetAbsElapsedWalClk(&pThis->SinkLineIn.pStream->State.Period) : 0;
1075	# ifdef VBOX_WITH_HDA_MIC_IN
1076	const uint64_t u64MicInAbsWalClk = pThis->SinkMicIn.pStream
1077	? hdaR3StreamPeriodGetAbsElapsedWalClk(&pThis->SinkMicIn.pStream->State.Period) : 0;
1078	# endif
1079
1080	uint64_t u64WalClkNew = RT_MAX(u64WalClkCur, u64FrontAbsWalClk);
1081	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1082	# error "Implement me!"
1083	# endif
1084	u64WalClkNew = RT_MAX(u64WalClkNew, u64LineInAbsWalClk);
1085	# ifdef VBOX_WITH_HDA_MIC_IN
1086	u64WalClkNew = RT_MAX(u64WalClkNew, u64MicInAbsWalClk);
1087	# endif
1088
1089	Log3Func(("%RU64 -> Front=%RU64, LineIn=%RU64 -> %RU64\n",
1090	u64WalClkCur, u64FrontAbsWalClk, u64LineInAbsWalClk, u64WalClkNew));
1091
1092	return u64WalClkNew;
1093	}
1094	#endif /* IN_RING3 */
1095
1096	static int hdaRegReadWALCLK(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1097	{
1098	#ifdef IN_RING3
1099	RT_NOREF(iReg);
1100
1101	DEVHDA_LOCK(pDevIns, pThis);
1102
1103	*pu32Value = RT_LO_U32(ASMAtomicReadU64(&pThis->u64WalClk));
1104
1105	Log3Func(("%RU32 (max @ %RU64)\n",*pu32Value, hdaR3WalClkGetMax(pThis)));
1106
1107	DEVHDA_UNLOCK(pDevIns, pThis);
1108	return VINF_SUCCESS;
1109	#else
1110	RT_NOREF(pDevIns, pThis, iReg, pu32Value);
1111	return VINF_IOM_R3_MMIO_READ;
1112	#endif
1113	}
1114
1115	static int hdaRegWriteCORBRP(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1116	{
1117	RT_NOREF(iReg);
1118	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE);
1119
1120	if (u32Value & HDA_CORBRP_RST)
1121	{
1122	/* Do a CORB reset. */
1123	if (pThis->cbCorbBuf)
1124	{
1125	#ifdef IN_RING3
1126	Assert(pThis->pu32CorbBuf);
1127	RT_BZERO((void *)pThis->pu32CorbBuf, pThis->cbCorbBuf);
1128	#else
1129	DEVHDA_UNLOCK(pDevIns, pThis);
1130	return VINF_IOM_R3_MMIO_WRITE;
1131	#endif
1132	}
1133
1134	LogRel2(("HDA: CORB reset\n"));
1135
1136	HDA_REG(pThis, CORBRP) = HDA_CORBRP_RST; /* Clears the pointer. */
1137	}
1138	else
1139	HDA_REG(pThis, CORBRP) &= ~HDA_CORBRP_RST; /* Only CORBRP_RST bit is writable. */
1140
1141	DEVHDA_UNLOCK(pDevIns, pThis);
1142	return VINF_SUCCESS;
1143	}
1144
1145	static int hdaRegWriteCORBCTL(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1146	{
1147	#ifdef IN_RING3
1148	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE);
1149
1150	int rc = hdaRegWriteU8(pDevIns, pThis, iReg, u32Value);
1151	AssertRC(rc);
1152
1153	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Start DMA engine. */
1154	{
1155	rc = hdaR3CORBCmdProcess(pThis);
1156	}
1157	else
1158	LogFunc(("CORB DMA not running, skipping\n"));
1159
1160	DEVHDA_UNLOCK(pDevIns, pThis);
1161	return rc;
1162	#else
1163	RT_NOREF(pDevIns, pThis, iReg, u32Value);
1164	return VINF_IOM_R3_MMIO_WRITE;
1165	#endif
1166	}
1167
1168	static int hdaRegWriteCORBSIZE(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1169	{
1170	#ifdef IN_RING3
1171	RT_NOREF(iReg);
1172	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE);
1173
1174	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
1175	{
1176	LogFunc(("CORB DMA is (still) running, skipping\n"));
1177
1178	DEVHDA_UNLOCK(pDevIns, pThis);
1179	return VINF_SUCCESS;
1180	}
1181
1182	u32Value = (u32Value & HDA_CORBSIZE_SZ);
1183
1184	uint16_t cEntries = HDA_CORB_SIZE; /* Set default. */
1185
1186	switch (u32Value)
1187	{
1188	case 0: /* 8 byte; 2 entries. */
1189	cEntries = 2;
1190	break;
1191
1192	case 1: /* 64 byte; 16 entries. */
1193	cEntries = 16;
1194	break;
1195
1196	case 2: /* 1 KB; 256 entries. */
1197	/* Use default size. */
1198	break;
1199
1200	default:
1201	LogRel(("HDA: Guest tried to set an invalid CORB size (0x%x), keeping default\n", u32Value));
1202	u32Value = 2;
1203	/* Use default size. */
1204	break;
1205	}
1206
1207	uint32_t cbCorbBuf = cEntries * HDA_CORB_ELEMENT_SIZE;
1208	Assert(cbCorbBuf <= HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE); /* Paranoia. */
1209
1210	if (cbCorbBuf != pThis->cbCorbBuf)
1211	{
1212	RT_BZERO(pThis->pu32CorbBuf, HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE); /* Clear CORB when setting a new size. */
1213	pThis->cbCorbBuf = cbCorbBuf;
1214	}
1215
1216	LogFunc(("CORB buffer size is now %RU32 bytes (%u entries)\n", pThis->cbCorbBuf, pThis->cbCorbBuf / HDA_CORB_ELEMENT_SIZE));
1217
1218	HDA_REG(pThis, CORBSIZE) = u32Value;
1219
1220	DEVHDA_UNLOCK(pDevIns, pThis);
1221	return VINF_SUCCESS;
1222	#else
1223	RT_NOREF(pDevIns, pThis, iReg, u32Value);
1224	return VINF_IOM_R3_MMIO_WRITE;
1225	#endif
1226	}
1227
1228	static int hdaRegWriteCORBSTS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1229	{
1230	RT_NOREF_PV(iReg);
1231	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE);
1232
1233	uint32_t v = HDA_REG(pThis, CORBSTS);
1234	HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1235
1236	DEVHDA_UNLOCK(pDevIns, pThis);
1237	return VINF_SUCCESS;
1238	}
1239
1240	static int hdaRegWriteCORBWP(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1241	{
1242	#ifdef IN_RING3
1243	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE);
1244
1245	int rc = hdaRegWriteU16(pDevIns, pThis, iReg, u32Value);
1246	AssertRCSuccess(rc);
1247
1248	rc = hdaR3CORBCmdProcess(pThis);
1249
1250	DEVHDA_UNLOCK(pDevIns, pThis);
1251	return rc;
1252	#else
1253	RT_NOREF(pDevIns, pThis, iReg, u32Value);
1254	return VINF_IOM_R3_MMIO_WRITE;
1255	#endif
1256	}
1257
1258	static int hdaRegWriteSDCBL(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1259	{
1260	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE);
1261
1262	int rc = hdaRegWriteU32(pDevIns, pThis, iReg, u32Value);
1263	AssertRCSuccess(rc);
1264
1265	DEVHDA_UNLOCK(pDevIns, pThis);
1266	return rc;
1267	}
1268
1269	static int hdaRegWriteSDCTL(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1270	{
1271	#ifdef IN_RING3
1272	/* Get the stream descriptor. */
1273	const uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
1274
1275	/*
1276	* Some guests write too much (that is, 32-bit with the top 8 bit being junk)
1277	* instead of 24-bit required for SDCTL. So just mask this here to be safe.
1278	*/
1279	u32Value &= 0x00ffffff;
1280
1281	/*
1282	* Extract the stream tag the guest wants to use for this specific
1283	* stream descriptor (SDn). This only can happen if the stream is in a non-running
1284	* state, so we're doing the lookup and assignment here.
1285	*
1286	* So depending on the guest OS, SD3 can use stream tag 4, for example.
1287	*/
1288	uint8_t uTag = (u32Value >> HDA_SDCTL_NUM_SHIFT) & HDA_SDCTL_NUM_MASK;
1289	ASSERT_GUEST_MSG_RETURN(uTag < RT_ELEMENTS(pThis->aTags),
1290	("SD%RU8: Invalid stream tag %RU8 (u32Value=%#x)!\n", uSD, uTag, u32Value),
1291	VINF_SUCCESS /* Always return success to the MMIO handler. */);
1292
1293	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
1294	ASSERT_GUEST_LOGREL_MSG_RETURN(pStream, ("Guest tried writing SDCTL (0x%x) to unhandled stream #%RU8\n", u32Value, uSD),
1295	VINF_SUCCESS /* Always return success to the MMIO handler. */);
1296
1297	const bool fRun = RT_BOOL(u32Value & HDA_SDCTL_RUN);
1298	const bool fReset = RT_BOOL(u32Value & HDA_SDCTL_SRST);
1299
1300	/**
1301	* @todo r=bird: Must reduce the time we holding the virtual sync
1302	* clock lock here!
1303	*/
1304	DEVHDA_LOCK_BOTH_RETURN(pDevIns, pThis, pStream, VINF_IOM_R3_MMIO_WRITE);
1305
1306	const bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_SDCTL_RUN);
1307	const bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_SDCTL_SRST);
1308
1309	/*LogFunc(("[SD%RU8] fRun=%RTbool, fInRun=%RTbool, fReset=%RTbool, fInReset=%RTbool, %R[sdctl]\n",
1310	uSD, fRun, fInRun, fReset, fInReset, u32Value));*/
1311	if (fInReset)
1312	{
1313	Assert(!fReset);
1314	Assert(!fInRun && !fRun);
1315
1316	/* Exit reset state. */
1317	ASMAtomicXchgBool(&pStream->State.fInReset, false);
1318
1319	/* Report that we're done resetting this stream by clearing SRST. */
1320	HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_SRST;
1321
1322	LogFunc(("[SD%RU8] Reset exit\n", uSD));
1323	}
1324	else if (fReset)
1325	{
1326	/* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
1327	Assert(!fInRun && !fRun);
1328
1329	LogFunc(("[SD%RU8] Reset enter\n", uSD));
1330
1331	hdaR3StreamLock(pStream);
1332
1333	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1334	hdaR3StreamAsyncIOLock(pStream);
1335	# endif
1336	/* Make sure to remove the run bit before doing the actual stream reset. */
1337	HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_RUN;
1338
1339	hdaR3StreamReset(pThis, pStream, pStream->u8SD);
1340
1341	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1342	hdaR3StreamAsyncIOUnlock(pStream);
1343	# endif
1344	hdaR3StreamUnlock(pStream);
1345	}
1346	else
1347	{
1348	/*
1349	* We enter here to change DMA states only.
1350	*/
1351	if (fInRun != fRun)
1352	{
1353	Assert(!fReset && !fInReset);
1354	LogFunc(("[SD%RU8] State changed (fRun=%RTbool)\n", uSD, fRun));
1355
1356	hdaR3StreamLock(pStream);
1357
1358	int rc2 = VINF_SUCCESS;
1359
1360	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1361	if (fRun)
1362	rc2 = hdaR3StreamAsyncIOCreate(pStream);
1363
1364	hdaR3StreamAsyncIOLock(pStream);
1365	# endif
1366	if (fRun)
1367	{
1368	if (hdaGetDirFromSD(uSD) == PDMAUDIODIR_OUT)
1369	{
1370	const uint8_t uStripeCtl = ((u32Value >> HDA_SDCTL_STRIPE_SHIFT) & HDA_SDCTL_STRIPE_MASK) + 1;
1371	LogFunc(("[SD%RU8] Using %RU8 SDOs (stripe control)\n", uSD, uStripeCtl));
1372	if (uStripeCtl > 1)
1373	LogRel2(("HDA: Warning: Striping output over more than one SDO for stream #%RU8 currently is not implemented " \
1374	"(%RU8 SDOs requested)\n", uSD, uStripeCtl));
1375	}
1376
1377	PHDATAG pTag = &pThis->aTags[uTag];
1378	AssertPtr(pTag);
1379
1380	LogFunc(("[SD%RU8] Using stream tag=%RU8\n", uSD, uTag));
1381
1382	/* Assign new values. */
1383	pTag->uTag = uTag;
1384	pTag->pStream = hdaGetStreamFromSD(pThis, uSD);
1385
1386	# ifdef LOG_ENABLED
1387	PDMAUDIOPCMPROPS Props;
1388	rc2 = hdaR3SDFMTToPCMProps(HDA_STREAM_REG(pThis, FMT, pStream->u8SD), &Props);
1389	AssertRC(rc2);
1390	LogFunc(("[SD%RU8] %RU32Hz, %RU8bit, %RU8 channel(s)\n",
1391	pStream->u8SD, Props.uHz, Props.cbSample * 8 /* Bit */, Props.cChannels));
1392	# endif
1393	/* (Re-)initialize the stream with current values. */
1394	rc2 = hdaR3StreamInit(pDevIns, pStream, pStream->u8SD);
1395	if ( RT_SUCCESS(rc2)
1396	/* Any vital stream change occurred so that we need to (re-)add the stream to our setup?
1397	* Otherwise just skip this, as this costs a lot of performance. */
1398	&& rc2 != VINF_NO_CHANGE)
1399	{
1400	/* Remove the old stream from the device setup. */
1401	rc2 = hdaR3RemoveStream(pThis, &pStream->State.Cfg);
1402	AssertRC(rc2);
1403
1404	/* Add the stream to the device setup. */
1405	rc2 = hdaR3AddStream(pThis, &pStream->State.Cfg);
1406	AssertRC(rc2);
1407	}
1408	}
1409
1410	if (RT_SUCCESS(rc2))
1411	{
1412	/* Enable/disable the stream. */
1413	rc2 = hdaR3StreamEnable(pStream, fRun /* fEnable */);
1414	AssertRC(rc2);
1415
1416	if (fRun)
1417	{
1418	/* Keep track of running streams. */
1419	pThis->cStreamsActive++;
1420
1421	/* (Re-)init the stream's period. */
1422	hdaR3StreamPeriodInit(&pStream->State.Period,
1423	pStream->u8SD, pStream->u16LVI, pStream->u32CBL, &pStream->State.Cfg);
1424
1425	/* Begin a new period for this stream. */
1426	rc2 = hdaR3StreamPeriodBegin(&pStream->State.Period, hdaWalClkGetCurrent(pThis)/* Use current wall clock time */);
1427	AssertRC(rc2);
1428
1429	uint64_t const tsNow = PDMDevHlpTimerGet(pDevIns, pStream->hTimer);
1430	rc2 = hdaR3TimerSet(pDevIns, pStream, tsNow + pStream->State.cTransferTicks, false /* fForce */, tsNow);
1431	AssertRC(rc2);
1432	}
1433	else
1434	{
1435	/* Keep track of running streams. */
1436	Assert(pThis->cStreamsActive);
1437	if (pThis->cStreamsActive)
1438	pThis->cStreamsActive--;
1439
1440	/* Make sure to (re-)schedule outstanding (delayed) interrupts. */
1441	hdaR3ReschedulePendingInterrupts(pThis);
1442
1443	/* Reset the period. */
1444	hdaR3StreamPeriodReset(&pStream->State.Period);
1445	}
1446	}
1447
1448	# ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
1449	hdaR3StreamAsyncIOUnlock(pStream);
1450	# endif
1451	/* Make sure to leave the lock before (eventually) starting the timer. */
1452	hdaR3StreamUnlock(pStream);
1453	}
1454	}
1455
1456	int rc2 = hdaRegWriteU24(pDevIns, pThis, iReg, u32Value);
1457	AssertRC(rc2);
1458
1459	DEVHDA_UNLOCK_BOTH(pDevIns, pThis, pStream);
1460	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1461	#else /* !IN_RING3 */
1462	RT_NOREF(pDevIns, pThis, iReg, u32Value);
1463	return VINF_IOM_R3_MMIO_WRITE;
1464	#endif /* !IN_RING3 */
1465	}
1466
1467	static int hdaRegWriteSDSTS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1468	{
1469	#ifdef IN_RING3
1470	const uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, STS, iReg);
1471	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
1472	ASSERT_GUEST_LOGREL_MSG_RETURN(pStream, ("Guest tried writing SDSTS (0x%x) to unhandled stream #%RU8\n", u32Value, uSD),
1473	VINF_SUCCESS);
1474
1475	/**
1476	* @todo r=bird: Must reduce the time we holding the virtual sync
1477	* clock lock here!
1478	*/
1479	DEVHDA_LOCK_BOTH_RETURN(pDevIns, pThis, pStream, VINF_IOM_R3_MMIO_WRITE);
1480
1481	hdaR3StreamLock(pStream);
1482
1483	uint32_t v = HDA_REG_IND(pThis, iReg);
1484
1485	/* Clear (zero) FIFOE, DESE and BCIS bits when writing 1 to it (6.2.33). */
1486	HDA_REG_IND(pThis, iReg) &= ~(u32Value & v);
1487
1488	/* Some guests tend to write SDnSTS even if the stream is not running.
1489	* So make sure to check if the RUN bit is set first. */
1490	const bool fRunning = pStream->State.fRunning;
1491
1492	Log3Func(("[SD%RU8] fRunning=%RTbool %R[sdsts]\n", pStream->u8SD, fRunning, v));
1493
1494	PHDASTREAMPERIOD pPeriod = &pStream->State.Period;
1495
1496	if (hdaR3StreamPeriodLock(pPeriod))
1497	{
1498	const bool fNeedsInterrupt = hdaR3StreamPeriodNeedsInterrupt(pPeriod);
1499	if (fNeedsInterrupt)
1500	hdaR3StreamPeriodReleaseInterrupt(pPeriod);
1501
1502	if (hdaR3StreamPeriodIsComplete(pPeriod))
1503	{
1504	/* Make sure to try to update the WALCLK register if a period is complete.
1505	* Use the maximum WALCLK value all (active) streams agree to. */
1506	const uint64_t uWalClkMax = hdaR3WalClkGetMax(pThis);
1507	if (uWalClkMax > hdaWalClkGetCurrent(pThis))
1508	hdaR3WalClkSet(pThis, uWalClkMax, false /* fForce */);
1509
1510	hdaR3StreamPeriodEnd(pPeriod);
1511
1512	if (fRunning)
1513	hdaR3StreamPeriodBegin(pPeriod, hdaWalClkGetCurrent(pThis) /* Use current wall clock time */);
1514	}
1515
1516	hdaR3StreamPeriodUnlock(pPeriod); /* Unlock before processing interrupt. */
1517	}
1518
1519	HDA_PROCESS_INTERRUPT(pDevIns, pThis);
1520
1521	const uint64_t tsNow = PDMDevHlpTimerGet(pDevIns, pStream->hTimer);
1522	Assert(tsNow >= pStream->State.tsTransferLast);
1523
1524	const uint64_t cTicksElapsed = tsNow - pStream->State.tsTransferLast;
1525	# ifdef LOG_ENABLED
1526	const uint64_t cTicksTransferred = pStream->State.cbTransferProcessed * pStream->State.cTicksPerByte;
1527	# endif
1528
1529	uint64_t cTicksToNext = pStream->State.cTransferTicks;
1530	if (cTicksToNext) /* Only do any calculations if the stream currently is set up for transfers. */
1531	{
1532	Log3Func(("[SD%RU8] cTicksElapsed=%RU64, cTicksTransferred=%RU64, cTicksToNext=%RU64\n",
1533	pStream->u8SD, cTicksElapsed, cTicksTransferred, cTicksToNext));
1534
1535	Log3Func(("[SD%RU8] cbTransferProcessed=%RU32, cbTransferChunk=%RU32, cbTransferSize=%RU32\n",
1536	pStream->u8SD, pStream->State.cbTransferProcessed, pStream->State.cbTransferChunk, pStream->State.cbTransferSize));
1537
1538	if (cTicksElapsed <= cTicksToNext)
1539	cTicksToNext = cTicksToNext - cTicksElapsed;
1540	else /* Catch up. */
1541	{
1542	Log3Func(("[SD%RU8] Warning: Lagging behind (%RU64 ticks elapsed, maximum allowed is %RU64)\n",
1543	pStream->u8SD, cTicksElapsed, cTicksToNext));
1544
1545	LogRelMax2(64, ("HDA: Stream #%RU8 interrupt lagging behind (expected %uus, got %uus), trying to catch up ...\n",
1546	pStream->u8SD,
1547	(PDMDevHlpTimerGetFreq(pDevIns, pStream->hTimer) / pThis->uTimerHz) / 1000,
1548	(tsNow - pStream->State.tsTransferLast) / 1000));
1549
1550	cTicksToNext = 0;
1551	}
1552
1553	Log3Func(("[SD%RU8] -> cTicksToNext=%RU64\n", pStream->u8SD, cTicksToNext));
1554
1555	/* Reset processed data counter. */
1556	pStream->State.cbTransferProcessed = 0;
1557	pStream->State.tsTransferNext = tsNow + cTicksToNext;
1558
1559	/* Only re-arm the timer if there were pending transfer interrupts left
1560	* -- it could happen that we land in here if a guest writes to SDnSTS
1561	* unconditionally. */
1562	if (pStream->State.cTransferPendingInterrupts)
1563	{
1564	pStream->State.cTransferPendingInterrupts--;
1565
1566	/* Re-arm the timer. */
1567	LogFunc(("Timer set SD%RU8\n", pStream->u8SD));
1568	hdaR3TimerSet(pDevIns, pStream, tsNow + cTicksToNext, true /* fForce - we just set tsTransferNext/, 0 /tsNow*/);
1569	}
1570	}
1571
1572	hdaR3StreamUnlock(pStream);
1573
1574	DEVHDA_UNLOCK_BOTH(pDevIns, pThis, pStream);
1575	return VINF_SUCCESS;
1576	#else /* !IN_RING3 */
1577	RT_NOREF(pDevIns, pThis, iReg, u32Value);
1578	return VINF_IOM_R3_MMIO_WRITE;
1579	#endif /* !IN_RING3 */
1580	}
1581
1582	static int hdaRegWriteSDLVI(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1583	{
1584	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE);
1585
1586	const uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, LVI, iReg);
1587
1588	#ifdef HDA_USE_DMA_ACCESS_HANDLER
1589	if (hdaGetDirFromSD(uSD) == PDMAUDIODIR_OUT)
1590	{
1591	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
1592
1593	/* Try registering the DMA handlers.
1594	* As we can't be sure in which order LVI + BDL base are set, try registering in both routines. */
1595	if ( pStream
1596	&& hdaR3StreamRegisterDMAHandlers(pThis, pStream))
1597	{
1598	LogFunc(("[SD%RU8] DMA logging enabled\n", pStream->u8SD));
1599	}
1600	}
1601	#endif
1602
1603	ASSERT_GUEST_LOGREL_MSG(u32Value <= UINT8_MAX, /* Should be covered by the register write mask, but just to make sure. */
1604	("LVI for stream #%RU8 must not be bigger than %RU8\n", uSD, UINT8_MAX - 1));
1605
1606	int rc2 = hdaRegWriteU16(pDevIns, pThis, iReg, u32Value);
1607	AssertRC(rc2);
1608
1609	DEVHDA_UNLOCK(pDevIns, pThis);
1610	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1611	}
1612
1613	static int hdaRegWriteSDFIFOW(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1614	{
1615	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE);
1616
1617	uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg);
1618
1619	if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_IN) /* FIFOW for input streams only. */
1620	{
1621	#ifndef IN_RING0
1622	LogRel(("HDA: Warning: Guest tried to write read-only FIFOW to output stream #%RU8, ignoring\n", uSD));
1623	DEVHDA_UNLOCK(pDevIns, pThis);
1624	return VINF_SUCCESS;
1625	#else
1626	DEVHDA_UNLOCK(pDevIns, pThis);
1627	return VINF_IOM_R3_MMIO_WRITE;
1628	#endif
1629	}
1630
1631	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg));
1632	if (!pStream)
1633	{
1634	DEVHDA_UNLOCK(pDevIns, pThis);
1635	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1636	}
1637
1638	uint32_t u32FIFOW = 0;
1639
1640	switch (u32Value)
1641	{
1642	case HDA_SDFIFOW_8B:
1643	case HDA_SDFIFOW_16B:
1644	case HDA_SDFIFOW_32B:
1645	u32FIFOW = u32Value;
1646	break;
1647	default:
1648	ASSERT_GUEST_LOGREL_MSG_FAILED(("Guest tried writing unsupported FIFOW (0x%x) to stream #%RU8, defaulting to 32 bytes\n",
1649	u32Value, uSD));
1650	u32FIFOW = HDA_SDFIFOW_32B;
1651	break;
1652	}
1653
1654	if (u32FIFOW)
1655	{
1656	pStream->u16FIFOW = hdaSDFIFOWToBytes(u32FIFOW);
1657	LogFunc(("[SD%RU8] Updating FIFOW to %RU32 bytes\n", uSD, pStream->u16FIFOW));
1658
1659	int rc2 = hdaRegWriteU16(pDevIns, pThis, iReg, u32FIFOW);
1660	AssertRC(rc2);
1661	}
1662
1663	DEVHDA_UNLOCK(pDevIns, pThis);
1664	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1665	}
1666
1667	/**
1668	* @note This method could be called for changing value on Output Streams only (ICH6 datasheet 18.2.39).
1669	*/
1670	static int hdaRegWriteSDFIFOS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1671	{
1672	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE);
1673
1674	uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOS, iReg);
1675
1676	if (hdaGetDirFromSD(uSD) != PDMAUDIODIR_OUT) /* FIFOS for output streams only. */
1677	{
1678	ASSERT_GUEST_LOGREL_MSG_FAILED(("Guest tried writing read-only FIFOS to input stream #%RU8, ignoring\n", uSD));
1679	DEVHDA_UNLOCK(pDevIns, pThis);
1680	return VINF_SUCCESS;
1681	}
1682
1683	uint32_t u32FIFOS;
1684
1685	switch(u32Value)
1686	{
1687	case HDA_SDOFIFO_16B:
1688	case HDA_SDOFIFO_32B:
1689	case HDA_SDOFIFO_64B:
1690	case HDA_SDOFIFO_128B:
1691	case HDA_SDOFIFO_192B:
1692	case HDA_SDOFIFO_256B:
1693	u32FIFOS = u32Value;
1694	break;
1695
1696	default:
1697	ASSERT_GUEST_LOGREL_MSG_FAILED(("Guest tried writing unsupported FIFOS (0x%x) to stream #%RU8, defaulting to 192 bytes\n",
1698	u32Value, uSD));
1699	u32FIFOS = HDA_SDOFIFO_192B;
1700	break;
1701	}
1702
1703	int rc2 = hdaRegWriteU16(pDevIns, pThis, iReg, u32FIFOS);
1704	AssertRC(rc2);
1705
1706	DEVHDA_UNLOCK(pDevIns, pThis);
1707	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
1708	}
1709
1710	#ifdef IN_RING3
1711
1712	/**
1713	* Adds an audio output stream to the device setup using the given configuration.
1714	*
1715	* @returns IPRT status code.
1716	* @param pThis Device state.
1717	* @param pCfg Stream configuration to use for adding a stream.
1718	*/
1719	static int hdaR3AddStreamOut(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1720	{
1721	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1722	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1723
1724	AssertReturn(pCfg->enmDir == PDMAUDIODIR_OUT, VERR_INVALID_PARAMETER);
1725
1726	LogFlowFunc(("Stream=%s\n", pCfg->szName));
1727
1728	int rc = VINF_SUCCESS;
1729
1730	bool fUseFront = true; /* Always use front out by default. */
1731	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1732	bool fUseRear;
1733	bool fUseCenter;
1734	bool fUseLFE;
1735
1736	fUseRear = fUseCenter = fUseLFE = false;
1737
1738	/*
1739	* Use commonly used setups for speaker configurations.
1740	*/
1741
1742	/** @todo Make the following configurable through mixer API and/or CFGM? */
1743	switch (pCfg->Props.cChannels)
1744	{
1745	case 3: /* 2.1: Front (Stereo) + LFE. */
1746	{
1747	fUseLFE = true;
1748	break;
1749	}
1750
1751	case 4: /* Quadrophonic: Front (Stereo) + Rear (Stereo). */
1752	{
1753	fUseRear = true;
1754	break;
1755	}
1756
1757	case 5: /* 4.1: Front (Stereo) + Rear (Stereo) + LFE. */
1758	{
1759	fUseRear = true;
1760	fUseLFE = true;
1761	break;
1762	}
1763
1764	case 6: /* 5.1: Front (Stereo) + Rear (Stereo) + Center/LFE. */
1765	{
1766	fUseRear = true;
1767	fUseCenter = true;
1768	fUseLFE = true;
1769	break;
1770	}
1771
1772	default: /* Unknown; fall back to 2 front channels (stereo). */
1773	{
1774	rc = VERR_NOT_SUPPORTED;
1775	break;
1776	}
1777	}
1778	# endif /* !VBOX_WITH_AUDIO_HDA_51_SURROUND */
1779
1780	if (rc == VERR_NOT_SUPPORTED)
1781	{
1782	LogRel2(("HDA: Warning: Unsupported channel count (%RU8), falling back to stereo channels (2)\n", pCfg->Props.cChannels));
1783
1784	/* Fall back to 2 channels (see below in fUseFront block). */
1785	rc = VINF_SUCCESS;
1786	}
1787
1788	do
1789	{
1790	if (RT_FAILURE(rc))
1791	break;
1792
1793	if (fUseFront)
1794	{
1795	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Front");
1796
1797	pCfg->u.enmDst = PDMAUDIOPLAYBACKDST_FRONT;
1798	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1799
1800	pCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pCfg->Props.cbSample, pCfg->Props.cChannels);
1801
1802	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_FRONT, pCfg);
1803	}
1804
1805	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1806	if ( RT_SUCCESS(rc)
1807	&& (fUseCenter \|\| fUseLFE))
1808	{
1809	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Center/LFE");
1810
1811	pCfg->u.enmDst = PDMAUDIOPLAYBACKDST_CENTER_LFE;
1812	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1813
1814	pCfg->Props.cChannels = (fUseCenter && fUseLFE) ? 2 : 1;
1815	pCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pCfg->Props.cbSample, pCfg->Props.cChannels);
1816
1817	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_CENTER_LFE, pCfg);
1818	}
1819
1820	if ( RT_SUCCESS(rc)
1821	&& fUseRear)
1822	{
1823	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Rear");
1824
1825	pCfg->u.enmDst = PDMAUDIOPLAYBACKDST_REAR;
1826	pCfg->enmLayout = PDMAUDIOSTREAMLAYOUT_NON_INTERLEAVED;
1827
1828	pCfg->Props.cChannels = 2;
1829	pCfg->Props.cShift = PDMAUDIOPCMPROPS_MAKE_SHIFT_PARMS(pCfg->Props.cbSample, pCfg->Props.cChannels);
1830
1831	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_REAR, pCfg);
1832	}
1833	# endif /* VBOX_WITH_AUDIO_HDA_51_SURROUND */
1834
1835	} while (0);
1836
1837	LogFlowFuncLeaveRC(rc);
1838	return rc;
1839	}
1840
1841	/**
1842	* Adds an audio input stream to the device setup using the given configuration.
1843	*
1844	* @returns IPRT status code.
1845	* @param pThis Device state.
1846	* @param pCfg Stream configuration to use for adding a stream.
1847	*/
1848	static int hdaR3AddStreamIn(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1849	{
1850	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1851	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1852
1853	AssertReturn(pCfg->enmDir == PDMAUDIODIR_IN, VERR_INVALID_PARAMETER);
1854
1855	LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->u.enmSrc));
1856
1857	int rc;
1858
1859	switch (pCfg->u.enmSrc)
1860	{
1861	case PDMAUDIORECSRC_LINE:
1862	{
1863	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_LINE_IN, pCfg);
1864	break;
1865	}
1866	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
1867	case PDMAUDIORECSRC_MIC:
1868	{
1869	rc = hdaCodecAddStream(pThis->pCodec, PDMAUDIOMIXERCTL_MIC_IN, pCfg);
1870	break;
1871	}
1872	# endif
1873	default:
1874	rc = VERR_NOT_SUPPORTED;
1875	break;
1876	}
1877
1878	LogFlowFuncLeaveRC(rc);
1879	return rc;
1880	}
1881
1882	/**
1883	* Adds an audio stream to the device setup using the given configuration.
1884	*
1885	* @returns IPRT status code.
1886	* @param pThis Device state.
1887	* @param pCfg Stream configuration to use for adding a stream.
1888	*/
1889	static int hdaR3AddStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1890	{
1891	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1892	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1893
1894	int rc;
1895
1896	LogFlowFuncEnter();
1897
1898	switch (pCfg->enmDir)
1899	{
1900	case PDMAUDIODIR_OUT:
1901	rc = hdaR3AddStreamOut(pThis, pCfg);
1902	break;
1903
1904	case PDMAUDIODIR_IN:
1905	rc = hdaR3AddStreamIn(pThis, pCfg);
1906	break;
1907
1908	default:
1909	rc = VERR_NOT_SUPPORTED;
1910	AssertFailed();
1911	break;
1912	}
1913
1914	LogFlowFunc(("Returning %Rrc\n", rc));
1915
1916	return rc;
1917	}
1918
1919	/**
1920	* Removes an audio stream from the device setup using the given configuration.
1921	*
1922	* @returns IPRT status code.
1923	* @param pThis Device state.
1924	* @param pCfg Stream configuration to use for removing a stream.
1925	*/
1926	static int hdaR3RemoveStream(PHDASTATE pThis, PPDMAUDIOSTREAMCFG pCfg)
1927	{
1928	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
1929	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1930
1931	int rc = VINF_SUCCESS;
1932
1933	PDMAUDIOMIXERCTL enmMixerCtl = PDMAUDIOMIXERCTL_UNKNOWN;
1934	switch (pCfg->enmDir)
1935	{
1936	case PDMAUDIODIR_IN:
1937	{
1938	LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->u.enmSrc));
1939
1940	switch (pCfg->u.enmSrc)
1941	{
1942	case PDMAUDIORECSRC_UNKNOWN: break;
1943	case PDMAUDIORECSRC_LINE: enmMixerCtl = PDMAUDIOMIXERCTL_LINE_IN; break;
1944	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
1945	case PDMAUDIORECSRC_MIC: enmMixerCtl = PDMAUDIOMIXERCTL_MIC_IN; break;
1946	# endif
1947	default:
1948	rc = VERR_NOT_SUPPORTED;
1949	break;
1950	}
1951
1952	break;
1953	}
1954
1955	case PDMAUDIODIR_OUT:
1956	{
1957	LogFlowFunc(("Stream=%s, Source=%ld\n", pCfg->szName, pCfg->u.enmDst));
1958
1959	switch (pCfg->u.enmDst)
1960	{
1961	case PDMAUDIOPLAYBACKDST_UNKNOWN: break;
1962	case PDMAUDIOPLAYBACKDST_FRONT: enmMixerCtl = PDMAUDIOMIXERCTL_FRONT; break;
1963	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1964	case PDMAUDIOPLAYBACKDST_CENTER_LFE: enmMixerCtl = PDMAUDIOMIXERCTL_CENTER_LFE; break;
1965	case PDMAUDIOPLAYBACKDST_REAR: enmMixerCtl = PDMAUDIOMIXERCTL_REAR; break;
1966	# endif
1967	default:
1968	rc = VERR_NOT_SUPPORTED;
1969	break;
1970	}
1971	break;
1972	}
1973
1974	default:
1975	rc = VERR_NOT_SUPPORTED;
1976	break;
1977	}
1978
1979	if ( RT_SUCCESS(rc)
1980	&& enmMixerCtl != PDMAUDIOMIXERCTL_UNKNOWN)
1981	{
1982	rc = hdaCodecRemoveStream(pThis->pCodec, enmMixerCtl);
1983	}
1984
1985	LogFlowFuncLeaveRC(rc);
1986	return rc;
1987	}
1988	#endif /* IN_RING3 */
1989
1990	static int hdaRegWriteSDFMT(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1991	{
1992	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE);
1993
1994	/* Write the wanted stream format into the register in any case.
1995	*
1996	* This is important for e.g. MacOS guests, as those try to initialize streams which are not reported
1997	* by the device emulation (wants 4 channels, only have 2 channels at the moment).
1998	*
1999	* When ignoring those (invalid) formats, this leads to MacOS thinking that the device is malfunctioning
2000	* and therefore disabling the device completely. */
2001	int rc = hdaRegWriteU16(pDevIns, pThis, iReg, u32Value);
2002	AssertRC(rc);
2003
2004	DEVHDA_UNLOCK(pDevIns, pThis);
2005	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2006	}
2007
2008	/* Note: Will be called for both, BDPL and BDPU, registers. */
2009	DECLINLINE(int) hdaRegWriteSDBDPX(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value, uint8_t uSD)
2010	{
2011	#ifdef IN_RING3
2012	DEVHDA_LOCK(pDevIns, pThis);
2013
2014	# ifdef HDA_USE_DMA_ACCESS_HANDLER
2015	if (hdaGetDirFromSD(uSD) == PDMAUDIODIR_OUT)
2016	{
2017	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
2018
2019	/* Try registering the DMA handlers.
2020	* As we can't be sure in which order LVI + BDL base are set, try registering in both routines. */
2021	if ( pStream
2022	&& hdaR3StreamRegisterDMAHandlers(pThis, pStream))
2023	{
2024	LogFunc(("[SD%RU8] DMA logging enabled\n", pStream->u8SD));
2025	}
2026	}
2027	# else
2028	RT_NOREF(uSD);
2029	# endif
2030
2031	int rc2 = hdaRegWriteU32(pDevIns, pThis, iReg, u32Value);
2032	AssertRC(rc2);
2033
2034	DEVHDA_UNLOCK(pDevIns, pThis);
2035	return VINF_SUCCESS; /* Always return success to the MMIO handler. */
2036	#else /* !IN_RING3 */
2037	RT_NOREF(pDevIns, pThis, iReg, u32Value, uSD);
2038	return VINF_IOM_R3_MMIO_WRITE;
2039	#endif /* !IN_RING3 */
2040	}
2041
2042	static int hdaRegWriteSDBDPL(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2043	{
2044	return hdaRegWriteSDBDPX(pDevIns, pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPL, iReg));
2045	}
2046
2047	static int hdaRegWriteSDBDPU(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2048	{
2049	return hdaRegWriteSDBDPX(pDevIns, pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPU, iReg));
2050	}
2051
2052	static int hdaRegReadIRS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2053	{
2054	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_READ);
2055
2056	/* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
2057	if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2058	\|\| (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA))
2059	{
2060	HDA_REG(pThis, IRS) = HDA_IRS_ICB; /* busy */
2061	}
2062
2063	int rc = hdaRegReadU32(pDevIns, pThis, iReg, pu32Value);
2064	DEVHDA_UNLOCK(pDevIns, pThis);
2065
2066	return rc;
2067	}
2068
2069	static int hdaRegWriteIRS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2070	{
2071	RT_NOREF_PV(iReg);
2072	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE);
2073
2074	/*
2075	* If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
2076	* write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
2077	*/
2078	if ( (u32Value & HDA_IRS_ICB)
2079	&& !(HDA_REG(pThis, IRS) & HDA_IRS_ICB))
2080	{
2081	#ifdef IN_RING3
2082	uint32_t uCmd = HDA_REG(pThis, IC);
2083
2084	if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
2085	{
2086	DEVHDA_UNLOCK(pDevIns, pThis);
2087
2088	/*
2089	* 3.4.3: Defines behavior of immediate Command status register.
2090	*/
2091	LogRel(("HDA: Guest attempted process immediate verb (%x) with active CORB\n", uCmd));
2092	return VINF_SUCCESS;
2093	}
2094
2095	HDA_REG(pThis, IRS) = HDA_IRS_ICB; /* busy */
2096
2097	uint64_t uResp;
2098	int rc2 = pThis->pCodec->pfnLookup(pThis->pCodec,
2099	HDA_CODEC_CMD(uCmd, 0 /* LUN */), &uResp);
2100	if (RT_FAILURE(rc2))
2101	LogFunc(("Codec lookup failed with rc2=%Rrc\n", rc2));
2102
2103	HDA_REG(pThis, IR) = (uint32_t)uResp; /** @todo r=andy Do we need a 64-bit response? */
2104	HDA_REG(pThis, IRS) = HDA_IRS_IRV; /* result is ready */
2105	/** @todo r=michaln We just set the IRS value, why are we clearing unset bits? */
2106	HDA_REG(pThis, IRS) &= ~HDA_IRS_ICB; /* busy is clear */
2107
2108	DEVHDA_UNLOCK(pDevIns, pThis);
2109	return VINF_SUCCESS;
2110	#else /* !IN_RING3 */
2111	DEVHDA_UNLOCK(pDevIns, pThis);
2112	return VINF_IOM_R3_MMIO_WRITE;
2113	#endif /* !IN_RING3 */
2114	}
2115
2116	/*
2117	* Once the guest read the response, it should clear the IRV bit of the IRS register.
2118	*/
2119	HDA_REG(pThis, IRS) &= ~(u32Value & HDA_IRS_IRV);
2120
2121	DEVHDA_UNLOCK(pDevIns, pThis);
2122	return VINF_SUCCESS;
2123	}
2124
2125	static int hdaRegWriteRIRBWP(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2126	{
2127	RT_NOREF(iReg);
2128	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE);
2129
2130	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
2131	{
2132	LogFunc(("CORB DMA (still) running, skipping\n"));
2133
2134	DEVHDA_UNLOCK(pDevIns, pThis);
2135	return VINF_SUCCESS;
2136	}
2137
2138	if (u32Value & HDA_RIRBWP_RST)
2139	{
2140	/* Do a RIRB reset. */
2141	if (pThis->cbRirbBuf)
2142	{
2143	Assert(pThis->pu64RirbBuf);
2144	RT_BZERO((void *)pThis->pu64RirbBuf, pThis->cbRirbBuf);
2145	}
2146
2147	LogRel2(("HDA: RIRB reset\n"));
2148
2149	HDA_REG(pThis, RIRBWP) = 0;
2150	}
2151
2152	/* The remaining bits are O, see 6.2.22. */
2153
2154	DEVHDA_UNLOCK(pDevIns, pThis);
2155	return VINF_SUCCESS;
2156	}
2157
2158	static int hdaRegWriteRINTCNT(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2159	{
2160	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE);
2161
2162	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
2163	{
2164	LogFunc(("CORB DMA is (still) running, skipping\n"));
2165
2166	DEVHDA_UNLOCK(pDevIns, pThis);
2167	return VINF_SUCCESS;
2168	}
2169
2170	int rc = hdaRegWriteU16(pDevIns, pThis, iReg, u32Value);
2171	AssertRC(rc);
2172
2173	LogFunc(("Response interrupt count is now %RU8\n", HDA_REG(pThis, RINTCNT) & 0xFF));
2174
2175	DEVHDA_UNLOCK(pDevIns, pThis);
2176	return rc;
2177	}
2178
2179	static int hdaRegWriteBase(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2180	{
2181	uint32_t iRegMem = g_aHdaRegMap[iReg].mem_idx;
2182	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE);
2183
2184	int rc = hdaRegWriteU32(pDevIns, pThis, iReg, u32Value);
2185	AssertRCSuccess(rc);
2186
2187	switch (iReg)
2188	{
2189	case HDA_REG_CORBLBASE:
2190	pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
2191	pThis->u64CORBBase \|= pThis->au32Regs[iRegMem];
2192	break;
2193	case HDA_REG_CORBUBASE:
2194	pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
2195	pThis->u64CORBBase \|= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2196	break;
2197	case HDA_REG_RIRBLBASE:
2198	pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
2199	pThis->u64RIRBBase \|= pThis->au32Regs[iRegMem];
2200	break;
2201	case HDA_REG_RIRBUBASE:
2202	pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
2203	pThis->u64RIRBBase \|= ((uint64_t)pThis->au32Regs[iRegMem] << 32);
2204	break;
2205	case HDA_REG_DPLBASE:
2206	{
2207	pThis->u64DPBase = pThis->au32Regs[iRegMem] & DPBASE_ADDR_MASK;
2208	Assert(pThis->u64DPBase % 128 == 0); /* Must be 128-byte aligned. */
2209
2210	/* Also make sure to handle the DMA position enable bit. */
2211	pThis->fDMAPosition = pThis->au32Regs[iRegMem] & RT_BIT_32(0);
2212	LogRel(("HDA: %s DMA position buffer\n", pThis->fDMAPosition ? "Enabled" : "Disabled"));
2213	break;
2214	}
2215	case HDA_REG_DPUBASE:
2216	pThis->u64DPBase = RT_MAKE_U64(RT_LO_U32(pThis->u64DPBase) & DPBASE_ADDR_MASK, pThis->au32Regs[iRegMem]);
2217	break;
2218	default:
2219	AssertMsgFailed(("Invalid index\n"));
2220	break;
2221	}
2222
2223	LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
2224	pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
2225
2226	DEVHDA_UNLOCK(pDevIns, pThis);
2227	return rc;
2228	}
2229
2230	static int hdaRegWriteRIRBSTS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2231	{
2232	RT_NOREF_PV(iReg);
2233	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE);
2234
2235	uint8_t v = HDA_REG(pThis, RIRBSTS);
2236	HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
2237
2238	int rc = HDA_PROCESS_INTERRUPT(pDevIns, pThis);
2239
2240	DEVHDA_UNLOCK(pDevIns, pThis);
2241	return rc;
2242	}
2243
2244	#ifdef IN_RING3
2245
2246	/**
2247	* Retrieves a corresponding sink for a given mixer control.
2248	* Returns NULL if no sink is found.
2249	*
2250	* @return PHDAMIXERSINK
2251	* @param pThis HDA state.
2252	* @param enmMixerCtl Mixer control to get the corresponding sink for.
2253	*/
2254	static PHDAMIXERSINK hdaR3MixerControlToSink(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
2255	{
2256	PHDAMIXERSINK pSink;
2257
2258	switch (enmMixerCtl)
2259	{
2260	case PDMAUDIOMIXERCTL_VOLUME_MASTER:
2261	/* Fall through is intentional. */
2262	case PDMAUDIOMIXERCTL_FRONT:
2263	pSink = &pThis->SinkFront;
2264	break;
2265	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2266	case PDMAUDIOMIXERCTL_CENTER_LFE:
2267	pSink = &pThis->SinkCenterLFE;
2268	break;
2269	case PDMAUDIOMIXERCTL_REAR:
2270	pSink = &pThis->SinkRear;
2271	break;
2272	# endif
2273	case PDMAUDIOMIXERCTL_LINE_IN:
2274	pSink = &pThis->SinkLineIn;
2275	break;
2276	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2277	case PDMAUDIOMIXERCTL_MIC_IN:
2278	pSink = &pThis->SinkMicIn;
2279	break;
2280	# endif
2281	default:
2282	pSink = NULL;
2283	AssertMsgFailed(("Unhandled mixer control\n"));
2284	break;
2285	}
2286
2287	return pSink;
2288	}
2289
2290	/**
2291	* Adds a specific HDA driver to the driver chain.
2292	*
2293	* @return IPRT status code.
2294	* @param pThis HDA state.
2295	* @param pDrv HDA driver to add.
2296	*/
2297	static int hdaR3MixerAddDrv(PHDASTATE pThis, PHDADRIVER pDrv)
2298	{
2299	int rc = VINF_SUCCESS;
2300
2301	PHDASTREAM pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkLineIn);
2302	if ( pStream
2303	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2304	{
2305	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkLineIn.pMixSink, &pStream->State.Cfg, pDrv);
2306	if (RT_SUCCESS(rc))
2307	rc = rc2;
2308	}
2309
2310	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2311	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkMicIn);
2312	if ( pStream
2313	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2314	{
2315	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkMicIn.pMixSink, &pStream->State.Cfg, pDrv);
2316	if (RT_SUCCESS(rc))
2317	rc = rc2;
2318	}
2319	# endif
2320
2321	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkFront);
2322	if ( pStream
2323	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2324	{
2325	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkFront.pMixSink, &pStream->State.Cfg, pDrv);
2326	if (RT_SUCCESS(rc))
2327	rc = rc2;
2328	}
2329
2330	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2331	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkCenterLFE);
2332	if ( pStream
2333	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2334	{
2335	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkCenterLFE.pMixSink, &pStream->State.Cfg, pDrv);
2336	if (RT_SUCCESS(rc))
2337	rc = rc2;
2338	}
2339
2340	pStream = hdaR3GetStreamFromSink(pThis, &pThis->SinkRear);
2341	if ( pStream
2342	&& DrvAudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2343	{
2344	int rc2 = hdaR3MixerAddDrvStream(pThis, pThis->SinkRear.pMixSink, &pStream->State.Cfg, pDrv);
2345	if (RT_SUCCESS(rc))
2346	rc = rc2;
2347	}
2348	# endif
2349
2350	return rc;
2351	}
2352
2353	/**
2354	* Removes a specific HDA driver from the driver chain and destroys its
2355	* associated streams.
2356	*
2357	* @param pThis HDA state.
2358	* @param pDrv HDA driver to remove.
2359	*/
2360	static void hdaR3MixerRemoveDrv(PHDASTATE pThis, PHDADRIVER pDrv)
2361	{
2362	AssertPtrReturnVoid(pThis);
2363	AssertPtrReturnVoid(pDrv);
2364
2365	if (pDrv->LineIn.pMixStrm)
2366	{
2367	if (AudioMixerSinkGetRecordingSource(pThis->SinkLineIn.pMixSink) == pDrv->LineIn.pMixStrm)
2368	AudioMixerSinkSetRecordingSource(pThis->SinkLineIn.pMixSink, NULL);
2369
2370	AudioMixerSinkRemoveStream(pThis->SinkLineIn.pMixSink, pDrv->LineIn.pMixStrm);
2371	AudioMixerStreamDestroy(pDrv->LineIn.pMixStrm);
2372	pDrv->LineIn.pMixStrm = NULL;
2373	}
2374
2375	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2376	if (pDrv->MicIn.pMixStrm)
2377	{
2378	if (AudioMixerSinkGetRecordingSource(pThis->SinkMicIn.pMixSink) == pDrv->MicIn.pMixStrm)
2379	AudioMixerSinkSetRecordingSource(&pThis->SinkMicIn.pMixSink, NULL);
2380
2381	AudioMixerSinkRemoveStream(pThis->SinkMicIn.pMixSink, pDrv->MicIn.pMixStrm);
2382	AudioMixerStreamDestroy(pDrv->MicIn.pMixStrm);
2383	pDrv->MicIn.pMixStrm = NULL;
2384	}
2385	# endif
2386
2387	if (pDrv->Front.pMixStrm)
2388	{
2389	AudioMixerSinkRemoveStream(pThis->SinkFront.pMixSink, pDrv->Front.pMixStrm);
2390	AudioMixerStreamDestroy(pDrv->Front.pMixStrm);
2391	pDrv->Front.pMixStrm = NULL;
2392	}
2393
2394	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2395	if (pDrv->CenterLFE.pMixStrm)
2396	{
2397	AudioMixerSinkRemoveStream(pThis->SinkCenterLFE.pMixSink, pDrv->CenterLFE.pMixStrm);
2398	AudioMixerStreamDestroy(pDrv->CenterLFE.pMixStrm);
2399	pDrv->CenterLFE.pMixStrm = NULL;
2400	}
2401
2402	if (pDrv->Rear.pMixStrm)
2403	{
2404	AudioMixerSinkRemoveStream(pThis->SinkRear.pMixSink, pDrv->Rear.pMixStrm);
2405	AudioMixerStreamDestroy(pDrv->Rear.pMixStrm);
2406	pDrv->Rear.pMixStrm = NULL;
2407	}
2408	# endif
2409
2410	RTListNodeRemove(&pDrv->Node);
2411	}
2412
2413	/**
2414	* Adds a driver stream to a specific mixer sink.
2415	*
2416	* @returns IPRT status code (ignored by caller).
2417	* @param pThis HDA state.
2418	* @param pMixSink Audio mixer sink to add audio streams to.
2419	* @param pCfg Audio stream configuration to use for the audio streams to add.
2420	* @param pDrv Driver stream to add.
2421	*/
2422	static int hdaR3MixerAddDrvStream(PHDASTATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg, PHDADRIVER pDrv)
2423	{
2424	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2425	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
2426	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2427
2428	LogFunc(("szSink=%s, szStream=%s, cChannels=%RU8\n", pMixSink->pszName, pCfg->szName, pCfg->Props.cChannels));
2429
2430	PPDMAUDIOSTREAMCFG pStreamCfg = DrvAudioHlpStreamCfgDup(pCfg);
2431	if (!pStreamCfg)
2432	return VERR_NO_MEMORY;
2433
2434	LogFunc(("[LUN#%RU8] %s\n", pDrv->uLUN, pStreamCfg->szName));
2435
2436	int rc = VINF_SUCCESS;
2437
2438	PHDADRIVERSTREAM pDrvStream = NULL;
2439
2440	if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
2441	{
2442	LogFunc(("enmRecSource=%d\n", pStreamCfg->u.enmSrc));
2443
2444	switch (pStreamCfg->u.enmSrc)
2445	{
2446	case PDMAUDIORECSRC_LINE:
2447	pDrvStream = &pDrv->LineIn;
2448	break;
2449	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2450	case PDMAUDIORECSRC_MIC:
2451	pDrvStream = &pDrv->MicIn;
2452	break;
2453	# endif
2454	default:
2455	rc = VERR_NOT_SUPPORTED;
2456	break;
2457	}
2458	}
2459	else if (pStreamCfg->enmDir == PDMAUDIODIR_OUT)
2460	{
2461	LogFunc(("enmPlaybackDest=%d\n", pStreamCfg->u.enmDst));
2462
2463	switch (pStreamCfg->u.enmDst)
2464	{
2465	case PDMAUDIOPLAYBACKDST_FRONT:
2466	pDrvStream = &pDrv->Front;
2467	break;
2468	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2469	case PDMAUDIOPLAYBACKDST_CENTER_LFE:
2470	pDrvStream = &pDrv->CenterLFE;
2471	break;
2472	case PDMAUDIOPLAYBACKDST_REAR:
2473	pDrvStream = &pDrv->Rear;
2474	break;
2475	# endif
2476	default:
2477	rc = VERR_NOT_SUPPORTED;
2478	break;
2479	}
2480	}
2481	else
2482	rc = VERR_NOT_SUPPORTED;
2483
2484	if (RT_SUCCESS(rc))
2485	{
2486	AssertPtr(pDrvStream);
2487	AssertMsg(pDrvStream->pMixStrm == NULL, ("[LUN#%RU8] Driver stream already present when it must not\n", pDrv->uLUN));
2488
2489	PAUDMIXSTREAM pMixStrm;
2490	rc = AudioMixerSinkCreateStream(pMixSink, pDrv->pConnector, pStreamCfg, 0 /* fFlags */, &pMixStrm);
2491	LogFlowFunc(("LUN#%RU8: Created stream \"%s\" for sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
2492	if (RT_SUCCESS(rc))
2493	{
2494	rc = AudioMixerSinkAddStream(pMixSink, pMixStrm);
2495	LogFlowFunc(("LUN#%RU8: Added stream \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pStreamCfg->szName, rc));
2496	if (RT_SUCCESS(rc))
2497	{
2498	/* If this is an input stream, always set the latest (added) stream
2499	* as the recording source. */
2500	/** @todo Make the recording source dynamic (CFGM?). */
2501	if (pStreamCfg->enmDir == PDMAUDIODIR_IN)
2502	{
2503	PDMAUDIOBACKENDCFG Cfg;
2504	rc = pDrv->pConnector->pfnGetConfig(pDrv->pConnector, &Cfg);
2505	if (RT_SUCCESS(rc))
2506	{
2507	if (Cfg.cMaxStreamsIn) /* At least one input source available? */
2508	{
2509	rc = AudioMixerSinkSetRecordingSource(pMixSink, pMixStrm);
2510	LogFlowFunc(("LUN#%RU8: Recording source for '%s' -> '%s', rc=%Rrc\n",
2511	pDrv->uLUN, pStreamCfg->szName, Cfg.szName, rc));
2512
2513	if (RT_SUCCESS(rc))
2514	LogRel(("HDA: Set recording source for '%s' to '%s'\n",
2515	pStreamCfg->szName, Cfg.szName));
2516	}
2517	else
2518	LogRel(("HDA: Backend '%s' currently is not offering any recording source for '%s'\n",
2519	Cfg.szName, pStreamCfg->szName));
2520	}
2521	else if (RT_FAILURE(rc))
2522	LogFunc(("LUN#%RU8: Unable to retrieve backend configuration for '%s', rc=%Rrc\n",
2523	pDrv->uLUN, pStreamCfg->szName, rc));
2524	}
2525	}
2526	}
2527
2528	if (RT_SUCCESS(rc))
2529	pDrvStream->pMixStrm = pMixStrm;
2530	}
2531
2532	DrvAudioHlpStreamCfgFree(pStreamCfg);
2533
2534	LogFlowFuncLeaveRC(rc);
2535	return rc;
2536	}
2537
2538	/**
2539	* Adds all current driver streams to a specific mixer sink.
2540	*
2541	* @returns IPRT status code.
2542	* @param pThis HDA state.
2543	* @param pMixSink Audio mixer sink to add stream to.
2544	* @param pCfg Audio stream configuration to use for the audio streams to add.
2545	*/
2546	static int hdaR3MixerAddDrvStreams(PHDASTATE pThis, PAUDMIXSINK pMixSink, PPDMAUDIOSTREAMCFG pCfg)
2547	{
2548	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2549	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
2550	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2551
2552	LogFunc(("Sink=%s, Stream=%s\n", pMixSink->pszName, pCfg->szName));
2553
2554	if (!DrvAudioHlpStreamCfgIsValid(pCfg))
2555	return VERR_INVALID_PARAMETER;
2556
2557	int rc = AudioMixerSinkSetFormat(pMixSink, &pCfg->Props);
2558	if (RT_FAILURE(rc))
2559	return rc;
2560
2561	PHDADRIVER pDrv;
2562	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2563	{
2564	int rc2 = hdaR3MixerAddDrvStream(pThis, pMixSink, pCfg, pDrv);
2565	if (RT_FAILURE(rc2))
2566	LogFunc(("Attaching stream failed with %Rrc\n", rc2));
2567
2568	/* Do not pass failure to rc here, as there might be drivers which aren't
2569	* configured / ready yet. */
2570	}
2571
2572	return rc;
2573	}
2574
2575	/**
2576	* @interface_method_impl{HDACODEC,pfnCbMixerAddStream}
2577	*
2578	* Adds a new audio stream to a specific mixer control.
2579	*
2580	* Depending on the mixer control the stream then gets assigned to one of the internal
2581	* mixer sinks, which in turn then handle the mixing of all connected streams to that sink.
2582	*
2583	* @return IPRT status code.
2584	* @param pThis HDA state.
2585	* @param enmMixerCtl Mixer control to assign new stream to.
2586	* @param pCfg Stream configuration for the new stream.
2587	*/
2588	static DECLCALLBACK(int) hdaR3MixerAddStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOSTREAMCFG pCfg)
2589	{
2590	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2591	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2592
2593	int rc;
2594
2595	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2596	if (pSink)
2597	{
2598	rc = hdaR3MixerAddDrvStreams(pThis, pSink->pMixSink, pCfg);
2599
2600	AssertPtr(pSink->pMixSink);
2601	LogFlowFunc(("Sink=%s, Mixer control=%s\n", pSink->pMixSink->pszName, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl)));
2602	}
2603	else
2604	rc = VERR_NOT_FOUND;
2605
2606	LogFlowFuncLeaveRC(rc);
2607	return rc;
2608	}
2609
2610	/**
2611	* @interface_method_impl{HDACODEC,pfnCbMixerRemoveStream}
2612	*
2613	* Removes a specified mixer control from the HDA's mixer.
2614	*
2615	* @return IPRT status code.
2616	* @param pThis HDA state.
2617	* @param enmMixerCtl Mixer control to remove.
2618	*
2619	* @remarks Can be called as a callback by the HDA codec.
2620	*/
2621	static DECLCALLBACK(int) hdaR3MixerRemoveStream(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl)
2622	{
2623	AssertPtrReturn(pThis, VERR_INVALID_POINTER);
2624
2625	int rc;
2626
2627	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2628	if (pSink)
2629	{
2630	PHDADRIVER pDrv;
2631	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
2632	{
2633	PAUDMIXSTREAM pMixStream = NULL;
2634	switch (enmMixerCtl)
2635	{
2636	/*
2637	* Input.
2638	*/
2639	case PDMAUDIOMIXERCTL_LINE_IN:
2640	pMixStream = pDrv->LineIn.pMixStrm;
2641	pDrv->LineIn.pMixStrm = NULL;
2642	break;
2643	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2644	case PDMAUDIOMIXERCTL_MIC_IN:
2645	pMixStream = pDrv->MicIn.pMixStrm;
2646	pDrv->MicIn.pMixStrm = NULL;
2647	break;
2648	# endif
2649	/*
2650	* Output.
2651	*/
2652	case PDMAUDIOMIXERCTL_FRONT:
2653	pMixStream = pDrv->Front.pMixStrm;
2654	pDrv->Front.pMixStrm = NULL;
2655	break;
2656	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2657	case PDMAUDIOMIXERCTL_CENTER_LFE:
2658	pMixStream = pDrv->CenterLFE.pMixStrm;
2659	pDrv->CenterLFE.pMixStrm = NULL;
2660	break;
2661	case PDMAUDIOMIXERCTL_REAR:
2662	pMixStream = pDrv->Rear.pMixStrm;
2663	pDrv->Rear.pMixStrm = NULL;
2664	break;
2665	# endif
2666	default:
2667	AssertMsgFailed(("Mixer control %d not implemented\n", enmMixerCtl));
2668	break;
2669	}
2670
2671	if (pMixStream)
2672	{
2673	AudioMixerSinkRemoveStream(pSink->pMixSink, pMixStream);
2674	AudioMixerStreamDestroy(pMixStream);
2675
2676	pMixStream = NULL;
2677	}
2678	}
2679
2680	AudioMixerSinkRemoveAllStreams(pSink->pMixSink);
2681	rc = VINF_SUCCESS;
2682	}
2683	else
2684	rc = VERR_NOT_FOUND;
2685
2686	LogFunc(("Mixer control=%s, rc=%Rrc\n", DrvAudioHlpAudMixerCtlToStr(enmMixerCtl), rc));
2687	return rc;
2688	}
2689
2690	/**
2691	* @interface_method_impl{HDACODEC,pfnCbMixerControl}
2692	*
2693	* Controls an input / output converter widget, that is, which converter is connected
2694	* to which stream (and channel).
2695	*
2696	* @returns IPRT status code.
2697	* @param pThis HDA State.
2698	* @param enmMixerCtl Mixer control to set SD stream number and channel for.
2699	* @param uSD SD stream number (number + 1) to set. Set to 0 for unassign.
2700	* @param uChannel Channel to set. Only valid if a valid SD stream number is specified.
2701	*
2702	* @remarks Can be called as a callback by the HDA codec.
2703	*/
2704	static DECLCALLBACK(int) hdaR3MixerControl(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, uint8_t uSD, uint8_t uChannel)
2705	{
2706	LogFunc(("enmMixerCtl=%s, uSD=%RU8, uChannel=%RU8\n", DrvAudioHlpAudMixerCtlToStr(enmMixerCtl), uSD, uChannel));
2707
2708	if (uSD == 0) /* Stream number 0 is reserved. */
2709	{
2710	Log2Func(("Invalid SDn (%RU8) number for mixer control '%s', ignoring\n", uSD, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl)));
2711	return VINF_SUCCESS;
2712	}
2713	/* uChannel is optional. */
2714
2715	/* SDn0 starts as 1. */
2716	Assert(uSD);
2717	uSD--;
2718
2719	# ifndef VBOX_WITH_AUDIO_HDA_MIC_IN
2720	/* Only SDI0 (Line-In) is supported. */
2721	if ( hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN
2722	&& uSD >= 1)
2723	{
2724	LogRel2(("HDA: Dedicated Mic-In support not imlpemented / built-in (stream #%RU8), using Line-In (stream #0) instead\n", uSD));
2725	uSD = 0;
2726	}
2727	# endif
2728
2729	int rc = VINF_SUCCESS;
2730
2731	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2732	if (pSink)
2733	{
2734	AssertPtr(pSink->pMixSink);
2735
2736	/* If this an output stream, determine the correct SD#. */
2737	if ( (uSD < HDA_MAX_SDI)
2738	&& AudioMixerSinkGetDir(pSink->pMixSink) == AUDMIXSINKDIR_OUTPUT)
2739	{
2740	uSD += HDA_MAX_SDI;
2741	}
2742
2743	/* Detach the existing stream from the sink. */
2744	if ( pSink->pStream
2745	&& ( pSink->pStream->u8SD != uSD
2746	\|\| pSink->pStream->u8Channel != uChannel)
2747	)
2748	{
2749	LogFunc(("Sink '%s' was assigned to stream #%RU8 (channel %RU8) before\n",
2750	pSink->pMixSink->pszName, pSink->pStream->u8SD, pSink->pStream->u8Channel));
2751
2752	hdaR3StreamLock(pSink->pStream);
2753
2754	/* Only disable the stream if the stream descriptor # has changed. */
2755	if (pSink->pStream->u8SD != uSD)
2756	hdaR3StreamEnable(pSink->pStream, false);
2757
2758	pSink->pStream->pMixSink = NULL;
2759
2760	hdaR3StreamUnlock(pSink->pStream);
2761
2762	pSink->pStream = NULL;
2763	}
2764
2765	Assert(uSD < HDA_MAX_STREAMS);
2766
2767	/* Attach the new stream to the sink.
2768	* Enabling the stream will be done by the gust via a separate SDnCTL call then. */
2769	if (pSink->pStream == NULL)
2770	{
2771	LogRel2(("HDA: Setting sink '%s' to stream #%RU8 (channel %RU8), mixer control=%s\n",
2772	pSink->pMixSink->pszName, uSD, uChannel, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl)));
2773
2774	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, uSD);
2775	if (pStream)
2776	{
2777	hdaR3StreamLock(pStream);
2778
2779	pSink->pStream = pStream;
2780
2781	pStream->u8Channel = uChannel;
2782	pStream->pMixSink = pSink;
2783
2784	hdaR3StreamUnlock(pStream);
2785
2786	rc = VINF_SUCCESS;
2787	}
2788	else
2789	rc = VERR_NOT_IMPLEMENTED;
2790	}
2791	}
2792	else
2793	rc = VERR_NOT_FOUND;
2794
2795	if (RT_FAILURE(rc))
2796	LogRel(("HDA: Converter control for stream #%RU8 (channel %RU8) / mixer control '%s' failed with %Rrc, skipping\n",
2797	uSD, uChannel, DrvAudioHlpAudMixerCtlToStr(enmMixerCtl), rc));
2798
2799	LogFlowFuncLeaveRC(rc);
2800	return rc;
2801	}
2802
2803	/**
2804	* @interface_method_impl{HDACODEC,pfnCbMixerSetVolume}
2805	*
2806	* Sets the volume of a specified mixer control.
2807	*
2808	* @return IPRT status code.
2809	* @param pThis HDA State.
2810	* @param enmMixerCtl Mixer control to set volume for.
2811	* @param pVol Pointer to volume data to set.
2812	*
2813	* @remarks Can be called as a callback by the HDA codec.
2814	*/
2815	static DECLCALLBACK(int) hdaR3MixerSetVolume(PHDASTATE pThis, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOVOLUME pVol)
2816	{
2817	int rc;
2818
2819	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThis, enmMixerCtl);
2820	if ( pSink
2821	&& pSink->pMixSink)
2822	{
2823	LogRel2(("HDA: Setting volume for mixer sink '%s' to %RU8/%RU8 (%s)\n",
2824	pSink->pMixSink->pszName, pVol->uLeft, pVol->uRight, pVol->fMuted ? "Muted" : "Unmuted"));
2825
2826	/* Set the volume.
2827	* We assume that the codec already converted it to the correct range. */
2828	rc = AudioMixerSinkSetVolume(pSink->pMixSink, pVol);
2829	}
2830	else
2831	rc = VERR_NOT_FOUND;
2832
2833	LogFlowFuncLeaveRC(rc);
2834	return rc;
2835	}
2836
2837	/**
2838	* @callback_method_impl{FNTMTIMERDEV, Main routine for the stream's timer.}
2839	*/
2840	static DECLCALLBACK(void) hdaR3Timer(PPDMDEVINS pDevIns, PTMTIMER pTimer, void *pvUser)
2841	{
2842	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
2843	PHDASTREAM pStream = (PHDASTREAM)pvUser;
2844	TMTIMERHANDLE hTimer = pStream->hTimer;
2845	RT_NOREF(pTimer);
2846
2847	AssertPtr(pStream);
2848	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2849	Assert(PDMDevHlpTimerIsLockOwner(pDevIns, hTimer));
2850
2851	hdaR3StreamUpdate(pDevIns, pStream, true /* fInTimer */);
2852
2853	/* Flag indicating whether to kick the timer again for a new data processing round. */
2854	bool fSinkActive = false;
2855	if (pStream->pMixSink)
2856	fSinkActive = AudioMixerSinkIsActive(pStream->pMixSink->pMixSink);
2857
2858	if (fSinkActive)
2859	{
2860	uint64_t const tsNow = PDMDevHlpTimerGet(pDevIns, hTimer); /* (For virtual sync this remains the same for the whole callout IIRC) */
2861	const bool fTimerScheduled = hdaR3StreamTransferIsScheduled(pStream, tsNow);
2862	Log3Func(("fSinksActive=%RTbool, fTimerScheduled=%RTbool\n", fSinkActive, fTimerScheduled));
2863	if (!fTimerScheduled)
2864	hdaR3TimerSet(pDevIns, pStream, tsNow + PDMDevHlpTimerGetFreq(pDevIns, hTimer) / pThis->uTimerHz,
2865	true /fForce/, tsNow /fixed/ );
2866	}
2867	else
2868	Log3Func(("fSinksActive=%RTbool\n", fSinkActive));
2869	}
2870
2871	# ifdef HDA_USE_DMA_ACCESS_HANDLER
2872	/**
2873	* HC access handler for the FIFO.
2874	*
2875	* @returns VINF_SUCCESS if the handler have carried out the operation.
2876	* @returns VINF_PGM_HANDLER_DO_DEFAULT if the caller should carry out the access operation.
2877	* @param pVM VM Handle.
2878	* @param pVCpu The cross context CPU structure for the calling EMT.
2879	* @param GCPhys The physical address the guest is writing to.
2880	* @param pvPhys The HC mapping of that address.
2881	* @param pvBuf What the guest is reading/writing.
2882	* @param cbBuf How much it's reading/writing.
2883	* @param enmAccessType The access type.
2884	* @param enmOrigin Who is making the access.
2885	* @param pvUser User argument.
2886	*/
2887	static DECLCALLBACK(VBOXSTRICTRC) hdaR3DMAAccessHandler(PVM pVM, PVMCPU pVCpu, RTGCPHYS GCPhys, void *pvPhys,
2888	void *pvBuf, size_t cbBuf,
2889	PGMACCESSTYPE enmAccessType, PGMACCESSORIGIN enmOrigin, void *pvUser)
2890	{
2891	RT_NOREF(pVM, pVCpu, pvPhys, pvBuf, enmOrigin);
2892
2893	PHDADMAACCESSHANDLER pHandler = (PHDADMAACCESSHANDLER)pvUser;
2894	AssertPtr(pHandler);
2895
2896	PHDASTREAM pStream = pHandler->pStream;
2897	AssertPtr(pStream);
2898
2899	Assert(GCPhys >= pHandler->GCPhysFirst);
2900	Assert(GCPhys <= pHandler->GCPhysLast);
2901	Assert(enmAccessType == PGMACCESSTYPE_WRITE);
2902
2903	/* Not within BDLE range? Bail out. */
2904	if ( (GCPhys < pHandler->BDLEAddr)
2905	\|\| (GCPhys + cbBuf > pHandler->BDLEAddr + pHandler->BDLESize))
2906	{
2907	return VINF_PGM_HANDLER_DO_DEFAULT;
2908	}
2909
2910	switch (enmAccessType)
2911	{
2912	case PGMACCESSTYPE_WRITE:
2913	{
2914	# ifdef DEBUG
2915	PHDASTREAMDBGINFO pStreamDbg = &pStream->Dbg;
2916
2917	const uint64_t tsNowNs = RTTimeNanoTS();
2918	const uint32_t tsElapsedMs = (tsNowNs - pStreamDbg->tsWriteSlotBegin) / 1000 / 1000;
2919
2920	uint64_t cWritesHz = ASMAtomicReadU64(&pStreamDbg->cWritesHz);
2921	uint64_t cbWrittenHz = ASMAtomicReadU64(&pStreamDbg->cbWrittenHz);
2922
2923	if (tsElapsedMs >= (1000 / HDA_TIMER_HZ_DEFAULT))
2924	{
2925	LogFunc(("[SD%RU8] %RU32ms elapsed, cbWritten=%RU64, cWritten=%RU64 -- %RU32 bytes on average per time slot (%zums)\n",
2926	pStream->u8SD, tsElapsedMs, cbWrittenHz, cWritesHz,
2927	ASMDivU64ByU32RetU32(cbWrittenHz, cWritesHz ? cWritesHz : 1), 1000 / HDA_TIMER_HZ_DEFAULT));
2928
2929	pStreamDbg->tsWriteSlotBegin = tsNowNs;
2930
2931	cWritesHz = 0;
2932	cbWrittenHz = 0;
2933	}
2934
2935	cWritesHz += 1;
2936	cbWrittenHz += cbBuf;
2937
2938	ASMAtomicIncU64(&pStreamDbg->cWritesTotal);
2939	ASMAtomicAddU64(&pStreamDbg->cbWrittenTotal, cbBuf);
2940
2941	ASMAtomicWriteU64(&pStreamDbg->cWritesHz, cWritesHz);
2942	ASMAtomicWriteU64(&pStreamDbg->cbWrittenHz, cbWrittenHz);
2943
2944	LogFunc(("[SD%RU8] Writing %3zu @ 0x%x (off %zu)\n",
2945	pStream->u8SD, cbBuf, GCPhys, GCPhys - pHandler->BDLEAddr));
2946
2947	LogFunc(("[SD%RU8] cWrites=%RU64, cbWritten=%RU64 -> %RU32 bytes on average\n",
2948	pStream->u8SD, pStreamDbg->cWritesTotal, pStreamDbg->cbWrittenTotal,
2949	ASMDivU64ByU32RetU32(pStreamDbg->cbWrittenTotal, pStreamDbg->cWritesTotal)));
2950	# endif
2951
2952	if (pThis->fDebugEnabled)
2953	{
2954	RTFILE fh;
2955	RTFileOpen(&fh, VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH "hdaDMAAccessWrite.pcm",
2956	RTFILE_O_OPEN_CREATE \| RTFILE_O_APPEND \| RTFILE_O_WRITE \| RTFILE_O_DENY_NONE);
2957	RTFileWrite(fh, pvBuf, cbBuf, NULL);
2958	RTFileClose(fh);
2959	}
2960
2961	# ifdef HDA_USE_DMA_ACCESS_HANDLER_WRITING
2962	PRTCIRCBUF pCircBuf = pStream->State.pCircBuf;
2963	AssertPtr(pCircBuf);
2964
2965	uint8_t pbBuf = (uint8_t )pvBuf;
2966	while (cbBuf)
2967	{
2968	/* Make sure we only copy as much as the stream's FIFO can hold (SDFIFOS, 18.2.39). */
2969	void *pvChunk;
2970	size_t cbChunk;
2971	RTCircBufAcquireWriteBlock(pCircBuf, cbBuf, &pvChunk, &cbChunk);
2972
2973	if (cbChunk)
2974	{
2975	memcpy(pvChunk, pbBuf, cbChunk);
2976
2977	pbBuf += cbChunk;
2978	Assert(cbBuf >= cbChunk);
2979	cbBuf -= cbChunk;
2980	}
2981	else
2982	{
2983	//AssertMsg(RTCircBufFree(pCircBuf), ("No more space but still %zu bytes to write\n", cbBuf));
2984	break;
2985	}
2986
2987	LogFunc(("[SD%RU8] cbChunk=%zu\n", pStream->u8SD, cbChunk));
2988
2989	RTCircBufReleaseWriteBlock(pCircBuf, cbChunk);
2990	}
2991	# endif /* HDA_USE_DMA_ACCESS_HANDLER_WRITING */
2992	break;
2993	}
2994
2995	default:
2996	AssertMsgFailed(("Access type not implemented\n"));
2997	break;
2998	}
2999
3000	return VINF_PGM_HANDLER_DO_DEFAULT;
3001	}
3002	# endif /* HDA_USE_DMA_ACCESS_HANDLER */
3003
3004	/**
3005	* Soft reset of the device triggered via GCTL.
3006	*
3007	* @param pThis HDA state.
3008	*
3009	*/
3010	static void hdaR3GCTLReset(PHDASTATE pThis)
3011	{
3012	LogFlowFuncEnter();
3013
3014	pThis->cStreamsActive = 0;
3015
3016	HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(HDA_MAX_SDO, HDA_MAX_SDI, 0, 0, 1); /* see 6.2.1 */
3017	HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
3018	HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
3019	HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
3020	HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
3021	HDA_REG(pThis, CORBSIZE) = 0x42; /* Up to 256 CORB entries see 6.2.1 */
3022	HDA_REG(pThis, RIRBSIZE) = 0x42; /* Up to 256 RIRB entries see 6.2.1 */
3023	HDA_REG(pThis, CORBRP) = 0x0;
3024	HDA_REG(pThis, CORBWP) = 0x0;
3025	HDA_REG(pThis, RIRBWP) = 0x0;
3026	/* Some guests (like Haiku) don't set RINTCNT explicitly but expect an interrupt after each
3027	* RIRB response -- so initialize RINTCNT to 1 by default. */
3028	HDA_REG(pThis, RINTCNT) = 0x1;
3029
3030	/*
3031	* Stop any audio currently playing and/or recording.
3032	*/
3033	pThis->SinkFront.pStream = NULL;
3034	if (pThis->SinkFront.pMixSink)
3035	AudioMixerSinkReset(pThis->SinkFront.pMixSink);
3036	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3037	pThis->SinkMicIn.pStream = NULL;
3038	if (pThis->SinkMicIn.pMixSink)
3039	AudioMixerSinkReset(pThis->SinkMicIn.pMixSink);
3040	# endif
3041	pThis->SinkLineIn.pStream = NULL;
3042	if (pThis->SinkLineIn.pMixSink)
3043	AudioMixerSinkReset(pThis->SinkLineIn.pMixSink);
3044	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3045	pThis->SinkCenterLFE = NULL;
3046	if (pThis->SinkCenterLFE.pMixSink)
3047	AudioMixerSinkReset(pThis->SinkCenterLFE.pMixSink);
3048	pThis->SinkRear.pStream = NULL;
3049	if (pThis->SinkRear.pMixSink)
3050	AudioMixerSinkReset(pThis->SinkRear.pMixSink);
3051	# endif
3052
3053	/*
3054	* Reset the codec.
3055	*/
3056	if ( pThis->pCodec
3057	&& pThis->pCodec->pfnReset)
3058	{
3059	pThis->pCodec->pfnReset(pThis->pCodec);
3060	}
3061
3062	/*
3063	* Set some sensible defaults for which HDA sinks
3064	* are connected to which stream number.
3065	*
3066	* We use SD0 for input and SD4 for output by default.
3067	* These stream numbers can be changed by the guest dynamically lateron.
3068	*/
3069	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3070	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_MIC_IN , 1 /* SD0 /, 0 / Channel */);
3071	# endif
3072	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_LINE_IN , 1 /* SD0 /, 0 / Channel */);
3073
3074	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_FRONT , 5 /* SD4 /, 0 / Channel */);
3075	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3076	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_CENTER_LFE, 5 /* SD4 /, 0 / Channel */);
3077	hdaR3MixerControl(pThis, PDMAUDIOMIXERCTL_REAR , 5 /* SD4 /, 0 / Channel */);
3078	# endif
3079
3080	/* Reset CORB. */
3081	pThis->cbCorbBuf = HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE;
3082	RT_BZERO(pThis->pu32CorbBuf, pThis->cbCorbBuf);
3083
3084	/* Reset RIRB. */
3085	pThis->cbRirbBuf = HDA_RIRB_SIZE * HDA_RIRB_ELEMENT_SIZE;
3086	RT_BZERO(pThis->pu64RirbBuf, pThis->cbRirbBuf);
3087
3088	/* Clear our internal response interrupt counter. */
3089	pThis->u16RespIntCnt = 0;
3090
3091	for (uint8_t uSD = 0; uSD < HDA_MAX_STREAMS; ++uSD)
3092	{
3093	int rc2 = hdaR3StreamEnable(&pThis->aStreams[uSD], false /* fEnable */);
3094	if (RT_SUCCESS(rc2))
3095	{
3096	/* Remove the RUN bit from SDnCTL in case the stream was in a running state before. */
3097	HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_RUN;
3098	hdaR3StreamReset(pThis, &pThis->aStreams[uSD], uSD);
3099	}
3100	}
3101
3102	/* Clear stream tags <-> objects mapping table. */
3103	RT_ZERO(pThis->aTags);
3104
3105	/* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
3106	HDA_REG(pThis, STATESTS) = 0x1;
3107
3108	LogFlowFuncLeave();
3109	LogRel(("HDA: Reset\n"));
3110	}
3111
3112	#endif /* IN_RING3 */
3113
3114	/* MMIO callbacks */
3115
3116	/**
3117	* @callback_method_impl{FNIOMMMIONEWREAD, Looks up and calls the appropriate handler.}
3118	*
3119	* @note During implementation, we discovered so-called "forgotten" or "hole"
3120	* registers whose description is not listed in the RPM, datasheet, or
3121	* spec.
3122	*/
3123	static DECLCALLBACK(VBOXSTRICTRC) hdaMMIORead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
3124	{
3125	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
3126	int rc;
3127	RT_NOREF_PV(pvUser);
3128	Assert(pThis->uAlignmentCheckMagic == HDASTATE_ALIGNMENT_CHECK_MAGIC);
3129
3130	/*
3131	* Look up and log.
3132	*/
3133	int idxRegDsc = hdaRegLookup(off); /* Register descriptor index. */
3134	#ifdef LOG_ENABLED
3135	unsigned const cbLog = cb;
3136	uint32_t offRegLog = (uint32_t)off;
3137	#endif
3138
3139	Log3Func(("off=%#x cb=%#x\n", offRegLog, cb));
3140	Assert(cb == 4); Assert((off & 3) == 0);
3141
3142	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_READ);
3143
3144	if (!(HDA_REG(pThis, GCTL) & HDA_GCTL_CRST) && idxRegDsc != HDA_REG_GCTL)
3145	LogFunc(("Access to registers except GCTL is blocked while reset\n"));
3146
3147	if (idxRegDsc == -1)
3148	LogRel(("HDA: Invalid read access @0x%x (bytes=%u)\n", (uint32_t)off, cb));
3149
3150	if (idxRegDsc != -1)
3151	{
3152	/* Leave lock before calling read function. */
3153	DEVHDA_UNLOCK(pDevIns, pThis);
3154
3155	/* ASSUMES gapless DWORD at end of map. */
3156	if (g_aHdaRegMap[idxRegDsc].size == 4)
3157	{
3158	/*
3159	* Straight forward DWORD access.
3160	*/
3161	rc = g_aHdaRegMap[idxRegDsc].pfnRead(pDevIns, pThis, idxRegDsc, (uint32_t *)pv);
3162	Log3Func(("\tRead %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].abbrev, (uint32_t )pv, rc));
3163	}
3164	else
3165	{
3166	/*
3167	* Multi register read (unless there are trailing gaps).
3168	* ASSUMES that only DWORD reads have sideeffects.
3169	*/
3170	#ifdef IN_RING3
3171	uint32_t u32Value = 0;
3172	unsigned cbLeft = 4;
3173	do
3174	{
3175	uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].size;
3176	uint32_t u32Tmp = 0;
3177
3178	rc = g_aHdaRegMap[idxRegDsc].pfnRead(pDevIns, pThis, idxRegDsc, &u32Tmp);
3179	Log3Func(("\tRead %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].abbrev, cbReg, u32Tmp, rc));
3180	if (rc != VINF_SUCCESS)
3181	break;
3182	u32Value \|= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
3183
3184	cbLeft -= cbReg;
3185	off += cbReg;
3186	idxRegDsc++;
3187	} while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].offset == off);
3188
3189	if (rc == VINF_SUCCESS)
3190	(uint32_t )pv = u32Value;
3191	else
3192	Assert(!IOM_SUCCESS(rc));
3193	#else /* !IN_RING3 */
3194	/* Take the easy way out. */
3195	rc = VINF_IOM_R3_MMIO_READ;
3196	#endif /* !IN_RING3 */
3197	}
3198	}
3199	else
3200	{
3201	DEVHDA_UNLOCK(pDevIns, pThis);
3202
3203	rc = VINF_IOM_MMIO_UNUSED_FF;
3204	Log3Func(("\tHole at %x is accessed for read\n", offRegLog));
3205	}
3206
3207	/*
3208	* Log the outcome.
3209	*/
3210	#ifdef LOG_ENABLED
3211	if (cbLog == 4)
3212	Log3Func(("\tReturning @%#05x -> %#010x %Rrc\n", offRegLog, (uint32_t )pv, rc));
3213	else if (cbLog == 2)
3214	Log3Func(("\tReturning @%#05x -> %#06x %Rrc\n", offRegLog, (uint16_t )pv, rc));
3215	else if (cbLog == 1)
3216	Log3Func(("\tReturning @%#05x -> %#04x %Rrc\n", offRegLog, (uint8_t )pv, rc));
3217	#endif
3218	return rc;
3219	}
3220
3221
3222	DECLINLINE(int) hdaWriteReg(PPDMDEVINS pDevIns, PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
3223	{
3224	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE);
3225
3226	if (!(HDA_REG(pThis, GCTL) & HDA_GCTL_CRST) && idxRegDsc != HDA_REG_GCTL)
3227	{
3228	Log(("hdaWriteReg: Warning: Access to %s is blocked while controller is in reset mode\n", g_aHdaRegMap[idxRegDsc].abbrev));
3229	LogRel2(("HDA: Warning: Access to register %s is blocked while controller is in reset mode\n",
3230	g_aHdaRegMap[idxRegDsc].abbrev));
3231
3232	DEVHDA_UNLOCK(pDevIns, pThis);
3233	return VINF_SUCCESS;
3234	}
3235
3236	/*
3237	* Handle RD (register description) flags.
3238	*/
3239
3240	/* For SDI / SDO: Check if writes to those registers are allowed while SDCTL's RUN bit is set. */
3241	if (idxRegDsc >= HDA_NUM_GENERAL_REGS)
3242	{
3243	const uint32_t uSDCTL = HDA_STREAM_REG(pThis, CTL, HDA_SD_NUM_FROM_REG(pThis, CTL, idxRegDsc));
3244
3245	/*
3246	* Some OSes (like Win 10 AU) violate the spec by writing stuff to registers which are not supposed to be be touched
3247	* while SDCTL's RUN bit is set. So just ignore those values.
3248	*/
3249
3250	/* Is the RUN bit currently set? */
3251	if ( RT_BOOL(uSDCTL & HDA_SDCTL_RUN)
3252	/* Are writes to the register denied if RUN bit is set? */
3253	&& !(g_aHdaRegMap[idxRegDsc].fFlags & HDA_RD_FLAG_SD_WRITE_RUN))
3254	{
3255	Log(("hdaWriteReg: Warning: Access to %s is blocked! %R[sdctl]\n", g_aHdaRegMap[idxRegDsc].abbrev, uSDCTL));
3256	LogRel2(("HDA: Warning: Access to register %s is blocked while the stream's RUN bit is set\n",
3257	g_aHdaRegMap[idxRegDsc].abbrev));
3258
3259	DEVHDA_UNLOCK(pDevIns, pThis);
3260	return VINF_SUCCESS;
3261	}
3262	}
3263
3264	/* Leave the lock before calling write function. */
3265	/** @todo r=bird: Why do we need to do that?? There is no
3266	* explanation why this is necessary here...
3267	*
3268	* More or less all write functions retake the lock, so why not let
3269	* those who need to drop the lock or take additional locks release
3270	* it? See, releasing a lock you already got always runs the risk
3271	* of someone else grabbing it and forcing you to wait, better to
3272	* do the two-three things a write handle needs to do than enter
3273	* and exit the lock all the time. */
3274	DEVHDA_UNLOCK(pDevIns, pThis);
3275
3276	#ifdef LOG_ENABLED
3277	uint32_t const idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3278	uint32_t const u32OldValue = pThis->au32Regs[idxRegMem];
3279	#endif
3280	int rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pDevIns, pThis, idxRegDsc, u32Value);
3281	Log3Func(("Written value %#x to %s[%d byte]; %x => %x%s, rc=%d\n", u32Value, g_aHdaRegMap[idxRegDsc].abbrev,
3282	g_aHdaRegMap[idxRegDsc].size, u32OldValue, pThis->au32Regs[idxRegMem], pszLog, rc));
3283	RT_NOREF(pszLog);
3284	return rc;
3285	}
3286
3287
3288	/**
3289	* @callback_method_impl{FNIOMMMIONEWWRITE,
3290	* Looks up and calls the appropriate handler.}
3291	*/
3292	static DECLCALLBACK(VBOXSTRICTRC) hdaMMIOWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
3293	{
3294	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
3295	int rc;
3296	RT_NOREF_PV(pvUser);
3297	Assert(pThis->uAlignmentCheckMagic == HDASTATE_ALIGNMENT_CHECK_MAGIC);
3298
3299	/*
3300	* Look up and log the access.
3301	*/
3302	int idxRegDsc = hdaRegLookup(off);
3303	#if defined(IN_RING3) \|\| defined(LOG_ENABLED)
3304	uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].mem_idx : UINT32_MAX;
3305	#endif
3306	uint64_t u64Value;
3307	if (cb == 4) u64Value = (uint32_t const )pv;
3308	else if (cb == 2) u64Value = (uint16_t const )pv;
3309	else if (cb == 1) u64Value = (uint8_t const )pv;
3310	else if (cb == 8) u64Value = (uint64_t const )pv;
3311	else
3312	ASSERT_GUEST_MSG_FAILED_RETURN(("cb=%u %.*Rhxs\n", cb, cb, pv),
3313	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "odd write size: off=%RGp cb=%u\n", off, cb));
3314
3315	/*
3316	* The behavior of accesses that aren't aligned on natural boundraries is
3317	* undefined. Just reject them outright.
3318	*/
3319	ASSERT_GUEST_MSG_RETURN((off & (cb - 1)) == 0, ("off=%RGp cb=%u %.*Rhxs\n", off, cb, cb, pv),
3320	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: off=%RGp cb=%u\n", off, cb));
3321
3322	#ifdef LOG_ENABLED
3323	uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
3324	if (idxRegDsc == -1)
3325	Log3Func(("@%#05x u32=%#010x cb=%d\n", (uint32_t)off, (uint32_t const )pv, cb));
3326	else
3327	Log3Func(("@%#05x u%u=%#0RX64 %s\n", (uint32_t)off, cb 8, 2 + cb * 2, u64Value, g_aHdaRegMap[idxRegDsc].abbrev));
3328	#endif
3329
3330	/*
3331	* Try for a direct hit first.
3332	*/
3333	if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size == cb)
3334	{
3335	rc = hdaWriteReg(pDevIns, pThis, idxRegDsc, u64Value, "");
3336	Log3Func(("\t%#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
3337	}
3338	/*
3339	* Partial or multiple register access, loop thru the requested memory.
3340	*/
3341	else
3342	{
3343	#ifdef IN_RING3
3344	if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].size != cb)
3345	Log3Func(("\tSize mismatch: %RU32 (reg) vs %u (access)!!\n", g_aHdaRegMap[idxRegDsc].size, cb));
3346
3347	/*
3348	* If it's an access beyond the start of the register, shift the input
3349	* value and fill in missing bits. Natural alignment rules means we
3350	* will only see 1 or 2 byte accesses of this kind, so no risk of
3351	* shifting out input values.
3352	*/
3353	if (idxRegDsc < 0 && (idxRegDsc = hdaR3RegLookupWithin(off)) != -1)
3354	{
3355	uint32_t const cbBefore = (uint32_t)off - g_aHdaRegMap[idxRegDsc].offset; Assert(cbBefore > 0 && cbBefore < 4);
3356	off -= cbBefore;
3357	idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3358	u64Value <<= cbBefore * 8;
3359	u64Value \|= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
3360	Log3Func(("\tWithin register, supplied %u leading bits: %#llx -> %#llx ...\n",
3361	cbBefore * 8, ~g_afMasks[cbBefore] & u64Value, u64Value));
3362	}
3363
3364	/* Loop thru the write area, it may cover multiple registers. */
3365	rc = VINF_SUCCESS;
3366	for (;;)
3367	{
3368	uint32_t cbReg;
3369	if (idxRegDsc >= 0)
3370	{
3371	idxRegMem = g_aHdaRegMap[idxRegDsc].mem_idx;
3372	cbReg = g_aHdaRegMap[idxRegDsc].size;
3373	if (cb < cbReg)
3374	{
3375	u64Value \|= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
3376	Log3Func(("\tSupplying missing bits (%#x): %#llx -> %#llx ...\n",
3377	g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
3378	}
3379	# ifdef LOG_ENABLED
3380	uint32_t uLogOldVal = pThis->au32Regs[idxRegMem];
3381	# endif
3382	rc = hdaWriteReg(pDevIns, pThis, idxRegDsc, u64Value, "*");
3383	Log3Func(("\t%#x -> %#x\n", uLogOldVal, pThis->au32Regs[idxRegMem]));
3384	}
3385	else
3386	{
3387	LogRel(("HDA: Invalid write access @0x%x\n", (uint32_t)off));
3388	cbReg = 1;
3389	}
3390	if (rc != VINF_SUCCESS)
3391	break;
3392	if (cbReg >= cb)
3393	break;
3394
3395	/* Advance. */
3396	off += cbReg;
3397	cb -= cbReg;
3398	u64Value >>= cbReg * 8;
3399	if (idxRegDsc == -1)
3400	idxRegDsc = hdaRegLookup(off);
3401	else
3402	{
3403	idxRegDsc++;
3404	if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
3405	\|\| g_aHdaRegMap[idxRegDsc].offset != off)
3406	idxRegDsc = -1;
3407	}
3408	}
3409
3410	#else /* !IN_RING3 */
3411	/* Take the simple way out. */
3412	rc = VINF_IOM_R3_MMIO_WRITE;
3413	#endif /* !IN_RING3 */
3414	}
3415
3416	return rc;
3417	}
3418
3419	#ifdef IN_RING3
3420
3421
3422	/*********************************************************************************************************************************
3423	* Saved state *
3424	*********************************************************************************************************************************/
3425
3426	/**
3427	* @callback_method_impl{FNSSMFIELDGETPUT,
3428	* Version 6 saves the IOC flag in HDABDLEDESC::fFlags as a bool}
3429	*/
3430	static DECLCALLBACK(int)
3431	hdaR3GetPutTrans_HDABDLEDESC_fFlags_6(PSSMHANDLE pSSM, const struct SSMFIELD pField, void pvStruct,
3432	uint32_t fFlags, bool fGetOrPut, void *pvUser)
3433	{
3434	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
3435	RT_NOREF(pSSM, pField, pvStruct, fFlags);
3436	AssertReturn(fGetOrPut, VERR_INTERNAL_ERROR_4);
3437	bool fIoc;
3438	int rc = pDevIns->pHlpR3->pfnSSMGetBool(pSSM, &fIoc);
3439	if (RT_SUCCESS(rc))
3440	{
3441	PHDABDLEDESC pDesc = (PHDABDLEDESC)pvStruct;
3442	pDesc->fFlags = fIoc ? HDA_BDLE_FLAG_IOC : 0;
3443	}
3444	return rc;
3445	}
3446
3447
3448	/**
3449	* @callback_method_impl{FNSSMFIELDGETPUT,
3450	* Versions 1 thru 4 save the IOC flag in HDASTREAMSTATE::DescfFlags as a bool}
3451	*/
3452	static DECLCALLBACK(int)
3453	hdaR3GetPutTrans_HDABDLE_Desc_fFlags_1thru4(PSSMHANDLE pSSM, const struct SSMFIELD pField, void pvStruct,
3454	uint32_t fFlags, bool fGetOrPut, void *pvUser)
3455	{
3456	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
3457	RT_NOREF(pSSM, pField, pvStruct, fFlags);
3458	AssertReturn(fGetOrPut, VERR_INTERNAL_ERROR_4);
3459	bool fIoc;
3460	int rc = pDevIns->pHlpR3->pfnSSMGetBool(pSSM, &fIoc);
3461	if (RT_SUCCESS(rc))
3462	{
3463	PHDABDLE pState = (PHDABDLE)pvStruct;
3464	pState->Desc.fFlags = fIoc ? HDA_BDLE_FLAG_IOC : 0;
3465	}
3466	return rc;
3467	}
3468
3469
3470	static int hdaR3SaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStream)
3471	{
3472	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3473	# ifdef LOG_ENABLED
3474	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
3475	# endif
3476
3477	Log2Func(("[SD%RU8]\n", pStream->u8SD));
3478
3479	/* Save stream ID. */
3480	int rc = pHlp->pfnSSMPutU8(pSSM, pStream->u8SD);
3481	AssertRCReturn(rc, rc);
3482	Assert(pStream->u8SD < HDA_MAX_STREAMS);
3483
3484	rc = pHlp->pfnSSMPutStructEx(pSSM, &pStream->State, sizeof(HDASTREAMSTATE), 0 /fFlags/, g_aSSMStreamStateFields7, NULL);
3485	AssertRCReturn(rc, rc);
3486
3487	rc = pHlp->pfnSSMPutStructEx(pSSM, &pStream->State.BDLE.Desc, sizeof(HDABDLEDESC), 0 /fFlags/, g_aSSMBDLEDescFields7, NULL);
3488	AssertRCReturn(rc, rc);
3489
3490	rc = pHlp->pfnSSMPutStructEx(pSSM, &pStream->State.BDLE.State, sizeof(HDABDLESTATE), 0 /fFlags/, g_aSSMBDLEStateFields7, NULL);
3491	AssertRCReturn(rc, rc);
3492
3493	rc = pHlp->pfnSSMPutStructEx(pSSM, &pStream->State.Period, sizeof(HDASTREAMPERIOD), 0 /* fFlags */, g_aSSMStreamPeriodFields7, NULL);
3494	AssertRCReturn(rc, rc);
3495
3496	uint32_t cbCircBufSize = 0;
3497	uint32_t cbCircBufUsed = 0;
3498
3499	if (pStream->State.pCircBuf)
3500	{
3501	cbCircBufSize = (uint32_t)RTCircBufSize(pStream->State.pCircBuf);
3502	cbCircBufUsed = (uint32_t)RTCircBufUsed(pStream->State.pCircBuf);
3503	}
3504
3505	rc = pHlp->pfnSSMPutU32(pSSM, cbCircBufSize);
3506	AssertRCReturn(rc, rc);
3507
3508	rc = pHlp->pfnSSMPutU32(pSSM, cbCircBufUsed);
3509	AssertRCReturn(rc, rc);
3510
3511	if (cbCircBufUsed)
3512	{
3513	/*
3514	* We now need to get the circular buffer's data without actually modifying
3515	* the internal read / used offsets -- otherwise we would end up with broken audio
3516	* data after saving the state.
3517	*
3518	* So get the current read offset and serialize the buffer data manually based on that.
3519	*/
3520	size_t const offBuf = RTCircBufOffsetRead(pStream->State.pCircBuf);
3521	void *pvBuf;
3522	size_t cbBuf;
3523	RTCircBufAcquireReadBlock(pStream->State.pCircBuf, cbCircBufUsed, &pvBuf, &cbBuf);
3524	Assert(cbBuf);
3525	if (cbBuf)
3526	{
3527	rc = pHlp->pfnSSMPutMem(pSSM, pvBuf, cbBuf);
3528	AssertRC(rc);
3529	if ( RT_SUCCESS(rc)
3530	&& cbBuf < cbCircBufUsed)
3531	{
3532	rc = pHlp->pfnSSMPutMem(pSSM, (uint8_t *)pvBuf - offBuf, cbCircBufUsed - cbBuf);
3533	}
3534	}
3535	RTCircBufReleaseReadBlock(pStream->State.pCircBuf, 0 /* Don't advance read pointer -- see comment above */);
3536	}
3537
3538	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n",
3539	pStream->u8SD,
3540	HDA_STREAM_REG(pThis, LPIB, pStream->u8SD), HDA_STREAM_REG(pThis, CBL, pStream->u8SD), HDA_STREAM_REG(pThis, LVI, pStream->u8SD)));
3541
3542	#ifdef LOG_ENABLED
3543	hdaR3BDLEDumpAll(pThis, pStream->u64BDLBase, pStream->u16LVI + 1);
3544	#endif
3545
3546	return rc;
3547	}
3548
3549	/**
3550	* @callback_method_impl{FNSSMDEVSAVEEXEC}
3551	*/
3552	static DECLCALLBACK(int) hdaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3553	{
3554	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
3555	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3556
3557	/* Save Codec nodes states. */
3558	hdaCodecSaveState(pDevIns, pThis->pCodec, pSSM);
3559
3560	/* Save MMIO registers. */
3561	pHlp->pfnSSMPutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3562	pHlp->pfnSSMPutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3563
3564	/* Save controller-specifc internals. */
3565	pHlp->pfnSSMPutU64(pSSM, pThis->u64WalClk);
3566	pHlp->pfnSSMPutU8(pSSM, pThis->u8IRQL);
3567
3568	/* Save number of streams. */
3569	pHlp->pfnSSMPutU32(pSSM, HDA_MAX_STREAMS);
3570
3571	/* Save stream states. */
3572	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
3573	{
3574	int rc = hdaR3SaveStream(pDevIns, pSSM, &pThis->aStreams[i]);
3575	AssertRCReturn(rc, rc);
3576	}
3577
3578	return VINF_SUCCESS;
3579	}
3580
3581	/**
3582	* Does required post processing when loading a saved state.
3583	*
3584	* @param pDevIns The device instance.
3585	* @param pThis Pointer to HDA state.
3586	*/
3587	static int hdaR3LoadExecPost(PPDMDEVINS pDevIns, PHDASTATE pThis)
3588	{
3589	int rc = VINF_SUCCESS;
3590
3591	/*
3592	* Enable all previously active streams.
3593	*/
3594	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
3595	{
3596	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, i);
3597	if (pStream)
3598	{
3599	int rc2;
3600
3601	bool fActive = RT_BOOL(HDA_STREAM_REG(pThis, CTL, i) & HDA_SDCTL_RUN);
3602	if (fActive)
3603	{
3604	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
3605	/* Make sure to also create the async I/O thread before actually enabling the stream. */
3606	rc2 = hdaR3StreamAsyncIOCreate(pStream);
3607	AssertRC(rc2);
3608
3609	/* ... and enabling it. */
3610	hdaR3StreamAsyncIOEnable(pStream, true /* fEnable */);
3611	#endif
3612	/* Resume the stream's period. */
3613	hdaR3StreamPeriodResume(&pStream->State.Period);
3614
3615	/* (Re-)enable the stream. */
3616	rc2 = hdaR3StreamEnable(pStream, true /* fEnable */);
3617	AssertRC(rc2);
3618
3619	/* Add the stream to the device setup. */
3620	rc2 = hdaR3AddStream(pThis, &pStream->State.Cfg);
3621	AssertRC(rc2);
3622
3623	#ifdef HDA_USE_DMA_ACCESS_HANDLER
3624	/* (Re-)install the DMA handler. */
3625	hdaR3StreamRegisterDMAHandlers(pThis, pStream);
3626	#endif
3627	if (hdaR3StreamTransferIsScheduled(pStream, PDMDevHlpTimerGet(pDevIns, pStream->hTimer)))
3628	hdaR3TimerSet(pDevIns, pStream, hdaR3StreamTransferGetNext(pStream), true /fForce/, 0 /tsNow/);
3629
3630	/* Also keep track of the currently active streams. */
3631	pThis->cStreamsActive++;
3632	}
3633	}
3634	}
3635
3636	LogFlowFuncLeaveRC(rc);
3637	return rc;
3638	}
3639
3640
3641	/**
3642	* Handles loading of all saved state versions older than the current one.
3643	*
3644	* @param pDevIns The device instance.
3645	* @param pThis Pointer to HDA state.
3646	* @param pSSM Pointer to SSM handle.
3647	* @param uVersion Saved state version to load.
3648	*/
3649	static int hdaR3LoadExecLegacy(PPDMDEVINS pDevIns, PHDASTATE pThis, PSSMHANDLE pSSM, uint32_t uVersion)
3650	{
3651	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3652	int rc;
3653
3654	/*
3655	* Load MMIO registers.
3656	*/
3657	uint32_t cRegs;
3658	switch (uVersion)
3659	{
3660	case HDA_SAVED_STATE_VERSION_1:
3661	/* Starting with r71199, we would save 112 instead of 113
3662	registers due to some code cleanups. This only affected trunk
3663	builds in the 4.1 development period. */
3664	cRegs = 113;
3665	if (pHlp->pfnSSMHandleRevision(pSSM) >= 71199)
3666	{
3667	uint32_t uVer = pHlp->pfnSSMHandleVersion(pSSM);
3668	if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3669	&& VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3670	&& VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3671	cRegs = 112;
3672	}
3673	break;
3674
3675	case HDA_SAVED_STATE_VERSION_2:
3676	case HDA_SAVED_STATE_VERSION_3:
3677	cRegs = 112;
3678	AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= 112);
3679	break;
3680
3681	/* Since version 4 we store the register count to stay flexible. */
3682	case HDA_SAVED_STATE_VERSION_4:
3683	case HDA_SAVED_STATE_VERSION_5:
3684	case HDA_SAVED_STATE_VERSION_6:
3685	rc = pHlp->pfnSSMGetU32(pSSM, &cRegs);
3686	AssertRCReturn(rc, rc);
3687	if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3688	LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3689	break;
3690
3691	default:
3692	AssertLogRelMsgFailedReturn(("HDA: Internal Error! Didn't expect saved state version %RU32 ending up in hdaR3LoadExecLegacy!\n",
3693	uVersion), VERR_INTERNAL_ERROR_5);
3694	}
3695
3696	if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3697	{
3698	pHlp->pfnSSMGetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3699	pHlp->pfnSSMSkip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3700	}
3701	else
3702	pHlp->pfnSSMGetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3703
3704	/* Make sure to update the base addresses first before initializing any streams down below. */
3705	pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3706	pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3707	pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE) & DPBASE_ADDR_MASK, HDA_REG(pThis, DPUBASE));
3708
3709	/* Also make sure to update the DMA position bit if this was enabled when saving the state. */
3710	pThis->fDMAPosition = RT_BOOL(HDA_REG(pThis, DPLBASE) & RT_BIT_32(0));
3711
3712	/*
3713	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3714	*
3715	* Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
3716	* every BDLE state, whereas it only needs to be stored
3717	* once for every stream. Most of the BDLE state we can
3718	* get out of the registers anyway, so just ignore those values.
3719	*
3720	* Also, only the current BDLE was saved, regardless whether
3721	* there were more than one (and there are at least two entries,
3722	* according to the spec).
3723	*/
3724	switch (uVersion)
3725	{
3726	case HDA_SAVED_STATE_VERSION_1:
3727	case HDA_SAVED_STATE_VERSION_2:
3728	case HDA_SAVED_STATE_VERSION_3:
3729	case HDA_SAVED_STATE_VERSION_4:
3730	{
3731	/* Only load the internal states.
3732	* The rest will be initialized from the saved registers later. */
3733
3734	/* Note 1: Only the current BDLE for a stream was saved! */
3735	/* Note 2: The stream's saving order is/was fixed, so don't touch! */
3736
3737	/* Output */
3738	PHDASTREAM pStream = &pThis->aStreams[4];
3739	rc = hdaR3StreamInit(pDevIns, pStream, 4 /* Stream descriptor, hardcoded */);
3740	AssertRCReturn(rc, rc);
3741	rc = pHlp->pfnSSMGetStructEx(pSSM, &pStream->State.BDLE, sizeof(pStream->State.BDLE),
3742	0 /* fFlags */, g_aSSMStreamBdleFields1234, pDevIns);
3743	AssertRCReturn(rc, rc);
3744	pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
3745
3746	/* Microphone-In */
3747	pStream = &pThis->aStreams[2];
3748	rc = hdaR3StreamInit(pDevIns, pStream, 2 /* Stream descriptor, hardcoded */);
3749	AssertRCReturn(rc, rc);
3750	rc = pHlp->pfnSSMGetStructEx(pSSM, &pStream->State.BDLE, sizeof(pStream->State.BDLE),
3751	0 /* fFlags */, g_aSSMStreamBdleFields1234, pDevIns);
3752	AssertRCReturn(rc, rc);
3753	pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
3754
3755	/* Line-In */
3756	pStream = &pThis->aStreams[0];
3757	rc = hdaR3StreamInit(pDevIns, pStream, 0 /* Stream descriptor, hardcoded */);
3758	AssertRCReturn(rc, rc);
3759	rc = pHlp->pfnSSMGetStructEx(pSSM, &pStream->State.BDLE, sizeof(pStream->State.BDLE),
3760	0 /* fFlags */, g_aSSMStreamBdleFields1234, pDevIns);
3761	AssertRCReturn(rc, rc);
3762	pStream->State.uCurBDLE = pStream->State.BDLE.State.u32BDLIndex;
3763	break;
3764	}
3765
3766	/*
3767	* v5 & v6 - Since v5 we support flexible stream and BDLE counts.
3768	*/
3769	default:
3770	{
3771	/* Stream count. */
3772	uint32_t cStreams;
3773	rc = pHlp->pfnSSMGetU32(pSSM, &cStreams);
3774	AssertRCReturn(rc, rc);
3775	if (cStreams > HDA_MAX_STREAMS)
3776	return pHlp->pfnSSMSetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
3777	N_("State contains %u streams while %u is the maximum supported"),
3778	cStreams, HDA_MAX_STREAMS);
3779
3780	/* Load stream states. */
3781	for (uint32_t i = 0; i < cStreams; i++)
3782	{
3783	uint8_t idStream;
3784	rc = pHlp->pfnSSMGetU8(pSSM, &idStream);
3785	AssertRCReturn(rc, rc);
3786
3787	HDASTREAM StreamDummy;
3788	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, idStream);
3789	if (!pStream)
3790	{
3791	pStream = &StreamDummy;
3792	LogRel2(("HDA: Warning: Stream ID=%RU32 not supported, skipping loading it ...\n", idStream));
3793	}
3794
3795	rc = hdaR3StreamInit(pDevIns, pStream, idStream);
3796	if (RT_FAILURE(rc))
3797	{
3798	LogRel(("HDA: Stream #%RU32: Initialization of stream %RU8 failed, rc=%Rrc\n", i, idStream, rc));
3799	break;
3800	}
3801
3802	/*
3803	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3804	*/
3805	if (uVersion == HDA_SAVED_STATE_VERSION_5)
3806	{
3807	struct V5HDASTREAMSTATE /* HDASTREAMSTATE + HDABDLE */
3808	{
3809	uint16_t cBLDEs;
3810	uint16_t uCurBDLE;
3811	uint32_t u32BDLEIndex;
3812	uint32_t cbBelowFIFOW;
3813	uint32_t u32BufOff;
3814	} Tmp;
3815	static SSMFIELD const g_aV5State1Fields[] =
3816	{
3817	SSMFIELD_ENTRY(V5HDASTREAMSTATE, cBLDEs),
3818	SSMFIELD_ENTRY(V5HDASTREAMSTATE, uCurBDLE),
3819	SSMFIELD_ENTRY_TERM()
3820	};
3821	rc = pHlp->pfnSSMGetStructEx(pSSM, &Tmp, sizeof(Tmp), 0 /* fFlags */, g_aV5State1Fields, NULL);
3822	AssertRCReturn(rc, rc);
3823	pStream->State.uCurBDLE = Tmp.uCurBDLE;
3824
3825	for (uint16_t a = 0; a < Tmp.cBLDEs; a++)
3826	{
3827	static SSMFIELD const g_aV5State2Fields[] =
3828	{
3829	SSMFIELD_ENTRY(V5HDASTREAMSTATE, u32BDLEIndex),
3830	SSMFIELD_ENTRY_OLD(au8FIFO, 256),
3831	SSMFIELD_ENTRY(V5HDASTREAMSTATE, cbBelowFIFOW),
3832	SSMFIELD_ENTRY_TERM()
3833	};
3834	rc = pHlp->pfnSSMGetStructEx(pSSM, &Tmp, sizeof(Tmp), 0 /* fFlags */, g_aV5State2Fields, NULL);
3835	AssertRCReturn(rc, rc);
3836	if (Tmp.u32BDLEIndex == pStream->State.uCurBDLE)
3837	{
3838	pStream->State.BDLE.State.cbBelowFIFOW = Tmp.cbBelowFIFOW;
3839	pStream->State.BDLE.State.u32BufOff = Tmp.u32BufOff;
3840	}
3841	}
3842	}
3843	else
3844	{
3845	rc = pHlp->pfnSSMGetStructEx(pSSM, &pStream->State, sizeof(HDASTREAMSTATE),
3846	0 /* fFlags */, g_aSSMStreamStateFields6, NULL);
3847	AssertRCReturn(rc, rc);
3848
3849	rc = pHlp->pfnSSMGetStructEx(pSSM, &pStream->State.BDLE.Desc, sizeof(pStream->State.BDLE.Desc),
3850	0 /* fFlags */, g_aSSMBDLEDescFields6, pDevIns);
3851	AssertRCReturn(rc, rc);
3852
3853	rc = pHlp->pfnSSMGetStructEx(pSSM, &pStream->State.BDLE.State, sizeof(HDABDLESTATE),
3854	0 /* fFlags */, g_aSSMBDLEStateFields6, NULL);
3855	AssertRCReturn(rc, rc);
3856
3857	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n", idStream, HDA_STREAM_REG(pThis, LPIB, idStream),
3858	HDA_STREAM_REG(pThis, CBL, idStream), HDA_STREAM_REG(pThis, LVI, idStream)));
3859	#ifdef LOG_ENABLED
3860	hdaR3BDLEDumpAll(pThis, pStream->u64BDLBase, pStream->u16LVI + 1);
3861	#endif
3862	}
3863
3864	} /* for cStreams */
3865	break;
3866	} /* default */
3867	}
3868
3869	return rc;
3870	}
3871
3872	/**
3873	* @callback_method_impl{FNSSMDEVLOADEXEC}
3874	*/
3875	static DECLCALLBACK(int) hdaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3876	{
3877	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
3878	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3879
3880	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3881
3882	LogRel2(("hdaR3LoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
3883
3884	/*
3885	* Load Codec nodes states.
3886	*/
3887	int rc = hdaCodecLoadState(pDevIns, pThis->pCodec, pSSM, uVersion);
3888	if (RT_FAILURE(rc))
3889	{
3890	LogRel(("HDA: Failed loading codec state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
3891	return rc;
3892	}
3893
3894	if (uVersion <= HDA_SAVED_STATE_VERSION_6) /* Handle older saved states? */
3895	{
3896	rc = hdaR3LoadExecLegacy(pDevIns, pThis, pSSM, uVersion);
3897	if (RT_SUCCESS(rc))
3898	rc = hdaR3LoadExecPost(pDevIns, pThis);
3899	return rc;
3900	}
3901
3902	/*
3903	* Load MMIO registers.
3904	*/
3905	uint32_t cRegs;
3906	rc = pHlp->pfnSSMGetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
3907	AssertRCReturn(rc, rc);
3908	if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3909	LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3910
3911	if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3912	{
3913	pHlp->pfnSSMGetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3914	rc = pHlp->pfnSSMSkip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3915	AssertRCReturn(rc, rc);
3916	}
3917	else
3918	{
3919	rc = pHlp->pfnSSMGetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3920	AssertRCReturn(rc, rc);
3921	}
3922
3923	/* Make sure to update the base addresses first before initializing any streams down below. */
3924	pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3925	pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3926	pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE) & DPBASE_ADDR_MASK, HDA_REG(pThis, DPUBASE));
3927
3928	/* Also make sure to update the DMA position bit if this was enabled when saving the state. */
3929	pThis->fDMAPosition = RT_BOOL(HDA_REG(pThis, DPLBASE) & RT_BIT_32(0));
3930
3931	/*
3932	* Load controller-specifc internals.
3933	* Don't annoy other team mates (forgot this for state v7).
3934	*/
3935	if ( pHlp->pfnSSMHandleRevision(pSSM) >= 116273
3936	\|\| pHlp->pfnSSMHandleVersion(pSSM) >= VBOX_FULL_VERSION_MAKE(5, 2, 0))
3937	{
3938	pHlp->pfnSSMGetU64(pSSM, &pThis->u64WalClk);
3939	rc = pHlp->pfnSSMGetU8(pSSM, &pThis->u8IRQL);
3940	AssertRCReturn(rc, rc);
3941	}
3942
3943	/*
3944	* Load streams.
3945	*/
3946	uint32_t cStreams;
3947	rc = pHlp->pfnSSMGetU32(pSSM, &cStreams);
3948	AssertRCReturn(rc, rc);
3949	if (cStreams > HDA_MAX_STREAMS)
3950	return pHlp->pfnSSMSetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
3951	N_("State contains %u streams while %u is the maximum supported"),
3952	cStreams, HDA_MAX_STREAMS);
3953	Log2Func(("cStreams=%RU32\n", cStreams));
3954
3955	/* Load stream states. */
3956	for (uint32_t i = 0; i < cStreams; i++)
3957	{
3958	uint8_t idStream;
3959	rc = pHlp->pfnSSMGetU8(pSSM, &idStream);
3960	AssertRCReturn(rc, rc);
3961
3962	PHDASTREAM pStream = hdaGetStreamFromSD(pThis, idStream);
3963	HDASTREAM StreamDummy;
3964
3965	if (!pStream)
3966	{
3967	RT_ZERO(StreamDummy);
3968	pStream = &StreamDummy;
3969	LogRel2(("HDA: Warning: Loading of stream #%RU8 not supported, skipping to load ...\n", idStream));
3970	}
3971
3972	rc = hdaR3StreamInit(pDevIns, pStream, idStream);
3973	if (RT_FAILURE(rc))
3974	{
3975	LogRel(("HDA: Stream #%RU8: Loading initialization failed, rc=%Rrc\n", idStream, rc));
3976	/* Continue. */
3977	}
3978
3979	rc = pHlp->pfnSSMGetStructEx(pSSM, &pStream->State, sizeof(HDASTREAMSTATE),
3980	0 /* fFlags */, g_aSSMStreamStateFields7, NULL);
3981	AssertRCReturn(rc, rc);
3982
3983	/*
3984	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3985	*/
3986	rc = pHlp->pfnSSMGetStructEx(pSSM, &pStream->State.BDLE.Desc, sizeof(HDABDLEDESC),
3987	0 /* fFlags */, g_aSSMBDLEDescFields7, NULL);
3988	AssertRCReturn(rc, rc);
3989
3990	rc = pHlp->pfnSSMGetStructEx(pSSM, &pStream->State.BDLE.State, sizeof(HDABDLESTATE),
3991	0 /* fFlags */, g_aSSMBDLEStateFields7, NULL);
3992	AssertRCReturn(rc, rc);
3993
3994	Log2Func(("[SD%RU8] %R[bdle]\n", pStream->u8SD, &pStream->State.BDLE));
3995
3996	/*
3997	* Load period state.
3998	*/
3999	hdaR3StreamPeriodInit(&pStream->State.Period, pStream->u8SD, pStream->u16LVI, pStream->u32CBL, &pStream->State.Cfg);
4000
4001	rc = pHlp->pfnSSMGetStructEx(pSSM, &pStream->State.Period, sizeof(HDASTREAMPERIOD),
4002	0 /* fFlags */, g_aSSMStreamPeriodFields7, NULL);
4003	AssertRCReturn(rc, rc);
4004
4005	/*
4006	* Load internal (FIFO) buffer.
4007	*/
4008	uint32_t cbCircBufSize = 0;
4009	pHlp->pfnSSMGetU32(pSSM, &cbCircBufSize); /* cbCircBuf */
4010	uint32_t cbCircBufUsed = 0;
4011	rc = pHlp->pfnSSMGetU32(pSSM, &cbCircBufUsed); /* cbCircBuf */
4012	AssertRCReturn(rc, rc);
4013
4014	if (cbCircBufSize) /* If 0, skip the buffer. */
4015	{
4016	/* Paranoia. */
4017	AssertLogRelMsgReturn(cbCircBufSize <= _1M,
4018	("HDA: Saved state contains bogus DMA buffer size (%RU32) for stream #%RU8",
4019	cbCircBufSize, idStream),
4020	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
4021	AssertLogRelMsgReturn(cbCircBufUsed <= cbCircBufSize,
4022	("HDA: Saved state contains invalid DMA buffer usage (%RU32/%RU32) for stream #%RU8",
4023	cbCircBufUsed, cbCircBufSize, idStream),
4024	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
4025
4026	/* Do we need to cre-create the circular buffer do fit the data size? */
4027	if ( pStream->State.pCircBuf
4028	&& cbCircBufSize != (uint32_t)RTCircBufSize(pStream->State.pCircBuf))
4029	{
4030	RTCircBufDestroy(pStream->State.pCircBuf);
4031	pStream->State.pCircBuf = NULL;
4032	}
4033
4034	rc = RTCircBufCreate(&pStream->State.pCircBuf, cbCircBufSize);
4035	AssertRCReturn(rc, rc);
4036
4037	if (cbCircBufUsed)
4038	{
4039	void *pvBuf;
4040	size_t cbBuf;
4041	RTCircBufAcquireWriteBlock(pStream->State.pCircBuf, cbCircBufUsed, &pvBuf, &cbBuf);
4042
4043	AssertLogRelMsgReturn(cbBuf == cbCircBufUsed, ("cbBuf=%zu cbCircBufUsed=%zu\n", cbBuf, cbCircBufUsed),
4044	VERR_INTERNAL_ERROR_3);
4045	rc = pHlp->pfnSSMGetMem(pSSM, pvBuf, cbBuf);
4046	AssertRCReturn(rc, rc);
4047
4048	RTCircBufReleaseWriteBlock(pStream->State.pCircBuf, cbBuf);
4049
4050	Assert(cbBuf == cbCircBufUsed);
4051	}
4052	}
4053
4054	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n", idStream, HDA_STREAM_REG(pThis, LPIB, idStream),
4055	HDA_STREAM_REG(pThis, CBL, idStream), HDA_STREAM_REG(pThis, LVI, idStream)));
4056	#ifdef LOG_ENABLED
4057	hdaR3BDLEDumpAll(pThis, pStream->u64BDLBase, pStream->u16LVI + 1);
4058	#endif
4059	/** @todo (Re-)initialize active periods? */
4060
4061	} /* for cStreams */
4062
4063	rc = hdaR3LoadExecPost(pDevIns, pThis);
4064	AssertRC(rc);
4065
4066	LogFlowFuncLeaveRC(rc);
4067	return rc;
4068	}
4069
4070
4071	/*********************************************************************************************************************************
4072	* IPRT format type handlers *
4073	*********************************************************************************************************************************/
4074
4075	/**
4076	* @callback_method_impl{FNRTSTRFORMATTYPE}
4077	*/
4078	static DECLCALLBACK(size_t) hdaR3StrFmtBDLE(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4079	const char pszType, void const pvValue,
4080	int cchWidth, int cchPrecision, unsigned fFlags,
4081	void *pvUser)
4082	{
4083	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4084	PHDABDLE pBDLE = (PHDABDLE)pvValue;
4085	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4086	"BDLE(idx:%RU32, off:%RU32, fifow:%RU32, IOC:%RTbool, DMA[%RU32 bytes @ 0x%x])",
4087	pBDLE->State.u32BDLIndex, pBDLE->State.u32BufOff, pBDLE->State.cbBelowFIFOW,
4088	pBDLE->Desc.fFlags & HDA_BDLE_FLAG_IOC, pBDLE->Desc.u32BufSize, pBDLE->Desc.u64BufAddr);
4089	}
4090
4091	/**
4092	* @callback_method_impl{FNRTSTRFORMATTYPE}
4093	*/
4094	static DECLCALLBACK(size_t) hdaR3StrFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4095	const char pszType, void const pvValue,
4096	int cchWidth, int cchPrecision, unsigned fFlags,
4097	void *pvUser)
4098	{
4099	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4100	uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
4101	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4102	"SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
4103	uSDCTL,
4104	uSDCTL & HDA_SDCTL_DIR ? "OUT" : "IN",
4105	RT_BOOL(uSDCTL & HDA_SDCTL_TP),
4106	(uSDCTL & HDA_SDCTL_STRIPE_MASK) >> HDA_SDCTL_STRIPE_SHIFT,
4107	RT_BOOL(uSDCTL & HDA_SDCTL_DEIE),
4108	RT_BOOL(uSDCTL & HDA_SDCTL_FEIE),
4109	RT_BOOL(uSDCTL & HDA_SDCTL_IOCE),
4110	RT_BOOL(uSDCTL & HDA_SDCTL_RUN),
4111	RT_BOOL(uSDCTL & HDA_SDCTL_SRST));
4112	}
4113
4114	/**
4115	* @callback_method_impl{FNRTSTRFORMATTYPE}
4116	*/
4117	static DECLCALLBACK(size_t) hdaR3StrFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4118	const char pszType, void const pvValue,
4119	int cchWidth, int cchPrecision, unsigned fFlags,
4120	void *pvUser)
4121	{
4122	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4123	uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
4124	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, uSDFIFOS ? uSDFIFOS + 1 : 0);
4125	}
4126
4127	/**
4128	* @callback_method_impl{FNRTSTRFORMATTYPE}
4129	*/
4130	static DECLCALLBACK(size_t) hdaR3StrFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4131	const char pszType, void const pvValue,
4132	int cchWidth, int cchPrecision, unsigned fFlags,
4133	void *pvUser)
4134	{
4135	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4136	uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
4137	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
4138	}
4139
4140	/**
4141	* @callback_method_impl{FNRTSTRFORMATTYPE}
4142	*/
4143	static DECLCALLBACK(size_t) hdaR3StrFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4144	const char pszType, void const pvValue,
4145	int cchWidth, int cchPrecision, unsigned fFlags,
4146	void *pvUser)
4147	{
4148	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4149	uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
4150	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4151	"SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
4152	uSdSts,
4153	RT_BOOL(uSdSts & HDA_SDSTS_FIFORDY),
4154	RT_BOOL(uSdSts & HDA_SDSTS_DESE),
4155	RT_BOOL(uSdSts & HDA_SDSTS_FIFOE),
4156	RT_BOOL(uSdSts & HDA_SDSTS_BCIS));
4157	}
4158
4159
4160	/*********************************************************************************************************************************
4161	* Debug Info Item Handlers *
4162	*********************************************************************************************************************************/
4163
4164	static int hdaR3DbgLookupRegByName(const char *pszArgs)
4165	{
4166	int iReg = 0;
4167	for (; iReg < HDA_NUM_REGS; ++iReg)
4168	if (!RTStrICmp(g_aHdaRegMap[iReg].abbrev, pszArgs))
4169	return iReg;
4170	return -1;
4171	}
4172
4173
4174	static void hdaR3DbgPrintRegister(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
4175	{
4176	Assert( pThis
4177	&& iHdaIndex >= 0
4178	&& iHdaIndex < HDA_NUM_REGS);
4179	pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].abbrev, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].mem_idx]);
4180	}
4181
4182	/**
4183	* @callback_method_impl{FNDBGFHANDLERDEV}
4184	*/
4185	static DECLCALLBACK(void) hdaR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4186	{
4187	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
4188	int iHdaRegisterIndex = hdaR3DbgLookupRegByName(pszArgs);
4189	if (iHdaRegisterIndex != -1)
4190	hdaR3DbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
4191	else
4192	{
4193	for(iHdaRegisterIndex = 0; (unsigned int)iHdaRegisterIndex < HDA_NUM_REGS; ++iHdaRegisterIndex)
4194	hdaR3DbgPrintRegister(pThis, pHlp, iHdaRegisterIndex);
4195	}
4196	}
4197
4198	static void hdaR3DbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
4199	{
4200	Assert( pThis
4201	&& iIdx >= 0
4202	&& iIdx < HDA_MAX_STREAMS);
4203
4204	const PHDASTREAM pStream = &pThis->aStreams[iIdx];
4205
4206	pHlp->pfnPrintf(pHlp, "Stream #%d:\n", iIdx);
4207	pHlp->pfnPrintf(pHlp, "\tSD%dCTL : %R[sdctl]\n", iIdx, HDA_STREAM_REG(pThis, CTL, iIdx));
4208	pHlp->pfnPrintf(pHlp, "\tSD%dCTS : %R[sdsts]\n", iIdx, HDA_STREAM_REG(pThis, STS, iIdx));
4209	pHlp->pfnPrintf(pHlp, "\tSD%dFIFOS: %R[sdfifos]\n", iIdx, HDA_STREAM_REG(pThis, FIFOS, iIdx));
4210	pHlp->pfnPrintf(pHlp, "\tSD%dFIFOW: %R[sdfifow]\n", iIdx, HDA_STREAM_REG(pThis, FIFOW, iIdx));
4211	pHlp->pfnPrintf(pHlp, "\tBDLE : %R[bdle]\n", &pStream->State.BDLE);
4212	}
4213
4214	static void hdaR3DbgPrintBDLE(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iIdx)
4215	{
4216	Assert( pThis
4217	&& iIdx >= 0
4218	&& iIdx < HDA_MAX_STREAMS);
4219
4220	const PHDASTREAM pStream = &pThis->aStreams[iIdx];
4221	const PHDABDLE pBDLE = &pStream->State.BDLE;
4222
4223	pHlp->pfnPrintf(pHlp, "Stream #%d BDLE:\n", iIdx);
4224
4225	uint64_t u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, iIdx),
4226	HDA_STREAM_REG(pThis, BDPU, iIdx));
4227	uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, iIdx);
4228	uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, iIdx);
4229
4230	if (!u64BaseDMA)
4231	return;
4232
4233	pHlp->pfnPrintf(pHlp, "\tCurrent: %R[bdle]\n\n", pBDLE);
4234
4235	pHlp->pfnPrintf(pHlp, "\tMemory:\n");
4236
4237	uint32_t cbBDLE = 0;
4238	for (uint16_t i = 0; i < u16LVI + 1; i++)
4239	{
4240	HDABDLEDESC bd;
4241	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), u64BaseDMA + i * sizeof(HDABDLEDESC), &bd, sizeof(bd));
4242
4243	pHlp->pfnPrintf(pHlp, "\t\t%s #%03d BDLE(adr:0x%llx, size:%RU32, ioc:%RTbool)\n",
4244	pBDLE->State.u32BDLIndex == i ? "*" : " ", i, bd.u64BufAddr, bd.u32BufSize, bd.fFlags & HDA_BDLE_FLAG_IOC);
4245
4246	cbBDLE += bd.u32BufSize;
4247	}
4248
4249	pHlp->pfnPrintf(pHlp, "Total: %RU32 bytes\n", cbBDLE);
4250
4251	if (cbBDLE != u32CBL)
4252	pHlp->pfnPrintf(pHlp, "Warning: %RU32 bytes does not match CBL (%RU32)!\n", cbBDLE, u32CBL);
4253
4254	pHlp->pfnPrintf(pHlp, "DMA counters (base @ 0x%llx):\n", u64BaseDMA);
4255	if (!u64BaseDMA) /* No DMA base given? Bail out. */
4256	{
4257	pHlp->pfnPrintf(pHlp, "\tNo counters found\n");
4258	return;
4259	}
4260
4261	for (int i = 0; i < u16LVI + 1; i++)
4262	{
4263	uint32_t uDMACnt;
4264	PDMDevHlpPhysRead(pThis->CTX_SUFF(pDevIns), (pThis->u64DPBase & DPBASE_ADDR_MASK) + (i * 2 * sizeof(uint32_t)),
4265	&uDMACnt, sizeof(uDMACnt));
4266
4267	pHlp->pfnPrintf(pHlp, "\t#%03d DMA @ 0x%x\n", i , uDMACnt);
4268	}
4269	}
4270
4271	static int hdaR3DbgLookupStrmIdx(PHDASTATE pThis, const char *pszArgs)
4272	{
4273	RT_NOREF(pThis, pszArgs);
4274	/** @todo Add args parsing. */
4275	return -1;
4276	}
4277
4278	/**
4279	* @callback_method_impl{FNDBGFHANDLERDEV}
4280	*/
4281	static DECLCALLBACK(void) hdaR3DbgInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4282	{
4283	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
4284	int iHdaStreamdex = hdaR3DbgLookupStrmIdx(pThis, pszArgs);
4285	if (iHdaStreamdex != -1)
4286	hdaR3DbgPrintStream(pThis, pHlp, iHdaStreamdex);
4287	else
4288	for(iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
4289	hdaR3DbgPrintStream(pThis, pHlp, iHdaStreamdex);
4290	}
4291
4292	/**
4293	* @callback_method_impl{FNDBGFHANDLERDEV}
4294	*/
4295	static DECLCALLBACK(void) hdaR3DbgInfoBDLE(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4296	{
4297	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
4298	int iHdaStreamdex = hdaR3DbgLookupStrmIdx(pThis, pszArgs);
4299	if (iHdaStreamdex != -1)
4300	hdaR3DbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
4301	else
4302	for (iHdaStreamdex = 0; iHdaStreamdex < HDA_MAX_STREAMS; ++iHdaStreamdex)
4303	hdaR3DbgPrintBDLE(pThis, pHlp, iHdaStreamdex);
4304	}
4305
4306	/**
4307	* @callback_method_impl{FNDBGFHANDLERDEV}
4308	*/
4309	static DECLCALLBACK(void) hdaR3DbgInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4310	{
4311	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
4312
4313	if (pThis->pCodec->pfnDbgListNodes)
4314	pThis->pCodec->pfnDbgListNodes(pThis->pCodec, pHlp, pszArgs);
4315	else
4316	pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
4317	}
4318
4319	/**
4320	* @callback_method_impl{FNDBGFHANDLERDEV}
4321	*/
4322	static DECLCALLBACK(void) hdaR3DbgInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4323	{
4324	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
4325
4326	if (pThis->pCodec->pfnDbgSelector)
4327	pThis->pCodec->pfnDbgSelector(pThis->pCodec, pHlp, pszArgs);
4328	else
4329	pHlp->pfnPrintf(pHlp, "Codec implementation doesn't provide corresponding callback\n");
4330	}
4331
4332	/**
4333	* @callback_method_impl{FNDBGFHANDLERDEV}
4334	*/
4335	static DECLCALLBACK(void) hdaR3DbgInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4336	{
4337	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
4338
4339	if (pThis->pMixer)
4340	AudioMixerDebug(pThis->pMixer, pHlp, pszArgs);
4341	else
4342	pHlp->pfnPrintf(pHlp, "Mixer not available\n");
4343	}
4344
4345
4346	/*********************************************************************************************************************************
4347	* PDMIBASE *
4348	*********************************************************************************************************************************/
4349
4350	/**
4351	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
4352	*/
4353	static DECLCALLBACK(void ) hdaR3QueryInterface(struct PDMIBASE pInterface, const char *pszIID)
4354	{
4355	PHDASTATE pThis = RT_FROM_MEMBER(pInterface, HDASTATE, IBase);
4356	Assert(&pThis->IBase == pInterface);
4357
4358	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThis->IBase);
4359	return NULL;
4360	}
4361
4362
4363	/*********************************************************************************************************************************
4364	* PDMDEVREGR3 *
4365	*********************************************************************************************************************************/
4366
4367	/**
4368	* Attach command, internal version.
4369	*
4370	* This is called to let the device attach to a driver for a specified LUN
4371	* during runtime. This is not called during VM construction, the device
4372	* constructor has to attach to all the available drivers.
4373	*
4374	* @returns VBox status code.
4375	* @param pThis HDA state.
4376	* @param uLUN The logical unit which is being detached.
4377	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4378	* @param ppDrv Attached driver instance on success. Optional.
4379	*/
4380	static int hdaR3AttachInternal(PHDASTATE pThis, unsigned uLUN, uint32_t fFlags, PHDADRIVER *ppDrv)
4381	{
4382	RT_NOREF(fFlags);
4383
4384	/*
4385	* Attach driver.
4386	*/
4387	char *pszDesc;
4388	if (RTStrAPrintf(&pszDesc, "Audio driver port (HDA) for LUN#%u", uLUN) <= 0)
4389	AssertLogRelFailedReturn(VERR_NO_MEMORY);
4390
4391	PPDMIBASE pDrvBase;
4392	int rc = PDMDevHlpDriverAttach(pThis->pDevInsR3, uLUN,
4393	&pThis->IBase, &pDrvBase, pszDesc);
4394	if (RT_SUCCESS(rc))
4395	{
4396	PHDADRIVER pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
4397	if (pDrv)
4398	{
4399	pDrv->pDrvBase = pDrvBase;
4400	pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
4401	AssertMsg(pDrv->pConnector != NULL, ("Configuration error: LUN#%u has no host audio interface, rc=%Rrc\n", uLUN, rc));
4402	pDrv->pHDAState = pThis;
4403	pDrv->uLUN = uLUN;
4404
4405	/*
4406	* For now we always set the driver at LUN 0 as our primary
4407	* host backend. This might change in the future.
4408	*/
4409	if (pDrv->uLUN == 0)
4410	pDrv->fFlags \|= PDMAUDIODRVFLAGS_PRIMARY;
4411
4412	LogFunc(("LUN#%u: pCon=%p, drvFlags=0x%x\n", uLUN, pDrv->pConnector, pDrv->fFlags));
4413
4414	/* Attach to driver list if not attached yet. */
4415	if (!pDrv->fAttached)
4416	{
4417	RTListAppend(&pThis->lstDrv, &pDrv->Node);
4418	pDrv->fAttached = true;
4419	}
4420
4421	if (ppDrv)
4422	*ppDrv = pDrv;
4423	}
4424	else
4425	rc = VERR_NO_MEMORY;
4426	}
4427	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4428	LogFunc(("No attached driver for LUN #%u\n", uLUN));
4429
4430	if (RT_FAILURE(rc))
4431	{
4432	/* Only free this string on failure;
4433	* must remain valid for the live of the driver instance. */
4434	RTStrFree(pszDesc);
4435	}
4436
4437	LogFunc(("uLUN=%u, fFlags=0x%x, rc=%Rrc\n", uLUN, fFlags, rc));
4438	return rc;
4439	}
4440
4441	/**
4442	* Detach command, internal version.
4443	*
4444	* This is called to let the device detach from a driver for a specified LUN
4445	* during runtime.
4446	*
4447	* @returns VBox status code.
4448	* @param pThis HDA state.
4449	* @param pDrv Driver to detach from device.
4450	* @param fFlags Flags, combination of the PDMDEVATT_FLAGS_* \#defines.
4451	*/
4452	static int hdaR3DetachInternal(PHDASTATE pThis, PHDADRIVER pDrv, uint32_t fFlags)
4453	{
4454	RT_NOREF(fFlags);
4455
4456	/* First, remove the driver from our list and destory it's associated streams.
4457	* This also will un-set the driver as a recording source (if associated). */
4458	hdaR3MixerRemoveDrv(pThis, pDrv);
4459
4460	/* Next, search backwards for a capable (attached) driver which now will be the
4461	* new recording source. */
4462	PHDADRIVER pDrvCur;
4463	RTListForEachReverse(&pThis->lstDrv, pDrvCur, HDADRIVER, Node)
4464	{
4465	if (!pDrvCur->pConnector)
4466	continue;
4467
4468	PDMAUDIOBACKENDCFG Cfg;
4469	int rc2 = pDrvCur->pConnector->pfnGetConfig(pDrvCur->pConnector, &Cfg);
4470	if (RT_FAILURE(rc2))
4471	continue;
4472
4473	PHDADRIVERSTREAM pDrvStrm;
4474	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
4475	pDrvStrm = &pDrvCur->MicIn;
4476	if ( pDrvStrm
4477	&& pDrvStrm->pMixStrm)
4478	{
4479	rc2 = AudioMixerSinkSetRecordingSource(pThis->SinkMicIn.pMixSink, pDrvStrm->pMixStrm);
4480	if (RT_SUCCESS(rc2))
4481	LogRel2(("HDA: Set new recording source for 'Mic In' to '%s'\n", Cfg.szName));
4482	}
4483	# endif
4484	pDrvStrm = &pDrvCur->LineIn;
4485	if ( pDrvStrm
4486	&& pDrvStrm->pMixStrm)
4487	{
4488	rc2 = AudioMixerSinkSetRecordingSource(pThis->SinkLineIn.pMixSink, pDrvStrm->pMixStrm);
4489	if (RT_SUCCESS(rc2))
4490	LogRel2(("HDA: Set new recording source for 'Line In' to '%s'\n", Cfg.szName));
4491	}
4492	}
4493
4494	LogFunc(("uLUN=%u, fFlags=0x%x\n", pDrv->uLUN, fFlags));
4495	return VINF_SUCCESS;
4496	}
4497
4498	/**
4499	* @interface_method_impl{PDMDEVREG,pfnAttach}
4500	*/
4501	static DECLCALLBACK(int) hdaR3Attach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4502	{
4503	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
4504
4505	DEVHDA_LOCK_RETURN(pDevIns, pThis, VERR_IGNORED);
4506
4507	LogFunc(("uLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
4508
4509	PHDADRIVER pDrv;
4510	int rc2 = hdaR3AttachInternal(pThis, uLUN, fFlags, &pDrv);
4511	if (RT_SUCCESS(rc2))
4512	rc2 = hdaR3MixerAddDrv(pThis, pDrv);
4513
4514	if (RT_FAILURE(rc2))
4515	LogFunc(("Failed with %Rrc\n", rc2));
4516
4517	DEVHDA_UNLOCK(pDevIns, pThis);
4518
4519	return VINF_SUCCESS;
4520	}
4521
4522	/**
4523	* @interface_method_impl{PDMDEVREG,pfnDetach}
4524	*/
4525	static DECLCALLBACK(void) hdaR3Detach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4526	{
4527	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
4528
4529	DEVHDA_LOCK(pDevIns, pThis);
4530
4531	LogFunc(("uLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
4532
4533	PHDADRIVER pDrv, pDrvNext;
4534	RTListForEachSafe(&pThis->lstDrv, pDrv, pDrvNext, HDADRIVER, Node)
4535	{
4536	if (pDrv->uLUN == uLUN)
4537	{
4538	int rc2 = hdaR3DetachInternal(pThis, pDrv, fFlags);
4539	if (RT_SUCCESS(rc2))
4540	{
4541	RTMemFree(pDrv);
4542	pDrv = NULL;
4543	}
4544
4545	break;
4546	}
4547	}
4548
4549	DEVHDA_UNLOCK(pDevIns, pThis);
4550	}
4551
4552	/**
4553	* Powers off the device.
4554	*
4555	* @param pDevIns Device instance to power off.
4556	*/
4557	static DECLCALLBACK(void) hdaR3PowerOff(PPDMDEVINS pDevIns)
4558	{
4559	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
4560
4561	DEVHDA_LOCK_RETURN_VOID(pDevIns, pThis);
4562
4563	LogRel2(("HDA: Powering off ...\n"));
4564
4565	/* Ditto goes for the codec, which in turn uses the mixer. */
4566	hdaCodecPowerOff(pThis->pCodec);
4567
4568	/*
4569	* Note: Destroy the mixer while powering off and not in hdaR3Destruct,
4570	* giving the mixer the chance to release any references held to
4571	* PDM audio streams it maintains.
4572	*/
4573	if (pThis->pMixer)
4574	{
4575	AudioMixerDestroy(pThis->pMixer);
4576	pThis->pMixer = NULL;
4577	}
4578
4579	DEVHDA_UNLOCK(pDevIns, pThis);
4580	}
4581
4582	/**
4583	* Replaces a driver with a the NullAudio drivers.
4584	*
4585	* @returns VBox status code.
4586	* @param pThis Device instance.
4587	* @param iLun The logical unit which is being replaced.
4588	*/
4589	static int hdaR3ReconfigLunWithNullAudio(PHDASTATE pThis, unsigned iLun)
4590	{
4591	int rc = PDMDevHlpDriverReconfigure2(pThis->pDevInsR3, iLun, "AUDIO", "NullAudio");
4592	if (RT_SUCCESS(rc))
4593	rc = hdaR3AttachInternal(pThis, iLun, 0 /* fFlags /, NULL / ppDrv */);
4594	LogFunc(("pThis=%p, iLun=%u, rc=%Rrc\n", pThis, iLun, rc));
4595	return rc;
4596	}
4597
4598
4599	/**
4600	* @interface_method_impl{PDMDEVREG,pfnReset}
4601	*/
4602	static DECLCALLBACK(void) hdaR3Reset(PPDMDEVINS pDevIns)
4603	{
4604	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
4605
4606	LogFlowFuncEnter();
4607
4608	DEVHDA_LOCK_RETURN_VOID(pDevIns, pThis);
4609
4610	/*
4611	* 18.2.6,7 defines that values of this registers might be cleared on power on/reset
4612	* hdaR3Reset shouldn't affects these registers.
4613	*/
4614	HDA_REG(pThis, WAKEEN) = 0x0;
4615
4616	hdaR3GCTLReset(pThis);
4617
4618	/* Indicate that HDA is not in reset. The firmware is supposed to (un)reset HDA,
4619	* but we can take a shortcut.
4620	*/
4621	HDA_REG(pThis, GCTL) = HDA_GCTL_CRST;
4622
4623	DEVHDA_UNLOCK(pDevIns, pThis);
4624	}
4625
4626
4627	/**
4628	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4629	*/
4630	static DECLCALLBACK(int) hdaR3Destruct(PPDMDEVINS pDevIns)
4631	{
4632	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns); /* this shall come first */
4633	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
4634	DEVHDA_LOCK(pDevIns, pThis); /** @todo r=bird: this will fail on early constructor failure. */
4635
4636	PHDADRIVER pDrv;
4637	while (!RTListIsEmpty(&pThis->lstDrv))
4638	{
4639	pDrv = RTListGetFirst(&pThis->lstDrv, HDADRIVER, Node);
4640
4641	RTListNodeRemove(&pDrv->Node);
4642	RTMemFree(pDrv);
4643	}
4644
4645	if (pThis->pCodec)
4646	{
4647	hdaCodecDestruct(pThis->pCodec);
4648
4649	RTMemFree(pThis->pCodec);
4650	pThis->pCodec = NULL;
4651	}
4652
4653	RTMemFree(pThis->pu32CorbBuf);
4654	pThis->pu32CorbBuf = NULL;
4655
4656	RTMemFree(pThis->pu64RirbBuf);
4657	pThis->pu64RirbBuf = NULL;
4658
4659	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
4660	hdaR3StreamDestroy(&pThis->aStreams[i]);
4661
4662	DEVHDA_UNLOCK(pDevIns, pThis);
4663	return VINF_SUCCESS;
4664	}
4665
4666
4667	/**
4668	* @interface_method_impl{PDMDEVREG,pfnConstruct}
4669	*/
4670	static DECLCALLBACK(int) hdaR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4671	{
4672	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); /* this shall come first */
4673	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
4674	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4675	Assert(iInstance == 0); RT_NOREF(iInstance);
4676
4677	/*
4678	* Initialize the state sufficently to make the destructor work.
4679	*/
4680	pThis->uAlignmentCheckMagic = HDASTATE_ALIGNMENT_CHECK_MAGIC;
4681	RTListInit(&pThis->lstDrv);
4682	/** @todo r=bird: There are probably other things which should be
4683	* initialized here before we start failing. */
4684
4685	/*
4686	* Validate and read configuration.
4687	*/
4688	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "TimerHz\|PosAdjustEnabled\|PosAdjustFrames\|DebugEnabled\|DebugPathOut", "");
4689
4690	int rc = pHlp->pfnCFGMQueryU16Def(pCfg, "TimerHz", &pThis->uTimerHz, HDA_TIMER_HZ_DEFAULT /* Default value, if not set. */);
4691	if (RT_FAILURE(rc))
4692	return PDMDEV_SET_ERROR(pDevIns, rc,
4693	N_("HDA configuration error: failed to read Hertz (Hz) rate as unsigned integer"));
4694
4695	if (pThis->uTimerHz != HDA_TIMER_HZ_DEFAULT)
4696	LogRel(("HDA: Using custom device timer rate (%RU16Hz)\n", pThis->uTimerHz));
4697
4698	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "PosAdjustEnabled", &pThis->fPosAdjustEnabled, true);
4699	if (RT_FAILURE(rc))
4700	return PDMDEV_SET_ERROR(pDevIns, rc,
4701	N_("HDA configuration error: failed to read position adjustment enabled as boolean"));
4702
4703	if (!pThis->fPosAdjustEnabled)
4704	LogRel(("HDA: Position adjustment is disabled\n"));
4705
4706	rc = pHlp->pfnCFGMQueryU16Def(pCfg, "PosAdjustFrames", &pThis->cPosAdjustFrames, HDA_POS_ADJUST_DEFAULT);
4707	if (RT_FAILURE(rc))
4708	return PDMDEV_SET_ERROR(pDevIns, rc,
4709	N_("HDA configuration error: failed to read position adjustment frames as unsigned integer"));
4710
4711	if (pThis->cPosAdjustFrames)
4712	LogRel(("HDA: Using custom position adjustment (%RU16 audio frames)\n", pThis->cPosAdjustFrames));
4713
4714	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "DebugEnabled", &pThis->Dbg.fEnabled, false);
4715	if (RT_FAILURE(rc))
4716	return PDMDEV_SET_ERROR(pDevIns, rc,
4717	N_("HDA configuration error: failed to read debugging enabled flag as boolean"));
4718
4719	rc = pHlp->pfnCFGMQueryStringDef(pCfg, "DebugPathOut", pThis->Dbg.szOutPath, sizeof(pThis->Dbg.szOutPath),
4720	VBOX_AUDIO_DEBUG_DUMP_PCM_DATA_PATH);
4721	if (RT_FAILURE(rc))
4722	return PDMDEV_SET_ERROR(pDevIns, rc,
4723	N_("HDA configuration error: failed to read debugging output path flag as string"));
4724
4725	if (pThis->Dbg.fEnabled)
4726	LogRel2(("HDA: Debug output will be saved to '%s'\n", pThis->Dbg.szOutPath));
4727
4728	/*
4729	* Use our own critical section for the device instead of the default
4730	* one provided by PDM. This allows fine-grained locking in combination
4731	* with TM when timer-specific stuff is being called in e.g. the MMIO handlers.
4732	*/
4733	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "HDA");
4734	AssertRCReturn(rc, rc);
4735
4736	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4737	AssertRCReturn(rc, rc);
4738
4739	/*
4740	* Initialize data (most of it anyway).
4741	*/
4742	pThis->pDevInsR3 = pDevIns;
4743	/* IBase */
4744	pThis->IBase.pfnQueryInterface = hdaR3QueryInterface;
4745
4746	/* PCI Device */
4747	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4748	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4749
4750	PDMPciDevSetVendorId( pPciDev, HDA_PCI_VENDOR_ID); /* nVidia */
4751	PDMPciDevSetDeviceId( pPciDev, HDA_PCI_DEVICE_ID); /* HDA */
4752
4753	PDMPciDevSetCommand( pPciDev, 0x0000); /* 04 rw,ro - pcicmd. */
4754	PDMPciDevSetStatus( pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
4755	PDMPciDevSetRevisionId( pPciDev, 0x01); /* 08 ro - rid. */
4756	PDMPciDevSetClassProg( pPciDev, 0x00); /* 09 ro - pi. */
4757	PDMPciDevSetClassSub( pPciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
4758	PDMPciDevSetClassBase( pPciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
4759	PDMPciDevSetHeaderType( pPciDev, 0x00); /* 0e ro - headtyp. */
4760	PDMPciDevSetBaseAddress( pPciDev, 0, /* 10 rw - MMIO */
4761	false /* fIoSpace /, false / fPrefetchable /, true / f64Bit */, 0x00000000);
4762	PDMPciDevSetInterruptLine( pPciDev, 0x00); /* 3c rw. */
4763	PDMPciDevSetInterruptPin( pPciDev, 0x01); /* 3d ro - INTA#. */
4764
4765	#if defined(HDA_AS_PCI_EXPRESS)
4766	PDMPciDevSetCapabilityList(pPciDev, 0x80);
4767	#elif defined(VBOX_WITH_MSI_DEVICES)
4768	PDMPciDevSetCapabilityList(pPciDev, 0x60);
4769	#else
4770	PDMPciDevSetCapabilityList(pPciDev, 0x50); /* ICH6 datasheet 18.1.16 */
4771	#endif
4772
4773	/// @todo r=michaln: If there are really no PDMPciDevSetXx for these, the
4774	/// meaning of these values needs to be properly documented!
4775	/* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
4776	PDMPciDevSetByte( pPciDev, 0x40, 0x01);
4777
4778	/* Power Management */
4779	PDMPciDevSetByte( pPciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
4780	PDMPciDevSetByte( pPciDev, 0x50 + 1, 0x0); /* next */
4781	PDMPciDevSetWord( pPciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI \| 0x02 /* version, PM1.1 */ );
4782
4783	#ifdef HDA_AS_PCI_EXPRESS
4784	/* PCI Express */
4785	PDMPciDevSetByte( pPciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
4786	PDMPciDevSetByte( pPciDev, 0x80 + 1, 0x60); /* next */
4787	/* Device flags */
4788	PDMPciDevSetWord( pPciDev, 0x80 + 2,
4789	1 /* version */
4790	\| (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) /* Root Complex Integrated Endpoint */
4791	\| (100 << 9) /* MSI */ );
4792	/* Device capabilities */
4793	PDMPciDevSetDWord( pPciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
4794	/* Device control */
4795	PDMPciDevSetWord( pPciDev, 0x80 + 8, 0);
4796	/* Device status */
4797	PDMPciDevSetWord( pPciDev, 0x80 + 10, 0);
4798	/* Link caps */
4799	PDMPciDevSetDWord( pPciDev, 0x80 + 12, 0);
4800	/* Link control */
4801	PDMPciDevSetWord( pPciDev, 0x80 + 16, 0);
4802	/* Link status */
4803	PDMPciDevSetWord( pPciDev, 0x80 + 18, 0);
4804	/* Slot capabilities */
4805	PDMPciDevSetDWord( pPciDev, 0x80 + 20, 0);
4806	/* Slot control */
4807	PDMPciDevSetWord( pPciDev, 0x80 + 24, 0);
4808	/* Slot status */
4809	PDMPciDevSetWord( pPciDev, 0x80 + 26, 0);
4810	/* Root control */
4811	PDMPciDevSetWord( pPciDev, 0x80 + 28, 0);
4812	/* Root capabilities */
4813	PDMPciDevSetWord( pPciDev, 0x80 + 30, 0);
4814	/* Root status */
4815	PDMPciDevSetDWord( pPciDev, 0x80 + 32, 0);
4816	/* Device capabilities 2 */
4817	PDMPciDevSetDWord( pPciDev, 0x80 + 36, 0);
4818	/* Device control 2 */
4819	PDMPciDevSetQWord( pPciDev, 0x80 + 40, 0);
4820	/* Link control 2 */
4821	PDMPciDevSetQWord( pPciDev, 0x80 + 48, 0);
4822	/* Slot control 2 */
4823	PDMPciDevSetWord( pPciDev, 0x80 + 56, 0);
4824	#endif
4825
4826	/*
4827	* Register the PCI device.
4828	*/
4829	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4830	AssertRCReturn(rc, rc);
4831
4832	rc = PDMDevHlpPCIIORegionCreateMmio(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaMMIOWrite, hdaMMIORead, NULL /pvUser/,
4833	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_PASSTHRU, "HDA", &pThis->hMmio);
4834	AssertRCReturn(rc, rc);
4835
4836	#ifdef VBOX_WITH_MSI_DEVICES
4837	PDMMSIREG MsiReg;
4838	RT_ZERO(MsiReg);
4839	MsiReg.cMsiVectors = 1;
4840	MsiReg.iMsiCapOffset = 0x60;
4841	MsiReg.iMsiNextOffset = 0x50;
4842	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
4843	if (RT_FAILURE(rc))
4844	{
4845	/* That's OK, we can work without MSI */
4846	PDMPciDevSetCapabilityList(pPciDev, 0x50);
4847	}
4848	#endif
4849
4850	rc = PDMDevHlpSSMRegister(pDevIns, HDA_SAVED_STATE_VERSION, sizeof(*pThis), hdaR3SaveExec, hdaR3LoadExec);
4851	AssertRCReturn(rc, rc);
4852
4853	#ifdef VBOX_WITH_AUDIO_HDA_ASYNC_IO
4854	LogRel(("HDA: Asynchronous I/O enabled\n"));
4855	#endif
4856
4857	/*
4858	* Attach drivers. We ASSUME they are configured consecutively without any
4859	* gaps, so we stop when we hit the first LUN w/o a driver configured.
4860	*/
4861	for (unsigned iLun = 0; ; iLun++)
4862	{
4863	AssertBreak(iLun < UINT8_MAX);
4864	LogFunc(("Trying to attach driver for LUN#%u ...\n", iLun));
4865	rc = hdaR3AttachInternal(pThis, iLun, 0 /* fFlags /, NULL / ppDrv */);
4866	if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4867	{
4868	LogFunc(("cLUNs=%u\n", iLun));
4869	break;
4870	}
4871	if (rc == VERR_AUDIO_BACKEND_INIT_FAILED)
4872	{
4873	hdaR3ReconfigLunWithNullAudio(pThis, iLun); /* Pretend attaching to the NULL audio backend will never fail. */
4874	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
4875	N_("Host audio backend initialization has failed. Selecting the NULL audio backend with the consequence that no sound is audible"));
4876	}
4877	else
4878	AssertLogRelMsgReturn(RT_SUCCESS(rc), ("LUN#%u: rc=%Rrc\n", iLun, rc), rc);
4879	}
4880
4881	/*
4882	* Create the mixer.
4883	*/
4884	rc = AudioMixerCreate("HDA Mixer", 0 /* uFlags */, &pThis->pMixer);
4885	AssertRCReturn(rc, rc);
4886
4887	/*
4888	* Add mixer output sinks.
4889	*/
4890	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
4891	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Front", AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
4892	AssertRCReturn(rc, rc);
4893	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Center / Subwoofer", AUDMIXSINKDIR_OUTPUT, &pThis->SinkCenterLFE.pMixSink);
4894	AssertRCReturn(rc, rc);
4895	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] Rear", AUDMIXSINKDIR_OUTPUT, &pThis->SinkRear.pMixSink);
4896	AssertRCReturn(rc, rc);
4897	#else
4898	rc = AudioMixerCreateSink(pThis->pMixer, "[Playback] PCM Output", AUDMIXSINKDIR_OUTPUT, &pThis->SinkFront.pMixSink);
4899	AssertRCReturn(rc, rc);
4900	#endif
4901
4902	/*
4903	* Add mixer input sinks.
4904	*/
4905	rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Line In", AUDMIXSINKDIR_INPUT, &pThis->SinkLineIn.pMixSink);
4906	AssertRCReturn(rc, rc);
4907	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
4908	rc = AudioMixerCreateSink(pThis->pMixer, "[Recording] Microphone In", AUDMIXSINKDIR_INPUT, &pThis->SinkMicIn.pMixSink);
4909	AssertRCReturn(rc, rc);
4910	#endif
4911
4912	/* There is no master volume control. Set the master to max. */
4913	PDMAUDIOVOLUME vol = { false, 255, 255 };
4914	rc = AudioMixerSetMasterVolume(pThis->pMixer, &vol);
4915	AssertRCReturn(rc, rc);
4916
4917	/* Allocate CORB buffer. */
4918	pThis->cbCorbBuf = HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE;
4919	pThis->pu32CorbBuf = (uint32_t *)RTMemAllocZ(pThis->cbCorbBuf);
4920	AssertReturn(pThis->pu32CorbBuf, VERR_NO_MEMORY);
4921
4922	/* Allocate RIRB buffer. */
4923	pThis->cbRirbBuf = HDA_RIRB_SIZE * HDA_RIRB_ELEMENT_SIZE;
4924	pThis->pu64RirbBuf = (uint64_t *)RTMemAllocZ(pThis->cbRirbBuf);
4925	AssertReturn(pThis->pu64RirbBuf, VERR_NO_MEMORY);
4926
4927	/* Allocate codec. */
4928	pThis->pCodec = (PHDACODEC)RTMemAllocZ(sizeof(HDACODEC));
4929	AssertReturn(pThis->pCodec, VERR_NO_MEMORY);
4930
4931	/* Set codec callbacks to this controller. */
4932	pThis->pCodec->pfnCbMixerAddStream = hdaR3MixerAddStream;
4933	pThis->pCodec->pfnCbMixerRemoveStream = hdaR3MixerRemoveStream;
4934	pThis->pCodec->pfnCbMixerControl = hdaR3MixerControl;
4935	pThis->pCodec->pfnCbMixerSetVolume = hdaR3MixerSetVolume;
4936
4937	pThis->pCodec->pHDAState = pThis; /* Assign HDA controller state to codec. */
4938
4939	/* Construct the codec. */
4940	rc = hdaCodecConstruct(pDevIns, pThis->pCodec, 0 /* Codec index */, pCfg);
4941	AssertRCReturn(rc, rc);
4942
4943	/* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
4944	verb F20 should provide device/codec recognition. */
4945	Assert(pThis->pCodec->u16VendorId);
4946	Assert(pThis->pCodec->u16DeviceId);
4947	PDMPciDevSetSubSystemVendorId(pPciDev, pThis->pCodec->u16VendorId); /* 2c ro - intel.) */
4948	PDMPciDevSetSubSystemId( pPciDev, pThis->pCodec->u16DeviceId); /* 2e ro. */
4949
4950	/*
4951	* Create the per stream timers and the asso.
4952	*
4953	* We must the critical section for the timers as the device has a
4954	* noop section associated with it.
4955	*
4956	* Note: Use TMCLOCK_VIRTUAL_SYNC here, as the guest's HDA driver relies
4957	* on exact (virtual) DMA timing and uses DMA Position Buffers
4958	* instead of the LPIB registers.
4959	*/
4960	static const char * const s_apszNames[] =
4961	{
4962	"HDA SD0", "HDA SD1", "HDA SD2", "HDA SD3",
4963	"HDA SD4", "HDA SD5", "HDA SD6", "HDA SD7",
4964	};
4965	AssertCompile(RT_ELEMENTS(s_apszNames) == HDA_MAX_STREAMS);
4966	for (size_t i = 0; i < HDA_MAX_STREAMS; i++)
4967	{
4968	rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, hdaR3Timer, &pThis->aStreams[i],
4969	TMTIMER_FLAGS_NO_CRIT_SECT, s_apszNames[i], &pThis->aStreams[i].hTimer);
4970	AssertRCReturn(rc, rc);
4971
4972	rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->aStreams[i].hTimer, &pThis->CritSect);
4973	AssertRCReturn(rc, rc);
4974	}
4975
4976	/*
4977	* Create all hardware streams.
4978	*/
4979	for (uint8_t i = 0; i < HDA_MAX_STREAMS; ++i)
4980	{
4981	rc = hdaR3StreamCreate(&pThis->aStreams[i], pThis, i /* u8SD */);
4982	AssertRCReturn(rc, rc);
4983	}
4984
4985	#ifdef VBOX_WITH_AUDIO_HDA_ONETIME_INIT
4986	/*
4987	* Initialize the driver chain.
4988	*/
4989	PHDADRIVER pDrv;
4990	RTListForEach(&pThis->lstDrv, pDrv, HDADRIVER, Node)
4991	{
4992	/*
4993	* Only primary drivers are critical for the VM to run. Everything else
4994	* might not worth showing an own error message box in the GUI.
4995	*/
4996	if (!(pDrv->fFlags & PDMAUDIODRVFLAGS_PRIMARY))
4997	continue;
4998
4999	PPDMIAUDIOCONNECTOR pCon = pDrv->pConnector;
5000	AssertPtr(pCon);
5001
5002	bool fValidLineIn = AudioMixerStreamIsValid(pDrv->LineIn.pMixStrm);
5003	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5004	bool fValidMicIn = AudioMixerStreamIsValid(pDrv->MicIn.pMixStrm);
5005	# endif
5006	bool fValidOut = AudioMixerStreamIsValid(pDrv->Front.pMixStrm);
5007	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
5008	/** @todo Anything to do here? */
5009	# endif
5010
5011	if ( !fValidLineIn
5012	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5013	&& !fValidMicIn
5014	# endif
5015	&& !fValidOut)
5016	{
5017	LogRel(("HDA: Falling back to NULL backend (no sound audible)\n"));
5018	hdaR3Reset(pDevIns);
5019	hdaR3ReconfigLunWithNullAudio(pThis, pDrv->uLUN);
5020	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
5021	N_("No audio devices could be opened. "
5022	"Selecting the NULL audio backend with the consequence that no sound is audible"));
5023	}
5024	else
5025	{
5026	bool fWarn = false;
5027
5028	PDMAUDIOBACKENDCFG BackendCfg;
5029	int rc2 = pCon->pfnGetConfig(pCon, &BackendCfg);
5030	if (RT_SUCCESS(rc2))
5031	{
5032	if (BackendCfg.cMaxStreamsIn)
5033	{
5034	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5035	/* If the audio backend supports two or more input streams at once,
5036	* warn if one of our two inputs (microphone-in and line-in) failed to initialize. */
5037	if (BackendCfg.cMaxStreamsIn >= 2)
5038	fWarn = !fValidLineIn \|\| !fValidMicIn;
5039	/* If the audio backend only supports one input stream at once (e.g. pure ALSA, and
5040	* not ALSA via PulseAudio plugin!), only warn if both of our inputs failed to initialize.
5041	* One of the two simply is not in use then. */
5042	else if (BackendCfg.cMaxStreamsIn == 1)
5043	fWarn = !fValidLineIn && !fValidMicIn;
5044	/* Don't warn if our backend is not able of supporting any input streams at all. */
5045	# else /* !VBOX_WITH_AUDIO_HDA_MIC_IN */
5046	/* We only have line-in as input source. */
5047	fWarn = !fValidLineIn;
5048	# endif /* !VBOX_WITH_AUDIO_HDA_MIC_IN */
5049	}
5050
5051	if ( !fWarn
5052	&& BackendCfg.cMaxStreamsOut)
5053	fWarn = !fValidOut;
5054	}
5055	else
5056	{
5057	LogRel(("HDA: Unable to retrieve audio backend configuration for LUN #%RU8, rc=%Rrc\n", pDrv->uLUN, rc2));
5058	fWarn = true;
5059	}
5060
5061	if (fWarn)
5062	{
5063	char szMissingStreams[255];
5064	size_t len = 0;
5065	if (!fValidLineIn)
5066	{
5067	LogRel(("HDA: WARNING: Unable to open PCM line input for LUN #%RU8!\n", pDrv->uLUN));
5068	len = RTStrPrintf(szMissingStreams, sizeof(szMissingStreams), "PCM Input");
5069	}
5070	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5071	if (!fValidMicIn)
5072	{
5073	LogRel(("HDA: WARNING: Unable to open PCM microphone input for LUN #%RU8!\n", pDrv->uLUN));
5074	len += RTStrPrintf(szMissingStreams + len,
5075	sizeof(szMissingStreams) - len, len ? ", PCM Microphone" : "PCM Microphone");
5076	}
5077	# endif
5078	if (!fValidOut)
5079	{
5080	LogRel(("HDA: WARNING: Unable to open PCM output for LUN #%RU8!\n", pDrv->uLUN));
5081	len += RTStrPrintf(szMissingStreams + len,
5082	sizeof(szMissingStreams) - len, len ? ", PCM Output" : "PCM Output");
5083	}
5084
5085	PDMDevHlpVMSetRuntimeError(pDevIns, 0 /fFlags/, "HostAudioNotResponding",
5086	N_("Some HDA audio streams (%s) could not be opened. "
5087	"Guest applications generating audio output or depending on audio input may hang. "
5088	"Make sure your host audio device is working properly. "
5089	"Check the logfile for error messages of the audio subsystem"), szMissingStreams);
5090	}
5091	}
5092	}
5093	#endif /* VBOX_WITH_AUDIO_HDA_ONETIME_INIT */
5094
5095	hdaR3Reset(pDevIns);
5096
5097	/*
5098	* Info items and string formatter types. The latter is non-optional as
5099	* the info handles use (at least some of) the custom types and we cannot
5100	* accept screwing formatting.
5101	*/
5102	PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA info. (hda [register case-insensitive])", hdaR3DbgInfo);
5103	PDMDevHlpDBGFInfoRegister(pDevIns, "hdabdle", "HDA stream BDLE info. (hdabdle [stream number])", hdaR3DbgInfoBDLE);
5104	PDMDevHlpDBGFInfoRegister(pDevIns, "hdastream", "HDA stream info. (hdastream [stream number])", hdaR3DbgInfoStream);
5105	PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaR3DbgInfoCodecNodes);
5106	PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaR3DbgInfoCodecSelector);
5107	PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaR3DbgInfoMixer);
5108
5109	rc = RTStrFormatTypeRegister("bdle", hdaR3StrFmtBDLE, NULL);
5110	AssertMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_ALREADY_EXISTS, ("%Rrc\n", rc), rc);
5111	rc = RTStrFormatTypeRegister("sdctl", hdaR3StrFmtSDCTL, NULL);
5112	AssertMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_ALREADY_EXISTS, ("%Rrc\n", rc), rc);
5113	rc = RTStrFormatTypeRegister("sdsts", hdaR3StrFmtSDSTS, NULL);
5114	AssertMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_ALREADY_EXISTS, ("%Rrc\n", rc), rc);
5115	rc = RTStrFormatTypeRegister("sdfifos", hdaR3StrFmtSDFIFOS, NULL);
5116	AssertMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_ALREADY_EXISTS, ("%Rrc\n", rc), rc);
5117	rc = RTStrFormatTypeRegister("sdfifow", hdaR3StrFmtSDFIFOW, NULL);
5118	AssertMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_ALREADY_EXISTS, ("%Rrc\n", rc), rc);
5119
5120	/*
5121	* Asserting sanity.
5122	*/
5123	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
5124	{
5125	struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
5126	struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
5127
5128	/* binary search order. */
5129	AssertReleaseMsg(!pNextReg \|\| pReg->offset + pReg->size <= pNextReg->offset,
5130	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5131	i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
5132
5133	/* alignment. */
5134	AssertReleaseMsg( pReg->size == 1
5135	\|\| (pReg->size == 2 && (pReg->offset & 1) == 0)
5136	\|\| (pReg->size == 3 && (pReg->offset & 3) == 0)
5137	\|\| (pReg->size == 4 && (pReg->offset & 3) == 0),
5138	("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5139
5140	/* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
5141	AssertRelease(((pReg->offset + pReg->size) & 3) == 0 \|\| pNextReg);
5142	if (pReg->offset & 3)
5143	{
5144	struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
5145	AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5146	if (pPrevReg)
5147	AssertReleaseMsg(pPrevReg->offset + pPrevReg->size == pReg->offset,
5148	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5149	i - 1, pPrevReg->offset, pPrevReg->size, i + 1, pReg->offset, pReg->size));
5150	}
5151	#if 0
5152	if ((pReg->offset + pReg->size) & 3)
5153	{
5154	AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5155	if (pNextReg)
5156	AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
5157	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5158	i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
5159	}
5160	#endif
5161	/* The final entry is a full DWORD, no gaps! Allows shortcuts. */
5162	AssertReleaseMsg(pNextReg \|\| ((pReg->offset + pReg->size) & 3) == 0,
5163	("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5164	}
5165
5166	# ifdef VBOX_WITH_STATISTICS
5167	/*
5168	* Register statistics.
5169	*/
5170	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatTimer, STAMTYPE_PROFILE, "/Devices/HDA/Timer", STAMUNIT_TICKS_PER_CALL, "Profiling hdaR3Timer.");
5171	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIn, STAMTYPE_PROFILE, "/Devices/HDA/Input", STAMUNIT_TICKS_PER_CALL, "Profiling input.");
5172	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatOut, STAMTYPE_PROFILE, "/Devices/HDA/Output", STAMUNIT_TICKS_PER_CALL, "Profiling output.");
5173	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "/Devices/HDA/BytesRead" , STAMUNIT_BYTES, "Bytes read from HDA emulation.");
5174	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "/Devices/HDA/BytesWritten", STAMUNIT_BYTES, "Bytes written to HDA emulation.");
5175	# endif
5176
5177	return VINF_SUCCESS;
5178	}
5179
5180	#else /* !IN_RING3 */
5181
5182	/**
5183	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
5184	*/
5185	static DECLCALLBACK(int) hdaRZConstruct(PPDMDEVINS pDevIns)
5186	{
5187	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); /* this shall come first */
5188	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
5189
5190	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
5191	AssertRCReturn(rc, rc);
5192
5193	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, hdaMMIOWrite, hdaMMIORead, NULL /pvUser/);
5194	AssertRCReturn(rc, rc);
5195
5196	return VINF_SUCCESS;
5197	}
5198
5199	#endif /* !IN_RING3 */
5200
5201	/**
5202	* The device registration structure.
5203	*/
5204	const PDMDEVREG g_DeviceHDA =
5205	{
5206	/* .u32Version = */ PDM_DEVREG_VERSION,
5207	/* .uReserved0 = */ 0,
5208	/* .szName = */ "hda",
5209	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ,
5210	/* .fClass = */ PDM_DEVREG_CLASS_AUDIO,
5211	/* .cMaxInstances = */ 1,
5212	/* .uSharedVersion = */ 42,
5213	/* .cbInstanceShared = */ sizeof(HDASTATE),
5214	/* .cbInstanceCC = */ 0,
5215	/* .cbInstanceRC = */ 0,
5216	/* .cMaxPciDevices = */ 1,
5217	/* .cMaxMsixVectors = */ 0,
5218	/* .pszDescription = */ "Intel HD Audio Controller",
5219	#if defined(IN_RING3)
5220	/* .pszRCMod = */ "VBoxDDRC.rc",
5221	/* .pszR0Mod = */ "VBoxDDR0.r0",
5222	/* .pfnConstruct = */ hdaR3Construct,
5223	/* .pfnDestruct = */ hdaR3Destruct,
5224	/* .pfnRelocate = */ NULL,
5225	/* .pfnMemSetup = */ NULL,
5226	/* .pfnPowerOn = */ NULL,
5227	/* .pfnReset = */ hdaR3Reset,
5228	/* .pfnSuspend = */ NULL,
5229	/* .pfnResume = */ NULL,
5230	/* .pfnAttach = */ hdaR3Attach,
5231	/* .pfnDetach = */ hdaR3Detach,
5232	/* .pfnQueryInterface = */ NULL,
5233	/* .pfnInitComplete = */ NULL,
5234	/* .pfnPowerOff = */ hdaR3PowerOff,
5235	/* .pfnSoftReset = */ NULL,
5236	/* .pfnReserved0 = */ NULL,
5237	/* .pfnReserved1 = */ NULL,
5238	/* .pfnReserved2 = */ NULL,
5239	/* .pfnReserved3 = */ NULL,
5240	/* .pfnReserved4 = */ NULL,
5241	/* .pfnReserved5 = */ NULL,
5242	/* .pfnReserved6 = */ NULL,
5243	/* .pfnReserved7 = */ NULL,
5244	#elif defined(IN_RING0)
5245	/* .pfnEarlyConstruct = */ NULL,
5246	/* .pfnConstruct = */ hdaRZConstruct,
5247	/* .pfnDestruct = */ NULL,
5248	/* .pfnFinalDestruct = */ NULL,
5249	/* .pfnRequest = */ NULL,
5250	/* .pfnReserved0 = */ NULL,
5251	/* .pfnReserved1 = */ NULL,
5252	/* .pfnReserved2 = */ NULL,
5253	/* .pfnReserved3 = */ NULL,
5254	/* .pfnReserved4 = */ NULL,
5255	/* .pfnReserved5 = */ NULL,
5256	/* .pfnReserved6 = */ NULL,
5257	/* .pfnReserved7 = */ NULL,
5258	#elif defined(IN_RC)
5259	/* .pfnConstruct = */ hdaRZConstruct,
5260	/* .pfnReserved0 = */ NULL,
5261	/* .pfnReserved1 = */ NULL,
5262	/* .pfnReserved2 = */ NULL,
5263	/* .pfnReserved3 = */ NULL,
5264	/* .pfnReserved4 = */ NULL,
5265	/* .pfnReserved5 = */ NULL,
5266	/* .pfnReserved6 = */ NULL,
5267	/* .pfnReserved7 = */ NULL,
5268	#else
5269	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
5270	#endif
5271	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
5272	};
5273
5274	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5275

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source: vbox/trunk/src/VBox/Devices/Audio/DevHDA.cpp@ 82362

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