VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevHDA.h@ 88163

Last change on this file since 88163 was 88063, checked in by vboxsync, 4 years ago

DevHDA: Tweaked the AIO output scheduling a little, ignoring uTimerHz and instead using a new initial delay parameter (default to 12 ms). The AIO thread is always woken up after the delay (actually, that's been the case since r143099 (trunk) / r143109 (6.1)). bugref:9890

  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 10.0 KB
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1/* $Id: DevHDA.h 88063 2021-03-09 21:48:07Z vboxsync $ */
2/** @file
3 * DevHDA.h - VBox Intel HD Audio Controller.
4 */
5
6/*
7 * Copyright (C) 2016-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VBOX_INCLUDED_SRC_Audio_DevHDA_h
19#define VBOX_INCLUDED_SRC_Audio_DevHDA_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <iprt/path.h>
25
26#include <VBox/vmm/pdmdev.h>
27
28#include "AudioMixer.h"
29
30#include "HDACodec.h"
31#include "HDAStream.h"
32#include "HDAStreamMap.h"
33#include "HDAStreamPeriod.h"
34
35#ifdef DEBUG_andy
36/** Enables strict mode, which checks for stuff which isn't supposed to happen.
37 * Be prepared for assertions coming in! */
38//# define HDA_STRICT
39#endif
40
41/**
42 * HDA mixer sink definition (ring-3).
43 *
44 * Its purpose is to know which audio mixer sink is bound to which SDn
45 * (SDI/SDO) device stream.
46 *
47 * This is needed in order to handle interleaved streams (that is, multiple
48 * channels in one stream) or non-interleaved streams (each channel has a
49 * dedicated stream).
50 *
51 * This is only known to the actual device emulation level.
52 */
53typedef struct HDAMIXERSINK
54{
55 R3PTRTYPE(PHDASTREAM) pStreamShared;
56 R3PTRTYPE(PHDASTREAMR3) pStreamR3;
57 /** Pointer to the actual audio mixer sink. */
58 R3PTRTYPE(PAUDMIXSINK) pMixSink;
59} HDAMIXERSINK;
60/** Pointer to an HDA mixer sink definition (ring-3). */
61typedef HDAMIXERSINK *PHDAMIXERSINK;
62
63/**
64 * Mapping a stream tag to an HDA stream (ring-3).
65 */
66typedef struct HDATAG
67{
68 /** Own stream tag. */
69 uint8_t uTag;
70 uint8_t Padding[7];
71 /** Pointer to associated stream. */
72 R3PTRTYPE(PHDASTREAMR3) pStreamR3;
73} HDATAG;
74/** Pointer to a HDA stream tag mapping. */
75typedef HDATAG *PHDATAG;
76
77/**
78 * Shared ICH Intel HD audio controller state.
79 */
80typedef struct HDASTATE
81{
82 /** Critical section protecting the HDA state. */
83 PDMCRITSECT CritSect;
84 /** The HDA's register set. */
85 uint32_t au32Regs[HDA_NUM_REGS];
86 /** Internal stream states. */
87 HDASTREAM aStreams[HDA_MAX_STREAMS];
88 /** CORB buffer base address. */
89 uint64_t u64CORBBase;
90 /** RIRB buffer base address. */
91 uint64_t u64RIRBBase;
92 /** DMA base address.
93 * Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
94 uint64_t u64DPBase;
95 /** Size in bytes of CORB buffer (#au32CorbBuf). */
96 uint32_t cbCorbBuf;
97 /** Size in bytes of RIRB buffer (#au64RirbBuf). */
98 uint32_t cbRirbBuf;
99 /** Response Interrupt Count (RINTCNT). */
100 uint16_t u16RespIntCnt;
101 /** Position adjustment (in audio frames).
102 *
103 * This is not an official feature of the HDA specs, but used by
104 * certain OS drivers (e.g. snd_hda_intel) to work around certain
105 * quirks by "real" HDA hardware implementations.
106 *
107 * The position adjustment specifies how many audio frames
108 * a stream is ahead from its actual reading/writing position when
109 * starting a stream.
110 */
111 uint16_t cPosAdjustFrames;
112 /** Whether the position adjustment is enabled or not. */
113 bool fPosAdjustEnabled;
114 /** Whether data transfer heuristics are enabled or not.
115 * This tries to determine the approx. data rate a guest audio driver expects. */
116 bool fTransferHeuristicsEnabled;
117 /** DMA position buffer enable bit. */
118 bool fDMAPosition;
119 /** Current IRQ level. */
120 uint8_t u8IRQL;
121#ifdef VBOX_STRICT
122 /** Wall clock (WALCLK) stale count.
123 * This indicates the number of set wall clock values which did not actually
124 * move the counter forward (stale). */
125 uint8_t u8WalClkStaleCnt;
126#else
127 uint8_t bPadding1;
128#endif
129 uint8_t bPadding2;
130 /** The device timer Hz rate. Defaults to HDA_TIMER_HZ_DEFAULT. */
131 uint16_t uTimerHz;
132 /** Number of milliseconds to delay kicking off the AIO when a stream starts.
133 * @sa InitialDelayMs config value. */
134 uint16_t msInitialDelay;
135 /** Buffer size (in ms) of the internal input FIFO buffer.
136 * The actual buffer size in bytes will depend on the actual stream configuration. */
137 uint16_t cbCircBufInMs;
138 /** Buffer size (in ms) of the internal output FIFO buffer.
139 * The actual buffer size in bytes will depend on the actual stream configuration. */
140 uint16_t cbCircBufOutMs;
141 uint16_t au16Padding3[3];
142 /** Last updated wall clock (WALCLK) counter. */
143 uint64_t u64WalClk;
144 /** The CORB buffer. */
145 uint32_t au32CorbBuf[HDA_CORB_SIZE];
146 /** Pointer to RIRB buffer. */
147 uint64_t au64RirbBuf[HDA_RIRB_SIZE];
148
149 /** PCI Region \#0: 16KB of MMIO stuff. */
150 IOMMMIOHANDLE hMmio;
151
152 /** Shared R0/R3 HDA codec to use. */
153 HDACODEC Codec;
154
155#ifdef VBOX_WITH_STATISTICS
156 STAMPROFILE StatIn;
157 STAMPROFILE StatOut;
158 STAMCOUNTER StatBytesRead;
159 STAMCOUNTER StatBytesWritten;
160
161 /** @name Register statistics.
162 * The array members run parallel to g_aHdaRegMap.
163 * @{ */
164 STAMCOUNTER aStatRegReads[HDA_NUM_REGS];
165 STAMCOUNTER aStatRegReadsToR3[HDA_NUM_REGS];
166 STAMCOUNTER aStatRegWrites[HDA_NUM_REGS];
167 STAMCOUNTER aStatRegWritesToR3[HDA_NUM_REGS];
168 STAMCOUNTER StatRegMultiReadsRZ;
169 STAMCOUNTER StatRegMultiReadsR3;
170 STAMCOUNTER StatRegMultiWritesRZ;
171 STAMCOUNTER StatRegMultiWritesR3;
172 STAMCOUNTER StatRegSubWriteRZ;
173 STAMCOUNTER StatRegSubWriteR3;
174 STAMCOUNTER StatRegUnknownReads;
175 STAMCOUNTER StatRegUnknownWrites;
176 STAMCOUNTER StatRegWritesBlockedByReset;
177 STAMCOUNTER StatRegWritesBlockedByRun;
178 /** @} */
179#endif
180
181#ifdef DEBUG
182 /** Debug stuff.
183 * @todo Make STAM values out some of this? */
184 struct
185 {
186# if 0 /* unused */
187 /** Timestamp (in ns) of the last timer callback (hdaTimer).
188 * Used to calculate the time actually elapsed between two timer callbacks. */
189 uint64_t tsTimerLastCalledNs;
190# endif
191 /** IRQ debugging information. */
192 struct
193 {
194 /** Timestamp (in ns) of last processed (asserted / deasserted) IRQ. */
195 uint64_t tsProcessedLastNs;
196 /** Timestamp (in ns) of last asserted IRQ. */
197 uint64_t tsAssertedNs;
198# if 0 /* unused */
199 /** How many IRQs have been asserted already. */
200 uint64_t cAsserted;
201 /** Accumulated elapsed time (in ns) of all IRQ being asserted. */
202 uint64_t tsAssertedTotalNs;
203 /** Timestamp (in ns) of last deasserted IRQ. */
204 uint64_t tsDeassertedNs;
205 /** How many IRQs have been deasserted already. */
206 uint64_t cDeasserted;
207 /** Accumulated elapsed time (in ns) of all IRQ being deasserted. */
208 uint64_t tsDeassertedTotalNs;
209# endif
210 } IRQ;
211 } Dbg;
212#endif
213 /** This is for checking that the build was correctly configured in all contexts.
214 * This is set to HDASTATE_ALIGNMENT_CHECK_MAGIC. */
215 uint64_t uAlignmentCheckMagic;
216} HDASTATE;
217/** Pointer to a shared HDA device state. */
218typedef HDASTATE *PHDASTATE;
219
220/** Value for HDASTATE:uAlignmentCheckMagic. */
221#define HDASTATE_ALIGNMENT_CHECK_MAGIC UINT64_C(0x1298afb75893e059)
222
223/**
224 * Ring-0 ICH Intel HD audio controller state.
225 */
226typedef struct HDASTATER0
227{
228 /** Pointer to HDA codec to use. */
229 HDACODECR0 Codec;
230} HDASTATER0;
231/** Pointer to a ring-0 HDA device state. */
232typedef HDASTATER0 *PHDASTATER0;
233
234/**
235 * Ring-3 ICH Intel HD audio controller state.
236 */
237typedef struct HDASTATER3
238{
239 /** Internal stream states. */
240 HDASTREAMR3 aStreams[HDA_MAX_STREAMS];
241 /** Mapping table between stream tags and stream states. */
242 HDATAG aTags[HDA_MAX_TAGS];
243 /** Number of active (running) SDn streams. */
244 uint8_t cStreamsActive;
245 uint8_t abPadding0[7];
246 /** R3 Pointer to the device instance. */
247 PPDMDEVINSR3 pDevIns;
248 /** The base interface for LUN\#0. */
249 PDMIBASE IBase;
250 /** Pointer to HDA codec to use. */
251 R3PTRTYPE(PHDACODECR3) pCodec;
252 /** List of associated LUN drivers (HDADRIVER). */
253 RTLISTANCHORR3 lstDrv;
254 /** The device' software mixer. */
255 R3PTRTYPE(PAUDIOMIXER) pMixer;
256 /** HDA sink for (front) output. */
257 HDAMIXERSINK SinkFront;
258#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
259 /** HDA sink for center / LFE output. */
260 HDAMIXERSINK SinkCenterLFE;
261 /** HDA sink for rear output. */
262 HDAMIXERSINK SinkRear;
263#endif
264 /** HDA mixer sink for line input. */
265 HDAMIXERSINK SinkLineIn;
266#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
267 /** Audio mixer sink for microphone input. */
268 HDAMIXERSINK SinkMicIn;
269#endif
270 /** Debug stuff. */
271 struct
272 {
273 /** Whether debugging is enabled or not. */
274 bool fEnabled;
275 /** Path where to dump the debug output to.
276 * Can be NULL, in which the system's temporary directory will be used then. */
277 R3PTRTYPE(char *) pszOutPath;
278 } Dbg;
279} HDASTATER3;
280/** Pointer to a ring-3 HDA device state. */
281typedef HDASTATER3 *PHDASTATER3;
282
283
284#endif /* !VBOX_INCLUDED_SRC_Audio_DevHDA_h */
285
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