| 1 | /* $Id: DevHDACommon.h 69119 2017-10-17 19:08:38Z vboxsync $ */
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| 2 | /** @file
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| 3 | * DevHDACommon.h - Shared HDA device defines / functions.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2016-2017 Oracle Corporation
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| 8 | *
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| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | * available from http://www.virtualbox.org. This file is free software;
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| 11 | * you can redistribute it and/or modify it under the terms of the GNU
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| 12 | * General Public License (GPL) as published by the Free Software
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| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | */
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| 17 |
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| 18 | #ifndef DEV_HDA_COMMON_H
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| 19 | #define DEV_HDA_COMMON_H
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| 20 |
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| 21 | #include "AudioMixer.h"
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| 22 |
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| 23 | /** See 302349 p 6.2. */
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| 24 | typedef struct HDAREGDESC
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| 25 | {
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| 26 | /** Register offset in the register space. */
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| 27 | uint32_t offset;
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| 28 | /** Size in bytes. Registers of size > 4 are in fact tables. */
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| 29 | uint32_t size;
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| 30 | /** Readable bits. */
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| 31 | uint32_t readable;
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| 32 | /** Writable bits. */
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| 33 | uint32_t writable;
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| 34 | /** Register descriptor (RD) flags of type HDA_RD_FLAG_.
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| 35 | * These are used to specify the handling (read/write)
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| 36 | * policy of the register. */
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| 37 | uint32_t fFlags;
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| 38 | /** Read callback. */
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| 39 | int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
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| 40 | /** Write callback. */
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| 41 | int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
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| 42 | /** Index into the register storage array. */
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| 43 | uint32_t mem_idx;
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| 44 | /** Abbreviated name. */
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| 45 | const char *abbrev;
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| 46 | /** Descripton. */
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| 47 | const char *desc;
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| 48 | } HDAREGDESC, *PHDAREGDESC;
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| 49 |
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| 50 | /**
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| 51 | * HDA register aliases (HDA spec 3.3.45).
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| 52 | * @remarks Sorted by offReg.
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| 53 | */
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| 54 | typedef struct HDAREGALIAS
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| 55 | {
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| 56 | /** The alias register offset. */
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| 57 | uint32_t offReg;
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| 58 | /** The register index. */
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| 59 | int idxAlias;
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| 60 | } HDAREGALIAS, *PHDAREGALIAS;
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| 61 |
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| 62 | /**
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| 63 | * At the moment we support 4 input + 4 output streams max, which is 8 in total.
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| 64 | * Bidirectional streams are currently *not* supported.
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| 65 | *
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| 66 | * Note: When changing any of those values, be prepared for some saved state
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| 67 | * fixups / trouble!
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| 68 | */
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| 69 | #define HDA_MAX_SDI 4
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| 70 | #define HDA_MAX_SDO 4
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| 71 | #define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
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| 72 | AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
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| 73 |
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| 74 | /** Number of general registers. */
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| 75 | #define HDA_NUM_GENERAL_REGS 34
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| 76 | /** Number of total registers in the HDA's register map. */
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| 77 | #define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */))
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| 78 | /** Total number of stream tags (channels). Index 0 is reserved / invalid. */
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| 79 | #define HDA_MAX_TAGS 16
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| 80 |
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| 81 | /**
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| 82 | * ICH6 datasheet defines limits for FIFOS registers (18.2.39).
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| 83 | * Formula: size - 1
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| 84 | * Other values not listed are not supported.
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| 85 | */
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| 86 | /** Maximum FIFO size (in bytes). */
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| 87 | #define HDA_FIFO_MAX 256
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| 88 |
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| 89 | /** Default timer frequency (in Hz).
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| 90 | *
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| 91 | * Note: Keep in mind that the Hz rate has nothing to do with samples rates
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| 92 | * or DMA / interrupt timing -- it's purely needed in order to drive
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| 93 | * the data flow at a constant (and sufficient) rate.
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| 94 | *
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| 95 | * Lowering this value can ask for trouble, as backends then can run
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| 96 | * into data underruns. */
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| 97 | #define HDA_TIMER_HZ 200
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| 98 |
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| 99 | /** HDA's (fixed) audio frame size in bytes.
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| 100 | * We only support 16-bit stereo frames at the moment. */
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| 101 | #define HDA_FRAME_SIZE 4
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| 102 |
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| 103 | /** Offset of the SD0 register map. */
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| 104 | #define HDA_REG_DESC_SD0_BASE 0x80
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| 105 |
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| 106 | /** Turn a short global register name into an memory index and a stringized name. */
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| 107 | #define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
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| 108 |
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| 109 | /** Turns a short stream register name into an memory index and a stringized name. */
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| 110 | #define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
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| 111 |
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| 112 | /** Same as above for a register *not* stored in memory. */
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| 113 | #define HDA_REG_IDX_NOMEM(abbrev) 0, #abbrev
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| 114 |
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| 115 | extern const HDAREGDESC g_aHdaRegMap[HDA_NUM_REGS];
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| 116 |
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| 117 | /**
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| 118 | * NB: Register values stored in memory (au32Regs[]) are indexed through
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| 119 | * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
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| 120 | * register descriptors in g_aHdaRegMap[] are indexed through the
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| 121 | * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
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| 122 | *
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| 123 | * The au32Regs[] layout is kept unchanged for saved state
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| 124 | * compatibility.
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| 125 | */
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| 126 |
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| 127 | /* Registers */
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| 128 | #define HDA_REG_IND_NAME(x) HDA_REG_##x
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| 129 | #define HDA_MEM_IND_NAME(x) HDA_RMX_##x
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| 130 | #define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
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| 131 | #define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
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| 132 |
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| 133 |
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| 134 | #define HDA_REG_GCAP 0 /* Range 0x00 - 0x01 */
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| 135 | #define HDA_RMX_GCAP 0
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| 136 | /**
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| 137 | * GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
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| 138 | *
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| 139 | * oss (15:12) - Number of output streams supported.
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| 140 | * iss (11:8) - Number of input streams supported.
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| 141 | * bss (7:3) - Number of bidirectional streams supported.
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| 142 | * bds (2:1) - Number of serial data out (SDO) signals supported.
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| 143 | * b64sup (0) - 64 bit addressing supported.
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| 144 | */
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| 145 | #define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
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| 146 | ( (((oss) & 0xF) << 12) \
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| 147 | | (((iss) & 0xF) << 8) \
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| 148 | | (((bss) & 0x1F) << 3) \
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| 149 | | (((bds) & 0x3) << 2) \
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| 150 | | ((b64sup) & 1))
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| 151 |
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| 152 | #define HDA_REG_VMIN 1 /* 0x02 */
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| 153 | #define HDA_RMX_VMIN 1
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| 154 |
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| 155 | #define HDA_REG_VMAJ 2 /* 0x03 */
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| 156 | #define HDA_RMX_VMAJ 2
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| 157 |
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| 158 | #define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
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| 159 | #define HDA_RMX_OUTPAY 3
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| 160 |
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| 161 | #define HDA_REG_INPAY 4 /* 0x06-0x07 */
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| 162 | #define HDA_RMX_INPAY 4
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| 163 |
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| 164 | #define HDA_REG_GCTL 5 /* 0x08-0x0B */
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| 165 | #define HDA_RMX_GCTL 5
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| 166 | #define HDA_GCTL_UNSOL RT_BIT(8) /* Accept Unsolicited Response Enable */
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| 167 | #define HDA_GCTL_FCNTRL RT_BIT(1) /* Flush Control */
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| 168 | #define HDA_GCTL_CRST RT_BIT(0) /* Controller Reset */
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| 169 |
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| 170 | #define HDA_REG_WAKEEN 6 /* 0x0C */
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| 171 | #define HDA_RMX_WAKEEN 6
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| 172 |
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| 173 | #define HDA_REG_STATESTS 7 /* 0x0E */
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| 174 | #define HDA_RMX_STATESTS 7
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| 175 | #define HDA_STATESTS_SCSF_MASK 0x7 /* State Change Status Flags (6.2.8). */
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| 176 |
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| 177 | #define HDA_REG_GSTS 8 /* 0x10-0x11*/
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| 178 | #define HDA_RMX_GSTS 8
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| 179 | #define HDA_GSTS_FSTS RT_BIT(1) /* Flush Status */
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| 180 |
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| 181 | #define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
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| 182 | #define HDA_RMX_OUTSTRMPAY 112
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| 183 |
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| 184 | #define HDA_REG_INSTRMPAY 10 /* 0x1a */
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| 185 | #define HDA_RMX_INSTRMPAY 113
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| 186 |
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| 187 | #define HDA_REG_INTCTL 11 /* 0x20 */
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| 188 | #define HDA_RMX_INTCTL 9
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| 189 | #define HDA_INTCTL_GIE RT_BIT(31) /* Global Interrupt Enable */
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| 190 | #define HDA_INTCTL_CIE RT_BIT(30) /* Controller Interrupt Enable */
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| 191 | /** Bits 0-29 correspond to streams 0-29. */
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| 192 | #define HDA_STRMINT_MASK 0xFF /* Streams 0-7 implemented. Applies to INTCTL and INTSTS. */
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| 193 |
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| 194 | #define HDA_REG_INTSTS 12 /* 0x24 */
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| 195 | #define HDA_RMX_INTSTS 10
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| 196 | #define HDA_INTSTS_GIS RT_BIT(31) /* Global Interrupt Status */
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| 197 | #define HDA_INTSTS_CIS RT_BIT(30) /* Controller Interrupt Status */
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| 198 |
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| 199 | #define HDA_REG_WALCLK 13 /* 0x30 */
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| 200 | /**NB: HDA_RMX_WALCLK is not defined because the register is not stored in memory. */
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| 201 |
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| 202 | /**
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| 203 | * Note: The HDA specification defines a SSYNC register at offset 0x38. The
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| 204 | * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
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| 205 | * the datasheet.
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| 206 | */
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| 207 | #define HDA_REG_SSYNC 14 /* 0x34 */
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| 208 | #define HDA_RMX_SSYNC 12
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| 209 |
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| 210 | #define HDA_REG_CORBLBASE 15 /* 0x40 */
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| 211 | #define HDA_RMX_CORBLBASE 13
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| 212 |
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| 213 | #define HDA_REG_CORBUBASE 16 /* 0x44 */
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| 214 | #define HDA_RMX_CORBUBASE 14
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| 215 |
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| 216 | #define HDA_REG_CORBWP 17 /* 0x48 */
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| 217 | #define HDA_RMX_CORBWP 15
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| 218 |
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| 219 | #define HDA_REG_CORBRP 18 /* 0x4A */
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| 220 | #define HDA_RMX_CORBRP 16
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| 221 | #define HDA_CORBRP_RST RT_BIT(15) /* CORB Read Pointer Reset */
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| 222 |
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| 223 | #define HDA_REG_CORBCTL 19 /* 0x4C */
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| 224 | #define HDA_RMX_CORBCTL 17
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| 225 | #define HDA_CORBCTL_DMA RT_BIT(1) /* Enable CORB DMA Engine */
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| 226 | #define HDA_CORBCTL_CMEIE RT_BIT(0) /* CORB Memory Error Interrupt Enable */
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| 227 |
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| 228 | #define HDA_REG_CORBSTS 20 /* 0x4D */
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| 229 | #define HDA_RMX_CORBSTS 18
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| 230 |
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| 231 | #define HDA_REG_CORBSIZE 21 /* 0x4E */
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| 232 | #define HDA_RMX_CORBSIZE 19
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| 233 | /** NB: Up to and including ICH 10, sizes of CORB and RIRB are fixed at 256 entries. */
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| 234 |
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| 235 | #define HDA_REG_RIRBLBASE 22 /* 0x50 */
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| 236 | #define HDA_RMX_RIRBLBASE 20
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| 237 |
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| 238 | #define HDA_REG_RIRBUBASE 23 /* 0x54 */
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| 239 | #define HDA_RMX_RIRBUBASE 21
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| 240 |
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| 241 | #define HDA_REG_RIRBWP 24 /* 0x58 */
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| 242 | #define HDA_RMX_RIRBWP 22
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| 243 | #define HDA_RIRBWP_RST RT_BIT(15) /* RIRB Write Pointer Reset */
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| 244 |
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| 245 | #define HDA_REG_RINTCNT 25 /* 0x5A */
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| 246 | #define HDA_RMX_RINTCNT 23
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| 247 | #define RINTCNT_N(pThis) (HDA_REG(pThis, RINTCNT) & 0xff)
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| 248 |
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| 249 | #define HDA_REG_RIRBCTL 26 /* 0x5C */
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| 250 | #define HDA_RMX_RIRBCTL 24
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| 251 | #define HDA_RIRBCTL_ROIC RT_BIT(2) /* Response Overrun Interrupt Control */
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| 252 | #define HDA_RIRBCTL_RDMAEN RT_BIT(1) /* RIRB DMA Enable */
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| 253 | #define HDA_RIRBCTL_RINTCTL RT_BIT(0) /* Response Interrupt Control */
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| 254 |
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| 255 | #define HDA_REG_RIRBSTS 27 /* 0x5D */
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| 256 | #define HDA_RMX_RIRBSTS 25
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| 257 | #define HDA_RIRBSTS_RIRBOIS RT_BIT(2) /* Response Overrun Interrupt Status */
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| 258 | #define HDA_RIRBSTS_RINTFL RT_BIT(0) /* Response Interrupt Flag */
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| 259 |
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| 260 | #define HDA_REG_RIRBSIZE 28 /* 0x5E */
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| 261 | #define HDA_RMX_RIRBSIZE 26
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| 262 |
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| 263 | #define HDA_REG_IC 29 /* 0x60 */
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| 264 | #define HDA_RMX_IC 27
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| 265 |
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| 266 | #define HDA_REG_IR 30 /* 0x64 */
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| 267 | #define HDA_RMX_IR 28
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| 268 |
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| 269 | #define HDA_REG_IRS 31 /* 0x68 */
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| 270 | #define HDA_RMX_IRS 29
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| 271 | #define HDA_IRS_IRV RT_BIT(1) /* Immediate Result Valid */
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| 272 | #define HDA_IRS_ICB RT_BIT(0) /* Immediate Command Busy */
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| 273 |
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| 274 | #define HDA_REG_DPLBASE 32 /* 0x70 */
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| 275 | #define HDA_RMX_DPLBASE 30
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| 276 |
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| 277 | #define HDA_REG_DPUBASE 33 /* 0x74 */
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| 278 | #define HDA_RMX_DPUBASE 31
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| 279 |
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| 280 | #define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
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| 281 |
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| 282 | #define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
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| 283 | #define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
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| 284 | /** Note: sdnum here _MUST_ be stream reg number [0,7]. */
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| 285 | #define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
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| 286 |
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| 287 | #define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
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| 288 |
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| 289 | /** @todo Condense marcos! */
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| 290 |
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| 291 | #define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80; other streams offset by 0x20 */
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| 292 | #define HDA_RMX_SD0CTL 32
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| 293 | #define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
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| 294 | #define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
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| 295 | #define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
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| 296 | #define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
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| 297 | #define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
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| 298 | #define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
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| 299 | #define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
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| 300 |
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| 301 | #define HDA_SDCTL_NUM_MASK 0xF
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| 302 | #define HDA_SDCTL_NUM_SHIFT 20
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| 303 | #define HDA_SDCTL_DIR RT_BIT(19) /* Direction (Bidirectional streams only!) */
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| 304 | #define HDA_SDCTL_TP RT_BIT(18) /* Traffic Priority (PCI Express) */
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| 305 | #define HDA_SDCTL_STRIPE_MASK 0x3
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| 306 | #define HDA_SDCTL_STRIPE_SHIFT 16
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| 307 | #define HDA_SDCTL_DEIE RT_BIT(4) /* Descriptor Error Interrupt Enable */
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| 308 | #define HDA_SDCTL_FEIE RT_BIT(3) /* FIFO Error Interrupt Enable */
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| 309 | #define HDA_SDCTL_IOCE RT_BIT(2) /* Interrupt On Completion Enable */
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| 310 | #define HDA_SDCTL_RUN RT_BIT(1) /* Stream Run */
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| 311 | #define HDA_SDCTL_SRST RT_BIT(0) /* Stream Reset */
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| 312 |
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| 313 | #define HDA_REG_SD0STS 35 /* 0x83; other streams offset by 0x20 */
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| 314 | #define HDA_RMX_SD0STS 33
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| 315 | #define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
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| 316 | #define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
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| 317 | #define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
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| 318 | #define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
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| 319 | #define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
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| 320 | #define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
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| 321 | #define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
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| 322 |
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| 323 | #define HDA_SDSTS_FIFORDY RT_BIT(5) /* FIFO Ready */
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| 324 | #define HDA_SDSTS_DESE RT_BIT(4) /* Descriptor Error */
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| 325 | #define HDA_SDSTS_FIFOE RT_BIT(3) /* FIFO Error */
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| 326 | #define HDA_SDSTS_BCIS RT_BIT(2) /* Buffer Completion Interrupt Status */
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| 327 |
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| 328 | #define HDA_REG_SD0LPIB 36 /* 0x84; other streams offset by 0x20 */
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| 329 | #define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
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| 330 | #define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
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| 331 | #define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
|
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| 332 | #define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
|
|---|
| 333 | #define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
|
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| 334 | #define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
|
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| 335 | #define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
|
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| 336 | #define HDA_RMX_SD0LPIB 34
|
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| 337 | #define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
|
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| 338 | #define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
|
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| 339 | #define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
|
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| 340 | #define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
|
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| 341 | #define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
|
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| 342 | #define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
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| 343 | #define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
|
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| 344 |
|
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| 345 | #define HDA_REG_SD0CBL 37 /* 0x88; other streams offset by 0x20 */
|
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| 346 | #define HDA_RMX_SD0CBL 35
|
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| 347 | #define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
|
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| 348 | #define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
|
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| 349 | #define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
|
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| 350 | #define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
|
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| 351 | #define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
|
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| 352 | #define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
|
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| 353 | #define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
|
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| 354 |
|
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| 355 | #define HDA_REG_SD0LVI 38 /* 0x8C; other streams offset by 0x20 */
|
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| 356 | #define HDA_RMX_SD0LVI 36
|
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| 357 | #define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
|
|---|
| 358 | #define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
|
|---|
| 359 | #define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
|
|---|
| 360 | #define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
|
|---|
| 361 | #define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
|
|---|
| 362 | #define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
|
|---|
| 363 | #define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
|
|---|
| 364 |
|
|---|
| 365 | #define HDA_REG_SD0FIFOW 39 /* 0x8E; other streams offset by 0x20 */
|
|---|
| 366 | #define HDA_RMX_SD0FIFOW 37
|
|---|
| 367 | #define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
|
|---|
| 368 | #define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
|
|---|
| 369 | #define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
|
|---|
| 370 | #define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
|
|---|
| 371 | #define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
|
|---|
| 372 | #define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
|
|---|
| 373 | #define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
|
|---|
| 374 |
|
|---|
| 375 | /*
|
|---|
| 376 | * ICH6 datasheet defined limits for FIFOW values (18.2.38).
|
|---|
| 377 | */
|
|---|
| 378 | #define HDA_SDFIFOW_8B 0x2
|
|---|
| 379 | #define HDA_SDFIFOW_16B 0x3
|
|---|
| 380 | #define HDA_SDFIFOW_32B 0x4
|
|---|
| 381 |
|
|---|
| 382 | #define HDA_REG_SD0FIFOS 40 /* 0x90; other streams offset by 0x20 */
|
|---|
| 383 | #define HDA_RMX_SD0FIFOS 38
|
|---|
| 384 | #define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
|
|---|
| 385 | #define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
|
|---|
| 386 | #define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
|
|---|
| 387 | #define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
|
|---|
| 388 | #define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
|
|---|
| 389 | #define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
|
|---|
| 390 | #define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
|
|---|
| 391 |
|
|---|
| 392 | #define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
|
|---|
| 393 | #define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
|
|---|
| 394 |
|
|---|
| 395 | #define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
|
|---|
| 396 | #define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
|
|---|
| 397 | #define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
|
|---|
| 398 | #define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
|
|---|
| 399 | #define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
|
|---|
| 400 | #define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
|
|---|
| 401 |
|
|---|
| 402 | #define HDA_REG_SD0FMT 41 /* 0x92; other streams offset by 0x20 */
|
|---|
| 403 | #define HDA_RMX_SD0FMT 39
|
|---|
| 404 | #define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
|
|---|
| 405 | #define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
|
|---|
| 406 | #define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
|
|---|
| 407 | #define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
|
|---|
| 408 | #define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
|
|---|
| 409 | #define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
|
|---|
| 410 | #define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
|
|---|
| 411 |
|
|---|
| 412 | #define HDA_REG_SD0BDPL 42 /* 0x98; other streams offset by 0x20 */
|
|---|
| 413 | #define HDA_RMX_SD0BDPL 40
|
|---|
| 414 | #define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
|
|---|
| 415 | #define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
|
|---|
| 416 | #define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
|
|---|
| 417 | #define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
|
|---|
| 418 | #define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
|
|---|
| 419 | #define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
|
|---|
| 420 | #define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
|
|---|
| 421 |
|
|---|
| 422 | #define HDA_REG_SD0BDPU 43 /* 0x9C; other streams offset by 0x20 */
|
|---|
| 423 | #define HDA_RMX_SD0BDPU 41
|
|---|
| 424 | #define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
|
|---|
| 425 | #define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
|
|---|
| 426 | #define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
|
|---|
| 427 | #define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
|
|---|
| 428 | #define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
|
|---|
| 429 | #define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
|
|---|
| 430 | #define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
|
|---|
| 431 |
|
|---|
| 432 | #define HDA_CODEC_CAD_SHIFT 28
|
|---|
| 433 | /** Encodes the (required) LUN into a codec command. */
|
|---|
| 434 | #define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
|
|---|
| 435 |
|
|---|
| 436 | #define HDA_SDFMT_NON_PCM_SHIFT 15
|
|---|
| 437 | #define HDA_SDFMT_NON_PCM_MASK 0x1
|
|---|
| 438 | #define HDA_SDFMT_BASE_RATE_SHIFT 14
|
|---|
| 439 | #define HDA_SDFMT_BASE_RATE_MASK 0x1
|
|---|
| 440 | #define HDA_SDFMT_MULT_SHIFT 11
|
|---|
| 441 | #define HDA_SDFMT_MULT_MASK 0x7
|
|---|
| 442 | #define HDA_SDFMT_DIV_SHIFT 8
|
|---|
| 443 | #define HDA_SDFMT_DIV_MASK 0x7
|
|---|
| 444 | #define HDA_SDFMT_BITS_SHIFT 4
|
|---|
| 445 | #define HDA_SDFMT_BITS_MASK 0x7
|
|---|
| 446 | #define HDA_SDFMT_CHANNELS_MASK 0xF
|
|---|
| 447 |
|
|---|
| 448 | #define HDA_SDFMT_TYPE RT_BIT(15)
|
|---|
| 449 | #define HDA_SDFMT_TYPE_PCM (0)
|
|---|
| 450 | #define HDA_SDFMT_TYPE_NON_PCM (1)
|
|---|
| 451 |
|
|---|
| 452 | #define HDA_SDFMT_BASE RT_BIT(14)
|
|---|
| 453 | #define HDA_SDFMT_BASE_48KHZ (0)
|
|---|
| 454 | #define HDA_SDFMT_BASE_44KHZ (1)
|
|---|
| 455 |
|
|---|
| 456 | #define HDA_SDFMT_MULT_1X (0)
|
|---|
| 457 | #define HDA_SDFMT_MULT_2X (1)
|
|---|
| 458 | #define HDA_SDFMT_MULT_3X (2)
|
|---|
| 459 | #define HDA_SDFMT_MULT_4X (3)
|
|---|
| 460 |
|
|---|
| 461 | #define HDA_SDFMT_DIV_1X (0)
|
|---|
| 462 | #define HDA_SDFMT_DIV_2X (1)
|
|---|
| 463 | #define HDA_SDFMT_DIV_3X (2)
|
|---|
| 464 | #define HDA_SDFMT_DIV_4X (3)
|
|---|
| 465 | #define HDA_SDFMT_DIV_5X (4)
|
|---|
| 466 | #define HDA_SDFMT_DIV_6X (5)
|
|---|
| 467 | #define HDA_SDFMT_DIV_7X (6)
|
|---|
| 468 | #define HDA_SDFMT_DIV_8X (7)
|
|---|
| 469 |
|
|---|
| 470 | #define HDA_SDFMT_8_BIT (0)
|
|---|
| 471 | #define HDA_SDFMT_16_BIT (1)
|
|---|
| 472 | #define HDA_SDFMT_20_BIT (2)
|
|---|
| 473 | #define HDA_SDFMT_24_BIT (3)
|
|---|
| 474 | #define HDA_SDFMT_32_BIT (4)
|
|---|
| 475 |
|
|---|
| 476 | #define HDA_SDFMT_CHAN_MONO (0)
|
|---|
| 477 | #define HDA_SDFMT_CHAN_STEREO (1)
|
|---|
| 478 |
|
|---|
| 479 | /** Emits a SDnFMT register format.
|
|---|
| 480 | * Also being used in the codec's converter format. */
|
|---|
| 481 | #define HDA_SDFMT_MAKE(_afNonPCM, _aBaseRate, _aMult, _aDiv, _aBits, _aChan) \
|
|---|
| 482 | ( (((_afNonPCM) & HDA_SDFMT_NON_PCM_MASK) << HDA_SDFMT_NON_PCM_SHIFT) \
|
|---|
| 483 | | (((_aBaseRate) & HDA_SDFMT_BASE_RATE_MASK) << HDA_SDFMT_BASE_RATE_SHIFT) \
|
|---|
| 484 | | (((_aMult) & HDA_SDFMT_MULT_MASK) << HDA_SDFMT_MULT_SHIFT) \
|
|---|
| 485 | | (((_aDiv) & HDA_SDFMT_DIV_MASK) << HDA_SDFMT_DIV_SHIFT) \
|
|---|
| 486 | | (((_aBits) & HDA_SDFMT_BITS_MASK) << HDA_SDFMT_BITS_SHIFT) \
|
|---|
| 487 | | ( (_aChan) & HDA_SDFMT_CHANNELS_MASK))
|
|---|
| 488 |
|
|---|
| 489 | /** Interrupt on completion (IOC) flag. */
|
|---|
| 490 | #define HDA_BDLE_FLAG_IOC RT_BIT(0)
|
|---|
| 491 |
|
|---|
| 492 | /*********************************************************************************************************************************
|
|---|
| 493 | * Prototypes *
|
|---|
| 494 | *********************************************************************************************************************************/
|
|---|
| 495 |
|
|---|
| 496 | /** The HDA controller. */
|
|---|
| 497 | typedef struct HDASTATE *PHDASTATE;
|
|---|
| 498 | /** The HDA stream. */
|
|---|
| 499 | typedef struct HDASTREAM *PHDASTREAM;
|
|---|
| 500 |
|
|---|
| 501 | typedef struct HDAMIXERSINK *PHDAMIXERSINK;
|
|---|
| 502 |
|
|---|
| 503 |
|
|---|
| 504 | /**
|
|---|
| 505 | * Internal state of a Buffer Descriptor List Entry (BDLE),
|
|---|
| 506 | * needed to keep track of the data needed for the actual device
|
|---|
| 507 | * emulation.
|
|---|
| 508 | */
|
|---|
| 509 | typedef struct HDABDLESTATE
|
|---|
| 510 | {
|
|---|
| 511 | /** Own index within the BDL (Buffer Descriptor List). */
|
|---|
| 512 | uint32_t u32BDLIndex;
|
|---|
| 513 | /** Number of bytes below the stream's FIFO watermark (SDFIFOW).
|
|---|
| 514 | * Used to check if we need fill up the FIFO again. */
|
|---|
| 515 | uint32_t cbBelowFIFOW;
|
|---|
| 516 | /** Current offset in DMA buffer (in bytes).*/
|
|---|
| 517 | uint32_t u32BufOff;
|
|---|
| 518 | uint32_t Padding;
|
|---|
| 519 | } HDABDLESTATE, *PHDABDLESTATE;
|
|---|
| 520 |
|
|---|
| 521 | /**
|
|---|
| 522 | * BDL description structure.
|
|---|
| 523 | * Do not touch this, as this must match to the HDA specs.
|
|---|
| 524 | */
|
|---|
| 525 | typedef struct HDABDLEDESC
|
|---|
| 526 | {
|
|---|
| 527 | /** Starting address of the actual buffer. Must be 128-bit aligned. */
|
|---|
| 528 | uint64_t u64BufAdr;
|
|---|
| 529 | /** Size of the actual buffer (in bytes). */
|
|---|
| 530 | uint32_t u32BufSize;
|
|---|
| 531 | /** Bit 0: Interrupt on completion; the controller will generate
|
|---|
| 532 | * an interrupt when the last byte of the buffer has been
|
|---|
| 533 | * fetched by the DMA engine.
|
|---|
| 534 | *
|
|---|
| 535 | * Rest is reserved for further use and must be 0. */
|
|---|
| 536 | uint32_t fFlags;
|
|---|
| 537 | } HDABDLEDESC, *PHDABDLEDESC;
|
|---|
| 538 | AssertCompileSize(HDABDLEDESC, 16); /* Always 16 byte. Also must be aligned on 128-byte boundary. */
|
|---|
| 539 |
|
|---|
| 540 | /**
|
|---|
| 541 | * Buffer Descriptor List Entry (BDLE) (3.6.3).
|
|---|
| 542 | */
|
|---|
| 543 | typedef struct HDABDLE
|
|---|
| 544 | {
|
|---|
| 545 | /** The actual BDL description. */
|
|---|
| 546 | HDABDLEDESC Desc;
|
|---|
| 547 | /** Internal state of this BDLE.
|
|---|
| 548 | * Not part of the actual BDLE registers. */
|
|---|
| 549 | HDABDLESTATE State;
|
|---|
| 550 | } HDABDLE, *PHDABDLE;
|
|---|
| 551 |
|
|---|
| 552 | /** @name Object lookup functions.
|
|---|
| 553 | * @{
|
|---|
| 554 | */
|
|---|
| 555 | PDMAUDIODIR hdaGetDirFromSD(uint8_t uSD);
|
|---|
| 556 | PHDASTREAM hdaGetStreamFromSD(PHDASTATE pThis, uint8_t uSD);
|
|---|
| 557 | PHDASTREAM hdaGetStreamFromSink(PHDASTATE pThis, PHDAMIXERSINK pSink);
|
|---|
| 558 | /** @} */
|
|---|
| 559 |
|
|---|
| 560 | /** @name Interrupt functions.
|
|---|
| 561 | * @{
|
|---|
| 562 | */
|
|---|
| 563 | #ifdef DEBUG
|
|---|
| 564 | int hdaProcessInterrupt(PHDASTATE pThis, const char *pszSource);
|
|---|
| 565 | #else
|
|---|
| 566 | int hdaProcessInterrupt(PHDASTATE pThis);
|
|---|
| 567 | #endif
|
|---|
| 568 | /** @} */
|
|---|
| 569 |
|
|---|
| 570 | /** @name Wall clock (WALCLK) functions.
|
|---|
| 571 | * @{
|
|---|
| 572 | */
|
|---|
| 573 | uint64_t hdaWalClkGetCurrent(PHDASTATE pThis);
|
|---|
| 574 | #ifdef IN_RING3
|
|---|
| 575 | bool hdaWalClkSet(PHDASTATE pThis, uint64_t u64WalClk, bool fForce);
|
|---|
| 576 | #endif
|
|---|
| 577 | /** @} */
|
|---|
| 578 |
|
|---|
| 579 | /** @name DMA utility functions.
|
|---|
| 580 | * @{
|
|---|
| 581 | */
|
|---|
| 582 | int hdaDMARead(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToRead, uint32_t *pcbRead);
|
|---|
| 583 | int hdaDMAWrite(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToWrite, uint32_t *pcbWritten);
|
|---|
| 584 | /** @} */
|
|---|
| 585 |
|
|---|
| 586 | /** @name Register functions.
|
|---|
| 587 | * @{
|
|---|
| 588 | */
|
|---|
| 589 | uint32_t hdaGetINTSTS(PHDASTATE pThis);
|
|---|
| 590 | #ifdef IN_RING3
|
|---|
| 591 | int hdaSDFMTToPCMProps(uint32_t u32SDFMT, PPDMAUDIOPCMPROPS pProps);
|
|---|
| 592 | #endif /* IN_RING3 */
|
|---|
| 593 | /** @} */
|
|---|
| 594 |
|
|---|
| 595 | /** @name BDLE (Buffer Descriptor List Entry) functions.
|
|---|
| 596 | * @{
|
|---|
| 597 | */
|
|---|
| 598 | #ifdef IN_RING3
|
|---|
| 599 | int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry);
|
|---|
| 600 | bool hdaBDLEIsComplete(PHDABDLE pBDLE);
|
|---|
| 601 | bool hdaBDLENeedsInterrupt(PHDABDLE pBDLE);
|
|---|
| 602 | #endif /* IN_RING3 */
|
|---|
| 603 | /** @} */
|
|---|
| 604 |
|
|---|
| 605 | #endif /* !DEV_HDA_H_COMMON */
|
|---|
| 606 |
|
|---|
