VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevHDACommon.h@ 85639

Last change on this file since 85639 was 82968, checked in by vboxsync, 5 years ago

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1/* $Id: DevHDACommon.h 82968 2020-02-04 10:35:17Z vboxsync $ */
2/** @file
3 * DevHDACommon.h - Shared HDA device defines / functions.
4 */
5
6/*
7 * Copyright (C) 2016-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VBOX_INCLUDED_SRC_Audio_DevHDACommon_h
19#define VBOX_INCLUDED_SRC_Audio_DevHDACommon_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include "AudioMixer.h"
25#include <VBox/log.h> /* LOG_ENABLED */
26
27/** Pointer to an HDA stream (SDI / SDO). */
28typedef struct HDASTREAMR3 *PHDASTREAMR3;
29
30
31
32/** Read callback. */
33typedef VBOXSTRICTRC FNHDAREGREAD(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
34/** Write callback. */
35typedef VBOXSTRICTRC FNHDAREGWRITE(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
36
37/**
38 * HDA register descriptor.
39 *
40 * See 302349 p 6.2.
41 */
42typedef struct HDAREGDESC
43{
44 /** Register offset in the register space. */
45 uint32_t offset;
46 /** Size in bytes. Registers of size > 4 are in fact tables. */
47 uint32_t size;
48 /** Readable bits. */
49 uint32_t readable;
50 /** Writable bits. */
51 uint32_t writable;
52 /** Register descriptor (RD) flags of type HDA_RD_F_XXX. These are used to
53 * specify the handling (read/write) policy of the register. */
54 uint32_t fFlags;
55 /** Read callback. */
56 FNHDAREGREAD *pfnRead;
57 /** Write callback. */
58 FNHDAREGWRITE *pfnWrite;
59 /** Index into the register storage array. */
60 uint32_t mem_idx;
61 /** Abbreviated name. */
62 const char *abbrev;
63 /** Descripton. */
64 const char *desc;
65} HDAREGDESC;
66/** Pointer to a a const HDA register descriptor. */
67typedef HDAREGDESC const *PCHDAREGDESC;
68
69/**
70 * HDA register aliases (HDA spec 3.3.45).
71 * @remarks Sorted by offReg.
72 */
73typedef struct HDAREGALIAS
74{
75 /** The alias register offset. */
76 uint32_t offReg;
77 /** The register index. */
78 int idxAlias;
79} HDAREGALIAS;
80
81/**
82 * At the moment we support 4 input + 4 output streams max, which is 8 in total.
83 * Bidirectional streams are currently *not* supported.
84 *
85 * Note: When changing any of those values, be prepared for some saved state
86 * fixups / trouble!
87 */
88#define HDA_MAX_SDI 4
89#define HDA_MAX_SDO 4
90#define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
91AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
92
93/** Number of general registers. */
94#define HDA_NUM_GENERAL_REGS 34
95/** Number of total registers in the HDA's register map. */
96#define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */))
97/** Total number of stream tags (channels). Index 0 is reserved / invalid. */
98#define HDA_MAX_TAGS 16
99
100/**
101 * ICH6 datasheet defines limits for FIFOS registers (18.2.39).
102 * Formula: size - 1
103 * Other values not listed are not supported.
104 */
105/** Maximum FIFO size (in bytes). */
106#define HDA_FIFO_MAX 256
107
108/** Default timer frequency (in Hz).
109 *
110 * Lowering this value can ask for trouble, as backends then can run
111 * into data underruns.
112 *
113 * Note: For handling surround setups (e.g. 5.1 speaker setups) we need
114 * a higher Hz rate, as the device emulation otherwise will come into
115 * timing trouble, making the output (DMA reads) crackling. */
116#define HDA_TIMER_HZ_DEFAULT 100
117
118/** Default position adjustment (in audio samples).
119 *
120 * For snd_hda_intel (Linux guests), the first BDL entry always is being used as
121 * so-called BDL adjustment, which can vary, and is being used for chipsets which
122 * misbehave and/or are incorrectly implemented.
123 *
124 * The BDL adjustment entry *always* has the IOC (Interrupt on Completion) bit set.
125 *
126 * For Intel Baytrail / Braswell implementations the BDL default adjustment is 32 frames, whereas
127 * for ICH / PCH it's only one (1) frame.
128 *
129 * See default_bdl_pos_adj() and snd_hdac_stream_setup_periods() for more information.
130 *
131 * By default we apply some simple heuristics in hdaStreamInit().
132 */
133#define HDA_POS_ADJUST_DEFAULT 0
134
135/** HDA's (fixed) audio frame size in bytes.
136 * We only support 16-bit stereo frames at the moment. */
137#define HDA_FRAME_SIZE_DEFAULT 4
138
139/** Offset of the SD0 register map. */
140#define HDA_REG_DESC_SD0_BASE 0x80
141
142/** Turn a short global register name into an memory index and a stringized name. */
143#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
144
145/** Turns a short stream register name into an memory index and a stringized name. */
146#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
147
148/** Same as above for a register *not* stored in memory. */
149#define HDA_REG_IDX_NOMEM(abbrev) 0, #abbrev
150
151extern const HDAREGDESC g_aHdaRegMap[HDA_NUM_REGS];
152
153/**
154 * NB: Register values stored in memory (au32Regs[]) are indexed through
155 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
156 * register descriptors in g_aHdaRegMap[] are indexed through the
157 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
158 *
159 * The au32Regs[] layout is kept unchanged for saved state
160 * compatibility.
161 */
162
163/* Registers */
164#define HDA_REG_IND_NAME(x) HDA_REG_##x
165#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
166#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
167#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
168
169
170#define HDA_REG_GCAP 0 /* Range 0x00 - 0x01 */
171#define HDA_RMX_GCAP 0
172/**
173 * GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
174 *
175 * oss (15:12) - Number of output streams supported.
176 * iss (11:8) - Number of input streams supported.
177 * bss (7:3) - Number of bidirectional streams supported.
178 * bds (2:1) - Number of serial data out (SDO) signals supported.
179 * b64sup (0) - 64 bit addressing supported.
180 */
181#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
182 ( (((oss) & 0xF) << 12) \
183 | (((iss) & 0xF) << 8) \
184 | (((bss) & 0x1F) << 3) \
185 | (((bds) & 0x3) << 2) \
186 | ((b64sup) & 1))
187
188#define HDA_REG_VMIN 1 /* 0x02 */
189#define HDA_RMX_VMIN 1
190
191#define HDA_REG_VMAJ 2 /* 0x03 */
192#define HDA_RMX_VMAJ 2
193
194#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
195#define HDA_RMX_OUTPAY 3
196
197#define HDA_REG_INPAY 4 /* 0x06-0x07 */
198#define HDA_RMX_INPAY 4
199
200#define HDA_REG_GCTL 5 /* 0x08-0x0B */
201#define HDA_RMX_GCTL 5
202#define HDA_GCTL_UNSOL RT_BIT(8) /* Accept Unsolicited Response Enable */
203#define HDA_GCTL_FCNTRL RT_BIT(1) /* Flush Control */
204#define HDA_GCTL_CRST RT_BIT(0) /* Controller Reset */
205
206#define HDA_REG_WAKEEN 6 /* 0x0C */
207#define HDA_RMX_WAKEEN 6
208
209#define HDA_REG_STATESTS 7 /* 0x0E */
210#define HDA_RMX_STATESTS 7
211#define HDA_STATESTS_SCSF_MASK 0x7 /* State Change Status Flags (6.2.8). */
212
213#define HDA_REG_GSTS 8 /* 0x10-0x11*/
214#define HDA_RMX_GSTS 8
215#define HDA_GSTS_FSTS RT_BIT(1) /* Flush Status */
216
217#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
218#define HDA_RMX_OUTSTRMPAY 112
219
220#define HDA_REG_INSTRMPAY 10 /* 0x1a */
221#define HDA_RMX_INSTRMPAY 113
222
223#define HDA_REG_INTCTL 11 /* 0x20 */
224#define HDA_RMX_INTCTL 9
225#define HDA_INTCTL_GIE RT_BIT(31) /* Global Interrupt Enable */
226#define HDA_INTCTL_CIE RT_BIT(30) /* Controller Interrupt Enable */
227/** Bits 0-29 correspond to streams 0-29. */
228#define HDA_STRMINT_MASK 0xFF /* Streams 0-7 implemented. Applies to INTCTL and INTSTS. */
229
230#define HDA_REG_INTSTS 12 /* 0x24 */
231#define HDA_RMX_INTSTS 10
232#define HDA_INTSTS_GIS RT_BIT(31) /* Global Interrupt Status */
233#define HDA_INTSTS_CIS RT_BIT(30) /* Controller Interrupt Status */
234
235#define HDA_REG_WALCLK 13 /* 0x30 */
236/**NB: HDA_RMX_WALCLK is not defined because the register is not stored in memory. */
237
238/**
239 * Note: The HDA specification defines a SSYNC register at offset 0x38. The
240 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
241 * the datasheet.
242 */
243#define HDA_REG_SSYNC 14 /* 0x34 */
244#define HDA_RMX_SSYNC 12
245
246#define HDA_REG_CORBLBASE 15 /* 0x40 */
247#define HDA_RMX_CORBLBASE 13
248
249#define HDA_REG_CORBUBASE 16 /* 0x44 */
250#define HDA_RMX_CORBUBASE 14
251
252#define HDA_REG_CORBWP 17 /* 0x48 */
253#define HDA_RMX_CORBWP 15
254
255#define HDA_REG_CORBRP 18 /* 0x4A */
256#define HDA_RMX_CORBRP 16
257#define HDA_CORBRP_RST RT_BIT(15) /* CORB Read Pointer Reset */
258
259#define HDA_REG_CORBCTL 19 /* 0x4C */
260#define HDA_RMX_CORBCTL 17
261#define HDA_CORBCTL_DMA RT_BIT(1) /* Enable CORB DMA Engine */
262#define HDA_CORBCTL_CMEIE RT_BIT(0) /* CORB Memory Error Interrupt Enable */
263
264#define HDA_REG_CORBSTS 20 /* 0x4D */
265#define HDA_RMX_CORBSTS 18
266
267#define HDA_REG_CORBSIZE 21 /* 0x4E */
268#define HDA_RMX_CORBSIZE 19
269#define HDA_CORBSIZE_SZ_CAP 0xF0
270#define HDA_CORBSIZE_SZ 0x3
271
272/** Number of CORB buffer entries. */
273#define HDA_CORB_SIZE 256
274/** CORB element size (in bytes). */
275#define HDA_CORB_ELEMENT_SIZE 4
276/** Number of RIRB buffer entries. */
277#define HDA_RIRB_SIZE 256
278/** RIRB element size (in bytes). */
279#define HDA_RIRB_ELEMENT_SIZE 8
280
281#define HDA_REG_RIRBLBASE 22 /* 0x50 */
282#define HDA_RMX_RIRBLBASE 20
283
284#define HDA_REG_RIRBUBASE 23 /* 0x54 */
285#define HDA_RMX_RIRBUBASE 21
286
287#define HDA_REG_RIRBWP 24 /* 0x58 */
288#define HDA_RMX_RIRBWP 22
289#define HDA_RIRBWP_RST RT_BIT(15) /* RIRB Write Pointer Reset */
290
291#define HDA_REG_RINTCNT 25 /* 0x5A */
292#define HDA_RMX_RINTCNT 23
293
294/** Maximum number of Response Interrupts. */
295#define HDA_MAX_RINTCNT 256
296
297#define HDA_REG_RIRBCTL 26 /* 0x5C */
298#define HDA_RMX_RIRBCTL 24
299#define HDA_RIRBCTL_ROIC RT_BIT(2) /* Response Overrun Interrupt Control */
300#define HDA_RIRBCTL_RDMAEN RT_BIT(1) /* RIRB DMA Enable */
301#define HDA_RIRBCTL_RINTCTL RT_BIT(0) /* Response Interrupt Control */
302
303#define HDA_REG_RIRBSTS 27 /* 0x5D */
304#define HDA_RMX_RIRBSTS 25
305#define HDA_RIRBSTS_RIRBOIS RT_BIT(2) /* Response Overrun Interrupt Status */
306#define HDA_RIRBSTS_RINTFL RT_BIT(0) /* Response Interrupt Flag */
307
308#define HDA_REG_RIRBSIZE 28 /* 0x5E */
309#define HDA_RMX_RIRBSIZE 26
310
311#define HDA_REG_IC 29 /* 0x60 */
312#define HDA_RMX_IC 27
313
314#define HDA_REG_IR 30 /* 0x64 */
315#define HDA_RMX_IR 28
316
317#define HDA_REG_IRS 31 /* 0x68 */
318#define HDA_RMX_IRS 29
319#define HDA_IRS_IRV RT_BIT(1) /* Immediate Result Valid */
320#define HDA_IRS_ICB RT_BIT(0) /* Immediate Command Busy */
321
322#define HDA_REG_DPLBASE 32 /* 0x70 */
323#define HDA_RMX_DPLBASE 30
324
325#define HDA_REG_DPUBASE 33 /* 0x74 */
326#define HDA_RMX_DPUBASE 31
327
328#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
329
330#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
331#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
332/** Note: sdnum here _MUST_ be stream reg number [0,7]. */
333#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
334
335#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
336
337/** @todo Condense marcos! */
338
339#define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80; other streams offset by 0x20 */
340#define HDA_RMX_SD0CTL 32
341#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
342#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
343#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
344#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
345#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
346#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
347#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
348
349#define HDA_SDCTL_NUM_MASK 0xF
350#define HDA_SDCTL_NUM_SHIFT 20
351#define HDA_SDCTL_DIR RT_BIT(19) /* Direction (Bidirectional streams only!) */
352#define HDA_SDCTL_TP RT_BIT(18) /* Traffic Priority (PCI Express) */
353#define HDA_SDCTL_STRIPE_MASK 0x3
354#define HDA_SDCTL_STRIPE_SHIFT 16
355#define HDA_SDCTL_DEIE RT_BIT(4) /* Descriptor Error Interrupt Enable */
356#define HDA_SDCTL_FEIE RT_BIT(3) /* FIFO Error Interrupt Enable */
357#define HDA_SDCTL_IOCE RT_BIT(2) /* Interrupt On Completion Enable */
358#define HDA_SDCTL_RUN RT_BIT(1) /* Stream Run */
359#define HDA_SDCTL_SRST RT_BIT(0) /* Stream Reset */
360
361#define HDA_REG_SD0STS 35 /* 0x83; other streams offset by 0x20 */
362#define HDA_RMX_SD0STS 33
363#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
364#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
365#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
366#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
367#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
368#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
369#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
370
371#define HDA_SDSTS_FIFORDY RT_BIT(5) /* FIFO Ready */
372#define HDA_SDSTS_DESE RT_BIT(4) /* Descriptor Error */
373#define HDA_SDSTS_FIFOE RT_BIT(3) /* FIFO Error */
374#define HDA_SDSTS_BCIS RT_BIT(2) /* Buffer Completion Interrupt Status */
375
376#define HDA_REG_SD0LPIB 36 /* 0x84; other streams offset by 0x20 */
377#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
378#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
379#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
380#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
381#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
382#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
383#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
384#define HDA_RMX_SD0LPIB 34
385#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
386#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
387#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
388#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
389#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
390#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
391#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
392
393#define HDA_REG_SD0CBL 37 /* 0x88; other streams offset by 0x20 */
394#define HDA_RMX_SD0CBL 35
395#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
396#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
397#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
398#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
399#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
400#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
401#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
402
403#define HDA_REG_SD0LVI 38 /* 0x8C; other streams offset by 0x20 */
404#define HDA_RMX_SD0LVI 36
405#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
406#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
407#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
408#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
409#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
410#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
411#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
412
413#define HDA_REG_SD0FIFOW 39 /* 0x8E; other streams offset by 0x20 */
414#define HDA_RMX_SD0FIFOW 37
415#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
416#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
417#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
418#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
419#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
420#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
421#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
422
423/*
424 * ICH6 datasheet defined limits for FIFOW values (18.2.38).
425 */
426#define HDA_SDFIFOW_8B 0x2
427#define HDA_SDFIFOW_16B 0x3
428#define HDA_SDFIFOW_32B 0x4
429
430#define HDA_REG_SD0FIFOS 40 /* 0x90; other streams offset by 0x20 */
431#define HDA_RMX_SD0FIFOS 38
432#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
433#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
434#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
435#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
436#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
437#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
438#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
439
440#define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
441#define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
442
443#define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
444#define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
445#define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
446#define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
447#define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
448#define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
449
450#define HDA_REG_SD0FMT 41 /* 0x92; other streams offset by 0x20 */
451#define HDA_RMX_SD0FMT 39
452#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
453#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
454#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
455#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
456#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
457#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
458#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
459
460#define HDA_REG_SD0BDPL 42 /* 0x98; other streams offset by 0x20 */
461#define HDA_RMX_SD0BDPL 40
462#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
463#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
464#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
465#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
466#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
467#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
468#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
469
470#define HDA_REG_SD0BDPU 43 /* 0x9C; other streams offset by 0x20 */
471#define HDA_RMX_SD0BDPU 41
472#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
473#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
474#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
475#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
476#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
477#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
478#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
479
480#define HDA_CODEC_CAD_SHIFT 28
481/** Encodes the (required) LUN into a codec command. */
482#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
483
484#define HDA_SDFMT_NON_PCM_SHIFT 15
485#define HDA_SDFMT_NON_PCM_MASK 0x1
486#define HDA_SDFMT_BASE_RATE_SHIFT 14
487#define HDA_SDFMT_BASE_RATE_MASK 0x1
488#define HDA_SDFMT_MULT_SHIFT 11
489#define HDA_SDFMT_MULT_MASK 0x7
490#define HDA_SDFMT_DIV_SHIFT 8
491#define HDA_SDFMT_DIV_MASK 0x7
492#define HDA_SDFMT_BITS_SHIFT 4
493#define HDA_SDFMT_BITS_MASK 0x7
494#define HDA_SDFMT_CHANNELS_MASK 0xF
495
496#define HDA_SDFMT_TYPE RT_BIT(15)
497#define HDA_SDFMT_TYPE_PCM (0)
498#define HDA_SDFMT_TYPE_NON_PCM (1)
499
500#define HDA_SDFMT_BASE RT_BIT(14)
501#define HDA_SDFMT_BASE_48KHZ (0)
502#define HDA_SDFMT_BASE_44KHZ (1)
503
504#define HDA_SDFMT_MULT_1X (0)
505#define HDA_SDFMT_MULT_2X (1)
506#define HDA_SDFMT_MULT_3X (2)
507#define HDA_SDFMT_MULT_4X (3)
508
509#define HDA_SDFMT_DIV_1X (0)
510#define HDA_SDFMT_DIV_2X (1)
511#define HDA_SDFMT_DIV_3X (2)
512#define HDA_SDFMT_DIV_4X (3)
513#define HDA_SDFMT_DIV_5X (4)
514#define HDA_SDFMT_DIV_6X (5)
515#define HDA_SDFMT_DIV_7X (6)
516#define HDA_SDFMT_DIV_8X (7)
517
518#define HDA_SDFMT_8_BIT (0)
519#define HDA_SDFMT_16_BIT (1)
520#define HDA_SDFMT_20_BIT (2)
521#define HDA_SDFMT_24_BIT (3)
522#define HDA_SDFMT_32_BIT (4)
523
524#define HDA_SDFMT_CHAN_MONO (0)
525#define HDA_SDFMT_CHAN_STEREO (1)
526
527/** Emits a SDnFMT register format.
528 * Also being used in the codec's converter format. */
529#define HDA_SDFMT_MAKE(_afNonPCM, _aBaseRate, _aMult, _aDiv, _aBits, _aChan) \
530 ( (((_afNonPCM) & HDA_SDFMT_NON_PCM_MASK) << HDA_SDFMT_NON_PCM_SHIFT) \
531 | (((_aBaseRate) & HDA_SDFMT_BASE_RATE_MASK) << HDA_SDFMT_BASE_RATE_SHIFT) \
532 | (((_aMult) & HDA_SDFMT_MULT_MASK) << HDA_SDFMT_MULT_SHIFT) \
533 | (((_aDiv) & HDA_SDFMT_DIV_MASK) << HDA_SDFMT_DIV_SHIFT) \
534 | (((_aBits) & HDA_SDFMT_BITS_MASK) << HDA_SDFMT_BITS_SHIFT) \
535 | ( (_aChan) & HDA_SDFMT_CHANNELS_MASK))
536
537/** Interrupt on completion (IOC) flag. */
538#define HDA_BDLE_F_IOC RT_BIT(0)
539
540
541
542/** Pointer to a shared HDA state. */
543typedef struct HDASTATE *PHDASTATE;
544/** Pointer to a HDA stream state. */
545typedef struct HDASTREAM *PHDASTREAM;
546/** Pointer to a mixer sink. */
547typedef struct HDAMIXERSINK *PHDAMIXERSINK;
548
549
550/**
551 * Internal state of a Buffer Descriptor List Entry (BDLE),
552 * needed to keep track of the data needed for the actual device
553 * emulation.
554 */
555typedef struct HDABDLESTATE
556{
557 /** Own index within the BDL (Buffer Descriptor List). */
558 uint32_t u32BDLIndex;
559 /** Number of bytes below the stream's FIFO watermark (SDFIFOW).
560 * Used to check if we need fill up the FIFO again. */
561 uint32_t cbBelowFIFOW;
562 /** Current offset in DMA buffer (in bytes).*/
563 uint32_t u32BufOff;
564 uint32_t Padding;
565} HDABDLESTATE, *PHDABDLESTATE;
566
567/**
568 * BDL description structure.
569 * Do not touch this, as this must match to the HDA specs.
570 */
571typedef struct HDABDLEDESC
572{
573 /** Starting address of the actual buffer. Must be 128-bit aligned. */
574 uint64_t u64BufAddr;
575 /** Size of the actual buffer (in bytes). */
576 uint32_t u32BufSize;
577 /** Bit 0: Interrupt on completion; the controller will generate
578 * an interrupt when the last byte of the buffer has been
579 * fetched by the DMA engine.
580 *
581 * Rest is reserved for further use and must be 0. */
582 uint32_t fFlags;
583} HDABDLEDESC, *PHDABDLEDESC;
584AssertCompileSize(HDABDLEDESC, 16); /* Always 16 byte. Also must be aligned on 128-byte boundary. */
585
586/**
587 * Buffer Descriptor List Entry (BDLE) (3.6.3).
588 */
589typedef struct HDABDLE
590{
591 /** The actual BDL description. */
592 HDABDLEDESC Desc;
593 /** Internal state of this BDLE.
594 * Not part of the actual BDLE registers. */
595 HDABDLESTATE State;
596} HDABDLE;
597AssertCompileSizeAlignment(HDABDLE, 8);
598/** Pointer to a buffer descriptor list entry (BDLE). */
599typedef HDABDLE *PHDABDLE;
600
601/** @name Object lookup functions.
602 * @{
603 */
604#ifdef IN_RING3
605PHDAMIXERSINK hdaR3GetDefaultSink(PHDASTATER3 pThisCC, uint8_t uSD);
606#endif
607PDMAUDIODIR hdaGetDirFromSD(uint8_t uSD);
608//PHDASTREAM hdaGetStreamFromSD(PHDASTATER3 pThisCC, uint8_t uSD);
609#ifdef IN_RING3
610PHDASTREAMR3 hdaR3GetR3StreamFromSink(PHDAMIXERSINK pSink);
611PHDASTREAM hdaR3GetSharedStreamFromSink(PHDAMIXERSINK pSink);
612#endif
613/** @} */
614
615/** @name Interrupt functions.
616 * @{
617 */
618#if defined(LOG_ENABLED) || defined(DOXYGEN_RUNNING)
619void hdaProcessInterrupt(PPDMDEVINS pDevIns, PHDASTATE pThis, const char *pszSource);
620# define HDA_PROCESS_INTERRUPT(a_pDevIns, a_pThis) hdaProcessInterrupt((a_pDevIns), (a_pThis), __FUNCTION__)
621#else
622void hdaProcessInterrupt(PPDMDEVINS pDevIns, PHDASTATE pThis);
623# define HDA_PROCESS_INTERRUPT(a_pDevIns, a_pThis) hdaProcessInterrupt((a_pDevIns), (a_pThis))
624#endif
625/** @} */
626
627/** @name Wall clock (WALCLK) functions.
628 * @{
629 */
630uint64_t hdaWalClkGetCurrent(PHDASTATE pThis);
631#ifdef IN_RING3
632bool hdaR3WalClkSet(PHDASTATE pThis, PHDASTATER3 pThisCC, uint64_t u64WalClk, bool fForce);
633#endif
634/** @} */
635
636/** @name DMA utility functions.
637 * @{
638 */
639#ifdef IN_RING3
640int hdaR3DMARead(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3,
641 void *pvBuf, uint32_t cbBuf, uint32_t *pcbRead);
642int hdaR3DMAWrite(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3,
643 const void *pvBuf, uint32_t cbBuf, uint32_t *pcbWritten);
644#endif
645/** @} */
646
647/** @name Register functions.
648 * @{
649 */
650uint32_t hdaGetINTSTS(PHDASTATE pThis);
651#ifdef IN_RING3
652int hdaR3SDFMTToPCMProps(uint16_t u16SDFMT, PPDMAUDIOPCMPROPS pProps);
653#endif /* IN_RING3 */
654/** @} */
655
656/** @name BDLE (Buffer Descriptor List Entry) functions.
657 * @{
658 */
659#ifdef IN_RING3
660# ifdef LOG_ENABLED
661void hdaR3BDLEDumpAll(PPDMDEVINS pDevIns, PHDASTATE pThis, uint64_t u64BDLBase, uint16_t cBDLE);
662# endif
663int hdaR3BDLEFetch(PPDMDEVINS pDevIns, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry);
664bool hdaR3BDLEIsComplete(PHDABDLE pBDLE);
665bool hdaR3BDLENeedsInterrupt(PHDABDLE pBDLE);
666#endif /* IN_RING3 */
667/** @} */
668
669/** @name Device timer functions.
670 * @{
671 */
672#ifdef IN_RING3
673bool hdaR3TimerSet(PPDMDEVINS pDevIns, PHDASTREAM pStreamShared, uint64_t u64Expire, bool fForce, uint64_t tsNow);
674#endif
675/** @} */
676
677#endif /* !VBOX_INCLUDED_SRC_Audio_DevHDACommon_h */
678
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