DevHDACommon.h@ 69833

Last change on this file since 69833 was 69719, checked in by vboxsync, 7 years ago
Audio/HDA: Forward ported / integrated r119000 + r119062 (Fixed CORB / RIRB buffer handling when issuing multiple commands at once; fixes device detection on some OSes (e.g. Haiku)).
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 25.5 KB

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1	/* $Id: DevHDACommon.h 69719 2017-11-16 15:11:55Z vboxsync $ */
2	/** @file
3	* DevHDACommon.h - Shared HDA device defines / functions.
4	*/
5
6	/*
7	* Copyright (C) 2016-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef DEV_HDA_COMMON_H
19	#define DEV_HDA_COMMON_H
20
21	#include "AudioMixer.h"
22
23	/** See 302349 p 6.2. */
24	typedef struct HDAREGDESC
25	{
26	/** Register offset in the register space. */
27	uint32_t offset;
28	/** Size in bytes. Registers of size > 4 are in fact tables. */
29	uint32_t size;
30	/** Readable bits. */
31	uint32_t readable;
32	/** Writable bits. */
33	uint32_t writable;
34	/** Register descriptor (RD) flags of type HDA_RD_FLAG_.
35	* These are used to specify the handling (read/write)
36	* policy of the register. */
37	uint32_t fFlags;
38	/** Read callback. */
39	int (pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t pu32Value);
40	/** Write callback. */
41	int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
42	/** Index into the register storage array. */
43	uint32_t mem_idx;
44	/** Abbreviated name. */
45	const char *abbrev;
46	/** Descripton. */
47	const char *desc;
48	} HDAREGDESC, *PHDAREGDESC;
49
50	/**
51	* HDA register aliases (HDA spec 3.3.45).
52	* @remarks Sorted by offReg.
53	*/
54	typedef struct HDAREGALIAS
55	{
56	/** The alias register offset. */
57	uint32_t offReg;
58	/** The register index. */
59	int idxAlias;
60	} HDAREGALIAS, *PHDAREGALIAS;
61
62	/**
63	* At the moment we support 4 input + 4 output streams max, which is 8 in total.
64	* Bidirectional streams are currently not supported.
65	*
66	* Note: When changing any of those values, be prepared for some saved state
67	* fixups / trouble!
68	*/
69	#define HDA_MAX_SDI 4
70	#define HDA_MAX_SDO 4
71	#define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
72	AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
73
74	/** Number of general registers. */
75	#define HDA_NUM_GENERAL_REGS 34
76	/** Number of total registers in the HDA's register map. */
77	#define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */))
78	/** Total number of stream tags (channels). Index 0 is reserved / invalid. */
79	#define HDA_MAX_TAGS 16
80
81	/**
82	* ICH6 datasheet defines limits for FIFOS registers (18.2.39).
83	* Formula: size - 1
84	* Other values not listed are not supported.
85	*/
86	/** Maximum FIFO size (in bytes). */
87	#define HDA_FIFO_MAX 256
88
89	/** Default timer frequency (in Hz).
90	*
91	* Note: Keep in mind that the Hz rate has nothing to do with samples rates
92	* or DMA / interrupt timing -- it's purely needed in order to drive
93	* the data flow at a constant (and sufficient) rate.
94	*
95	* Lowering this value can ask for trouble, as backends then can run
96	* into data underruns. */
97	#define HDA_TIMER_HZ 200
98
99	/** HDA's (fixed) audio frame size in bytes.
100	* We only support 16-bit stereo frames at the moment. */
101	#define HDA_FRAME_SIZE 4
102
103	/** Offset of the SD0 register map. */
104	#define HDA_REG_DESC_SD0_BASE 0x80
105
106	/** Turn a short global register name into an memory index and a stringized name. */
107	#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
108
109	/** Turns a short stream register name into an memory index and a stringized name. */
110	#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
111
112	/** Same as above for a register not stored in memory. */
113	#define HDA_REG_IDX_NOMEM(abbrev) 0, #abbrev
114
115	extern const HDAREGDESC g_aHdaRegMap[HDA_NUM_REGS];
116
117	/**
118	* NB: Register values stored in memory (au32Regs[]) are indexed through
119	* the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
120	* register descriptors in g_aHdaRegMap[] are indexed through the
121	* HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
122	*
123	* The au32Regs[] layout is kept unchanged for saved state
124	* compatibility.
125	*/
126
127	/* Registers */
128	#define HDA_REG_IND_NAME(x) HDA_REG_##x
129	#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
130	#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
131	#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
132
133
134	#define HDA_REG_GCAP 0 /* Range 0x00 - 0x01 */
135	#define HDA_RMX_GCAP 0
136	/**
137	* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
138	*
139	* oss (15:12) - Number of output streams supported.
140	* iss (11:8) - Number of input streams supported.
141	* bss (7:3) - Number of bidirectional streams supported.
142	* bds (2:1) - Number of serial data out (SDO) signals supported.
143	* b64sup (0) - 64 bit addressing supported.
144	*/
145	#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
146	( (((oss) & 0xF) << 12) \
147	\| (((iss) & 0xF) << 8) \
148	\| (((bss) & 0x1F) << 3) \
149	\| (((bds) & 0x3) << 2) \
150	\| ((b64sup) & 1))
151
152	#define HDA_REG_VMIN 1 /* 0x02 */
153	#define HDA_RMX_VMIN 1
154
155	#define HDA_REG_VMAJ 2 /* 0x03 */
156	#define HDA_RMX_VMAJ 2
157
158	#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
159	#define HDA_RMX_OUTPAY 3
160
161	#define HDA_REG_INPAY 4 /* 0x06-0x07 */
162	#define HDA_RMX_INPAY 4
163
164	#define HDA_REG_GCTL 5 /* 0x08-0x0B */
165	#define HDA_RMX_GCTL 5
166	#define HDA_GCTL_UNSOL RT_BIT(8) /* Accept Unsolicited Response Enable */
167	#define HDA_GCTL_FCNTRL RT_BIT(1) /* Flush Control */
168	#define HDA_GCTL_CRST RT_BIT(0) /* Controller Reset */
169
170	#define HDA_REG_WAKEEN 6 /* 0x0C */
171	#define HDA_RMX_WAKEEN 6
172
173	#define HDA_REG_STATESTS 7 /* 0x0E */
174	#define HDA_RMX_STATESTS 7
175	#define HDA_STATESTS_SCSF_MASK 0x7 /* State Change Status Flags (6.2.8). */
176
177	#define HDA_REG_GSTS 8 /* 0x10-0x11*/
178	#define HDA_RMX_GSTS 8
179	#define HDA_GSTS_FSTS RT_BIT(1) /* Flush Status */
180
181	#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
182	#define HDA_RMX_OUTSTRMPAY 112
183
184	#define HDA_REG_INSTRMPAY 10 /* 0x1a */
185	#define HDA_RMX_INSTRMPAY 113
186
187	#define HDA_REG_INTCTL 11 /* 0x20 */
188	#define HDA_RMX_INTCTL 9
189	#define HDA_INTCTL_GIE RT_BIT(31) /* Global Interrupt Enable */
190	#define HDA_INTCTL_CIE RT_BIT(30) /* Controller Interrupt Enable */
191	/** Bits 0-29 correspond to streams 0-29. */
192	#define HDA_STRMINT_MASK 0xFF /* Streams 0-7 implemented. Applies to INTCTL and INTSTS. */
193
194	#define HDA_REG_INTSTS 12 /* 0x24 */
195	#define HDA_RMX_INTSTS 10
196	#define HDA_INTSTS_GIS RT_BIT(31) /* Global Interrupt Status */
197	#define HDA_INTSTS_CIS RT_BIT(30) /* Controller Interrupt Status */
198
199	#define HDA_REG_WALCLK 13 /* 0x30 */
200	/*NB: HDA_RMX_WALCLK is not defined because the register is not stored in memory. /
201
202	/**
203	* Note: The HDA specification defines a SSYNC register at offset 0x38. The
204	* ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
205	* the datasheet.
206	*/
207	#define HDA_REG_SSYNC 14 /* 0x34 */
208	#define HDA_RMX_SSYNC 12
209
210	#define HDA_REG_CORBLBASE 15 /* 0x40 */
211	#define HDA_RMX_CORBLBASE 13
212
213	#define HDA_REG_CORBUBASE 16 /* 0x44 */
214	#define HDA_RMX_CORBUBASE 14
215
216	#define HDA_REG_CORBWP 17 /* 0x48 */
217	#define HDA_RMX_CORBWP 15
218
219	#define HDA_REG_CORBRP 18 /* 0x4A */
220	#define HDA_RMX_CORBRP 16
221	#define HDA_CORBRP_RST RT_BIT(15) /* CORB Read Pointer Reset */
222
223	#define HDA_REG_CORBCTL 19 /* 0x4C */
224	#define HDA_RMX_CORBCTL 17
225	#define HDA_CORBCTL_DMA RT_BIT(1) /* Enable CORB DMA Engine */
226	#define HDA_CORBCTL_CMEIE RT_BIT(0) /* CORB Memory Error Interrupt Enable */
227
228	#define HDA_REG_CORBSTS 20 /* 0x4D */
229	#define HDA_RMX_CORBSTS 18
230
231	#define HDA_REG_CORBSIZE 21 /* 0x4E */
232	#define HDA_RMX_CORBSIZE 19
233
234	/** Number of CORB buffer entries. */
235	#define HDA_CORB_SIZE 256
236	/** Number of RIRB buffer entries. */
237	#define HDA_RIRB_SIZE 256
238
239	#define HDA_REG_RIRBLBASE 22 /* 0x50 */
240	#define HDA_RMX_RIRBLBASE 20
241
242	#define HDA_REG_RIRBUBASE 23 /* 0x54 */
243	#define HDA_RMX_RIRBUBASE 21
244
245	#define HDA_REG_RIRBWP 24 /* 0x58 */
246	#define HDA_RMX_RIRBWP 22
247	#define HDA_RIRBWP_RST RT_BIT(15) /* RIRB Write Pointer Reset */
248
249	#define HDA_REG_RINTCNT 25 /* 0x5A */
250	#define HDA_RMX_RINTCNT 23
251
252	/** Maximum number of Response Interrupts. */
253	#define HDA_MAX_RINTCNT 256
254
255	#define HDA_REG_RIRBCTL 26 /* 0x5C */
256	#define HDA_RMX_RIRBCTL 24
257	#define HDA_RIRBCTL_ROIC RT_BIT(2) /* Response Overrun Interrupt Control */
258	#define HDA_RIRBCTL_RDMAEN RT_BIT(1) /* RIRB DMA Enable */
259	#define HDA_RIRBCTL_RINTCTL RT_BIT(0) /* Response Interrupt Control */
260
261	#define HDA_REG_RIRBSTS 27 /* 0x5D */
262	#define HDA_RMX_RIRBSTS 25
263	#define HDA_RIRBSTS_RIRBOIS RT_BIT(2) /* Response Overrun Interrupt Status */
264	#define HDA_RIRBSTS_RINTFL RT_BIT(0) /* Response Interrupt Flag */
265
266	#define HDA_REG_RIRBSIZE 28 /* 0x5E */
267	#define HDA_RMX_RIRBSIZE 26
268
269	#define HDA_REG_IC 29 /* 0x60 */
270	#define HDA_RMX_IC 27
271
272	#define HDA_REG_IR 30 /* 0x64 */
273	#define HDA_RMX_IR 28
274
275	#define HDA_REG_IRS 31 /* 0x68 */
276	#define HDA_RMX_IRS 29
277	#define HDA_IRS_IRV RT_BIT(1) /* Immediate Result Valid */
278	#define HDA_IRS_ICB RT_BIT(0) /* Immediate Command Busy */
279
280	#define HDA_REG_DPLBASE 32 /* 0x70 */
281	#define HDA_RMX_DPLBASE 30
282
283	#define HDA_REG_DPUBASE 33 /* 0x74 */
284	#define HDA_RMX_DPUBASE 31
285
286	#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
287
288	#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
289	#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
290	/** Note: sdnum here _MUST_ be stream reg number [0,7]. */
291	#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
292
293	#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
294
295	/** @todo Condense marcos! */
296
297	#define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80; other streams offset by 0x20 */
298	#define HDA_RMX_SD0CTL 32
299	#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
300	#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
301	#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
302	#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
303	#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
304	#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
305	#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
306
307	#define HDA_SDCTL_NUM_MASK 0xF
308	#define HDA_SDCTL_NUM_SHIFT 20
309	#define HDA_SDCTL_DIR RT_BIT(19) /* Direction (Bidirectional streams only!) */
310	#define HDA_SDCTL_TP RT_BIT(18) /* Traffic Priority (PCI Express) */
311	#define HDA_SDCTL_STRIPE_MASK 0x3
312	#define HDA_SDCTL_STRIPE_SHIFT 16
313	#define HDA_SDCTL_DEIE RT_BIT(4) /* Descriptor Error Interrupt Enable */
314	#define HDA_SDCTL_FEIE RT_BIT(3) /* FIFO Error Interrupt Enable */
315	#define HDA_SDCTL_IOCE RT_BIT(2) /* Interrupt On Completion Enable */
316	#define HDA_SDCTL_RUN RT_BIT(1) /* Stream Run */
317	#define HDA_SDCTL_SRST RT_BIT(0) /* Stream Reset */
318
319	#define HDA_REG_SD0STS 35 /* 0x83; other streams offset by 0x20 */
320	#define HDA_RMX_SD0STS 33
321	#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
322	#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
323	#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
324	#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
325	#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
326	#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
327	#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
328
329	#define HDA_SDSTS_FIFORDY RT_BIT(5) /* FIFO Ready */
330	#define HDA_SDSTS_DESE RT_BIT(4) /* Descriptor Error */
331	#define HDA_SDSTS_FIFOE RT_BIT(3) /* FIFO Error */
332	#define HDA_SDSTS_BCIS RT_BIT(2) /* Buffer Completion Interrupt Status */
333
334	#define HDA_REG_SD0LPIB 36 /* 0x84; other streams offset by 0x20 */
335	#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
336	#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
337	#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
338	#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
339	#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
340	#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
341	#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
342	#define HDA_RMX_SD0LPIB 34
343	#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
344	#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
345	#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
346	#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
347	#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
348	#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
349	#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
350
351	#define HDA_REG_SD0CBL 37 /* 0x88; other streams offset by 0x20 */
352	#define HDA_RMX_SD0CBL 35
353	#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
354	#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
355	#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
356	#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
357	#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
358	#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
359	#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
360
361	#define HDA_REG_SD0LVI 38 /* 0x8C; other streams offset by 0x20 */
362	#define HDA_RMX_SD0LVI 36
363	#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
364	#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
365	#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
366	#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
367	#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
368	#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
369	#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
370
371	#define HDA_REG_SD0FIFOW 39 /* 0x8E; other streams offset by 0x20 */
372	#define HDA_RMX_SD0FIFOW 37
373	#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
374	#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
375	#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
376	#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
377	#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
378	#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
379	#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
380
381	/*
382	* ICH6 datasheet defined limits for FIFOW values (18.2.38).
383	*/
384	#define HDA_SDFIFOW_8B 0x2
385	#define HDA_SDFIFOW_16B 0x3
386	#define HDA_SDFIFOW_32B 0x4
387
388	#define HDA_REG_SD0FIFOS 40 /* 0x90; other streams offset by 0x20 */
389	#define HDA_RMX_SD0FIFOS 38
390	#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
391	#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
392	#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
393	#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
394	#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
395	#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
396	#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
397
398	#define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
399	#define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
400
401	#define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
402	#define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
403	#define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
404	#define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
405	#define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
406	#define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
407
408	#define HDA_REG_SD0FMT 41 /* 0x92; other streams offset by 0x20 */
409	#define HDA_RMX_SD0FMT 39
410	#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
411	#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
412	#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
413	#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
414	#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
415	#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
416	#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
417
418	#define HDA_REG_SD0BDPL 42 /* 0x98; other streams offset by 0x20 */
419	#define HDA_RMX_SD0BDPL 40
420	#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
421	#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
422	#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
423	#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
424	#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
425	#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
426	#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
427
428	#define HDA_REG_SD0BDPU 43 /* 0x9C; other streams offset by 0x20 */
429	#define HDA_RMX_SD0BDPU 41
430	#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
431	#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
432	#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
433	#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
434	#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
435	#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
436	#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
437
438	#define HDA_CODEC_CAD_SHIFT 28
439	/** Encodes the (required) LUN into a codec command. */
440	#define HDA_CODEC_CMD(cmd, lun) ((cmd) \| (lun << HDA_CODEC_CAD_SHIFT))
441
442	#define HDA_SDFMT_NON_PCM_SHIFT 15
443	#define HDA_SDFMT_NON_PCM_MASK 0x1
444	#define HDA_SDFMT_BASE_RATE_SHIFT 14
445	#define HDA_SDFMT_BASE_RATE_MASK 0x1
446	#define HDA_SDFMT_MULT_SHIFT 11
447	#define HDA_SDFMT_MULT_MASK 0x7
448	#define HDA_SDFMT_DIV_SHIFT 8
449	#define HDA_SDFMT_DIV_MASK 0x7
450	#define HDA_SDFMT_BITS_SHIFT 4
451	#define HDA_SDFMT_BITS_MASK 0x7
452	#define HDA_SDFMT_CHANNELS_MASK 0xF
453
454	#define HDA_SDFMT_TYPE RT_BIT(15)
455	#define HDA_SDFMT_TYPE_PCM (0)
456	#define HDA_SDFMT_TYPE_NON_PCM (1)
457
458	#define HDA_SDFMT_BASE RT_BIT(14)
459	#define HDA_SDFMT_BASE_48KHZ (0)
460	#define HDA_SDFMT_BASE_44KHZ (1)
461
462	#define HDA_SDFMT_MULT_1X (0)
463	#define HDA_SDFMT_MULT_2X (1)
464	#define HDA_SDFMT_MULT_3X (2)
465	#define HDA_SDFMT_MULT_4X (3)
466
467	#define HDA_SDFMT_DIV_1X (0)
468	#define HDA_SDFMT_DIV_2X (1)
469	#define HDA_SDFMT_DIV_3X (2)
470	#define HDA_SDFMT_DIV_4X (3)
471	#define HDA_SDFMT_DIV_5X (4)
472	#define HDA_SDFMT_DIV_6X (5)
473	#define HDA_SDFMT_DIV_7X (6)
474	#define HDA_SDFMT_DIV_8X (7)
475
476	#define HDA_SDFMT_8_BIT (0)
477	#define HDA_SDFMT_16_BIT (1)
478	#define HDA_SDFMT_20_BIT (2)
479	#define HDA_SDFMT_24_BIT (3)
480	#define HDA_SDFMT_32_BIT (4)
481
482	#define HDA_SDFMT_CHAN_MONO (0)
483	#define HDA_SDFMT_CHAN_STEREO (1)
484
485	/** Emits a SDnFMT register format.
486	* Also being used in the codec's converter format. */
487	#define HDA_SDFMT_MAKE(_afNonPCM, _aBaseRate, _aMult, _aDiv, _aBits, _aChan) \
488	( (((_afNonPCM) & HDA_SDFMT_NON_PCM_MASK) << HDA_SDFMT_NON_PCM_SHIFT) \
489	\| (((_aBaseRate) & HDA_SDFMT_BASE_RATE_MASK) << HDA_SDFMT_BASE_RATE_SHIFT) \
490	\| (((_aMult) & HDA_SDFMT_MULT_MASK) << HDA_SDFMT_MULT_SHIFT) \
491	\| (((_aDiv) & HDA_SDFMT_DIV_MASK) << HDA_SDFMT_DIV_SHIFT) \
492	\| (((_aBits) & HDA_SDFMT_BITS_MASK) << HDA_SDFMT_BITS_SHIFT) \
493	\| ( (_aChan) & HDA_SDFMT_CHANNELS_MASK))
494
495	/** Interrupt on completion (IOC) flag. */
496	#define HDA_BDLE_FLAG_IOC RT_BIT(0)
497
498	/*********************************************************************************************************************************
499	* Prototypes *
500	*********************************************************************************************************************************/
501
502	/** The HDA controller. */
503	typedef struct HDASTATE *PHDASTATE;
504	/** The HDA stream. */
505	typedef struct HDASTREAM *PHDASTREAM;
506
507	typedef struct HDAMIXERSINK *PHDAMIXERSINK;
508
509
510	/**
511	* Internal state of a Buffer Descriptor List Entry (BDLE),
512	* needed to keep track of the data needed for the actual device
513	* emulation.
514	*/
515	typedef struct HDABDLESTATE
516	{
517	/** Own index within the BDL (Buffer Descriptor List). */
518	uint32_t u32BDLIndex;
519	/** Number of bytes below the stream's FIFO watermark (SDFIFOW).
520	* Used to check if we need fill up the FIFO again. */
521	uint32_t cbBelowFIFOW;
522	/** Current offset in DMA buffer (in bytes).*/
523	uint32_t u32BufOff;
524	uint32_t Padding;
525	} HDABDLESTATE, *PHDABDLESTATE;
526
527	/**
528	* BDL description structure.
529	* Do not touch this, as this must match to the HDA specs.
530	*/
531	typedef struct HDABDLEDESC
532	{
533	/** Starting address of the actual buffer. Must be 128-bit aligned. */
534	uint64_t u64BufAdr;
535	/** Size of the actual buffer (in bytes). */
536	uint32_t u32BufSize;
537	/** Bit 0: Interrupt on completion; the controller will generate
538	* an interrupt when the last byte of the buffer has been
539	* fetched by the DMA engine.
540	*
541	* Rest is reserved for further use and must be 0. */
542	uint32_t fFlags;
543	} HDABDLEDESC, *PHDABDLEDESC;
544	AssertCompileSize(HDABDLEDESC, 16); /* Always 16 byte. Also must be aligned on 128-byte boundary. */
545
546	/**
547	* Buffer Descriptor List Entry (BDLE) (3.6.3).
548	*/
549	typedef struct HDABDLE
550	{
551	/** The actual BDL description. */
552	HDABDLEDESC Desc;
553	/** Internal state of this BDLE.
554	* Not part of the actual BDLE registers. */
555	HDABDLESTATE State;
556	} HDABDLE, *PHDABDLE;
557
558	/** @name Object lookup functions.
559	* @{
560	*/
561	PDMAUDIODIR hdaGetDirFromSD(uint8_t uSD);
562	PHDASTREAM hdaGetStreamFromSD(PHDASTATE pThis, uint8_t uSD);
563	PHDASTREAM hdaGetStreamFromSink(PHDASTATE pThis, PHDAMIXERSINK pSink);
564	/** @} */
565
566	/** @name Interrupt functions.
567	* @{
568	*/
569	#ifdef DEBUG
570	int hdaProcessInterrupt(PHDASTATE pThis, const char *pszSource);
571	#else
572	int hdaProcessInterrupt(PHDASTATE pThis);
573	#endif
574	/** @} */
575
576	/** @name Wall clock (WALCLK) functions.
577	* @{
578	*/
579	uint64_t hdaWalClkGetCurrent(PHDASTATE pThis);
580	#ifdef IN_RING3
581	bool hdaWalClkSet(PHDASTATE pThis, uint64_t u64WalClk, bool fForce);
582	#endif
583	/** @} */
584
585	/** @name DMA utility functions.
586	* @{
587	*/
588	int hdaDMARead(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToRead, uint32_t *pcbRead);
589	int hdaDMAWrite(PHDASTATE pThis, PHDASTREAM pStream, uint32_t cbToWrite, uint32_t *pcbWritten);
590	/** @} */
591
592	/** @name Register functions.
593	* @{
594	*/
595	uint32_t hdaGetINTSTS(PHDASTATE pThis);
596	#ifdef IN_RING3
597	int hdaSDFMTToPCMProps(uint32_t u32SDFMT, PPDMAUDIOPCMPROPS pProps);
598	#endif /* IN_RING3 */
599	/** @} */
600
601	/** @name BDLE (Buffer Descriptor List Entry) functions.
602	* @{
603	*/
604	#ifdef IN_RING3
605	int hdaBDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry);
606	bool hdaBDLEIsComplete(PHDABDLE pBDLE);
607	bool hdaBDLENeedsInterrupt(PHDABDLE pBDLE);
608	#endif /* IN_RING3 */
609	/** @} */
610
611	#endif /* !DEV_HDA_H_COMMON */
612

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source: vbox/trunk/src/VBox/Devices/Audio/DevHDACommon.h@ 69833

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