VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevHDACommon.h@ 76077

Last change on this file since 76077 was 76049, checked in by vboxsync, 6 years ago

Audio/HDA: Implemented adaptive stream timer Hz rates, based on the stream's channel count.
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File size: 26.6 KB
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1/* $Id: DevHDACommon.h 76049 2018-12-07 10:51:32Z vboxsync $ */
2/** @file
3 * DevHDACommon.h - Shared HDA device defines / functions.
4 */
5
6/*
7 * Copyright (C) 2016-2018 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef DEV_HDA_COMMON_H
19#define DEV_HDA_COMMON_H
20
21#include "AudioMixer.h"
22#include <VBox/log.h> /* LOG_ENABLED */
23
24/** See 302349 p 6.2. */
25typedef struct HDAREGDESC
26{
27 /** Register offset in the register space. */
28 uint32_t offset;
29 /** Size in bytes. Registers of size > 4 are in fact tables. */
30 uint32_t size;
31 /** Readable bits. */
32 uint32_t readable;
33 /** Writable bits. */
34 uint32_t writable;
35 /** Register descriptor (RD) flags of type HDA_RD_FLAG_.
36 * These are used to specify the handling (read/write)
37 * policy of the register. */
38 uint32_t fFlags;
39 /** Read callback. */
40 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
41 /** Write callback. */
42 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
43 /** Index into the register storage array. */
44 uint32_t mem_idx;
45 /** Abbreviated name. */
46 const char *abbrev;
47 /** Descripton. */
48 const char *desc;
49} HDAREGDESC, *PHDAREGDESC;
50
51/**
52 * HDA register aliases (HDA spec 3.3.45).
53 * @remarks Sorted by offReg.
54 */
55typedef struct HDAREGALIAS
56{
57 /** The alias register offset. */
58 uint32_t offReg;
59 /** The register index. */
60 int idxAlias;
61} HDAREGALIAS, *PHDAREGALIAS;
62
63/**
64 * At the moment we support 4 input + 4 output streams max, which is 8 in total.
65 * Bidirectional streams are currently *not* supported.
66 *
67 * Note: When changing any of those values, be prepared for some saved state
68 * fixups / trouble!
69 */
70#define HDA_MAX_SDI 4
71#define HDA_MAX_SDO 4
72#define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
73AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
74
75/** Number of general registers. */
76#define HDA_NUM_GENERAL_REGS 34
77/** Number of total registers in the HDA's register map. */
78#define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */))
79/** Total number of stream tags (channels). Index 0 is reserved / invalid. */
80#define HDA_MAX_TAGS 16
81
82/**
83 * ICH6 datasheet defines limits for FIFOS registers (18.2.39).
84 * Formula: size - 1
85 * Other values not listed are not supported.
86 */
87/** Maximum FIFO size (in bytes). */
88#define HDA_FIFO_MAX 256
89
90/** Default timer frequency (in Hz).
91 *
92 * Lowering this value can ask for trouble, as backends then can run
93 * into data underruns.
94 *
95 * Note: For handling surround setups (e.g. 5.1 speaker setups) we need
96 * a higher Hz rate, as the device emulation otherwise will come into
97 * timing trouble, making the output (DMA reads) crackling. */
98#define HDA_TIMER_HZ_DEFAULT 100
99
100/** Default position adjustment (in audio samples).
101 *
102 * For snd_hda_intel (Linux guests), the first BDL entry always is being used as
103 * so-called BDL adjustment, which can vary, and is being used for chipsets which
104 * misbehave and/or are incorrectly implemented.
105 *
106 * The BDL adjustment entry *always* has the IOC (Interrupt on Completion) bit set.
107 *
108 * For Intel Baytrail / Braswell implementations the BDL default adjustment is 32 frames, whereas
109 * for ICH / PCH it's only one (1) frame.
110 *
111 * See default_bdl_pos_adj() and snd_hdac_stream_setup_periods() for more information.
112 *
113 * By default we apply some simple heuristics in hdaStreamInit().
114 */
115#define HDA_POS_ADJUST_DEFAULT 0
116
117/** HDA's (fixed) audio frame size in bytes.
118 * We only support 16-bit stereo frames at the moment. */
119#define HDA_FRAME_SIZE_DEFAULT 4
120
121/** Offset of the SD0 register map. */
122#define HDA_REG_DESC_SD0_BASE 0x80
123
124/** Turn a short global register name into an memory index and a stringized name. */
125#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
126
127/** Turns a short stream register name into an memory index and a stringized name. */
128#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
129
130/** Same as above for a register *not* stored in memory. */
131#define HDA_REG_IDX_NOMEM(abbrev) 0, #abbrev
132
133extern const HDAREGDESC g_aHdaRegMap[HDA_NUM_REGS];
134
135/**
136 * NB: Register values stored in memory (au32Regs[]) are indexed through
137 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
138 * register descriptors in g_aHdaRegMap[] are indexed through the
139 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
140 *
141 * The au32Regs[] layout is kept unchanged for saved state
142 * compatibility.
143 */
144
145/* Registers */
146#define HDA_REG_IND_NAME(x) HDA_REG_##x
147#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
148#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
149#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
150
151
152#define HDA_REG_GCAP 0 /* Range 0x00 - 0x01 */
153#define HDA_RMX_GCAP 0
154/**
155 * GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
156 *
157 * oss (15:12) - Number of output streams supported.
158 * iss (11:8) - Number of input streams supported.
159 * bss (7:3) - Number of bidirectional streams supported.
160 * bds (2:1) - Number of serial data out (SDO) signals supported.
161 * b64sup (0) - 64 bit addressing supported.
162 */
163#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
164 ( (((oss) & 0xF) << 12) \
165 | (((iss) & 0xF) << 8) \
166 | (((bss) & 0x1F) << 3) \
167 | (((bds) & 0x3) << 2) \
168 | ((b64sup) & 1))
169
170#define HDA_REG_VMIN 1 /* 0x02 */
171#define HDA_RMX_VMIN 1
172
173#define HDA_REG_VMAJ 2 /* 0x03 */
174#define HDA_RMX_VMAJ 2
175
176#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
177#define HDA_RMX_OUTPAY 3
178
179#define HDA_REG_INPAY 4 /* 0x06-0x07 */
180#define HDA_RMX_INPAY 4
181
182#define HDA_REG_GCTL 5 /* 0x08-0x0B */
183#define HDA_RMX_GCTL 5
184#define HDA_GCTL_UNSOL RT_BIT(8) /* Accept Unsolicited Response Enable */
185#define HDA_GCTL_FCNTRL RT_BIT(1) /* Flush Control */
186#define HDA_GCTL_CRST RT_BIT(0) /* Controller Reset */
187
188#define HDA_REG_WAKEEN 6 /* 0x0C */
189#define HDA_RMX_WAKEEN 6
190
191#define HDA_REG_STATESTS 7 /* 0x0E */
192#define HDA_RMX_STATESTS 7
193#define HDA_STATESTS_SCSF_MASK 0x7 /* State Change Status Flags (6.2.8). */
194
195#define HDA_REG_GSTS 8 /* 0x10-0x11*/
196#define HDA_RMX_GSTS 8
197#define HDA_GSTS_FSTS RT_BIT(1) /* Flush Status */
198
199#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
200#define HDA_RMX_OUTSTRMPAY 112
201
202#define HDA_REG_INSTRMPAY 10 /* 0x1a */
203#define HDA_RMX_INSTRMPAY 113
204
205#define HDA_REG_INTCTL 11 /* 0x20 */
206#define HDA_RMX_INTCTL 9
207#define HDA_INTCTL_GIE RT_BIT(31) /* Global Interrupt Enable */
208#define HDA_INTCTL_CIE RT_BIT(30) /* Controller Interrupt Enable */
209/** Bits 0-29 correspond to streams 0-29. */
210#define HDA_STRMINT_MASK 0xFF /* Streams 0-7 implemented. Applies to INTCTL and INTSTS. */
211
212#define HDA_REG_INTSTS 12 /* 0x24 */
213#define HDA_RMX_INTSTS 10
214#define HDA_INTSTS_GIS RT_BIT(31) /* Global Interrupt Status */
215#define HDA_INTSTS_CIS RT_BIT(30) /* Controller Interrupt Status */
216
217#define HDA_REG_WALCLK 13 /* 0x30 */
218/**NB: HDA_RMX_WALCLK is not defined because the register is not stored in memory. */
219
220/**
221 * Note: The HDA specification defines a SSYNC register at offset 0x38. The
222 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
223 * the datasheet.
224 */
225#define HDA_REG_SSYNC 14 /* 0x34 */
226#define HDA_RMX_SSYNC 12
227
228#define HDA_REG_CORBLBASE 15 /* 0x40 */
229#define HDA_RMX_CORBLBASE 13
230
231#define HDA_REG_CORBUBASE 16 /* 0x44 */
232#define HDA_RMX_CORBUBASE 14
233
234#define HDA_REG_CORBWP 17 /* 0x48 */
235#define HDA_RMX_CORBWP 15
236
237#define HDA_REG_CORBRP 18 /* 0x4A */
238#define HDA_RMX_CORBRP 16
239#define HDA_CORBRP_RST RT_BIT(15) /* CORB Read Pointer Reset */
240
241#define HDA_REG_CORBCTL 19 /* 0x4C */
242#define HDA_RMX_CORBCTL 17
243#define HDA_CORBCTL_DMA RT_BIT(1) /* Enable CORB DMA Engine */
244#define HDA_CORBCTL_CMEIE RT_BIT(0) /* CORB Memory Error Interrupt Enable */
245
246#define HDA_REG_CORBSTS 20 /* 0x4D */
247#define HDA_RMX_CORBSTS 18
248
249#define HDA_REG_CORBSIZE 21 /* 0x4E */
250#define HDA_RMX_CORBSIZE 19
251#define HDA_CORBSIZE_SZ_CAP 0xF0
252#define HDA_CORBSIZE_SZ 0x3
253
254/** Number of CORB buffer entries. */
255#define HDA_CORB_SIZE 256
256/** CORB element size (in bytes). */
257#define HDA_CORB_ELEMENT_SIZE 4
258/** Number of RIRB buffer entries. */
259#define HDA_RIRB_SIZE 256
260/** RIRB element size (in bytes). */
261#define HDA_RIRB_ELEMENT_SIZE 8
262
263#define HDA_REG_RIRBLBASE 22 /* 0x50 */
264#define HDA_RMX_RIRBLBASE 20
265
266#define HDA_REG_RIRBUBASE 23 /* 0x54 */
267#define HDA_RMX_RIRBUBASE 21
268
269#define HDA_REG_RIRBWP 24 /* 0x58 */
270#define HDA_RMX_RIRBWP 22
271#define HDA_RIRBWP_RST RT_BIT(15) /* RIRB Write Pointer Reset */
272
273#define HDA_REG_RINTCNT 25 /* 0x5A */
274#define HDA_RMX_RINTCNT 23
275
276/** Maximum number of Response Interrupts. */
277#define HDA_MAX_RINTCNT 256
278
279#define HDA_REG_RIRBCTL 26 /* 0x5C */
280#define HDA_RMX_RIRBCTL 24
281#define HDA_RIRBCTL_ROIC RT_BIT(2) /* Response Overrun Interrupt Control */
282#define HDA_RIRBCTL_RDMAEN RT_BIT(1) /* RIRB DMA Enable */
283#define HDA_RIRBCTL_RINTCTL RT_BIT(0) /* Response Interrupt Control */
284
285#define HDA_REG_RIRBSTS 27 /* 0x5D */
286#define HDA_RMX_RIRBSTS 25
287#define HDA_RIRBSTS_RIRBOIS RT_BIT(2) /* Response Overrun Interrupt Status */
288#define HDA_RIRBSTS_RINTFL RT_BIT(0) /* Response Interrupt Flag */
289
290#define HDA_REG_RIRBSIZE 28 /* 0x5E */
291#define HDA_RMX_RIRBSIZE 26
292
293#define HDA_REG_IC 29 /* 0x60 */
294#define HDA_RMX_IC 27
295
296#define HDA_REG_IR 30 /* 0x64 */
297#define HDA_RMX_IR 28
298
299#define HDA_REG_IRS 31 /* 0x68 */
300#define HDA_RMX_IRS 29
301#define HDA_IRS_IRV RT_BIT(1) /* Immediate Result Valid */
302#define HDA_IRS_ICB RT_BIT(0) /* Immediate Command Busy */
303
304#define HDA_REG_DPLBASE 32 /* 0x70 */
305#define HDA_RMX_DPLBASE 30
306
307#define HDA_REG_DPUBASE 33 /* 0x74 */
308#define HDA_RMX_DPUBASE 31
309
310#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
311
312#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
313#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
314/** Note: sdnum here _MUST_ be stream reg number [0,7]. */
315#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
316
317#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
318
319/** @todo Condense marcos! */
320
321#define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80; other streams offset by 0x20 */
322#define HDA_RMX_SD0CTL 32
323#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
324#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
325#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
326#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
327#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
328#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
329#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
330
331#define HDA_SDCTL_NUM_MASK 0xF
332#define HDA_SDCTL_NUM_SHIFT 20
333#define HDA_SDCTL_DIR RT_BIT(19) /* Direction (Bidirectional streams only!) */
334#define HDA_SDCTL_TP RT_BIT(18) /* Traffic Priority (PCI Express) */
335#define HDA_SDCTL_STRIPE_MASK 0x3
336#define HDA_SDCTL_STRIPE_SHIFT 16
337#define HDA_SDCTL_DEIE RT_BIT(4) /* Descriptor Error Interrupt Enable */
338#define HDA_SDCTL_FEIE RT_BIT(3) /* FIFO Error Interrupt Enable */
339#define HDA_SDCTL_IOCE RT_BIT(2) /* Interrupt On Completion Enable */
340#define HDA_SDCTL_RUN RT_BIT(1) /* Stream Run */
341#define HDA_SDCTL_SRST RT_BIT(0) /* Stream Reset */
342
343#define HDA_REG_SD0STS 35 /* 0x83; other streams offset by 0x20 */
344#define HDA_RMX_SD0STS 33
345#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
346#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
347#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
348#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
349#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
350#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
351#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
352
353#define HDA_SDSTS_FIFORDY RT_BIT(5) /* FIFO Ready */
354#define HDA_SDSTS_DESE RT_BIT(4) /* Descriptor Error */
355#define HDA_SDSTS_FIFOE RT_BIT(3) /* FIFO Error */
356#define HDA_SDSTS_BCIS RT_BIT(2) /* Buffer Completion Interrupt Status */
357
358#define HDA_REG_SD0LPIB 36 /* 0x84; other streams offset by 0x20 */
359#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
360#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
361#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
362#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
363#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
364#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
365#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
366#define HDA_RMX_SD0LPIB 34
367#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
368#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
369#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
370#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
371#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
372#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
373#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
374
375#define HDA_REG_SD0CBL 37 /* 0x88; other streams offset by 0x20 */
376#define HDA_RMX_SD0CBL 35
377#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
378#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
379#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
380#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
381#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
382#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
383#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
384
385#define HDA_REG_SD0LVI 38 /* 0x8C; other streams offset by 0x20 */
386#define HDA_RMX_SD0LVI 36
387#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
388#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
389#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
390#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
391#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
392#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
393#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
394
395#define HDA_REG_SD0FIFOW 39 /* 0x8E; other streams offset by 0x20 */
396#define HDA_RMX_SD0FIFOW 37
397#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
398#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
399#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
400#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
401#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
402#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
403#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
404
405/*
406 * ICH6 datasheet defined limits for FIFOW values (18.2.38).
407 */
408#define HDA_SDFIFOW_8B 0x2
409#define HDA_SDFIFOW_16B 0x3
410#define HDA_SDFIFOW_32B 0x4
411
412#define HDA_REG_SD0FIFOS 40 /* 0x90; other streams offset by 0x20 */
413#define HDA_RMX_SD0FIFOS 38
414#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
415#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
416#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
417#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
418#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
419#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
420#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
421
422#define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
423#define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
424
425#define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
426#define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
427#define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
428#define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
429#define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
430#define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
431
432#define HDA_REG_SD0FMT 41 /* 0x92; other streams offset by 0x20 */
433#define HDA_RMX_SD0FMT 39
434#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
435#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
436#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
437#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
438#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
439#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
440#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
441
442#define HDA_REG_SD0BDPL 42 /* 0x98; other streams offset by 0x20 */
443#define HDA_RMX_SD0BDPL 40
444#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
445#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
446#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
447#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
448#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
449#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
450#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
451
452#define HDA_REG_SD0BDPU 43 /* 0x9C; other streams offset by 0x20 */
453#define HDA_RMX_SD0BDPU 41
454#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
455#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
456#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
457#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
458#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
459#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
460#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
461
462#define HDA_CODEC_CAD_SHIFT 28
463/** Encodes the (required) LUN into a codec command. */
464#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
465
466#define HDA_SDFMT_NON_PCM_SHIFT 15
467#define HDA_SDFMT_NON_PCM_MASK 0x1
468#define HDA_SDFMT_BASE_RATE_SHIFT 14
469#define HDA_SDFMT_BASE_RATE_MASK 0x1
470#define HDA_SDFMT_MULT_SHIFT 11
471#define HDA_SDFMT_MULT_MASK 0x7
472#define HDA_SDFMT_DIV_SHIFT 8
473#define HDA_SDFMT_DIV_MASK 0x7
474#define HDA_SDFMT_BITS_SHIFT 4
475#define HDA_SDFMT_BITS_MASK 0x7
476#define HDA_SDFMT_CHANNELS_MASK 0xF
477
478#define HDA_SDFMT_TYPE RT_BIT(15)
479#define HDA_SDFMT_TYPE_PCM (0)
480#define HDA_SDFMT_TYPE_NON_PCM (1)
481
482#define HDA_SDFMT_BASE RT_BIT(14)
483#define HDA_SDFMT_BASE_48KHZ (0)
484#define HDA_SDFMT_BASE_44KHZ (1)
485
486#define HDA_SDFMT_MULT_1X (0)
487#define HDA_SDFMT_MULT_2X (1)
488#define HDA_SDFMT_MULT_3X (2)
489#define HDA_SDFMT_MULT_4X (3)
490
491#define HDA_SDFMT_DIV_1X (0)
492#define HDA_SDFMT_DIV_2X (1)
493#define HDA_SDFMT_DIV_3X (2)
494#define HDA_SDFMT_DIV_4X (3)
495#define HDA_SDFMT_DIV_5X (4)
496#define HDA_SDFMT_DIV_6X (5)
497#define HDA_SDFMT_DIV_7X (6)
498#define HDA_SDFMT_DIV_8X (7)
499
500#define HDA_SDFMT_8_BIT (0)
501#define HDA_SDFMT_16_BIT (1)
502#define HDA_SDFMT_20_BIT (2)
503#define HDA_SDFMT_24_BIT (3)
504#define HDA_SDFMT_32_BIT (4)
505
506#define HDA_SDFMT_CHAN_MONO (0)
507#define HDA_SDFMT_CHAN_STEREO (1)
508
509/** Emits a SDnFMT register format.
510 * Also being used in the codec's converter format. */
511#define HDA_SDFMT_MAKE(_afNonPCM, _aBaseRate, _aMult, _aDiv, _aBits, _aChan) \
512 ( (((_afNonPCM) & HDA_SDFMT_NON_PCM_MASK) << HDA_SDFMT_NON_PCM_SHIFT) \
513 | (((_aBaseRate) & HDA_SDFMT_BASE_RATE_MASK) << HDA_SDFMT_BASE_RATE_SHIFT) \
514 | (((_aMult) & HDA_SDFMT_MULT_MASK) << HDA_SDFMT_MULT_SHIFT) \
515 | (((_aDiv) & HDA_SDFMT_DIV_MASK) << HDA_SDFMT_DIV_SHIFT) \
516 | (((_aBits) & HDA_SDFMT_BITS_MASK) << HDA_SDFMT_BITS_SHIFT) \
517 | ( (_aChan) & HDA_SDFMT_CHANNELS_MASK))
518
519/** Interrupt on completion (IOC) flag. */
520#define HDA_BDLE_FLAG_IOC RT_BIT(0)
521
522
523
524/** The HDA controller. */
525typedef struct HDASTATE *PHDASTATE;
526/** The HDA stream. */
527typedef struct HDASTREAM *PHDASTREAM;
528
529typedef struct HDAMIXERSINK *PHDAMIXERSINK;
530
531
532/**
533 * Internal state of a Buffer Descriptor List Entry (BDLE),
534 * needed to keep track of the data needed for the actual device
535 * emulation.
536 */
537typedef struct HDABDLESTATE
538{
539 /** Own index within the BDL (Buffer Descriptor List). */
540 uint32_t u32BDLIndex;
541 /** Number of bytes below the stream's FIFO watermark (SDFIFOW).
542 * Used to check if we need fill up the FIFO again. */
543 uint32_t cbBelowFIFOW;
544 /** Current offset in DMA buffer (in bytes).*/
545 uint32_t u32BufOff;
546 uint32_t Padding;
547} HDABDLESTATE, *PHDABDLESTATE;
548
549/**
550 * BDL description structure.
551 * Do not touch this, as this must match to the HDA specs.
552 */
553typedef struct HDABDLEDESC
554{
555 /** Starting address of the actual buffer. Must be 128-bit aligned. */
556 uint64_t u64BufAddr;
557 /** Size of the actual buffer (in bytes). */
558 uint32_t u32BufSize;
559 /** Bit 0: Interrupt on completion; the controller will generate
560 * an interrupt when the last byte of the buffer has been
561 * fetched by the DMA engine.
562 *
563 * Rest is reserved for further use and must be 0. */
564 uint32_t fFlags;
565} HDABDLEDESC, *PHDABDLEDESC;
566AssertCompileSize(HDABDLEDESC, 16); /* Always 16 byte. Also must be aligned on 128-byte boundary. */
567
568/**
569 * Buffer Descriptor List Entry (BDLE) (3.6.3).
570 */
571typedef struct HDABDLE
572{
573 /** The actual BDL description. */
574 HDABDLEDESC Desc;
575 /** Internal state of this BDLE.
576 * Not part of the actual BDLE registers. */
577 HDABDLESTATE State;
578} HDABDLE;
579AssertCompileSizeAlignment(HDABDLE, 8);
580/** Pointer to a buffer descriptor list entry (BDLE). */
581typedef HDABDLE *PHDABDLE;
582
583/** @name Object lookup functions.
584 * @{
585 */
586#ifdef IN_RING3
587PHDAMIXERSINK hdaR3GetDefaultSink(PHDASTATE pThis, uint8_t uSD);
588#endif
589PDMAUDIODIR hdaGetDirFromSD(uint8_t uSD);
590PHDASTREAM hdaGetStreamFromSD(PHDASTATE pThis, uint8_t uSD);
591#ifdef IN_RING3
592PHDASTREAM hdaR3GetStreamFromSink(PHDASTATE pThis, PHDAMIXERSINK pSink);
593#endif
594/** @} */
595
596/** @name Interrupt functions.
597 * @{
598 */
599#ifdef LOG_ENABLED
600int hdaProcessInterrupt(PHDASTATE pThis, const char *pszSource);
601#else
602int hdaProcessInterrupt(PHDASTATE pThis);
603#endif
604/** @} */
605
606/** @name Wall clock (WALCLK) functions.
607 * @{
608 */
609uint64_t hdaWalClkGetCurrent(PHDASTATE pThis);
610#ifdef IN_RING3
611bool hdaR3WalClkSet(PHDASTATE pThis, uint64_t u64WalClk, bool fForce);
612#endif
613/** @} */
614
615/** @name DMA utility functions.
616 * @{
617 */
618#ifdef IN_RING3
619int hdaR3DMARead(PHDASTATE pThis, PHDASTREAM pStream, void *pvBuf, uint32_t cbBuf, uint32_t *pcbRead);
620int hdaR3DMAWrite(PHDASTATE pThis, PHDASTREAM pStream, const void *pvBuf, uint32_t cbBuf, uint32_t *pcbWritten);
621#endif
622/** @} */
623
624/** @name Register functions.
625 * @{
626 */
627uint32_t hdaGetINTSTS(PHDASTATE pThis);
628#ifdef IN_RING3
629int hdaR3SDFMTToPCMProps(uint16_t u16SDFMT, PPDMAUDIOPCMPROPS pProps);
630#endif /* IN_RING3 */
631/** @} */
632
633/** @name BDLE (Buffer Descriptor List Entry) functions.
634 * @{
635 */
636#ifdef IN_RING3
637# ifdef LOG_ENABLED
638void hdaR3BDLEDumpAll(PHDASTATE pThis, uint64_t u64BDLBase, uint16_t cBDLE);
639# endif
640int hdaR3BDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry);
641bool hdaR3BDLEIsComplete(PHDABDLE pBDLE);
642bool hdaR3BDLENeedsInterrupt(PHDABDLE pBDLE);
643#endif /* IN_RING3 */
644/** @} */
645
646/** @name Device timer functions.
647 * @{
648 */
649#ifdef IN_RING3
650bool hdaR3TimerSet(PHDASTATE pThis, PHDASTREAM pStream, uint64_t u64Expire, bool fForce);
651#endif /* IN_RING3 */
652/** @} */
653
654#endif /* !DEV_HDA_H_COMMON */
655
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