VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevHDACommon.h@ 78392

Last change on this file since 78392 was 76565, checked in by vboxsync, 6 years ago

Devices: Use VBOX_INCLUDED_SRC_ as header guard prefix with scm.
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1/* $Id: DevHDACommon.h 76565 2019-01-01 04:23:20Z vboxsync $ */
2/** @file
3 * DevHDACommon.h - Shared HDA device defines / functions.
4 */
5
6/*
7 * Copyright (C) 2016-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VBOX_INCLUDED_SRC_Audio_DevHDACommon_h
19#define VBOX_INCLUDED_SRC_Audio_DevHDACommon_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include "AudioMixer.h"
25#include <VBox/log.h> /* LOG_ENABLED */
26
27/** See 302349 p 6.2. */
28typedef struct HDAREGDESC
29{
30 /** Register offset in the register space. */
31 uint32_t offset;
32 /** Size in bytes. Registers of size > 4 are in fact tables. */
33 uint32_t size;
34 /** Readable bits. */
35 uint32_t readable;
36 /** Writable bits. */
37 uint32_t writable;
38 /** Register descriptor (RD) flags of type HDA_RD_FLAG_.
39 * These are used to specify the handling (read/write)
40 * policy of the register. */
41 uint32_t fFlags;
42 /** Read callback. */
43 int (*pfnRead)(PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
44 /** Write callback. */
45 int (*pfnWrite)(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
46 /** Index into the register storage array. */
47 uint32_t mem_idx;
48 /** Abbreviated name. */
49 const char *abbrev;
50 /** Descripton. */
51 const char *desc;
52} HDAREGDESC, *PHDAREGDESC;
53
54/**
55 * HDA register aliases (HDA spec 3.3.45).
56 * @remarks Sorted by offReg.
57 */
58typedef struct HDAREGALIAS
59{
60 /** The alias register offset. */
61 uint32_t offReg;
62 /** The register index. */
63 int idxAlias;
64} HDAREGALIAS, *PHDAREGALIAS;
65
66/**
67 * At the moment we support 4 input + 4 output streams max, which is 8 in total.
68 * Bidirectional streams are currently *not* supported.
69 *
70 * Note: When changing any of those values, be prepared for some saved state
71 * fixups / trouble!
72 */
73#define HDA_MAX_SDI 4
74#define HDA_MAX_SDO 4
75#define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
76AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
77
78/** Number of general registers. */
79#define HDA_NUM_GENERAL_REGS 34
80/** Number of total registers in the HDA's register map. */
81#define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */))
82/** Total number of stream tags (channels). Index 0 is reserved / invalid. */
83#define HDA_MAX_TAGS 16
84
85/**
86 * ICH6 datasheet defines limits for FIFOS registers (18.2.39).
87 * Formula: size - 1
88 * Other values not listed are not supported.
89 */
90/** Maximum FIFO size (in bytes). */
91#define HDA_FIFO_MAX 256
92
93/** Default timer frequency (in Hz).
94 *
95 * Lowering this value can ask for trouble, as backends then can run
96 * into data underruns.
97 *
98 * Note: For handling surround setups (e.g. 5.1 speaker setups) we need
99 * a higher Hz rate, as the device emulation otherwise will come into
100 * timing trouble, making the output (DMA reads) crackling. */
101#define HDA_TIMER_HZ_DEFAULT 100
102
103/** Default position adjustment (in audio samples).
104 *
105 * For snd_hda_intel (Linux guests), the first BDL entry always is being used as
106 * so-called BDL adjustment, which can vary, and is being used for chipsets which
107 * misbehave and/or are incorrectly implemented.
108 *
109 * The BDL adjustment entry *always* has the IOC (Interrupt on Completion) bit set.
110 *
111 * For Intel Baytrail / Braswell implementations the BDL default adjustment is 32 frames, whereas
112 * for ICH / PCH it's only one (1) frame.
113 *
114 * See default_bdl_pos_adj() and snd_hdac_stream_setup_periods() for more information.
115 *
116 * By default we apply some simple heuristics in hdaStreamInit().
117 */
118#define HDA_POS_ADJUST_DEFAULT 0
119
120/** HDA's (fixed) audio frame size in bytes.
121 * We only support 16-bit stereo frames at the moment. */
122#define HDA_FRAME_SIZE_DEFAULT 4
123
124/** Offset of the SD0 register map. */
125#define HDA_REG_DESC_SD0_BASE 0x80
126
127/** Turn a short global register name into an memory index and a stringized name. */
128#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
129
130/** Turns a short stream register name into an memory index and a stringized name. */
131#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
132
133/** Same as above for a register *not* stored in memory. */
134#define HDA_REG_IDX_NOMEM(abbrev) 0, #abbrev
135
136extern const HDAREGDESC g_aHdaRegMap[HDA_NUM_REGS];
137
138/**
139 * NB: Register values stored in memory (au32Regs[]) are indexed through
140 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
141 * register descriptors in g_aHdaRegMap[] are indexed through the
142 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
143 *
144 * The au32Regs[] layout is kept unchanged for saved state
145 * compatibility.
146 */
147
148/* Registers */
149#define HDA_REG_IND_NAME(x) HDA_REG_##x
150#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
151#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
152#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
153
154
155#define HDA_REG_GCAP 0 /* Range 0x00 - 0x01 */
156#define HDA_RMX_GCAP 0
157/**
158 * GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
159 *
160 * oss (15:12) - Number of output streams supported.
161 * iss (11:8) - Number of input streams supported.
162 * bss (7:3) - Number of bidirectional streams supported.
163 * bds (2:1) - Number of serial data out (SDO) signals supported.
164 * b64sup (0) - 64 bit addressing supported.
165 */
166#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
167 ( (((oss) & 0xF) << 12) \
168 | (((iss) & 0xF) << 8) \
169 | (((bss) & 0x1F) << 3) \
170 | (((bds) & 0x3) << 2) \
171 | ((b64sup) & 1))
172
173#define HDA_REG_VMIN 1 /* 0x02 */
174#define HDA_RMX_VMIN 1
175
176#define HDA_REG_VMAJ 2 /* 0x03 */
177#define HDA_RMX_VMAJ 2
178
179#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
180#define HDA_RMX_OUTPAY 3
181
182#define HDA_REG_INPAY 4 /* 0x06-0x07 */
183#define HDA_RMX_INPAY 4
184
185#define HDA_REG_GCTL 5 /* 0x08-0x0B */
186#define HDA_RMX_GCTL 5
187#define HDA_GCTL_UNSOL RT_BIT(8) /* Accept Unsolicited Response Enable */
188#define HDA_GCTL_FCNTRL RT_BIT(1) /* Flush Control */
189#define HDA_GCTL_CRST RT_BIT(0) /* Controller Reset */
190
191#define HDA_REG_WAKEEN 6 /* 0x0C */
192#define HDA_RMX_WAKEEN 6
193
194#define HDA_REG_STATESTS 7 /* 0x0E */
195#define HDA_RMX_STATESTS 7
196#define HDA_STATESTS_SCSF_MASK 0x7 /* State Change Status Flags (6.2.8). */
197
198#define HDA_REG_GSTS 8 /* 0x10-0x11*/
199#define HDA_RMX_GSTS 8
200#define HDA_GSTS_FSTS RT_BIT(1) /* Flush Status */
201
202#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
203#define HDA_RMX_OUTSTRMPAY 112
204
205#define HDA_REG_INSTRMPAY 10 /* 0x1a */
206#define HDA_RMX_INSTRMPAY 113
207
208#define HDA_REG_INTCTL 11 /* 0x20 */
209#define HDA_RMX_INTCTL 9
210#define HDA_INTCTL_GIE RT_BIT(31) /* Global Interrupt Enable */
211#define HDA_INTCTL_CIE RT_BIT(30) /* Controller Interrupt Enable */
212/** Bits 0-29 correspond to streams 0-29. */
213#define HDA_STRMINT_MASK 0xFF /* Streams 0-7 implemented. Applies to INTCTL and INTSTS. */
214
215#define HDA_REG_INTSTS 12 /* 0x24 */
216#define HDA_RMX_INTSTS 10
217#define HDA_INTSTS_GIS RT_BIT(31) /* Global Interrupt Status */
218#define HDA_INTSTS_CIS RT_BIT(30) /* Controller Interrupt Status */
219
220#define HDA_REG_WALCLK 13 /* 0x30 */
221/**NB: HDA_RMX_WALCLK is not defined because the register is not stored in memory. */
222
223/**
224 * Note: The HDA specification defines a SSYNC register at offset 0x38. The
225 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
226 * the datasheet.
227 */
228#define HDA_REG_SSYNC 14 /* 0x34 */
229#define HDA_RMX_SSYNC 12
230
231#define HDA_REG_CORBLBASE 15 /* 0x40 */
232#define HDA_RMX_CORBLBASE 13
233
234#define HDA_REG_CORBUBASE 16 /* 0x44 */
235#define HDA_RMX_CORBUBASE 14
236
237#define HDA_REG_CORBWP 17 /* 0x48 */
238#define HDA_RMX_CORBWP 15
239
240#define HDA_REG_CORBRP 18 /* 0x4A */
241#define HDA_RMX_CORBRP 16
242#define HDA_CORBRP_RST RT_BIT(15) /* CORB Read Pointer Reset */
243
244#define HDA_REG_CORBCTL 19 /* 0x4C */
245#define HDA_RMX_CORBCTL 17
246#define HDA_CORBCTL_DMA RT_BIT(1) /* Enable CORB DMA Engine */
247#define HDA_CORBCTL_CMEIE RT_BIT(0) /* CORB Memory Error Interrupt Enable */
248
249#define HDA_REG_CORBSTS 20 /* 0x4D */
250#define HDA_RMX_CORBSTS 18
251
252#define HDA_REG_CORBSIZE 21 /* 0x4E */
253#define HDA_RMX_CORBSIZE 19
254#define HDA_CORBSIZE_SZ_CAP 0xF0
255#define HDA_CORBSIZE_SZ 0x3
256
257/** Number of CORB buffer entries. */
258#define HDA_CORB_SIZE 256
259/** CORB element size (in bytes). */
260#define HDA_CORB_ELEMENT_SIZE 4
261/** Number of RIRB buffer entries. */
262#define HDA_RIRB_SIZE 256
263/** RIRB element size (in bytes). */
264#define HDA_RIRB_ELEMENT_SIZE 8
265
266#define HDA_REG_RIRBLBASE 22 /* 0x50 */
267#define HDA_RMX_RIRBLBASE 20
268
269#define HDA_REG_RIRBUBASE 23 /* 0x54 */
270#define HDA_RMX_RIRBUBASE 21
271
272#define HDA_REG_RIRBWP 24 /* 0x58 */
273#define HDA_RMX_RIRBWP 22
274#define HDA_RIRBWP_RST RT_BIT(15) /* RIRB Write Pointer Reset */
275
276#define HDA_REG_RINTCNT 25 /* 0x5A */
277#define HDA_RMX_RINTCNT 23
278
279/** Maximum number of Response Interrupts. */
280#define HDA_MAX_RINTCNT 256
281
282#define HDA_REG_RIRBCTL 26 /* 0x5C */
283#define HDA_RMX_RIRBCTL 24
284#define HDA_RIRBCTL_ROIC RT_BIT(2) /* Response Overrun Interrupt Control */
285#define HDA_RIRBCTL_RDMAEN RT_BIT(1) /* RIRB DMA Enable */
286#define HDA_RIRBCTL_RINTCTL RT_BIT(0) /* Response Interrupt Control */
287
288#define HDA_REG_RIRBSTS 27 /* 0x5D */
289#define HDA_RMX_RIRBSTS 25
290#define HDA_RIRBSTS_RIRBOIS RT_BIT(2) /* Response Overrun Interrupt Status */
291#define HDA_RIRBSTS_RINTFL RT_BIT(0) /* Response Interrupt Flag */
292
293#define HDA_REG_RIRBSIZE 28 /* 0x5E */
294#define HDA_RMX_RIRBSIZE 26
295
296#define HDA_REG_IC 29 /* 0x60 */
297#define HDA_RMX_IC 27
298
299#define HDA_REG_IR 30 /* 0x64 */
300#define HDA_RMX_IR 28
301
302#define HDA_REG_IRS 31 /* 0x68 */
303#define HDA_RMX_IRS 29
304#define HDA_IRS_IRV RT_BIT(1) /* Immediate Result Valid */
305#define HDA_IRS_ICB RT_BIT(0) /* Immediate Command Busy */
306
307#define HDA_REG_DPLBASE 32 /* 0x70 */
308#define HDA_RMX_DPLBASE 30
309
310#define HDA_REG_DPUBASE 33 /* 0x74 */
311#define HDA_RMX_DPUBASE 31
312
313#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
314
315#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
316#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
317/** Note: sdnum here _MUST_ be stream reg number [0,7]. */
318#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
319
320#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
321
322/** @todo Condense marcos! */
323
324#define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80; other streams offset by 0x20 */
325#define HDA_RMX_SD0CTL 32
326#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
327#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
328#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
329#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
330#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
331#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
332#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
333
334#define HDA_SDCTL_NUM_MASK 0xF
335#define HDA_SDCTL_NUM_SHIFT 20
336#define HDA_SDCTL_DIR RT_BIT(19) /* Direction (Bidirectional streams only!) */
337#define HDA_SDCTL_TP RT_BIT(18) /* Traffic Priority (PCI Express) */
338#define HDA_SDCTL_STRIPE_MASK 0x3
339#define HDA_SDCTL_STRIPE_SHIFT 16
340#define HDA_SDCTL_DEIE RT_BIT(4) /* Descriptor Error Interrupt Enable */
341#define HDA_SDCTL_FEIE RT_BIT(3) /* FIFO Error Interrupt Enable */
342#define HDA_SDCTL_IOCE RT_BIT(2) /* Interrupt On Completion Enable */
343#define HDA_SDCTL_RUN RT_BIT(1) /* Stream Run */
344#define HDA_SDCTL_SRST RT_BIT(0) /* Stream Reset */
345
346#define HDA_REG_SD0STS 35 /* 0x83; other streams offset by 0x20 */
347#define HDA_RMX_SD0STS 33
348#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
349#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
350#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
351#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
352#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
353#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
354#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
355
356#define HDA_SDSTS_FIFORDY RT_BIT(5) /* FIFO Ready */
357#define HDA_SDSTS_DESE RT_BIT(4) /* Descriptor Error */
358#define HDA_SDSTS_FIFOE RT_BIT(3) /* FIFO Error */
359#define HDA_SDSTS_BCIS RT_BIT(2) /* Buffer Completion Interrupt Status */
360
361#define HDA_REG_SD0LPIB 36 /* 0x84; other streams offset by 0x20 */
362#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
363#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
364#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
365#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
366#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
367#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
368#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
369#define HDA_RMX_SD0LPIB 34
370#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
371#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
372#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
373#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
374#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
375#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
376#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
377
378#define HDA_REG_SD0CBL 37 /* 0x88; other streams offset by 0x20 */
379#define HDA_RMX_SD0CBL 35
380#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
381#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
382#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
383#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
384#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
385#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
386#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
387
388#define HDA_REG_SD0LVI 38 /* 0x8C; other streams offset by 0x20 */
389#define HDA_RMX_SD0LVI 36
390#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
391#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
392#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
393#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
394#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
395#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
396#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
397
398#define HDA_REG_SD0FIFOW 39 /* 0x8E; other streams offset by 0x20 */
399#define HDA_RMX_SD0FIFOW 37
400#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
401#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
402#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
403#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
404#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
405#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
406#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
407
408/*
409 * ICH6 datasheet defined limits for FIFOW values (18.2.38).
410 */
411#define HDA_SDFIFOW_8B 0x2
412#define HDA_SDFIFOW_16B 0x3
413#define HDA_SDFIFOW_32B 0x4
414
415#define HDA_REG_SD0FIFOS 40 /* 0x90; other streams offset by 0x20 */
416#define HDA_RMX_SD0FIFOS 38
417#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
418#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
419#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
420#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
421#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
422#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
423#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
424
425#define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
426#define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
427
428#define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
429#define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
430#define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
431#define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
432#define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
433#define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
434
435#define HDA_REG_SD0FMT 41 /* 0x92; other streams offset by 0x20 */
436#define HDA_RMX_SD0FMT 39
437#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
438#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
439#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
440#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
441#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
442#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
443#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
444
445#define HDA_REG_SD0BDPL 42 /* 0x98; other streams offset by 0x20 */
446#define HDA_RMX_SD0BDPL 40
447#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
448#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
449#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
450#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
451#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
452#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
453#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
454
455#define HDA_REG_SD0BDPU 43 /* 0x9C; other streams offset by 0x20 */
456#define HDA_RMX_SD0BDPU 41
457#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
458#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
459#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
460#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
461#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
462#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
463#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
464
465#define HDA_CODEC_CAD_SHIFT 28
466/** Encodes the (required) LUN into a codec command. */
467#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
468
469#define HDA_SDFMT_NON_PCM_SHIFT 15
470#define HDA_SDFMT_NON_PCM_MASK 0x1
471#define HDA_SDFMT_BASE_RATE_SHIFT 14
472#define HDA_SDFMT_BASE_RATE_MASK 0x1
473#define HDA_SDFMT_MULT_SHIFT 11
474#define HDA_SDFMT_MULT_MASK 0x7
475#define HDA_SDFMT_DIV_SHIFT 8
476#define HDA_SDFMT_DIV_MASK 0x7
477#define HDA_SDFMT_BITS_SHIFT 4
478#define HDA_SDFMT_BITS_MASK 0x7
479#define HDA_SDFMT_CHANNELS_MASK 0xF
480
481#define HDA_SDFMT_TYPE RT_BIT(15)
482#define HDA_SDFMT_TYPE_PCM (0)
483#define HDA_SDFMT_TYPE_NON_PCM (1)
484
485#define HDA_SDFMT_BASE RT_BIT(14)
486#define HDA_SDFMT_BASE_48KHZ (0)
487#define HDA_SDFMT_BASE_44KHZ (1)
488
489#define HDA_SDFMT_MULT_1X (0)
490#define HDA_SDFMT_MULT_2X (1)
491#define HDA_SDFMT_MULT_3X (2)
492#define HDA_SDFMT_MULT_4X (3)
493
494#define HDA_SDFMT_DIV_1X (0)
495#define HDA_SDFMT_DIV_2X (1)
496#define HDA_SDFMT_DIV_3X (2)
497#define HDA_SDFMT_DIV_4X (3)
498#define HDA_SDFMT_DIV_5X (4)
499#define HDA_SDFMT_DIV_6X (5)
500#define HDA_SDFMT_DIV_7X (6)
501#define HDA_SDFMT_DIV_8X (7)
502
503#define HDA_SDFMT_8_BIT (0)
504#define HDA_SDFMT_16_BIT (1)
505#define HDA_SDFMT_20_BIT (2)
506#define HDA_SDFMT_24_BIT (3)
507#define HDA_SDFMT_32_BIT (4)
508
509#define HDA_SDFMT_CHAN_MONO (0)
510#define HDA_SDFMT_CHAN_STEREO (1)
511
512/** Emits a SDnFMT register format.
513 * Also being used in the codec's converter format. */
514#define HDA_SDFMT_MAKE(_afNonPCM, _aBaseRate, _aMult, _aDiv, _aBits, _aChan) \
515 ( (((_afNonPCM) & HDA_SDFMT_NON_PCM_MASK) << HDA_SDFMT_NON_PCM_SHIFT) \
516 | (((_aBaseRate) & HDA_SDFMT_BASE_RATE_MASK) << HDA_SDFMT_BASE_RATE_SHIFT) \
517 | (((_aMult) & HDA_SDFMT_MULT_MASK) << HDA_SDFMT_MULT_SHIFT) \
518 | (((_aDiv) & HDA_SDFMT_DIV_MASK) << HDA_SDFMT_DIV_SHIFT) \
519 | (((_aBits) & HDA_SDFMT_BITS_MASK) << HDA_SDFMT_BITS_SHIFT) \
520 | ( (_aChan) & HDA_SDFMT_CHANNELS_MASK))
521
522/** Interrupt on completion (IOC) flag. */
523#define HDA_BDLE_FLAG_IOC RT_BIT(0)
524
525
526
527/** The HDA controller. */
528typedef struct HDASTATE *PHDASTATE;
529/** The HDA stream. */
530typedef struct HDASTREAM *PHDASTREAM;
531
532typedef struct HDAMIXERSINK *PHDAMIXERSINK;
533
534
535/**
536 * Internal state of a Buffer Descriptor List Entry (BDLE),
537 * needed to keep track of the data needed for the actual device
538 * emulation.
539 */
540typedef struct HDABDLESTATE
541{
542 /** Own index within the BDL (Buffer Descriptor List). */
543 uint32_t u32BDLIndex;
544 /** Number of bytes below the stream's FIFO watermark (SDFIFOW).
545 * Used to check if we need fill up the FIFO again. */
546 uint32_t cbBelowFIFOW;
547 /** Current offset in DMA buffer (in bytes).*/
548 uint32_t u32BufOff;
549 uint32_t Padding;
550} HDABDLESTATE, *PHDABDLESTATE;
551
552/**
553 * BDL description structure.
554 * Do not touch this, as this must match to the HDA specs.
555 */
556typedef struct HDABDLEDESC
557{
558 /** Starting address of the actual buffer. Must be 128-bit aligned. */
559 uint64_t u64BufAddr;
560 /** Size of the actual buffer (in bytes). */
561 uint32_t u32BufSize;
562 /** Bit 0: Interrupt on completion; the controller will generate
563 * an interrupt when the last byte of the buffer has been
564 * fetched by the DMA engine.
565 *
566 * Rest is reserved for further use and must be 0. */
567 uint32_t fFlags;
568} HDABDLEDESC, *PHDABDLEDESC;
569AssertCompileSize(HDABDLEDESC, 16); /* Always 16 byte. Also must be aligned on 128-byte boundary. */
570
571/**
572 * Buffer Descriptor List Entry (BDLE) (3.6.3).
573 */
574typedef struct HDABDLE
575{
576 /** The actual BDL description. */
577 HDABDLEDESC Desc;
578 /** Internal state of this BDLE.
579 * Not part of the actual BDLE registers. */
580 HDABDLESTATE State;
581} HDABDLE;
582AssertCompileSizeAlignment(HDABDLE, 8);
583/** Pointer to a buffer descriptor list entry (BDLE). */
584typedef HDABDLE *PHDABDLE;
585
586/** @name Object lookup functions.
587 * @{
588 */
589#ifdef IN_RING3
590PHDAMIXERSINK hdaR3GetDefaultSink(PHDASTATE pThis, uint8_t uSD);
591#endif
592PDMAUDIODIR hdaGetDirFromSD(uint8_t uSD);
593PHDASTREAM hdaGetStreamFromSD(PHDASTATE pThis, uint8_t uSD);
594#ifdef IN_RING3
595PHDASTREAM hdaR3GetStreamFromSink(PHDASTATE pThis, PHDAMIXERSINK pSink);
596#endif
597/** @} */
598
599/** @name Interrupt functions.
600 * @{
601 */
602#ifdef LOG_ENABLED
603int hdaProcessInterrupt(PHDASTATE pThis, const char *pszSource);
604#else
605int hdaProcessInterrupt(PHDASTATE pThis);
606#endif
607/** @} */
608
609/** @name Wall clock (WALCLK) functions.
610 * @{
611 */
612uint64_t hdaWalClkGetCurrent(PHDASTATE pThis);
613#ifdef IN_RING3
614bool hdaR3WalClkSet(PHDASTATE pThis, uint64_t u64WalClk, bool fForce);
615#endif
616/** @} */
617
618/** @name DMA utility functions.
619 * @{
620 */
621#ifdef IN_RING3
622int hdaR3DMARead(PHDASTATE pThis, PHDASTREAM pStream, void *pvBuf, uint32_t cbBuf, uint32_t *pcbRead);
623int hdaR3DMAWrite(PHDASTATE pThis, PHDASTREAM pStream, const void *pvBuf, uint32_t cbBuf, uint32_t *pcbWritten);
624#endif
625/** @} */
626
627/** @name Register functions.
628 * @{
629 */
630uint32_t hdaGetINTSTS(PHDASTATE pThis);
631#ifdef IN_RING3
632int hdaR3SDFMTToPCMProps(uint16_t u16SDFMT, PPDMAUDIOPCMPROPS pProps);
633#endif /* IN_RING3 */
634/** @} */
635
636/** @name BDLE (Buffer Descriptor List Entry) functions.
637 * @{
638 */
639#ifdef IN_RING3
640# ifdef LOG_ENABLED
641void hdaR3BDLEDumpAll(PHDASTATE pThis, uint64_t u64BDLBase, uint16_t cBDLE);
642# endif
643int hdaR3BDLEFetch(PHDASTATE pThis, PHDABDLE pBDLE, uint64_t u64BaseDMA, uint16_t u16Entry);
644bool hdaR3BDLEIsComplete(PHDABDLE pBDLE);
645bool hdaR3BDLENeedsInterrupt(PHDABDLE pBDLE);
646#endif /* IN_RING3 */
647/** @} */
648
649/** @name Device timer functions.
650 * @{
651 */
652#ifdef IN_RING3
653bool hdaR3TimerSet(PHDASTATE pThis, PHDASTREAM pStream, uint64_t u64Expire, bool fForce);
654#endif /* IN_RING3 */
655/** @} */
656
657#endif /* !VBOX_INCLUDED_SRC_Audio_DevHDACommon_h */
658
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