DevHda.cpp@ 92030

Last change on this file since 92030 was 91687, checked in by vboxsync, 3 years ago
Audio: Fixed a small memory leak (driver description) in the driver attach logic of the HDA emulation and matched it to AC'97 and SB16. bugref:10008
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 219.9 KB

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1	/* $Id: DevHda.cpp 91687 2021-10-12 10:26:53Z vboxsync $ */
2	/** @file
3	* Intel HD Audio Controller Emulation.
4	*
5	* Implemented against the specifications found in "High Definition Audio
6	* Specification", Revision 1.0a June 17, 2010, and "Intel I/O Controller
7	* HUB 6 (ICH6) Family, Datasheet", document number 301473-002.
8	*/
9
10	/*
11	* Copyright (C) 2006-2020 Oracle Corporation
12	*
13	* This file is part of VirtualBox Open Source Edition (OSE), as
14	* available from http://www.virtualbox.org. This file is free software;
15	* you can redistribute it and/or modify it under the terms of the GNU
16	* General Public License (GPL) as published by the Free Software
17	* Foundation, in version 2 as it comes in the "COPYING" file of the
18	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20	*/
21
22
23	/*********************************************************************************************************************************
24	* Header Files *
25	*********************************************************************************************************************************/
26	#define LOG_GROUP LOG_GROUP_DEV_HDA
27	#include <VBox/log.h>
28
29	#include <VBox/vmm/pdmdev.h>
30	#include <VBox/vmm/pdmaudioifs.h>
31	#include <VBox/vmm/pdmaudioinline.h>
32	#ifdef HDA_DEBUG_GUEST_RIP
33	# include <VBox/vmm/cpum.h>
34	#endif
35	#include <VBox/version.h>
36	#include <VBox/AssertGuest.h>
37
38	#include <iprt/assert.h>
39	#include <iprt/asm.h>
40	#include <iprt/asm-math.h>
41	#include <iprt/file.h>
42	#include <iprt/list.h>
43	# include <iprt/string.h>
44	#ifdef IN_RING3
45	# include <iprt/mem.h>
46	# include <iprt/semaphore.h>
47	# include <iprt/uuid.h>
48	#endif
49
50	#include "VBoxDD.h"
51
52	#include "AudioMixBuffer.h"
53	#include "AudioMixer.h"
54
55	#define VBOX_HDA_CAN_ACCESS_REG_MAP /* g_aHdaRegMap is accessible */
56	#include "DevHda.h"
57
58	#include "AudioHlp.h"
59
60
61	/*********************************************************************************************************************************
62	* Defined Constants And Macros *
63	*********************************************************************************************************************************/
64	#if defined(VBOX_WITH_HP_HDA)
65	/* HP Pavilion dv4t-1300 */
66	# define HDA_PCI_VENDOR_ID 0x103c
67	# define HDA_PCI_DEVICE_ID 0x30f7
68	#elif defined(VBOX_WITH_INTEL_HDA)
69	/* Intel HDA controller */
70	# define HDA_PCI_VENDOR_ID 0x8086
71	# define HDA_PCI_DEVICE_ID 0x2668
72	#elif defined(VBOX_WITH_NVIDIA_HDA)
73	/* nVidia HDA controller */
74	# define HDA_PCI_VENDOR_ID 0x10de
75	# define HDA_PCI_DEVICE_ID 0x0ac0
76	#else
77	# error "Please specify your HDA device vendor/device IDs"
78	#endif
79
80	/**
81	* Acquires the HDA lock.
82	*/
83	#define DEVHDA_LOCK(a_pDevIns, a_pThis) \
84	do { \
85	int const rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
86	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV((a_pDevIns), &(a_pThis)->CritSect, rcLock); \
87	} while (0)
88
89	/**
90	* Acquires the HDA lock or returns.
91	*/
92	#define DEVHDA_LOCK_RETURN(a_pDevIns, a_pThis, a_rcBusy) \
93	do { \
94	int const rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, a_rcBusy); \
95	if (rcLock == VINF_SUCCESS) \
96	{ /* likely */ } \
97	else \
98	{ \
99	AssertRC(rcLock); \
100	return rcLock; \
101	} \
102	} while (0)
103
104	/**
105	* Acquires the HDA lock or returns.
106	*/
107	# define DEVHDA_LOCK_RETURN_VOID(a_pDevIns, a_pThis) \
108	do { \
109	int const rcLock = PDMDevHlpCritSectEnter((a_pDevIns), &(a_pThis)->CritSect, VERR_IGNORED); \
110	if (rcLock == VINF_SUCCESS) \
111	{ /* likely */ } \
112	else \
113	{ \
114	PDM_CRITSECT_RELEASE_ASSERT_RC_DEV((a_pDevIns), &(a_pThis)->CritSect, rcLock); \
115	return; \
116	} \
117	} while (0)
118
119	/**
120	* Releases the HDA lock.
121	*/
122	#define DEVHDA_UNLOCK(a_pDevIns, a_pThis) \
123	do { PDMDevHlpCritSectLeave((a_pDevIns), &(a_pThis)->CritSect); } while (0)
124
125	/**
126	* Acquires the TM lock and HDA lock, returns on failure.
127	*/
128	#define DEVHDA_LOCK_BOTH_RETURN(a_pDevIns, a_pThis, a_pStream, a_rcBusy) \
129	do { \
130	VBOXSTRICTRC rcLock = PDMDevHlpTimerLockClock2(pDevIns, (a_pStream)->hTimer, &(a_pThis)->CritSect, (a_rcBusy)); \
131	if (RT_LIKELY(rcLock == VINF_SUCCESS)) \
132	{ /* likely */ } \
133	else \
134	return VBOXSTRICTRC_TODO(rcLock); \
135	} while (0)
136
137
138	/*********************************************************************************************************************************
139	* Structures and Typedefs *
140	*********************************************************************************************************************************/
141
142	/**
143	* Structure defining a (host backend) driver stream.
144	* Each driver has its own instances of audio mixer streams, which then
145	* can go into the same (or even different) audio mixer sinks.
146	*/
147	typedef struct HDADRIVERSTREAM
148	{
149	/** Associated mixer handle. */
150	R3PTRTYPE(PAUDMIXSTREAM) pMixStrm;
151	} HDADRIVERSTREAM, *PHDADRIVERSTREAM;
152
153	/**
154	* Struct for maintaining a host backend driver.
155	* This driver must be associated to one, and only one,
156	* HDA codec. The HDA controller does the actual multiplexing
157	* of HDA codec data to various host backend drivers then.
158	*
159	* This HDA device uses a timer in order to synchronize all
160	* read/write accesses across all attached LUNs / backends.
161	*/
162	typedef struct HDADRIVER
163	{
164	/** Node for storing this driver in our device driver list of HDASTATE. */
165	RTLISTNODER3 Node;
166	/** Pointer to shared HDA device state. */
167	R3PTRTYPE(PHDASTATE) pHDAStateShared;
168	/** Pointer to the ring-3 HDA device state. */
169	R3PTRTYPE(PHDASTATER3) pHDAStateR3;
170	/** LUN to which this driver has been assigned. */
171	uint8_t uLUN;
172	/** Whether this driver is in an attached state or not. */
173	bool fAttached;
174	uint8_t u32Padding0[6];
175	/** Pointer to attached driver base interface. */
176	R3PTRTYPE(PPDMIBASE) pDrvBase;
177	/** Audio connector interface to the underlying host backend. */
178	R3PTRTYPE(PPDMIAUDIOCONNECTOR) pConnector;
179	/** Mixer stream for line input. */
180	HDADRIVERSTREAM LineIn;
181	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
182	/** Mixer stream for mic input. */
183	HDADRIVERSTREAM MicIn;
184	#endif
185	/** Mixer stream for front output. */
186	HDADRIVERSTREAM Front;
187	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
188	/** Mixer stream for center/LFE output. */
189	HDADRIVERSTREAM CenterLFE;
190	/** Mixer stream for rear output. */
191	HDADRIVERSTREAM Rear;
192	#endif
193	/** The LUN description. */
194	char szDesc[48 - 2];
195	} HDADRIVER;
196	/** The HDA host driver backend. */
197	typedef struct HDADRIVER *PHDADRIVER;
198
199
200	/** Internal state of this BDLE.
201	* Not part of the actual BDLE registers.
202	* @note Only for saved state. */
203	typedef struct HDABDLESTATELEGACY
204	{
205	/** Own index within the BDL (Buffer Descriptor List). */
206	uint32_t u32BDLIndex;
207	/** Number of bytes below the stream's FIFO watermark (SDFIFOW).
208	* Used to check if we need fill up the FIFO again. */
209	uint32_t cbBelowFIFOW;
210	/** Current offset in DMA buffer (in bytes).*/
211	uint32_t u32BufOff;
212	uint32_t Padding;
213	} HDABDLESTATELEGACY;
214
215	/**
216	* BDLE and state.
217	* @note Only for saved state.
218	*/
219	typedef struct HDABDLELEGACY
220	{
221	/** The actual BDL description. */
222	HDABDLEDESC Desc;
223	HDABDLESTATELEGACY State;
224	} HDABDLELEGACY;
225	AssertCompileSize(HDABDLELEGACY, 32);
226
227
228	/** Read callback. */
229	typedef VBOXSTRICTRC FNHDAREGREAD(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
230	/** Write callback. */
231	typedef VBOXSTRICTRC FNHDAREGWRITE(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
232
233	/**
234	* HDA register descriptor.
235	*/
236	typedef struct HDAREGDESC
237	{
238	/** Register offset in the register space. */
239	uint32_t off;
240	/** Size in bytes. Registers of size > 4 are in fact tables. */
241	uint8_t cb;
242	/** Register descriptor (RD) flags of type HDA_RD_F_XXX. These are used to
243	* specify the read/write handling policy of the register. */
244	uint8_t fFlags;
245	/** Index into the register storage array (HDASTATE::au32Regs). */
246	uint8_t idxReg;
247	uint8_t bUnused;
248	/** Readable bits. */
249	uint32_t fReadableMask;
250	/** Writable bits. */
251	uint32_t fWritableMask;
252	/** Read callback. */
253	FNHDAREGREAD *pfnRead;
254	/** Write callback. */
255	FNHDAREGWRITE *pfnWrite;
256	#if defined(IN_RING3) \|\| defined(LOG_ENABLED) /* Saves 0x2f23 - 0x1888 = 0x169B (5787) bytes in VBoxDDR0. */
257	/** Abbreviated name. */
258	const char *pszName;
259	# ifdef IN_RING3
260	/** Description (for stats). */
261	const char *pszDesc;
262	# endif
263	#endif
264	} HDAREGDESC;
265
266
267	/*********************************************************************************************************************************
268	* Internal Functions *
269	*********************************************************************************************************************************/
270	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
271	#ifdef IN_RING3
272	static void hdaR3GCTLReset(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC);
273	#endif
274
275	/** @name Register read/write stubs.
276	* @{
277	*/
278	static FNHDAREGREAD hdaRegReadUnimpl;
279	static FNHDAREGWRITE hdaRegWriteUnimpl;
280	/** @} */
281
282	/** @name Global register set read/write functions.
283	* @{
284	*/
285	static FNHDAREGWRITE hdaRegWriteGCTL;
286	static FNHDAREGREAD hdaRegReadLPIB;
287	static FNHDAREGREAD hdaRegReadWALCLK;
288	static FNHDAREGWRITE hdaRegWriteSSYNC;
289	static FNHDAREGWRITE hdaRegWriteNewSSYNC;
290	static FNHDAREGWRITE hdaRegWriteCORBWP;
291	static FNHDAREGWRITE hdaRegWriteCORBRP;
292	static FNHDAREGWRITE hdaRegWriteCORBCTL;
293	static FNHDAREGWRITE hdaRegWriteCORBSIZE;
294	static FNHDAREGWRITE hdaRegWriteCORBSTS;
295	static FNHDAREGWRITE hdaRegWriteRINTCNT;
296	static FNHDAREGWRITE hdaRegWriteRIRBWP;
297	static FNHDAREGWRITE hdaRegWriteRIRBSTS;
298	static FNHDAREGWRITE hdaRegWriteSTATESTS;
299	static FNHDAREGWRITE hdaRegWriteIRS;
300	static FNHDAREGREAD hdaRegReadIRS;
301	static FNHDAREGWRITE hdaRegWriteBase;
302	/** @} */
303
304	/** @name {IOB}SDn read/write functions.
305	* @{
306	*/
307	static FNHDAREGWRITE hdaRegWriteSDCBL;
308	static FNHDAREGWRITE hdaRegWriteSDCTL;
309	static FNHDAREGWRITE hdaRegWriteSDSTS;
310	static FNHDAREGWRITE hdaRegWriteSDLVI;
311	static FNHDAREGWRITE hdaRegWriteSDFIFOW;
312	static FNHDAREGWRITE hdaRegWriteSDFIFOS;
313	static FNHDAREGWRITE hdaRegWriteSDFMT;
314	static FNHDAREGWRITE hdaRegWriteSDBDPL;
315	static FNHDAREGWRITE hdaRegWriteSDBDPU;
316	static FNHDAREGREAD hdaRegReadSDnPIB;
317	static FNHDAREGREAD hdaRegReadSDnEFIFOS;
318	/** @} */
319
320	/** @name Generic register read/write functions.
321	* @{
322	*/
323	static FNHDAREGREAD hdaRegReadU32;
324	static FNHDAREGWRITE hdaRegWriteU32;
325	static FNHDAREGREAD hdaRegReadU24;
326	#ifdef IN_RING3
327	static FNHDAREGWRITE hdaRegWriteU24;
328	#endif
329	static FNHDAREGREAD hdaRegReadU16;
330	static FNHDAREGWRITE hdaRegWriteU16;
331	static FNHDAREGREAD hdaRegReadU8;
332	static FNHDAREGWRITE hdaRegWriteU8;
333	/** @} */
334
335	/** @name HDA device functions.
336	* @{
337	*/
338	#ifdef IN_RING3
339	static int hdaR3AddStream(PHDASTATER3 pThisCC, PPDMAUDIOSTREAMCFG pCfg);
340	static int hdaR3RemoveStream(PHDASTATER3 pThisCC, PPDMAUDIOSTREAMCFG pCfg);
341	#endif /* IN_RING3 */
342	/** @} */
343
344	/** @name HDA mixer functions.
345	* @{
346	*/
347	#ifdef IN_RING3
348	static int hdaR3MixerAddDrvStream(PPDMDEVINS pDevIns, PAUDMIXSINK pMixSink, PCPDMAUDIOSTREAMCFG pCfg, PHDADRIVER pDrv);
349	#endif
350	/** @} */
351
352	#ifdef IN_RING3
353	static FNSSMFIELDGETPUT hdaR3GetPutTrans_HDABDLEDESC_fFlags_6;
354	static FNSSMFIELDGETPUT hdaR3GetPutTrans_HDABDLE_Desc_fFlags_1thru4;
355	#endif
356
357
358	/*********************************************************************************************************************************
359	* Global Variables *
360	*********************************************************************************************************************************/
361	/** No register description (RD) flags defined. */
362	#define HDA_RD_F_NONE 0
363	/** Writes to SD are allowed while RUN bit is set. */
364	#define HDA_RD_F_SD_WRITE_RUN RT_BIT(0)
365
366	/** @def HDA_REG_ENTRY_EX
367	* Maps the entry values to the actual HDAREGDESC layout, which is differs
368	* depending on context and build type. */
369	#if defined(IN_RING3) \|\| defined(LOG_ENABLED)
370	# ifdef IN_RING3
371	# define HDA_REG_ENTRY_EX(a_offBar, a_cbReg, a_fReadMask, a_fWriteMask, a_fFlags, a_pfnRead, a_pfnWrite, a_idxMap, a_szName, a_szDesc) \
372	{ a_offBar, a_cbReg, a_fFlags, a_idxMap, 0, a_fReadMask, a_fWriteMask, a_pfnRead, a_pfnWrite, a_szName, a_szDesc }
373	# else
374	# define HDA_REG_ENTRY_EX(a_offBar, a_cbReg, a_fReadMask, a_fWriteMask, a_fFlags, a_pfnRead, a_pfnWrite, a_idxMap, a_szName, a_szDesc) \
375	{ a_offBar, a_cbReg, a_fFlags, a_idxMap, 0, a_fReadMask, a_fWriteMask, a_pfnRead, a_pfnWrite, a_szName }
376	# endif
377	#else
378	# define HDA_REG_ENTRY_EX(a_offBar, a_cbReg, a_fReadMask, a_fWriteMask, a_fFlags, a_pfnRead, a_pfnWrite, a_idxMap, a_szName, a_szDesc) \
379	{ a_offBar, a_cbReg, a_fFlags, a_idxMap, 0, a_fReadMask, a_fWriteMask, a_pfnRead, a_pfnWrite }
380	#endif
381
382	#define HDA_REG_ENTRY(a_offBar, a_cbReg, a_fReadMask, a_fWriteMask, a_fFlags, a_pfnRead, a_pfnWrite, a_ShortRegNm, a_szDesc) \
383	HDA_REG_ENTRY_EX(a_offBar, a_cbReg, a_fReadMask, a_fWriteMask, a_fFlags, a_pfnRead, a_pfnWrite, HDA_MEM_IND_NAME(a_ShortRegNm), #a_ShortRegNm, a_szDesc)
384	#define HDA_REG_ENTRY_STR(a_offBar, a_cbReg, a_fReadMask, a_fWriteMask, a_fFlags, a_pfnRead, a_pfnWrite, a_StrPrefix, a_ShortRegNm, a_szDesc) \
385	HDA_REG_ENTRY_EX(a_offBar, a_cbReg, a_fReadMask, a_fWriteMask, a_fFlags, a_pfnRead, a_pfnWrite, HDA_MEM_IND_NAME(a_StrPrefix ## a_ShortRegNm), #a_StrPrefix #a_ShortRegNm, #a_StrPrefix ": " a_szDesc)
386
387	/** Emits a single audio stream register set (e.g. OSD0) at a specified offset. */
388	#define HDA_REG_MAP_STRM(offset, name) \
389	/* offset size read mask write mask flags read callback write callback index, abbrev, description */ \
390	/* ------- ------- ---------- ---------- ---------------------- -------------- ----------------- ----------------------------- ----------- */ \
391	/* Offset 0x80 (SD0) */ \
392	HDA_REG_ENTRY_STR(offset, 0x00003, 0x00FF001F, 0x00F0001F, HDA_RD_F_SD_WRITE_RUN, hdaRegReadU24 , hdaRegWriteSDCTL , name, CTL , "Stream Descriptor Control"), \
393	/* Offset 0x83 (SD0) */ \
394	HDA_REG_ENTRY_STR(offset + 0x3, 0x00001, 0x0000003C, 0x0000001C, HDA_RD_F_SD_WRITE_RUN, hdaRegReadU8 , hdaRegWriteSDSTS , name, STS , "Status" ), \
395	/* Offset 0x84 (SD0) */ \
396	HDA_REG_ENTRY_STR(offset + 0x4, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadLPIB, hdaRegWriteU32 , name, LPIB , "Link Position In Buffer" ), \
397	/* Offset 0x88 (SD0) */ \
398	HDA_REG_ENTRY_STR(offset + 0x8, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteSDCBL , name, CBL , "Cyclic Buffer Length" ), \
399	/* Offset 0x8C (SD0) -- upper 8 bits are reserved */ \
400	HDA_REG_ENTRY_STR(offset + 0xC, 0x00002, 0x0000FFFF, 0x000000FF, HDA_RD_F_NONE, hdaRegReadU16 , hdaRegWriteSDLVI , name, LVI , "Last Valid Index" ), \
401	/* Reserved: FIFO Watermark. ** @todo Document this! */ \
402	HDA_REG_ENTRY_STR(offset + 0xE, 0x00002, 0x00000007, 0x00000007, HDA_RD_F_NONE, hdaRegReadU16 , hdaRegWriteSDFIFOW, name, FIFOW, "FIFO Watermark" ), \
403	/* Offset 0x90 (SD0) */ \
404	HDA_REG_ENTRY_STR(offset + 0x10, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_F_NONE, hdaRegReadU16 , hdaRegWriteSDFIFOS, name, FIFOS, "FIFO Size" ), \
405	/* Offset 0x92 (SD0) */ \
406	HDA_REG_ENTRY_STR(offset + 0x12, 0x00002, 0x00007F7F, 0x00007F7F, HDA_RD_F_NONE, hdaRegReadU16 , hdaRegWriteSDFMT , name, FMT , "Stream Format" ), \
407	/* Reserved: 0x94 - 0x98. */ \
408	/* Offset 0x98 (SD0) */ \
409	HDA_REG_ENTRY_STR(offset + 0x18, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteSDBDPL , name, BDPL , "Buffer Descriptor List Pointer-Lower Base Address" ), \
410	/* Offset 0x9C (SD0) */ \
411	HDA_REG_ENTRY_STR(offset + 0x1C, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteSDBDPU , name, BDPU , "Buffer Descriptor List Pointer-Upper Base Address" )
412
413	/** Defines a single audio stream register set (e.g. OSD0). */
414	#define HDA_REG_MAP_DEF_STREAM(index, name) \
415	HDA_REG_MAP_STRM(HDA_REG_DESC_SD0_BASE + (index * 32 /* 0x20 */), name)
416
417	/** Skylake stream registers. */
418	#define HDA_REG_MAP_SKYLAKE_STRM(a_off, a_StrPrefix) \
419	/* offset size read mask write mask flags read callback write callback index, abbrev, description */ \
420	/* ------- ------- ---------- ---------- -------------- -------------- ----------------- ----------------------------- ----------- */ \
421	/* 0x1084 */ \
422	HDA_REG_ENTRY_STR(a_off + 0x04, 0x00004, 0xffffffff, 0x00000000, HDA_RD_F_NONE, hdaRegReadSDnPIB, hdaRegWriteUnimpl, a_StrPrefix, DPIB, "DMA Position In Buffer" ), \
423	/* 0x1094 */ \
424	HDA_REG_ENTRY_STR(a_off + 0x14, 0x00004, 0xffffffff, 0x00000000, HDA_RD_F_NONE, hdaRegReadSDnEFIFOS, hdaRegWriteUnimpl, a_StrPrefix, EFIFOS, "Extended FIFO Size" )
425
426
427	/** See 302349 p 6.2. */
428	static const HDAREGDESC g_aHdaRegMap[HDA_NUM_REGS] =
429	{
430	/* offset size read mask write mask flags read callback write callback index + abbrev */
431	/------- ------- ---------- ---------- -------------- ---------------- ------------------- ------------------------ /
432	HDA_REG_ENTRY(0x00000, 0x00002, 0x0000FFFB, 0x00000000, HDA_RD_F_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , GCAP, "Global Capabilities" ),
433	HDA_REG_ENTRY(0x00002, 0x00001, 0x000000FF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , VMIN, "Minor Version" ),
434	HDA_REG_ENTRY(0x00003, 0x00001, 0x000000FF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , VMAJ, "Major Version" ),
435	HDA_REG_ENTRY(0x00004, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU16 , hdaRegWriteU16 , OUTPAY, "Output Payload Capabilities" ),
436	HDA_REG_ENTRY(0x00006, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , INPAY, "Input Payload Capabilities" ),
437	HDA_REG_ENTRY(0x00008, 0x00004, 0x00000103, 0x00000103, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteGCTL , GCTL, "Global Control" ),
438	HDA_REG_ENTRY(0x0000c, 0x00002, 0x00007FFF, 0x00007FFF, HDA_RD_F_NONE, hdaRegReadU16 , hdaRegWriteU16 , WAKEEN, "Wake Enable" ),
439	HDA_REG_ENTRY(0x0000e, 0x00002, 0x00000007, 0x00000007, HDA_RD_F_NONE, hdaRegReadU8 , hdaRegWriteSTATESTS, STATESTS, "State Change Status" ),
440	HDA_REG_ENTRY(0x00010, 0x00002, 0xFFFFFFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadUnimpl, hdaRegWriteUnimpl , GSTS, "Global Status" ),
441	HDA_REG_ENTRY(0x00014, 0x00002, 0xFFFFFFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , LLCH, "Linked List Capabilities Header" ),
442	HDA_REG_ENTRY(0x00018, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU16 , hdaRegWriteU16 , OUTSTRMPAY, "Output Stream Payload Capability" ),
443	HDA_REG_ENTRY(0x0001A, 0x00002, 0x0000FFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU16 , hdaRegWriteUnimpl , INSTRMPAY, "Input Stream Payload Capability" ),
444	HDA_REG_ENTRY(0x00020, 0x00004, 0xC00000FF, 0xC00000FF, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteU32 , INTCTL, "Interrupt Control" ),
445	HDA_REG_ENTRY(0x00024, 0x00004, 0xC00000FF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , INTSTS, "Interrupt Status" ),
446	HDA_REG_ENTRY_EX(0x00030, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadWALCLK, hdaRegWriteUnimpl , 0, "WALCLK", "Wall Clock Counter" ),
447	HDA_REG_ENTRY(0x00034, 0x00004, 0x000000FF, 0x000000FF, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteSSYNC , SSYNC, "Stream Synchronization (old)" ),
448	HDA_REG_ENTRY(0x00038, 0x00004, 0x000000FF, 0x000000FF, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteNewSSYNC, SSYNC, "Stream Synchronization (new)" ),
449	HDA_REG_ENTRY(0x00040, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteBase , CORBLBASE, "CORB Lower Base Address" ),
450	HDA_REG_ENTRY(0x00044, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteBase , CORBUBASE, "CORB Upper Base Address" ),
451	HDA_REG_ENTRY(0x00048, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_F_NONE, hdaRegReadU16 , hdaRegWriteCORBWP , CORBWP, "CORB Write Pointer" ),
452	HDA_REG_ENTRY(0x0004A, 0x00002, 0x000080FF, 0x00008000, HDA_RD_F_NONE, hdaRegReadU16 , hdaRegWriteCORBRP , CORBRP, "CORB Read Pointer" ),
453	HDA_REG_ENTRY(0x0004C, 0x00001, 0x00000003, 0x00000003, HDA_RD_F_NONE, hdaRegReadU8 , hdaRegWriteCORBCTL , CORBCTL, "CORB Control" ),
454	HDA_REG_ENTRY(0x0004D, 0x00001, 0x00000001, 0x00000001, HDA_RD_F_NONE, hdaRegReadU8 , hdaRegWriteCORBSTS , CORBSTS, "CORB Status" ),
455	HDA_REG_ENTRY(0x0004E, 0x00001, 0x000000F3, 0x00000003, HDA_RD_F_NONE, hdaRegReadU8 , hdaRegWriteCORBSIZE, CORBSIZE, "CORB Size" ),
456	HDA_REG_ENTRY(0x00050, 0x00004, 0xFFFFFF80, 0xFFFFFF80, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteBase , RIRBLBASE, "RIRB Lower Base Address" ),
457	HDA_REG_ENTRY(0x00054, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteBase , RIRBUBASE, "RIRB Upper Base Address" ),
458	HDA_REG_ENTRY(0x00058, 0x00002, 0x000000FF, 0x00008000, HDA_RD_F_NONE, hdaRegReadU8 , hdaRegWriteRIRBWP , RIRBWP, "RIRB Write Pointer" ),
459	HDA_REG_ENTRY(0x0005A, 0x00002, 0x000000FF, 0x000000FF, HDA_RD_F_NONE, hdaRegReadU16 , hdaRegWriteRINTCNT , RINTCNT, "Response Interrupt Count" ),
460	HDA_REG_ENTRY(0x0005C, 0x00001, 0x00000007, 0x00000007, HDA_RD_F_NONE, hdaRegReadU8 , hdaRegWriteU8 , RIRBCTL, "RIRB Control" ),
461	HDA_REG_ENTRY(0x0005D, 0x00001, 0x00000005, 0x00000005, HDA_RD_F_NONE, hdaRegReadU8 , hdaRegWriteRIRBSTS , RIRBSTS, "RIRB Status" ),
462	HDA_REG_ENTRY(0x0005E, 0x00001, 0x000000F3, 0x00000000, HDA_RD_F_NONE, hdaRegReadU8 , hdaRegWriteUnimpl , RIRBSIZE, "RIRB Size" ),
463	HDA_REG_ENTRY(0x00060, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteU32 , IC, "Immediate Command" ),
464	HDA_REG_ENTRY(0x00064, 0x00004, 0x00000000, 0xFFFFFFFF, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , IR, "Immediate Response" ),
465	HDA_REG_ENTRY(0x00068, 0x00002, 0x00000002, 0x00000002, HDA_RD_F_NONE, hdaRegReadIRS , hdaRegWriteIRS , IRS, "Immediate Command Status" ),
466	HDA_REG_ENTRY(0x00070, 0x00004, 0xFFFFFFFF, 0xFFFFFF81, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteBase , DPLBASE, "DMA Position Lower Base" ),
467	HDA_REG_ENTRY(0x00074, 0x00004, 0xFFFFFFFF, 0xFFFFFFFF, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteBase , DPUBASE, "DMA Position Upper Base" ),
468	/* 4 Serial Data In (SDI). */
469	HDA_REG_MAP_DEF_STREAM(0, SD0),
470	HDA_REG_MAP_DEF_STREAM(1, SD1),
471	HDA_REG_MAP_DEF_STREAM(2, SD2),
472	HDA_REG_MAP_DEF_STREAM(3, SD3),
473	/* 4 Serial Data Out (SDO). */
474	HDA_REG_MAP_DEF_STREAM(4, SD4),
475	HDA_REG_MAP_DEF_STREAM(5, SD5),
476	HDA_REG_MAP_DEF_STREAM(6, SD6),
477	HDA_REG_MAP_DEF_STREAM(7, SD7),
478	HDA_REG_ENTRY(0x00c00, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , MLCH, "Multiple Links Capability Header" ),
479	HDA_REG_ENTRY(0x00c04, 0x00004, 0xFFFFFFFF, 0x00000000, HDA_RD_F_NONE, hdaRegReadU32 , hdaRegWriteUnimpl , MLCD, "Multiple Links Capability Declaration" ),
480	HDA_REG_MAP_SKYLAKE_STRM(0x01080, SD0),
481	HDA_REG_MAP_SKYLAKE_STRM(0x010a0, SD1),
482	HDA_REG_MAP_SKYLAKE_STRM(0x010c0, SD2),
483	HDA_REG_MAP_SKYLAKE_STRM(0x010e0, SD3),
484	HDA_REG_MAP_SKYLAKE_STRM(0x01100, SD4),
485	HDA_REG_MAP_SKYLAKE_STRM(0x01120, SD5),
486	HDA_REG_MAP_SKYLAKE_STRM(0x01140, SD6),
487	HDA_REG_MAP_SKYLAKE_STRM(0x01160, SD7),
488	};
489
490	#undef HDA_REG_ENTRY_EX
491	#undef HDA_REG_ENTRY
492	#undef HDA_REG_ENTRY_STR
493	#undef HDA_REG_MAP_STRM
494	#undef HDA_REG_MAP_DEF_STREAM
495
496	/**
497	* HDA register aliases (HDA spec 3.3.45).
498	* @remarks Sorted by offReg.
499	* @remarks Lookup code ASSUMES this starts somewhere after g_aHdaRegMap ends.
500	*/
501	static struct HDAREGALIAS
502	{
503	/** The alias register offset. */
504	uint32_t offReg;
505	/** The register index. */
506	int idxAlias;
507	} const g_aHdaRegAliases[] =
508	{
509	{ 0x2030, HDA_REG_WALCLK },
510	{ 0x2084, HDA_REG_SD0LPIB },
511	{ 0x20a4, HDA_REG_SD1LPIB },
512	{ 0x20c4, HDA_REG_SD2LPIB },
513	{ 0x20e4, HDA_REG_SD3LPIB },
514	{ 0x2104, HDA_REG_SD4LPIB },
515	{ 0x2124, HDA_REG_SD5LPIB },
516	{ 0x2144, HDA_REG_SD6LPIB },
517	{ 0x2164, HDA_REG_SD7LPIB }
518	};
519
520	#ifdef IN_RING3
521
522	/** HDABDLEDESC field descriptors for the v7+ saved state. */
523	static SSMFIELD const g_aSSMBDLEDescFields7[] =
524	{
525	SSMFIELD_ENTRY(HDABDLEDESC, u64BufAddr),
526	SSMFIELD_ENTRY(HDABDLEDESC, u32BufSize),
527	SSMFIELD_ENTRY(HDABDLEDESC, fFlags),
528	SSMFIELD_ENTRY_TERM()
529	};
530
531	/** HDABDLEDESC field descriptors for the v6 saved states. */
532	static SSMFIELD const g_aSSMBDLEDescFields6[] =
533	{
534	SSMFIELD_ENTRY(HDABDLEDESC, u64BufAddr),
535	SSMFIELD_ENTRY(HDABDLEDESC, u32BufSize),
536	SSMFIELD_ENTRY_CALLBACK(HDABDLEDESC, fFlags, hdaR3GetPutTrans_HDABDLEDESC_fFlags_6),
537	SSMFIELD_ENTRY_TERM()
538	};
539
540	/** HDABDLESTATE field descriptors for the v6 saved state. */
541	static SSMFIELD const g_aSSMBDLEStateFields6[] =
542	{
543	SSMFIELD_ENTRY(HDABDLESTATELEGACY, u32BDLIndex),
544	SSMFIELD_ENTRY(HDABDLESTATELEGACY, cbBelowFIFOW),
545	SSMFIELD_ENTRY_OLD(FIFO, 256), /* Deprecated; now is handled in the stream's circular buffer. */
546	SSMFIELD_ENTRY(HDABDLESTATELEGACY, u32BufOff),
547	SSMFIELD_ENTRY_TERM()
548	};
549
550	/** HDABDLESTATE field descriptors for the v7+ saved state. */
551	static SSMFIELD const g_aSSMBDLEStateFields7[] =
552	{
553	SSMFIELD_ENTRY(HDABDLESTATELEGACY, u32BDLIndex),
554	SSMFIELD_ENTRY(HDABDLESTATELEGACY, cbBelowFIFOW),
555	SSMFIELD_ENTRY(HDABDLESTATELEGACY, u32BufOff),
556	SSMFIELD_ENTRY_TERM()
557	};
558
559	/** HDASTREAMSTATE field descriptors for the v6 saved state. */
560	static SSMFIELD const g_aSSMStreamStateFields6[] =
561	{
562	SSMFIELD_ENTRY_OLD(cBDLE, sizeof(uint16_t)), /* Deprecated. */
563	SSMFIELD_ENTRY_OLD(uCurBDLE, sizeof(uint16_t)), /* We figure it out from LPID */
564	SSMFIELD_ENTRY_OLD(fStop, 1), /* Deprecated; see SSMR3PutBool(). */
565	SSMFIELD_ENTRY_OLD(fRunning, 1), /* Deprecated; using the HDA_SDCTL_RUN bit is sufficient. */
566	SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
567	SSMFIELD_ENTRY_TERM()
568	};
569
570	/** HDASTREAMSTATE field descriptors for the v7+ saved state. */
571	static SSMFIELD const g_aSSMStreamStateFields7[] =
572	{
573	SSMFIELD_ENTRY(HDASTREAMSTATE, idxCurBdle), /* For backward compatibility we save this. We use LPIB on restore. */
574	SSMFIELD_ENTRY_OLD(uCurBDLEHi, sizeof(uint8_t)), /* uCurBDLE was 16-bit for some reason, so store/ignore the zero top byte. */
575	SSMFIELD_ENTRY(HDASTREAMSTATE, fInReset),
576	SSMFIELD_ENTRY(HDASTREAMSTATE, tsTransferNext),
577	SSMFIELD_ENTRY_TERM()
578	};
579
580	/** HDABDLE field descriptors for the v1 thru v4 saved states. */
581	static SSMFIELD const g_aSSMStreamBdleFields1234[] =
582	{
583	SSMFIELD_ENTRY(HDABDLELEGACY, Desc.u64BufAddr), /* u64BdleCviAddr */
584	SSMFIELD_ENTRY_OLD(u32BdleMaxCvi, sizeof(uint32_t)), /* u32BdleMaxCvi */
585	SSMFIELD_ENTRY(HDABDLELEGACY, State.u32BDLIndex), /* u32BdleCvi */
586	SSMFIELD_ENTRY(HDABDLELEGACY, Desc.u32BufSize), /* u32BdleCviLen */
587	SSMFIELD_ENTRY(HDABDLELEGACY, State.u32BufOff), /* u32BdleCviPos */
588	SSMFIELD_ENTRY_CALLBACK(HDABDLELEGACY, Desc.fFlags, hdaR3GetPutTrans_HDABDLE_Desc_fFlags_1thru4), /* fBdleCviIoc */
589	SSMFIELD_ENTRY(HDABDLELEGACY, State.cbBelowFIFOW), /* cbUnderFifoW */
590	SSMFIELD_ENTRY_OLD(au8FIFO, 256), /* au8FIFO */
591	SSMFIELD_ENTRY_TERM()
592	};
593
594	#endif /* IN_RING3 */
595
596	/**
597	* 32-bit size indexed masks, i.e. g_afMasks[2 bytes] = 0xffff.
598	*/
599	static uint32_t const g_afMasks[5] =
600	{
601	UINT32_C(0), UINT32_C(0x000000ff), UINT32_C(0x0000ffff), UINT32_C(0x00ffffff), UINT32_C(0xffffffff)
602	};
603
604
605	#ifdef VBOX_STRICT
606
607	/**
608	* Strict register accessor verifing defines and mapping table.
609	* @see HDA_REG
610	*/
611	DECLINLINE(uint32_t *) hdaStrictRegAccessor(PHDASTATE pThis, uint32_t idxMap, uint32_t idxReg)
612	{
613	Assert(idxMap < RT_ELEMENTS(g_aHdaRegMap));
614	AssertMsg(idxReg == g_aHdaRegMap[idxMap].idxReg, ("idxReg=%d\n", idxReg));
615	return &pThis->au32Regs[idxReg];
616	}
617
618	/**
619	* Strict stream register accessor verifing defines and mapping table.
620	* @see HDA_STREAM_REG
621	*/
622	DECLINLINE(uint32_t *) hdaStrictStreamRegAccessor(PHDASTATE pThis, uint32_t idxMap0, uint32_t idxReg0, size_t idxStream)
623	{
624	Assert(idxMap0 < RT_ELEMENTS(g_aHdaRegMap));
625	AssertMsg(idxStream < RT_ELEMENTS(pThis->aStreams), ("%#zx\n", idxStream));
626	AssertMsg(idxReg0 + idxStream * 10 == g_aHdaRegMap[idxMap0 + idxStream * 10].idxReg,
627	("idxReg0=%d idxStream=%zx\n", idxReg0, idxStream));
628	return &pThis->au32Regs[idxReg0 + idxStream * 10];
629	}
630
631	#endif /* VBOX_STRICT */
632
633
634	/**
635	* Returns a new INTSTS value based on the current device state.
636	*
637	* @returns Determined INTSTS register value.
638	* @param pThis The shared HDA device state.
639	*
640	* @remarks This function does not set INTSTS!
641	*/
642	static uint32_t hdaGetINTSTS(PHDASTATE pThis)
643	{
644	uint32_t intSts = 0;
645
646	/* Check controller interrupts (RIRB, STATEST). */
647	if (HDA_REG(pThis, RIRBSTS) & HDA_REG(pThis, RIRBCTL) & (HDA_RIRBCTL_ROIC \| HDA_RIRBCTL_RINTCTL))
648	{
649	intSts \|= HDA_INTSTS_CIS; /* Set the Controller Interrupt Status (CIS). */
650	}
651
652	/* Check SDIN State Change Status Flags. */
653	if (HDA_REG(pThis, STATESTS) & HDA_REG(pThis, WAKEEN))
654	{
655	intSts \|= HDA_INTSTS_CIS; /* Touch Controller Interrupt Status (CIS). */
656	}
657
658	/* For each stream, check if any interrupt status bit is set and enabled. */
659	for (uint8_t iStrm = 0; iStrm < HDA_MAX_STREAMS; ++iStrm)
660	{
661	if (HDA_STREAM_REG(pThis, STS, iStrm) & HDA_STREAM_REG(pThis, CTL, iStrm) & (HDA_SDCTL_DEIE \| HDA_SDCTL_FEIE \| HDA_SDCTL_IOCE))
662	{
663	Log3Func(("[SD%d] interrupt status set\n", iStrm));
664	intSts \|= RT_BIT(iStrm);
665	}
666	}
667
668	if (intSts)
669	intSts \|= HDA_INTSTS_GIS; /* Set the Global Interrupt Status (GIS). */
670
671	Log3Func(("-> 0x%x\n", intSts));
672
673	return intSts;
674	}
675
676
677	/**
678	* Processes (asserts/deasserts) the HDA interrupt according to the current state.
679	*
680	* @param pDevIns The device instance.
681	* @param pThis The shared HDA device state.
682	* @param pszSource Caller information.
683	*/
684	#if defined(LOG_ENABLED) \|\| defined(DOXYGEN_RUNNING)
685	void hdaProcessInterrupt(PPDMDEVINS pDevIns, PHDASTATE pThis, const char *pszSource)
686	#else
687	void hdaProcessInterrupt(PPDMDEVINS pDevIns, PHDASTATE pThis)
688	#endif
689	{
690	uint32_t uIntSts = hdaGetINTSTS(pThis);
691
692	HDA_REG(pThis, INTSTS) = uIntSts;
693
694	/* NB: It is possible to have GIS set even when CIE/SIEn are all zero; the GIS bit does
695	* not control the interrupt signal. See Figure 4 on page 54 of the HDA 1.0a spec.
696	*/
697	/* Global Interrupt Enable (GIE) set? */
698	if ( (HDA_REG(pThis, INTCTL) & HDA_INTCTL_GIE)
699	&& (HDA_REG(pThis, INTSTS) & HDA_REG(pThis, INTCTL) & (HDA_INTCTL_CIE \| HDA_STRMINT_MASK)))
700	{
701	Log3Func(("Asserted (%s)\n", pszSource));
702
703	PDMDevHlpPCISetIrq(pDevIns, 0, 1 /* Assert */);
704	pThis->u8IRQL = 1;
705
706	#ifdef DEBUG
707	pThis->Dbg.IRQ.tsAssertedNs = RTTimeNanoTS();
708	pThis->Dbg.IRQ.tsProcessedLastNs = pThis->Dbg.IRQ.tsAssertedNs;
709	#endif
710	}
711	else
712	{
713	Log3Func(("Deasserted (%s)\n", pszSource));
714
715	PDMDevHlpPCISetIrq(pDevIns, 0, 0 /* Deassert */);
716	pThis->u8IRQL = 0;
717	}
718	}
719
720
721	/**
722	* Looks up a register at the exact offset given by @a offReg.
723	*
724	* @returns Register index on success, -1 if not found.
725	* @param offReg The register offset.
726	*/
727	static int hdaRegLookup(uint32_t offReg)
728	{
729	/*
730	* Aliases.
731	*/
732	if (offReg >= g_aHdaRegAliases[0].offReg)
733	{
734	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
735	if (offReg == g_aHdaRegAliases[i].offReg)
736	return g_aHdaRegAliases[i].idxAlias;
737	Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].off < offReg);
738	return -1;
739	}
740
741	/*
742	* Binary search the
743	*/
744	int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
745	int idxLow = 0;
746	for (;;)
747	{
748	int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
749	if (offReg < g_aHdaRegMap[idxMiddle].off)
750	{
751	if (idxLow != idxMiddle)
752	idxEnd = idxMiddle;
753	else
754	break;
755	}
756	else if (offReg > g_aHdaRegMap[idxMiddle].off)
757	{
758	idxLow = idxMiddle + 1;
759	if (idxLow < idxEnd)
760	{ /* likely */ }
761	else
762	break;
763	}
764	else
765	return idxMiddle;
766	}
767
768	#ifdef RT_STRICT
769	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
770	Assert(g_aHdaRegMap[i].off != offReg);
771	#endif
772	return -1;
773	}
774
775	#ifdef IN_RING3
776
777	/**
778	* Looks up a register covering the offset given by @a offReg.
779	*
780	* @returns Register index on success, -1 if not found.
781	* @param offReg The register offset.
782	*/
783	static int hdaR3RegLookupWithin(uint32_t offReg)
784	{
785	/*
786	* Aliases.
787	*/
788	if (offReg >= g_aHdaRegAliases[0].offReg)
789	{
790	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegAliases); i++)
791	{
792	uint32_t off = offReg - g_aHdaRegAliases[i].offReg;
793	if (off < 4 && off < g_aHdaRegMap[g_aHdaRegAliases[i].idxAlias].cb)
794	return g_aHdaRegAliases[i].idxAlias;
795	}
796	Assert(g_aHdaRegMap[RT_ELEMENTS(g_aHdaRegMap) - 1].off < offReg);
797	return -1;
798	}
799
800	/*
801	* Binary search the register map.
802	*/
803	int idxEnd = RT_ELEMENTS(g_aHdaRegMap);
804	int idxLow = 0;
805	for (;;)
806	{
807	int idxMiddle = idxLow + (idxEnd - idxLow) / 2;
808	if (offReg < g_aHdaRegMap[idxMiddle].off)
809	{
810	if (idxLow == idxMiddle)
811	break;
812	idxEnd = idxMiddle;
813	}
814	else if (offReg >= g_aHdaRegMap[idxMiddle].off + g_aHdaRegMap[idxMiddle].cb)
815	{
816	idxLow = idxMiddle + 1;
817	if (idxLow >= idxEnd)
818	break;
819	}
820	else
821	return idxMiddle;
822	}
823
824	# ifdef RT_STRICT
825	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
826	Assert(offReg - g_aHdaRegMap[i].off >= g_aHdaRegMap[i].cb);
827	# endif
828	return -1;
829	}
830
831	#endif /* IN_RING3 */
832
833	#ifdef IN_RING3 /* Codec is not yet kosher enough for ring-0. @bugref{9890c64} */
834
835	/**
836	* Synchronizes the CORB / RIRB buffers between internal <-> device state.
837	*
838	* @returns VBox status code.
839	*
840	* @param pDevIns The device instance.
841	* @param pThis The shared HDA device state.
842	* @param fLocal Specify true to synchronize HDA state's CORB buffer with the device state,
843	* or false to synchronize the device state's RIRB buffer with the HDA state.
844	*
845	* @todo r=andy Break this up into two functions?
846	*/
847	static int hdaR3CmdSync(PPDMDEVINS pDevIns, PHDASTATE pThis, bool fLocal)
848	{
849	int rc = VINF_SUCCESS;
850	if (fLocal)
851	{
852	if (pThis->u64CORBBase)
853	{
854	Assert(pThis->cbCorbBuf);
855	rc = PDMDevHlpPCIPhysRead(pDevIns, pThis->u64CORBBase, pThis->au32CorbBuf,
856	RT_MIN(pThis->cbCorbBuf, sizeof(pThis->au32CorbBuf)));
857	Log3Func(("CORB: read %RGp LB %#x (%Rrc)\n", pThis->u64CORBBase, pThis->cbCorbBuf, rc));
858	AssertRCReturn(rc, rc);
859	}
860	}
861	else
862	{
863	if (pThis->u64RIRBBase)
864	{
865	Assert(pThis->cbRirbBuf);
866
867	rc = PDMDevHlpPCIPhysWrite(pDevIns, pThis->u64RIRBBase, pThis->au64RirbBuf,
868	RT_MIN(pThis->cbRirbBuf, sizeof(pThis->au64RirbBuf)));
869	Log3Func(("RIRB: phys read %RGp LB %#x (%Rrc)\n", pThis->u64RIRBBase, pThis->cbRirbBuf, rc));
870	AssertRCReturn(rc, rc);
871	}
872	}
873
874	# ifdef DEBUG_CMD_BUFFER
875	LogFunc(("fLocal=%RTbool\n", fLocal));
876
877	uint8_t i = 0;
878	do
879	{
880	LogFunc(("CORB%02x: ", i));
881	uint8_t j = 0;
882	do
883	{
884	const char *pszPrefix;
885	if ((i + j) == HDA_REG(pThis, CORBRP))
886	pszPrefix = "[R]";
887	else if ((i + j) == HDA_REG(pThis, CORBWP))
888	pszPrefix = "[W]";
889	else
890	pszPrefix = " "; /* three spaces */
891	Log((" %s%08x", pszPrefix, pThis->pu32CorbBuf[i + j]));
892	j++;
893	} while (j < 8);
894	Log(("\n"));
895	i += 8;
896	} while (i != 0);
897
898	do
899	{
900	LogFunc(("RIRB%02x: ", i));
901	uint8_t j = 0;
902	do
903	{
904	const char *prefix;
905	if ((i + j) == HDA_REG(pThis, RIRBWP))
906	prefix = "[W]";
907	else
908	prefix = " ";
909	Log((" %s%016lx", prefix, pThis->pu64RirbBuf[i + j]));
910	} while (++j < 8);
911	Log(("\n"));
912	i += 8;
913	} while (i != 0);
914	# endif
915	return rc;
916	}
917
918
919	/**
920	* Processes the next CORB buffer command in the queue.
921	*
922	* This will invoke the HDA codec ring-3 verb dispatcher.
923	*
924	* @returns VBox status code.
925	* @param pDevIns The device instance.
926	* @param pThis The shared HDA device state.
927	* @param pThisCC The ring-0 HDA device state.
928	*/
929	static int hdaR3CORBCmdProcess(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATECC pThisCC)
930	{
931	Log3Func(("ENTER CORB(RP:%x, WP:%x) RIRBWP:%x\n", HDA_REG(pThis, CORBRP), HDA_REG(pThis, CORBWP), HDA_REG(pThis, RIRBWP)));
932
933	if (!(HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA))
934	{
935	LogFunc(("CORB DMA not active, skipping\n"));
936	return VINF_SUCCESS;
937	}
938
939	Assert(pThis->cbCorbBuf);
940
941	int rc = hdaR3CmdSync(pDevIns, pThis, true /* Sync from guest */);
942	AssertRCReturn(rc, rc);
943
944	/*
945	* Prepare local copies of relevant registers.
946	*/
947	uint16_t cIntCnt = HDA_REG(pThis, RINTCNT) & 0xff;
948	if (!cIntCnt) /* 0 means 256 interrupts. */
949	cIntCnt = HDA_MAX_RINTCNT;
950
951	uint32_t const cCorbEntries = RT_MIN(RT_MAX(pThis->cbCorbBuf, 1), sizeof(pThis->au32CorbBuf)) / HDA_CORB_ELEMENT_SIZE;
952	uint8_t const corbWp = HDA_REG(pThis, CORBWP) % cCorbEntries;
953	uint8_t corbRp = HDA_REG(pThis, CORBRP);
954	uint8_t rirbWp = HDA_REG(pThis, RIRBWP);
955
956	/*
957	* The loop.
958	*/
959	Log3Func(("START CORB(RP:%x, WP:%x) RIRBWP:%x, RINTCNT:%RU8/%RU8\n", corbRp, corbWp, rirbWp, pThis->u16RespIntCnt, cIntCnt));
960	while (corbRp != corbWp)
961	{
962	/* Fetch the command from the CORB. */
963	corbRp = (corbRp + 1) /* Advance +1 as the first command(s) are at CORBWP + 1. */ % cCorbEntries;
964	uint32_t const uCmd = pThis->au32CorbBuf[corbRp];
965
966	/*
967	* Execute the command.
968	*/
969	uint64_t uResp = 0;
970	rc = hdaR3CodecLookup(&pThisCC->Codec, HDA_CODEC_CMD(uCmd, 0 /* Codec index */), &uResp);
971	if (RT_SUCCESS(rc))
972	AssertRCSuccess(rc); /* no informational statuses */
973	else
974	Log3Func(("Lookup for codec verb %08x failed: %Rrc\n", uCmd, rc));
975	Log3Func(("Codec verb %08x -> response %016RX64\n", uCmd, uResp));
976
977	if ( (uResp & CODEC_RESPONSE_UNSOLICITED)
978	&& !(HDA_REG(pThis, GCTL) & HDA_GCTL_UNSOL))
979	{
980	LogFunc(("Unexpected unsolicited response.\n"));
981	HDA_REG(pThis, CORBRP) = corbRp;
982	/** @todo r=andy No RIRB syncing to guest required in that case? */
983	/** @todo r=bird: Why isn't RIRBWP updated here. The response might come
984	* after already processing several commands, can't it? (When you think
985	* about it, it is bascially the same question as Andy is asking.) */
986	return VINF_SUCCESS;
987	}
988
989	/*
990	* Store the response in the RIRB.
991	*/
992	AssertCompile(HDA_RIRB_SIZE == RT_ELEMENTS(pThis->au64RirbBuf));
993	rirbWp = (rirbWp + 1) % HDA_RIRB_SIZE;
994	pThis->au64RirbBuf[rirbWp] = uResp;
995
996	/*
997	* Send interrupt if needed.
998	*/
999	bool fSendInterrupt = false;
1000	pThis->u16RespIntCnt++;
1001	if (pThis->u16RespIntCnt >= cIntCnt) /* Response interrupt count reached? */
1002	{
1003	pThis->u16RespIntCnt = 0; /* Reset internal interrupt response counter. */
1004
1005	Log3Func(("Response interrupt count reached (%RU16)\n", pThis->u16RespIntCnt));
1006	fSendInterrupt = true;
1007	}
1008	else if (corbRp == corbWp) /* Did we reach the end of the current command buffer? */
1009	{
1010	Log3Func(("Command buffer empty\n"));
1011	fSendInterrupt = true;
1012	}
1013	if (fSendInterrupt)
1014	{
1015	if (HDA_REG(pThis, RIRBCTL) & HDA_RIRBCTL_RINTCTL) /* Response Interrupt Control (RINTCTL) enabled? */
1016	{
1017	HDA_REG(pThis, RIRBSTS) \|= HDA_RIRBSTS_RINTFL;
1018	HDA_PROCESS_INTERRUPT(pDevIns, pThis);
1019	}
1020	}
1021	}
1022
1023	/*
1024	* Put register locals back.
1025	*/
1026	Log3Func(("END CORB(RP:%x, WP:%x) RIRBWP:%x, RINTCNT:%RU8/%RU8\n", corbRp, corbWp, rirbWp, pThis->u16RespIntCnt, cIntCnt));
1027	HDA_REG(pThis, CORBRP) = corbRp;
1028	HDA_REG(pThis, RIRBWP) = rirbWp;
1029
1030	/*
1031	* Write out the response.
1032	*/
1033	rc = hdaR3CmdSync(pDevIns, pThis, false /* Sync to guest */);
1034	AssertRC(rc);
1035
1036	return rc;
1037	}
1038
1039	#endif /* IN_RING3 - @bugref{9890c64} */
1040
1041	#ifdef IN_RING3
1042	/**
1043	* @callback_method_impl{FNPDMTASKDEV, Continue CORB DMA in ring-3}
1044	*/
1045	static DECLCALLBACK(void) hdaR3CorbDmaTaskWorker(PPDMDEVINS pDevIns, void *pvUser)
1046	{
1047	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
1048	PHDASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
1049	RT_NOREF(pvUser);
1050	LogFlowFunc(("\n"));
1051
1052	DEVHDA_LOCK(pDevIns, pThis);
1053	hdaR3CORBCmdProcess(pDevIns, pThis, pThisCC);
1054	DEVHDA_UNLOCK(pDevIns, pThis);
1055
1056	}
1057	#endif /* IN_RING3 */
1058
1059	/* Register access handlers. */
1060
1061	static VBOXSTRICTRC hdaRegReadUnimpl(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1062	{
1063	RT_NOREF(pDevIns, pThis, iReg);
1064	*pu32Value = 0;
1065	return VINF_SUCCESS;
1066	}
1067
1068	static VBOXSTRICTRC hdaRegWriteUnimpl(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1069	{
1070	RT_NOREF(pDevIns, pThis, iReg, u32Value);
1071	return VINF_SUCCESS;
1072	}
1073
1074	/* U8 */
1075	static VBOXSTRICTRC hdaRegReadU8(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1076	{
1077	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].idxReg] & g_aHdaRegMap[iReg].fReadableMask) & UINT32_C(0xffffff00)) == 0);
1078	return hdaRegReadU32(pDevIns, pThis, iReg, pu32Value);
1079	}
1080
1081	static VBOXSTRICTRC hdaRegWriteU8(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1082	{
1083	Assert((u32Value & 0xffffff00) == 0);
1084	return hdaRegWriteU32(pDevIns, pThis, iReg, u32Value);
1085	}
1086
1087	/* U16 */
1088	static VBOXSTRICTRC hdaRegReadU16(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1089	{
1090	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].idxReg] & g_aHdaRegMap[iReg].fReadableMask) & UINT32_C(0xffff0000)) == 0);
1091	return hdaRegReadU32(pDevIns, pThis, iReg, pu32Value);
1092	}
1093
1094	static VBOXSTRICTRC hdaRegWriteU16(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1095	{
1096	Assert((u32Value & 0xffff0000) == 0);
1097	return hdaRegWriteU32(pDevIns, pThis, iReg, u32Value);
1098	}
1099
1100	/* U24 */
1101	static VBOXSTRICTRC hdaRegReadU24(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1102	{
1103	Assert(((pThis->au32Regs[g_aHdaRegMap[iReg].idxReg] & g_aHdaRegMap[iReg].fReadableMask) & UINT32_C(0xff000000)) == 0);
1104	return hdaRegReadU32(pDevIns, pThis, iReg, pu32Value);
1105	}
1106
1107	#ifdef IN_RING3
1108	static VBOXSTRICTRC hdaRegWriteU24(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1109	{
1110	Assert((u32Value & 0xff000000) == 0);
1111	return hdaRegWriteU32(pDevIns, pThis, iReg, u32Value);
1112	}
1113	#endif
1114
1115	/* U32 */
1116	static VBOXSTRICTRC hdaRegReadU32(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1117	{
1118	RT_NOREF(pDevIns);
1119
1120	uint32_t const iRegMem = g_aHdaRegMap[iReg].idxReg;
1121	*pu32Value = pThis->au32Regs[iRegMem] & g_aHdaRegMap[iReg].fReadableMask;
1122	return VINF_SUCCESS;
1123	}
1124
1125	static VBOXSTRICTRC hdaRegWriteU32(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1126	{
1127	RT_NOREF(pDevIns);
1128
1129	uint32_t const iRegMem = g_aHdaRegMap[iReg].idxReg;
1130	pThis->au32Regs[iRegMem] = (u32Value & g_aHdaRegMap[iReg].fWritableMask)
1131	\| (pThis->au32Regs[iRegMem] & ~g_aHdaRegMap[iReg].fWritableMask);
1132	return VINF_SUCCESS;
1133	}
1134
1135	static VBOXSTRICTRC hdaRegWriteGCTL(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1136	{
1137	RT_NOREF(pDevIns, iReg);
1138
1139	if (u32Value & HDA_GCTL_CRST)
1140	{
1141	/* Set the CRST bit to indicate that we're leaving reset mode. */
1142	HDA_REG(pThis, GCTL) \|= HDA_GCTL_CRST;
1143	LogFunc(("Guest leaving HDA reset\n"));
1144	}
1145	else
1146	{
1147	#ifdef IN_RING3
1148	/* Enter reset state. */
1149	LogFunc(("Guest entering HDA reset with DMA(RIRB:%s, CORB:%s)\n",
1150	HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA ? "on" : "off",
1151	HDA_REG(pThis, RIRBCTL) & HDA_RIRBCTL_RDMAEN ? "on" : "off"));
1152
1153	/* Clear the CRST bit to indicate that we're in reset state. */
1154	HDA_REG(pThis, GCTL) &= ~HDA_GCTL_CRST;
1155
1156	hdaR3GCTLReset(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3));
1157	#else
1158	return VINF_IOM_R3_MMIO_WRITE;
1159	#endif
1160	}
1161
1162	if (u32Value & HDA_GCTL_FCNTRL)
1163	{
1164	/* Flush: GSTS:1 set, see 6.2.6. */
1165	HDA_REG(pThis, GSTS) \|= HDA_GSTS_FSTS; /* Set the flush status. */
1166	/* DPLBASE and DPUBASE should be initialized with initial value (see 6.2.6). */
1167	}
1168
1169	return VINF_SUCCESS;
1170	}
1171
1172	static VBOXSTRICTRC hdaRegWriteSTATESTS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1173	{
1174	RT_NOREF(pDevIns);
1175
1176	uint32_t v = HDA_REG_IND(pThis, iReg);
1177	uint32_t nv = u32Value & HDA_STATESTS_SCSF_MASK;
1178
1179	HDA_REG(pThis, STATESTS) &= ~(v & nv); /* Write of 1 clears corresponding bit. */
1180
1181	return VINF_SUCCESS;
1182	}
1183
1184	static VBOXSTRICTRC hdaRegReadLPIB(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1185	{
1186	RT_NOREF(pDevIns);
1187	uint8_t const uSD = HDA_SD_NUM_FROM_REG(pThis, LPIB, iReg);
1188	uint32_t const uLPIB = HDA_STREAM_REG(pThis, LPIB, uSD);
1189
1190	#ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
1191	/*
1192	* Should we consider doing DMA work while we're here? That would require
1193	* the stream to have the DMA engine enabled and be an output stream.
1194	*/
1195	if ( (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_SDCTL_RUN)
1196	&& hdaGetDirFromSD(uSD) == PDMAUDIODIR_OUT
1197	&& uSD < RT_ELEMENTS(pThis->aStreams) /* paranoia */)
1198	{
1199	PHDASTREAM const pStreamShared = &pThis->aStreams[uSD];
1200	Assert(pStreamShared->u8SD == uSD);
1201	if (pStreamShared->State.fRunning /* should be same as HDA_SDCTL_RUN, but doesn't hurt to check twice */)
1202	{
1203	/*
1204	* Calculate where the DMA engine should be according to the clock, if we can.
1205	*/
1206	uint32_t const cbFrame = PDMAudioPropsFrameSize(&pStreamShared->State.Cfg.Props);
1207	uint32_t const cbPeriod = pStreamShared->State.cbCurDmaPeriod;
1208	if (cbPeriod > cbFrame)
1209	{
1210	AssertMsg(pStreamShared->State.cbDmaTotal < cbPeriod, ("%#x vs %#x\n", pStreamShared->State.cbDmaTotal, cbPeriod));
1211	uint64_t const tsTransferNext = pStreamShared->State.tsTransferNext;
1212	uint64_t const tsNow = PDMDevHlpTimerGet(pDevIns, pThis->aStreams[0].hTimer); /* only #0 works in r0 */
1213	uint32_t cbFuture;
1214	if (tsNow < tsTransferNext)
1215	{
1216	/** @todo ASSUMES nanosecond clock ticks, need to make this
1217	* resolution independent. */
1218	cbFuture = PDMAudioPropsNanoToBytes(&pStreamShared->State.Cfg.Props, tsTransferNext - tsNow);
1219	cbFuture = RT_MIN(cbFuture, cbPeriod - cbFrame);
1220	}
1221	else
1222	{
1223	/* We've hit/overshot the timer deadline. Return to ring-3 if we're
1224	not already there to increase the chance that we'll help expidite
1225	the timer. If we're already in ring-3, do all but the last frame. */
1226	# ifndef IN_RING3
1227	LogFunc(("[SD%RU8] DMA period expired: tsNow=%RU64 >= tsTransferNext=%RU64 -> VINF_IOM_R3_MMIO_READ\n",
1228	tsNow, tsTransferNext));
1229	return VINF_IOM_R3_MMIO_READ;
1230	# else
1231	cbFuture = cbPeriod - cbFrame;
1232	LogFunc(("[SD%RU8] DMA period expired: tsNow=%RU64 >= tsTransferNext=%RU64 -> cbFuture=%#x (cbPeriod=%#x - cbFrame=%#x)\n",
1233	tsNow, tsTransferNext, cbFuture, cbPeriod, cbFrame));
1234	# endif
1235	}
1236	uint32_t const offNow = PDMAudioPropsFloorBytesToFrame(&pStreamShared->State.Cfg.Props, cbPeriod - cbFuture);
1237
1238	/*
1239	* Should we transfer a little? Minimum is 64 bytes (semi-random,
1240	* suspect real hardware might be doing some cache aligned stuff,
1241	* which might soon get complicated if you take unaligned buffers
1242	* into consideration and which cache line size (128 bytes is just
1243	* as likely as 64 or 32 bytes)).
1244	*/
1245	uint32_t cbDmaTotal = pStreamShared->State.cbDmaTotal;
1246	if (cbDmaTotal + 64 <= offNow)
1247	{
1248	VBOXSTRICTRC rcStrict = hdaStreamDoOnAccessDmaOutput(pDevIns, pThis, pStreamShared,
1249	tsNow, offNow - cbDmaTotal);
1250
1251	/* LPIB is updated by hdaStreamDoOnAccessDmaOutput, so get the new value. */
1252	uint32_t const uNewLpib = HDA_STREAM_REG(pThis, LPIB, uSD);
1253	*pu32Value = uNewLpib;
1254
1255	LogFlowFunc(("[SD%RU8] LPIB=%#RX32 (CBL=%#RX32 PrevLPIB=%#x offNow=%#x) rcStrict=%Rrc\n", uSD,
1256	uNewLpib, HDA_STREAM_REG(pThis, CBL, uSD), uLPIB, offNow, VBOXSTRICTRC_VAL(rcStrict) ));
1257	return rcStrict;
1258	}
1259
1260	/*
1261	* Do nothing, just return LPIB as it is.
1262	*/
1263	LogFlowFunc(("[SD%RU8] Skipping DMA transfer: cbDmaTotal=%#x offNow=%#x\n", uSD, cbDmaTotal, offNow));
1264	}
1265	else
1266	LogFunc(("[SD%RU8] cbPeriod=%#x <= cbFrame=%#x!!\n", uSD, cbPeriod, cbFrame));
1267	}
1268	else
1269	LogFunc(("[SD%RU8] fRunning=0 SDnCTL=%#x!!\n", uSD, HDA_STREAM_REG(pThis, CTL, uSD) ));
1270	}
1271	#endif /* VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
1272
1273	LogFlowFunc(("[SD%RU8] LPIB=%#RX32 (CBL=%#RX32 CTL=%#RX32)\n",
1274	uSD, uLPIB, HDA_STREAM_REG(pThis, CBL, uSD), HDA_STREAM_REG(pThis, CTL, uSD) ));
1275	*pu32Value = uLPIB;
1276	return VINF_SUCCESS;
1277	}
1278
1279	/**
1280	* Gets the wall clock.
1281	*
1282	* Used by hdaRegReadWALCLK() and 'info hda'.
1283	*
1284	* @returns Strict VBox status code if @a fDoDma is @c true, otherwise
1285	* VINF_SUCCESS.
1286	* @param pDevIns The device instance.
1287	* @param pThis The shared HDA device state.
1288	* @param fDoDma Whether to consider doing DMA work or not.
1289	* @param puWallNow Where to return the current wall clock time.
1290	*/
1291	static VBOXSTRICTRC hdaQueryWallClock(PPDMDEVINS pDevIns, PHDASTATE pThis, bool fDoDma, uint64_t *puWallNow)
1292	{
1293	/*
1294	* The wall clock is calculated from the virtual sync clock. Since
1295	* the clock is supposed to reset to zero on controller reset, a
1296	* start offset is subtracted.
1297	*
1298	* In addition, we hold the clock back when there are active DMA engines
1299	* so that the guest won't conclude we've gotten further in the buffer
1300	* processing than what we really have. (We generally read a whole buffer
1301	* at once when the IOC is due, so we're a lot later than what real
1302	* hardware would be in reading/writing the buffers.)
1303	*
1304	* Here are some old notes from the DMA engine that might be useful even
1305	* if a little dated:
1306	*
1307	* Note 1) Only certain guests (like Linux' snd_hda_intel) rely on the WALCLK register
1308	* in order to determine the correct timing of the sound device. Other guests
1309	* like Windows 7 + 10 (or even more exotic ones like Haiku) will completely
1310	* ignore this.
1311	*
1312	* Note 2) When updating the WALCLK register too often / early (or even in a non-monotonic
1313	* fashion) this will upset guest device drivers and will completely fuck up the
1314	* sound output. Running VLC on the guest will tell!
1315	*/
1316	uint64_t const uFreq = PDMDevHlpTimerGetFreq(pDevIns, pThis->aStreams[0].hTimer);
1317	Assert(uFreq <= UINT32_MAX);
1318	uint64_t const tsStart = 0; /** @todo pThis->tsWallClkStart (as it is reset on controller reset) */
1319	uint64_t const tsNow = PDMDevHlpTimerGet(pDevIns, pThis->aStreams[0].hTimer);
1320
1321	/* Find the oldest DMA transfer timestamp from the active streams. */
1322	int iDmaNow = -1;
1323	uint64_t tsDmaNow = tsNow;
1324	for (size_t i = 0; i < RT_ELEMENTS(pThis->aStreams); i++)
1325	if (pThis->aStreams[i].State.fRunning)
1326	{
1327	#ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
1328	/* Linux is reading WALCLK before one of the DMA position reads and
1329	we've already got the current time from TM, so check if we should
1330	do a little bit of DMA'ing here to help WALCLK ahead. */
1331	if (fDoDma)
1332	{
1333	if (hdaGetDirFromSD((uint8_t)i) == PDMAUDIODIR_OUT)
1334	{
1335	VBOXSTRICTRC rcStrict = hdaStreamMaybeDoOnAccessDmaOutput(pDevIns, pThis, &pThis->aStreams[i], tsNow);
1336	if (rcStrict == VINF_SUCCESS)
1337	{ /* likely */ }
1338	else
1339	return rcStrict;
1340	}
1341	}
1342	#endif
1343
1344	if ( pThis->aStreams[i].State.tsTransferLast < tsDmaNow
1345	&& pThis->aStreams[i].State.tsTransferLast > tsStart)
1346	{
1347	tsDmaNow = pThis->aStreams[i].State.tsTransferLast;
1348	iDmaNow = (int)i;
1349	}
1350	}
1351
1352	/* Convert it to wall clock ticks. */
1353	uint64_t const uWallClkNow = ASMMultU64ByU32DivByU32(tsDmaNow - tsStart,
1354	24000000 /Wall clock frequency /,
1355	uFreq);
1356	Log3Func(("Returning %#RX64 - tsNow=%#RX64 tsDmaNow=%#RX64 (%d) -> %#RX64\n",
1357	uWallClkNow, tsNow, tsDmaNow, iDmaNow, tsNow - tsDmaNow));
1358	RT_NOREF(iDmaNow, fDoDma);
1359	*puWallNow = uWallClkNow;
1360	return VINF_SUCCESS;
1361	}
1362
1363	static VBOXSTRICTRC hdaRegReadWALCLK(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
1364	{
1365	uint64_t uWallNow = 0;
1366	VBOXSTRICTRC rcStrict = hdaQueryWallClock(pDevIns, pThis, true /fDoDma/, &uWallNow);
1367	if (rcStrict == VINF_SUCCESS)
1368	{
1369	*pu32Value = (uint32_t)uWallNow;
1370	return VINF_SUCCESS;
1371	}
1372	RT_NOREF(iReg);
1373	return rcStrict;
1374	}
1375
1376	static VBOXSTRICTRC hdaRegWriteSSYNCWorker(PHDASTATE pThis, uint32_t iReg, uint32_t u32Value, const char *pszCaller)
1377	{
1378	RT_NOREF(pszCaller);
1379
1380	/*
1381	* The SSYNC register is a DMA pause mask where each bit represents a stream.
1382	* There should be no DMA transfers going down the driver chains when the a
1383	* stream has its bit set here. There are two scenarios described in the
1384	* specification, starting and stopping, though it can probably be used for
1385	* other purposes if the guest gets creative...
1386	*
1387	* Anyway, if we ever want to implement this, we'd be manipulating the DMA
1388	* timers of the affected streams here, I think. At least in the start
1389	* scenario, we would run the first DMA transfers from here.
1390	*/
1391	uint32_t const fOld = HDA_REG(pThis, SSYNC);
1392	uint32_t const fNew = (u32Value & g_aHdaRegMap[iReg].fWritableMask)
1393	\| (fOld & ~g_aHdaRegMap[iReg].fWritableMask);
1394	uint32_t const fChanged = (fNew ^ fOld) & (RT_BIT_32(HDA_MAX_STREAMS) - 1);
1395	if (fChanged)
1396	{
1397	#if 0 /** @todo implement SSYNC: ndef IN_RING3 */
1398	Log3(("%s: Going to ring-3 to handle SSYNC change: %#x\n", pszCaller, fChanged));
1399	return VINF_IOM_R3_MMIO_WRITE;
1400	#else
1401	for (uint32_t fMask = 1, i = 0; fMask < RT_BIT_32(HDA_MAX_STREAMS); i++, fMask <<= 1)
1402	if (!(fChanged & fMask))
1403	{ /* nothing */ }
1404	else if (fNew & fMask)
1405	{
1406	Log3(("%Rfn: SSYNC bit %u set\n", pszCaller, i));
1407	/* See code in SDCTL around hdaR3StreamTimerMain call. */
1408	}
1409	else
1410	{
1411	Log3(("%Rfn: SSYNC bit %u cleared\n", pszCaller, i));
1412	/* The next DMA timer callout will not do anything. */
1413	}
1414	#endif
1415	}
1416
1417	HDA_REG(pThis, SSYNC) = fNew;
1418	return VINF_SUCCESS;
1419	}
1420
1421	static VBOXSTRICTRC hdaRegWriteSSYNC(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1422	{
1423	RT_NOREF(pDevIns);
1424	return hdaRegWriteSSYNCWorker(pThis, iReg, u32Value, __FUNCTION__);
1425	}
1426
1427	static VBOXSTRICTRC hdaRegWriteNewSSYNC(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1428	{
1429	RT_NOREF(pDevIns);
1430	return hdaRegWriteSSYNCWorker(pThis, iReg, u32Value, __FUNCTION__);
1431	}
1432
1433	static VBOXSTRICTRC hdaRegWriteCORBRP(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1434	{
1435	RT_NOREF(pDevIns, iReg);
1436	if (u32Value & HDA_CORBRP_RST)
1437	{
1438	/* Do a CORB reset. */
1439	if (pThis->cbCorbBuf)
1440	RT_ZERO(pThis->au32CorbBuf);
1441
1442	LogRel2(("HDA: CORB reset\n"));
1443	HDA_REG(pThis, CORBRP) = HDA_CORBRP_RST; /* Clears the pointer. */
1444	}
1445	else
1446	HDA_REG(pThis, CORBRP) &= ~HDA_CORBRP_RST; /* Only CORBRP_RST bit is writable. */
1447
1448	return VINF_SUCCESS;
1449	}
1450
1451	static VBOXSTRICTRC hdaRegWriteCORBCTL(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1452	{
1453	VBOXSTRICTRC rc = hdaRegWriteU8(pDevIns, pThis, iReg, u32Value);
1454	AssertRCSuccess(VBOXSTRICTRC_VAL(rc));
1455
1456	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* DMA engine started? */
1457	{
1458	#ifdef IN_RING3 /** @todo do PDMDevHlpTaskTrigger everywhere? */
1459	rc = hdaR3CORBCmdProcess(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATECC));
1460	#else
1461	rc = PDMDevHlpTaskTrigger(pDevIns, pThis->hCorbDmaTask);
1462	if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
1463	rc = VINF_SUCCESS;
1464	#endif
1465	}
1466	else
1467	LogFunc(("CORB DMA not running, skipping\n"));
1468
1469	return rc;
1470	}
1471
1472	static VBOXSTRICTRC hdaRegWriteCORBSIZE(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1473	{
1474	RT_NOREF(pDevIns, iReg);
1475
1476	if (!(HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA)) /* Ignore request if CORB DMA engine is (still) running. */
1477	{
1478	u32Value = (u32Value & HDA_CORBSIZE_SZ);
1479
1480	uint16_t cEntries;
1481	switch (u32Value)
1482	{
1483	case 0: /* 8 byte; 2 entries. */
1484	cEntries = 2;
1485	break;
1486	case 1: /* 64 byte; 16 entries. */
1487	cEntries = 16;
1488	break;
1489	case 2: /* 1 KB; 256 entries. */
1490	cEntries = HDA_CORB_SIZE; /* default. */
1491	break;
1492	default:
1493	LogRel(("HDA: Guest tried to set an invalid CORB size (0x%x), keeping default\n", u32Value));
1494	u32Value = 2;
1495	cEntries = HDA_CORB_SIZE; /* Use default size. */
1496	break;
1497	}
1498
1499	uint32_t cbCorbBuf = cEntries * HDA_CORB_ELEMENT_SIZE;
1500	Assert(cbCorbBuf <= sizeof(pThis->au32CorbBuf)); /* paranoia */
1501
1502	if (cbCorbBuf != pThis->cbCorbBuf)
1503	{
1504	RT_ZERO(pThis->au32CorbBuf); /* Clear CORB when setting a new size. */
1505	pThis->cbCorbBuf = cbCorbBuf;
1506	}
1507
1508	LogFunc(("CORB buffer size is now %RU32 bytes (%u entries)\n", pThis->cbCorbBuf, pThis->cbCorbBuf / HDA_CORB_ELEMENT_SIZE));
1509
1510	HDA_REG(pThis, CORBSIZE) = u32Value;
1511	}
1512	else
1513	LogFunc(("CORB DMA is (still) running, skipping\n"));
1514	return VINF_SUCCESS;
1515	}
1516
1517	static VBOXSTRICTRC hdaRegWriteCORBSTS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1518	{
1519	RT_NOREF(pDevIns, iReg);
1520
1521	uint32_t v = HDA_REG(pThis, CORBSTS);
1522	HDA_REG(pThis, CORBSTS) &= ~(v & u32Value);
1523
1524	return VINF_SUCCESS;
1525	}
1526
1527	static VBOXSTRICTRC hdaRegWriteCORBWP(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1528	{
1529	VBOXSTRICTRC rc = hdaRegWriteU16(pDevIns, pThis, iReg, u32Value);
1530	AssertRCSuccess(VBOXSTRICTRC_VAL(rc));
1531
1532	#ifdef IN_RING3 /** @todo do PDMDevHlpTaskTrigger everywhere? */
1533	return hdaR3CORBCmdProcess(pDevIns, pThis, PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATECC));
1534	#else
1535	rc = PDMDevHlpTaskTrigger(pDevIns, pThis->hCorbDmaTask);
1536	return RT_SUCCESS(rc) ? VINF_SUCCESS : rc;
1537	#endif
1538	}
1539
1540	static VBOXSTRICTRC hdaRegWriteSDCBL(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1541	{
1542	return hdaRegWriteU32(pDevIns, pThis, iReg, u32Value);
1543	}
1544
1545	static VBOXSTRICTRC hdaRegWriteSDCTL(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1546	{
1547	#ifdef IN_RING3
1548	/* Get the stream descriptor number. */
1549	const uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, CTL, iReg);
1550	AssertReturn(uSD < RT_ELEMENTS(pThis->aStreams), VERR_INTERNAL_ERROR_3); /* paranoia^2: Bad g_aHdaRegMap. */
1551
1552	/*
1553	* Extract the stream tag the guest wants to use for this specific
1554	* stream descriptor (SDn). This only can happen if the stream is in a non-running
1555	* state, so we're doing the lookup and assignment here.
1556	*
1557	* So depending on the guest OS, SD3 can use stream tag 4, for example.
1558	*/
1559	PHDASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
1560	uint8_t uTag = (u32Value >> HDA_SDCTL_NUM_SHIFT) & HDA_SDCTL_NUM_MASK;
1561	ASSERT_GUEST_MSG_RETURN(uTag < RT_ELEMENTS(pThisCC->aTags),
1562	("SD%RU8: Invalid stream tag %RU8 (u32Value=%#x)!\n", uSD, uTag, u32Value),
1563	VINF_SUCCESS /* Always return success to the MMIO handler. */);
1564
1565	PHDASTREAM const pStreamShared = &pThis->aStreams[uSD];
1566	PHDASTREAMR3 const pStreamR3 = &pThisCC->aStreams[uSD];
1567
1568	const bool fRun = RT_BOOL(u32Value & HDA_SDCTL_RUN);
1569	const bool fReset = RT_BOOL(u32Value & HDA_SDCTL_SRST);
1570
1571	/* If the run bit is set, we take the virtual-sync clock lock as well so we
1572	can safely update timers via hdaR3TimerSet if necessary. We need to be
1573	very careful with the fInReset and fInRun indicators here, as they may
1574	change during the relocking if we need to acquire the clock lock. */
1575	const bool fNeedVirtualSyncClockLock = (u32Value & (HDA_SDCTL_RUN \| HDA_SDCTL_SRST)) == HDA_SDCTL_RUN
1576	&& (HDA_REG_IND(pThis, iReg) & HDA_SDCTL_RUN) == 0;
1577	if (fNeedVirtualSyncClockLock)
1578	{
1579	DEVHDA_UNLOCK(pDevIns, pThis);
1580	DEVHDA_LOCK_BOTH_RETURN(pDevIns, pThis, pStreamShared, VINF_IOM_R3_MMIO_WRITE);
1581	}
1582
1583	const bool fInRun = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_SDCTL_RUN);
1584	const bool fInReset = RT_BOOL(HDA_REG_IND(pThis, iReg) & HDA_SDCTL_SRST);
1585
1586	/*LogFunc(("[SD%RU8] fRun=%RTbool, fInRun=%RTbool, fReset=%RTbool, fInReset=%RTbool, %R[sdctl]\n",
1587	uSD, fRun, fInRun, fReset, fInReset, u32Value));*/
1588	if (fInReset)
1589	{
1590	ASSERT_GUEST(!fReset);
1591	ASSERT_GUEST(!fInRun && !fRun);
1592
1593	/* Exit reset state. */
1594	ASMAtomicXchgBool(&pStreamShared->State.fInReset, false);
1595
1596	/* Report that we're done resetting this stream by clearing SRST. */
1597	HDA_STREAM_REG(pThis, CTL, uSD) &= ~HDA_SDCTL_SRST;
1598
1599	LogFunc(("[SD%RU8] Reset exit\n", uSD));
1600	}
1601	else if (fReset)
1602	{
1603	/* ICH6 datasheet 18.2.33 says that RUN bit should be cleared before initiation of reset. */
1604	ASSERT_GUEST(!fInRun && !fRun);
1605
1606	LogFunc(("[SD%RU8] Reset enter\n", uSD));
1607
1608	STAM_REL_PROFILE_START_NS(&pStreamR3->State.StatReset, a);
1609	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
1610	PAUDMIXSINK const pMixSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
1611	if (pMixSink)
1612	AudioMixerSinkLock(pMixSink);
1613
1614	/* Deal with reset while running. */
1615	if (pStreamShared->State.fRunning)
1616	{
1617	int rc2 = hdaR3StreamEnable(pThis, pStreamShared, pStreamR3, false /* fEnable */);
1618	AssertRC(rc2); Assert(!pStreamShared->State.fRunning);
1619	pStreamShared->State.fRunning = false;
1620	}
1621
1622	hdaR3StreamReset(pThis, pThisCC, pStreamShared, pStreamR3, uSD);
1623
1624	if (pMixSink) /* (FYI. pMixSink might not be what pStreamR3->pMixSink->pMixSink points at any longer) */
1625	AudioMixerSinkUnlock(pMixSink);
1626	STAM_REL_PROFILE_STOP_NS(&pStreamR3->State.StatReset, a);
1627	}
1628	else
1629	{
1630	/*
1631	* We enter here to change DMA states only.
1632	*/
1633	if (fInRun != fRun)
1634	{
1635	STAM_REL_PROFILE_START_NS((fRun ? &pStreamR3->State.StatStart : &pStreamR3->State.StatStop), r);
1636	Assert(!fReset && !fInReset); /* (code change paranoia, currently impossible ) */
1637	LogFunc(("[SD%RU8] State changed (fRun=%RTbool)\n", uSD, fRun));
1638
1639	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
1640	/** @todo bird: It's not clear to me when the pMixSink is actually
1641	* assigned to the stream, so being paranoid till I find out... */
1642	PAUDMIXSINK const pMixSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
1643	if (pMixSink)
1644	AudioMixerSinkLock(pMixSink);
1645
1646	int rc2 = VINF_SUCCESS;
1647	if (fRun)
1648	{
1649	if (hdaGetDirFromSD(uSD) == PDMAUDIODIR_OUT)
1650	{
1651	const uint8_t uStripeCtl = ((u32Value >> HDA_SDCTL_STRIPE_SHIFT) & HDA_SDCTL_STRIPE_MASK) + 1;
1652	LogFunc(("[SD%RU8] Using %RU8 SDOs (stripe control)\n", uSD, uStripeCtl));
1653	if (uStripeCtl > 1)
1654	LogRel2(("HDA: Warning: Striping output over more than one SDO for stream #%RU8 currently is not implemented " \
1655	"(%RU8 SDOs requested)\n", uSD, uStripeCtl));
1656	}
1657
1658	/* Assign new values. */
1659	LogFunc(("[SD%RU8] Using stream tag=%RU8\n", uSD, uTag));
1660	PHDATAG pTag = &pThisCC->aTags[uTag];
1661	pTag->uTag = uTag;
1662	pTag->pStreamR3 = &pThisCC->aStreams[uSD];
1663
1664	# ifdef LOG_ENABLED
1665	if (LogIsEnabled())
1666	{
1667	PDMAUDIOPCMPROPS Props = { 0 };
1668	rc2 = hdaR3SDFMTToPCMProps(HDA_STREAM_REG(pThis, FMT, uSD), &Props); AssertRC(rc2);
1669	LogFunc(("[SD%RU8] %RU32Hz, %RU8bit, %RU8 channel(s)\n",
1670	uSD, Props.uHz, PDMAudioPropsSampleBits(&Props), PDMAudioPropsChannels(&Props)));
1671	}
1672	# endif
1673	/* (Re-)initialize the stream with current values. */
1674	rc2 = hdaR3StreamSetUp(pDevIns, pThis, pStreamShared, pStreamR3, uSD);
1675	if ( RT_SUCCESS(rc2)
1676	/* Any vital stream change occurred so that we need to (re-)add the stream to our setup?
1677	* Otherwise just skip this, as this costs a lot of performance. */
1678	/** @todo r=bird: hdaR3StreamSetUp does not return VINF_NO_CHANGE since r142810. */
1679	&& rc2 != VINF_NO_CHANGE)
1680	{
1681	/* Remove the old stream from the device setup. */
1682	rc2 = hdaR3RemoveStream(pThisCC, &pStreamShared->State.Cfg);
1683	AssertRC(rc2);
1684
1685	/* Add the stream to the device setup. */
1686	rc2 = hdaR3AddStream(pThisCC, &pStreamShared->State.Cfg);
1687	AssertRC(rc2);
1688	}
1689	}
1690
1691	if (RT_SUCCESS(rc2))
1692	{
1693	/* Enable/disable the stream. */
1694	rc2 = hdaR3StreamEnable(pThis, pStreamShared, pStreamR3, fRun /* fEnable */);
1695	AssertRC(rc2);
1696
1697	if (fRun)
1698	{
1699	/** @todo move this into a HDAStream.cpp function. */
1700	uint64_t tsNow;
1701	if (hdaGetDirFromSD(uSD) == PDMAUDIODIR_OUT)
1702	{
1703	/* Output streams: Avoid going through the timer here by calling the stream's timer
1704	function directly. Should speed up starting the stream transfers. */
1705	tsNow = hdaR3StreamTimerMain(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3);
1706	}
1707	else
1708	{
1709	/* Input streams: Arm the timer and kick the AIO thread. */
1710	tsNow = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer);
1711	pStreamShared->State.tsTransferLast = tsNow; /* for WALCLK */
1712
1713	uint64_t tsTransferNext = tsNow + pStreamShared->State.aSchedule[0].cPeriodTicks;
1714	pStreamShared->State.tsTransferNext = tsTransferNext; /* legacy */
1715	pStreamShared->State.cbCurDmaPeriod = pStreamShared->State.aSchedule[0].cbPeriod;
1716	Log3Func(("[SD%RU8] tsTransferNext=%RU64 (in %RU64)\n",
1717	pStreamShared->u8SD, tsTransferNext, tsTransferNext - tsNow));
1718
1719	int rc = PDMDevHlpTimerSet(pDevIns, pStreamShared->hTimer, tsTransferNext);
1720	AssertRC(rc);
1721
1722	/** @todo we should have a delayed AIO thread kick off, really... */
1723	if (pStreamR3->pMixSink && pStreamR3->pMixSink->pMixSink)
1724	AudioMixerSinkSignalUpdateJob(pStreamR3->pMixSink->pMixSink);
1725	else
1726	AssertFailed();
1727	}
1728	hdaR3StreamMarkStarted(pDevIns, pThis, pStreamShared, tsNow);
1729	}
1730	else
1731	hdaR3StreamMarkStopped(pStreamShared);
1732	}
1733
1734	/* Make sure to leave the lock before (eventually) starting the timer. */
1735	if (pMixSink)
1736	AudioMixerSinkUnlock(pMixSink);
1737	STAM_REL_PROFILE_STOP_NS((fRun ? &pStreamR3->State.StatStart : &pStreamR3->State.StatStop), r);
1738	}
1739	}
1740
1741	if (fNeedVirtualSyncClockLock)
1742	PDMDevHlpTimerUnlockClock(pDevIns, pStreamShared->hTimer); /* Caller will unlock pThis->CritSect. */
1743
1744	return hdaRegWriteU24(pDevIns, pThis, iReg, u32Value);
1745	#else /* !IN_RING3 */
1746	RT_NOREF(pDevIns, pThis, iReg, u32Value);
1747	return VINF_IOM_R3_MMIO_WRITE;
1748	#endif /* !IN_RING3 */
1749	}
1750
1751	static VBOXSTRICTRC hdaRegWriteSDSTS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1752	{
1753	uint32_t v = HDA_REG_IND(pThis, iReg);
1754
1755	/* Clear (zero) FIFOE, DESE and BCIS bits when writing 1 to it (6.2.33). */
1756	HDA_REG_IND(pThis, iReg) &= ~(u32Value & v);
1757
1758	HDA_PROCESS_INTERRUPT(pDevIns, pThis);
1759
1760	return VINF_SUCCESS;
1761	}
1762
1763	static VBOXSTRICTRC hdaRegWriteSDLVI(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1764	{
1765	const size_t idxStream = HDA_SD_NUM_FROM_REG(pThis, LVI, iReg);
1766	AssertReturn(idxStream < RT_ELEMENTS(pThis->aStreams), VERR_INTERNAL_ERROR_3); /* paranoia^2: Bad g_aHdaRegMap. */
1767
1768	ASSERT_GUEST_LOGREL_MSG(u32Value <= UINT8_MAX, /* Should be covered by the register write mask, but just to make sure. */
1769	("LVI for stream #%zu must not be bigger than %RU8\n", idxStream, UINT8_MAX - 1));
1770	return hdaRegWriteU16(pDevIns, pThis, iReg, u32Value);
1771	}
1772
1773	/**
1774	* Calculates the number of bytes of a FIFOW register.
1775	*
1776	* @return Number of bytes of a given FIFOW register.
1777	* @param u16RegFIFOW FIFOW register to convert.
1778	*/
1779	uint8_t hdaSDFIFOWToBytes(uint16_t u16RegFIFOW)
1780	{
1781	uint32_t cb;
1782	switch (u16RegFIFOW)
1783	{
1784	case HDA_SDFIFOW_8B: cb = 8; break;
1785	case HDA_SDFIFOW_16B: cb = 16; break;
1786	case HDA_SDFIFOW_32B: cb = 32; break;
1787	default:
1788	AssertFailedStmt(cb = 32); /* Paranoia. */
1789	break;
1790	}
1791
1792	Assert(RT_IS_POWER_OF_TWO(cb));
1793	return cb;
1794	}
1795
1796	static VBOXSTRICTRC hdaRegWriteSDFIFOW(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1797	{
1798	size_t const idxStream = HDA_SD_NUM_FROM_REG(pThis, FIFOW, iReg);
1799	AssertReturn(idxStream < RT_ELEMENTS(pThis->aStreams), VERR_INTERNAL_ERROR_3); /* paranoia^2: Bad g_aHdaRegMap. */
1800
1801	if (RT_LIKELY(hdaGetDirFromSD((uint8_t)idxStream) == PDMAUDIODIR_IN)) /* FIFOW for input streams only. */
1802	{ /* likely */ }
1803	else
1804	{
1805	#ifndef IN_RING0
1806	LogRel(("HDA: Warning: Guest tried to write read-only FIFOW to output stream #%RU8, ignoring\n", idxStream));
1807	return VINF_SUCCESS;
1808	#else
1809	return VINF_IOM_R3_MMIO_WRITE; /* (Go to ring-3 for release logging.) */
1810	#endif
1811	}
1812
1813	uint16_t u16FIFOW = 0;
1814	switch (u32Value)
1815	{
1816	case HDA_SDFIFOW_8B:
1817	case HDA_SDFIFOW_16B:
1818	case HDA_SDFIFOW_32B:
1819	u16FIFOW = RT_LO_U16(u32Value); /* Only bits 2:0 are used; see ICH-6, 18.2.38. */
1820	break;
1821	default:
1822	ASSERT_GUEST_LOGREL_MSG_FAILED(("Guest tried writing unsupported FIFOW (0x%zx) to stream #%RU8, defaulting to 32 bytes\n",
1823	u32Value, idxStream));
1824	u16FIFOW = HDA_SDFIFOW_32B;
1825	break;
1826	}
1827
1828	pThis->aStreams[idxStream].u8FIFOW = hdaSDFIFOWToBytes(u16FIFOW);
1829	LogFunc(("[SD%zu] Updating FIFOW to %RU8 bytes\n", idxStream, pThis->aStreams[idxStream].u8FIFOW));
1830	return hdaRegWriteU16(pDevIns, pThis, iReg, u16FIFOW);
1831	}
1832
1833	/**
1834	* @note This method could be called for changing value on Output Streams only (ICH6 datasheet 18.2.39).
1835	*/
1836	static VBOXSTRICTRC hdaRegWriteSDFIFOS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
1837	{
1838	uint8_t uSD = HDA_SD_NUM_FROM_REG(pThis, FIFOS, iReg);
1839
1840	ASSERT_GUEST_LOGREL_MSG_RETURN(hdaGetDirFromSD(uSD) == PDMAUDIODIR_OUT, /* FIFOS for output streams only. */
1841	("Guest tried writing read-only FIFOS to input stream #%RU8, ignoring\n", uSD),
1842	VINF_SUCCESS);
1843
1844	uint32_t u32FIFOS;
1845	switch (u32Value)
1846	{
1847	case HDA_SDOFIFO_16B:
1848	case HDA_SDOFIFO_32B:
1849	case HDA_SDOFIFO_64B:
1850	case HDA_SDOFIFO_128B:
1851	case HDA_SDOFIFO_192B:
1852	case HDA_SDOFIFO_256B:
1853	u32FIFOS = u32Value;
1854	break;
1855
1856	default:
1857	ASSERT_GUEST_LOGREL_MSG_FAILED(("Guest tried writing unsupported FIFOS (0x%x) to stream #%RU8, defaulting to 192 bytes\n",
1858	u32Value, uSD));
1859	u32FIFOS = HDA_SDOFIFO_192B;
1860	break;
1861	}
1862
1863	return hdaRegWriteU16(pDevIns, pThis, iReg, u32FIFOS);
1864	}
1865
1866	#ifdef IN_RING3
1867
1868	/**
1869	* Adds an audio output stream to the device setup using the given configuration.
1870	*
1871	* @returns VBox status code.
1872	* @param pThisCC The ring-3 HDA device state.
1873	* @param pCfg Stream configuration to use for adding a stream.
1874	*/
1875	static int hdaR3AddStreamOut(PHDASTATER3 pThisCC, PPDMAUDIOSTREAMCFG pCfg)
1876	{
1877	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1878
1879	AssertReturn(pCfg->enmDir == PDMAUDIODIR_OUT, VERR_INVALID_PARAMETER);
1880
1881	LogFlowFunc(("Stream=%s\n", pCfg->szName));
1882
1883	int rc = VINF_SUCCESS;
1884
1885	bool fUseFront = true; /* Always use front out by default. */
1886	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1887	bool fUseRear;
1888	bool fUseCenter;
1889	bool fUseLFE;
1890
1891	fUseRear = fUseCenter = fUseLFE = false;
1892
1893	/*
1894	* Use commonly used setups for speaker configurations.
1895	*/
1896
1897	/** @todo Make the following configurable through mixer API and/or CFGM? */
1898	switch (PDMAudioPropsChannels(&pCfg->Props))
1899	{
1900	case 3: /* 2.1: Front (Stereo) + LFE. */
1901	{
1902	fUseLFE = true;
1903	break;
1904	}
1905
1906	case 4: /* Quadrophonic: Front (Stereo) + Rear (Stereo). */
1907	{
1908	fUseRear = true;
1909	break;
1910	}
1911
1912	case 5: /* 4.1: Front (Stereo) + Rear (Stereo) + LFE. */
1913	{
1914	fUseRear = true;
1915	fUseLFE = true;
1916	break;
1917	}
1918
1919	case 6: /* 5.1: Front (Stereo) + Rear (Stereo) + Center/LFE. */
1920	{
1921	fUseRear = true;
1922	fUseCenter = true;
1923	fUseLFE = true;
1924	break;
1925	}
1926
1927	default: /* Unknown; fall back to 2 front channels (stereo). */
1928	{
1929	rc = VERR_NOT_SUPPORTED;
1930	break;
1931	}
1932	}
1933	# endif /* !VBOX_WITH_AUDIO_HDA_51_SURROUND */
1934
1935	if (rc == VERR_NOT_SUPPORTED)
1936	{
1937	LogRel2(("HDA: Warning: Unsupported channel count (%RU8), falling back to stereo channels (2)\n",
1938	PDMAudioPropsChannels(&pCfg->Props) ));
1939
1940	/* Fall back to 2 channels (see below in fUseFront block). */
1941	rc = VINF_SUCCESS;
1942	}
1943
1944	do
1945	{
1946	if (RT_FAILURE(rc))
1947	break;
1948
1949	if (fUseFront)
1950	{
1951	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Front");
1952
1953	pCfg->enmPath = PDMAUDIOPATH_OUT_FRONT;
1954	/// @todo PDMAudioPropsSetChannels(&pCfg->Props, 2); ?
1955
1956	rc = hdaR3CodecAddStream(&pThisCC->Codec, PDMAUDIOMIXERCTL_FRONT, pCfg);
1957	}
1958
1959	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
1960	if ( RT_SUCCESS(rc)
1961	&& (fUseCenter \|\| fUseLFE))
1962	{
1963	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Center/LFE");
1964
1965	pCfg->enmPath = PDMAUDIOPATH_OUT_CENTER_LFE;
1966	PDMAudioPropsSetChannels(&pCfg->Props, fUseCenter && fUseLFE ? 2 : 1);
1967
1968	rc = hdaR3CodecAddStream(&pThisCC->Codec, PDMAUDIOMIXERCTL_CENTER_LFE, pCfg);
1969	}
1970
1971	if ( RT_SUCCESS(rc)
1972	&& fUseRear)
1973	{
1974	RTStrPrintf(pCfg->szName, RT_ELEMENTS(pCfg->szName), "Rear");
1975
1976	pCfg->enmPath = PDMAUDIOPATH_OUT_REAR;
1977	PDMAudioPropsSetChannels(&pCfg->Props, 2);
1978
1979	rc = hdaR3CodecAddStream(&pThisCC->Codec, PDMAUDIOMIXERCTL_REAR, pCfg);
1980	}
1981	# endif /* VBOX_WITH_AUDIO_HDA_51_SURROUND */
1982
1983	} while (0);
1984
1985	LogFlowFuncLeaveRC(rc);
1986	return rc;
1987	}
1988
1989	/**
1990	* Adds an audio input stream to the device setup using the given configuration.
1991	*
1992	* @returns VBox status code.
1993	* @param pThisCC The ring-3 HDA device state.
1994	* @param pCfg Stream configuration to use for adding a stream.
1995	*/
1996	static int hdaR3AddStreamIn(PHDASTATER3 pThisCC, PPDMAUDIOSTREAMCFG pCfg)
1997	{
1998	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
1999
2000	AssertReturn(pCfg->enmDir == PDMAUDIODIR_IN, VERR_INVALID_PARAMETER);
2001
2002	LogFlowFunc(("Stream=%s enmPath=%ld\n", pCfg->szName, pCfg->enmPath));
2003
2004	int rc;
2005	switch (pCfg->enmPath)
2006	{
2007	case PDMAUDIOPATH_IN_LINE:
2008	rc = hdaR3CodecAddStream(&pThisCC->Codec, PDMAUDIOMIXERCTL_LINE_IN, pCfg);
2009	break;
2010	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2011	case PDMAUDIOPATH_IN_MIC:
2012	rc = hdaR3CodecAddStream(&pThisCC->Codec, PDMAUDIOMIXERCTL_MIC_IN, pCfg);
2013	break;
2014	# endif
2015	default:
2016	rc = VERR_NOT_SUPPORTED;
2017	break;
2018	}
2019
2020	LogFlowFuncLeaveRC(rc);
2021	return rc;
2022	}
2023
2024	/**
2025	* Adds an audio stream to the device setup using the given configuration.
2026	*
2027	* @returns VBox status code.
2028	* @param pThisCC The ring-3 HDA device state.
2029	* @param pCfg Stream configuration to use for adding a stream.
2030	*/
2031	static int hdaR3AddStream(PHDASTATER3 pThisCC, PPDMAUDIOSTREAMCFG pCfg)
2032	{
2033	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2034
2035	LogFlowFuncEnter();
2036
2037	int rc;
2038	switch (pCfg->enmDir)
2039	{
2040	case PDMAUDIODIR_OUT:
2041	rc = hdaR3AddStreamOut(pThisCC, pCfg);
2042	break;
2043
2044	case PDMAUDIODIR_IN:
2045	rc = hdaR3AddStreamIn(pThisCC, pCfg);
2046	break;
2047
2048	default:
2049	rc = VERR_NOT_SUPPORTED;
2050	AssertFailed();
2051	break;
2052	}
2053
2054	LogFlowFunc(("Returning %Rrc\n", rc));
2055
2056	return rc;
2057	}
2058
2059	/**
2060	* Removes an audio stream from the device setup using the given configuration.
2061	*
2062	* Used by hdaRegWriteSDCTL().
2063	*
2064	* @returns VBox status code.
2065	* @param pThisCC The ring-3 HDA device state.
2066	* @param pCfg Stream configuration to use for removing a stream.
2067	*/
2068	static int hdaR3RemoveStream(PHDASTATER3 pThisCC, PPDMAUDIOSTREAMCFG pCfg)
2069	{
2070	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2071
2072	int rc = VINF_SUCCESS;
2073
2074	PDMAUDIOMIXERCTL enmMixerCtl = PDMAUDIOMIXERCTL_UNKNOWN;
2075	switch (pCfg->enmDir)
2076	{
2077	case PDMAUDIODIR_IN:
2078	{
2079	LogFlowFunc(("Stream=%s enmPath=%d (src)\n", pCfg->szName, pCfg->enmPath));
2080
2081	switch (pCfg->enmPath)
2082	{
2083	case PDMAUDIOPATH_UNKNOWN: break;
2084	case PDMAUDIOPATH_IN_LINE: enmMixerCtl = PDMAUDIOMIXERCTL_LINE_IN; break;
2085	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2086	case PDMAUDIOPATH_IN_MIC: enmMixerCtl = PDMAUDIOMIXERCTL_MIC_IN; break;
2087	# endif
2088	default:
2089	rc = VERR_NOT_SUPPORTED;
2090	break;
2091	}
2092	break;
2093	}
2094
2095	case PDMAUDIODIR_OUT:
2096	{
2097	LogFlowFunc(("Stream=%s, enmPath=%d (dst)\n", pCfg->szName, pCfg->enmPath));
2098
2099	switch (pCfg->enmPath)
2100	{
2101	case PDMAUDIOPATH_UNKNOWN: break;
2102	case PDMAUDIOPATH_OUT_FRONT: enmMixerCtl = PDMAUDIOMIXERCTL_FRONT; break;
2103	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2104	case PDMAUDIOPATH_OUT_CENTER_LFE: enmMixerCtl = PDMAUDIOMIXERCTL_CENTER_LFE; break;
2105	case PDMAUDIOPATH_OUT_REAR: enmMixerCtl = PDMAUDIOMIXERCTL_REAR; break;
2106	# endif
2107	default:
2108	rc = VERR_NOT_SUPPORTED;
2109	break;
2110	}
2111	break;
2112	}
2113
2114	default:
2115	rc = VERR_NOT_SUPPORTED;
2116	break;
2117	}
2118
2119	if ( RT_SUCCESS(rc)
2120	&& enmMixerCtl != PDMAUDIOMIXERCTL_UNKNOWN)
2121	{
2122	rc = hdaR3CodecRemoveStream(&pThisCC->Codec, enmMixerCtl, false /fImmediate/);
2123	}
2124
2125	LogFlowFuncLeaveRC(rc);
2126	return rc;
2127	}
2128
2129	#endif /* IN_RING3 */
2130
2131	static VBOXSTRICTRC hdaRegWriteSDFMT(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2132	{
2133	#ifdef IN_RING3
2134	PDMAUDIOPCMPROPS Props;
2135	int rc2 = hdaR3SDFMTToPCMProps(RT_LO_U16(u32Value), &Props);
2136	AssertRC(rc2);
2137	LogFunc(("[SD%RU8] Set to %#x (%RU32Hz, %RU8bit, %RU8 channel(s))\n", HDA_SD_NUM_FROM_REG(pThis, FMT, iReg), u32Value,
2138	PDMAudioPropsHz(&Props), PDMAudioPropsSampleBits(&Props), PDMAudioPropsChannels(&Props)));
2139
2140	/*
2141	* Write the wanted stream format into the register in any case.
2142	*
2143	* This is important for e.g. MacOS guests, as those try to initialize streams which are not reported
2144	* by the device emulation (wants 4 channels, only have 2 channels at the moment).
2145	*
2146	* When ignoring those (invalid) formats, this leads to MacOS thinking that the device is malfunctioning
2147	* and therefore disabling the device completely.
2148	*/
2149	return hdaRegWriteU16(pDevIns, pThis, iReg, u32Value);
2150	#else
2151	RT_NOREF(pDevIns, pThis, iReg, u32Value);
2152	return VINF_IOM_R3_MMIO_WRITE;
2153	#endif
2154	}
2155
2156	/**
2157	* Worker for writes to the BDPL and BDPU registers.
2158	*/
2159	DECLINLINE(VBOXSTRICTRC) hdaRegWriteSDBDPX(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value, uint8_t uSD)
2160	{
2161	RT_NOREF(uSD);
2162	return hdaRegWriteU32(pDevIns, pThis, iReg, u32Value);
2163	}
2164
2165	static VBOXSTRICTRC hdaRegWriteSDBDPL(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2166	{
2167	return hdaRegWriteSDBDPX(pDevIns, pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPL, iReg));
2168	}
2169
2170	static VBOXSTRICTRC hdaRegWriteSDBDPU(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2171	{
2172	return hdaRegWriteSDBDPX(pDevIns, pThis, iReg, u32Value, HDA_SD_NUM_FROM_REG(pThis, BDPU, iReg));
2173	}
2174
2175	/** Skylake specific. */
2176	static VBOXSTRICTRC hdaRegReadSDnPIB(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2177	{
2178	uint8_t const uSD = HDA_SD_NUM_FROM_SKYLAKE_REG(DPIB, iReg);
2179	LogFlowFunc(("uSD=%u -> SDnLPIB\n", uSD));
2180	return hdaRegReadLPIB(pDevIns, pThis, HDA_SD_TO_REG(LPIB, uSD), pu32Value);
2181	}
2182
2183	/** Skylake specific. */
2184	static VBOXSTRICTRC hdaRegReadSDnEFIFOS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2185	{
2186	/** @todo This is not implemented as I have found no specs yet. */
2187	RT_NOREF(pDevIns, pThis, iReg);
2188	LogFunc(("TODO - need register spec: uSD=%u\n", HDA_SD_NUM_FROM_SKYLAKE_REG(DPIB, iReg)));
2189	*pu32Value = 256;
2190	return VINF_SUCCESS;
2191	}
2192
2193
2194	static VBOXSTRICTRC hdaRegReadIRS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value)
2195	{
2196	/* regarding 3.4.3 we should mark IRS as busy in case CORB is active */
2197	if ( HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP)
2198	\|\| (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA))
2199	HDA_REG(pThis, IRS) = HDA_IRS_ICB; /* busy */
2200
2201	return hdaRegReadU32(pDevIns, pThis, iReg, pu32Value);
2202	}
2203
2204	static VBOXSTRICTRC hdaRegWriteIRS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2205	{
2206	RT_NOREF(pDevIns, iReg);
2207
2208	/*
2209	* If the guest set the ICB bit of IRS register, HDA should process the verb in IC register,
2210	* write the response to IR register, and set the IRV (valid in case of success) bit of IRS register.
2211	*/
2212	if ( (u32Value & HDA_IRS_ICB)
2213	&& !(HDA_REG(pThis, IRS) & HDA_IRS_ICB))
2214	{
2215	#ifdef IN_RING3
2216	uint32_t uCmd = HDA_REG(pThis, IC);
2217
2218	if (HDA_REG(pThis, CORBWP) != HDA_REG(pThis, CORBRP))
2219	{
2220	/*
2221	* 3.4.3: Defines behavior of immediate Command status register.
2222	*/
2223	LogRel(("HDA: Guest attempted process immediate verb (%x) with active CORB\n", uCmd));
2224	return VINF_SUCCESS;
2225	}
2226
2227	HDA_REG(pThis, IRS) = HDA_IRS_ICB; /* busy */
2228
2229	PHDASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
2230	uint64_t uResp = 0;
2231	int rc2 = hdaR3CodecLookup(&pThisCC->Codec, HDA_CODEC_CMD(uCmd, 0 /* LUN */), &uResp);
2232	if (RT_FAILURE(rc2))
2233	LogFunc(("Codec lookup failed with rc2=%Rrc\n", rc2));
2234
2235	HDA_REG(pThis, IR) = (uint32_t)uResp; /** @todo r=andy Do we need a 64-bit response? */
2236	HDA_REG(pThis, IRS) = HDA_IRS_IRV; /* result is ready */
2237	/** @todo r=michaln We just set the IRS value, why are we clearing unset bits? */
2238	HDA_REG(pThis, IRS) &= ~HDA_IRS_ICB; /* busy is clear */
2239
2240	return VINF_SUCCESS;
2241	#else /* !IN_RING3 */
2242	return VINF_IOM_R3_MMIO_WRITE;
2243	#endif /* !IN_RING3 */
2244	}
2245
2246	/*
2247	* Once the guest read the response, it should clear the IRV bit of the IRS register.
2248	*/
2249	HDA_REG(pThis, IRS) &= ~(u32Value & HDA_IRS_IRV);
2250	return VINF_SUCCESS;
2251	}
2252
2253	static VBOXSTRICTRC hdaRegWriteRIRBWP(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2254	{
2255	RT_NOREF(pDevIns, iReg);
2256
2257	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
2258	LogFunc(("CORB DMA (still) running, skipping\n"));
2259	else
2260	{
2261	if (u32Value & HDA_RIRBWP_RST)
2262	{
2263	/* Do a RIRB reset. */
2264	if (pThis->cbRirbBuf)
2265	RT_ZERO(pThis->au64RirbBuf);
2266
2267	LogRel2(("HDA: RIRB reset\n"));
2268
2269	HDA_REG(pThis, RIRBWP) = 0;
2270	}
2271	/* The remaining bits are O, see 6.2.22. */
2272	}
2273	return VINF_SUCCESS;
2274	}
2275
2276	static VBOXSTRICTRC hdaRegWriteRINTCNT(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2277	{
2278	RT_NOREF(pDevIns);
2279	if (HDA_REG(pThis, CORBCTL) & HDA_CORBCTL_DMA) /* Ignore request if CORB DMA engine is (still) running. */
2280	{
2281	LogFunc(("CORB DMA is (still) running, skipping\n"));
2282	return VINF_SUCCESS;
2283	}
2284
2285	VBOXSTRICTRC rc = hdaRegWriteU16(pDevIns, pThis, iReg, u32Value);
2286	AssertRC(VBOXSTRICTRC_VAL(rc));
2287
2288	/** @todo r=bird: Shouldn't we make sure the HDASTATE::u16RespIntCnt is below
2289	* the new RINTCNT value? Or alterantively, make the DMA look take
2290	* this into account instead... I'll do the later for now. */
2291
2292	LogFunc(("Response interrupt count is now %RU8\n", HDA_REG(pThis, RINTCNT) & 0xFF));
2293	return rc;
2294	}
2295
2296	static VBOXSTRICTRC hdaRegWriteBase(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2297	{
2298	RT_NOREF(pDevIns);
2299
2300	VBOXSTRICTRC rc = hdaRegWriteU32(pDevIns, pThis, iReg, u32Value);
2301	AssertRCSuccess(VBOXSTRICTRC_VAL(rc));
2302
2303	uint32_t const iRegMem = g_aHdaRegMap[iReg].idxReg;
2304	switch (iReg)
2305	{
2306	case HDA_REG_CORBLBASE:
2307	pThis->u64CORBBase &= UINT64_C(0xFFFFFFFF00000000);
2308	pThis->u64CORBBase \|= pThis->au32Regs[iRegMem];
2309	break;
2310	case HDA_REG_CORBUBASE:
2311	pThis->u64CORBBase &= UINT64_C(0x00000000FFFFFFFF);
2312	pThis->u64CORBBase \|= (uint64_t)pThis->au32Regs[iRegMem] << 32;
2313	break;
2314	case HDA_REG_RIRBLBASE:
2315	pThis->u64RIRBBase &= UINT64_C(0xFFFFFFFF00000000);
2316	pThis->u64RIRBBase \|= pThis->au32Regs[iRegMem];
2317	break;
2318	case HDA_REG_RIRBUBASE:
2319	pThis->u64RIRBBase &= UINT64_C(0x00000000FFFFFFFF);
2320	pThis->u64RIRBBase \|= (uint64_t)pThis->au32Regs[iRegMem] << 32;
2321	break;
2322	case HDA_REG_DPLBASE:
2323	pThis->u64DPBase = pThis->au32Regs[iRegMem] & DPBASE_ADDR_MASK;
2324	Assert(pThis->u64DPBase % 128 == 0); /* Must be 128-byte aligned. */
2325
2326	/* Also make sure to handle the DMA position enable bit. */
2327	pThis->fDMAPosition = pThis->au32Regs[iRegMem] & RT_BIT_32(0);
2328
2329	#ifndef IN_RING0
2330	LogRel(("HDA: DP base (lower) set: %#RGp\n", pThis->u64DPBase));
2331	LogRel(("HDA: DMA position buffer is %s\n", pThis->fDMAPosition ? "enabled" : "disabled"));
2332	#else
2333	return VINF_IOM_R3_MMIO_WRITE; /* (Go to ring-3 for release logging.) */
2334	#endif
2335	break;
2336	case HDA_REG_DPUBASE:
2337	pThis->u64DPBase = RT_MAKE_U64(RT_LO_U32(pThis->u64DPBase) & DPBASE_ADDR_MASK, pThis->au32Regs[iRegMem]);
2338	#ifndef IN_RING0
2339	LogRel(("HDA: DP base (upper) set: %#RGp\n", pThis->u64DPBase));
2340	#else
2341	return VINF_IOM_R3_MMIO_WRITE; /* (Go to ring-3 for release logging.) */
2342	#endif
2343	break;
2344	default:
2345	AssertMsgFailed(("Invalid index\n"));
2346	break;
2347	}
2348
2349	LogFunc(("CORB base:%llx RIRB base: %llx DP base: %llx\n",
2350	pThis->u64CORBBase, pThis->u64RIRBBase, pThis->u64DPBase));
2351	return rc;
2352	}
2353
2354	static VBOXSTRICTRC hdaRegWriteRIRBSTS(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value)
2355	{
2356	RT_NOREF(pDevIns, iReg);
2357
2358	uint8_t v = HDA_REG(pThis, RIRBSTS);
2359	HDA_REG(pThis, RIRBSTS) &= ~(v & u32Value);
2360
2361	HDA_PROCESS_INTERRUPT(pDevIns, pThis);
2362	return VINF_SUCCESS;
2363	}
2364
2365	#ifdef IN_RING3
2366
2367	/**
2368	* Retrieves a corresponding sink for a given mixer control.
2369	*
2370	* @return Pointer to the sink, NULL if no sink is found.
2371	* @param pThisCC The ring-3 HDA device state.
2372	* @param enmMixerCtl Mixer control to get the corresponding sink for.
2373	*/
2374	static PHDAMIXERSINK hdaR3MixerControlToSink(PHDASTATER3 pThisCC, PDMAUDIOMIXERCTL enmMixerCtl)
2375	{
2376	PHDAMIXERSINK pSink;
2377
2378	switch (enmMixerCtl)
2379	{
2380	case PDMAUDIOMIXERCTL_VOLUME_MASTER:
2381	/* Fall through is intentional. */
2382	case PDMAUDIOMIXERCTL_FRONT:
2383	pSink = &pThisCC->SinkFront;
2384	break;
2385	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2386	case PDMAUDIOMIXERCTL_CENTER_LFE:
2387	pSink = &pThisCC->SinkCenterLFE;
2388	break;
2389	case PDMAUDIOMIXERCTL_REAR:
2390	pSink = &pThisCC->SinkRear;
2391	break;
2392	# endif
2393	case PDMAUDIOMIXERCTL_LINE_IN:
2394	pSink = &pThisCC->SinkLineIn;
2395	break;
2396	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2397	case PDMAUDIOMIXERCTL_MIC_IN:
2398	pSink = &pThisCC->SinkMicIn;
2399	break;
2400	# endif
2401	default:
2402	AssertMsgFailed(("Unhandled mixer control\n"));
2403	pSink = NULL;
2404	break;
2405	}
2406
2407	return pSink;
2408	}
2409
2410	/**
2411	* Adds a specific HDA driver to the driver chain.
2412	*
2413	* @returns VBox status code.
2414	* @param pDevIns The HDA device instance.
2415	* @param pThisCC The ring-3 HDA device state.
2416	* @param pDrv HDA driver to add.
2417	*/
2418	static int hdaR3MixerAddDrv(PPDMDEVINS pDevIns, PHDASTATER3 pThisCC, PHDADRIVER pDrv)
2419	{
2420	int rc = VINF_SUCCESS;
2421
2422	PHDASTREAM pStream = pThisCC->SinkLineIn.pStreamShared;
2423	if ( pStream
2424	&& AudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2425	{
2426	int rc2 = hdaR3MixerAddDrvStream(pDevIns, pThisCC->SinkLineIn.pMixSink, &pStream->State.Cfg, pDrv);
2427	if (RT_SUCCESS(rc))
2428	rc = rc2;
2429	}
2430
2431	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2432	pStream = pThisCC->SinkMicIn.pStreamShared;
2433	if ( pStream
2434	&& AudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2435	{
2436	int rc2 = hdaR3MixerAddDrvStream(pDevIns, pThisCC->SinkMicIn.pMixSink, &pStream->State.Cfg, pDrv);
2437	if (RT_SUCCESS(rc))
2438	rc = rc2;
2439	}
2440	# endif
2441
2442	pStream = pThisCC->SinkFront.pStreamShared;
2443	if ( pStream
2444	&& AudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2445	{
2446	int rc2 = hdaR3MixerAddDrvStream(pDevIns, pThisCC->SinkFront.pMixSink, &pStream->State.Cfg, pDrv);
2447	if (RT_SUCCESS(rc))
2448	rc = rc2;
2449	}
2450
2451	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2452	pStream = pThisCC->SinkCenterLFE.pStreamShared;
2453	if ( pStream
2454	&& AudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2455	{
2456	int rc2 = hdaR3MixerAddDrvStream(pDevIns, pThisCC->SinkCenterLFE.pMixSink, &pStream->State.Cfg, pDrv);
2457	if (RT_SUCCESS(rc))
2458	rc = rc2;
2459	}
2460
2461	pStream = pThisCC->SinkRear.pStreamShared;
2462	if ( pStream
2463	&& AudioHlpStreamCfgIsValid(&pStream->State.Cfg))
2464	{
2465	int rc2 = hdaR3MixerAddDrvStream(pDevIns, pThisCC->SinkRear.pMixSink, &pStream->State.Cfg, pDrv);
2466	if (RT_SUCCESS(rc))
2467	rc = rc2;
2468	}
2469	# endif
2470
2471	return rc;
2472	}
2473
2474	/**
2475	* Removes a specific HDA driver from the driver chain and destroys its
2476	* associated streams.
2477	*
2478	* @param pDevIns The device instance.
2479	* @param pThisCC The ring-3 HDA device state.
2480	* @param pDrv HDA driver to remove.
2481	*/
2482	static void hdaR3MixerRemoveDrv(PPDMDEVINS pDevIns, PHDASTATER3 pThisCC, PHDADRIVER pDrv)
2483	{
2484	AssertPtrReturnVoid(pDrv);
2485
2486	if (pDrv->LineIn.pMixStrm)
2487	{
2488	AudioMixerSinkRemoveStream(pThisCC->SinkLineIn.pMixSink, pDrv->LineIn.pMixStrm);
2489	AudioMixerStreamDestroy(pDrv->LineIn.pMixStrm, pDevIns, true /fImmediate/);
2490	pDrv->LineIn.pMixStrm = NULL;
2491	}
2492
2493	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2494	if (pDrv->MicIn.pMixStrm)
2495	{
2496	AudioMixerSinkRemoveStream(pThisCC->SinkMicIn.pMixSink, pDrv->MicIn.pMixStrm);
2497	AudioMixerStreamDestroy(pDrv->MicIn.pMixStrm, pDevIns, true /fImmediate/);
2498	pDrv->MicIn.pMixStrm = NULL;
2499	}
2500	# endif
2501
2502	if (pDrv->Front.pMixStrm)
2503	{
2504	AudioMixerSinkRemoveStream(pThisCC->SinkFront.pMixSink, pDrv->Front.pMixStrm);
2505	AudioMixerStreamDestroy(pDrv->Front.pMixStrm, pDevIns, true /fImmediate/);
2506	pDrv->Front.pMixStrm = NULL;
2507	}
2508
2509	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2510	if (pDrv->CenterLFE.pMixStrm)
2511	{
2512	AudioMixerSinkRemoveStream(pThisCC->SinkCenterLFE.pMixSink, pDrv->CenterLFE.pMixStrm);
2513	AudioMixerStreamDestroy(pDrv->CenterLFE.pMixStrm, pDevIns, true /fImmediate/);
2514	pDrv->CenterLFE.pMixStrm = NULL;
2515	}
2516
2517	if (pDrv->Rear.pMixStrm)
2518	{
2519	AudioMixerSinkRemoveStream(pThisCC->SinkRear.pMixSink, pDrv->Rear.pMixStrm);
2520	AudioMixerStreamDestroy(pDrv->Rear.pMixStrm, pDevIns, true /fImmediate/);
2521	pDrv->Rear.pMixStrm = NULL;
2522	}
2523	# endif
2524
2525	RTListNodeRemove(&pDrv->Node);
2526	}
2527
2528	/**
2529	* Adds a driver stream to a specific mixer sink.
2530	*
2531	* @returns VBox status code (ignored by caller).
2532	* @param pDevIns The HDA device instance.
2533	* @param pMixSink Audio mixer sink to add audio streams to.
2534	* @param pCfg Audio stream configuration to use for the audio
2535	* streams to add.
2536	* @param pDrv Driver stream to add.
2537	*/
2538	static int hdaR3MixerAddDrvStream(PPDMDEVINS pDevIns, PAUDMIXSINK pMixSink, PCPDMAUDIOSTREAMCFG pCfg, PHDADRIVER pDrv)
2539	{
2540	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
2541	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2542
2543	LogFunc(("szSink=%s, szStream=%s, cChannels=%RU8\n", pMixSink->pszName, pCfg->szName, PDMAudioPropsChannels(&pCfg->Props)));
2544
2545	/*
2546	* Get the matching stream driver.
2547	*/
2548	PHDADRIVERSTREAM pDrvStream = NULL;
2549	if (pCfg->enmDir == PDMAUDIODIR_IN)
2550	{
2551	LogFunc(("enmPath=%d (src)\n", pCfg->enmPath));
2552	switch (pCfg->enmPath)
2553	{
2554	case PDMAUDIOPATH_IN_LINE:
2555	pDrvStream = &pDrv->LineIn;
2556	break;
2557	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2558	case PDMAUDIOPATH_IN_MIC:
2559	pDrvStream = &pDrv->MicIn;
2560	break;
2561	# endif
2562	default:
2563	LogFunc(("returns VERR_NOT_SUPPORTED - enmPath=%d\n", pCfg->enmPath));
2564	return VERR_NOT_SUPPORTED;
2565	}
2566	}
2567	else if (pCfg->enmDir == PDMAUDIODIR_OUT)
2568	{
2569	LogFunc(("enmDst=%d %s (dst)\n", pCfg->enmPath, PDMAudioPathGetName(pCfg->enmPath)));
2570	switch (pCfg->enmPath)
2571	{
2572	case PDMAUDIOPATH_OUT_FRONT:
2573	pDrvStream = &pDrv->Front;
2574	break;
2575	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2576	case PDMAUDIOPATH_OUT_CENTER_LFE:
2577	pDrvStream = &pDrv->CenterLFE;
2578	break;
2579	case PDMAUDIOPATH_OUT_REAR:
2580	pDrvStream = &pDrv->Rear;
2581	break;
2582	# endif
2583	default:
2584	LogFunc(("returns VERR_NOT_SUPPORTED - enmPath=%d %s\n", pCfg->enmPath, PDMAudioPathGetName(pCfg->enmPath)));
2585	return VERR_NOT_SUPPORTED;
2586	}
2587	}
2588	else
2589	AssertFailedReturn(VERR_NOT_SUPPORTED);
2590
2591	LogFunc(("[LUN#%RU8] %s\n", pDrv->uLUN, pCfg->szName));
2592
2593	AssertPtr(pDrvStream);
2594	AssertMsg(pDrvStream->pMixStrm == NULL, ("[LUN#%RU8] Driver stream already present when it must not\n", pDrv->uLUN));
2595
2596	PAUDMIXSTREAM pMixStrm = NULL;
2597	int rc = AudioMixerSinkCreateStream(pMixSink, pDrv->pConnector, pCfg, pDevIns, &pMixStrm);
2598	LogFlowFunc(("LUN#%RU8: Created stream \"%s\" for sink, rc=%Rrc\n", pDrv->uLUN, pCfg->szName, rc));
2599	if (RT_SUCCESS(rc))
2600	{
2601	rc = AudioMixerSinkAddStream(pMixSink, pMixStrm);
2602	LogFlowFunc(("LUN#%RU8: Added stream \"%s\" to sink, rc=%Rrc\n", pDrv->uLUN, pCfg->szName, rc));
2603	if (RT_FAILURE(rc))
2604	AudioMixerStreamDestroy(pMixStrm, pDevIns, true /fImmediate/);
2605	}
2606
2607	if (RT_SUCCESS(rc))
2608	pDrvStream->pMixStrm = pMixStrm;
2609
2610	LogFlowFuncLeaveRC(rc);
2611	return rc;
2612	}
2613
2614	/**
2615	* Adds all current driver streams to a specific mixer sink.
2616	*
2617	* @returns VBox status code.
2618	* @param pDevIns The HDA device instance.
2619	* @param pThisCC The ring-3 HDA device state.
2620	* @param pMixSink Audio mixer sink to add stream to.
2621	* @param pCfg Audio stream configuration to use for the audio streams
2622	* to add.
2623	*/
2624	static int hdaR3MixerAddDrvStreams(PPDMDEVINS pDevIns, PHDASTATER3 pThisCC, PAUDMIXSINK pMixSink, PCPDMAUDIOSTREAMCFG pCfg)
2625	{
2626	AssertPtrReturn(pMixSink, VERR_INVALID_POINTER);
2627	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2628
2629	LogFunc(("Sink=%s, Stream=%s\n", pMixSink->pszName, pCfg->szName));
2630
2631	int rc;
2632	if (AudioHlpStreamCfgIsValid(pCfg))
2633	{
2634	rc = AudioMixerSinkSetFormat(pMixSink, &pCfg->Props, pCfg->Device.cMsSchedulingHint);
2635	if (RT_SUCCESS(rc))
2636	{
2637	PHDADRIVER pDrv;
2638	RTListForEach(&pThisCC->lstDrv, pDrv, HDADRIVER, Node)
2639	{
2640	/* We ignore failures here because one non-working driver shouldn't
2641	be allowed to spoil it for everyone else. */
2642	int rc2 = hdaR3MixerAddDrvStream(pDevIns, pMixSink, pCfg, pDrv);
2643	if (RT_FAILURE(rc2))
2644	LogFunc(("Attaching stream failed with %Rrc (ignored)\n", rc2));
2645	}
2646	}
2647	}
2648	else
2649	rc = VERR_INVALID_PARAMETER;
2650	return rc;
2651	}
2652
2653
2654	/**
2655	* Adds a new audio stream to a specific mixer control.
2656	*
2657	* Depending on the mixer control the stream then gets assigned to one of the
2658	* internal mixer sinks, which in turn then handle the mixing of all connected
2659	* streams to that sink.
2660	*
2661	* @return VBox status code.
2662	* @param pCodec The codec instance data.
2663	* @param enmMixerCtl Mixer control to assign new stream to.
2664	* @param pCfg Stream configuration for the new stream.
2665	*/
2666	DECLHIDDEN(int) hdaR3MixerAddStream(PHDACODECR3 pCodec, PDMAUDIOMIXERCTL enmMixerCtl, PCPDMAUDIOSTREAMCFG pCfg)
2667	{
2668	PHDASTATER3 pThisCC = RT_FROM_MEMBER(pCodec, HDASTATER3, Codec);
2669	AssertPtrReturn(pCfg, VERR_INVALID_POINTER);
2670
2671	int rc;
2672	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThisCC, enmMixerCtl);
2673	if (pSink)
2674	{
2675	rc = hdaR3MixerAddDrvStreams(pThisCC->pDevIns, pThisCC, pSink->pMixSink, pCfg);
2676
2677	AssertPtr(pSink->pMixSink);
2678	LogFlowFunc(("Sink=%s, Mixer control=%s\n", pSink->pMixSink->pszName, PDMAudioMixerCtlGetName(enmMixerCtl)));
2679	}
2680	else
2681	rc = VERR_NOT_FOUND;
2682
2683	LogFlowFuncLeaveRC(rc);
2684	return rc;
2685	}
2686
2687	/**
2688	* Removes a specified mixer control from the HDA's mixer.
2689	*
2690	* @return VBox status code.
2691	* @param pCodec The codec instance data.
2692	* @param enmMixerCtl Mixer control to remove.
2693	* @param fImmediate Whether the backend should be allowed to
2694	* finished draining (@c false) or if it must be
2695	* destroyed immediately (@c true).
2696	*/
2697	DECLHIDDEN(int) hdaR3MixerRemoveStream(PHDACODECR3 pCodec, PDMAUDIOMIXERCTL enmMixerCtl, bool fImmediate)
2698	{
2699	PHDASTATER3 pThisCC = RT_FROM_MEMBER(pCodec, HDASTATER3, Codec);
2700	int rc;
2701
2702	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThisCC, enmMixerCtl);
2703	if (pSink)
2704	{
2705	PHDADRIVER pDrv;
2706	RTListForEach(&pThisCC->lstDrv, pDrv, HDADRIVER, Node)
2707	{
2708	PAUDMIXSTREAM pMixStream = NULL;
2709	switch (enmMixerCtl)
2710	{
2711	/*
2712	* Input.
2713	*/
2714	case PDMAUDIOMIXERCTL_LINE_IN:
2715	pMixStream = pDrv->LineIn.pMixStrm;
2716	pDrv->LineIn.pMixStrm = NULL;
2717	break;
2718	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
2719	case PDMAUDIOMIXERCTL_MIC_IN:
2720	pMixStream = pDrv->MicIn.pMixStrm;
2721	pDrv->MicIn.pMixStrm = NULL;
2722	break;
2723	# endif
2724	/*
2725	* Output.
2726	*/
2727	case PDMAUDIOMIXERCTL_FRONT:
2728	pMixStream = pDrv->Front.pMixStrm;
2729	pDrv->Front.pMixStrm = NULL;
2730	break;
2731	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
2732	case PDMAUDIOMIXERCTL_CENTER_LFE:
2733	pMixStream = pDrv->CenterLFE.pMixStrm;
2734	pDrv->CenterLFE.pMixStrm = NULL;
2735	break;
2736	case PDMAUDIOMIXERCTL_REAR:
2737	pMixStream = pDrv->Rear.pMixStrm;
2738	pDrv->Rear.pMixStrm = NULL;
2739	break;
2740	# endif
2741	default:
2742	AssertMsgFailed(("Mixer control %d not implemented\n", enmMixerCtl));
2743	break;
2744	}
2745
2746	if (pMixStream)
2747	{
2748	AudioMixerSinkRemoveStream(pSink->pMixSink, pMixStream);
2749	AudioMixerStreamDestroy(pMixStream, pThisCC->pDevIns, fImmediate);
2750
2751	pMixStream = NULL;
2752	}
2753	}
2754
2755	AudioMixerSinkRemoveAllStreams(pSink->pMixSink);
2756	rc = VINF_SUCCESS;
2757	}
2758	else
2759	rc = VERR_NOT_FOUND;
2760
2761	LogFunc(("Mixer control=%s, rc=%Rrc\n", PDMAudioMixerCtlGetName(enmMixerCtl), rc));
2762	return rc;
2763	}
2764
2765	/**
2766	* Controls an input / output converter widget, that is, which converter is
2767	* connected to which stream (and channel).
2768	*
2769	* @return VBox status code.
2770	* @param pCodec The codec instance data.
2771	* @param enmMixerCtl Mixer control to set SD stream number and channel for.
2772	* @param uSD SD stream number (number + 1) to set. Set to 0 for unassign.
2773	* @param uChannel Channel to set. Only valid if a valid SD stream number is specified.
2774	*
2775	* @note Is also called directly by the DevHDA code.
2776	*/
2777	DECLHIDDEN(int) hdaR3MixerControl(PHDACODECR3 pCodec, PDMAUDIOMIXERCTL enmMixerCtl, uint8_t uSD, uint8_t uChannel)
2778	{
2779	PHDASTATER3 pThisCC = RT_FROM_MEMBER(pCodec, HDASTATER3, Codec);
2780	PPDMDEVINS pDevIns = pThisCC->pDevIns;
2781	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
2782	LogFunc(("enmMixerCtl=%s, uSD=%RU8, uChannel=%RU8\n", PDMAudioMixerCtlGetName(enmMixerCtl), uSD, uChannel));
2783
2784	if (uSD == 0) /* Stream number 0 is reserved. */
2785	{
2786	Log2Func(("Invalid SDn (%RU8) number for mixer control '%s', ignoring\n", uSD, PDMAudioMixerCtlGetName(enmMixerCtl)));
2787	return VINF_SUCCESS;
2788	}
2789	/* uChannel is optional. */
2790
2791	/* SDn0 starts as 1. */
2792	Assert(uSD);
2793	uSD--;
2794
2795	# ifndef VBOX_WITH_AUDIO_HDA_MIC_IN
2796	/* Only SDI0 (Line-In) is supported. */
2797	if ( hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN
2798	&& uSD >= 1)
2799	{
2800	LogRel2(("HDA: Dedicated Mic-In support not imlpemented / built-in (stream #%RU8), using Line-In (stream #0) instead\n", uSD));
2801	uSD = 0;
2802	}
2803	# endif
2804
2805	int rc = VINF_SUCCESS;
2806
2807	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThisCC, enmMixerCtl);
2808	if (pSink)
2809	{
2810	AssertPtr(pSink->pMixSink);
2811
2812	/* If this an output stream, determine the correct SD#. */
2813	if ( uSD < HDA_MAX_SDI
2814	&& AudioMixerSinkGetDir(pSink->pMixSink) == PDMAUDIODIR_OUT)
2815	uSD += HDA_MAX_SDI;
2816
2817	/* Make 100% sure we got a good stream number before continuing. */
2818	AssertLogRelReturn(uSD < RT_ELEMENTS(pThisCC->aStreams), VERR_NOT_IMPLEMENTED);
2819
2820	/* Detach the existing stream from the sink. */
2821	PHDASTREAM const pOldStreamShared = pSink->pStreamShared;
2822	PHDASTREAMR3 const pOldStreamR3 = pSink->pStreamR3;
2823	if ( pOldStreamShared
2824	&& pOldStreamR3
2825	&& ( pOldStreamShared->u8SD != uSD
2826	\|\| pOldStreamShared->u8Channel != uChannel)
2827	)
2828	{
2829	LogFunc(("Sink '%s' was assigned to stream #%RU8 (channel %RU8) before\n",
2830	pSink->pMixSink->pszName, pOldStreamShared->u8SD, pOldStreamShared->u8Channel));
2831	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2832
2833	/* Only disable the stream if the stream descriptor # has changed. */
2834	if (pOldStreamShared->u8SD != uSD)
2835	hdaR3StreamEnable(pThis, pOldStreamShared, pOldStreamR3, false /fEnable/);
2836
2837	if (pOldStreamR3->State.pAioRegSink)
2838	{
2839	AudioMixerSinkRemoveUpdateJob(pOldStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pOldStreamR3);
2840	pOldStreamR3->State.pAioRegSink = NULL;
2841	}
2842
2843	pOldStreamR3->pMixSink = NULL;
2844
2845
2846	pSink->pStreamShared = NULL;
2847	pSink->pStreamR3 = NULL;
2848	}
2849
2850	/* Attach the new stream to the sink.
2851	* Enabling the stream will be done by the guest via a separate SDnCTL call then. */
2852	if (pSink->pStreamShared == NULL)
2853	{
2854	LogRel2(("HDA: Setting sink '%s' to stream #%RU8 (channel %RU8), mixer control=%s\n",
2855	pSink->pMixSink->pszName, uSD, uChannel, PDMAudioMixerCtlGetName(enmMixerCtl)));
2856
2857	PHDASTREAMR3 pStreamR3 = &pThisCC->aStreams[uSD];
2858	PHDASTREAM pStreamShared = &pThis->aStreams[uSD];
2859	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2860
2861	pSink->pStreamR3 = pStreamR3;
2862	pSink->pStreamShared = pStreamShared;
2863
2864	pStreamShared->u8Channel = uChannel;
2865	pStreamR3->pMixSink = pSink;
2866
2867	rc = VINF_SUCCESS;
2868	}
2869	}
2870	else
2871	rc = VERR_NOT_FOUND;
2872
2873	if (RT_FAILURE(rc))
2874	LogRel(("HDA: Converter control for stream #%RU8 (channel %RU8) / mixer control '%s' failed with %Rrc, skipping\n",
2875	uSD, uChannel, PDMAudioMixerCtlGetName(enmMixerCtl), rc));
2876
2877	LogFlowFuncLeaveRC(rc);
2878	return rc;
2879	}
2880
2881	/**
2882	* Sets the volume of a specified mixer control.
2883	*
2884	* @return IPRT status code.
2885	* @param pCodec The codec instance data.
2886	* @param enmMixerCtl Mixer control to set volume for.
2887	* @param pVol Pointer to volume data to set.
2888	*/
2889	DECLHIDDEN(int) hdaR3MixerSetVolume(PHDACODECR3 pCodec, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOVOLUME pVol)
2890	{
2891	PHDASTATER3 pThisCC = RT_FROM_MEMBER(pCodec, HDASTATER3, Codec);
2892	int rc;
2893
2894	PHDAMIXERSINK pSink = hdaR3MixerControlToSink(pThisCC, enmMixerCtl);
2895	if ( pSink
2896	&& pSink->pMixSink)
2897	{
2898	LogRel2(("HDA: Setting volume for mixer sink '%s' to fMuted=%RTbool auChannels=%.*Rhxs\n",
2899	pSink->pMixSink->pszName, pVol->fMuted, sizeof(pVol->auChannels), pVol->auChannels));
2900
2901	/* Set the volume.
2902	* We assume that the codec already converted it to the correct range. */
2903	rc = AudioMixerSinkSetVolume(pSink->pMixSink, pVol);
2904	}
2905	else
2906	rc = VERR_NOT_FOUND;
2907
2908	LogFlowFuncLeaveRC(rc);
2909	return rc;
2910	}
2911
2912	/**
2913	* @callback_method_impl{FNTMTIMERDEV, Main routine for the stream's timer.}
2914	*/
2915	static DECLCALLBACK(void) hdaR3Timer(PPDMDEVINS pDevIns, TMTIMERHANDLE hTimer, void *pvUser)
2916	{
2917	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
2918	PHDASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
2919	uintptr_t idxStream = (uintptr_t)pvUser;
2920	AssertReturnVoid(idxStream < RT_ELEMENTS(pThis->aStreams));
2921	PHDASTREAM pStreamShared = &pThis->aStreams[idxStream];
2922	PHDASTREAMR3 pStreamR3 = &pThisCC->aStreams[idxStream];
2923	Assert(hTimer == pStreamShared->hTimer);
2924
2925	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2926	Assert(PDMDevHlpTimerIsLockOwner(pDevIns, hTimer));
2927
2928	RT_NOREF(hTimer);
2929
2930	hdaR3StreamTimerMain(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3);
2931	}
2932
2933	/**
2934	* Soft reset of the device triggered via GCTL.
2935	*
2936	* @param pDevIns The device instance.
2937	* @param pThis The shared HDA device state.
2938	* @param pThisCC The ring-3 HDA device state.
2939	*/
2940	static void hdaR3GCTLReset(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC)
2941	{
2942	LogFlowFuncEnter();
2943	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2944
2945	/*
2946	* Make sure all streams have stopped as these have both timers and
2947	* asynchronous worker threads that would race us if we delay this work.
2948	*/
2949	for (size_t idxStream = 0; idxStream < RT_ELEMENTS(pThis->aStreams); idxStream++)
2950	{
2951	PHDASTREAM const pStreamShared = &pThis->aStreams[idxStream];
2952	PHDASTREAMR3 const pStreamR3 = &pThisCC->aStreams[idxStream];
2953	PAUDMIXSINK const pMixSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
2954	if (pMixSink)
2955	AudioMixerSinkLock(pMixSink);
2956
2957	/* We're doing this unconditionally, hope that's not problematic in any way... */
2958	int rc = hdaR3StreamEnable(pThis, pStreamShared, &pThisCC->aStreams[idxStream], false /* fEnable */);
2959	AssertLogRelMsg(RT_SUCCESS(rc) && !pStreamShared->State.fRunning,
2960	("Disabling stream #%u failed: %Rrc, fRunning=%d\n", idxStream, rc, pStreamShared->State.fRunning));
2961	pStreamShared->State.fRunning = false;
2962
2963	hdaR3StreamReset(pThis, pThisCC, pStreamShared, &pThisCC->aStreams[idxStream], (uint8_t)idxStream);
2964
2965	if (pMixSink) /* (FYI. pMixSink might not be what pStreamR3->pMixSink->pMixSink points at any longer) */
2966	AudioMixerSinkUnlock(pMixSink);
2967	}
2968
2969	/*
2970	* Reset registers.
2971	*/
2972	HDA_REG(pThis, GCAP) = HDA_MAKE_GCAP(HDA_MAX_SDO, HDA_MAX_SDI, 0, 0, 1); /* see 6.2.1 */
2973	HDA_REG(pThis, VMIN) = 0x00; /* see 6.2.2 */
2974	HDA_REG(pThis, VMAJ) = 0x01; /* see 6.2.3 */
2975	HDA_REG(pThis, OUTPAY) = 0x003C; /* see 6.2.4 */
2976	HDA_REG(pThis, INPAY) = 0x001D; /* see 6.2.5 */
2977	HDA_REG(pThis, CORBSIZE) = 0x42; /* Up to 256 CORB entries see 6.2.1 */
2978	HDA_REG(pThis, RIRBSIZE) = 0x42; /* Up to 256 RIRB entries see 6.2.1 */
2979	HDA_REG(pThis, CORBRP) = 0x0;
2980	HDA_REG(pThis, CORBWP) = 0x0;
2981	HDA_REG(pThis, RIRBWP) = 0x0;
2982	/* Some guests (like Haiku) don't set RINTCNT explicitly but expect an interrupt after each
2983	* RIRB response -- so initialize RINTCNT to 1 by default. */
2984	HDA_REG(pThis, RINTCNT) = 0x1;
2985	/* For newer devices, there is a capability list offset word at 0x14, linux read it, does
2986	no checking and simply reads the dword it specifies. The list terminates when the lower
2987	16 bits are zero. See snd_hdac_bus_parse_capabilities. Table 5-2 in intel 341081-002
2988	specifies this to be 0xc00 and chaining with 0x800, 0x500 and 0x1f00. We just terminate
2989	it at 0xc00 for now. */
2990	HDA_REG(pThis, LLCH) = 0xc00;
2991	HDA_REG(pThis, MLCH) = 0x0;
2992	HDA_REG(pThis, MLCD) = 0x0;
2993
2994	/*
2995	* Stop any audio currently playing and/or recording.
2996	*/
2997	pThisCC->SinkFront.pStreamShared = NULL;
2998	pThisCC->SinkFront.pStreamR3 = NULL;
2999	if (pThisCC->SinkFront.pMixSink)
3000	AudioMixerSinkReset(pThisCC->SinkFront.pMixSink);
3001	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3002	pThisCC->SinkMicIn.pStreamShared = NULL;
3003	pThisCC->SinkMicIn.pStreamR3 = NULL;
3004	if (pThisCC->SinkMicIn.pMixSink)
3005	AudioMixerSinkReset(pThisCC->SinkMicIn.pMixSink);
3006	# endif
3007	pThisCC->SinkLineIn.pStreamShared = NULL;
3008	pThisCC->SinkLineIn.pStreamR3 = NULL;
3009	if (pThisCC->SinkLineIn.pMixSink)
3010	AudioMixerSinkReset(pThisCC->SinkLineIn.pMixSink);
3011	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3012	pThisCC->SinkCenterLFE = NULL;
3013	if (pThisCC->SinkCenterLFE.pMixSink)
3014	AudioMixerSinkReset(pThisCC->SinkCenterLFE.pMixSink);
3015	pThisCC->SinkRear.pStreamShared = NULL;
3016	pThisCC->SinkRear.pStreamR3 = NULL;
3017	if (pThisCC->SinkRear.pMixSink)
3018	AudioMixerSinkReset(pThisCC->SinkRear.pMixSink);
3019	# endif
3020
3021	/*
3022	* Reset the codec.
3023	*/
3024	hdaCodecReset(&pThisCC->Codec);
3025
3026	/*
3027	* Set some sensible defaults for which HDA sinks
3028	* are connected to which stream number.
3029	*
3030	* We use SD0 for input and SD4 for output by default.
3031	* These stream numbers can be changed by the guest dynamically lateron.
3032	*/
3033	ASMCompilerBarrier(); /* paranoia */
3034	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
3035	hdaR3MixerControl(&pThisCC->Codec, PDMAUDIOMIXERCTL_MIC_IN , 1 /* SD0 /, 0 / Channel */);
3036	# endif
3037	hdaR3MixerControl(&pThisCC->Codec, PDMAUDIOMIXERCTL_LINE_IN , 1 /* SD0 /, 0 / Channel */);
3038
3039	hdaR3MixerControl(&pThisCC->Codec, PDMAUDIOMIXERCTL_FRONT , 5 /* SD4 /, 0 / Channel */);
3040	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
3041	hdaR3MixerControl(&pThisCC->Codec, PDMAUDIOMIXERCTL_CENTER_LFE, 5 /* SD4 /, 0 / Channel */);
3042	hdaR3MixerControl(&pThisCC->Codec, PDMAUDIOMIXERCTL_REAR , 5 /* SD4 /, 0 / Channel */);
3043	# endif
3044	ASMCompilerBarrier(); /* paranoia */
3045
3046	/* Reset CORB. */
3047	pThis->cbCorbBuf = HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE;
3048	RT_ZERO(pThis->au32CorbBuf);
3049
3050	/* Reset RIRB. */
3051	pThis->cbRirbBuf = HDA_RIRB_SIZE * HDA_RIRB_ELEMENT_SIZE;
3052	RT_ZERO(pThis->au64RirbBuf);
3053
3054	/* Clear our internal response interrupt counter. */
3055	pThis->u16RespIntCnt = 0;
3056
3057	/* Clear stream tags <-> objects mapping table. */
3058	RT_ZERO(pThisCC->aTags);
3059
3060	/* Emulation of codec "wake up" (HDA spec 5.5.1 and 6.5). */
3061	HDA_REG(pThis, STATESTS) = 0x1;
3062
3063	/* Reset the wall clock. */
3064	pThis->tsWalClkStart = PDMDevHlpTimerGet(pDevIns, pThis->aStreams[0].hTimer);
3065
3066	LogFlowFuncLeave();
3067	LogRel(("HDA: Reset\n"));
3068	}
3069
3070	#else /* !IN_RING3 */
3071
3072	/**
3073	* Checks if a dword read starting with @a idxRegDsc is safe.
3074	*
3075	* We can guarentee it only standard reader callbacks are used.
3076	* @returns true if it will always succeed, false if it may return back to
3077	* ring-3 or we're just not sure.
3078	* @param idxRegDsc The first register descriptor in the DWORD being read.
3079	*/
3080	DECLINLINE(bool) hdaIsMultiReadSafeInRZ(unsigned idxRegDsc)
3081	{
3082	int32_t cbLeft = 4; /* signed on purpose */
3083	do
3084	{
3085	if ( g_aHdaRegMap[idxRegDsc].pfnRead == hdaRegReadU24
3086	\|\| g_aHdaRegMap[idxRegDsc].pfnRead == hdaRegReadU16
3087	\|\| g_aHdaRegMap[idxRegDsc].pfnRead == hdaRegReadU8
3088	\|\| g_aHdaRegMap[idxRegDsc].pfnRead == hdaRegReadUnimpl)
3089	{ /* okay */ }
3090	else
3091	{
3092	Log4(("hdaIsMultiReadSafeInRZ: idxRegDsc=%u %s\n", idxRegDsc, g_aHdaRegMap[idxRegDsc].pszName));
3093	return false;
3094	}
3095
3096	idxRegDsc++;
3097	if (idxRegDsc < RT_ELEMENTS(g_aHdaRegMap))
3098	cbLeft -= g_aHdaRegMap[idxRegDsc].off - g_aHdaRegMap[idxRegDsc - 1].off;
3099	else
3100	break;
3101	} while (cbLeft > 0);
3102	return true;
3103	}
3104
3105
3106	#endif /* !IN_RING3 */
3107
3108
3109	/* MMIO callbacks */
3110
3111	/**
3112	* @callback_method_impl{FNIOMMMIONEWREAD, Looks up and calls the appropriate handler.}
3113	*
3114	* @note During implementation, we discovered so-called "forgotten" or "hole"
3115	* registers whose description is not listed in the RPM, datasheet, or
3116	* spec.
3117	*/
3118	static DECLCALLBACK(VBOXSTRICTRC) hdaMmioRead(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void pv, unsigned cb)
3119	{
3120	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
3121	VBOXSTRICTRC rc;
3122	RT_NOREF_PV(pvUser);
3123	Assert(pThis->uAlignmentCheckMagic == HDASTATE_ALIGNMENT_CHECK_MAGIC);
3124
3125	/*
3126	* Look up and log.
3127	*/
3128	int idxRegDsc = hdaRegLookup(off); /* Register descriptor index. */
3129	#ifdef LOG_ENABLED
3130	unsigned const cbLog = cb;
3131	uint32_t offRegLog = (uint32_t)off;
3132	# ifdef HDA_DEBUG_GUEST_RIP
3133	if (LogIs6Enabled())
3134	{
3135	PVMCPU pVCpu = (PVMCPU)PDMDevHlpGetVMCPU(pDevIns);
3136	Log6Func(("cs:rip=%04x:%016RX64 rflags=%08RX32\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestRIP(pVCpu), CPUMGetGuestEFlags(pVCpu)));
3137	}
3138	# endif
3139	#endif
3140
3141	Log3Func(("off=%#x cb=%#x\n", offRegLog, cb));
3142	Assert(cb == 4); Assert((off & 3) == 0);
3143
3144	rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VINF_IOM_R3_MMIO_READ);
3145	if (rc == VINF_SUCCESS)
3146	{
3147	if (!(HDA_REG(pThis, GCTL) & HDA_GCTL_CRST) && idxRegDsc != HDA_REG_GCTL)
3148	LogFunc(("Access to registers except GCTL is blocked while resetting\n"));
3149
3150	if (idxRegDsc >= 0)
3151	{
3152	/* ASSUMES gapless DWORD at end of map. */
3153	if (g_aHdaRegMap[idxRegDsc].cb == 4)
3154	{
3155	/*
3156	* Straight forward DWORD access.
3157	*/
3158	rc = g_aHdaRegMap[idxRegDsc].pfnRead(pDevIns, pThis, idxRegDsc, (uint32_t *)pv);
3159	Log3Func((" Read %s => %x (%Rrc)\n", g_aHdaRegMap[idxRegDsc].pszName, (uint32_t )pv, VBOXSTRICTRC_VAL(rc)));
3160	STAM_COUNTER_INC(&pThis->aStatRegReads[idxRegDsc]);
3161	}
3162	#ifndef IN_RING3
3163	else if (!hdaIsMultiReadSafeInRZ(idxRegDsc))
3164
3165	{
3166	STAM_COUNTER_INC(&pThis->aStatRegReadsToR3[idxRegDsc]);
3167	rc = VINF_IOM_R3_MMIO_READ;
3168	}
3169	#endif
3170	else
3171	{
3172	/*
3173	* Multi register read (unless there are trailing gaps).
3174	* ASSUMES that only DWORD reads have sideeffects.
3175	*/
3176	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatRegMultiReads));
3177	Log4(("hdaMmioRead: multi read: %#x LB %#x %s\n", off, cb, g_aHdaRegMap[idxRegDsc].pszName));
3178	uint32_t u32Value = 0;
3179	unsigned cbLeft = 4;
3180	do
3181	{
3182	uint32_t const cbReg = g_aHdaRegMap[idxRegDsc].cb;
3183	uint32_t u32Tmp = 0;
3184
3185	rc = g_aHdaRegMap[idxRegDsc].pfnRead(pDevIns, pThis, idxRegDsc, &u32Tmp);
3186	Log4Func((" Read %s[%db] => %x (%Rrc)*\n", g_aHdaRegMap[idxRegDsc].pszName, cbReg, u32Tmp, VBOXSTRICTRC_VAL(rc)));
3187	STAM_COUNTER_INC(&pThis->aStatRegReads[idxRegDsc]);
3188	#ifdef IN_RING3
3189	if (rc != VINF_SUCCESS)
3190	break;
3191	#else
3192	AssertMsgBreak(rc == VINF_SUCCESS, ("rc=%Rrc - impossible, we sanitized the readers!\n", VBOXSTRICTRC_VAL(rc)));
3193	#endif
3194	u32Value \|= (u32Tmp & g_afMasks[cbReg]) << ((4 - cbLeft) * 8);
3195
3196	cbLeft -= cbReg;
3197	off += cbReg;
3198	idxRegDsc++;
3199	} while (cbLeft > 0 && g_aHdaRegMap[idxRegDsc].off == off);
3200
3201	if (rc == VINF_SUCCESS)
3202	(uint32_t )pv = u32Value;
3203	else
3204	Assert(!IOM_SUCCESS(rc));
3205	}
3206	}
3207	else
3208	{
3209	LogRel(("HDA: Invalid read access @0x%x (bytes=%u)\n", (uint32_t)off, cb));
3210	Log3Func((" Hole at %x is accessed for read\n", offRegLog));
3211	STAM_COUNTER_INC(&pThis->StatRegUnknownReads);
3212	rc = VINF_IOM_MMIO_UNUSED_FF;
3213	}
3214
3215	DEVHDA_UNLOCK(pDevIns, pThis);
3216
3217	/*
3218	* Log the outcome.
3219	*/
3220	#ifdef LOG_ENABLED
3221	if (cbLog == 4)
3222	Log3Func((" Returning @%#05x -> %#010x %Rrc\n", offRegLog, (uint32_t )pv, VBOXSTRICTRC_VAL(rc)));
3223	else if (cbLog == 2)
3224	Log3Func((" Returning @%#05x -> %#06x %Rrc\n", offRegLog, (uint16_t )pv, VBOXSTRICTRC_VAL(rc)));
3225	else if (cbLog == 1)
3226	Log3Func((" Returning @%#05x -> %#04x %Rrc\n", offRegLog, (uint8_t )pv, VBOXSTRICTRC_VAL(rc)));
3227	#endif
3228	}
3229	else
3230	{
3231	if (idxRegDsc >= 0)
3232	STAM_COUNTER_INC(&pThis->aStatRegReadsToR3[idxRegDsc]);
3233	}
3234	return rc;
3235	}
3236
3237
3238	DECLINLINE(VBOXSTRICTRC) hdaWriteReg(PPDMDEVINS pDevIns, PHDASTATE pThis, int idxRegDsc, uint32_t u32Value, char const *pszLog)
3239	{
3240	if ( (HDA_REG(pThis, GCTL) & HDA_GCTL_CRST)
3241	\|\| idxRegDsc == HDA_REG_GCTL)
3242	{ /* likely */ }
3243	else
3244	{
3245	Log(("hdaWriteReg: Warning: Access to %s is blocked while controller is in reset mode\n", g_aHdaRegMap[idxRegDsc].pszName));
3246	#if defined(IN_RING3) \|\| defined(LOG_ENABLED)
3247	LogRel2(("HDA: Warning: Access to register %s is blocked while controller is in reset mode\n",
3248	g_aHdaRegMap[idxRegDsc].pszName));
3249	#endif
3250	STAM_COUNTER_INC(&pThis->StatRegWritesBlockedByReset);
3251	return VINF_SUCCESS;
3252	}
3253
3254	/*
3255	* Handle RD (register description) flags.
3256	*/
3257
3258	/* For SDI / SDO: Check if writes to those registers are allowed while SDCTL's RUN bit is set. */
3259	if (idxRegDsc >= HDA_NUM_GENERAL_REGS)
3260	{
3261	/*
3262	* Some OSes (like Win 10 AU) violate the spec by writing stuff to registers which are not supposed to be be touched
3263	* while SDCTL's RUN bit is set. So just ignore those values.
3264	*/
3265	const uint32_t uSDCTL = HDA_STREAM_REG(pThis, CTL, HDA_SD_NUM_FROM_REG(pThis, CTL, idxRegDsc));
3266	if ( !(uSDCTL & HDA_SDCTL_RUN)
3267	\|\| (g_aHdaRegMap[idxRegDsc].fFlags & HDA_RD_F_SD_WRITE_RUN))
3268	{ /* likely */ }
3269	else
3270	{
3271	Log(("hdaWriteReg: Warning: Access to %s is blocked! %R[sdctl]\n", g_aHdaRegMap[idxRegDsc].pszName, uSDCTL));
3272	#if defined(IN_RING3) \|\| defined(LOG_ENABLED)
3273	LogRel2(("HDA: Warning: Access to register %s is blocked while the stream's RUN bit is set\n",
3274	g_aHdaRegMap[idxRegDsc].pszName));
3275	#endif
3276	STAM_COUNTER_INC(&pThis->StatRegWritesBlockedByRun);
3277	return VINF_SUCCESS;
3278	}
3279	}
3280
3281	#ifdef LOG_ENABLED
3282	uint32_t const idxRegMem = g_aHdaRegMap[idxRegDsc].idxReg;
3283	uint32_t const u32OldValue = pThis->au32Regs[idxRegMem];
3284	#endif
3285	VBOXSTRICTRC rc = g_aHdaRegMap[idxRegDsc].pfnWrite(pDevIns, pThis, idxRegDsc, u32Value);
3286	Log3Func(("Written value %#x to %s[%d byte]; %x => %x%s, rc=%d\n", u32Value, g_aHdaRegMap[idxRegDsc].pszName,
3287	g_aHdaRegMap[idxRegDsc].cb, u32OldValue, pThis->au32Regs[idxRegMem], pszLog, VBOXSTRICTRC_VAL(rc)));
3288	#ifndef IN_RING3
3289	if (rc == VINF_IOM_R3_MMIO_WRITE)
3290	STAM_COUNTER_INC(&pThis->aStatRegWritesToR3[idxRegDsc]);
3291	else
3292	#endif
3293	STAM_COUNTER_INC(&pThis->aStatRegWrites[idxRegDsc]);
3294
3295	RT_NOREF(pszLog);
3296	return rc;
3297	}
3298
3299
3300	/**
3301	* @callback_method_impl{FNIOMMMIONEWWRITE,
3302	* Looks up and calls the appropriate handler.}
3303	*/
3304	static DECLCALLBACK(VBOXSTRICTRC) hdaMmioWrite(PPDMDEVINS pDevIns, void pvUser, RTGCPHYS off, void const pv, unsigned cb)
3305	{
3306	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
3307	RT_NOREF_PV(pvUser);
3308	Assert(pThis->uAlignmentCheckMagic == HDASTATE_ALIGNMENT_CHECK_MAGIC);
3309
3310	/*
3311	* Look up and log the access.
3312	*/
3313	int idxRegDsc = hdaRegLookup(off);
3314	#if defined(IN_RING3) \|\| defined(LOG_ENABLED)
3315	uint32_t idxRegMem = idxRegDsc != -1 ? g_aHdaRegMap[idxRegDsc].idxReg : UINT32_MAX;
3316	#endif
3317	uint64_t u64Value;
3318	if (cb == 4) u64Value = (uint32_t const )pv;
3319	else if (cb == 2) u64Value = (uint16_t const )pv;
3320	else if (cb == 1) u64Value = (uint8_t const )pv;
3321	else if (cb == 8) u64Value = (uint64_t const )pv;
3322	else
3323	ASSERT_GUEST_MSG_FAILED_RETURN(("cb=%u %.*Rhxs\n", cb, cb, pv),
3324	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "odd write size: off=%RGp cb=%u\n", off, cb));
3325
3326	/*
3327	* The behavior of accesses that aren't aligned on natural boundraries is
3328	* undefined. Just reject them outright.
3329	*/
3330	ASSERT_GUEST_MSG_RETURN((off & (cb - 1)) == 0, ("off=%RGp cb=%u %.*Rhxs\n", off, cb, cb, pv),
3331	PDMDevHlpDBGFStop(pDevIns, RT_SRC_POS, "misaligned write access: off=%RGp cb=%u\n", off, cb));
3332
3333	#ifdef LOG_ENABLED
3334	uint32_t const u32LogOldValue = idxRegDsc >= 0 ? pThis->au32Regs[idxRegMem] : UINT32_MAX;
3335	# ifdef HDA_DEBUG_GUEST_RIP
3336	if (LogIs6Enabled())
3337	{
3338	PVMCPU pVCpu = (PVMCPU)PDMDevHlpGetVMCPU(pDevIns);
3339	Log6Func(("cs:rip=%04x:%016RX64 rflags=%08RX32\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestRIP(pVCpu), CPUMGetGuestEFlags(pVCpu)));
3340	}
3341	# endif
3342	#endif
3343
3344	/*
3345	* Try for a direct hit first.
3346	*/
3347	VBOXSTRICTRC rc;
3348	if (idxRegDsc >= 0 && g_aHdaRegMap[idxRegDsc].cb == cb)
3349	{
3350	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE);
3351
3352	Log3Func(("@%#05x u%u=%#0RX64 %s\n", (uint32_t)off, cb 8, 2 + cb * 2, u64Value, g_aHdaRegMap[idxRegDsc].pszName));
3353	rc = hdaWriteReg(pDevIns, pThis, idxRegDsc, u64Value, "");
3354	Log3Func((" %#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
3355
3356	DEVHDA_UNLOCK(pDevIns, pThis);
3357	}
3358	/*
3359	* Sub-register access. Supply missing bits as needed.
3360	*/
3361	else if ( idxRegDsc >= 0
3362	&& cb < g_aHdaRegMap[idxRegDsc].cb)
3363	{
3364	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE);
3365
3366	u64Value \|= pThis->au32Regs[g_aHdaRegMap[idxRegDsc].idxReg]
3367	& g_afMasks[g_aHdaRegMap[idxRegDsc].cb]
3368	& ~g_afMasks[cb];
3369	Log4Func(("@%#05x u%u=%#0*RX64 cb=%#x cbReg=%x %s\n"
3370	"hdaMmioWrite: Supplying missing bits (%#x): %#llx -> %#llx ...\n",
3371	(uint32_t)off, cb * 8, 2 + cb * 2, u64Value, cb, g_aHdaRegMap[idxRegDsc].cb, g_aHdaRegMap[idxRegDsc].pszName,
3372	g_afMasks[g_aHdaRegMap[idxRegDsc].cb] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
3373	rc = hdaWriteReg(pDevIns, pThis, idxRegDsc, u64Value, "");
3374	Log4Func((" %#x -> %#x\n", u32LogOldValue, idxRegMem != UINT32_MAX ? pThis->au32Regs[idxRegMem] : UINT32_MAX));
3375	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatRegSubWrite));
3376
3377	DEVHDA_UNLOCK(pDevIns, pThis);
3378	}
3379	/*
3380	* Partial or multiple register access, loop thru the requested memory.
3381	*/
3382	else
3383	{
3384	#ifdef IN_RING3
3385	DEVHDA_LOCK_RETURN(pDevIns, pThis, VINF_IOM_R3_MMIO_WRITE);
3386
3387	if (idxRegDsc == -1)
3388	Log4Func(("@%#05x u32=%#010x cb=%d\n", (uint32_t)off, (uint32_t const )pv, cb));
3389	else if (g_aHdaRegMap[idxRegDsc].cb == cb)
3390	Log4Func(("@%#05x u%u=%#0RX64 %s\n", (uint32_t)off, cb 8, 2 + cb * 2, u64Value, g_aHdaRegMap[idxRegDsc].pszName));
3391	else
3392	Log4Func(("@%#05x u%u=%#0RX64 %s - mismatch cbReg=%u\n", (uint32_t)off, cb 8, 2 + cb * 2, u64Value,
3393	g_aHdaRegMap[idxRegDsc].pszName, g_aHdaRegMap[idxRegDsc].cb));
3394
3395	/*
3396	* If it's an access beyond the start of the register, shift the input
3397	* value and fill in missing bits. Natural alignment rules means we
3398	* will only see 1 or 2 byte accesses of this kind, so no risk of
3399	* shifting out input values.
3400	*/
3401	if (idxRegDsc < 0)
3402	{
3403	idxRegDsc = hdaR3RegLookupWithin(off);
3404	if (idxRegDsc != -1)
3405	{
3406	uint32_t const cbBefore = (uint32_t)off - g_aHdaRegMap[idxRegDsc].off;
3407	Assert(cbBefore > 0 && cbBefore < 4);
3408	off -= cbBefore;
3409	idxRegMem = g_aHdaRegMap[idxRegDsc].idxReg;
3410	u64Value <<= cbBefore * 8;
3411	u64Value \|= pThis->au32Regs[idxRegMem] & g_afMasks[cbBefore];
3412	Log4Func((" Within register, supplied %u leading bits: %#llx -> %#llx ...\n",
3413	cbBefore * 8, ~(uint64_t)g_afMasks[cbBefore] & u64Value, u64Value));
3414	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatRegMultiWrites));
3415	}
3416	else
3417	STAM_COUNTER_INC(&pThis->StatRegUnknownWrites);
3418	}
3419	else
3420	{
3421	Log4(("hdaMmioWrite: multi write: %s\n", g_aHdaRegMap[idxRegDsc].pszName));
3422	STAM_COUNTER_INC(&pThis->CTX_SUFF_Z(StatRegMultiWrites));
3423	}
3424
3425	/* Loop thru the write area, it may cover multiple registers. */
3426	rc = VINF_SUCCESS;
3427	for (;;)
3428	{
3429	uint32_t cbReg;
3430	if (idxRegDsc >= 0)
3431	{
3432	idxRegMem = g_aHdaRegMap[idxRegDsc].idxReg;
3433	cbReg = g_aHdaRegMap[idxRegDsc].cb;
3434	if (cb < cbReg)
3435	{
3436	u64Value \|= pThis->au32Regs[idxRegMem] & g_afMasks[cbReg] & ~g_afMasks[cb];
3437	Log4Func((" Supplying missing bits (%#x): %#llx -> %#llx ...\n",
3438	g_afMasks[cbReg] & ~g_afMasks[cb], u64Value & g_afMasks[cb], u64Value));
3439	}
3440	# ifdef LOG_ENABLED
3441	uint32_t uLogOldVal = pThis->au32Regs[idxRegMem];
3442	# endif
3443	rc = hdaWriteReg(pDevIns, pThis, idxRegDsc, u64Value & g_afMasks[cbReg], "*");
3444	Log4Func((" %#x -> %#x\n", uLogOldVal, pThis->au32Regs[idxRegMem]));
3445	}
3446	else
3447	{
3448	LogRel(("HDA: Invalid write access @0x%x\n", (uint32_t)off));
3449	cbReg = 1;
3450	}
3451	if (rc != VINF_SUCCESS)
3452	break;
3453	if (cbReg >= cb)
3454	break;
3455
3456	/* Advance. */
3457	off += cbReg;
3458	cb -= cbReg;
3459	u64Value >>= cbReg * 8;
3460	if (idxRegDsc == -1)
3461	idxRegDsc = hdaRegLookup(off);
3462	else
3463	{
3464	idxRegDsc++;
3465	if ( (unsigned)idxRegDsc >= RT_ELEMENTS(g_aHdaRegMap)
3466	\|\| g_aHdaRegMap[idxRegDsc].off != off)
3467	idxRegDsc = -1;
3468	}
3469	}
3470
3471	DEVHDA_UNLOCK(pDevIns, pThis);
3472
3473	#else /* !IN_RING3 */
3474	/* Take the simple way out. */
3475	rc = VINF_IOM_R3_MMIO_WRITE;
3476	#endif /* !IN_RING3 */
3477	}
3478
3479	return rc;
3480	}
3481
3482	#ifdef IN_RING3
3483
3484
3485	/*********************************************************************************************************************************
3486	* Saved state *
3487	*********************************************************************************************************************************/
3488
3489	/**
3490	* @callback_method_impl{FNSSMFIELDGETPUT,
3491	* Version 6 saves the IOC flag in HDABDLEDESC::fFlags as a bool}
3492	*/
3493	static DECLCALLBACK(int)
3494	hdaR3GetPutTrans_HDABDLEDESC_fFlags_6(PSSMHANDLE pSSM, const struct SSMFIELD pField, void pvStruct,
3495	uint32_t fFlags, bool fGetOrPut, void *pvUser)
3496	{
3497	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
3498	RT_NOREF(pSSM, pField, pvStruct, fFlags);
3499	AssertReturn(fGetOrPut, VERR_INTERNAL_ERROR_4);
3500	bool fIoc;
3501	int rc = pDevIns->pHlpR3->pfnSSMGetBool(pSSM, &fIoc);
3502	if (RT_SUCCESS(rc))
3503	{
3504	PHDABDLEDESC pDesc = (PHDABDLEDESC)pvStruct;
3505	pDesc->fFlags = fIoc ? HDA_BDLE_F_IOC : 0;
3506	}
3507	return rc;
3508	}
3509
3510
3511	/**
3512	* @callback_method_impl{FNSSMFIELDGETPUT,
3513	* Versions 1 thru 4 save the IOC flag in HDASTREAMSTATE::DescfFlags as a bool}
3514	*/
3515	static DECLCALLBACK(int)
3516	hdaR3GetPutTrans_HDABDLE_Desc_fFlags_1thru4(PSSMHANDLE pSSM, const struct SSMFIELD pField, void pvStruct,
3517	uint32_t fFlags, bool fGetOrPut, void *pvUser)
3518	{
3519	PPDMDEVINS pDevIns = (PPDMDEVINS)pvUser;
3520	RT_NOREF(pSSM, pField, pvStruct, fFlags);
3521	AssertReturn(fGetOrPut, VERR_INTERNAL_ERROR_4);
3522	bool fIoc;
3523	int rc = pDevIns->pHlpR3->pfnSSMGetBool(pSSM, &fIoc);
3524	if (RT_SUCCESS(rc))
3525	{
3526	HDABDLELEGACY pState = (HDABDLELEGACY )pvStruct;
3527	pState->Desc.fFlags = fIoc ? HDA_BDLE_F_IOC : 0;
3528	}
3529	return rc;
3530	}
3531
3532
3533	static int hdaR3SaveStream(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
3534	{
3535	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3536	# ifdef LOG_ENABLED
3537	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
3538	# endif
3539
3540	Log2Func(("[SD%RU8]\n", pStreamShared->u8SD));
3541
3542	/* Save stream ID. */
3543	Assert(pStreamShared->u8SD < HDA_MAX_STREAMS);
3544	int rc = pHlp->pfnSSMPutU8(pSSM, pStreamShared->u8SD);
3545	AssertRCReturn(rc, rc);
3546
3547	rc = pHlp->pfnSSMPutStructEx(pSSM, &pStreamShared->State, sizeof(pStreamShared->State),
3548	0 /fFlags/, g_aSSMStreamStateFields7, NULL);
3549	AssertRCReturn(rc, rc);
3550
3551	AssertCompile(sizeof(pStreamShared->State.idxCurBdle) == sizeof(uint8_t) && RT_ELEMENTS(pStreamShared->State.aBdl) == 256);
3552	HDABDLEDESC TmpDesc = (HDABDLEDESC )&pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle];
3553	rc = pHlp->pfnSSMPutStructEx(pSSM, &TmpDesc, sizeof(TmpDesc), 0 /fFlags/, g_aSSMBDLEDescFields7, NULL);
3554	AssertRCReturn(rc, rc);
3555
3556	HDABDLESTATELEGACY TmpState = { pStreamShared->State.idxCurBdle, 0, pStreamShared->State.offCurBdle, 0 };
3557	rc = pHlp->pfnSSMPutStructEx(pSSM, &TmpState, sizeof(TmpState), 0 /fFlags/, g_aSSMBDLEStateFields7, NULL);
3558	AssertRCReturn(rc, rc);
3559
3560	PAUDMIXSINK pSink = NULL;
3561	uint32_t cbCircBuf = 0;
3562	uint32_t cbCircBufUsed = 0;
3563	if (pStreamR3->State.pCircBuf)
3564	{
3565	cbCircBuf = (uint32_t)RTCircBufSize(pStreamR3->State.pCircBuf);
3566
3567	/* We take the AIO lock here and releases it after saving the buffer,
3568	otherwise the AIO thread could race us reading out the buffer data. */
3569	pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
3570	if ( !pSink
3571	\|\| RT_SUCCESS(AudioMixerSinkTryLock(pSink)))
3572	{
3573	cbCircBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
3574	if (cbCircBufUsed == 0 && pSink)
3575	AudioMixerSinkUnlock(pSink);
3576	}
3577	}
3578
3579	pHlp->pfnSSMPutU32(pSSM, cbCircBuf);
3580	rc = pHlp->pfnSSMPutU32(pSSM, cbCircBufUsed);
3581
3582	if (cbCircBufUsed > 0)
3583	{
3584	/* HACK ALERT! We cannot remove data from the buffer (live snapshot),
3585	we use RTCircBufOffsetRead and RTCircBufAcquireReadBlock
3586	creatively to get at the other buffer segment in case
3587	of a wraparound. */
3588	size_t const offBuf = RTCircBufOffsetRead(pStreamR3->State.pCircBuf);
3589	void *pvBuf = NULL;
3590	size_t cbBuf = 0;
3591	RTCircBufAcquireReadBlock(pStreamR3->State.pCircBuf, cbCircBufUsed, &pvBuf, &cbBuf);
3592	Assert(cbBuf);
3593	rc = pHlp->pfnSSMPutMem(pSSM, pvBuf, cbBuf);
3594	if (cbBuf < cbCircBufUsed)
3595	rc = pHlp->pfnSSMPutMem(pSSM, (uint8_t *)pvBuf - offBuf, cbCircBufUsed - cbBuf);
3596	RTCircBufReleaseReadBlock(pStreamR3->State.pCircBuf, 0 /* Don't advance read pointer! */);
3597
3598	if (pSink)
3599	AudioMixerSinkUnlock(pSink);
3600	}
3601
3602	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n", pStreamR3->u8SD, HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD),
3603	HDA_STREAM_REG(pThis, CBL, pStreamShared->u8SD), HDA_STREAM_REG(pThis, LVI, pStreamShared->u8SD)));
3604
3605	#ifdef LOG_ENABLED
3606	hdaR3BDLEDumpAll(pDevIns, pThis, pStreamShared->u64BDLBase, pStreamShared->u16LVI + 1);
3607	#endif
3608
3609	return rc;
3610	}
3611
3612	/**
3613	* @callback_method_impl{FNSSMDEVSAVEEXEC}
3614	*/
3615	static DECLCALLBACK(int) hdaR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3616	{
3617	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
3618	PHDASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
3619	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3620
3621	/* Save Codec nodes states. */
3622	hdaCodecSaveState(pDevIns, &pThisCC->Codec, pSSM);
3623
3624	/* Save MMIO registers. */
3625	pHlp->pfnSSMPutU32(pSSM, RT_ELEMENTS(pThis->au32Regs));
3626	pHlp->pfnSSMPutMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3627
3628	/* Save controller-specifc internals. */
3629	pHlp->pfnSSMPutU64(pSSM, pThis->tsWalClkStart);
3630	pHlp->pfnSSMPutU8(pSSM, pThis->u8IRQL);
3631
3632	/* Save number of streams. */
3633	pHlp->pfnSSMPutU32(pSSM, HDA_MAX_STREAMS);
3634
3635	/* Save stream states. */
3636	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
3637	{
3638	int rc = hdaR3SaveStream(pDevIns, pSSM, &pThis->aStreams[i], &pThisCC->aStreams[i]);
3639	AssertRCReturn(rc, rc);
3640	}
3641
3642	return VINF_SUCCESS;
3643	}
3644
3645	/**
3646	* @callback_method_impl{FNSSMDEVLOADDONE,
3647	* Finishes stream setup and resuming.}
3648	*/
3649	static DECLCALLBACK(int) hdaR3LoadDone(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
3650	{
3651	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
3652	PHDASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
3653	LogFlowFuncEnter();
3654
3655	/*
3656	* Enable all previously active streams.
3657	*/
3658	for (size_t i = 0; i < HDA_MAX_STREAMS; i++)
3659	{
3660	PHDASTREAM pStreamShared = &pThis->aStreams[i];
3661
3662	bool fActive = RT_BOOL(HDA_STREAM_REG(pThis, CTL, i) & HDA_SDCTL_RUN);
3663	if (fActive)
3664	{
3665	PHDASTREAMR3 pStreamR3 = &pThisCC->aStreams[i];
3666
3667	/* (Re-)enable the stream. */
3668	int rc2 = hdaR3StreamEnable(pThis, pStreamShared, pStreamR3, true /* fEnable */);
3669	AssertRC(rc2);
3670
3671	/* Add the stream to the device setup. */
3672	rc2 = hdaR3AddStream(pThisCC, &pStreamShared->State.Cfg);
3673	AssertRC(rc2);
3674
3675	/* Use the LPIB to find the current scheduling position. If this isn't
3676	exactly on a scheduling item adjust LPIB down to the start of the
3677	current. This isn't entirely ideal, but it avoid the IRQ counting
3678	issue if we round it upwards. (it is also a lot simpler) */
3679	uint32_t uLpib = HDA_STREAM_REG(pThis, LPIB, i);
3680	AssertLogRelMsgStmt(uLpib < pStreamShared->u32CBL, ("LPIB=%#RX32 CBL=%#RX32\n", uLpib, pStreamShared->u32CBL),
3681	HDA_STREAM_REG(pThis, LPIB, i) = uLpib = 0);
3682
3683	uint32_t off = 0;
3684	for (uint32_t j = 0; j < pStreamShared->State.cSchedule; j++)
3685	{
3686	AssertReturn(pStreamShared->State.aSchedule[j].cbPeriod >= 1 && pStreamShared->State.aSchedule[j].cLoops >= 1,
3687	pDevIns->pHlpR3->pfnSSMSetLoadError(pSSM, VERR_INTERNAL_ERROR_2, RT_SRC_POS,
3688	"Stream #%u, sched #%u: cbPeriod=%u cLoops=%u\n",
3689	pStreamShared->u8SD, j,
3690	pStreamShared->State.aSchedule[j].cbPeriod,
3691	pStreamShared->State.aSchedule[j].cLoops));
3692	uint32_t cbCur = pStreamShared->State.aSchedule[j].cbPeriod
3693	* pStreamShared->State.aSchedule[j].cLoops;
3694	if (uLpib >= off + cbCur)
3695	off += cbCur;
3696	else
3697	{
3698	uint32_t const offDelta = uLpib - off;
3699	uint32_t idxLoop = offDelta / pStreamShared->State.aSchedule[j].cbPeriod;
3700	uint32_t offLoop = offDelta % pStreamShared->State.aSchedule[j].cbPeriod;
3701	if (offLoop)
3702	{
3703	/** @todo somehow bake this into the DMA timer logic. */
3704	LogFunc(("stream #%u: LPIB=%#RX32; adjusting due to scheduling clash: -%#x (j=%u idxLoop=%u cbPeriod=%#x)\n",
3705	pStreamShared->u8SD, uLpib, offLoop, j, idxLoop, pStreamShared->State.aSchedule[j].cbPeriod));
3706	uLpib -= offLoop;
3707	HDA_STREAM_REG(pThis, LPIB, i) = uLpib;
3708	}
3709	pStreamShared->State.idxSchedule = (uint16_t)j;
3710	pStreamShared->State.idxScheduleLoop = (uint16_t)idxLoop;
3711	off = UINT32_MAX;
3712	break;
3713	}
3714	}
3715	Assert(off == UINT32_MAX);
3716
3717	/* Now figure out the current BDLE and the offset within it. */
3718	off = 0;
3719	for (uint32_t j = 0; j < pStreamShared->State.cBdles; j++)
3720	if (uLpib >= off + pStreamShared->State.aBdl[j].cb)
3721	off += pStreamShared->State.aBdl[j].cb;
3722	else
3723	{
3724	pStreamShared->State.idxCurBdle = j;
3725	pStreamShared->State.offCurBdle = uLpib - off;
3726	off = UINT32_MAX;
3727	break;
3728	}
3729	AssertReturn(off == UINT32_MAX, pDevIns->pHlpR3->pfnSSMSetLoadError(pSSM, VERR_INTERNAL_ERROR_3, RT_SRC_POS,
3730	"Stream #%u: LPIB=%#RX32 not found in loaded BDL\n",
3731	pStreamShared->u8SD, uLpib));
3732
3733	/* Avoid going through the timer here by calling the stream's timer function directly.
3734	* Should speed up starting the stream transfers. */
3735	PDMDevHlpTimerLockClock2(pDevIns, pStreamShared->hTimer, &pThis->CritSect, VERR_IGNORED);
3736	uint64_t tsNow = hdaR3StreamTimerMain(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3);
3737	PDMDevHlpTimerUnlockClock2(pDevIns, pStreamShared->hTimer, &pThis->CritSect);
3738
3739	hdaR3StreamMarkStarted(pDevIns, pThis, pStreamShared, tsNow);
3740	}
3741	}
3742
3743	LogFlowFuncLeave();
3744	return VINF_SUCCESS;
3745	}
3746
3747	/**
3748	* Handles loading of all saved state versions older than the current one.
3749	*
3750	* @param pDevIns The device instance.
3751	* @param pThis Pointer to the shared HDA state.
3752	* @param pThisCC Pointer to the ring-3 HDA state.
3753	* @param pSSM The saved state handle.
3754	* @param uVersion Saved state version to load.
3755	*/
3756	static int hdaR3LoadExecLegacy(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC, PSSMHANDLE pSSM, uint32_t uVersion)
3757	{
3758	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3759	int rc;
3760
3761	/*
3762	* Load MMIO registers.
3763	*/
3764	uint32_t cRegs;
3765	switch (uVersion)
3766	{
3767	case HDA_SAVED_STATE_VERSION_1:
3768	/* Starting with r71199, we would save 112 instead of 113
3769	registers due to some code cleanups. This only affected trunk
3770	builds in the 4.1 development period. */
3771	cRegs = 113;
3772	if (pHlp->pfnSSMHandleRevision(pSSM) >= 71199)
3773	{
3774	uint32_t uVer = pHlp->pfnSSMHandleVersion(pSSM);
3775	if ( VBOX_FULL_VERSION_GET_MAJOR(uVer) == 4
3776	&& VBOX_FULL_VERSION_GET_MINOR(uVer) == 0
3777	&& VBOX_FULL_VERSION_GET_BUILD(uVer) >= 51)
3778	cRegs = 112;
3779	}
3780	break;
3781
3782	case HDA_SAVED_STATE_VERSION_2:
3783	case HDA_SAVED_STATE_VERSION_3:
3784	cRegs = 112;
3785	AssertCompile(RT_ELEMENTS(pThis->au32Regs) >= 112);
3786	break;
3787
3788	/* Since version 4 we store the register count to stay flexible. */
3789	case HDA_SAVED_STATE_VERSION_4:
3790	case HDA_SAVED_STATE_VERSION_5:
3791	case HDA_SAVED_STATE_VERSION_6:
3792	rc = pHlp->pfnSSMGetU32(pSSM, &cRegs);
3793	AssertRCReturn(rc, rc);
3794	if (cRegs != RT_ELEMENTS(pThis->au32Regs))
3795	LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
3796	break;
3797
3798	default:
3799	AssertLogRelMsgFailedReturn(("HDA: Internal Error! Didn't expect saved state version %RU32 ending up in hdaR3LoadExecLegacy!\n",
3800	uVersion), VERR_INTERNAL_ERROR_5);
3801	}
3802
3803	if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
3804	{
3805	pHlp->pfnSSMGetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
3806	pHlp->pfnSSMSkip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
3807	}
3808	else
3809	pHlp->pfnSSMGetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
3810
3811	/* Make sure to update the base addresses first before initializing any streams down below. */
3812	pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
3813	pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
3814	pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE) & DPBASE_ADDR_MASK, HDA_REG(pThis, DPUBASE));
3815
3816	/* Also make sure to update the DMA position bit if this was enabled when saving the state. */
3817	pThis->fDMAPosition = RT_BOOL(HDA_REG(pThis, DPLBASE) & RT_BIT_32(0));
3818
3819	/*
3820	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3821	*
3822	* Note: Saved states < v5 store LVI (u32BdleMaxCvi) for
3823	* every BDLE state, whereas it only needs to be stored
3824	* once for every stream. Most of the BDLE state we can
3825	* get out of the registers anyway, so just ignore those values.
3826	*
3827	* Also, only the current BDLE was saved, regardless whether
3828	* there were more than one (and there are at least two entries,
3829	* according to the spec).
3830	*/
3831	switch (uVersion)
3832	{
3833	case HDA_SAVED_STATE_VERSION_1:
3834	case HDA_SAVED_STATE_VERSION_2:
3835	case HDA_SAVED_STATE_VERSION_3:
3836	case HDA_SAVED_STATE_VERSION_4:
3837	{
3838	/* Only load the internal states.
3839	* The rest will be initialized from the saved registers later. */
3840
3841	/* Note 1: Only the current BDLE for a stream was saved! */
3842	/* Note 2: The stream's saving order is/was fixed, so don't touch! */
3843
3844	HDABDLELEGACY BDLE;
3845
3846	/* Output */
3847	PHDASTREAM pStreamShared = &pThis->aStreams[4];
3848	rc = hdaR3StreamSetUp(pDevIns, pThis, pStreamShared, &pThisCC->aStreams[4], 4 /* Stream descriptor, hardcoded */);
3849	AssertRCReturn(rc, rc);
3850	RT_ZERO(BDLE);
3851	rc = pHlp->pfnSSMGetStructEx(pSSM, &BDLE, sizeof(BDLE), 0 /* fFlags */, g_aSSMStreamBdleFields1234, pDevIns);
3852	AssertRCReturn(rc, rc);
3853	pStreamShared->State.idxCurBdle = (uint8_t)BDLE.State.u32BDLIndex; /* not necessary */
3854
3855	/* Microphone-In */
3856	pStreamShared = &pThis->aStreams[2];
3857	rc = hdaR3StreamSetUp(pDevIns, pThis, pStreamShared, &pThisCC->aStreams[2], 2 /* Stream descriptor, hardcoded */);
3858	AssertRCReturn(rc, rc);
3859	rc = pHlp->pfnSSMGetStructEx(pSSM, &BDLE, sizeof(BDLE), 0 /* fFlags */, g_aSSMStreamBdleFields1234, pDevIns);
3860	AssertRCReturn(rc, rc);
3861	pStreamShared->State.idxCurBdle = (uint8_t)BDLE.State.u32BDLIndex; /* not necessary */
3862
3863	/* Line-In */
3864	pStreamShared = &pThis->aStreams[0];
3865	rc = hdaR3StreamSetUp(pDevIns, pThis, pStreamShared, &pThisCC->aStreams[0], 0 /* Stream descriptor, hardcoded */);
3866	AssertRCReturn(rc, rc);
3867	rc = pHlp->pfnSSMGetStructEx(pSSM, &BDLE, sizeof(BDLE), 0 /* fFlags */, g_aSSMStreamBdleFields1234, pDevIns);
3868	AssertRCReturn(rc, rc);
3869	pStreamShared->State.idxCurBdle = (uint8_t)BDLE.State.u32BDLIndex; /* not necessary */
3870	break;
3871	}
3872
3873	/*
3874	* v5 & v6 - Since v5 we support flexible stream and BDLE counts.
3875	*/
3876	default:
3877	{
3878	/* Stream count. */
3879	uint32_t cStreams;
3880	rc = pHlp->pfnSSMGetU32(pSSM, &cStreams);
3881	AssertRCReturn(rc, rc);
3882	if (cStreams > HDA_MAX_STREAMS)
3883	return pHlp->pfnSSMSetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
3884	N_("State contains %u streams while %u is the maximum supported"),
3885	cStreams, HDA_MAX_STREAMS);
3886
3887	/* Load stream states. */
3888	for (uint32_t i = 0; i < cStreams; i++)
3889	{
3890	uint8_t idStream;
3891	rc = pHlp->pfnSSMGetU8(pSSM, &idStream);
3892	AssertRCReturn(rc, rc);
3893
3894	HDASTREAM StreamDummyShared;
3895	HDASTREAMR3 StreamDummyR3;
3896	PHDASTREAM pStreamShared = idStream < RT_ELEMENTS(pThis->aStreams) ? &pThis->aStreams[idStream] : &StreamDummyShared;
3897	PHDASTREAMR3 pStreamR3 = idStream < RT_ELEMENTS(pThisCC->aStreams) ? &pThisCC->aStreams[idStream] : &StreamDummyR3;
3898	AssertLogRelMsgStmt(idStream < RT_ELEMENTS(pThisCC->aStreams),
3899	("HDA stream ID=%RU8 not supported, skipping loadingit ...\n", idStream),
3900	RT_ZERO(StreamDummyShared); RT_ZERO(StreamDummyR3));
3901
3902	rc = hdaR3StreamSetUp(pDevIns, pThis, pStreamShared, pStreamR3, idStream);
3903	if (RT_FAILURE(rc))
3904	{
3905	LogRel(("HDA: Stream #%RU32: Setting up of stream %RU8 failed, rc=%Rrc\n", i, idStream, rc));
3906	break;
3907	}
3908
3909	/*
3910	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
3911	*/
3912	if (uVersion == HDA_SAVED_STATE_VERSION_5)
3913	{
3914	struct V5HDASTREAMSTATE /* HDASTREAMSTATE + HDABDLE */
3915	{
3916	uint16_t cBLDEs;
3917	uint16_t uCurBDLE;
3918	uint32_t u32BDLEIndex;
3919	uint32_t cbBelowFIFOW;
3920	uint32_t u32BufOff;
3921	} Tmp;
3922	static SSMFIELD const g_aV5State1Fields[] =
3923	{
3924	SSMFIELD_ENTRY(V5HDASTREAMSTATE, cBLDEs),
3925	SSMFIELD_ENTRY(V5HDASTREAMSTATE, uCurBDLE),
3926	SSMFIELD_ENTRY_TERM()
3927	};
3928	rc = pHlp->pfnSSMGetStructEx(pSSM, &Tmp, sizeof(Tmp), 0 /* fFlags */, g_aV5State1Fields, NULL);
3929	AssertRCReturn(rc, rc);
3930	pStreamShared->State.idxCurBdle = (uint8_t)Tmp.uCurBDLE; /* not necessary */
3931
3932	for (uint16_t a = 0; a < Tmp.cBLDEs; a++)
3933	{
3934	static SSMFIELD const g_aV5State2Fields[] =
3935	{
3936	SSMFIELD_ENTRY(V5HDASTREAMSTATE, u32BDLEIndex),
3937	SSMFIELD_ENTRY_OLD(au8FIFO, 256),
3938	SSMFIELD_ENTRY(V5HDASTREAMSTATE, cbBelowFIFOW),
3939	SSMFIELD_ENTRY_TERM()
3940	};
3941	rc = pHlp->pfnSSMGetStructEx(pSSM, &Tmp, sizeof(Tmp), 0 /* fFlags */, g_aV5State2Fields, NULL);
3942	AssertRCReturn(rc, rc);
3943	}
3944	}
3945	else
3946	{
3947	rc = pHlp->pfnSSMGetStructEx(pSSM, &pStreamShared->State, sizeof(HDASTREAMSTATE),
3948	0 /* fFlags */, g_aSSMStreamStateFields6, NULL);
3949	AssertRCReturn(rc, rc);
3950
3951	HDABDLEDESC IgnDesc;
3952	rc = pHlp->pfnSSMGetStructEx(pSSM, &IgnDesc, sizeof(IgnDesc), 0 /* fFlags */, g_aSSMBDLEDescFields6, pDevIns);
3953	AssertRCReturn(rc, rc);
3954
3955	HDABDLESTATELEGACY IgnState;
3956	rc = pHlp->pfnSSMGetStructEx(pSSM, &IgnState, sizeof(IgnState), 0 /* fFlags */, g_aSSMBDLEStateFields6, NULL);
3957	AssertRCReturn(rc, rc);
3958
3959	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n", idStream, HDA_STREAM_REG(pThis, LPIB, idStream),
3960	HDA_STREAM_REG(pThis, CBL, idStream), HDA_STREAM_REG(pThis, LVI, idStream)));
3961	#ifdef LOG_ENABLED
3962	hdaR3BDLEDumpAll(pDevIns, pThis, pStreamShared->u64BDLBase, pStreamShared->u16LVI + 1);
3963	#endif
3964	}
3965
3966	} /* for cStreams */
3967	break;
3968	} /* default */
3969	}
3970
3971	return rc;
3972	}
3973
3974	/**
3975	* @callback_method_impl{FNSSMDEVLOADEXEC}
3976	*/
3977	static DECLCALLBACK(int) hdaR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3978	{
3979	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
3980	PHDASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
3981	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
3982
3983	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3984
3985	LogRel2(("hdaR3LoadExec: uVersion=%RU32, uPass=0x%x\n", uVersion, uPass));
3986
3987	/*
3988	* Load Codec nodes states.
3989	*/
3990	int rc = hdaR3CodecLoadState(pDevIns, &pThisCC->Codec, pSSM, uVersion);
3991	if (RT_FAILURE(rc))
3992	{
3993	LogRel(("HDA: Failed loading codec state (version %RU32, pass 0x%x), rc=%Rrc\n", uVersion, uPass, rc));
3994	return rc;
3995	}
3996
3997	if (uVersion <= HDA_SAVED_STATE_VERSION_6) /* Handle older saved states? */
3998	return hdaR3LoadExecLegacy(pDevIns, pThis, pThisCC, pSSM, uVersion);
3999
4000	/*
4001	* Load MMIO registers.
4002	*/
4003	uint32_t cRegs;
4004	rc = pHlp->pfnSSMGetU32(pSSM, &cRegs); AssertRCReturn(rc, rc);
4005	AssertRCReturn(rc, rc);
4006	if (cRegs != RT_ELEMENTS(pThis->au32Regs))
4007	LogRel(("HDA: SSM version cRegs is %RU32, expected %RU32\n", cRegs, RT_ELEMENTS(pThis->au32Regs)));
4008
4009	if (cRegs >= RT_ELEMENTS(pThis->au32Regs))
4010	{
4011	pHlp->pfnSSMGetMem(pSSM, pThis->au32Regs, sizeof(pThis->au32Regs));
4012	rc = pHlp->pfnSSMSkip(pSSM, sizeof(uint32_t) * (cRegs - RT_ELEMENTS(pThis->au32Regs)));
4013	AssertRCReturn(rc, rc);
4014	}
4015	else
4016	{
4017	rc = pHlp->pfnSSMGetMem(pSSM, pThis->au32Regs, sizeof(uint32_t) * cRegs);
4018	AssertRCReturn(rc, rc);
4019	}
4020
4021	/* Make sure to update the base addresses first before initializing any streams down below. */
4022	pThis->u64CORBBase = RT_MAKE_U64(HDA_REG(pThis, CORBLBASE), HDA_REG(pThis, CORBUBASE));
4023	pThis->u64RIRBBase = RT_MAKE_U64(HDA_REG(pThis, RIRBLBASE), HDA_REG(pThis, RIRBUBASE));
4024	pThis->u64DPBase = RT_MAKE_U64(HDA_REG(pThis, DPLBASE) & DPBASE_ADDR_MASK, HDA_REG(pThis, DPUBASE));
4025
4026	/* Also make sure to update the DMA position bit if this was enabled when saving the state. */
4027	pThis->fDMAPosition = RT_BOOL(HDA_REG(pThis, DPLBASE) & RT_BIT_32(0));
4028
4029	/*
4030	* Load controller-specific internals.
4031	*/
4032	if ( uVersion >= HDA_SAVED_STATE_WITHOUT_PERIOD
4033	/* Don't annoy other team mates (forgot this for state v7): */
4034	\|\| pHlp->pfnSSMHandleRevision(pSSM) >= 116273
4035	\|\| pHlp->pfnSSMHandleVersion(pSSM) >= VBOX_FULL_VERSION_MAKE(5, 2, 0))
4036	{
4037	pHlp->pfnSSMGetU64(pSSM, &pThis->tsWalClkStart); /* Was current wall clock */
4038	rc = pHlp->pfnSSMGetU8(pSSM, &pThis->u8IRQL);
4039	AssertRCReturn(rc, rc);
4040
4041	/* Convert the saved wall clock timestamp to a start timestamp. */
4042	if (uVersion < HDA_SAVED_STATE_WITHOUT_PERIOD && pThis->tsWalClkStart != 0)
4043	{
4044	uint64_t const cTimerTicksPerSec = PDMDevHlpTimerGetFreq(pDevIns, pThis->aStreams[0].hTimer);
4045	AssertLogRel(cTimerTicksPerSec <= UINT32_MAX);
4046	pThis->tsWalClkStart = ASMMultU64ByU32DivByU32(pThis->tsWalClkStart,
4047	cTimerTicksPerSec,
4048	24000000 /* wall clock freq */);
4049	pThis->tsWalClkStart = PDMDevHlpTimerGet(pDevIns, pThis->aStreams[0].hTimer) - pThis->tsWalClkStart;
4050	}
4051	}
4052
4053	/*
4054	* Load streams.
4055	*/
4056	uint32_t cStreams;
4057	rc = pHlp->pfnSSMGetU32(pSSM, &cStreams);
4058	AssertRCReturn(rc, rc);
4059	if (cStreams > HDA_MAX_STREAMS)
4060	return pHlp->pfnSSMSetLoadError(pSSM, VERR_SSM_DATA_UNIT_FORMAT_CHANGED, RT_SRC_POS,
4061	N_("State contains %u streams while %u is the maximum supported"),
4062	cStreams, HDA_MAX_STREAMS);
4063	Log2Func(("cStreams=%RU32\n", cStreams));
4064
4065	/* Load stream states. */
4066	for (uint32_t i = 0; i < cStreams; i++)
4067	{
4068	uint8_t idStream;
4069	rc = pHlp->pfnSSMGetU8(pSSM, &idStream);
4070	AssertRCReturn(rc, rc);
4071
4072	/* Paranoia. */
4073	AssertLogRelMsgReturn(idStream < HDA_MAX_STREAMS,
4074	("HDA: Saved state contains bogus stream ID %RU8 for stream #%RU8", idStream, i),
4075	VERR_SSM_INVALID_STATE);
4076
4077	HDASTREAM StreamDummyShared;
4078	HDASTREAMR3 StreamDummyR3;
4079	PHDASTREAM pStreamShared = idStream < RT_ELEMENTS(pThis->aStreams) ? &pThis->aStreams[idStream] : &StreamDummyShared;
4080	PHDASTREAMR3 pStreamR3 = idStream < RT_ELEMENTS(pThisCC->aStreams) ? &pThisCC->aStreams[idStream] : &StreamDummyR3;
4081	AssertLogRelMsgStmt(idStream < RT_ELEMENTS(pThisCC->aStreams),
4082	("HDA stream ID=%RU8 not supported, skipping loadingit ...\n", idStream),
4083	RT_ZERO(StreamDummyShared); RT_ZERO(StreamDummyR3));
4084
4085	rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED); /* timer code requires this */
4086	AssertRCReturn(rc, rc);
4087	rc = hdaR3StreamSetUp(pDevIns, pThis, pStreamShared, pStreamR3, idStream);
4088	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4089	if (RT_FAILURE(rc))
4090	{
4091	LogRel(("HDA: Stream #%RU8: Setting up failed, rc=%Rrc\n", idStream, rc));
4092	/* Continue. */
4093	}
4094
4095	rc = pHlp->pfnSSMGetStructEx(pSSM, &pStreamShared->State, sizeof(HDASTREAMSTATE),
4096	0 /* fFlags */, g_aSSMStreamStateFields7, NULL);
4097	AssertRCReturn(rc, rc);
4098
4099	/*
4100	* Load BDLEs (Buffer Descriptor List Entries) and DMA counters.
4101	* Obsolete. Derived from LPID now.
4102	*/
4103	HDABDLEDESC IgnDesc;
4104	rc = pHlp->pfnSSMGetStructEx(pSSM, &IgnDesc, sizeof(IgnDesc), 0 /* fFlags */, g_aSSMBDLEDescFields7, NULL);
4105	AssertRCReturn(rc, rc);
4106
4107	HDABDLESTATELEGACY IgnState;
4108	rc = pHlp->pfnSSMGetStructEx(pSSM, &IgnState, sizeof(IgnState), 0 /* fFlags */, g_aSSMBDLEStateFields7, NULL);
4109	AssertRCReturn(rc, rc);
4110
4111	Log2Func(("[SD%RU8]\n", pStreamShared->u8SD));
4112
4113	/*
4114	* Load period state if present.
4115	*/
4116	if (uVersion < HDA_SAVED_STATE_WITHOUT_PERIOD)
4117	{
4118	static SSMFIELD const s_aSSMStreamPeriodFields7[] = /* For the removed HDASTREAMPERIOD structure. */
4119	{
4120	SSMFIELD_ENTRY_OLD(u64StartWalClk, sizeof(uint64_t)),
4121	SSMFIELD_ENTRY_OLD(u64ElapsedWalClk, sizeof(uint64_t)),
4122	SSMFIELD_ENTRY_OLD(cFramesTransferred, sizeof(uint32_t)),
4123	SSMFIELD_ENTRY_OLD(cIntPending, sizeof(uint8_t)), /** @todo Not sure what we should for non-zero values on restore... ignoring it for now. */
4124	SSMFIELD_ENTRY_TERM()
4125	};
4126	uint8_t bWhatever = 0;
4127	rc = pHlp->pfnSSMGetStructEx(pSSM, &bWhatever, sizeof(bWhatever), 0 /* fFlags */, s_aSSMStreamPeriodFields7, NULL);
4128	AssertRCReturn(rc, rc);
4129	}
4130
4131	/*
4132	* Load internal DMA buffer.
4133	*/
4134	uint32_t cbCircBuf = 0;
4135	pHlp->pfnSSMGetU32(pSSM, &cbCircBuf); /* cbCircBuf */
4136	uint32_t cbCircBufUsed = 0;
4137	rc = pHlp->pfnSSMGetU32(pSSM, &cbCircBufUsed); /* cbCircBuf */
4138	AssertRCReturn(rc, rc);
4139
4140	if (cbCircBuf) /* If 0, skip the buffer. */
4141	{
4142	/* Paranoia. */
4143	AssertLogRelMsgReturn(cbCircBuf <= _32M,
4144	("HDA: Saved state contains bogus DMA buffer size (%RU32) for stream #%RU8",
4145	cbCircBuf, idStream),
4146	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
4147	AssertLogRelMsgReturn(cbCircBufUsed <= cbCircBuf,
4148	("HDA: Saved state contains invalid DMA buffer usage (%RU32/%RU32) for stream #%RU8",
4149	cbCircBufUsed, cbCircBuf, idStream),
4150	VERR_SSM_DATA_UNIT_FORMAT_CHANGED);
4151
4152	/* Do we need to cre-create the circular buffer do fit the data size? */
4153	if ( pStreamR3->State.pCircBuf
4154	&& cbCircBuf != (uint32_t)RTCircBufSize(pStreamR3->State.pCircBuf))
4155	{
4156	RTCircBufDestroy(pStreamR3->State.pCircBuf);
4157	pStreamR3->State.pCircBuf = NULL;
4158	}
4159
4160	rc = RTCircBufCreate(&pStreamR3->State.pCircBuf, cbCircBuf);
4161	AssertRCReturn(rc, rc);
4162	pStreamR3->State.StatDmaBufSize = cbCircBuf;
4163
4164	if (cbCircBufUsed)
4165	{
4166	void *pvBuf = NULL;
4167	size_t cbBuf = 0;
4168	RTCircBufAcquireWriteBlock(pStreamR3->State.pCircBuf, cbCircBufUsed, &pvBuf, &cbBuf);
4169
4170	AssertLogRelMsgReturn(cbBuf == cbCircBufUsed, ("cbBuf=%zu cbCircBufUsed=%zu\n", cbBuf, cbCircBufUsed),
4171	VERR_INTERNAL_ERROR_3);
4172	rc = pHlp->pfnSSMGetMem(pSSM, pvBuf, cbBuf);
4173	AssertRCReturn(rc, rc);
4174	pStreamShared->State.offWrite = cbCircBufUsed;
4175
4176	RTCircBufReleaseWriteBlock(pStreamR3->State.pCircBuf, cbBuf);
4177
4178	Assert(cbBuf == cbCircBufUsed);
4179	}
4180	}
4181
4182	Log2Func(("[SD%RU8] LPIB=%RU32, CBL=%RU32, LVI=%RU32\n", idStream, HDA_STREAM_REG(pThis, LPIB, idStream),
4183	HDA_STREAM_REG(pThis, CBL, idStream), HDA_STREAM_REG(pThis, LVI, idStream)));
4184	#ifdef LOG_ENABLED
4185	hdaR3BDLEDumpAll(pDevIns, pThis, pStreamShared->u64BDLBase, pStreamShared->u16LVI + 1);
4186	#endif
4187	/** @todo (Re-)initialize active periods? */
4188
4189	} /* for cStreams */
4190
4191	LogFlowFuncLeaveRC(rc);
4192	return rc;
4193	}
4194
4195
4196	/*********************************************************************************************************************************
4197	* IPRT format type handlers *
4198	*********************************************************************************************************************************/
4199
4200	/**
4201	* @callback_method_impl{FNRTSTRFORMATTYPE}
4202	*/
4203	static DECLCALLBACK(size_t) hdaR3StrFmtSDCTL(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4204	const char pszType, void const pvValue,
4205	int cchWidth, int cchPrecision, unsigned fFlags,
4206	void *pvUser)
4207	{
4208	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4209	uint32_t uSDCTL = (uint32_t)(uintptr_t)pvValue;
4210	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4211	"SDCTL(raw:%#x, DIR:%s, TP:%RTbool, STRIPE:%x, DEIE:%RTbool, FEIE:%RTbool, IOCE:%RTbool, RUN:%RTbool, RESET:%RTbool)",
4212	uSDCTL,
4213	uSDCTL & HDA_SDCTL_DIR ? "OUT" : "IN",
4214	RT_BOOL(uSDCTL & HDA_SDCTL_TP),
4215	(uSDCTL & HDA_SDCTL_STRIPE_MASK) >> HDA_SDCTL_STRIPE_SHIFT,
4216	RT_BOOL(uSDCTL & HDA_SDCTL_DEIE),
4217	RT_BOOL(uSDCTL & HDA_SDCTL_FEIE),
4218	RT_BOOL(uSDCTL & HDA_SDCTL_IOCE),
4219	RT_BOOL(uSDCTL & HDA_SDCTL_RUN),
4220	RT_BOOL(uSDCTL & HDA_SDCTL_SRST));
4221	}
4222
4223	/**
4224	* @callback_method_impl{FNRTSTRFORMATTYPE}
4225	*/
4226	static DECLCALLBACK(size_t) hdaR3StrFmtSDFIFOS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4227	const char pszType, void const pvValue,
4228	int cchWidth, int cchPrecision, unsigned fFlags,
4229	void *pvUser)
4230	{
4231	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4232	uint32_t uSDFIFOS = (uint32_t)(uintptr_t)pvValue;
4233	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOS(raw:%#x, sdfifos:%RU8 B)", uSDFIFOS, uSDFIFOS ? uSDFIFOS + 1 : 0);
4234	}
4235
4236	/**
4237	* @callback_method_impl{FNRTSTRFORMATTYPE}
4238	*/
4239	static DECLCALLBACK(size_t) hdaR3StrFmtSDFIFOW(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4240	const char pszType, void const pvValue,
4241	int cchWidth, int cchPrecision, unsigned fFlags,
4242	void *pvUser)
4243	{
4244	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4245	uint32_t uSDFIFOW = (uint32_t)(uintptr_t)pvValue;
4246	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0, "SDFIFOW(raw: %#0x, sdfifow:%d B)", uSDFIFOW, hdaSDFIFOWToBytes(uSDFIFOW));
4247	}
4248
4249	/**
4250	* @callback_method_impl{FNRTSTRFORMATTYPE}
4251	*/
4252	static DECLCALLBACK(size_t) hdaR3StrFmtSDSTS(PFNRTSTROUTPUT pfnOutput, void *pvArgOutput,
4253	const char pszType, void const pvValue,
4254	int cchWidth, int cchPrecision, unsigned fFlags,
4255	void *pvUser)
4256	{
4257	RT_NOREF(pszType, cchWidth, cchPrecision, fFlags, pvUser);
4258	uint32_t uSdSts = (uint32_t)(uintptr_t)pvValue;
4259	return RTStrFormat(pfnOutput, pvArgOutput, NULL, 0,
4260	"SDSTS(raw:%#0x, fifordy:%RTbool, dese:%RTbool, fifoe:%RTbool, bcis:%RTbool)",
4261	uSdSts,
4262	RT_BOOL(uSdSts & HDA_SDSTS_FIFORDY),
4263	RT_BOOL(uSdSts & HDA_SDSTS_DESE),
4264	RT_BOOL(uSdSts & HDA_SDSTS_FIFOE),
4265	RT_BOOL(uSdSts & HDA_SDSTS_BCIS));
4266	}
4267
4268
4269	/*********************************************************************************************************************************
4270	* Debug Info Item Handlers *
4271	*********************************************************************************************************************************/
4272
4273	/** Worker for hdaR3DbgInfo. */
4274	static int hdaR3DbgLookupRegByName(const char *pszArgs)
4275	{
4276	if (pszArgs && *pszArgs != '\0')
4277	for (int iReg = 0; iReg < HDA_NUM_REGS; ++iReg)
4278	if (!RTStrICmp(g_aHdaRegMap[iReg].pszName, pszArgs))
4279	return iReg;
4280	return -1;
4281	}
4282
4283	/** Worker for hdaR3DbgInfo. */
4284	static void hdaR3DbgPrintRegister(PPDMDEVINS pDevIns, PHDASTATE pThis, PCDBGFINFOHLP pHlp, int iHdaIndex)
4285	{
4286	/** @todo HDA_REG_IDX_NOMEM & GCAP both uses idxReg zero, no flag or anything
4287	* to tell them appart. */
4288	if (g_aHdaRegMap[iHdaIndex].idxReg != 0 \|\| g_aHdaRegMap[iHdaIndex].pfnRead != hdaRegReadWALCLK)
4289	pHlp->pfnPrintf(pHlp, "%s: 0x%x\n", g_aHdaRegMap[iHdaIndex].pszName, pThis->au32Regs[g_aHdaRegMap[iHdaIndex].idxReg]);
4290	else
4291	{
4292	uint64_t uWallNow = 0;
4293	hdaQueryWallClock(pDevIns, pThis, false /fDoDma/, &uWallNow);
4294	pHlp->pfnPrintf(pHlp, "%s: 0x%RX64\n", g_aHdaRegMap[iHdaIndex].pszName, uWallNow);
4295	}
4296	}
4297
4298	/**
4299	* @callback_method_impl{FNDBGFHANDLERDEV}
4300	*/
4301	static DECLCALLBACK(void) hdaR3DbgInfo(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4302	{
4303	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
4304	int idxReg = hdaR3DbgLookupRegByName(pszArgs);
4305	if (idxReg != -1)
4306	hdaR3DbgPrintRegister(pDevIns, pThis, pHlp, idxReg);
4307	else
4308	for (idxReg = 0; idxReg < HDA_NUM_REGS; ++idxReg)
4309	hdaR3DbgPrintRegister(pDevIns, pThis, pHlp, idxReg);
4310	}
4311
4312	/** Worker for hdaR3DbgInfoStream. */
4313	static void hdaR3DbgPrintStream(PHDASTATE pThis, PCDBGFINFOHLP pHlp, int idxStream)
4314	{
4315	char szTmp[PDMAUDIOSTRMCFGTOSTRING_MAX];
4316	PHDASTREAM const pStream = &pThis->aStreams[idxStream];
4317	pHlp->pfnPrintf(pHlp, "Stream #%d: %s\n", idxStream, PDMAudioStrmCfgToString(&pStream->State.Cfg, szTmp, sizeof(szTmp)));
4318	pHlp->pfnPrintf(pHlp, " SD%dCTL : %R[sdctl]\n", idxStream, HDA_STREAM_REG(pThis, CTL, idxStream));
4319	pHlp->pfnPrintf(pHlp, " SD%dCTS : %R[sdsts]\n", idxStream, HDA_STREAM_REG(pThis, STS, idxStream));
4320	pHlp->pfnPrintf(pHlp, " SD%dFIFOS: %R[sdfifos]\n", idxStream, HDA_STREAM_REG(pThis, FIFOS, idxStream));
4321	pHlp->pfnPrintf(pHlp, " SD%dFIFOW: %R[sdfifow]\n", idxStream, HDA_STREAM_REG(pThis, FIFOW, idxStream));
4322	pHlp->pfnPrintf(pHlp, " Current BDLE%02u: %s%#RX64 LB %#x%s - off=%#x\n", pStream->State.idxCurBdle, "%%" /vboxdbg phys prefix/,
4323	pStream->State.aBdl[pStream->State.idxCurBdle].GCPhys, pStream->State.aBdl[pStream->State.idxCurBdle].cb,
4324	pStream->State.aBdl[pStream->State.idxCurBdle].fFlags ? " IOC" : "", pStream->State.offCurBdle);
4325	}
4326
4327	/** Worker for hdaR3DbgInfoBDL. */
4328	static void hdaR3DbgPrintBDL(PPDMDEVINS pDevIns, PHDASTATE pThis, PCDBGFINFOHLP pHlp, int idxStream)
4329	{
4330	const PHDASTREAM pStream = &pThis->aStreams[idxStream];
4331	PCPDMAUDIOPCMPROPS pProps = &pStream->State.Cfg.Props;
4332	uint64_t const u64BaseDMA = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, idxStream),
4333	HDA_STREAM_REG(pThis, BDPU, idxStream));
4334	uint16_t const u16LVI = HDA_STREAM_REG(pThis, LVI, idxStream);
4335	uint32_t const u32CBL = HDA_STREAM_REG(pThis, CBL, idxStream);
4336	uint8_t const idxCurBdle = pStream->State.idxCurBdle;
4337	pHlp->pfnPrintf(pHlp, "Stream #%d BDL: %s%#011RX64 LB %#x (LVI=%u)\n", idxStream, "%%" /vboxdbg phys prefix/,
4338	u64BaseDMA, u16LVI * sizeof(HDABDLEDESC), u16LVI);
4339	if (u64BaseDMA \|\| idxCurBdle != 0 \|\| pStream->State.aBdl[idxCurBdle].GCPhys != 0 \|\| pStream->State.aBdl[idxCurBdle].cb != 0)
4340	pHlp->pfnPrintf(pHlp, " Current: BDLE%03u: %s%#011RX64 LB %#x%s - off=%#x LPIB=%#RX32\n",
4341	pStream->State.idxCurBdle, "%%" /vboxdbg phys prefix/,
4342	pStream->State.aBdl[idxCurBdle].GCPhys, pStream->State.aBdl[idxCurBdle].cb,
4343	pStream->State.aBdl[idxCurBdle].fFlags ? " IOC" : "", pStream->State.offCurBdle,
4344	HDA_STREAM_REG(pThis, LPIB, idxStream));
4345	if (!u64BaseDMA)
4346	return;
4347
4348	/*
4349	* The BDL:
4350	*/
4351	uint64_t cbTotal = 0;
4352	for (uint16_t i = 0; i < u16LVI + 1; i++)
4353	{
4354	HDABDLEDESC bd = {0, 0, 0};
4355	PDMDevHlpPCIPhysRead(pDevIns, u64BaseDMA + i * sizeof(HDABDLEDESC), &bd, sizeof(bd));
4356
4357	char szFlags[64];
4358	szFlags[0] = '\0';
4359	if (bd.fFlags & ~HDA_BDLE_F_IOC)
4360	RTStrPrintf(szFlags, sizeof(szFlags), " !!fFlags=%#x!!\n", bd.fFlags);
4361	pHlp->pfnPrintf(pHlp, " %sBDLE%03u: %s%#011RX64 LB %#06x (%RU64 us) %s%s\n", idxCurBdle == i ? "=>" : " ", i, "%%",
4362	bd.u64BufAddr, bd.u32BufSize, PDMAudioPropsBytesToMicro(pProps, bd.u32BufSize),
4363	bd.fFlags & HDA_BDLE_F_IOC ? " IOC=1" : "", szFlags);
4364
4365	if (memcmp(&bd, &pStream->State.aBdl[i], sizeof(bd)) != 0)
4366	{
4367	szFlags[0] = '\0';
4368	if (bd.fFlags & ~HDA_BDLE_F_IOC)
4369	RTStrPrintf(szFlags, sizeof(szFlags), " !!fFlags=%#x!!\n", bd.fFlags);
4370	pHlp->pfnPrintf(pHlp, " !!!loaded: %s%#011RX64 LB %#06x %s%s\n", "%%", pStream->State.aBdl[i].GCPhys,
4371	pStream->State.aBdl[i].cb, pStream->State.aBdl[i].fFlags & HDA_BDLE_F_IOC ? " IOC=1" : "", szFlags);
4372	}
4373
4374	cbTotal += bd.u32BufSize;
4375	}
4376	pHlp->pfnPrintf(pHlp, " Total: %#RX64 bytes (%RU64), %RU64 ms\n", cbTotal, cbTotal,
4377	PDMAudioPropsBytesToMilli(pProps, (uint32_t)cbTotal));
4378	if (cbTotal != u32CBL)
4379	pHlp->pfnPrintf(pHlp, " Warning: %#RX64 bytes does not match CBL (%#RX64)!\n", cbTotal, u32CBL);
4380
4381	/*
4382	* The scheduling plan.
4383	*/
4384	uint16_t const idxSchedule = pStream->State.idxSchedule;
4385	pHlp->pfnPrintf(pHlp, " Scheduling: %u items, %u prologue. Current: %u, loop %u.\n", pStream->State.cSchedule,
4386	pStream->State.cSchedulePrologue, idxSchedule, pStream->State.idxScheduleLoop);
4387	for (uint16_t i = 0; i < pStream->State.cSchedule; i++)
4388	pHlp->pfnPrintf(pHlp, " %s#%02u: %#x bytes, %u loop%s, %RU32 ticks. BDLE%u thru BDLE%u\n",
4389	i == idxSchedule ? "=>" : " ", i,
4390	pStream->State.aSchedule[i].cbPeriod, pStream->State.aSchedule[i].cLoops,
4391	pStream->State.aSchedule[i].cLoops == 1 ? "" : "s",
4392	pStream->State.aSchedule[i].cPeriodTicks, pStream->State.aSchedule[i].idxFirst,
4393	pStream->State.aSchedule[i].idxFirst + pStream->State.aSchedule[i].cEntries - 1);
4394	}
4395
4396	/** Used by hdaR3DbgInfoStream and hdaR3DbgInfoBDL. */
4397	static int hdaR3DbgLookupStrmIdx(PCDBGFINFOHLP pHlp, const char *pszArgs)
4398	{
4399	if (pszArgs && *pszArgs)
4400	{
4401	int32_t idxStream;
4402	int rc = RTStrToInt32Full(pszArgs, 0, &idxStream);
4403	if (RT_SUCCESS(rc) && idxStream >= -1 && idxStream < HDA_MAX_STREAMS)
4404	return idxStream;
4405	pHlp->pfnPrintf(pHlp, "Argument '%s' is not a valid stream number!\n", pszArgs);
4406	}
4407	return -1;
4408	}
4409
4410	/**
4411	* @callback_method_impl{FNDBGFHANDLERDEV, hdastream}
4412	*/
4413	static DECLCALLBACK(void) hdaR3DbgInfoStream(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4414	{
4415	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
4416	int idxStream = hdaR3DbgLookupStrmIdx(pHlp, pszArgs);
4417	if (idxStream != -1)
4418	hdaR3DbgPrintStream(pThis, pHlp, idxStream);
4419	else
4420	for (idxStream = 0; idxStream < HDA_MAX_STREAMS; ++idxStream)
4421	hdaR3DbgPrintStream(pThis, pHlp, idxStream);
4422	}
4423
4424	/**
4425	* @callback_method_impl{FNDBGFHANDLERDEV, hdabdl}
4426	*/
4427	static DECLCALLBACK(void) hdaR3DbgInfoBDL(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4428	{
4429	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
4430	int idxStream = hdaR3DbgLookupStrmIdx(pHlp, pszArgs);
4431	if (idxStream != -1)
4432	hdaR3DbgPrintBDL(pDevIns, pThis, pHlp, idxStream);
4433	else
4434	{
4435	for (idxStream = 0; idxStream < HDA_MAX_STREAMS; ++idxStream)
4436	hdaR3DbgPrintBDL(pDevIns, pThis, pHlp, idxStream);
4437	idxStream = -1;
4438	}
4439
4440	/*
4441	* DMA stream positions:
4442	*/
4443	uint64_t const uDPBase = pThis->u64DPBase & DPBASE_ADDR_MASK;
4444	pHlp->pfnPrintf(pHlp, "DMA counters %#011RX64 LB %#x, %s:\n", uDPBase, HDA_MAX_STREAMS * 2 * sizeof(uint32_t),
4445	pThis->fDMAPosition ? "enabled" : "disabled");
4446	if (uDPBase)
4447	{
4448	struct
4449	{
4450	uint32_t off, uReserved;
4451	} aPositions[HDA_MAX_STREAMS];
4452	RT_ZERO(aPositions);
4453	PDMDevHlpPCIPhysRead(pDevIns, uDPBase , &aPositions[0], sizeof(aPositions));
4454
4455	for (unsigned i = 0; i < RT_ELEMENTS(aPositions); i++)
4456	if (idxStream == -1 \|\| i == (unsigned)idxStream) /* lazy bird */
4457	{
4458	char szReserved[64];
4459	szReserved[0] = '\0';
4460	if (aPositions[i].uReserved != 0)
4461	RTStrPrintf(szReserved, sizeof(szReserved), " reserved=%#x", aPositions[i].uReserved);
4462	pHlp->pfnPrintf(pHlp, " Stream #%u DMA @ %#x%s\n", i, aPositions[i].off, szReserved);
4463	}
4464	}
4465	}
4466
4467	/**
4468	* @callback_method_impl{FNDBGFHANDLERDEV, hdcnodes}
4469	*/
4470	static DECLCALLBACK(void) hdaR3DbgInfoCodecNodes(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4471	{
4472	PHDASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
4473	hdaR3CodecDbgListNodes(&pThisCC->Codec, pHlp, pszArgs);
4474	}
4475
4476	/**
4477	* @callback_method_impl{FNDBGFHANDLERDEV, hdcselector}
4478	*/
4479	static DECLCALLBACK(void) hdaR3DbgInfoCodecSelector(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4480	{
4481	PHDASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
4482	hdaR3CodecDbgSelector(&pThisCC->Codec, pHlp, pszArgs);
4483	}
4484
4485	/**
4486	* @callback_method_impl{FNDBGFHANDLERDEV, hdamixer}
4487	*/
4488	static DECLCALLBACK(void) hdaR3DbgInfoMixer(PPDMDEVINS pDevIns, PCDBGFINFOHLP pHlp, const char *pszArgs)
4489	{
4490	PHDASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
4491	if (pThisCC->pMixer)
4492	AudioMixerDebug(pThisCC->pMixer, pHlp, pszArgs);
4493	else
4494	pHlp->pfnPrintf(pHlp, "Mixer not available\n");
4495	}
4496
4497
4498	/*********************************************************************************************************************************
4499	* PDMIBASE *
4500	*********************************************************************************************************************************/
4501
4502	/**
4503	* @interface_method_impl{PDMIBASE,pfnQueryInterface}
4504	*/
4505	static DECLCALLBACK(void ) hdaR3QueryInterface(struct PDMIBASE pInterface, const char *pszIID)
4506	{
4507	PHDASTATER3 pThisCC = RT_FROM_MEMBER(pInterface, HDASTATER3, IBase);
4508
4509	PDMIBASE_RETURN_INTERFACE(pszIID, PDMIBASE, &pThisCC->IBase);
4510	return NULL;
4511	}
4512
4513
4514	/*********************************************************************************************************************************
4515	* PDMDEVREGR3 *
4516	*********************************************************************************************************************************/
4517
4518	/**
4519	* Worker for hdaR3Construct() and hdaR3Attach().
4520	*
4521	* @returns VBox status code.
4522	* @param pDevIns The device instance.
4523	* @param pThis The shared HDA device state.
4524	* @param pThisCC The ring-3 HDA device state.
4525	* @param uLUN The logical unit which is being detached.
4526	* @param ppDrv Attached driver instance on success. Optional.
4527	*/
4528	static int hdaR3AttachInternal(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC, unsigned uLUN, PHDADRIVER *ppDrv)
4529	{
4530	PHDADRIVER pDrv = (PHDADRIVER)RTMemAllocZ(sizeof(HDADRIVER));
4531	AssertPtrReturn(pDrv, VERR_NO_MEMORY);
4532	RTStrPrintf(pDrv->szDesc, sizeof(pDrv->szDesc), "Audio driver port (HDA) for LUN #%u", uLUN);
4533
4534	PPDMIBASE pDrvBase;
4535	int rc = PDMDevHlpDriverAttach(pDevIns, uLUN, &pThisCC->IBase, &pDrvBase, pDrv->szDesc);
4536	if (RT_SUCCESS(rc))
4537	{
4538	pDrv->pConnector = PDMIBASE_QUERY_INTERFACE(pDrvBase, PDMIAUDIOCONNECTOR);
4539	AssertPtr(pDrv->pConnector);
4540	if (RT_VALID_PTR(pDrv->pConnector))
4541	{
4542	pDrv->pDrvBase = pDrvBase;
4543	pDrv->pHDAStateShared = pThis;
4544	pDrv->pHDAStateR3 = pThisCC;
4545	pDrv->uLUN = uLUN;
4546
4547	/* Attach to driver list if not attached yet. */
4548	if (!pDrv->fAttached)
4549	{
4550	RTListAppend(&pThisCC->lstDrv, &pDrv->Node);
4551	pDrv->fAttached = true;
4552	}
4553
4554	if (ppDrv)
4555	*ppDrv = pDrv;
4556
4557	/*
4558	* While we're here, give the windows backends a hint about our typical playback
4559	* configuration.
4560	* Note! If 48000Hz is advertised to the guest, add it here.
4561	*/
4562	if ( pDrv->pConnector
4563	&& pDrv->pConnector->pfnStreamConfigHint)
4564	{
4565	PDMAUDIOSTREAMCFG Cfg;
4566	RT_ZERO(Cfg);
4567	Cfg.enmDir = PDMAUDIODIR_OUT;
4568	Cfg.enmPath = PDMAUDIOPATH_OUT_FRONT;
4569	Cfg.Device.cMsSchedulingHint = 10;
4570	Cfg.Backend.cFramesPreBuffering = UINT32_MAX;
4571	PDMAudioPropsInit(&Cfg.Props, 2, true /fSigned/, 2, 44100);
4572	RTStrPrintf(Cfg.szName, sizeof(Cfg.szName), "output 44.1kHz 2ch S16 (HDA config hint)");
4573
4574	pDrv->pConnector->pfnStreamConfigHint(pDrv->pConnector, &Cfg); /* (may trash CfgReq) */
4575	}
4576
4577	LogFunc(("LUN#%u: returns VINF_SUCCESS (pCon=%p)\n", uLUN, pDrv->pConnector));
4578	return VINF_SUCCESS;
4579	}
4580
4581	rc = VERR_PDM_MISSING_INTERFACE_BELOW;
4582	}
4583	else if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
4584	LogFunc(("No attached driver for LUN #%u\n", uLUN));
4585	else
4586	LogFunc(("Failed attaching driver for LUN #%u: %Rrc\n", uLUN, rc));
4587	RTMemFree(pDrv);
4588
4589	LogFunc(("LUN#%u: rc=%Rrc\n", uLUN, rc));
4590	return rc;
4591	}
4592
4593
4594	/**
4595	* @interface_method_impl{PDMDEVREG,pfnAttach}
4596	*/
4597	static DECLCALLBACK(int) hdaR3Attach(PPDMDEVINS pDevIns, unsigned uLUN, uint32_t fFlags)
4598	{
4599	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
4600	PHDASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
4601	RT_NOREF(fFlags);
4602	LogFunc(("uLUN=%u, fFlags=0x%x\n", uLUN, fFlags));
4603
4604	DEVHDA_LOCK_RETURN(pDevIns, pThis, VERR_IGNORED);
4605
4606	PHDADRIVER pDrv;
4607	int rc = hdaR3AttachInternal(pDevIns, pThis, pThisCC, uLUN, &pDrv);
4608	if (RT_SUCCESS(rc))
4609	{
4610	int rc2 = hdaR3MixerAddDrv(pDevIns, pThisCC, pDrv);
4611	if (RT_FAILURE(rc2))
4612	LogFunc(("hdaR3MixerAddDrv failed with %Rrc (ignored)\n", rc2));
4613	}
4614
4615	DEVHDA_UNLOCK(pDevIns, pThis);
4616	return rc;
4617	}
4618
4619
4620	/**
4621	* Worker for hdaR3Detach that does all but free pDrv.
4622	*
4623	* This is called to let the device detach from a driver for a specified LUN
4624	* at runtime.
4625	*
4626	* @param pDevIns The device instance.
4627	* @param pThisCC The ring-3 HDA device state.
4628	* @param pDrv Driver to detach from device.
4629	*/
4630	static void hdaR3DetachInternal(PPDMDEVINS pDevIns, PHDASTATER3 pThisCC, PHDADRIVER pDrv)
4631	{
4632	/* Remove the driver from our list and destory it's associated streams.
4633	This also will un-set the driver as a recording source (if associated). */
4634	hdaR3MixerRemoveDrv(pDevIns, pThisCC, pDrv);
4635	LogFunc(("LUN#%u detached\n", pDrv->uLUN));
4636	}
4637
4638
4639	/**
4640	* @interface_method_impl{PDMDEVREG,pfnDetach}
4641	*/
4642	static DECLCALLBACK(void) hdaR3Detach(PPDMDEVINS pDevIns, unsigned iLUN, uint32_t fFlags)
4643	{
4644	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
4645	PHDASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
4646	RT_NOREF(fFlags);
4647	LogFunc(("iLUN=%u, fFlags=%#x\n", iLUN, fFlags));
4648
4649	DEVHDA_LOCK(pDevIns, pThis);
4650
4651	PHDADRIVER pDrv;
4652	RTListForEach(&pThisCC->lstDrv, pDrv, HDADRIVER, Node)
4653	{
4654	if (pDrv->uLUN == iLUN)
4655	{
4656	hdaR3DetachInternal(pDevIns, pThisCC, pDrv);
4657	RTMemFree(pDrv);
4658	DEVHDA_UNLOCK(pDevIns, pThis);
4659	return;
4660	}
4661	}
4662
4663	DEVHDA_UNLOCK(pDevIns, pThis);
4664	LogFunc(("LUN#%u was not found\n", iLUN));
4665	}
4666
4667
4668	/**
4669	* Powers off the device.
4670	*
4671	* @param pDevIns Device instance to power off.
4672	*/
4673	static DECLCALLBACK(void) hdaR3PowerOff(PPDMDEVINS pDevIns)
4674	{
4675	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
4676	PHDASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
4677
4678	DEVHDA_LOCK_RETURN_VOID(pDevIns, pThis);
4679
4680	LogRel2(("HDA: Powering off ...\n"));
4681
4682	/** @todo r=bird: What this "releasing references" and whatever here is
4683	* referring to, is apparently that the device is destroyed after the
4684	* drivers, so creating trouble as those structures have been torn down
4685	* already... Reverse order, like we do for power off? Need a new
4686	* PDMDEVREG flag. */
4687
4688	/* Ditto goes for the codec, which in turn uses the mixer. */
4689	hdaR3CodecPowerOff(&pThisCC->Codec);
4690
4691	/* This is to prevent us from calling into the mixer and mixer sink code
4692	after it has been destroyed below. */
4693	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
4694	pThisCC->aStreams[i].State.pAioRegSink = NULL; /* don't need to remove, we're destorying it. */
4695
4696	/*
4697	* Note: Destroy the mixer while powering off and not in hdaR3Destruct,
4698	* giving the mixer the chance to release any references held to
4699	* PDM audio streams it maintains.
4700	*/
4701	if (pThisCC->pMixer)
4702	{
4703	AudioMixerDestroy(pThisCC->pMixer, pDevIns);
4704	pThisCC->pMixer = NULL;
4705	}
4706
4707	DEVHDA_UNLOCK(pDevIns, pThis);
4708	}
4709
4710
4711	/**
4712	* @interface_method_impl{PDMDEVREG,pfnReset}
4713	*/
4714	static DECLCALLBACK(void) hdaR3Reset(PPDMDEVINS pDevIns)
4715	{
4716	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
4717	PHDASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
4718
4719	LogFlowFuncEnter();
4720
4721	DEVHDA_LOCK_RETURN_VOID(pDevIns, pThis);
4722
4723	/*
4724	* 18.2.6,7 defines that values of this registers might be cleared on power on/reset
4725	* hdaR3Reset shouldn't affects these registers.
4726	*/
4727	HDA_REG(pThis, WAKEEN) = 0x0;
4728
4729	hdaR3GCTLReset(pDevIns, pThis, pThisCC);
4730
4731	/* Indicate that HDA is not in reset. The firmware is supposed to (un)reset HDA,
4732	* but we can take a shortcut.
4733	*/
4734	HDA_REG(pThis, GCTL) = HDA_GCTL_CRST;
4735
4736	DEVHDA_UNLOCK(pDevIns, pThis);
4737	}
4738
4739
4740	/**
4741	* @interface_method_impl{PDMDEVREG,pfnDestruct}
4742	*/
4743	static DECLCALLBACK(int) hdaR3Destruct(PPDMDEVINS pDevIns)
4744	{
4745	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns); /* this shall come first */
4746	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
4747	PHDASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
4748
4749	if (PDMDevHlpCritSectIsInitialized(pDevIns, &pThis->CritSect))
4750	{
4751	int rc = PDMDevHlpCritSectEnter(pDevIns, &pThis->CritSect, VERR_IGNORED);
4752	AssertRC(rc);
4753	}
4754
4755	PHDADRIVER pDrv;
4756	while (!RTListIsEmpty(&pThisCC->lstDrv))
4757	{
4758	pDrv = RTListGetFirst(&pThisCC->lstDrv, HDADRIVER, Node);
4759
4760	RTListNodeRemove(&pDrv->Node);
4761	RTMemFree(pDrv);
4762	}
4763
4764	hdaCodecDestruct(&pThisCC->Codec);
4765
4766	for (uint8_t i = 0; i < HDA_MAX_STREAMS; i++)
4767	hdaR3StreamDestroy(&pThisCC->aStreams[i]);
4768
4769	/* We don't always go via PowerOff, so make sure the mixer is destroyed. */
4770	if (pThisCC->pMixer)
4771	{
4772	AudioMixerDestroy(pThisCC->pMixer, pDevIns);
4773	pThisCC->pMixer = NULL;
4774	}
4775
4776	if (PDMDevHlpCritSectIsInitialized(pDevIns, &pThis->CritSect))
4777	{
4778	PDMDevHlpCritSectLeave(pDevIns, &pThis->CritSect);
4779	PDMDevHlpCritSectDelete(pDevIns, &pThis->CritSect);
4780	}
4781	return VINF_SUCCESS;
4782	}
4783
4784
4785	/**
4786	* @interface_method_impl{PDMDEVREG,pfnConstruct}
4787	*/
4788	static DECLCALLBACK(int) hdaR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
4789	{
4790	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); /* this shall come first */
4791	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
4792	PHDASTATER3 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
4793	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
4794	Assert(iInstance == 0); RT_NOREF(iInstance);
4795
4796	/*
4797	* Initialize the state sufficently to make the destructor work.
4798	*/
4799	pThis->uAlignmentCheckMagic = HDASTATE_ALIGNMENT_CHECK_MAGIC;
4800	RTListInit(&pThisCC->lstDrv);
4801	pThis->cbCorbBuf = HDA_CORB_SIZE * HDA_CORB_ELEMENT_SIZE;
4802	pThis->cbRirbBuf = HDA_RIRB_SIZE * HDA_RIRB_ELEMENT_SIZE;
4803	pThis->hCorbDmaTask = NIL_PDMTASKHANDLE;
4804
4805	/** @todo r=bird: There are probably other things which should be
4806	* initialized here before we start failing. */
4807
4808	/*
4809	* Validate and read configuration.
4810	*/
4811	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns,
4812	"BufSizeInMs"
4813	"\|BufSizeOutMs"
4814	"\|DebugEnabled"
4815	"\|DebugPathOut"
4816	"\|DeviceName",
4817	"");
4818
4819	/** @devcfgm{hda,BufSizeInMs,uint16_t,0,2000,0,ms}
4820	* The size of the DMA buffer for input streams expressed in milliseconds. */
4821	int rc = pHlp->pfnCFGMQueryU16Def(pCfg, "BufSizeInMs", &pThis->cMsCircBufIn, 0);
4822	if (RT_FAILURE(rc))
4823	return PDMDEV_SET_ERROR(pDevIns, rc,
4824	N_("HDA configuration error: failed to read 'BufSizeInMs' as 16-bit unsigned integer"));
4825	if (pThis->cMsCircBufIn > 2000)
4826	return PDMDEV_SET_ERROR(pDevIns, VERR_OUT_OF_RANGE,
4827	N_("HDA configuration error: 'BufSizeInMs' is out of bound, max 2000 ms"));
4828
4829	/** @devcfgm{hda,BufSizeOutMs,uint16_t,0,2000,0,ms}
4830	* The size of the DMA buffer for output streams expressed in milliseconds. */
4831	rc = pHlp->pfnCFGMQueryU16Def(pCfg, "BufSizeOutMs", &pThis->cMsCircBufOut, 0);
4832	if (RT_FAILURE(rc))
4833	return PDMDEV_SET_ERROR(pDevIns, rc,
4834	N_("HDA configuration error: failed to read 'BufSizeOutMs' as 16-bit unsigned integer"));
4835	if (pThis->cMsCircBufOut > 2000)
4836	return PDMDEV_SET_ERROR(pDevIns, VERR_OUT_OF_RANGE,
4837	N_("HDA configuration error: 'BufSizeOutMs' is out of bound, max 2000 ms"));
4838
4839	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "DebugEnabled", &pThisCC->Dbg.fEnabled, false);
4840	if (RT_FAILURE(rc))
4841	return PDMDEV_SET_ERROR(pDevIns, rc,
4842	N_("HDA configuration error: failed to read debugging enabled flag as boolean"));
4843
4844	rc = pHlp->pfnCFGMQueryStringAllocDef(pCfg, "DebugPathOut", &pThisCC->Dbg.pszOutPath, NULL);
4845	if (RT_FAILURE(rc))
4846	return PDMDEV_SET_ERROR(pDevIns, rc,
4847	N_("HDA configuration error: failed to read debugging output path flag as string"));
4848	if (pThisCC->Dbg.fEnabled)
4849	LogRel2(("HDA: Debug output will be saved to '%s'\n", pThisCC->Dbg.pszOutPath));
4850
4851	/** @devcfgm{hda,DeviceName,string}
4852	* Override the default device/vendor IDs for the emulated device:
4853	* - "" - default
4854	* - "Intel ICH6"
4855	* - "Intel Sunrise Point" - great for macOS 10.15
4856	*/
4857	char szDeviceName[32];
4858	rc = pHlp->pfnCFGMQueryStringDef(pCfg, "DeviceName", szDeviceName, sizeof(szDeviceName), "");
4859	if (RT_FAILURE(rc))
4860	return PDMDEV_SET_ERROR(pDevIns, rc, N_("HDA configuration error: failed to read 'DeviceName' name string"));
4861	enum
4862	{
4863	kDevice_Default,
4864	kDevice_IntelIch6,
4865	kDevice_IntelSunrisePoint /skylake timeframe/
4866	} enmDevice;
4867	if (strcmp(szDeviceName, "") == 0)
4868	enmDevice = kDevice_Default;
4869	else if (strcmp(szDeviceName, "Intel ICH6") == 0)
4870	enmDevice = kDevice_IntelIch6;
4871	else if (strcmp(szDeviceName, "Intel Sunrise Point") == 0)
4872	enmDevice = kDevice_IntelSunrisePoint;
4873	else
4874	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
4875	N_("HDA configuration error: Unknown 'DeviceName' name '%s'"), szDeviceName);
4876
4877	/*
4878	* Use our own critical section for the device instead of the default
4879	* one provided by PDM. This allows fine-grained locking in combination
4880	* with TM when timer-specific stuff is being called in e.g. the MMIO handlers.
4881	*/
4882	rc = PDMDevHlpCritSectInit(pDevIns, &pThis->CritSect, RT_SRC_POS, "HDA");
4883	AssertRCReturn(rc, rc);
4884
4885	rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
4886	AssertRCReturn(rc, rc);
4887
4888	/*
4889	* Initialize data (most of it anyway).
4890	*/
4891	pThisCC->pDevIns = pDevIns;
4892	/* IBase */
4893	pThisCC->IBase.pfnQueryInterface = hdaR3QueryInterface;
4894
4895	/* PCI Device */
4896	PPDMPCIDEV pPciDev = pDevIns->apPciDevs[0];
4897	PDMPCIDEV_ASSERT_VALID(pDevIns, pPciDev);
4898
4899	switch (enmDevice)
4900	{
4901	case kDevice_Default:
4902	PDMPciDevSetVendorId(pPciDev, HDA_PCI_VENDOR_ID);
4903	PDMPciDevSetDeviceId(pPciDev, HDA_PCI_DEVICE_ID);
4904	break;
4905	case kDevice_IntelIch6: /* Our default intel device. */
4906	PDMPciDevSetVendorId(pPciDev, 0x8086);
4907	PDMPciDevSetDeviceId(pPciDev, 0x2668);
4908	break;
4909	case kDevice_IntelSunrisePoint: /* this is supported by more recent macOS version, at least 10.15 */
4910	PDMPciDevSetVendorId(pPciDev, 0x8086);
4911	PDMPciDevSetDeviceId(pPciDev, 0x9d70);
4912	break;
4913	}
4914
4915	PDMPciDevSetCommand( pPciDev, 0x0000); /* 04 rw,ro - pcicmd. */
4916	PDMPciDevSetStatus( pPciDev, VBOX_PCI_STATUS_CAP_LIST); /* 06 rwc?,ro? - pcists. */
4917	PDMPciDevSetRevisionId( pPciDev, 0x01); /* 08 ro - rid. */
4918	PDMPciDevSetClassProg( pPciDev, 0x00); /* 09 ro - pi. */
4919	PDMPciDevSetClassSub( pPciDev, 0x03); /* 0a ro - scc; 03 == HDA. */
4920	PDMPciDevSetClassBase( pPciDev, 0x04); /* 0b ro - bcc; 04 == multimedia. */
4921	PDMPciDevSetHeaderType( pPciDev, 0x00); /* 0e ro - headtyp. */
4922	PDMPciDevSetBaseAddress( pPciDev, 0, /* 10 rw - MMIO */
4923	false /* fIoSpace /, false / fPrefetchable /, true / f64Bit */, 0x00000000);
4924	PDMPciDevSetInterruptLine( pPciDev, 0x00); /* 3c rw. */
4925	PDMPciDevSetInterruptPin( pPciDev, 0x01); /* 3d ro - INTA#. */
4926
4927	# if defined(HDA_AS_PCI_EXPRESS)
4928	PDMPciDevSetCapabilityList(pPciDev, 0x80);
4929	# elif defined(VBOX_WITH_MSI_DEVICES)
4930	PDMPciDevSetCapabilityList(pPciDev, 0x60);
4931	# else
4932	PDMPciDevSetCapabilityList(pPciDev, 0x50); /* ICH6 datasheet 18.1.16 */
4933	# endif
4934
4935	/// @todo r=michaln: If there are really no PDMPciDevSetXx for these, the
4936	/// meaning of these values needs to be properly documented!
4937	/* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
4938	PDMPciDevSetByte( pPciDev, 0x40, 0x01);
4939
4940	/* Power Management */
4941	PDMPciDevSetByte( pPciDev, 0x50 + 0, VBOX_PCI_CAP_ID_PM);
4942	PDMPciDevSetByte( pPciDev, 0x50 + 1, 0x0); /* next */
4943	PDMPciDevSetWord( pPciDev, 0x50 + 2, VBOX_PCI_PM_CAP_DSI \| 0x02 /* version, PM1.1 */ );
4944
4945	# ifdef HDA_AS_PCI_EXPRESS
4946	/* PCI Express */
4947	PDMPciDevSetByte( pPciDev, 0x80 + 0, VBOX_PCI_CAP_ID_EXP); /* PCI_Express */
4948	PDMPciDevSetByte( pPciDev, 0x80 + 1, 0x60); /* next */
4949	/* Device flags */
4950	PDMPciDevSetWord( pPciDev, 0x80 + 2,
4951	1 /* version */
4952	\| (VBOX_PCI_EXP_TYPE_ROOT_INT_EP << 4) /* Root Complex Integrated Endpoint */
4953	\| (100 << 9) /* MSI */ );
4954	/* Device capabilities */
4955	PDMPciDevSetDWord( pPciDev, 0x80 + 4, VBOX_PCI_EXP_DEVCAP_FLRESET);
4956	/* Device control */
4957	PDMPciDevSetWord( pPciDev, 0x80 + 8, 0);
4958	/* Device status */
4959	PDMPciDevSetWord( pPciDev, 0x80 + 10, 0);
4960	/* Link caps */
4961	PDMPciDevSetDWord( pPciDev, 0x80 + 12, 0);
4962	/* Link control */
4963	PDMPciDevSetWord( pPciDev, 0x80 + 16, 0);
4964	/* Link status */
4965	PDMPciDevSetWord( pPciDev, 0x80 + 18, 0);
4966	/* Slot capabilities */
4967	PDMPciDevSetDWord( pPciDev, 0x80 + 20, 0);
4968	/* Slot control */
4969	PDMPciDevSetWord( pPciDev, 0x80 + 24, 0);
4970	/* Slot status */
4971	PDMPciDevSetWord( pPciDev, 0x80 + 26, 0);
4972	/* Root control */
4973	PDMPciDevSetWord( pPciDev, 0x80 + 28, 0);
4974	/* Root capabilities */
4975	PDMPciDevSetWord( pPciDev, 0x80 + 30, 0);
4976	/* Root status */
4977	PDMPciDevSetDWord( pPciDev, 0x80 + 32, 0);
4978	/* Device capabilities 2 */
4979	PDMPciDevSetDWord( pPciDev, 0x80 + 36, 0);
4980	/* Device control 2 */
4981	PDMPciDevSetQWord( pPciDev, 0x80 + 40, 0);
4982	/* Link control 2 */
4983	PDMPciDevSetQWord( pPciDev, 0x80 + 48, 0);
4984	/* Slot control 2 */
4985	PDMPciDevSetWord( pPciDev, 0x80 + 56, 0);
4986	# endif /* HDA_AS_PCI_EXPRESS */
4987
4988	/*
4989	* Register the PCI device.
4990	*/
4991	rc = PDMDevHlpPCIRegister(pDevIns, pPciDev);
4992	AssertRCReturn(rc, rc);
4993
4994	/** @todo r=bird: The IOMMMIO_FLAGS_READ_DWORD flag isn't entirely optimal,
4995	* as several frequently used registers aren't dword sized. 6.0 and earlier
4996	* will go to ring-3 to handle accesses to any such register, where-as 6.1 and
4997	* later will do trivial register reads in ring-0. Real optimal code would use
4998	* IOMMMIO_FLAGS_READ_PASSTHRU and do the necessary extra work to deal with
4999	* anything the guest may throw at us. */
5000	rc = PDMDevHlpPCIIORegionCreateMmio(pDevIns, 0, 0x4000, PCI_ADDRESS_SPACE_MEM, hdaMmioWrite, hdaMmioRead, NULL /pvUser/,
5001	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_PASSTHRU, "HDA", &pThis->hMmio);
5002	AssertRCReturn(rc, rc);
5003
5004	# ifdef VBOX_WITH_MSI_DEVICES
5005	PDMMSIREG MsiReg;
5006	RT_ZERO(MsiReg);
5007	MsiReg.cMsiVectors = 1;
5008	MsiReg.iMsiCapOffset = 0x60;
5009	MsiReg.iMsiNextOffset = 0x50;
5010	rc = PDMDevHlpPCIRegisterMsi(pDevIns, &MsiReg);
5011	if (RT_FAILURE(rc))
5012	{
5013	/* That's OK, we can work without MSI */
5014	PDMPciDevSetCapabilityList(pPciDev, 0x50);
5015	}
5016	# endif
5017
5018	/* Create task for continuing CORB DMA in ring-3. */
5019	rc = PDMDevHlpTaskCreate(pDevIns, PDMTASK_F_RZ, "HDA CORB DMA",
5020	hdaR3CorbDmaTaskWorker, NULL /pvUser/, &pThis->hCorbDmaTask);
5021	AssertRCReturn(rc,rc);
5022
5023	rc = PDMDevHlpSSMRegisterEx(pDevIns, HDA_SAVED_STATE_VERSION, sizeof(pThis), NULL /pszBefore*/,
5024	NULL /pfnLivePrep/, NULL /pfnLiveExec/, NULL /pfnLiveVote/,
5025	NULL /pfnSavePrep/, hdaR3SaveExec, NULL /pfnSaveDone/,
5026	NULL /pfnLoadPrep/, hdaR3LoadExec, hdaR3LoadDone);
5027	AssertRCReturn(rc, rc);
5028
5029	/*
5030	* Attach drivers. We ASSUME they are configured consecutively without any
5031	* gaps, so we stop when we hit the first LUN w/o a driver configured.
5032	*/
5033	for (unsigned iLun = 0; ; iLun++)
5034	{
5035	AssertBreak(iLun < UINT8_MAX);
5036	LogFunc(("Trying to attach driver for LUN#%u ...\n", iLun));
5037	rc = hdaR3AttachInternal(pDevIns, pThis, pThisCC, iLun, NULL /* ppDrv */);
5038	if (rc == VERR_PDM_NO_ATTACHED_DRIVER)
5039	{
5040	LogFunc(("cLUNs=%u\n", iLun));
5041	break;
5042	}
5043	AssertLogRelMsgReturn(RT_SUCCESS(rc), ("LUN#%u: rc=%Rrc\n", iLun, rc), rc);
5044	}
5045
5046	/*
5047	* Create the mixer.
5048	*/
5049	uint32_t fMixer = AUDMIXER_FLAGS_NONE;
5050	if (pThisCC->Dbg.fEnabled)
5051	fMixer \|= AUDMIXER_FLAGS_DEBUG;
5052	rc = AudioMixerCreate("HDA Mixer", fMixer, &pThisCC->pMixer);
5053	AssertRCReturn(rc, rc);
5054
5055	/*
5056	* Add mixer output sinks.
5057	*/
5058	# ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
5059	rc = AudioMixerCreateSink(pThisCC->pMixer, "Front",
5060	PDMAUDIODIR_OUT, pDevIns, &pThisCC->SinkFront.pMixSink);
5061	AssertRCReturn(rc, rc);
5062	rc = AudioMixerCreateSink(pThisCC->pMixer, "Center+Subwoofer",
5063	PDMAUDIODIR_OUT, pDevIns, &pThisCC->SinkCenterLFE.pMixSink);
5064	AssertRCReturn(rc, rc);
5065	rc = AudioMixerCreateSink(pThisCC->pMixer, "Rear",
5066	PDMAUDIODIR_OUT, pDevIns, &pThisCC->SinkRear.pMixSink);
5067	AssertRCReturn(rc, rc);
5068	# else
5069	rc = AudioMixerCreateSink(pThisCC->pMixer, "PCM Output",
5070	PDMAUDIODIR_OUT, pDevIns, &pThisCC->SinkFront.pMixSink);
5071	AssertRCReturn(rc, rc);
5072	# endif /* VBOX_WITH_AUDIO_HDA_51_SURROUND */
5073
5074	/*
5075	* Add mixer input sinks.
5076	*/
5077	rc = AudioMixerCreateSink(pThisCC->pMixer, "Line In",
5078	PDMAUDIODIR_IN, pDevIns, &pThisCC->SinkLineIn.pMixSink);
5079	AssertRCReturn(rc, rc);
5080	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
5081	rc = AudioMixerCreateSink(pThisCC->pMixer, "Microphone In",
5082	PDMAUDIODIR_IN, pDevIns, &pThisCC->SinkMicIn.pMixSink);
5083	AssertRCReturn(rc, rc);
5084	# endif
5085
5086	/* There is no master volume control. Set the master to max. */
5087	PDMAUDIOVOLUME Vol = PDMAUDIOVOLUME_INITIALIZER_MAX;
5088	rc = AudioMixerSetMasterVolume(pThisCC->pMixer, &Vol);
5089	AssertRCReturn(rc, rc);
5090
5091	/*
5092	* Initialize the codec.
5093	*/
5094	/* Construct the common + R3 codec part. */
5095	rc = hdaR3CodecConstruct(pDevIns, &pThisCC->Codec, 0 /* Codec index */, pCfg);
5096	AssertRCReturn(rc, rc);
5097
5098	/* ICH6 datasheet defines 0 values for SVID and SID (18.1.14-15), which together with values returned for
5099	verb F20 should provide device/codec recognition. */
5100	Assert(pThisCC->Codec.Cfg.idVendor);
5101	Assert(pThisCC->Codec.Cfg.idDevice);
5102	PDMPciDevSetSubSystemVendorId(pPciDev, pThisCC->Codec.Cfg.idVendor); /* 2c ro - intel.) */
5103	PDMPciDevSetSubSystemId( pPciDev, pThisCC->Codec.Cfg.idDevice); /* 2e ro. */
5104
5105	/*
5106	* Create the per stream timers and the asso.
5107	*
5108	* We must the critical section for the timers as the device has a
5109	* noop section associated with it.
5110	*
5111	* Note: Use TMCLOCK_VIRTUAL_SYNC here, as the guest's HDA driver relies
5112	* on exact (virtual) DMA timing and uses DMA Position Buffers
5113	* instead of the LPIB registers.
5114	*/
5115	/** @todo r=bird: The need to use virtual sync is perhaps because TM
5116	* doesn't schedule regular TMCLOCK_VIRTUAL timers as accurately as it
5117	* should (VT-x preemption timer, etc). Hope to address that before
5118	* long. @bugref{9943}. */
5119	static const char * const s_apszNames[] =
5120	{ "HDA SD0", "HDA SD1", "HDA SD2", "HDA SD3", "HDA SD4", "HDA SD5", "HDA SD6", "HDA SD7", };
5121	AssertCompile(RT_ELEMENTS(s_apszNames) == HDA_MAX_STREAMS);
5122	for (size_t i = 0; i < HDA_MAX_STREAMS; i++)
5123	{
5124	rc = PDMDevHlpTimerCreate(pDevIns, TMCLOCK_VIRTUAL_SYNC, hdaR3Timer, (void *)(uintptr_t)i,
5125	TMTIMER_FLAGS_NO_CRIT_SECT \| TMTIMER_FLAGS_RING0, s_apszNames[i], &pThis->aStreams[i].hTimer);
5126	AssertRCReturn(rc, rc);
5127
5128	rc = PDMDevHlpTimerSetCritSect(pDevIns, pThis->aStreams[i].hTimer, &pThis->CritSect);
5129	AssertRCReturn(rc, rc);
5130	}
5131
5132	/*
5133	* Create all hardware streams.
5134	*/
5135	for (uint8_t i = 0; i < HDA_MAX_STREAMS; ++i)
5136	{
5137	rc = hdaR3StreamConstruct(&pThis->aStreams[i], &pThisCC->aStreams[i], pThis, pThisCC, i /* u8SD */);
5138	AssertRCReturn(rc, rc);
5139	}
5140
5141	hdaR3Reset(pDevIns);
5142
5143	/*
5144	* Info items and string formatter types. The latter is non-optional as
5145	* the info handles use (at least some of) the custom types and we cannot
5146	* accept screwing formatting.
5147	*/
5148	PDMDevHlpDBGFInfoRegister(pDevIns, "hda", "HDA registers. (hda [register case-insensitive])", hdaR3DbgInfo);
5149	PDMDevHlpDBGFInfoRegister(pDevIns, "hdabdl",
5150	"HDA buffer descriptor list (BDL) and DMA stream positions. (hdabdl [stream number])",
5151	hdaR3DbgInfoBDL);
5152	PDMDevHlpDBGFInfoRegister(pDevIns, "hdastream", "HDA stream info. (hdastream [stream number])", hdaR3DbgInfoStream);
5153	PDMDevHlpDBGFInfoRegister(pDevIns, "hdcnodes", "HDA codec nodes.", hdaR3DbgInfoCodecNodes);
5154	PDMDevHlpDBGFInfoRegister(pDevIns, "hdcselector", "HDA codec's selector states [node number].", hdaR3DbgInfoCodecSelector);
5155	PDMDevHlpDBGFInfoRegister(pDevIns, "hdamixer", "HDA mixer state.", hdaR3DbgInfoMixer);
5156
5157	rc = RTStrFormatTypeRegister("sdctl", hdaR3StrFmtSDCTL, NULL);
5158	AssertMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_ALREADY_EXISTS, ("%Rrc\n", rc), rc);
5159	rc = RTStrFormatTypeRegister("sdsts", hdaR3StrFmtSDSTS, NULL);
5160	AssertMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_ALREADY_EXISTS, ("%Rrc\n", rc), rc);
5161	/** @todo the next two are rather pointless. */
5162	rc = RTStrFormatTypeRegister("sdfifos", hdaR3StrFmtSDFIFOS, NULL);
5163	AssertMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_ALREADY_EXISTS, ("%Rrc\n", rc), rc);
5164	rc = RTStrFormatTypeRegister("sdfifow", hdaR3StrFmtSDFIFOW, NULL);
5165	AssertMsgReturn(RT_SUCCESS(rc) \|\| rc == VERR_ALREADY_EXISTS, ("%Rrc\n", rc), rc);
5166
5167	/*
5168	* Asserting sanity.
5169	*/
5170	AssertCompile(RT_ELEMENTS(pThis->au32Regs) < 256 /* assumption by HDAREGDESC::idxReg */);
5171	for (unsigned i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
5172	{
5173	struct HDAREGDESC const *pReg = &g_aHdaRegMap[i];
5174	struct HDAREGDESC const *pNextReg = i + 1 < RT_ELEMENTS(g_aHdaRegMap) ? &g_aHdaRegMap[i + 1] : NULL;
5175
5176	/* binary search order. */
5177	AssertReleaseMsg(!pNextReg \|\| pReg->off + pReg->cb <= pNextReg->off,
5178	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5179	i, pReg->off, pReg->cb, i + 1, pNextReg->off, pNextReg->cb));
5180
5181	/* alignment. */
5182	AssertReleaseMsg( pReg->cb == 1
5183	\|\| (pReg->cb == 2 && (pReg->off & 1) == 0)
5184	\|\| (pReg->cb == 3 && (pReg->off & 3) == 0)
5185	\|\| (pReg->cb == 4 && (pReg->off & 3) == 0),
5186	("[%#x] = {%#x LB %#x}\n", i, pReg->off, pReg->cb));
5187
5188	/* registers are packed into dwords - with 3 exceptions with gaps at the end of the dword. */
5189	AssertRelease(((pReg->off + pReg->cb) & 3) == 0 \|\| pNextReg);
5190	if (pReg->off & 3)
5191	{
5192	struct HDAREGDESC const *pPrevReg = i > 0 ? &g_aHdaRegMap[i - 1] : NULL;
5193	AssertReleaseMsg(pPrevReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->off, pReg->cb));
5194	if (pPrevReg)
5195	AssertReleaseMsg(pPrevReg->off + pPrevReg->cb == pReg->off,
5196	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5197	i - 1, pPrevReg->off, pPrevReg->cb, i + 1, pReg->off, pReg->cb));
5198	}
5199	#if 0
5200	if ((pReg->offset + pReg->size) & 3)
5201	{
5202	AssertReleaseMsg(pNextReg, ("[%#x] = {%#x LB %#x}\n", i, pReg->offset, pReg->size));
5203	if (pNextReg)
5204	AssertReleaseMsg(pReg->offset + pReg->size == pNextReg->offset,
5205	("[%#x] = {%#x LB %#x} vs. [%#x] = {%#x LB %#x}\n",
5206	i, pReg->offset, pReg->size, i + 1, pNextReg->offset, pNextReg->size));
5207	}
5208	#endif
5209	/* The final entry is a full DWORD, no gaps! Allows shortcuts. */
5210	AssertReleaseMsg(pNextReg \|\| ((pReg->off + pReg->cb) & 3) == 0,
5211	("[%#x] = {%#x LB %#x}\n", i, pReg->off, pReg->cb));
5212	}
5213	Assert(strcmp(g_aHdaRegMap[HDA_REG_SSYNC].pszName, "SSYNC") == 0);
5214	Assert(strcmp(g_aHdaRegMap[HDA_REG_DPUBASE].pszName, "DPUBASE") == 0);
5215	Assert(strcmp(g_aHdaRegMap[HDA_REG_MLCH].pszName, "MLCH") == 0);
5216	Assert(strcmp(g_aHdaRegMap[HDA_REG_SD3DPIB].pszName, "SD3DPIB") == 0);
5217	Assert(strcmp(g_aHdaRegMap[HDA_REG_SD7EFIFOS].pszName, "SD7EFIFOS") == 0);
5218
5219	/*
5220	* Register statistics.
5221	*/
5222	# ifdef VBOX_WITH_STATISTICS
5223	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatIn, STAMTYPE_PROFILE, "Input", STAMUNIT_TICKS_PER_CALL, "Profiling input.");
5224	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatOut, STAMTYPE_PROFILE, "Output", STAMUNIT_TICKS_PER_CALL, "Profiling output.");
5225	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesRead, STAMTYPE_COUNTER, "BytesRead" , STAMUNIT_BYTES, "Bytes read (DMA) from the guest.");
5226	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatBytesWritten, STAMTYPE_COUNTER, "BytesWritten", STAMUNIT_BYTES, "Bytes written (DMA) to the guest.");
5227	# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
5228	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessDmaOutput, STAMTYPE_COUNTER, "AccessDmaOutput", STAMUNIT_COUNT, "Number of on-register-access DMA sub-transfers we've made.");
5229	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatAccessDmaOutputToR3,STAMTYPE_COUNTER, "AccessDmaOutputToR3", STAMUNIT_COUNT, "Number of time the on-register-access DMA forced a ring-3 return.");
5230	# endif
5231
5232	AssertCompile(RT_ELEMENTS(g_aHdaRegMap) == HDA_NUM_REGS);
5233	AssertCompile(RT_ELEMENTS(pThis->aStatRegReads) == HDA_NUM_REGS);
5234	AssertCompile(RT_ELEMENTS(pThis->aStatRegReadsToR3) == HDA_NUM_REGS);
5235	AssertCompile(RT_ELEMENTS(pThis->aStatRegWrites) == HDA_NUM_REGS);
5236	AssertCompile(RT_ELEMENTS(pThis->aStatRegWritesToR3) == HDA_NUM_REGS);
5237	for (size_t i = 0; i < RT_ELEMENTS(g_aHdaRegMap); i++)
5238	{
5239	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegReads[i], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
5240	g_aHdaRegMap[i].pszDesc, "Regs/%03x-%s-Reads", g_aHdaRegMap[i].off, g_aHdaRegMap[i].pszName);
5241	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegReadsToR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
5242	g_aHdaRegMap[i].pszDesc, "Regs/%03x-%s-Reads-ToR3", g_aHdaRegMap[i].off, g_aHdaRegMap[i].pszName);
5243	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegWrites[i], STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
5244	g_aHdaRegMap[i].pszDesc, "Regs/%03x-%s-Writes", g_aHdaRegMap[i].off, g_aHdaRegMap[i].pszName);
5245	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStatRegWritesToR3[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
5246	g_aHdaRegMap[i].pszDesc, "Regs/%03x-%s-Writes-ToR3", g_aHdaRegMap[i].off, g_aHdaRegMap[i].pszName);
5247	}
5248	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRegMultiReadsR3, STAMTYPE_COUNTER, "RegMultiReadsR3", STAMUNIT_OCCURENCES, "Register read not targeting just one register, handled in ring-3");
5249	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRegMultiReadsRZ, STAMTYPE_COUNTER, "RegMultiReadsRZ", STAMUNIT_OCCURENCES, "Register read not targeting just one register, handled in ring-0");
5250	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRegMultiWritesR3, STAMTYPE_COUNTER, "RegMultiWritesR3", STAMUNIT_OCCURENCES, "Register writes not targeting just one register, handled in ring-3");
5251	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRegMultiWritesRZ, STAMTYPE_COUNTER, "RegMultiWritesRZ", STAMUNIT_OCCURENCES, "Register writes not targeting just one register, handled in ring-0");
5252	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRegSubWriteR3, STAMTYPE_COUNTER, "RegSubWritesR3", STAMUNIT_OCCURENCES, "Trucated register writes, handled in ring-3");
5253	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRegSubWriteRZ, STAMTYPE_COUNTER, "RegSubWritesRZ", STAMUNIT_OCCURENCES, "Trucated register writes, handled in ring-0");
5254	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRegUnknownReads, STAMTYPE_COUNTER, "RegUnknownReads", STAMUNIT_OCCURENCES, "Reads of unknown registers.");
5255	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRegUnknownWrites, STAMTYPE_COUNTER, "RegUnknownWrites", STAMUNIT_OCCURENCES, "Writes to unknown registers.");
5256	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRegWritesBlockedByReset, STAMTYPE_COUNTER, "RegWritesBlockedByReset", STAMUNIT_OCCURENCES, "Writes blocked by pending reset (GCTL/CRST)");
5257	PDMDevHlpSTAMRegister(pDevIns, &pThis->StatRegWritesBlockedByRun, STAMTYPE_COUNTER, "RegWritesBlockedByRun", STAMUNIT_OCCURENCES, "Writes blocked by byte RUN bit.");
5258	# endif
5259
5260	for (uint8_t idxStream = 0; idxStream < RT_ELEMENTS(pThisCC->aStreams); idxStream++)
5261	{
5262	PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatDmaFlowProblems, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
5263	"Number of internal DMA buffer problems.", "Stream%u/DMABufferProblems", idxStream);
5264	if (hdaGetDirFromSD(idxStream) == PDMAUDIODIR_OUT)
5265	PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatDmaFlowErrors, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
5266	"Number of internal DMA buffer overflows.", "Stream%u/DMABufferOverflows", idxStream);
5267	else
5268	{
5269	PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatDmaFlowErrors, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
5270	"Number of internal DMA buffer underuns.", "Stream%u/DMABufferUnderruns", idxStream);
5271	PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatDmaFlowErrorBytes, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_BYTES,
5272	"Number of bytes of silence added to cope with underruns.", "Stream%u/DMABufferSilence", idxStream);
5273	}
5274	PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatDmaSkippedPendingBcis, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
5275	"DMA transfer period skipped because of BCIS pending.", "Stream%u/DMASkippedPendingBCIS", idxStream);
5276
5277	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStreams[idxStream].State.offRead, STAMTYPE_U64, STAMVISIBILITY_USED, STAMUNIT_BYTES,
5278	"Virtual internal buffer read position.", "Stream%u/offRead", idxStream);
5279	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStreams[idxStream].State.offWrite, STAMTYPE_U64, STAMVISIBILITY_USED, STAMUNIT_BYTES,
5280	"Virtual internal buffer write position.", "Stream%u/offWrite", idxStream);
5281	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStreams[idxStream].State.cbCurDmaPeriod, STAMTYPE_U32, STAMVISIBILITY_USED, STAMUNIT_BYTES,
5282	"Bytes transfered per DMA timer callout.", "Stream%u/cbCurDmaPeriod", idxStream);
5283	PDMDevHlpSTAMRegisterF(pDevIns, (void*)&pThis->aStreams[idxStream].State.fRunning, STAMTYPE_BOOL, STAMVISIBILITY_USED, STAMUNIT_BYTES,
5284	"True if the stream is in RUN mode.", "Stream%u/fRunning", idxStream);
5285	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStreams[idxStream].State.Cfg.Props.uHz, STAMTYPE_U32, STAMVISIBILITY_USED, STAMUNIT_HZ,
5286	"The stream frequency.", "Stream%u/Cfg/Hz", idxStream);
5287	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStreams[idxStream].State.Cfg.Props.cbFrame, STAMTYPE_U8, STAMVISIBILITY_USED, STAMUNIT_BYTES,
5288	"The frame size.", "Stream%u/Cfg/FrameSize", idxStream);
5289	#if 0 /** @todo this would require some callback or expansion. */
5290	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStreams[idxStream].State.Cfg.Props.cChannelsX, STAMTYPE_U8, STAMVISIBILITY_USED, STAMUNIT_BYTES,
5291	"The number of channels.", "Stream%u/Cfg/Channels-Host", idxStream);
5292	PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.Mapping.GuestProps.cChannels, STAMTYPE_U8, STAMVISIBILITY_USED, STAMUNIT_BYTES,
5293	"The number of channels.", "Stream%u/Cfg/Channels-Guest", idxStream);
5294	PDMDevHlpSTAMRegisterF(pDevIns, &pThis->aStreams[idxStream].State.Cfg.Props.cbSample, STAMTYPE_U8, STAMVISIBILITY_USED, STAMUNIT_BYTES,
5295	"The size of a sample (per channel).", "Stream%u/Cfg/cbSample", idxStream);
5296	#endif
5297
5298	PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatDmaBufSize, STAMTYPE_U32, STAMVISIBILITY_USED, STAMUNIT_BYTES,
5299	"Size of the internal DMA buffer.", "Stream%u/DMABufSize", idxStream);
5300	PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatDmaBufUsed, STAMTYPE_U32, STAMVISIBILITY_USED, STAMUNIT_BYTES,
5301	"Number of bytes used in the internal DMA buffer.", "Stream%u/DMABufUsed", idxStream);
5302
5303	PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatStart, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_NS_PER_CALL,
5304	"Starting the stream.", "Stream%u/Start", idxStream);
5305	PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatStop, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_NS_PER_CALL,
5306	"Stopping the stream.", "Stream%u/Stop", idxStream);
5307	PDMDevHlpSTAMRegisterF(pDevIns, &pThisCC->aStreams[idxStream].State.StatReset, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_NS_PER_CALL,
5308	"Resetting the stream.", "Stream%u/Reset", idxStream);
5309	}
5310
5311	return VINF_SUCCESS;
5312	}
5313
5314	#else /* !IN_RING3 */
5315
5316	/**
5317	* @callback_method_impl{PDMDEVREGR0,pfnConstruct}
5318	*/
5319	static DECLCALLBACK(int) hdaRZConstruct(PPDMDEVINS pDevIns)
5320	{
5321	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns); /* this shall come first */
5322	PHDASTATE pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
5323	PHDASTATER0 pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER0);
5324
5325	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
5326	AssertRCReturn(rc, rc);
5327
5328	rc = PDMDevHlpMmioSetUpContext(pDevIns, pThis->hMmio, hdaMmioWrite, hdaMmioRead, NULL /pvUser/);
5329	AssertRCReturn(rc, rc);
5330
5331	# if 0 /* Codec is not yet kosher enough for ring-0. @bugref{9890c64} */
5332	/* Construct the R0 codec part. */
5333	rc = hdaR0CodecConstruct(pDevIns, &pThis->Codec, &pThisCC->Codec);
5334	AssertRCReturn(rc, rc);
5335	# else
5336	RT_NOREF(pThisCC);
5337	# endif
5338
5339	return VINF_SUCCESS;
5340	}
5341
5342	#endif /* !IN_RING3 */
5343
5344	/**
5345	* The device registration structure.
5346	*/
5347	const PDMDEVREG g_DeviceHDA =
5348	{
5349	/* .u32Version = */ PDM_DEVREG_VERSION,
5350	/* .uReserved0 = */ 0,
5351	/* .szName = */ "hda",
5352	/* .fFlags = */ PDM_DEVREG_FLAGS_DEFAULT_BITS \| PDM_DEVREG_FLAGS_RZ \| PDM_DEVREG_FLAGS_NEW_STYLE
5353	\| PDM_DEVREG_FLAGS_FIRST_POWEROFF_NOTIFICATION /* stream clearnup with working drivers */,
5354	/* .fClass = */ PDM_DEVREG_CLASS_AUDIO,
5355	/* .cMaxInstances = */ 1,
5356	/* .uSharedVersion = */ 42,
5357	/* .cbInstanceShared = */ sizeof(HDASTATE),
5358	/* .cbInstanceCC = */ CTX_EXPR(sizeof(HDASTATER3), sizeof(HDASTATER0), 0),
5359	/* .cbInstanceRC = */ 0,
5360	/* .cMaxPciDevices = */ 1,
5361	/* .cMaxMsixVectors = */ 0,
5362	/* .pszDescription = */ "Intel HD Audio Controller",
5363	#if defined(IN_RING3)
5364	/* .pszRCMod = */ "VBoxDDRC.rc",
5365	/* .pszR0Mod = */ "VBoxDDR0.r0",
5366	/* .pfnConstruct = */ hdaR3Construct,
5367	/* .pfnDestruct = */ hdaR3Destruct,
5368	/* .pfnRelocate = */ NULL,
5369	/* .pfnMemSetup = */ NULL,
5370	/* .pfnPowerOn = */ NULL,
5371	/* .pfnReset = */ hdaR3Reset,
5372	/* .pfnSuspend = */ NULL,
5373	/* .pfnResume = */ NULL,
5374	/* .pfnAttach = */ hdaR3Attach,
5375	/* .pfnDetach = */ hdaR3Detach,
5376	/* .pfnQueryInterface = */ NULL,
5377	/* .pfnInitComplete = */ NULL,
5378	/* .pfnPowerOff = */ hdaR3PowerOff,
5379	/* .pfnSoftReset = */ NULL,
5380	/* .pfnReserved0 = */ NULL,
5381	/* .pfnReserved1 = */ NULL,
5382	/* .pfnReserved2 = */ NULL,
5383	/* .pfnReserved3 = */ NULL,
5384	/* .pfnReserved4 = */ NULL,
5385	/* .pfnReserved5 = */ NULL,
5386	/* .pfnReserved6 = */ NULL,
5387	/* .pfnReserved7 = */ NULL,
5388	#elif defined(IN_RING0)
5389	/* .pfnEarlyConstruct = */ NULL,
5390	/* .pfnConstruct = */ hdaRZConstruct,
5391	/* .pfnDestruct = */ NULL,
5392	/* .pfnFinalDestruct = */ NULL,
5393	/* .pfnRequest = */ NULL,
5394	/* .pfnReserved0 = */ NULL,
5395	/* .pfnReserved1 = */ NULL,
5396	/* .pfnReserved2 = */ NULL,
5397	/* .pfnReserved3 = */ NULL,
5398	/* .pfnReserved4 = */ NULL,
5399	/* .pfnReserved5 = */ NULL,
5400	/* .pfnReserved6 = */ NULL,
5401	/* .pfnReserved7 = */ NULL,
5402	#elif defined(IN_RC)
5403	/* .pfnConstruct = */ hdaRZConstruct,
5404	/* .pfnReserved0 = */ NULL,
5405	/* .pfnReserved1 = */ NULL,
5406	/* .pfnReserved2 = */ NULL,
5407	/* .pfnReserved3 = */ NULL,
5408	/* .pfnReserved4 = */ NULL,
5409	/* .pfnReserved5 = */ NULL,
5410	/* .pfnReserved6 = */ NULL,
5411	/* .pfnReserved7 = */ NULL,
5412	#else
5413	# error "Not in IN_RING3, IN_RING0 or IN_RC!"
5414	#endif
5415	/* .u32VersionEnd = */ PDM_DEVREG_VERSION
5416	};
5417
5418	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
5419

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source: vbox/trunk/src/VBox/Devices/Audio/DevHda.cpp@ 92030

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