VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevHda.h@ 89873

Last change on this file since 89873 was 89873, checked in by vboxsync, 4 years ago

DevHda: Removed now obsolete config values: PosAdjustEnabled, PosAdjustFrames and TransferHeuristicsEnabled. bugref:9890

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1/* $Id: DevHda.h 89873 2021-06-24 09:11:18Z vboxsync $ */
2/** @file
3 * Intel HD Audio Controller Emulation - Structures.
4 */
5
6/*
7 * Copyright (C) 2016-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18#ifndef VBOX_INCLUDED_SRC_Audio_DevHda_h
19#define VBOX_INCLUDED_SRC_Audio_DevHda_h
20#ifndef RT_WITHOUT_PRAGMA_ONCE
21# pragma once
22#endif
23
24#include <iprt/path.h>
25#include <VBox/vmm/pdmdev.h>
26#include "AudioMixer.h"
27
28/*
29 * Compile time feature configuration.
30 */
31
32/** @def VBOX_HDA_WITH_ON_REG_ACCESS_DMA
33 * Enables doing DMA work on certain register accesses (LPIB, WALCLK) in
34 * addition to the DMA timer. All but the last frame can be done during
35 * register accesses (as we don't wish to leave the DMA timer w/o work to
36 * do in case that upsets it). */
37#if defined(DOXYGEN_RUNNING) || 0
38# define VBOX_HDA_WITH_ON_REG_ACCESS_DMA
39#endif
40
41#ifdef DEBUG_andy
42/** Enables strict mode, which checks for stuff which isn't supposed to happen.
43 * Be prepared for assertions coming in! */
44//# define HDA_STRICT
45#endif
46
47
48/*
49 * Common pointer types.
50 */
51/** Pointer to an HDA stream (SDI / SDO). */
52typedef struct HDASTREAMR3 *PHDASTREAMR3;
53/** Pointer to a shared HDA device state. */
54typedef struct HDASTATE *PHDASTATE;
55/** Pointer to a ring-3 HDA device state. */
56typedef struct HDASTATER3 *PHDASTATER3;
57
58
59/*
60 * The rest of the headers.
61 */
62#include "DevHdaCommon.h"
63#include "DevHdaStream.h"
64#include "DevHdaCodec.h"
65
66
67/**
68 * HDA mixer sink definition (ring-3).
69 *
70 * Its purpose is to know which audio mixer sink is bound to which SDn
71 * (SDI/SDO) device stream.
72 *
73 * This is needed in order to handle interleaved streams (that is, multiple
74 * channels in one stream) or non-interleaved streams (each channel has a
75 * dedicated stream).
76 *
77 * This is only known to the actual device emulation level.
78 */
79typedef struct HDAMIXERSINK
80{
81 R3PTRTYPE(PHDASTREAM) pStreamShared;
82 R3PTRTYPE(PHDASTREAMR3) pStreamR3;
83 /** Pointer to the actual audio mixer sink. */
84 R3PTRTYPE(PAUDMIXSINK) pMixSink;
85} HDAMIXERSINK;
86/** Pointer to an HDA mixer sink definition (ring-3). */
87typedef HDAMIXERSINK *PHDAMIXERSINK;
88
89/**
90 * Mapping a stream tag to an HDA stream (ring-3).
91 */
92typedef struct HDATAG
93{
94 /** Own stream tag. */
95 uint8_t uTag;
96 uint8_t Padding[7];
97 /** Pointer to associated stream. */
98 R3PTRTYPE(PHDASTREAMR3) pStreamR3;
99} HDATAG;
100/** Pointer to a HDA stream tag mapping. */
101typedef HDATAG *PHDATAG;
102
103/**
104 * Shared ICH Intel HD audio controller state.
105 */
106typedef struct HDASTATE
107{
108 /** Critical section protecting the HDA state. */
109 PDMCRITSECT CritSect;
110 /** Internal stream states (aligned on 64 byte boundrary). */
111 HDASTREAM aStreams[HDA_MAX_STREAMS];
112 /** The HDA's register set. */
113 uint32_t au32Regs[HDA_NUM_REGS];
114 /** CORB buffer base address. */
115 uint64_t u64CORBBase;
116 /** RIRB buffer base address. */
117 uint64_t u64RIRBBase;
118 /** DMA base address.
119 * Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
120 uint64_t u64DPBase;
121 /** Size in bytes of CORB buffer (#au32CorbBuf). */
122 uint32_t cbCorbBuf;
123 /** Size in bytes of RIRB buffer (#au64RirbBuf). */
124 uint32_t cbRirbBuf;
125 /** Response Interrupt Count (RINTCNT). */
126 uint16_t u16RespIntCnt;
127 /** DMA position buffer enable bit. */
128 bool fDMAPosition;
129 /** Current IRQ level. */
130 uint8_t u8IRQL;
131 uint8_t abPadding[4];
132 /** The device timer Hz rate. Defaults to HDA_TIMER_HZ_DEFAULT. */
133 uint16_t uTimerHz;
134 /** Number of milliseconds to delay kicking off the AIO when a stream starts.
135 * @sa InitialDelayMs config value. */
136 uint16_t msInitialDelay;
137 /** Config: Internal input DMA buffer size override, specified in milliseconds.
138 * Zero means default size according to buffer and stream config.
139 * @sa BufSizeInMs config value. */
140 uint16_t cMsCircBufIn;
141 /** Config: Internal output DMA buffer size override, specified in milliseconds.
142 * Zero means default size according to buffer and stream config.
143 * @sa BufSizeOutMs config value. */
144 uint16_t cMsCircBufOut;
145 /** The start time of the wall clock (WALCLK), measured on the virtual sync clock. */
146 uint64_t tsWalClkStart;
147 /** CORB DMA task handle.
148 * We use this when there is stuff we cannot handle in ring-0. */
149 PDMTASKHANDLE hCorbDmaTask;
150 /** The CORB buffer. */
151 uint32_t au32CorbBuf[HDA_CORB_SIZE];
152 /** Pointer to RIRB buffer. */
153 uint64_t au64RirbBuf[HDA_RIRB_SIZE];
154
155 /** PCI Region \#0: 16KB of MMIO stuff. */
156 IOMMMIOHANDLE hMmio;
157
158 /** Shared R0/R3 HDA codec to use. */
159 HDACODEC Codec;
160
161#ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
162 STAMCOUNTER StatAccessDmaOutput;
163 STAMCOUNTER StatAccessDmaOutputToR3;
164#endif
165#ifdef VBOX_WITH_STATISTICS
166 STAMPROFILE StatIn;
167 STAMPROFILE StatOut;
168 STAMCOUNTER StatBytesRead;
169 STAMCOUNTER StatBytesWritten;
170
171 /** @name Register statistics.
172 * The array members run parallel to g_aHdaRegMap.
173 * @{ */
174 STAMCOUNTER aStatRegReads[HDA_NUM_REGS];
175 STAMCOUNTER aStatRegReadsToR3[HDA_NUM_REGS];
176 STAMCOUNTER aStatRegWrites[HDA_NUM_REGS];
177 STAMCOUNTER aStatRegWritesToR3[HDA_NUM_REGS];
178 STAMCOUNTER StatRegMultiReadsRZ;
179 STAMCOUNTER StatRegMultiReadsR3;
180 STAMCOUNTER StatRegMultiWritesRZ;
181 STAMCOUNTER StatRegMultiWritesR3;
182 STAMCOUNTER StatRegSubWriteRZ;
183 STAMCOUNTER StatRegSubWriteR3;
184 STAMCOUNTER StatRegUnknownReads;
185 STAMCOUNTER StatRegUnknownWrites;
186 STAMCOUNTER StatRegWritesBlockedByReset;
187 STAMCOUNTER StatRegWritesBlockedByRun;
188 /** @} */
189#endif
190
191#ifdef DEBUG
192 /** Debug stuff.
193 * @todo Make STAM values out some of this? */
194 struct
195 {
196# if 0 /* unused */
197 /** Timestamp (in ns) of the last timer callback (hdaTimer).
198 * Used to calculate the time actually elapsed between two timer callbacks. */
199 uint64_t tsTimerLastCalledNs;
200# endif
201 /** IRQ debugging information. */
202 struct
203 {
204 /** Timestamp (in ns) of last processed (asserted / deasserted) IRQ. */
205 uint64_t tsProcessedLastNs;
206 /** Timestamp (in ns) of last asserted IRQ. */
207 uint64_t tsAssertedNs;
208# if 0 /* unused */
209 /** How many IRQs have been asserted already. */
210 uint64_t cAsserted;
211 /** Accumulated elapsed time (in ns) of all IRQ being asserted. */
212 uint64_t tsAssertedTotalNs;
213 /** Timestamp (in ns) of last deasserted IRQ. */
214 uint64_t tsDeassertedNs;
215 /** How many IRQs have been deasserted already. */
216 uint64_t cDeasserted;
217 /** Accumulated elapsed time (in ns) of all IRQ being deasserted. */
218 uint64_t tsDeassertedTotalNs;
219# endif
220 } IRQ;
221 } Dbg;
222#endif
223 /** This is for checking that the build was correctly configured in all contexts.
224 * This is set to HDASTATE_ALIGNMENT_CHECK_MAGIC. */
225 uint64_t uAlignmentCheckMagic;
226} HDASTATE;
227AssertCompileMemberAlignment(HDASTATE, aStreams, 64);
228/** Pointer to a shared HDA device state. */
229typedef HDASTATE *PHDASTATE;
230
231/** Value for HDASTATE:uAlignmentCheckMagic. */
232#define HDASTATE_ALIGNMENT_CHECK_MAGIC UINT64_C(0x1298afb75893e059)
233
234/**
235 * Ring-0 ICH Intel HD audio controller state.
236 */
237typedef struct HDASTATER0
238{
239# if 0 /* Codec is not yet kosher enough for ring-0. @bugref{9890c64} */
240 /** Pointer to HDA codec to use. */
241 HDACODECR0 Codec;
242# else
243 uint32_t u32Dummy;
244# endif
245} HDASTATER0;
246/** Pointer to a ring-0 HDA device state. */
247typedef HDASTATER0 *PHDASTATER0;
248
249/**
250 * Ring-3 ICH Intel HD audio controller state.
251 */
252typedef struct HDASTATER3
253{
254 /** Internal stream states. */
255 HDASTREAMR3 aStreams[HDA_MAX_STREAMS];
256 /** Mapping table between stream tags and stream states. */
257 HDATAG aTags[HDA_MAX_TAGS];
258 /** R3 Pointer to the device instance. */
259 PPDMDEVINSR3 pDevIns;
260 /** The base interface for LUN\#0. */
261 PDMIBASE IBase;
262 /** Pointer to HDA codec to use. */
263 R3PTRTYPE(PHDACODECR3) pCodec;
264 /** List of associated LUN drivers (HDADRIVER). */
265 RTLISTANCHORR3 lstDrv;
266 /** The device' software mixer. */
267 R3PTRTYPE(PAUDIOMIXER) pMixer;
268 /** HDA sink for (front) output. */
269 HDAMIXERSINK SinkFront;
270#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
271 /** HDA sink for center / LFE output. */
272 HDAMIXERSINK SinkCenterLFE;
273 /** HDA sink for rear output. */
274 HDAMIXERSINK SinkRear;
275#endif
276 /** HDA mixer sink for line input. */
277 HDAMIXERSINK SinkLineIn;
278#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
279 /** Audio mixer sink for microphone input. */
280 HDAMIXERSINK SinkMicIn;
281#endif
282 /** Debug stuff. */
283 struct
284 {
285 /** Whether debugging is enabled or not. */
286 bool fEnabled;
287 /** Path where to dump the debug output to.
288 * Can be NULL, in which the system's temporary directory will be used then. */
289 R3PTRTYPE(char *) pszOutPath;
290 } Dbg;
291} HDASTATER3;
292
293
294/** Pointer to the context specific HDA state (HDASTATER3 or HDASTATER0). */
295typedef CTX_SUFF(PHDASTATE) PHDASTATECC;
296
297#endif /* !VBOX_INCLUDED_SRC_Audio_DevHda_h */
298
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