DevHda.h@ 89897

Last change on this file since 89897 was 89897, checked in by vboxsync, 4 years ago
DevHda: Avoid indirect register accesses via g_aHdaRegMap. bugref:9890
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1	/* $Id: DevHda.h 89897 2021-06-24 18:28:04Z vboxsync $ */
2	/** @file
3	* Intel HD Audio Controller Emulation - Structures.
4	*/
5
6	/*
7	* Copyright (C) 2016-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VBOX_INCLUDED_SRC_Audio_DevHda_h
19	#define VBOX_INCLUDED_SRC_Audio_DevHda_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <iprt/path.h>
25	#include <VBox/vmm/pdmdev.h>
26	#include "AudioMixer.h"
27
28	/*
29	* Compile time feature configuration.
30	*/
31
32	/** @def VBOX_HDA_WITH_ON_REG_ACCESS_DMA
33	* Enables doing DMA work on certain register accesses (LPIB, WALCLK) in
34	* addition to the DMA timer. All but the last frame can be done during
35	* register accesses (as we don't wish to leave the DMA timer w/o work to
36	* do in case that upsets it). */
37	#if defined(DOXYGEN_RUNNING) \|\| 0
38	# define VBOX_HDA_WITH_ON_REG_ACCESS_DMA
39	#endif
40
41	#ifdef DEBUG_andy
42	/** Enables strict mode, which checks for stuff which isn't supposed to happen.
43	* Be prepared for assertions coming in! */
44	//# define HDA_STRICT
45	#endif
46
47	/** @def HDA_AS_PCI_EXPRESS
48	* Enables PCI express hardware. */
49	#if defined(DOXYGEN_RUNNING) \|\| 0
50	# define HDA_AS_PCI_EXPRESS
51	#endif
52
53	/** @def HDA_DEBUG_SILENCE
54	* To debug silence coming from the guest in form of audio gaps.
55	* Very crude implementation for now.
56	* @todo probably borked atm */
57	#if defined(DOXYGEN_RUNNING) \|\| 0
58	# define HDA_DEBUG_SILENCE
59	#endif
60
61
62	/*
63	* Common pointer types.
64	*/
65	/** Pointer to an HDA stream (SDI / SDO). */
66	typedef struct HDASTREAMR3 *PHDASTREAMR3;
67	/** Pointer to a shared HDA device state. */
68	typedef struct HDASTATE *PHDASTATE;
69	/** Pointer to a ring-3 HDA device state. */
70	typedef struct HDASTATER3 *PHDASTATER3;
71	/** Pointer to an HDA mixer sink definition (ring-3). */
72	typedef struct HDAMIXERSINK *PHDAMIXERSINK;
73
74
75	/*
76	* The rest of the headers.
77	*/
78	#include "DevHdaStream.h"
79	#include "DevHdaCodec.h"
80
81
82
83	/** @name Stream counts.
84	*
85	* At the moment we support 4 input + 4 output streams max, which is 8 in total.
86	* Bidirectional streams are currently not supported.
87	*
88	* @note When changing any of those values, be prepared for some saved state
89	* fixups / trouble!
90	* @{
91	*/
92	#define HDA_MAX_SDI 4
93	#define HDA_MAX_SDO 4
94	#define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
95	/** @} */
96	AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
97
98
99	/** Number of general registers. */
100	#define HDA_NUM_GENERAL_REGS 34
101	/** Number of total registers in the HDA's register map. */
102	#define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */))
103	/** Total number of stream tags (channels). Index 0 is reserved / invalid. */
104	#define HDA_MAX_TAGS 16
105
106
107	/** Read callback. */
108	typedef VBOXSTRICTRC FNHDAREGREAD(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
109	/** Write callback. */
110	typedef VBOXSTRICTRC FNHDAREGWRITE(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
111
112	/**
113	* HDA register descriptor.
114	*/
115	typedef struct HDAREGDESC
116	{
117	/** Register offset in the register space. */
118	uint32_t offset;
119	/** Size in bytes. Registers of size > 4 are in fact tables. */
120	uint32_t size;
121	/** Readable bits. */
122	uint32_t readable;
123	/** Writable bits. */
124	uint32_t writable;
125	/** Register descriptor (RD) flags of type HDA_RD_F_XXX. These are used to
126	* specify the read/write handling policy of the register. */
127	uint32_t fFlags;
128	/** Read callback. */
129	FNHDAREGREAD *pfnRead;
130	/** Write callback. */
131	FNHDAREGWRITE *pfnWrite;
132	/** Index into the register storage array.
133	* @todo r=bird: Bad structure layout. Move up before pfnRead. */
134	uint32_t mem_idx;
135	/** Abbreviated name. */
136	const char *abbrev;
137	/** Descripton. */
138	const char *desc;
139	} HDAREGDESC;
140
141	#ifdef VBOX_STRICT
142	extern const HDAREGDESC g_aHdaRegMap[HDA_NUM_REGS];
143	#endif
144
145
146	/**
147	* ICH6 datasheet defines limits for FIFOS registers (18.2.39).
148	* Formula: size - 1
149	* Other values not listed are not supported.
150	*/
151
152	/** Offset of the SD0 register map. */
153	#define HDA_REG_DESC_SD0_BASE 0x80
154
155	/*
156	* NB: Register values stored in memory (au32Regs[]) are indexed through
157	* the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
158	* register descriptors in g_aHdaRegMap[] are indexed through the
159	* HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
160	*
161	* The au32Regs[] layout is kept unchanged for saved state compatibility.
162	*/
163
164	/* Registers */
165	#define HDA_REG_IND_NAME(x) HDA_REG_##x
166	#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
167
168	/** Direct register access by HDASTATE::au32Reg index. */
169	#define HDA_REG_BY_IDX(a_pThis, a_idxReg) ((a_pThis)->au32Regs[(a_idxReg)])
170	/** Accesses register @a ShortRegNm. */
171	#define HDA_REG(a_pThis, a_ShortRegNm) HDA_REG_BY_IDX(a_pThis, HDA_MEM_IND_NAME(a_ShortRegNm))
172	/** Indirect register access via g_aHdaRegMap[].mem_idx. */
173	#define HDA_REG_IND(a_pThis, a_idxMap) HDA_REG_BY_IDX(a_pThis, g_aHdaRegMap[(a_idxMap)].mem_idx)
174
175
176	#define HDA_REG_GCAP 0 /* Range 0x00 - 0x01 */
177	#define HDA_RMX_GCAP 0
178	/**
179	* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
180	*
181	* oss (15:12) - Number of output streams supported.
182	* iss (11:8) - Number of input streams supported.
183	* bss (7:3) - Number of bidirectional streams supported.
184	* bds (2:1) - Number of serial data out (SDO) signals supported.
185	* b64sup (0) - 64 bit addressing supported.
186	*/
187	#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
188	( (((oss) & 0xF) << 12) \
189	\| (((iss) & 0xF) << 8) \
190	\| (((bss) & 0x1F) << 3) \
191	\| (((bds) & 0x3) << 2) \
192	\| ((b64sup) & 1))
193
194	#define HDA_REG_VMIN 1 /* 0x02 */
195	#define HDA_RMX_VMIN 1
196
197	#define HDA_REG_VMAJ 2 /* 0x03 */
198	#define HDA_RMX_VMAJ 2
199
200	#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
201	#define HDA_RMX_OUTPAY 3
202
203	#define HDA_REG_INPAY 4 /* 0x06-0x07 */
204	#define HDA_RMX_INPAY 4
205
206	#define HDA_REG_GCTL 5 /* 0x08-0x0B */
207	#define HDA_RMX_GCTL 5
208	#define HDA_GCTL_UNSOL RT_BIT(8) /* Accept Unsolicited Response Enable */
209	#define HDA_GCTL_FCNTRL RT_BIT(1) /* Flush Control */
210	#define HDA_GCTL_CRST RT_BIT(0) /* Controller Reset */
211
212	#define HDA_REG_WAKEEN 6 /* 0x0C */
213	#define HDA_RMX_WAKEEN 6
214
215	#define HDA_REG_STATESTS 7 /* 0x0E */
216	#define HDA_RMX_STATESTS 7
217	#define HDA_STATESTS_SCSF_MASK 0x7 /* State Change Status Flags (6.2.8). */
218
219	#define HDA_REG_GSTS 8 /* 0x10-0x11*/
220	#define HDA_RMX_GSTS 8
221	#define HDA_GSTS_FSTS RT_BIT(1) /* Flush Status */
222
223	#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
224	#define HDA_RMX_OUTSTRMPAY 112
225
226	#define HDA_REG_INSTRMPAY 10 /* 0x1a */
227	#define HDA_RMX_INSTRMPAY 113
228
229	#define HDA_REG_INTCTL 11 /* 0x20 */
230	#define HDA_RMX_INTCTL 9
231	#define HDA_INTCTL_GIE RT_BIT(31) /* Global Interrupt Enable */
232	#define HDA_INTCTL_CIE RT_BIT(30) /* Controller Interrupt Enable */
233	/** Bits 0-29 correspond to streams 0-29. */
234	#define HDA_STRMINT_MASK 0xFF /* Streams 0-7 implemented. Applies to INTCTL and INTSTS. */
235
236	#define HDA_REG_INTSTS 12 /* 0x24 */
237	#define HDA_RMX_INTSTS 10
238	#define HDA_INTSTS_GIS RT_BIT(31) /* Global Interrupt Status */
239	#define HDA_INTSTS_CIS RT_BIT(30) /* Controller Interrupt Status */
240
241	#define HDA_REG_WALCLK 13 /* 0x30 */
242	/*NB: HDA_RMX_WALCLK is not defined because the register is not stored in memory. /
243
244	/**
245	* Note: The HDA specification defines a SSYNC register at offset 0x38. The
246	* ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
247	* the datasheet.
248	*/
249	#define HDA_REG_SSYNC 14 /* 0x34 */
250	#define HDA_RMX_SSYNC 12
251
252	#define HDA_REG_CORBLBASE 15 /* 0x40 */
253	#define HDA_RMX_CORBLBASE 13
254
255	#define HDA_REG_CORBUBASE 16 /* 0x44 */
256	#define HDA_RMX_CORBUBASE 14
257
258	#define HDA_REG_CORBWP 17 /* 0x48 */
259	#define HDA_RMX_CORBWP 15
260
261	#define HDA_REG_CORBRP 18 /* 0x4A */
262	#define HDA_RMX_CORBRP 16
263	#define HDA_CORBRP_RST RT_BIT(15) /* CORB Read Pointer Reset */
264
265	#define HDA_REG_CORBCTL 19 /* 0x4C */
266	#define HDA_RMX_CORBCTL 17
267	#define HDA_CORBCTL_DMA RT_BIT(1) /* Enable CORB DMA Engine */
268	#define HDA_CORBCTL_CMEIE RT_BIT(0) /* CORB Memory Error Interrupt Enable */
269
270	#define HDA_REG_CORBSTS 20 /* 0x4D */
271	#define HDA_RMX_CORBSTS 18
272
273	#define HDA_REG_CORBSIZE 21 /* 0x4E */
274	#define HDA_RMX_CORBSIZE 19
275	#define HDA_CORBSIZE_SZ_CAP 0xF0
276	#define HDA_CORBSIZE_SZ 0x3
277
278	/** Number of CORB buffer entries. */
279	#define HDA_CORB_SIZE 256
280	/** CORB element size (in bytes). */
281	#define HDA_CORB_ELEMENT_SIZE 4
282	/** Number of RIRB buffer entries. */
283	#define HDA_RIRB_SIZE 256
284	/** RIRB element size (in bytes). */
285	#define HDA_RIRB_ELEMENT_SIZE 8
286
287	#define HDA_REG_RIRBLBASE 22 /* 0x50 */
288	#define HDA_RMX_RIRBLBASE 20
289
290	#define HDA_REG_RIRBUBASE 23 /* 0x54 */
291	#define HDA_RMX_RIRBUBASE 21
292
293	#define HDA_REG_RIRBWP 24 /* 0x58 */
294	#define HDA_RMX_RIRBWP 22
295	#define HDA_RIRBWP_RST RT_BIT(15) /* RIRB Write Pointer Reset */
296
297	#define HDA_REG_RINTCNT 25 /* 0x5A */
298	#define HDA_RMX_RINTCNT 23
299
300	/** Maximum number of Response Interrupts. */
301	#define HDA_MAX_RINTCNT 256
302
303	#define HDA_REG_RIRBCTL 26 /* 0x5C */
304	#define HDA_RMX_RIRBCTL 24
305	#define HDA_RIRBCTL_ROIC RT_BIT(2) /* Response Overrun Interrupt Control */
306	#define HDA_RIRBCTL_RDMAEN RT_BIT(1) /* RIRB DMA Enable */
307	#define HDA_RIRBCTL_RINTCTL RT_BIT(0) /* Response Interrupt Control */
308
309	#define HDA_REG_RIRBSTS 27 /* 0x5D */
310	#define HDA_RMX_RIRBSTS 25
311	#define HDA_RIRBSTS_RIRBOIS RT_BIT(2) /* Response Overrun Interrupt Status */
312	#define HDA_RIRBSTS_RINTFL RT_BIT(0) /* Response Interrupt Flag */
313
314	#define HDA_REG_RIRBSIZE 28 /* 0x5E */
315	#define HDA_RMX_RIRBSIZE 26
316
317	#define HDA_REG_IC 29 /* 0x60 */
318	#define HDA_RMX_IC 27
319
320	#define HDA_REG_IR 30 /* 0x64 */
321	#define HDA_RMX_IR 28
322
323	#define HDA_REG_IRS 31 /* 0x68 */
324	#define HDA_RMX_IRS 29
325	#define HDA_IRS_IRV RT_BIT(1) /* Immediate Result Valid */
326	#define HDA_IRS_ICB RT_BIT(0) /* Immediate Command Busy */
327
328	#define HDA_REG_DPLBASE 32 /* 0x70 */
329	#define HDA_RMX_DPLBASE 30
330
331	#define HDA_REG_DPUBASE 33 /* 0x74 */
332	#define HDA_RMX_DPUBASE 31
333
334	#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
335
336	#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
337	#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
338	/** @note sdnum here _MUST_ be stream reg number [0,7]. */
339	#ifdef VBOX_STRICT
340	# define HDA_STREAM_REG(pThis, name, sdnum) (*hdaStrictStreamRegAccessor((pThis), HDA_REG_SD0##name, HDA_RMX_SD0##name, (sdnum)))
341	#else
342	# define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_BY_IDX((pThis), HDA_RMX_SD0##name + (sdnum) * 10))
343	#endif
344
345	#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
346
347	/** @todo Condense marcos! */
348
349	#define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80; other streams offset by 0x20 */
350	#define HDA_RMX_SD0CTL 32
351	#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
352	#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
353	#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
354	#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
355	#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
356	#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
357	#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
358
359	#define HDA_SDCTL_NUM_MASK 0xF
360	#define HDA_SDCTL_NUM_SHIFT 20
361	#define HDA_SDCTL_DIR RT_BIT(19) /* Direction (Bidirectional streams only!) */
362	#define HDA_SDCTL_TP RT_BIT(18) /* Traffic Priority (PCI Express) */
363	#define HDA_SDCTL_STRIPE_MASK 0x3
364	#define HDA_SDCTL_STRIPE_SHIFT 16
365	#define HDA_SDCTL_DEIE RT_BIT(4) /* Descriptor Error Interrupt Enable */
366	#define HDA_SDCTL_FEIE RT_BIT(3) /* FIFO Error Interrupt Enable */
367	#define HDA_SDCTL_IOCE RT_BIT(2) /* Interrupt On Completion Enable */
368	#define HDA_SDCTL_RUN RT_BIT(1) /* Stream Run */
369	#define HDA_SDCTL_SRST RT_BIT(0) /* Stream Reset */
370
371	#define HDA_REG_SD0STS 35 /* 0x83; other streams offset by 0x20 */
372	#define HDA_RMX_SD0STS 33
373	#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
374	#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
375	#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
376	#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
377	#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
378	#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
379	#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
380
381	#define HDA_SDSTS_FIFORDY RT_BIT(5) /* FIFO Ready */
382	#define HDA_SDSTS_DESE RT_BIT(4) /* Descriptor Error */
383	#define HDA_SDSTS_FIFOE RT_BIT(3) /* FIFO Error */
384	#define HDA_SDSTS_BCIS RT_BIT(2) /* Buffer Completion Interrupt Status */
385
386	#define HDA_REG_SD0LPIB 36 /* 0x84; other streams offset by 0x20 */
387	#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
388	#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
389	#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
390	#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
391	#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
392	#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
393	#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
394	#define HDA_RMX_SD0LPIB 34
395	#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
396	#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
397	#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
398	#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
399	#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
400	#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
401	#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
402
403	#define HDA_REG_SD0CBL 37 /* 0x88; other streams offset by 0x20 */
404	#define HDA_RMX_SD0CBL 35
405	#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
406	#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
407	#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
408	#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
409	#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
410	#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
411	#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
412
413	#define HDA_REG_SD0LVI 38 /* 0x8C; other streams offset by 0x20 */
414	#define HDA_RMX_SD0LVI 36
415	#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
416	#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
417	#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
418	#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
419	#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
420	#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
421	#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
422
423	#define HDA_REG_SD0FIFOW 39 /* 0x8E; other streams offset by 0x20 */
424	#define HDA_RMX_SD0FIFOW 37
425	#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
426	#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
427	#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
428	#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
429	#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
430	#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
431	#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
432
433	/*
434	* ICH6 datasheet defined limits for FIFOW values (18.2.38).
435	*/
436	#define HDA_SDFIFOW_8B 0x2
437	#define HDA_SDFIFOW_16B 0x3
438	#define HDA_SDFIFOW_32B 0x4
439
440	#define HDA_REG_SD0FIFOS 40 /* 0x90; other streams offset by 0x20 */
441	#define HDA_RMX_SD0FIFOS 38
442	#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
443	#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
444	#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
445	#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
446	#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
447	#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
448	#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
449
450	#define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
451	#define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
452
453	#define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
454	#define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
455	#define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
456	#define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
457	#define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
458	#define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
459
460	#define HDA_REG_SD0FMT 41 /* 0x92; other streams offset by 0x20 */
461	#define HDA_RMX_SD0FMT 39
462	#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
463	#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
464	#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
465	#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
466	#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
467	#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
468	#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
469
470	#define HDA_REG_SD0BDPL 42 /* 0x98; other streams offset by 0x20 */
471	#define HDA_RMX_SD0BDPL 40
472	#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
473	#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
474	#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
475	#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
476	#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
477	#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
478	#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
479
480	#define HDA_REG_SD0BDPU 43 /* 0x9C; other streams offset by 0x20 */
481	#define HDA_RMX_SD0BDPU 41
482	#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
483	#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
484	#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
485	#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
486	#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
487	#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
488	#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
489
490	#define HDA_CODEC_CAD_SHIFT 28
491	/** Encodes the (required) LUN into a codec command. */
492	#define HDA_CODEC_CMD(cmd, lun) ((cmd) \| (lun << HDA_CODEC_CAD_SHIFT))
493
494	#define HDA_SDFMT_NON_PCM_SHIFT 15
495	#define HDA_SDFMT_NON_PCM_MASK 0x1
496	#define HDA_SDFMT_BASE_RATE_SHIFT 14
497	#define HDA_SDFMT_BASE_RATE_MASK 0x1
498	#define HDA_SDFMT_MULT_SHIFT 11
499	#define HDA_SDFMT_MULT_MASK 0x7
500	#define HDA_SDFMT_DIV_SHIFT 8
501	#define HDA_SDFMT_DIV_MASK 0x7
502	#define HDA_SDFMT_BITS_SHIFT 4
503	#define HDA_SDFMT_BITS_MASK 0x7
504	#define HDA_SDFMT_CHANNELS_MASK 0xF
505
506	#define HDA_SDFMT_TYPE RT_BIT(15)
507	#define HDA_SDFMT_TYPE_PCM (0)
508	#define HDA_SDFMT_TYPE_NON_PCM (1)
509
510	#define HDA_SDFMT_BASE RT_BIT(14)
511	#define HDA_SDFMT_BASE_48KHZ (0)
512	#define HDA_SDFMT_BASE_44KHZ (1)
513
514	#define HDA_SDFMT_MULT_1X (0)
515	#define HDA_SDFMT_MULT_2X (1)
516	#define HDA_SDFMT_MULT_3X (2)
517	#define HDA_SDFMT_MULT_4X (3)
518
519	#define HDA_SDFMT_DIV_1X (0)
520	#define HDA_SDFMT_DIV_2X (1)
521	#define HDA_SDFMT_DIV_3X (2)
522	#define HDA_SDFMT_DIV_4X (3)
523	#define HDA_SDFMT_DIV_5X (4)
524	#define HDA_SDFMT_DIV_6X (5)
525	#define HDA_SDFMT_DIV_7X (6)
526	#define HDA_SDFMT_DIV_8X (7)
527
528	#define HDA_SDFMT_8_BIT (0)
529	#define HDA_SDFMT_16_BIT (1)
530	#define HDA_SDFMT_20_BIT (2)
531	#define HDA_SDFMT_24_BIT (3)
532	#define HDA_SDFMT_32_BIT (4)
533
534	#define HDA_SDFMT_CHAN_MONO (0)
535	#define HDA_SDFMT_CHAN_STEREO (1)
536
537	/** Emits a SDnFMT register format.
538	* Also being used in the codec's converter format. */
539	#define HDA_SDFMT_MAKE(_afNonPCM, _aBaseRate, _aMult, _aDiv, _aBits, _aChan) \
540	( (((_afNonPCM) & HDA_SDFMT_NON_PCM_MASK) << HDA_SDFMT_NON_PCM_SHIFT) \
541	\| (((_aBaseRate) & HDA_SDFMT_BASE_RATE_MASK) << HDA_SDFMT_BASE_RATE_SHIFT) \
542	\| (((_aMult) & HDA_SDFMT_MULT_MASK) << HDA_SDFMT_MULT_SHIFT) \
543	\| (((_aDiv) & HDA_SDFMT_DIV_MASK) << HDA_SDFMT_DIV_SHIFT) \
544	\| (((_aBits) & HDA_SDFMT_BITS_MASK) << HDA_SDFMT_BITS_SHIFT) \
545	\| ( (_aChan) & HDA_SDFMT_CHANNELS_MASK))
546
547
548	/**
549	* Buffer descriptor list entry (BDLE).
550	*
551	* See 3.6.3 in HDA specs rev 1.0a (2010-06-17).
552	*/
553	typedef struct HDABDLEDESC
554	{
555	/** Starting address of the actual buffer. Must be 128-bit aligned. */
556	uint64_t u64BufAddr;
557	/** Size of the actual buffer (in bytes). */
558	uint32_t u32BufSize;
559	/** HDA_BDLE_F_XXX.
560	*
561	* Bit 0: IOC - Interrupt on completion / HDA_BDLE_F_IOC.
562	* The controller will generate an interrupt when the last byte of the buffer
563	* has been fetched by the DMA engine.
564	*
565	* Bits 31:1 are reserved for further use and must be 0. */
566	uint32_t fFlags;
567	} HDABDLEDESC, *PHDABDLEDESC;
568	AssertCompileSize(HDABDLEDESC, 16); /* Always 16 byte. Also must be aligned on 128-byte boundary. */
569
570	/** Interrupt on completion (IOC) flag. */
571	#define HDA_BDLE_F_IOC RT_BIT(0)
572
573
574	/**
575	* HDA mixer sink definition (ring-3).
576	*
577	* Its purpose is to know which audio mixer sink is bound to which SDn
578	* (SDI/SDO) device stream.
579	*
580	* This is needed in order to handle interleaved streams (that is, multiple
581	* channels in one stream) or non-interleaved streams (each channel has a
582	* dedicated stream).
583	*
584	* This is only known to the actual device emulation level.
585	*/
586	typedef struct HDAMIXERSINK
587	{
588	R3PTRTYPE(PHDASTREAM) pStreamShared;
589	R3PTRTYPE(PHDASTREAMR3) pStreamR3;
590	/** Pointer to the actual audio mixer sink. */
591	R3PTRTYPE(PAUDMIXSINK) pMixSink;
592	} HDAMIXERSINK;
593
594	/**
595	* Mapping a stream tag to an HDA stream (ring-3).
596	*/
597	typedef struct HDATAG
598	{
599	/** Own stream tag. */
600	uint8_t uTag;
601	uint8_t Padding[7];
602	/** Pointer to associated stream. */
603	R3PTRTYPE(PHDASTREAMR3) pStreamR3;
604	} HDATAG;
605	/** Pointer to a HDA stream tag mapping. */
606	typedef HDATAG *PHDATAG;
607
608	/**
609	* Shared ICH Intel HD audio controller state.
610	*/
611	typedef struct HDASTATE
612	{
613	/** Critical section protecting the HDA state. */
614	PDMCRITSECT CritSect;
615	/** Internal stream states (aligned on 64 byte boundrary). */
616	HDASTREAM aStreams[HDA_MAX_STREAMS];
617	/** The HDA's register set. */
618	uint32_t au32Regs[HDA_NUM_REGS];
619	/** CORB buffer base address. */
620	uint64_t u64CORBBase;
621	/** RIRB buffer base address. */
622	uint64_t u64RIRBBase;
623	/** DMA base address.
624	* Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
625	uint64_t u64DPBase;
626	/** Size in bytes of CORB buffer (#au32CorbBuf). */
627	uint32_t cbCorbBuf;
628	/** Size in bytes of RIRB buffer (#au64RirbBuf). */
629	uint32_t cbRirbBuf;
630	/** Response Interrupt Count (RINTCNT). */
631	uint16_t u16RespIntCnt;
632	/** DMA position buffer enable bit. */
633	bool fDMAPosition;
634	/** Current IRQ level. */
635	uint8_t u8IRQL;
636	/** Config: Internal input DMA buffer size override, specified in milliseconds.
637	* Zero means default size according to buffer and stream config.
638	* @sa BufSizeInMs config value. */
639	uint16_t cMsCircBufIn;
640	/** Config: Internal output DMA buffer size override, specified in milliseconds.
641	* Zero means default size according to buffer and stream config.
642	* @sa BufSizeOutMs config value. */
643	uint16_t cMsCircBufOut;
644	/** The start time of the wall clock (WALCLK), measured on the virtual sync clock. */
645	uint64_t tsWalClkStart;
646	/** CORB DMA task handle.
647	* We use this when there is stuff we cannot handle in ring-0. */
648	PDMTASKHANDLE hCorbDmaTask;
649	/** The CORB buffer. */
650	uint32_t au32CorbBuf[HDA_CORB_SIZE];
651	/** Pointer to RIRB buffer. */
652	uint64_t au64RirbBuf[HDA_RIRB_SIZE];
653
654	/** PCI Region \#0: 16KB of MMIO stuff. */
655	IOMMMIOHANDLE hMmio;
656
657	/** Shared R0/R3 HDA codec to use. */
658	HDACODEC Codec;
659
660	#ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
661	STAMCOUNTER StatAccessDmaOutput;
662	STAMCOUNTER StatAccessDmaOutputToR3;
663	#endif
664	#ifdef VBOX_WITH_STATISTICS
665	STAMPROFILE StatIn;
666	STAMPROFILE StatOut;
667	STAMCOUNTER StatBytesRead;
668	STAMCOUNTER StatBytesWritten;
669
670	/** @name Register statistics.
671	* The array members run parallel to g_aHdaRegMap.
672	* @{ */
673	STAMCOUNTER aStatRegReads[HDA_NUM_REGS];
674	STAMCOUNTER aStatRegReadsToR3[HDA_NUM_REGS];
675	STAMCOUNTER aStatRegWrites[HDA_NUM_REGS];
676	STAMCOUNTER aStatRegWritesToR3[HDA_NUM_REGS];
677	STAMCOUNTER StatRegMultiReadsRZ;
678	STAMCOUNTER StatRegMultiReadsR3;
679	STAMCOUNTER StatRegMultiWritesRZ;
680	STAMCOUNTER StatRegMultiWritesR3;
681	STAMCOUNTER StatRegSubWriteRZ;
682	STAMCOUNTER StatRegSubWriteR3;
683	STAMCOUNTER StatRegUnknownReads;
684	STAMCOUNTER StatRegUnknownWrites;
685	STAMCOUNTER StatRegWritesBlockedByReset;
686	STAMCOUNTER StatRegWritesBlockedByRun;
687	/** @} */
688	#endif
689
690	#ifdef DEBUG
691	/** Debug stuff.
692	* @todo Make STAM values out some of this? */
693	struct
694	{
695	# if 0 /* unused */
696	/** Timestamp (in ns) of the last timer callback (hdaTimer).
697	* Used to calculate the time actually elapsed between two timer callbacks. */
698	uint64_t tsTimerLastCalledNs;
699	# endif
700	/** IRQ debugging information. */
701	struct
702	{
703	/** Timestamp (in ns) of last processed (asserted / deasserted) IRQ. */
704	uint64_t tsProcessedLastNs;
705	/** Timestamp (in ns) of last asserted IRQ. */
706	uint64_t tsAssertedNs;
707	# if 0 /* unused */
708	/** How many IRQs have been asserted already. */
709	uint64_t cAsserted;
710	/** Accumulated elapsed time (in ns) of all IRQ being asserted. */
711	uint64_t tsAssertedTotalNs;
712	/** Timestamp (in ns) of last deasserted IRQ. */
713	uint64_t tsDeassertedNs;
714	/** How many IRQs have been deasserted already. */
715	uint64_t cDeasserted;
716	/** Accumulated elapsed time (in ns) of all IRQ being deasserted. */
717	uint64_t tsDeassertedTotalNs;
718	# endif
719	} IRQ;
720	} Dbg;
721	#endif
722	/** This is for checking that the build was correctly configured in all contexts.
723	* This is set to HDASTATE_ALIGNMENT_CHECK_MAGIC. */
724	uint64_t uAlignmentCheckMagic;
725	} HDASTATE;
726	AssertCompileMemberAlignment(HDASTATE, aStreams, 64);
727	/** Pointer to a shared HDA device state. */
728	typedef HDASTATE *PHDASTATE;
729
730	/** Value for HDASTATE:uAlignmentCheckMagic. */
731	#define HDASTATE_ALIGNMENT_CHECK_MAGIC UINT64_C(0x1298afb75893e059)
732
733	/**
734	* Ring-0 ICH Intel HD audio controller state.
735	*/
736	typedef struct HDASTATER0
737	{
738	# if 0 /* Codec is not yet kosher enough for ring-0. @bugref{9890c64} */
739	/** Pointer to HDA codec to use. */
740	HDACODECR0 Codec;
741	# else
742	uint32_t u32Dummy;
743	# endif
744	} HDASTATER0;
745	/** Pointer to a ring-0 HDA device state. */
746	typedef HDASTATER0 *PHDASTATER0;
747
748	/**
749	* Ring-3 ICH Intel HD audio controller state.
750	*/
751	typedef struct HDASTATER3
752	{
753	/** Internal stream states. */
754	HDASTREAMR3 aStreams[HDA_MAX_STREAMS];
755	/** Mapping table between stream tags and stream states. */
756	HDATAG aTags[HDA_MAX_TAGS];
757	/** R3 Pointer to the device instance. */
758	PPDMDEVINSR3 pDevIns;
759	/** The base interface for LUN\#0. */
760	PDMIBASE IBase;
761	/** Pointer to HDA codec to use. */
762	R3PTRTYPE(PHDACODECR3) pCodec;
763	/** List of associated LUN drivers (HDADRIVER). */
764	RTLISTANCHORR3 lstDrv;
765	/** The device' software mixer. */
766	R3PTRTYPE(PAUDIOMIXER) pMixer;
767	/** HDA sink for (front) output. */
768	HDAMIXERSINK SinkFront;
769	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
770	/** HDA sink for center / LFE output. */
771	HDAMIXERSINK SinkCenterLFE;
772	/** HDA sink for rear output. */
773	HDAMIXERSINK SinkRear;
774	#endif
775	/** HDA mixer sink for line input. */
776	HDAMIXERSINK SinkLineIn;
777	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
778	/** Audio mixer sink for microphone input. */
779	HDAMIXERSINK SinkMicIn;
780	#endif
781	/** Debug stuff. */
782	struct
783	{
784	/** Whether debugging is enabled or not. */
785	bool fEnabled;
786	/** Path where to dump the debug output to.
787	* Can be NULL, in which the system's temporary directory will be used then. */
788	R3PTRTYPE(char *) pszOutPath;
789	} Dbg;
790	} HDASTATER3;
791
792
793	/** Pointer to the context specific HDA state (HDASTATER3 or HDASTATER0). */
794	typedef CTX_SUFF(PHDASTATE) PHDASTATECC;
795
796
797	/** @def HDA_PROCESS_INTERRUPT
798	* Wrapper around hdaProcessInterrupt that supplies the source function name
799	* string in logging builds. */
800	#if defined(LOG_ENABLED) \|\| defined(DOXYGEN_RUNNING)
801	void hdaProcessInterrupt(PPDMDEVINS pDevIns, PHDASTATE pThis, const char *pszSource);
802	# define HDA_PROCESS_INTERRUPT(a_pDevIns, a_pThis) hdaProcessInterrupt((a_pDevIns), (a_pThis), __FUNCTION__)
803	#else
804	void hdaProcessInterrupt(PPDMDEVINS pDevIns, PHDASTATE pThis);
805	# define HDA_PROCESS_INTERRUPT(a_pDevIns, a_pThis) hdaProcessInterrupt((a_pDevIns), (a_pThis))
806	#endif
807
808	/**
809	* Returns the audio direction of a specified stream descriptor.
810	*
811	* The register layout specifies that input streams (SDI) come first,
812	* followed by the output streams (SDO). So every stream ID below HDA_MAX_SDI
813	* is an input stream, whereas everything >= HDA_MAX_SDI is an output stream.
814	*
815	* @note SDnFMT register does not provide that information, so we have to judge
816	* for ourselves.
817	*
818	* @return Audio direction.
819	* @param uSD The stream number.
820	*/
821	DECLINLINE(PDMAUDIODIR) hdaGetDirFromSD(uint8_t uSD)
822	{
823	if (uSD < HDA_MAX_SDI)
824	return PDMAUDIODIR_IN;
825	AssertReturn(uSD < HDA_MAX_STREAMS, PDMAUDIODIR_UNKNOWN);
826	return PDMAUDIODIR_OUT;
827	}
828
829	#ifdef VBOX_STRICT
830	DECLINLINE(uint32_t *) hdaStrictStreamRegAccessor(PHDASTATE pThis, uint32_t idxMap0, uint32_t idxReg0, size_t idxStream)
831	{
832	AssertMsg(idxStream < RT_ELEMENTS(pThis->aStreams), ("%#zx\n", idxStream));
833	AssertMsg(idxReg0 + idxStream * 10 == g_aHdaRegMap[idxMap0 + idxStream * 10].mem_idx,
834	("idxReg0=%d idxStream=%zx\n", idxReg0, idxStream));
835	return &pThis->au32Regs[idxReg0 + idxStream * 10];
836	}
837	#endif
838
839	/* Used by hdaR3StreamSetUp: */
840	uint8_t hdaSDFIFOWToBytes(uint16_t u16RegFIFOW);
841
842
843
844	/** @name Saved state versions for the HDA device
845	* @{ */
846	/** The current staved state version.
847	* @note Only for the registration call. Never used for tests. */
848	#define HDA_SAVED_STATE_VERSION HDA_SAVED_STATE_WITHOUT_PERIOD
849
850	/** Removed period and redefined wall clock. */
851	#define HDA_SAVED_STATE_WITHOUT_PERIOD 8
852	/** Added (Controller): Current wall clock value (this independent from WALCLK register value).
853	* Added (Controller): Current IRQ level.
854	* Added (Per stream): Ring buffer. This is optional and can be skipped if (not) needed.
855	* Added (Per stream): Struct g_aSSMStreamStateFields7.
856	* Added (Per stream): Struct g_aSSMStreamPeriodFields7.
857	* Added (Current BDLE per stream): Struct g_aSSMBDLEDescFields7.
858	* Added (Current BDLE per stream): Struct g_aSSMBDLEStateFields7. */
859	#define HDA_SAVED_STATE_VERSION_7 7
860	/** Saves the current BDLE state.
861	* @since 5.0.14 (r104839) */
862	#define HDA_SAVED_STATE_VERSION_6 6
863	/** Introduced dynamic number of streams + stream identifiers for serialization.
864	* Bug: Did not save the BDLE states correctly.
865	* Those will be skipped on load then.
866	* @since 5.0.12 (r104520) */
867	#define HDA_SAVED_STATE_VERSION_5 5
868	/** Since this version the number of MMIO registers can be flexible. */
869	#define HDA_SAVED_STATE_VERSION_4 4
870	#define HDA_SAVED_STATE_VERSION_3 3
871	#define HDA_SAVED_STATE_VERSION_2 2
872	#define HDA_SAVED_STATE_VERSION_1 1
873	/** @} */
874
875	#endif /* !VBOX_INCLUDED_SRC_Audio_DevHda_h */
876

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