DevHda.h@ 89899

Last change on this file since 89899 was 89899, checked in by vboxsync, 4 years ago
DevHda: Added another assertion wrapper for register access for strict builds. bugref:9890
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1	/* $Id: DevHda.h 89899 2021-06-24 18:57:00Z vboxsync $ */
2	/** @file
3	* Intel HD Audio Controller Emulation - Structures.
4	*/
5
6	/*
7	* Copyright (C) 2016-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VBOX_INCLUDED_SRC_Audio_DevHda_h
19	#define VBOX_INCLUDED_SRC_Audio_DevHda_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <iprt/path.h>
25	#include <VBox/vmm/pdmdev.h>
26	#include "AudioMixer.h"
27
28	/*
29	* Compile time feature configuration.
30	*/
31
32	/** @def VBOX_HDA_WITH_ON_REG_ACCESS_DMA
33	* Enables doing DMA work on certain register accesses (LPIB, WALCLK) in
34	* addition to the DMA timer. All but the last frame can be done during
35	* register accesses (as we don't wish to leave the DMA timer w/o work to
36	* do in case that upsets it). */
37	#if defined(DOXYGEN_RUNNING) \|\| 0
38	# define VBOX_HDA_WITH_ON_REG_ACCESS_DMA
39	#endif
40
41	#ifdef DEBUG_andy
42	/** Enables strict mode, which checks for stuff which isn't supposed to happen.
43	* Be prepared for assertions coming in! */
44	//# define HDA_STRICT
45	#endif
46
47	/** @def HDA_AS_PCI_EXPRESS
48	* Enables PCI express hardware. */
49	#if defined(DOXYGEN_RUNNING) \|\| 0
50	# define HDA_AS_PCI_EXPRESS
51	#endif
52
53	/** @def HDA_DEBUG_SILENCE
54	* To debug silence coming from the guest in form of audio gaps.
55	* Very crude implementation for now.
56	* @todo probably borked atm */
57	#if defined(DOXYGEN_RUNNING) \|\| 0
58	# define HDA_DEBUG_SILENCE
59	#endif
60
61
62	/*
63	* Common pointer types.
64	*/
65	/** Pointer to an HDA stream (SDI / SDO). */
66	typedef struct HDASTREAMR3 *PHDASTREAMR3;
67	/** Pointer to a shared HDA device state. */
68	typedef struct HDASTATE *PHDASTATE;
69	/** Pointer to a ring-3 HDA device state. */
70	typedef struct HDASTATER3 *PHDASTATER3;
71	/** Pointer to an HDA mixer sink definition (ring-3). */
72	typedef struct HDAMIXERSINK *PHDAMIXERSINK;
73
74
75	/*
76	* The rest of the headers.
77	*/
78	#include "DevHdaStream.h"
79	#include "DevHdaCodec.h"
80
81
82
83	/** @name Stream counts.
84	*
85	* At the moment we support 4 input + 4 output streams max, which is 8 in total.
86	* Bidirectional streams are currently not supported.
87	*
88	* @note When changing any of those values, be prepared for some saved state
89	* fixups / trouble!
90	* @{
91	*/
92	#define HDA_MAX_SDI 4
93	#define HDA_MAX_SDO 4
94	#define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
95	/** @} */
96	AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
97
98
99	/** Number of general registers. */
100	#define HDA_NUM_GENERAL_REGS 34
101	/** Number of total registers in the HDA's register map. */
102	#define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */))
103	/** Total number of stream tags (channels). Index 0 is reserved / invalid. */
104	#define HDA_MAX_TAGS 16
105
106
107	/** Read callback. */
108	typedef VBOXSTRICTRC FNHDAREGREAD(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
109	/** Write callback. */
110	typedef VBOXSTRICTRC FNHDAREGWRITE(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
111
112	/**
113	* HDA register descriptor.
114	*/
115	typedef struct HDAREGDESC
116	{
117	/** Register offset in the register space. */
118	uint32_t offset;
119	/** Size in bytes. Registers of size > 4 are in fact tables. */
120	uint32_t size;
121	/** Readable bits. */
122	uint32_t readable;
123	/** Writable bits. */
124	uint32_t writable;
125	/** Register descriptor (RD) flags of type HDA_RD_F_XXX. These are used to
126	* specify the read/write handling policy of the register. */
127	uint32_t fFlags;
128	/** Read callback. */
129	FNHDAREGREAD *pfnRead;
130	/** Write callback. */
131	FNHDAREGWRITE *pfnWrite;
132	/** Index into the register storage array.
133	* @todo r=bird: Bad structure layout. Move up before pfnRead. */
134	uint32_t mem_idx;
135	/** Abbreviated name. */
136	const char *abbrev;
137	/** Descripton. */
138	const char *desc;
139	} HDAREGDESC;
140
141	#ifdef VBOX_STRICT
142	extern const HDAREGDESC g_aHdaRegMap[HDA_NUM_REGS];
143	#endif
144
145
146	/**
147	* ICH6 datasheet defines limits for FIFOS registers (18.2.39).
148	* Formula: size - 1
149	* Other values not listed are not supported.
150	*/
151
152	/** Offset of the SD0 register map. */
153	#define HDA_REG_DESC_SD0_BASE 0x80
154
155	/*
156	* NB: Register values stored in memory (au32Regs[]) are indexed through
157	* the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
158	* register descriptors in g_aHdaRegMap[] are indexed through the
159	* HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
160	*
161	* The au32Regs[] layout is kept unchanged for saved state compatibility.
162	*/
163
164	/* Registers */
165	#define HDA_REG_IND_NAME(x) HDA_REG_##x
166	#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
167
168	/** Direct register access by HDASTATE::au32Reg index. */
169	#define HDA_REG_BY_IDX(a_pThis, a_idxReg) ((a_pThis)->au32Regs[(a_idxReg)])
170
171	/** Accesses register @a ShortRegNm. */
172	#ifdef VBOX_STRICT
173	# define HDA_REG(a_pThis, a_ShortRegNm) (*hdaStrictRegAccessor(a_pThis, HDA_REG_IND_NAME(a_ShortRegNm), HDA_MEM_IND_NAME(a_ShortRegNm)))
174	#else
175	# define HDA_REG(a_pThis, a_ShortRegNm) HDA_REG_BY_IDX(a_pThis, HDA_MEM_IND_NAME(a_ShortRegNm))
176	#endif
177
178	/** Indirect register access via g_aHdaRegMap[].mem_idx. */
179	#define HDA_REG_IND(a_pThis, a_idxMap) HDA_REG_BY_IDX(a_pThis, g_aHdaRegMap[(a_idxMap)].mem_idx)
180
181
182	#define HDA_REG_GCAP 0 /* Range 0x00 - 0x01 */
183	#define HDA_RMX_GCAP 0
184	/**
185	* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
186	*
187	* oss (15:12) - Number of output streams supported.
188	* iss (11:8) - Number of input streams supported.
189	* bss (7:3) - Number of bidirectional streams supported.
190	* bds (2:1) - Number of serial data out (SDO) signals supported.
191	* b64sup (0) - 64 bit addressing supported.
192	*/
193	#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
194	( (((oss) & 0xF) << 12) \
195	\| (((iss) & 0xF) << 8) \
196	\| (((bss) & 0x1F) << 3) \
197	\| (((bds) & 0x3) << 2) \
198	\| ((b64sup) & 1))
199
200	#define HDA_REG_VMIN 1 /* 0x02 */
201	#define HDA_RMX_VMIN 1
202
203	#define HDA_REG_VMAJ 2 /* 0x03 */
204	#define HDA_RMX_VMAJ 2
205
206	#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
207	#define HDA_RMX_OUTPAY 3
208
209	#define HDA_REG_INPAY 4 /* 0x06-0x07 */
210	#define HDA_RMX_INPAY 4
211
212	#define HDA_REG_GCTL 5 /* 0x08-0x0B */
213	#define HDA_RMX_GCTL 5
214	#define HDA_GCTL_UNSOL RT_BIT(8) /* Accept Unsolicited Response Enable */
215	#define HDA_GCTL_FCNTRL RT_BIT(1) /* Flush Control */
216	#define HDA_GCTL_CRST RT_BIT(0) /* Controller Reset */
217
218	#define HDA_REG_WAKEEN 6 /* 0x0C */
219	#define HDA_RMX_WAKEEN 6
220
221	#define HDA_REG_STATESTS 7 /* 0x0E */
222	#define HDA_RMX_STATESTS 7
223	#define HDA_STATESTS_SCSF_MASK 0x7 /* State Change Status Flags (6.2.8). */
224
225	#define HDA_REG_GSTS 8 /* 0x10-0x11*/
226	#define HDA_RMX_GSTS 8
227	#define HDA_GSTS_FSTS RT_BIT(1) /* Flush Status */
228
229	#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
230	#define HDA_RMX_OUTSTRMPAY 112
231
232	#define HDA_REG_INSTRMPAY 10 /* 0x1a */
233	#define HDA_RMX_INSTRMPAY 113
234
235	#define HDA_REG_INTCTL 11 /* 0x20 */
236	#define HDA_RMX_INTCTL 9
237	#define HDA_INTCTL_GIE RT_BIT(31) /* Global Interrupt Enable */
238	#define HDA_INTCTL_CIE RT_BIT(30) /* Controller Interrupt Enable */
239	/** Bits 0-29 correspond to streams 0-29. */
240	#define HDA_STRMINT_MASK 0xFF /* Streams 0-7 implemented. Applies to INTCTL and INTSTS. */
241
242	#define HDA_REG_INTSTS 12 /* 0x24 */
243	#define HDA_RMX_INTSTS 10
244	#define HDA_INTSTS_GIS RT_BIT(31) /* Global Interrupt Status */
245	#define HDA_INTSTS_CIS RT_BIT(30) /* Controller Interrupt Status */
246
247	#define HDA_REG_WALCLK 13 /* 0x30 */
248	/*NB: HDA_RMX_WALCLK is not defined because the register is not stored in memory. /
249
250	/**
251	* Note: The HDA specification defines a SSYNC register at offset 0x38. The
252	* ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
253	* the datasheet.
254	*/
255	#define HDA_REG_SSYNC 14 /* 0x34 */
256	#define HDA_RMX_SSYNC 12
257
258	#define HDA_REG_CORBLBASE 15 /* 0x40 */
259	#define HDA_RMX_CORBLBASE 13
260
261	#define HDA_REG_CORBUBASE 16 /* 0x44 */
262	#define HDA_RMX_CORBUBASE 14
263
264	#define HDA_REG_CORBWP 17 /* 0x48 */
265	#define HDA_RMX_CORBWP 15
266
267	#define HDA_REG_CORBRP 18 /* 0x4A */
268	#define HDA_RMX_CORBRP 16
269	#define HDA_CORBRP_RST RT_BIT(15) /* CORB Read Pointer Reset */
270
271	#define HDA_REG_CORBCTL 19 /* 0x4C */
272	#define HDA_RMX_CORBCTL 17
273	#define HDA_CORBCTL_DMA RT_BIT(1) /* Enable CORB DMA Engine */
274	#define HDA_CORBCTL_CMEIE RT_BIT(0) /* CORB Memory Error Interrupt Enable */
275
276	#define HDA_REG_CORBSTS 20 /* 0x4D */
277	#define HDA_RMX_CORBSTS 18
278
279	#define HDA_REG_CORBSIZE 21 /* 0x4E */
280	#define HDA_RMX_CORBSIZE 19
281	#define HDA_CORBSIZE_SZ_CAP 0xF0
282	#define HDA_CORBSIZE_SZ 0x3
283
284	/** Number of CORB buffer entries. */
285	#define HDA_CORB_SIZE 256
286	/** CORB element size (in bytes). */
287	#define HDA_CORB_ELEMENT_SIZE 4
288	/** Number of RIRB buffer entries. */
289	#define HDA_RIRB_SIZE 256
290	/** RIRB element size (in bytes). */
291	#define HDA_RIRB_ELEMENT_SIZE 8
292
293	#define HDA_REG_RIRBLBASE 22 /* 0x50 */
294	#define HDA_RMX_RIRBLBASE 20
295
296	#define HDA_REG_RIRBUBASE 23 /* 0x54 */
297	#define HDA_RMX_RIRBUBASE 21
298
299	#define HDA_REG_RIRBWP 24 /* 0x58 */
300	#define HDA_RMX_RIRBWP 22
301	#define HDA_RIRBWP_RST RT_BIT(15) /* RIRB Write Pointer Reset */
302
303	#define HDA_REG_RINTCNT 25 /* 0x5A */
304	#define HDA_RMX_RINTCNT 23
305
306	/** Maximum number of Response Interrupts. */
307	#define HDA_MAX_RINTCNT 256
308
309	#define HDA_REG_RIRBCTL 26 /* 0x5C */
310	#define HDA_RMX_RIRBCTL 24
311	#define HDA_RIRBCTL_ROIC RT_BIT(2) /* Response Overrun Interrupt Control */
312	#define HDA_RIRBCTL_RDMAEN RT_BIT(1) /* RIRB DMA Enable */
313	#define HDA_RIRBCTL_RINTCTL RT_BIT(0) /* Response Interrupt Control */
314
315	#define HDA_REG_RIRBSTS 27 /* 0x5D */
316	#define HDA_RMX_RIRBSTS 25
317	#define HDA_RIRBSTS_RIRBOIS RT_BIT(2) /* Response Overrun Interrupt Status */
318	#define HDA_RIRBSTS_RINTFL RT_BIT(0) /* Response Interrupt Flag */
319
320	#define HDA_REG_RIRBSIZE 28 /* 0x5E */
321	#define HDA_RMX_RIRBSIZE 26
322
323	#define HDA_REG_IC 29 /* 0x60 */
324	#define HDA_RMX_IC 27
325
326	#define HDA_REG_IR 30 /* 0x64 */
327	#define HDA_RMX_IR 28
328
329	#define HDA_REG_IRS 31 /* 0x68 */
330	#define HDA_RMX_IRS 29
331	#define HDA_IRS_IRV RT_BIT(1) /* Immediate Result Valid */
332	#define HDA_IRS_ICB RT_BIT(0) /* Immediate Command Busy */
333
334	#define HDA_REG_DPLBASE 32 /* 0x70 */
335	#define HDA_RMX_DPLBASE 30
336
337	#define HDA_REG_DPUBASE 33 /* 0x74 */
338	#define HDA_RMX_DPUBASE 31
339
340	#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
341
342	#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
343	#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
344	/** @note sdnum here _MUST_ be stream reg number [0,7]. */
345	#ifdef VBOX_STRICT
346	# define HDA_STREAM_REG(pThis, name, sdnum) (*hdaStrictStreamRegAccessor((pThis), HDA_REG_SD0##name, HDA_RMX_SD0##name, (sdnum)))
347	#else
348	# define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_BY_IDX((pThis), HDA_RMX_SD0##name + (sdnum) * 10))
349	#endif
350
351	#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
352
353	/** @todo Condense marcos! */
354
355	#define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80; other streams offset by 0x20 */
356	#define HDA_RMX_SD0CTL 32
357	#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
358	#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
359	#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
360	#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
361	#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
362	#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
363	#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
364
365	#define HDA_SDCTL_NUM_MASK 0xF
366	#define HDA_SDCTL_NUM_SHIFT 20
367	#define HDA_SDCTL_DIR RT_BIT(19) /* Direction (Bidirectional streams only!) */
368	#define HDA_SDCTL_TP RT_BIT(18) /* Traffic Priority (PCI Express) */
369	#define HDA_SDCTL_STRIPE_MASK 0x3
370	#define HDA_SDCTL_STRIPE_SHIFT 16
371	#define HDA_SDCTL_DEIE RT_BIT(4) /* Descriptor Error Interrupt Enable */
372	#define HDA_SDCTL_FEIE RT_BIT(3) /* FIFO Error Interrupt Enable */
373	#define HDA_SDCTL_IOCE RT_BIT(2) /* Interrupt On Completion Enable */
374	#define HDA_SDCTL_RUN RT_BIT(1) /* Stream Run */
375	#define HDA_SDCTL_SRST RT_BIT(0) /* Stream Reset */
376
377	#define HDA_REG_SD0STS 35 /* 0x83; other streams offset by 0x20 */
378	#define HDA_RMX_SD0STS 33
379	#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
380	#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
381	#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
382	#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
383	#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
384	#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
385	#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
386
387	#define HDA_SDSTS_FIFORDY RT_BIT(5) /* FIFO Ready */
388	#define HDA_SDSTS_DESE RT_BIT(4) /* Descriptor Error */
389	#define HDA_SDSTS_FIFOE RT_BIT(3) /* FIFO Error */
390	#define HDA_SDSTS_BCIS RT_BIT(2) /* Buffer Completion Interrupt Status */
391
392	#define HDA_REG_SD0LPIB 36 /* 0x84; other streams offset by 0x20 */
393	#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
394	#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
395	#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
396	#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
397	#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
398	#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
399	#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
400	#define HDA_RMX_SD0LPIB 34
401	#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
402	#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
403	#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
404	#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
405	#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
406	#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
407	#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
408
409	#define HDA_REG_SD0CBL 37 /* 0x88; other streams offset by 0x20 */
410	#define HDA_RMX_SD0CBL 35
411	#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
412	#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
413	#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
414	#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
415	#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
416	#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
417	#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
418
419	#define HDA_REG_SD0LVI 38 /* 0x8C; other streams offset by 0x20 */
420	#define HDA_RMX_SD0LVI 36
421	#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
422	#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
423	#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
424	#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
425	#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
426	#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
427	#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
428
429	#define HDA_REG_SD0FIFOW 39 /* 0x8E; other streams offset by 0x20 */
430	#define HDA_RMX_SD0FIFOW 37
431	#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
432	#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
433	#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
434	#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
435	#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
436	#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
437	#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
438
439	/*
440	* ICH6 datasheet defined limits for FIFOW values (18.2.38).
441	*/
442	#define HDA_SDFIFOW_8B 0x2
443	#define HDA_SDFIFOW_16B 0x3
444	#define HDA_SDFIFOW_32B 0x4
445
446	#define HDA_REG_SD0FIFOS 40 /* 0x90; other streams offset by 0x20 */
447	#define HDA_RMX_SD0FIFOS 38
448	#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
449	#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
450	#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
451	#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
452	#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
453	#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
454	#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
455
456	#define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
457	#define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
458
459	#define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
460	#define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
461	#define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
462	#define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
463	#define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
464	#define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
465
466	#define HDA_REG_SD0FMT 41 /* 0x92; other streams offset by 0x20 */
467	#define HDA_RMX_SD0FMT 39
468	#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
469	#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
470	#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
471	#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
472	#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
473	#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
474	#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
475
476	#define HDA_REG_SD0BDPL 42 /* 0x98; other streams offset by 0x20 */
477	#define HDA_RMX_SD0BDPL 40
478	#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
479	#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
480	#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
481	#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
482	#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
483	#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
484	#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
485
486	#define HDA_REG_SD0BDPU 43 /* 0x9C; other streams offset by 0x20 */
487	#define HDA_RMX_SD0BDPU 41
488	#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
489	#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
490	#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
491	#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
492	#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
493	#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
494	#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
495
496	#define HDA_CODEC_CAD_SHIFT 28
497	/** Encodes the (required) LUN into a codec command. */
498	#define HDA_CODEC_CMD(cmd, lun) ((cmd) \| (lun << HDA_CODEC_CAD_SHIFT))
499
500	#define HDA_SDFMT_NON_PCM_SHIFT 15
501	#define HDA_SDFMT_NON_PCM_MASK 0x1
502	#define HDA_SDFMT_BASE_RATE_SHIFT 14
503	#define HDA_SDFMT_BASE_RATE_MASK 0x1
504	#define HDA_SDFMT_MULT_SHIFT 11
505	#define HDA_SDFMT_MULT_MASK 0x7
506	#define HDA_SDFMT_DIV_SHIFT 8
507	#define HDA_SDFMT_DIV_MASK 0x7
508	#define HDA_SDFMT_BITS_SHIFT 4
509	#define HDA_SDFMT_BITS_MASK 0x7
510	#define HDA_SDFMT_CHANNELS_MASK 0xF
511
512	#define HDA_SDFMT_TYPE RT_BIT(15)
513	#define HDA_SDFMT_TYPE_PCM (0)
514	#define HDA_SDFMT_TYPE_NON_PCM (1)
515
516	#define HDA_SDFMT_BASE RT_BIT(14)
517	#define HDA_SDFMT_BASE_48KHZ (0)
518	#define HDA_SDFMT_BASE_44KHZ (1)
519
520	#define HDA_SDFMT_MULT_1X (0)
521	#define HDA_SDFMT_MULT_2X (1)
522	#define HDA_SDFMT_MULT_3X (2)
523	#define HDA_SDFMT_MULT_4X (3)
524
525	#define HDA_SDFMT_DIV_1X (0)
526	#define HDA_SDFMT_DIV_2X (1)
527	#define HDA_SDFMT_DIV_3X (2)
528	#define HDA_SDFMT_DIV_4X (3)
529	#define HDA_SDFMT_DIV_5X (4)
530	#define HDA_SDFMT_DIV_6X (5)
531	#define HDA_SDFMT_DIV_7X (6)
532	#define HDA_SDFMT_DIV_8X (7)
533
534	#define HDA_SDFMT_8_BIT (0)
535	#define HDA_SDFMT_16_BIT (1)
536	#define HDA_SDFMT_20_BIT (2)
537	#define HDA_SDFMT_24_BIT (3)
538	#define HDA_SDFMT_32_BIT (4)
539
540	#define HDA_SDFMT_CHAN_MONO (0)
541	#define HDA_SDFMT_CHAN_STEREO (1)
542
543	/** Emits a SDnFMT register format.
544	* Also being used in the codec's converter format. */
545	#define HDA_SDFMT_MAKE(_afNonPCM, _aBaseRate, _aMult, _aDiv, _aBits, _aChan) \
546	( (((_afNonPCM) & HDA_SDFMT_NON_PCM_MASK) << HDA_SDFMT_NON_PCM_SHIFT) \
547	\| (((_aBaseRate) & HDA_SDFMT_BASE_RATE_MASK) << HDA_SDFMT_BASE_RATE_SHIFT) \
548	\| (((_aMult) & HDA_SDFMT_MULT_MASK) << HDA_SDFMT_MULT_SHIFT) \
549	\| (((_aDiv) & HDA_SDFMT_DIV_MASK) << HDA_SDFMT_DIV_SHIFT) \
550	\| (((_aBits) & HDA_SDFMT_BITS_MASK) << HDA_SDFMT_BITS_SHIFT) \
551	\| ( (_aChan) & HDA_SDFMT_CHANNELS_MASK))
552
553
554	/**
555	* Buffer descriptor list entry (BDLE).
556	*
557	* See 3.6.3 in HDA specs rev 1.0a (2010-06-17).
558	*/
559	typedef struct HDABDLEDESC
560	{
561	/** Starting address of the actual buffer. Must be 128-bit aligned. */
562	uint64_t u64BufAddr;
563	/** Size of the actual buffer (in bytes). */
564	uint32_t u32BufSize;
565	/** HDA_BDLE_F_XXX.
566	*
567	* Bit 0: IOC - Interrupt on completion / HDA_BDLE_F_IOC.
568	* The controller will generate an interrupt when the last byte of the buffer
569	* has been fetched by the DMA engine.
570	*
571	* Bits 31:1 are reserved for further use and must be 0. */
572	uint32_t fFlags;
573	} HDABDLEDESC, *PHDABDLEDESC;
574	AssertCompileSize(HDABDLEDESC, 16); /* Always 16 byte. Also must be aligned on 128-byte boundary. */
575
576	/** Interrupt on completion (IOC) flag. */
577	#define HDA_BDLE_F_IOC RT_BIT(0)
578
579
580	/**
581	* HDA mixer sink definition (ring-3).
582	*
583	* Its purpose is to know which audio mixer sink is bound to which SDn
584	* (SDI/SDO) device stream.
585	*
586	* This is needed in order to handle interleaved streams (that is, multiple
587	* channels in one stream) or non-interleaved streams (each channel has a
588	* dedicated stream).
589	*
590	* This is only known to the actual device emulation level.
591	*/
592	typedef struct HDAMIXERSINK
593	{
594	R3PTRTYPE(PHDASTREAM) pStreamShared;
595	R3PTRTYPE(PHDASTREAMR3) pStreamR3;
596	/** Pointer to the actual audio mixer sink. */
597	R3PTRTYPE(PAUDMIXSINK) pMixSink;
598	} HDAMIXERSINK;
599
600	/**
601	* Mapping a stream tag to an HDA stream (ring-3).
602	*/
603	typedef struct HDATAG
604	{
605	/** Own stream tag. */
606	uint8_t uTag;
607	uint8_t Padding[7];
608	/** Pointer to associated stream. */
609	R3PTRTYPE(PHDASTREAMR3) pStreamR3;
610	} HDATAG;
611	/** Pointer to a HDA stream tag mapping. */
612	typedef HDATAG *PHDATAG;
613
614	/**
615	* Shared ICH Intel HD audio controller state.
616	*/
617	typedef struct HDASTATE
618	{
619	/** Critical section protecting the HDA state. */
620	PDMCRITSECT CritSect;
621	/** Internal stream states (aligned on 64 byte boundrary). */
622	HDASTREAM aStreams[HDA_MAX_STREAMS];
623	/** The HDA's register set. */
624	uint32_t au32Regs[HDA_NUM_REGS];
625	/** CORB buffer base address. */
626	uint64_t u64CORBBase;
627	/** RIRB buffer base address. */
628	uint64_t u64RIRBBase;
629	/** DMA base address.
630	* Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
631	uint64_t u64DPBase;
632	/** Size in bytes of CORB buffer (#au32CorbBuf). */
633	uint32_t cbCorbBuf;
634	/** Size in bytes of RIRB buffer (#au64RirbBuf). */
635	uint32_t cbRirbBuf;
636	/** Response Interrupt Count (RINTCNT). */
637	uint16_t u16RespIntCnt;
638	/** DMA position buffer enable bit. */
639	bool fDMAPosition;
640	/** Current IRQ level. */
641	uint8_t u8IRQL;
642	/** Config: Internal input DMA buffer size override, specified in milliseconds.
643	* Zero means default size according to buffer and stream config.
644	* @sa BufSizeInMs config value. */
645	uint16_t cMsCircBufIn;
646	/** Config: Internal output DMA buffer size override, specified in milliseconds.
647	* Zero means default size according to buffer and stream config.
648	* @sa BufSizeOutMs config value. */
649	uint16_t cMsCircBufOut;
650	/** The start time of the wall clock (WALCLK), measured on the virtual sync clock. */
651	uint64_t tsWalClkStart;
652	/** CORB DMA task handle.
653	* We use this when there is stuff we cannot handle in ring-0. */
654	PDMTASKHANDLE hCorbDmaTask;
655	/** The CORB buffer. */
656	uint32_t au32CorbBuf[HDA_CORB_SIZE];
657	/** Pointer to RIRB buffer. */
658	uint64_t au64RirbBuf[HDA_RIRB_SIZE];
659
660	/** PCI Region \#0: 16KB of MMIO stuff. */
661	IOMMMIOHANDLE hMmio;
662
663	/** Shared R0/R3 HDA codec to use. */
664	HDACODEC Codec;
665
666	#ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
667	STAMCOUNTER StatAccessDmaOutput;
668	STAMCOUNTER StatAccessDmaOutputToR3;
669	#endif
670	#ifdef VBOX_WITH_STATISTICS
671	STAMPROFILE StatIn;
672	STAMPROFILE StatOut;
673	STAMCOUNTER StatBytesRead;
674	STAMCOUNTER StatBytesWritten;
675
676	/** @name Register statistics.
677	* The array members run parallel to g_aHdaRegMap.
678	* @{ */
679	STAMCOUNTER aStatRegReads[HDA_NUM_REGS];
680	STAMCOUNTER aStatRegReadsToR3[HDA_NUM_REGS];
681	STAMCOUNTER aStatRegWrites[HDA_NUM_REGS];
682	STAMCOUNTER aStatRegWritesToR3[HDA_NUM_REGS];
683	STAMCOUNTER StatRegMultiReadsRZ;
684	STAMCOUNTER StatRegMultiReadsR3;
685	STAMCOUNTER StatRegMultiWritesRZ;
686	STAMCOUNTER StatRegMultiWritesR3;
687	STAMCOUNTER StatRegSubWriteRZ;
688	STAMCOUNTER StatRegSubWriteR3;
689	STAMCOUNTER StatRegUnknownReads;
690	STAMCOUNTER StatRegUnknownWrites;
691	STAMCOUNTER StatRegWritesBlockedByReset;
692	STAMCOUNTER StatRegWritesBlockedByRun;
693	/** @} */
694	#endif
695
696	#ifdef DEBUG
697	/** Debug stuff.
698	* @todo Make STAM values out some of this? */
699	struct
700	{
701	# if 0 /* unused */
702	/** Timestamp (in ns) of the last timer callback (hdaTimer).
703	* Used to calculate the time actually elapsed between two timer callbacks. */
704	uint64_t tsTimerLastCalledNs;
705	# endif
706	/** IRQ debugging information. */
707	struct
708	{
709	/** Timestamp (in ns) of last processed (asserted / deasserted) IRQ. */
710	uint64_t tsProcessedLastNs;
711	/** Timestamp (in ns) of last asserted IRQ. */
712	uint64_t tsAssertedNs;
713	# if 0 /* unused */
714	/** How many IRQs have been asserted already. */
715	uint64_t cAsserted;
716	/** Accumulated elapsed time (in ns) of all IRQ being asserted. */
717	uint64_t tsAssertedTotalNs;
718	/** Timestamp (in ns) of last deasserted IRQ. */
719	uint64_t tsDeassertedNs;
720	/** How many IRQs have been deasserted already. */
721	uint64_t cDeasserted;
722	/** Accumulated elapsed time (in ns) of all IRQ being deasserted. */
723	uint64_t tsDeassertedTotalNs;
724	# endif
725	} IRQ;
726	} Dbg;
727	#endif
728	/** This is for checking that the build was correctly configured in all contexts.
729	* This is set to HDASTATE_ALIGNMENT_CHECK_MAGIC. */
730	uint64_t uAlignmentCheckMagic;
731	} HDASTATE;
732	AssertCompileMemberAlignment(HDASTATE, aStreams, 64);
733	/** Pointer to a shared HDA device state. */
734	typedef HDASTATE *PHDASTATE;
735
736	/** Value for HDASTATE:uAlignmentCheckMagic. */
737	#define HDASTATE_ALIGNMENT_CHECK_MAGIC UINT64_C(0x1298afb75893e059)
738
739	/**
740	* Ring-0 ICH Intel HD audio controller state.
741	*/
742	typedef struct HDASTATER0
743	{
744	# if 0 /* Codec is not yet kosher enough for ring-0. @bugref{9890c64} */
745	/** Pointer to HDA codec to use. */
746	HDACODECR0 Codec;
747	# else
748	uint32_t u32Dummy;
749	# endif
750	} HDASTATER0;
751	/** Pointer to a ring-0 HDA device state. */
752	typedef HDASTATER0 *PHDASTATER0;
753
754	/**
755	* Ring-3 ICH Intel HD audio controller state.
756	*/
757	typedef struct HDASTATER3
758	{
759	/** Internal stream states. */
760	HDASTREAMR3 aStreams[HDA_MAX_STREAMS];
761	/** Mapping table between stream tags and stream states. */
762	HDATAG aTags[HDA_MAX_TAGS];
763	/** R3 Pointer to the device instance. */
764	PPDMDEVINSR3 pDevIns;
765	/** The base interface for LUN\#0. */
766	PDMIBASE IBase;
767	/** Pointer to HDA codec to use. */
768	R3PTRTYPE(PHDACODECR3) pCodec;
769	/** List of associated LUN drivers (HDADRIVER). */
770	RTLISTANCHORR3 lstDrv;
771	/** The device' software mixer. */
772	R3PTRTYPE(PAUDIOMIXER) pMixer;
773	/** HDA sink for (front) output. */
774	HDAMIXERSINK SinkFront;
775	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
776	/** HDA sink for center / LFE output. */
777	HDAMIXERSINK SinkCenterLFE;
778	/** HDA sink for rear output. */
779	HDAMIXERSINK SinkRear;
780	#endif
781	/** HDA mixer sink for line input. */
782	HDAMIXERSINK SinkLineIn;
783	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
784	/** Audio mixer sink for microphone input. */
785	HDAMIXERSINK SinkMicIn;
786	#endif
787	/** Debug stuff. */
788	struct
789	{
790	/** Whether debugging is enabled or not. */
791	bool fEnabled;
792	/** Path where to dump the debug output to.
793	* Can be NULL, in which the system's temporary directory will be used then. */
794	R3PTRTYPE(char *) pszOutPath;
795	} Dbg;
796	} HDASTATER3;
797
798
799	/** Pointer to the context specific HDA state (HDASTATER3 or HDASTATER0). */
800	typedef CTX_SUFF(PHDASTATE) PHDASTATECC;
801
802
803	/** @def HDA_PROCESS_INTERRUPT
804	* Wrapper around hdaProcessInterrupt that supplies the source function name
805	* string in logging builds. */
806	#if defined(LOG_ENABLED) \|\| defined(DOXYGEN_RUNNING)
807	void hdaProcessInterrupt(PPDMDEVINS pDevIns, PHDASTATE pThis, const char *pszSource);
808	# define HDA_PROCESS_INTERRUPT(a_pDevIns, a_pThis) hdaProcessInterrupt((a_pDevIns), (a_pThis), __FUNCTION__)
809	#else
810	void hdaProcessInterrupt(PPDMDEVINS pDevIns, PHDASTATE pThis);
811	# define HDA_PROCESS_INTERRUPT(a_pDevIns, a_pThis) hdaProcessInterrupt((a_pDevIns), (a_pThis))
812	#endif
813
814	/**
815	* Returns the audio direction of a specified stream descriptor.
816	*
817	* The register layout specifies that input streams (SDI) come first,
818	* followed by the output streams (SDO). So every stream ID below HDA_MAX_SDI
819	* is an input stream, whereas everything >= HDA_MAX_SDI is an output stream.
820	*
821	* @note SDnFMT register does not provide that information, so we have to judge
822	* for ourselves.
823	*
824	* @return Audio direction.
825	* @param uSD The stream number.
826	*/
827	DECLINLINE(PDMAUDIODIR) hdaGetDirFromSD(uint8_t uSD)
828	{
829	if (uSD < HDA_MAX_SDI)
830	return PDMAUDIODIR_IN;
831	AssertReturn(uSD < HDA_MAX_STREAMS, PDMAUDIODIR_UNKNOWN);
832	return PDMAUDIODIR_OUT;
833	}
834
835	/* Used by hdaR3StreamSetUp: */
836	uint8_t hdaSDFIFOWToBytes(uint16_t u16RegFIFOW);
837
838
839	#ifdef VBOX_STRICT
840	/**
841	* Strict register accessor verifing defines and mapping table.
842	* @see HDA_REG
843	*/
844	DECLINLINE(uint32_t *) hdaStrictRegAccessor(PHDASTATE pThis, uint32_t idxMap, uint32_t idxReg)
845	{
846	Assert(idxMap < RT_ELEMENTS(g_aHdaRegMap));
847	AssertMsg(idxReg == g_aHdaRegMap[idxMap].mem_idx, ("idxReg=%d\n", idxReg));
848	return &pThis->au32Regs[idxReg];
849	}
850
851	/**
852	* Strict stream register accessor verifing defines and mapping table.
853	* @see HDA_STREAM_REG
854	*/
855	DECLINLINE(uint32_t *) hdaStrictStreamRegAccessor(PHDASTATE pThis, uint32_t idxMap0, uint32_t idxReg0, size_t idxStream)
856	{
857	Assert(idxMap0 < RT_ELEMENTS(g_aHdaRegMap));
858	AssertMsg(idxStream < RT_ELEMENTS(pThis->aStreams), ("%#zx\n", idxStream));
859	AssertMsg(idxReg0 + idxStream * 10 == g_aHdaRegMap[idxMap0 + idxStream * 10].mem_idx,
860	("idxReg0=%d idxStream=%zx\n", idxReg0, idxStream));
861	return &pThis->au32Regs[idxReg0 + idxStream * 10];
862	}
863
864	#endif /* VBOX_STRICT */
865
866
867
868	/** @name Saved state versions for the HDA device
869	* @{ */
870	/** The current staved state version.
871	* @note Only for the registration call. Never used for tests. */
872	#define HDA_SAVED_STATE_VERSION HDA_SAVED_STATE_WITHOUT_PERIOD
873
874	/** Removed period and redefined wall clock. */
875	#define HDA_SAVED_STATE_WITHOUT_PERIOD 8
876	/** Added (Controller): Current wall clock value (this independent from WALCLK register value).
877	* Added (Controller): Current IRQ level.
878	* Added (Per stream): Ring buffer. This is optional and can be skipped if (not) needed.
879	* Added (Per stream): Struct g_aSSMStreamStateFields7.
880	* Added (Per stream): Struct g_aSSMStreamPeriodFields7.
881	* Added (Current BDLE per stream): Struct g_aSSMBDLEDescFields7.
882	* Added (Current BDLE per stream): Struct g_aSSMBDLEStateFields7. */
883	#define HDA_SAVED_STATE_VERSION_7 7
884	/** Saves the current BDLE state.
885	* @since 5.0.14 (r104839) */
886	#define HDA_SAVED_STATE_VERSION_6 6
887	/** Introduced dynamic number of streams + stream identifiers for serialization.
888	* Bug: Did not save the BDLE states correctly.
889	* Those will be skipped on load then.
890	* @since 5.0.12 (r104520) */
891	#define HDA_SAVED_STATE_VERSION_5 5
892	/** Since this version the number of MMIO registers can be flexible. */
893	#define HDA_SAVED_STATE_VERSION_4 4
894	#define HDA_SAVED_STATE_VERSION_3 3
895	#define HDA_SAVED_STATE_VERSION_2 2
896	#define HDA_SAVED_STATE_VERSION_1 1
897	/** @} */
898
899	#endif /* !VBOX_INCLUDED_SRC_Audio_DevHda_h */
900

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source: vbox/trunk/src/VBox/Devices/Audio/DevHda.h@ 89899

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