DevHda.h@ 90138

Last change on this file since 90138 was 90138, checked in by vboxsync, 3 years ago
DevHda: Only HDACODECR3, no HDACODEC structure any more. bugref:9890
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1	/* $Id: DevHda.h 90138 2021-07-09 21:02:07Z vboxsync $ */
2	/** @file
3	* Intel HD Audio Controller Emulation - Structures.
4	*/
5
6	/*
7	* Copyright (C) 2016-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VBOX_INCLUDED_SRC_Audio_DevHda_h
19	#define VBOX_INCLUDED_SRC_Audio_DevHda_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <iprt/path.h>
25	#include <VBox/vmm/pdmdev.h>
26	#include "AudioMixer.h"
27
28	/*
29	* Compile time feature configuration.
30	*/
31
32	/** @def VBOX_HDA_WITH_ON_REG_ACCESS_DMA
33	* Enables doing DMA work on certain register accesses (LPIB, WALCLK) in
34	* addition to the DMA timer. All but the last frame can be done during
35	* register accesses (as we don't wish to leave the DMA timer w/o work to
36	* do in case that upsets it). */
37	#if defined(DOXYGEN_RUNNING) \|\| 0
38	# define VBOX_HDA_WITH_ON_REG_ACCESS_DMA
39	#endif
40
41	#ifdef DEBUG_andy
42	/** Enables strict mode, which checks for stuff which isn't supposed to happen.
43	* Be prepared for assertions coming in! */
44	//# define HDA_STRICT
45	#endif
46
47	/** @def HDA_AS_PCI_EXPRESS
48	* Enables PCI express hardware. */
49	#if defined(DOXYGEN_RUNNING) \|\| 0
50	# define HDA_AS_PCI_EXPRESS
51	#endif
52
53	/** @def HDA_DEBUG_SILENCE
54	* To debug silence coming from the guest in form of audio gaps.
55	* Very crude implementation for now.
56	* @todo probably borked atm */
57	#if defined(DOXYGEN_RUNNING) \|\| 0
58	# define HDA_DEBUG_SILENCE
59	#endif
60
61
62	/*
63	* Common pointer types.
64	*/
65	/** Pointer to an HDA stream (SDI / SDO). */
66	typedef struct HDASTREAMR3 *PHDASTREAMR3;
67	/** Pointer to a shared HDA device state. */
68	typedef struct HDASTATE *PHDASTATE;
69	/** Pointer to a ring-3 HDA device state. */
70	typedef struct HDASTATER3 *PHDASTATER3;
71	/** Pointer to an HDA mixer sink definition (ring-3). */
72	typedef struct HDAMIXERSINK *PHDAMIXERSINK;
73
74
75	/*
76	* The rest of the headers.
77	*/
78	#include "DevHdaStream.h"
79	#include "DevHdaCodec.h"
80
81
82
83	/** @name Stream counts.
84	*
85	* At the moment we support 4 input + 4 output streams max, which is 8 in total.
86	* Bidirectional streams are currently not supported.
87	*
88	* @note When changing any of those values, be prepared for some saved state
89	* fixups / trouble!
90	* @{
91	*/
92	#define HDA_MAX_SDI 4
93	#define HDA_MAX_SDO 4
94	#define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
95	/** @} */
96	AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
97
98
99	/** @defgroup grp_hda_regs HDA Register Definitions
100	*
101	* There are two variants for most register defines:
102	* - HDA_REG_XXX: Index into g_aHdaRegMap
103	* - HDA_RMX_XXX: Index into HDASTATE::au32Regs
104	*
105	* Use the HDA_REG and HDA_STREAM_REG macros to access registers where possible.
106	*
107	* @note The au32Regs[] layout is kept unchanged for saved state compatibility,
108	* thus the HDA_RMX_XXX assignments are for all purposes set in stone.
109	*
110	* @{ */
111
112	/** Number of general registers. */
113	#define HDA_NUM_GENERAL_REGS 34
114	/** Number of total registers in the HDA's register map. */
115	#define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */))
116	/** Total number of stream tags (channels). Index 0 is reserved / invalid. */
117	#define HDA_MAX_TAGS 16
118
119
120	/** Offset of the SD0 register map. */
121	#define HDA_REG_DESC_SD0_BASE 0x80
122
123	/* Registers */
124	#define HDA_REG_IND_NAME(x) HDA_REG_##x
125	#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
126
127	/** Direct register access by HDASTATE::au32Reg index. */
128	#define HDA_REG_BY_IDX(a_pThis, a_idxReg) ((a_pThis)->au32Regs[(a_idxReg)])
129
130	/** Accesses register @a ShortRegNm. */
131	#if defined(VBOX_STRICT) && defined(VBOX_HDA_CAN_ACCESS_REG_MAP)
132	# define HDA_REG(a_pThis, a_ShortRegNm) (*hdaStrictRegAccessor(a_pThis, HDA_REG_IND_NAME(a_ShortRegNm), HDA_MEM_IND_NAME(a_ShortRegNm)))
133	#else
134	# define HDA_REG(a_pThis, a_ShortRegNm) HDA_REG_BY_IDX(a_pThis, HDA_MEM_IND_NAME(a_ShortRegNm))
135	#endif
136
137	/** Indirect register access via g_aHdaRegMap[].idxReg. */
138	#define HDA_REG_IND(a_pThis, a_idxMap) HDA_REG_BY_IDX(a_pThis, g_aHdaRegMap[(a_idxMap)].idxReg)
139
140
141	#define HDA_REG_GCAP 0 /* Range 0x00 - 0x01 */
142	#define HDA_RMX_GCAP 0
143	/**
144	* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
145	*
146	* oss (15:12) - Number of output streams supported.
147	* iss (11:8) - Number of input streams supported.
148	* bss (7:3) - Number of bidirectional streams supported.
149	* bds (2:1) - Number of serial data out (SDO) signals supported.
150	* b64sup (0) - 64 bit addressing supported.
151	*/
152	#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
153	( (((oss) & 0xF) << 12) \
154	\| (((iss) & 0xF) << 8) \
155	\| (((bss) & 0x1F) << 3) \
156	\| (((bds) & 0x3) << 2) \
157	\| ((b64sup) & 1))
158
159	#define HDA_REG_VMIN 1 /* 0x02 */
160	#define HDA_RMX_VMIN 1
161
162	#define HDA_REG_VMAJ 2 /* 0x03 */
163	#define HDA_RMX_VMAJ 2
164
165	#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
166	#define HDA_RMX_OUTPAY 3
167
168	#define HDA_REG_INPAY 4 /* 0x06-0x07 */
169	#define HDA_RMX_INPAY 4
170
171	#define HDA_REG_GCTL 5 /* 0x08-0x0B */
172	#define HDA_RMX_GCTL 5
173	#define HDA_GCTL_UNSOL RT_BIT(8) /* Accept Unsolicited Response Enable */
174	#define HDA_GCTL_FCNTRL RT_BIT(1) /* Flush Control */
175	#define HDA_GCTL_CRST RT_BIT(0) /* Controller Reset */
176
177	#define HDA_REG_WAKEEN 6 /* 0x0C */
178	#define HDA_RMX_WAKEEN 6
179
180	#define HDA_REG_STATESTS 7 /* 0x0E */
181	#define HDA_RMX_STATESTS 7
182	#define HDA_STATESTS_SCSF_MASK 0x7 /* State Change Status Flags (6.2.8). */
183
184	#define HDA_REG_GSTS 8 /* 0x10-0x11*/
185	#define HDA_RMX_GSTS 8
186	#define HDA_GSTS_FSTS RT_BIT(1) /* Flush Status */
187
188	#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
189	#define HDA_RMX_OUTSTRMPAY 112
190
191	#define HDA_REG_INSTRMPAY 10 /* 0x1a */
192	#define HDA_RMX_INSTRMPAY 113
193
194	#define HDA_REG_INTCTL 11 /* 0x20 */
195	#define HDA_RMX_INTCTL 9
196	#define HDA_INTCTL_GIE RT_BIT(31) /* Global Interrupt Enable */
197	#define HDA_INTCTL_CIE RT_BIT(30) /* Controller Interrupt Enable */
198	/** Bits 0-29 correspond to streams 0-29. */
199	#define HDA_STRMINT_MASK 0xFF /* Streams 0-7 implemented. Applies to INTCTL and INTSTS. */
200
201	#define HDA_REG_INTSTS 12 /* 0x24 */
202	#define HDA_RMX_INTSTS 10
203	#define HDA_INTSTS_GIS RT_BIT(31) /* Global Interrupt Status */
204	#define HDA_INTSTS_CIS RT_BIT(30) /* Controller Interrupt Status */
205
206	#define HDA_REG_WALCLK 13 /* 0x30 */
207	/*NB: HDA_RMX_WALCLK is not defined because the register is not stored in memory. /
208
209	/**
210	* Note: The HDA specification defines a SSYNC register at offset 0x38. The
211	* ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
212	* the datasheet.
213	*/
214	#define HDA_REG_SSYNC 14 /* 0x34 */
215	#define HDA_RMX_SSYNC 12
216
217	#define HDA_REG_CORBLBASE 15 /* 0x40 */
218	#define HDA_RMX_CORBLBASE 13
219
220	#define HDA_REG_CORBUBASE 16 /* 0x44 */
221	#define HDA_RMX_CORBUBASE 14
222
223	#define HDA_REG_CORBWP 17 /* 0x48 */
224	#define HDA_RMX_CORBWP 15
225
226	#define HDA_REG_CORBRP 18 /* 0x4A */
227	#define HDA_RMX_CORBRP 16
228	#define HDA_CORBRP_RST RT_BIT(15) /* CORB Read Pointer Reset */
229
230	#define HDA_REG_CORBCTL 19 /* 0x4C */
231	#define HDA_RMX_CORBCTL 17
232	#define HDA_CORBCTL_DMA RT_BIT(1) /* Enable CORB DMA Engine */
233	#define HDA_CORBCTL_CMEIE RT_BIT(0) /* CORB Memory Error Interrupt Enable */
234
235	#define HDA_REG_CORBSTS 20 /* 0x4D */
236	#define HDA_RMX_CORBSTS 18
237
238	#define HDA_REG_CORBSIZE 21 /* 0x4E */
239	#define HDA_RMX_CORBSIZE 19
240	#define HDA_CORBSIZE_SZ_CAP 0xF0
241	#define HDA_CORBSIZE_SZ 0x3
242
243	/** Number of CORB buffer entries. */
244	#define HDA_CORB_SIZE 256
245	/** CORB element size (in bytes). */
246	#define HDA_CORB_ELEMENT_SIZE 4
247	/** Number of RIRB buffer entries. */
248	#define HDA_RIRB_SIZE 256
249	/** RIRB element size (in bytes). */
250	#define HDA_RIRB_ELEMENT_SIZE 8
251
252	#define HDA_REG_RIRBLBASE 22 /* 0x50 */
253	#define HDA_RMX_RIRBLBASE 20
254
255	#define HDA_REG_RIRBUBASE 23 /* 0x54 */
256	#define HDA_RMX_RIRBUBASE 21
257
258	#define HDA_REG_RIRBWP 24 /* 0x58 */
259	#define HDA_RMX_RIRBWP 22
260	#define HDA_RIRBWP_RST RT_BIT(15) /* RIRB Write Pointer Reset */
261
262	#define HDA_REG_RINTCNT 25 /* 0x5A */
263	#define HDA_RMX_RINTCNT 23
264
265	/** Maximum number of Response Interrupts. */
266	#define HDA_MAX_RINTCNT 256
267
268	#define HDA_REG_RIRBCTL 26 /* 0x5C */
269	#define HDA_RMX_RIRBCTL 24
270	#define HDA_RIRBCTL_ROIC RT_BIT(2) /* Response Overrun Interrupt Control */
271	#define HDA_RIRBCTL_RDMAEN RT_BIT(1) /* RIRB DMA Enable */
272	#define HDA_RIRBCTL_RINTCTL RT_BIT(0) /* Response Interrupt Control */
273
274	#define HDA_REG_RIRBSTS 27 /* 0x5D */
275	#define HDA_RMX_RIRBSTS 25
276	#define HDA_RIRBSTS_RIRBOIS RT_BIT(2) /* Response Overrun Interrupt Status */
277	#define HDA_RIRBSTS_RINTFL RT_BIT(0) /* Response Interrupt Flag */
278
279	#define HDA_REG_RIRBSIZE 28 /* 0x5E */
280	#define HDA_RMX_RIRBSIZE 26
281
282	#define HDA_REG_IC 29 /* 0x60 */
283	#define HDA_RMX_IC 27
284
285	#define HDA_REG_IR 30 /* 0x64 */
286	#define HDA_RMX_IR 28
287
288	#define HDA_REG_IRS 31 /* 0x68 */
289	#define HDA_RMX_IRS 29
290	#define HDA_IRS_IRV RT_BIT(1) /* Immediate Result Valid */
291	#define HDA_IRS_ICB RT_BIT(0) /* Immediate Command Busy */
292
293	#define HDA_REG_DPLBASE 32 /* 0x70 */
294	#define HDA_RMX_DPLBASE 30
295
296	#define HDA_REG_DPUBASE 33 /* 0x74 */
297	#define HDA_RMX_DPUBASE 31
298
299	#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
300
301	#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
302	#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
303	/** @note sdnum here _MUST_ be stream reg number [0,7]. */
304	#if defined(VBOX_STRICT) && defined(VBOX_HDA_CAN_ACCESS_REG_MAP)
305	# define HDA_STREAM_REG(pThis, name, sdnum) (*hdaStrictStreamRegAccessor((pThis), HDA_REG_SD0##name, HDA_RMX_SD0##name, (sdnum)))
306	#else
307	# define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_BY_IDX((pThis), HDA_RMX_SD0##name + (sdnum) * 10))
308	#endif
309
310	#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
311
312	/** @todo Condense marcos! */
313
314	#define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80; other streams offset by 0x20 */
315	#define HDA_RMX_SD0CTL 32
316	#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
317	#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
318	#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
319	#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
320	#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
321	#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
322	#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
323
324	#define HDA_SDCTL_NUM_MASK 0xF
325	#define HDA_SDCTL_NUM_SHIFT 20
326	#define HDA_SDCTL_DIR RT_BIT(19) /* Direction (Bidirectional streams only!) */
327	#define HDA_SDCTL_TP RT_BIT(18) /* Traffic Priority (PCI Express) */
328	#define HDA_SDCTL_STRIPE_MASK 0x3
329	#define HDA_SDCTL_STRIPE_SHIFT 16
330	#define HDA_SDCTL_DEIE RT_BIT(4) /* Descriptor Error Interrupt Enable */
331	#define HDA_SDCTL_FEIE RT_BIT(3) /* FIFO Error Interrupt Enable */
332	#define HDA_SDCTL_IOCE RT_BIT(2) /* Interrupt On Completion Enable */
333	#define HDA_SDCTL_RUN RT_BIT(1) /* Stream Run */
334	#define HDA_SDCTL_SRST RT_BIT(0) /* Stream Reset */
335
336	#define HDA_REG_SD0STS 35 /* 0x83; other streams offset by 0x20 */
337	#define HDA_RMX_SD0STS 33
338	#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
339	#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
340	#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
341	#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
342	#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
343	#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
344	#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
345
346	#define HDA_SDSTS_FIFORDY RT_BIT(5) /* FIFO Ready */
347	#define HDA_SDSTS_DESE RT_BIT(4) /* Descriptor Error */
348	#define HDA_SDSTS_FIFOE RT_BIT(3) /* FIFO Error */
349	#define HDA_SDSTS_BCIS RT_BIT(2) /* Buffer Completion Interrupt Status */
350
351	#define HDA_REG_SD0LPIB 36 /* 0x84; other streams offset by 0x20 */
352	#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
353	#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
354	#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
355	#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
356	#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
357	#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
358	#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
359	#define HDA_RMX_SD0LPIB 34
360	#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
361	#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
362	#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
363	#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
364	#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
365	#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
366	#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
367
368	#define HDA_REG_SD0CBL 37 /* 0x88; other streams offset by 0x20 */
369	#define HDA_RMX_SD0CBL 35
370	#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
371	#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
372	#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
373	#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
374	#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
375	#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
376	#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
377
378	#define HDA_REG_SD0LVI 38 /* 0x8C; other streams offset by 0x20 */
379	#define HDA_RMX_SD0LVI 36
380	#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
381	#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
382	#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
383	#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
384	#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
385	#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
386	#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
387
388	#define HDA_REG_SD0FIFOW 39 /* 0x8E; other streams offset by 0x20 */
389	#define HDA_RMX_SD0FIFOW 37
390	#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
391	#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
392	#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
393	#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
394	#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
395	#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
396	#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
397
398	/*
399	* ICH6 datasheet defined limits for FIFOW values (18.2.38).
400	*/
401	#define HDA_SDFIFOW_8B 0x2
402	#define HDA_SDFIFOW_16B 0x3
403	#define HDA_SDFIFOW_32B 0x4
404
405	#define HDA_REG_SD0FIFOS 40 /* 0x90; other streams offset by 0x20 */
406	#define HDA_RMX_SD0FIFOS 38
407	#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
408	#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
409	#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
410	#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
411	#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
412	#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
413	#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
414
415	/* The ICH6 datasheet defines limits for FIFOS registers (18.2.39).
416	Formula: size - 1
417	Other values not listed are not supported. */
418
419	#define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
420	#define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
421
422	#define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
423	#define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
424	#define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
425	#define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
426	#define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
427	#define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
428
429	#define HDA_REG_SD0FMT 41 /* 0x92; other streams offset by 0x20 */
430	#define HDA_RMX_SD0FMT 39
431	#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
432	#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
433	#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
434	#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
435	#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
436	#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
437	#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
438
439	#define HDA_REG_SD0BDPL 42 /* 0x98; other streams offset by 0x20 */
440	#define HDA_RMX_SD0BDPL 40
441	#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
442	#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
443	#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
444	#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
445	#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
446	#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
447	#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
448
449	#define HDA_REG_SD0BDPU 43 /* 0x9C; other streams offset by 0x20 */
450	#define HDA_RMX_SD0BDPU 41
451	#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
452	#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
453	#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
454	#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
455	#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
456	#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
457	#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
458
459	#define HDA_CODEC_CAD_SHIFT 28
460	/** Encodes the (required) LUN into a codec command. */
461	#define HDA_CODEC_CMD(cmd, lun) ((cmd) \| (lun << HDA_CODEC_CAD_SHIFT))
462
463	#define HDA_SDFMT_NON_PCM_SHIFT 15
464	#define HDA_SDFMT_NON_PCM_MASK 0x1
465	#define HDA_SDFMT_BASE_RATE_SHIFT 14
466	#define HDA_SDFMT_BASE_RATE_MASK 0x1
467	#define HDA_SDFMT_MULT_SHIFT 11
468	#define HDA_SDFMT_MULT_MASK 0x7
469	#define HDA_SDFMT_DIV_SHIFT 8
470	#define HDA_SDFMT_DIV_MASK 0x7
471	#define HDA_SDFMT_BITS_SHIFT 4
472	#define HDA_SDFMT_BITS_MASK 0x7
473	#define HDA_SDFMT_CHANNELS_MASK 0xF
474
475	#define HDA_SDFMT_TYPE RT_BIT(15)
476	#define HDA_SDFMT_TYPE_PCM (0)
477	#define HDA_SDFMT_TYPE_NON_PCM (1)
478
479	#define HDA_SDFMT_BASE RT_BIT(14)
480	#define HDA_SDFMT_BASE_48KHZ (0)
481	#define HDA_SDFMT_BASE_44KHZ (1)
482
483	#define HDA_SDFMT_MULT_1X (0)
484	#define HDA_SDFMT_MULT_2X (1)
485	#define HDA_SDFMT_MULT_3X (2)
486	#define HDA_SDFMT_MULT_4X (3)
487
488	#define HDA_SDFMT_DIV_1X (0)
489	#define HDA_SDFMT_DIV_2X (1)
490	#define HDA_SDFMT_DIV_3X (2)
491	#define HDA_SDFMT_DIV_4X (3)
492	#define HDA_SDFMT_DIV_5X (4)
493	#define HDA_SDFMT_DIV_6X (5)
494	#define HDA_SDFMT_DIV_7X (6)
495	#define HDA_SDFMT_DIV_8X (7)
496
497	#define HDA_SDFMT_8_BIT (0)
498	#define HDA_SDFMT_16_BIT (1)
499	#define HDA_SDFMT_20_BIT (2)
500	#define HDA_SDFMT_24_BIT (3)
501	#define HDA_SDFMT_32_BIT (4)
502
503	#define HDA_SDFMT_CHAN_MONO (0)
504	#define HDA_SDFMT_CHAN_STEREO (1)
505
506	/** Emits a SDnFMT register format.
507	* Also being used in the codec's converter format. */
508	#define HDA_SDFMT_MAKE(_afNonPCM, _aBaseRate, _aMult, _aDiv, _aBits, _aChan) \
509	( (((_afNonPCM) & HDA_SDFMT_NON_PCM_MASK) << HDA_SDFMT_NON_PCM_SHIFT) \
510	\| (((_aBaseRate) & HDA_SDFMT_BASE_RATE_MASK) << HDA_SDFMT_BASE_RATE_SHIFT) \
511	\| (((_aMult) & HDA_SDFMT_MULT_MASK) << HDA_SDFMT_MULT_SHIFT) \
512	\| (((_aDiv) & HDA_SDFMT_DIV_MASK) << HDA_SDFMT_DIV_SHIFT) \
513	\| (((_aBits) & HDA_SDFMT_BITS_MASK) << HDA_SDFMT_BITS_SHIFT) \
514	\| ( (_aChan) & HDA_SDFMT_CHANNELS_MASK))
515
516	/** @} / / grp_hda_regs */
517
518
519	/**
520	* Buffer descriptor list entry (BDLE).
521	*
522	* See 3.6.3 in HDA specs rev 1.0a (2010-06-17).
523	*/
524	typedef struct HDABDLEDESC
525	{
526	/** Starting address of the actual buffer. Must be 128-bit aligned. */
527	uint64_t u64BufAddr;
528	/** Size of the actual buffer (in bytes). */
529	uint32_t u32BufSize;
530	/** HDA_BDLE_F_XXX.
531	*
532	* Bit 0: IOC - Interrupt on completion / HDA_BDLE_F_IOC.
533	* The controller will generate an interrupt when the last byte of the buffer
534	* has been fetched by the DMA engine.
535	*
536	* Bits 31:1 are reserved for further use and must be 0. */
537	uint32_t fFlags;
538	} HDABDLEDESC, *PHDABDLEDESC;
539	AssertCompileSize(HDABDLEDESC, 16); /* Always 16 byte. Also must be aligned on 128-byte boundary. */
540
541	/** Interrupt on completion (IOC) flag. */
542	#define HDA_BDLE_F_IOC RT_BIT(0)
543
544
545	/**
546	* HDA mixer sink definition (ring-3).
547	*
548	* Its purpose is to know which audio mixer sink is bound to which SDn
549	* (SDI/SDO) device stream.
550	*
551	* This is needed in order to handle interleaved streams (that is, multiple
552	* channels in one stream) or non-interleaved streams (each channel has a
553	* dedicated stream).
554	*
555	* This is only known to the actual device emulation level.
556	*/
557	typedef struct HDAMIXERSINK
558	{
559	R3PTRTYPE(PHDASTREAM) pStreamShared;
560	R3PTRTYPE(PHDASTREAMR3) pStreamR3;
561	/** Pointer to the actual audio mixer sink. */
562	R3PTRTYPE(PAUDMIXSINK) pMixSink;
563	} HDAMIXERSINK;
564
565	/**
566	* Mapping a stream tag to an HDA stream (ring-3).
567	*/
568	typedef struct HDATAG
569	{
570	/** Own stream tag. */
571	uint8_t uTag;
572	uint8_t Padding[7];
573	/** Pointer to associated stream. */
574	R3PTRTYPE(PHDASTREAMR3) pStreamR3;
575	} HDATAG;
576	/** Pointer to a HDA stream tag mapping. */
577	typedef HDATAG *PHDATAG;
578
579	/**
580	* Shared ICH Intel HD audio controller state.
581	*/
582	typedef struct HDASTATE
583	{
584	/** Critical section protecting the HDA state. */
585	PDMCRITSECT CritSect;
586	/** Internal stream states (aligned on 64 byte boundrary). */
587	HDASTREAM aStreams[HDA_MAX_STREAMS];
588	/** The HDA's register set. */
589	uint32_t au32Regs[HDA_NUM_REGS];
590	/** CORB buffer base address. */
591	uint64_t u64CORBBase;
592	/** RIRB buffer base address. */
593	uint64_t u64RIRBBase;
594	/** DMA base address.
595	* Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
596	uint64_t u64DPBase;
597	/** Size in bytes of CORB buffer (#au32CorbBuf). */
598	uint32_t cbCorbBuf;
599	/** Size in bytes of RIRB buffer (#au64RirbBuf). */
600	uint32_t cbRirbBuf;
601	/** Response Interrupt Count (RINTCNT). */
602	uint16_t u16RespIntCnt;
603	/** DMA position buffer enable bit. */
604	bool fDMAPosition;
605	/** Current IRQ level. */
606	uint8_t u8IRQL;
607	/** Config: Internal input DMA buffer size override, specified in milliseconds.
608	* Zero means default size according to buffer and stream config.
609	* @sa BufSizeInMs config value. */
610	uint16_t cMsCircBufIn;
611	/** Config: Internal output DMA buffer size override, specified in milliseconds.
612	* Zero means default size according to buffer and stream config.
613	* @sa BufSizeOutMs config value. */
614	uint16_t cMsCircBufOut;
615	/** The start time of the wall clock (WALCLK), measured on the virtual sync clock. */
616	uint64_t tsWalClkStart;
617	/** CORB DMA task handle.
618	* We use this when there is stuff we cannot handle in ring-0. */
619	PDMTASKHANDLE hCorbDmaTask;
620	/** The CORB buffer. */
621	uint32_t au32CorbBuf[HDA_CORB_SIZE];
622	/** Pointer to RIRB buffer. */
623	uint64_t au64RirbBuf[HDA_RIRB_SIZE];
624
625	/** PCI Region \#0: 16KB of MMIO stuff. */
626	IOMMMIOHANDLE hMmio;
627
628	#ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
629	STAMCOUNTER StatAccessDmaOutput;
630	STAMCOUNTER StatAccessDmaOutputToR3;
631	#endif
632	#ifdef VBOX_WITH_STATISTICS
633	STAMPROFILE StatIn;
634	STAMPROFILE StatOut;
635	STAMCOUNTER StatBytesRead;
636	STAMCOUNTER StatBytesWritten;
637
638	/** @name Register statistics.
639	* The array members run parallel to g_aHdaRegMap.
640	* @{ */
641	STAMCOUNTER aStatRegReads[HDA_NUM_REGS];
642	STAMCOUNTER aStatRegReadsToR3[HDA_NUM_REGS];
643	STAMCOUNTER aStatRegWrites[HDA_NUM_REGS];
644	STAMCOUNTER aStatRegWritesToR3[HDA_NUM_REGS];
645	STAMCOUNTER StatRegMultiReadsRZ;
646	STAMCOUNTER StatRegMultiReadsR3;
647	STAMCOUNTER StatRegMultiWritesRZ;
648	STAMCOUNTER StatRegMultiWritesR3;
649	STAMCOUNTER StatRegSubWriteRZ;
650	STAMCOUNTER StatRegSubWriteR3;
651	STAMCOUNTER StatRegUnknownReads;
652	STAMCOUNTER StatRegUnknownWrites;
653	STAMCOUNTER StatRegWritesBlockedByReset;
654	STAMCOUNTER StatRegWritesBlockedByRun;
655	/** @} */
656	#endif
657
658	#ifdef DEBUG
659	/** Debug stuff.
660	* @todo Make STAM values out some of this? */
661	struct
662	{
663	# if 0 /* unused */
664	/** Timestamp (in ns) of the last timer callback (hdaTimer).
665	* Used to calculate the time actually elapsed between two timer callbacks. */
666	uint64_t tsTimerLastCalledNs;
667	# endif
668	/** IRQ debugging information. */
669	struct
670	{
671	/** Timestamp (in ns) of last processed (asserted / deasserted) IRQ. */
672	uint64_t tsProcessedLastNs;
673	/** Timestamp (in ns) of last asserted IRQ. */
674	uint64_t tsAssertedNs;
675	# if 0 /* unused */
676	/** How many IRQs have been asserted already. */
677	uint64_t cAsserted;
678	/** Accumulated elapsed time (in ns) of all IRQ being asserted. */
679	uint64_t tsAssertedTotalNs;
680	/** Timestamp (in ns) of last deasserted IRQ. */
681	uint64_t tsDeassertedNs;
682	/** How many IRQs have been deasserted already. */
683	uint64_t cDeasserted;
684	/** Accumulated elapsed time (in ns) of all IRQ being deasserted. */
685	uint64_t tsDeassertedTotalNs;
686	# endif
687	} IRQ;
688	} Dbg;
689	#endif
690	/** This is for checking that the build was correctly configured in all contexts.
691	* This is set to HDASTATE_ALIGNMENT_CHECK_MAGIC. */
692	uint64_t uAlignmentCheckMagic;
693	} HDASTATE;
694	AssertCompileMemberAlignment(HDASTATE, aStreams, 64);
695	/** Pointer to a shared HDA device state. */
696	typedef HDASTATE *PHDASTATE;
697
698	/** Value for HDASTATE:uAlignmentCheckMagic. */
699	#define HDASTATE_ALIGNMENT_CHECK_MAGIC UINT64_C(0x1298afb75893e059)
700
701	/**
702	* Ring-0 ICH Intel HD audio controller state.
703	*/
704	typedef struct HDASTATER0
705	{
706	# if 0 /* Codec is not yet kosher enough for ring-0. @bugref{9890c64} */
707	/** Pointer to HDA codec to use. */
708	HDACODECR0 Codec;
709	# else
710	uint32_t u32Dummy;
711	# endif
712	} HDASTATER0;
713	/** Pointer to a ring-0 HDA device state. */
714	typedef HDASTATER0 *PHDASTATER0;
715
716	/**
717	* Ring-3 ICH Intel HD audio controller state.
718	*/
719	typedef struct HDASTATER3
720	{
721	/** Internal stream states. */
722	HDASTREAMR3 aStreams[HDA_MAX_STREAMS];
723	/** Mapping table between stream tags and stream states. */
724	HDATAG aTags[HDA_MAX_TAGS];
725	/** R3 Pointer to the device instance. */
726	PPDMDEVINSR3 pDevIns;
727	/** The base interface for LUN\#0. */
728	PDMIBASE IBase;
729	/** List of associated LUN drivers (HDADRIVER). */
730	RTLISTANCHORR3 lstDrv;
731	/** The device' software mixer. */
732	R3PTRTYPE(PAUDIOMIXER) pMixer;
733	/** HDA sink for (front) output. */
734	HDAMIXERSINK SinkFront;
735	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
736	/** HDA sink for center / LFE output. */
737	HDAMIXERSINK SinkCenterLFE;
738	/** HDA sink for rear output. */
739	HDAMIXERSINK SinkRear;
740	#endif
741	/** HDA mixer sink for line input. */
742	HDAMIXERSINK SinkLineIn;
743	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
744	/** Audio mixer sink for microphone input. */
745	HDAMIXERSINK SinkMicIn;
746	#endif
747	/** Debug stuff. */
748	struct
749	{
750	/** Whether debugging is enabled or not. */
751	bool fEnabled;
752	/** Path where to dump the debug output to.
753	* Can be NULL, in which the system's temporary directory will be used then. */
754	R3PTRTYPE(char *) pszOutPath;
755	} Dbg;
756
757	/** The HDA codec state. */
758	HDACODECR3 Codec;
759	} HDASTATER3;
760
761
762	/** Pointer to the context specific HDA state (HDASTATER3 or HDASTATER0). */
763	typedef CTX_SUFF(PHDASTATE) PHDASTATECC;
764
765
766	/** @def HDA_PROCESS_INTERRUPT
767	* Wrapper around hdaProcessInterrupt that supplies the source function name
768	* string in logging builds. */
769	#if defined(LOG_ENABLED) \|\| defined(DOXYGEN_RUNNING)
770	void hdaProcessInterrupt(PPDMDEVINS pDevIns, PHDASTATE pThis, const char *pszSource);
771	# define HDA_PROCESS_INTERRUPT(a_pDevIns, a_pThis) hdaProcessInterrupt((a_pDevIns), (a_pThis), __FUNCTION__)
772	#else
773	void hdaProcessInterrupt(PPDMDEVINS pDevIns, PHDASTATE pThis);
774	# define HDA_PROCESS_INTERRUPT(a_pDevIns, a_pThis) hdaProcessInterrupt((a_pDevIns), (a_pThis))
775	#endif
776
777	/**
778	* Returns the audio direction of a specified stream descriptor.
779	*
780	* The register layout specifies that input streams (SDI) come first,
781	* followed by the output streams (SDO). So every stream ID below HDA_MAX_SDI
782	* is an input stream, whereas everything >= HDA_MAX_SDI is an output stream.
783	*
784	* @note SDnFMT register does not provide that information, so we have to judge
785	* for ourselves.
786	*
787	* @return Audio direction.
788	* @param uSD The stream number.
789	*/
790	DECLINLINE(PDMAUDIODIR) hdaGetDirFromSD(uint8_t uSD)
791	{
792	if (uSD < HDA_MAX_SDI)
793	return PDMAUDIODIR_IN;
794	AssertReturn(uSD < HDA_MAX_STREAMS, PDMAUDIODIR_UNKNOWN);
795	return PDMAUDIODIR_OUT;
796	}
797
798	/* Used by hdaR3StreamSetUp: */
799	uint8_t hdaSDFIFOWToBytes(uint16_t u16RegFIFOW);
800
801	#if defined(VBOX_STRICT) && defined(VBOX_HDA_CAN_ACCESS_REG_MAP)
802	/* Only in DevHda.cpp: */
803	DECLINLINE(uint32_t *) hdaStrictRegAccessor(PHDASTATE pThis, uint32_t idxMap, uint32_t idxReg);
804	DECLINLINE(uint32_t *) hdaStrictStreamRegAccessor(PHDASTATE pThis, uint32_t idxMap0, uint32_t idxReg0, size_t idxStream);
805	#endif /* VBOX_STRICT && VBOX_HDA_CAN_ACCESS_REG_MAP */
806
807
808	/** @name HDA device functions used by the codec.
809	* @{ */
810	DECLHIDDEN(int) hdaR3MixerAddStream(PHDACODECR3 pCodec, PDMAUDIOMIXERCTL enmMixerCtl, PCPDMAUDIOSTREAMCFG pCfg);
811	DECLHIDDEN(int) hdaR3MixerRemoveStream(PHDACODECR3 pCodec, PDMAUDIOMIXERCTL enmMixerCtl, bool fImmediate);
812	DECLHIDDEN(int) hdaR3MixerControl(PHDACODECR3 pCodec, PDMAUDIOMIXERCTL enmMixerCtl, uint8_t uSD, uint8_t uChannel);
813	DECLHIDDEN(int) hdaR3MixerSetVolume(PHDACODECR3 pCodec, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOVOLUME pVol);
814	/** @} */
815
816
817	/** @name Saved state versions for the HDA device
818	* @{ */
819	/** The current staved state version.
820	* @note Only for the registration call. Never used for tests. */
821	#define HDA_SAVED_STATE_VERSION HDA_SAVED_STATE_WITHOUT_PERIOD
822
823	/** Removed period and redefined wall clock. */
824	#define HDA_SAVED_STATE_WITHOUT_PERIOD 8
825	/** Added (Controller): Current wall clock value (this independent from WALCLK register value).
826	* Added (Controller): Current IRQ level.
827	* Added (Per stream): Ring buffer. This is optional and can be skipped if (not) needed.
828	* Added (Per stream): Struct g_aSSMStreamStateFields7.
829	* Added (Per stream): Struct g_aSSMStreamPeriodFields7.
830	* Added (Current BDLE per stream): Struct g_aSSMBDLEDescFields7.
831	* Added (Current BDLE per stream): Struct g_aSSMBDLEStateFields7. */
832	#define HDA_SAVED_STATE_VERSION_7 7
833	/** Saves the current BDLE state.
834	* @since 5.0.14 (r104839) */
835	#define HDA_SAVED_STATE_VERSION_6 6
836	/** Introduced dynamic number of streams + stream identifiers for serialization.
837	* Bug: Did not save the BDLE states correctly.
838	* Those will be skipped on load then.
839	* @since 5.0.12 (r104520) */
840	#define HDA_SAVED_STATE_VERSION_5 5
841	/** Since this version the number of MMIO registers can be flexible. */
842	#define HDA_SAVED_STATE_VERSION_4 4
843	#define HDA_SAVED_STATE_VERSION_3 3
844	#define HDA_SAVED_STATE_VERSION_2 2
845	#define HDA_SAVED_STATE_VERSION_1 1
846	/** @} */
847
848	#endif /* !VBOX_INCLUDED_SRC_Audio_DevHda_h */
849

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