DevHda.h@ 92348

Last change on this file since 92348 was 90158, checked in by vboxsync, 3 years ago
DevHda: Added the minimum of registers linux accesses for the 8086:9d70 device. The result sounds pretty decent, maybe luck or maybe because of SDnDPIB registers used for getting stream position. Recording not tested. bugref:9890
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File size: 37.8 KB

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1	/* $Id: DevHda.h 90158 2021-07-12 13:49:57Z vboxsync $ */
2	/** @file
3	* Intel HD Audio Controller Emulation - Structures.
4	*/
5
6	/*
7	* Copyright (C) 2016-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VBOX_INCLUDED_SRC_Audio_DevHda_h
19	#define VBOX_INCLUDED_SRC_Audio_DevHda_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <iprt/path.h>
25	#include <VBox/vmm/pdmdev.h>
26	#include "AudioMixer.h"
27
28	/*
29	* Compile time feature configuration.
30	*/
31
32	/** @def VBOX_HDA_WITH_ON_REG_ACCESS_DMA
33	* Enables doing DMA work on certain register accesses (LPIB, WALCLK) in
34	* addition to the DMA timer. All but the last frame can be done during
35	* register accesses (as we don't wish to leave the DMA timer w/o work to
36	* do in case that upsets it). */
37	#if defined(DOXYGEN_RUNNING) \|\| 0
38	# define VBOX_HDA_WITH_ON_REG_ACCESS_DMA
39	#endif
40
41	#ifdef DEBUG_andy
42	/** Enables strict mode, which checks for stuff which isn't supposed to happen.
43	* Be prepared for assertions coming in! */
44	//# define HDA_STRICT
45	#endif
46
47	/** @def HDA_AS_PCI_EXPRESS
48	* Enables PCI express hardware. */
49	#if defined(DOXYGEN_RUNNING) \|\| 0
50	# define HDA_AS_PCI_EXPRESS
51	#endif
52
53	/** @def HDA_DEBUG_SILENCE
54	* To debug silence coming from the guest in form of audio gaps.
55	* Very crude implementation for now.
56	* @todo probably borked atm */
57	#if defined(DOXYGEN_RUNNING) \|\| 0
58	# define HDA_DEBUG_SILENCE
59	#endif
60
61
62	/*
63	* Common pointer types.
64	*/
65	/** Pointer to an HDA stream (SDI / SDO). */
66	typedef struct HDASTREAMR3 *PHDASTREAMR3;
67	/** Pointer to a shared HDA device state. */
68	typedef struct HDASTATE *PHDASTATE;
69	/** Pointer to a ring-3 HDA device state. */
70	typedef struct HDASTATER3 *PHDASTATER3;
71	/** Pointer to an HDA mixer sink definition (ring-3). */
72	typedef struct HDAMIXERSINK *PHDAMIXERSINK;
73
74
75	/*
76	* The rest of the headers.
77	*/
78	#include "DevHdaStream.h"
79	#include "DevHdaCodec.h"
80
81
82
83	/** @name Stream counts.
84	*
85	* At the moment we support 4 input + 4 output streams max, which is 8 in total.
86	* Bidirectional streams are currently not supported.
87	*
88	* @note When changing any of those values, be prepared for some saved state
89	* fixups / trouble!
90	* @{
91	*/
92	#define HDA_MAX_SDI 4
93	#define HDA_MAX_SDO 4
94	#define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
95	/** @} */
96	AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
97
98
99	/** @defgroup grp_hda_regs HDA Register Definitions
100	*
101	* There are two variants for most register defines:
102	* - HDA_REG_XXX: Index into g_aHdaRegMap
103	* - HDA_RMX_XXX: Index into HDASTATE::au32Regs
104	*
105	* Use the HDA_REG and HDA_STREAM_REG macros to access registers where possible.
106	*
107	* @note The au32Regs[] layout is kept unchanged for saved state compatibility,
108	* thus the HDA_RMX_XXX assignments are for all purposes set in stone.
109	*
110	* @{ */
111
112	/** Number of general registers. */
113	#define HDA_NUM_GENERAL_REGS 36
114	/** Number of stream registers (10 registers per stream). */
115	#define HDA_NUM_STREAM_REGS (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */)
116	/** Number of register after the stream registers. */
117	#define HDA_NUM_POST_STREAM_REGS (2 + HDA_MAX_STREAMS * 2)
118	/** Number of total registers in the HDA's register map. */
119	#define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + HDA_NUM_STREAM_REGS + HDA_NUM_POST_STREAM_REGS)
120	/** Total number of stream tags (channels). Index 0 is reserved / invalid. */
121	#define HDA_MAX_TAGS 16
122
123
124	/** Offset of the SD0 register map. */
125	#define HDA_REG_DESC_SD0_BASE 0x80
126
127	/* Registers */
128	#define HDA_REG_IND_NAME(x) HDA_REG_##x
129	#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
130
131	/** Direct register access by HDASTATE::au32Reg index. */
132	#define HDA_REG_BY_IDX(a_pThis, a_idxReg) ((a_pThis)->au32Regs[(a_idxReg)])
133
134	/** Accesses register @a ShortRegNm. */
135	#if defined(VBOX_STRICT) && defined(VBOX_HDA_CAN_ACCESS_REG_MAP)
136	# define HDA_REG(a_pThis, a_ShortRegNm) (*hdaStrictRegAccessor(a_pThis, HDA_REG_IND_NAME(a_ShortRegNm), HDA_MEM_IND_NAME(a_ShortRegNm)))
137	#else
138	# define HDA_REG(a_pThis, a_ShortRegNm) HDA_REG_BY_IDX(a_pThis, HDA_MEM_IND_NAME(a_ShortRegNm))
139	#endif
140
141	/** Indirect register access via g_aHdaRegMap[].idxReg. */
142	#define HDA_REG_IND(a_pThis, a_idxMap) HDA_REG_BY_IDX(a_pThis, g_aHdaRegMap[(a_idxMap)].idxReg)
143
144
145	#define HDA_REG_GCAP 0 /* Range 0x00 - 0x01 */
146	#define HDA_RMX_GCAP 0
147	/**
148	* GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
149	*
150	* oss (15:12) - Number of output streams supported.
151	* iss (11:8) - Number of input streams supported.
152	* bss (7:3) - Number of bidirectional streams supported.
153	* bds (2:1) - Number of serial data out (SDO) signals supported.
154	* b64sup (0) - 64 bit addressing supported.
155	*/
156	#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
157	( (((oss) & 0xF) << 12) \
158	\| (((iss) & 0xF) << 8) \
159	\| (((bss) & 0x1F) << 3) \
160	\| (((bds) & 0x3) << 2) \
161	\| ((b64sup) & 1))
162
163	#define HDA_REG_VMIN 1 /* 0x02 */
164	#define HDA_RMX_VMIN 1
165
166	#define HDA_REG_VMAJ 2 /* 0x03 */
167	#define HDA_RMX_VMAJ 2
168
169	#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
170	#define HDA_RMX_OUTPAY 3
171
172	#define HDA_REG_INPAY 4 /* 0x06-0x07 */
173	#define HDA_RMX_INPAY 4
174
175	#define HDA_REG_GCTL 5 /* 0x08-0x0B */
176	#define HDA_RMX_GCTL 5
177	#define HDA_GCTL_UNSOL RT_BIT(8) /* Accept Unsolicited Response Enable */
178	#define HDA_GCTL_FCNTRL RT_BIT(1) /* Flush Control */
179	#define HDA_GCTL_CRST RT_BIT(0) /* Controller Reset */
180
181	#define HDA_REG_WAKEEN 6 /* 0x0C */
182	#define HDA_RMX_WAKEEN 6
183
184	#define HDA_REG_STATESTS 7 /* 0x0E */
185	#define HDA_RMX_STATESTS 7
186	#define HDA_STATESTS_SCSF_MASK 0x7 /* State Change Status Flags (6.2.8). */
187
188	#define HDA_REG_GSTS 8 /* 0x10-0x11*/
189	#define HDA_RMX_GSTS 8
190	#define HDA_GSTS_FSTS RT_BIT(1) /* Flush Status */
191
192	#define HDA_REG_LLCH 9 /* 0x14 */
193	#define HDA_RMX_LLCH 114
194
195	#define HDA_REG_OUTSTRMPAY 10 /* 0x18 */
196	#define HDA_RMX_OUTSTRMPAY 112
197
198	#define HDA_REG_INSTRMPAY 11 /* 0x1a */
199	#define HDA_RMX_INSTRMPAY 113
200
201	#define HDA_REG_INTCTL 12 /* 0x20 */
202	#define HDA_RMX_INTCTL 9
203	#define HDA_INTCTL_GIE RT_BIT(31) /* Global Interrupt Enable */
204	#define HDA_INTCTL_CIE RT_BIT(30) /* Controller Interrupt Enable */
205	/** Bits 0-29 correspond to streams 0-29. */
206	#define HDA_STRMINT_MASK 0xFF /* Streams 0-7 implemented. Applies to INTCTL and INTSTS. */
207
208	#define HDA_REG_INTSTS 13 /* 0x24 */
209	#define HDA_RMX_INTSTS 10
210	#define HDA_INTSTS_GIS RT_BIT(31) /* Global Interrupt Status */
211	#define HDA_INTSTS_CIS RT_BIT(30) /* Controller Interrupt Status */
212
213	#define HDA_REG_WALCLK 14 /* 0x30 */
214	/* NB: HDA_RMX_WALCLK is not defined because the register is not stored in memory. */
215
216	/**
217	* @note The HDA specification defines a SSYNC register at offset 0x38. The ICH6/ICH9
218	* datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches the datasheet.
219	* See also https://mailman.alsa-project.org/pipermail/alsa-devel/2011-March/037819.html
220	*/
221	#define HDA_REG_SSYNC 15 /* 0x34 */
222	#define HDA_RMX_SSYNC 12
223
224	#define HDA_REG_NEW_SSYNC 16 /* 0x38 */
225	#define HDA_RMX_NEW_SSYNC HDA_RMX_SSYNC
226
227	#define HDA_REG_CORBLBASE 17 /* 0x40 */
228	#define HDA_RMX_CORBLBASE 13
229
230	#define HDA_REG_CORBUBASE 18 /* 0x44 */
231	#define HDA_RMX_CORBUBASE 14
232
233	#define HDA_REG_CORBWP 19 /* 0x48 */
234	#define HDA_RMX_CORBWP 15
235
236	#define HDA_REG_CORBRP 20 /* 0x4A */
237	#define HDA_RMX_CORBRP 16
238	#define HDA_CORBRP_RST RT_BIT(15) /* CORB Read Pointer Reset */
239
240	#define HDA_REG_CORBCTL 21 /* 0x4C */
241	#define HDA_RMX_CORBCTL 17
242	#define HDA_CORBCTL_DMA RT_BIT(1) /* Enable CORB DMA Engine */
243	#define HDA_CORBCTL_CMEIE RT_BIT(0) /* CORB Memory Error Interrupt Enable */
244
245	#define HDA_REG_CORBSTS 22 /* 0x4D */
246	#define HDA_RMX_CORBSTS 18
247
248	#define HDA_REG_CORBSIZE 23 /* 0x4E */
249	#define HDA_RMX_CORBSIZE 19
250	#define HDA_CORBSIZE_SZ_CAP 0xF0
251	#define HDA_CORBSIZE_SZ 0x3
252
253	/** Number of CORB buffer entries. */
254	#define HDA_CORB_SIZE 256
255	/** CORB element size (in bytes). */
256	#define HDA_CORB_ELEMENT_SIZE 4
257	/** Number of RIRB buffer entries. */
258	#define HDA_RIRB_SIZE 256
259	/** RIRB element size (in bytes). */
260	#define HDA_RIRB_ELEMENT_SIZE 8
261
262	#define HDA_REG_RIRBLBASE 24 /* 0x50 */
263	#define HDA_RMX_RIRBLBASE 20
264
265	#define HDA_REG_RIRBUBASE 25 /* 0x54 */
266	#define HDA_RMX_RIRBUBASE 21
267
268	#define HDA_REG_RIRBWP 26 /* 0x58 */
269	#define HDA_RMX_RIRBWP 22
270	#define HDA_RIRBWP_RST RT_BIT(15) /* RIRB Write Pointer Reset */
271
272	#define HDA_REG_RINTCNT 27 /* 0x5A */
273	#define HDA_RMX_RINTCNT 23
274
275	/** Maximum number of Response Interrupts. */
276	#define HDA_MAX_RINTCNT 256
277
278	#define HDA_REG_RIRBCTL 28 /* 0x5C */
279	#define HDA_RMX_RIRBCTL 24
280	#define HDA_RIRBCTL_ROIC RT_BIT(2) /* Response Overrun Interrupt Control */
281	#define HDA_RIRBCTL_RDMAEN RT_BIT(1) /* RIRB DMA Enable */
282	#define HDA_RIRBCTL_RINTCTL RT_BIT(0) /* Response Interrupt Control */
283
284	#define HDA_REG_RIRBSTS 29 /* 0x5D */
285	#define HDA_RMX_RIRBSTS 25
286	#define HDA_RIRBSTS_RIRBOIS RT_BIT(2) /* Response Overrun Interrupt Status */
287	#define HDA_RIRBSTS_RINTFL RT_BIT(0) /* Response Interrupt Flag */
288
289	#define HDA_REG_RIRBSIZE 30 /* 0x5E */
290	#define HDA_RMX_RIRBSIZE 26
291
292	#define HDA_REG_IC 31 /* 0x60 */
293	#define HDA_RMX_IC 27
294
295	#define HDA_REG_IR 32 /* 0x64 */
296	#define HDA_RMX_IR 28
297
298	#define HDA_REG_IRS 33 /* 0x68 */
299	#define HDA_RMX_IRS 29
300	#define HDA_IRS_IRV RT_BIT(1) /* Immediate Result Valid */
301	#define HDA_IRS_ICB RT_BIT(0) /* Immediate Command Busy */
302
303	#define HDA_REG_DPLBASE 34 /* 0x70 */
304	#define HDA_RMX_DPLBASE 30
305
306	#define HDA_REG_DPUBASE 35 /* 0x74 */
307	#define HDA_RMX_DPUBASE 31
308
309	#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
310
311	#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
312	#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
313	/** @note sdnum here _MUST_ be stream reg number [0,7]. */
314	#if defined(VBOX_STRICT) && defined(VBOX_HDA_CAN_ACCESS_REG_MAP)
315	# define HDA_STREAM_REG(pThis, name, sdnum) (*hdaStrictStreamRegAccessor((pThis), HDA_REG_SD0##name, HDA_RMX_SD0##name, (sdnum)))
316	#else
317	# define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_BY_IDX((pThis), HDA_RMX_SD0##name + (sdnum) * 10))
318	#endif
319
320	#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
321	#define HDA_SD_TO_REG(a_Name, uSD) (HDA_STREAM_REG_DEF(a_Name, 0) + (uSD) * 10)
322
323	/** @todo Condense marcos! */
324
325	#define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80; other streams offset by 0x20 */
326	#define HDA_RMX_SD0CTL 32
327	#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
328	#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
329	#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
330	#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
331	#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
332	#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
333	#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
334
335	#define HDA_SDCTL_NUM_MASK 0xF
336	#define HDA_SDCTL_NUM_SHIFT 20
337	#define HDA_SDCTL_DIR RT_BIT(19) /* Direction (Bidirectional streams only!) */
338	#define HDA_SDCTL_TP RT_BIT(18) /* Traffic Priority (PCI Express) */
339	#define HDA_SDCTL_STRIPE_MASK 0x3
340	#define HDA_SDCTL_STRIPE_SHIFT 16
341	#define HDA_SDCTL_DEIE RT_BIT(4) /* Descriptor Error Interrupt Enable */
342	#define HDA_SDCTL_FEIE RT_BIT(3) /* FIFO Error Interrupt Enable */
343	#define HDA_SDCTL_IOCE RT_BIT(2) /* Interrupt On Completion Enable */
344	#define HDA_SDCTL_RUN RT_BIT(1) /* Stream Run */
345	#define HDA_SDCTL_SRST RT_BIT(0) /* Stream Reset */
346
347	#define HDA_REG_SD0STS (HDA_NUM_GENERAL_REGS + 1) /* 0x83; other streams offset by 0x20 */
348	#define HDA_RMX_SD0STS 33
349	#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
350	#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
351	#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
352	#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
353	#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
354	#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
355	#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
356
357	#define HDA_SDSTS_FIFORDY RT_BIT(5) /* FIFO Ready */
358	#define HDA_SDSTS_DESE RT_BIT(4) /* Descriptor Error */
359	#define HDA_SDSTS_FIFOE RT_BIT(3) /* FIFO Error */
360	#define HDA_SDSTS_BCIS RT_BIT(2) /* Buffer Completion Interrupt Status */
361
362	#define HDA_REG_SD0LPIB (HDA_NUM_GENERAL_REGS + 2) /* 0x84; other streams offset by 0x20 */
363	#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
364	#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
365	#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
366	#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
367	#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
368	#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
369	#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
370	#define HDA_RMX_SD0LPIB 34
371	#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
372	#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
373	#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
374	#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
375	#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
376	#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
377	#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
378
379	#define HDA_REG_SD0CBL (HDA_NUM_GENERAL_REGS + 3) /* 0x88; other streams offset by 0x20 */
380	#define HDA_RMX_SD0CBL 35
381	#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
382	#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
383	#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
384	#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
385	#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
386	#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
387	#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
388
389	#define HDA_REG_SD0LVI (HDA_NUM_GENERAL_REGS + 4) /* 0x8C; other streams offset by 0x20 */
390	#define HDA_RMX_SD0LVI 36
391	#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
392	#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
393	#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
394	#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
395	#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
396	#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
397	#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
398
399	#define HDA_REG_SD0FIFOW (HDA_NUM_GENERAL_REGS + 5) /* 0x8E; other streams offset by 0x20 */
400	#define HDA_RMX_SD0FIFOW 37
401	#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
402	#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
403	#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
404	#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
405	#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
406	#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
407	#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
408
409	/*
410	* ICH6 datasheet defined limits for FIFOW values (18.2.38).
411	*/
412	#define HDA_SDFIFOW_8B 0x2
413	#define HDA_SDFIFOW_16B 0x3
414	#define HDA_SDFIFOW_32B 0x4
415
416	#define HDA_REG_SD0FIFOS (HDA_NUM_GENERAL_REGS + 6) /* 0x90; other streams offset by 0x20 */
417	#define HDA_RMX_SD0FIFOS 38
418	#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
419	#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
420	#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
421	#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
422	#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
423	#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
424	#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
425
426	/* The ICH6 datasheet defines limits for FIFOS registers (18.2.39).
427	Formula: size - 1
428	Other values not listed are not supported. */
429
430	#define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
431	#define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
432
433	#define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
434	#define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
435	#define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
436	#define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
437	#define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
438	#define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
439
440	#define HDA_REG_SD0FMT (HDA_NUM_GENERAL_REGS + 7) /* 0x92; other streams offset by 0x20 */
441	#define HDA_RMX_SD0FMT 39
442	#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
443	#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
444	#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
445	#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
446	#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
447	#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
448	#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
449
450	#define HDA_REG_SD0BDPL (HDA_NUM_GENERAL_REGS + 8) /* 0x98; other streams offset by 0x20 */
451	#define HDA_RMX_SD0BDPL 40
452	#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
453	#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
454	#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
455	#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
456	#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
457	#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
458	#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
459
460	#define HDA_REG_SD0BDPU (HDA_NUM_GENERAL_REGS + 9) /* 0x9C; other streams offset by 0x20 */
461	#define HDA_RMX_SD0BDPU 41
462	#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
463	#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
464	#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
465	#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
466	#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
467	#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
468	#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
469
470	#define HDA_CODEC_CAD_SHIFT 28
471	/** Encodes the (required) LUN into a codec command. */
472	#define HDA_CODEC_CMD(cmd, lun) ((cmd) \| (lun << HDA_CODEC_CAD_SHIFT))
473
474	#define HDA_SDFMT_NON_PCM_SHIFT 15
475	#define HDA_SDFMT_NON_PCM_MASK 0x1
476	#define HDA_SDFMT_BASE_RATE_SHIFT 14
477	#define HDA_SDFMT_BASE_RATE_MASK 0x1
478	#define HDA_SDFMT_MULT_SHIFT 11
479	#define HDA_SDFMT_MULT_MASK 0x7
480	#define HDA_SDFMT_DIV_SHIFT 8
481	#define HDA_SDFMT_DIV_MASK 0x7
482	#define HDA_SDFMT_BITS_SHIFT 4
483	#define HDA_SDFMT_BITS_MASK 0x7
484	#define HDA_SDFMT_CHANNELS_MASK 0xF
485
486	#define HDA_SDFMT_TYPE RT_BIT(15)
487	#define HDA_SDFMT_TYPE_PCM (0)
488	#define HDA_SDFMT_TYPE_NON_PCM (1)
489
490	#define HDA_SDFMT_BASE RT_BIT(14)
491	#define HDA_SDFMT_BASE_48KHZ (0)
492	#define HDA_SDFMT_BASE_44KHZ (1)
493
494	#define HDA_SDFMT_MULT_1X (0)
495	#define HDA_SDFMT_MULT_2X (1)
496	#define HDA_SDFMT_MULT_3X (2)
497	#define HDA_SDFMT_MULT_4X (3)
498
499	#define HDA_SDFMT_DIV_1X (0)
500	#define HDA_SDFMT_DIV_2X (1)
501	#define HDA_SDFMT_DIV_3X (2)
502	#define HDA_SDFMT_DIV_4X (3)
503	#define HDA_SDFMT_DIV_5X (4)
504	#define HDA_SDFMT_DIV_6X (5)
505	#define HDA_SDFMT_DIV_7X (6)
506	#define HDA_SDFMT_DIV_8X (7)
507
508	#define HDA_SDFMT_8_BIT (0)
509	#define HDA_SDFMT_16_BIT (1)
510	#define HDA_SDFMT_20_BIT (2)
511	#define HDA_SDFMT_24_BIT (3)
512	#define HDA_SDFMT_32_BIT (4)
513
514	#define HDA_SDFMT_CHAN_MONO (0)
515	#define HDA_SDFMT_CHAN_STEREO (1)
516
517	/** Emits a SDnFMT register format.
518	* Also being used in the codec's converter format. */
519	#define HDA_SDFMT_MAKE(_afNonPCM, _aBaseRate, _aMult, _aDiv, _aBits, _aChan) \
520	( (((_afNonPCM) & HDA_SDFMT_NON_PCM_MASK) << HDA_SDFMT_NON_PCM_SHIFT) \
521	\| (((_aBaseRate) & HDA_SDFMT_BASE_RATE_MASK) << HDA_SDFMT_BASE_RATE_SHIFT) \
522	\| (((_aMult) & HDA_SDFMT_MULT_MASK) << HDA_SDFMT_MULT_SHIFT) \
523	\| (((_aDiv) & HDA_SDFMT_DIV_MASK) << HDA_SDFMT_DIV_SHIFT) \
524	\| (((_aBits) & HDA_SDFMT_BITS_MASK) << HDA_SDFMT_BITS_SHIFT) \
525	\| ( (_aChan) & HDA_SDFMT_CHANNELS_MASK))
526
527
528	/* Post stream registers: */
529	#define HDA_REG_MLCH (HDA_NUM_GENERAL_REGS + HDA_NUM_STREAM_REGS) /* 0xc00 */
530	#define HDA_RMX_MLCH 115
531	#define HDA_REG_MLCD (HDA_REG_MLCH + 1) /* 0xc04 */
532	#define HDA_RMX_MLCD 116
533
534	/* Registers added/specific-to skylake/broxton: */
535	#define HDA_SD_NUM_FROM_SKYLAKE_REG(a_Name, a_iMap) (((a_iMap) - HDA_STREAM_REG_DEF(a_Name, 0)) / 2)
536
537	#define HDA_REG_SD0DPIB (HDA_REG_MLCD + 1) /* 0x1084 */
538	#define HDA_REG_SD1DPIB (HDA_REG_SD0DPIB + 1*2)
539	#define HDA_REG_SD2DPIB (HDA_REG_SD0DPIB + 2*2)
540	#define HDA_REG_SD3DPIB (HDA_REG_SD0DPIB + 3*2)
541	#define HDA_REG_SD4DPIB (HDA_REG_SD0DPIB + 4*2)
542	#define HDA_REG_SD5DPIB (HDA_REG_SD0DPIB + 5*2)
543	#define HDA_REG_SD6DPIB (HDA_REG_SD0DPIB + 6*2)
544	#define HDA_REG_SD7DPIB (HDA_REG_SD0DPIB + 7*2)
545
546	#define HDA_RMX_SD0DPIB HDA_RMX_SD0LPIB
547	#define HDA_RMX_SD1DPIB HDA_RMX_SD1LPIB
548	#define HDA_RMX_SD2DPIB HDA_RMX_SD2LPIB
549	#define HDA_RMX_SD3DPIB HDA_RMX_SD3LPIB
550	#define HDA_RMX_SD4DPIB HDA_RMX_SD4LPIB
551	#define HDA_RMX_SD5DPIB HDA_RMX_SD5LPIB
552	#define HDA_RMX_SD6DPIB HDA_RMX_SD6LPIB
553	#define HDA_RMX_SD7DPIB HDA_RMX_SD7LPIB
554
555	#define HDA_REG_SD0EFIFOS (HDA_REG_SD0DPIB + 1) /* 0x1094 */
556	#define HDA_REG_SD1EFIFOS (HDA_REG_SD0EFIFOS + 1*2)
557	#define HDA_REG_SD2EFIFOS (HDA_REG_SD0EFIFOS + 2*2)
558	#define HDA_REG_SD3EFIFOS (HDA_REG_SD0EFIFOS + 3*2)
559	#define HDA_REG_SD4EFIFOS (HDA_REG_SD0EFIFOS + 4*2)
560	#define HDA_REG_SD5EFIFOS (HDA_REG_SD0EFIFOS + 5*2)
561	#define HDA_REG_SD6EFIFOS (HDA_REG_SD0EFIFOS + 6*2)
562	#define HDA_REG_SD7EFIFOS (HDA_REG_SD0EFIFOS + 7*2)
563
564	#define HDA_RMX_SD0EFIFOS 117
565	#define HDA_RMX_SD1EFIFOS (HDA_RMX_SD0EFIFOS + 1)
566	#define HDA_RMX_SD2EFIFOS (HDA_RMX_SD0EFIFOS + 2)
567	#define HDA_RMX_SD3EFIFOS (HDA_RMX_SD0EFIFOS + 3)
568	#define HDA_RMX_SD4EFIFOS (HDA_RMX_SD0EFIFOS + 4)
569	#define HDA_RMX_SD5EFIFOS (HDA_RMX_SD0EFIFOS + 5)
570	#define HDA_RMX_SD6EFIFOS (HDA_RMX_SD0EFIFOS + 6)
571	#define HDA_RMX_SD7EFIFOS (HDA_RMX_SD0EFIFOS + 7)
572
573	/** @} / / grp_hda_regs */
574
575
576	/**
577	* Buffer descriptor list entry (BDLE).
578	*
579	* See 3.6.3 in HDA specs rev 1.0a (2010-06-17).
580	*/
581	typedef struct HDABDLEDESC
582	{
583	/** Starting address of the actual buffer. Must be 128-bit aligned. */
584	uint64_t u64BufAddr;
585	/** Size of the actual buffer (in bytes). */
586	uint32_t u32BufSize;
587	/** HDA_BDLE_F_XXX.
588	*
589	* Bit 0: IOC - Interrupt on completion / HDA_BDLE_F_IOC.
590	* The controller will generate an interrupt when the last byte of the buffer
591	* has been fetched by the DMA engine.
592	*
593	* Bits 31:1 are reserved for further use and must be 0. */
594	uint32_t fFlags;
595	} HDABDLEDESC, *PHDABDLEDESC;
596	AssertCompileSize(HDABDLEDESC, 16); /* Always 16 byte. Also must be aligned on 128-byte boundary. */
597
598	/** Interrupt on completion (IOC) flag. */
599	#define HDA_BDLE_F_IOC RT_BIT(0)
600
601
602	/**
603	* HDA mixer sink definition (ring-3).
604	*
605	* Its purpose is to know which audio mixer sink is bound to which SDn
606	* (SDI/SDO) device stream.
607	*
608	* This is needed in order to handle interleaved streams (that is, multiple
609	* channels in one stream) or non-interleaved streams (each channel has a
610	* dedicated stream).
611	*
612	* This is only known to the actual device emulation level.
613	*/
614	typedef struct HDAMIXERSINK
615	{
616	R3PTRTYPE(PHDASTREAM) pStreamShared;
617	R3PTRTYPE(PHDASTREAMR3) pStreamR3;
618	/** Pointer to the actual audio mixer sink. */
619	R3PTRTYPE(PAUDMIXSINK) pMixSink;
620	} HDAMIXERSINK;
621
622	/**
623	* Mapping a stream tag to an HDA stream (ring-3).
624	*/
625	typedef struct HDATAG
626	{
627	/** Own stream tag. */
628	uint8_t uTag;
629	uint8_t Padding[7];
630	/** Pointer to associated stream. */
631	R3PTRTYPE(PHDASTREAMR3) pStreamR3;
632	} HDATAG;
633	/** Pointer to a HDA stream tag mapping. */
634	typedef HDATAG *PHDATAG;
635
636	/**
637	* Shared ICH Intel HD audio controller state.
638	*/
639	typedef struct HDASTATE
640	{
641	/** Critical section protecting the HDA state. */
642	PDMCRITSECT CritSect;
643	/** Internal stream states (aligned on 64 byte boundrary). */
644	HDASTREAM aStreams[HDA_MAX_STREAMS];
645	/** The HDA's register set. */
646	uint32_t au32Regs[HDA_NUM_REGS];
647	/** CORB buffer base address. */
648	uint64_t u64CORBBase;
649	/** RIRB buffer base address. */
650	uint64_t u64RIRBBase;
651	/** DMA base address.
652	* Made out of DPLBASE + DPUBASE (3.3.32 + 3.3.33). */
653	uint64_t u64DPBase;
654	/** Size in bytes of CORB buffer (#au32CorbBuf). */
655	uint32_t cbCorbBuf;
656	/** Size in bytes of RIRB buffer (#au64RirbBuf). */
657	uint32_t cbRirbBuf;
658	/** Response Interrupt Count (RINTCNT). */
659	uint16_t u16RespIntCnt;
660	/** DMA position buffer enable bit. */
661	bool fDMAPosition;
662	/** Current IRQ level. */
663	uint8_t u8IRQL;
664	/** Config: Internal input DMA buffer size override, specified in milliseconds.
665	* Zero means default size according to buffer and stream config.
666	* @sa BufSizeInMs config value. */
667	uint16_t cMsCircBufIn;
668	/** Config: Internal output DMA buffer size override, specified in milliseconds.
669	* Zero means default size according to buffer and stream config.
670	* @sa BufSizeOutMs config value. */
671	uint16_t cMsCircBufOut;
672	/** The start time of the wall clock (WALCLK), measured on the virtual sync clock. */
673	uint64_t tsWalClkStart;
674	/** CORB DMA task handle.
675	* We use this when there is stuff we cannot handle in ring-0. */
676	PDMTASKHANDLE hCorbDmaTask;
677	/** The CORB buffer. */
678	uint32_t au32CorbBuf[HDA_CORB_SIZE];
679	/** Pointer to RIRB buffer. */
680	uint64_t au64RirbBuf[HDA_RIRB_SIZE];
681
682	/** PCI Region \#0: 16KB of MMIO stuff. */
683	IOMMMIOHANDLE hMmio;
684
685	#ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
686	STAMCOUNTER StatAccessDmaOutput;
687	STAMCOUNTER StatAccessDmaOutputToR3;
688	#endif
689	#ifdef VBOX_WITH_STATISTICS
690	STAMPROFILE StatIn;
691	STAMPROFILE StatOut;
692	STAMCOUNTER StatBytesRead;
693	STAMCOUNTER StatBytesWritten;
694
695	/** @name Register statistics.
696	* The array members run parallel to g_aHdaRegMap.
697	* @{ */
698	STAMCOUNTER aStatRegReads[HDA_NUM_REGS];
699	STAMCOUNTER aStatRegReadsToR3[HDA_NUM_REGS];
700	STAMCOUNTER aStatRegWrites[HDA_NUM_REGS];
701	STAMCOUNTER aStatRegWritesToR3[HDA_NUM_REGS];
702	STAMCOUNTER StatRegMultiReadsRZ;
703	STAMCOUNTER StatRegMultiReadsR3;
704	STAMCOUNTER StatRegMultiWritesRZ;
705	STAMCOUNTER StatRegMultiWritesR3;
706	STAMCOUNTER StatRegSubWriteRZ;
707	STAMCOUNTER StatRegSubWriteR3;
708	STAMCOUNTER StatRegUnknownReads;
709	STAMCOUNTER StatRegUnknownWrites;
710	STAMCOUNTER StatRegWritesBlockedByReset;
711	STAMCOUNTER StatRegWritesBlockedByRun;
712	/** @} */
713	#endif
714
715	#ifdef DEBUG
716	/** Debug stuff.
717	* @todo Make STAM values out some of this? */
718	struct
719	{
720	# if 0 /* unused */
721	/** Timestamp (in ns) of the last timer callback (hdaTimer).
722	* Used to calculate the time actually elapsed between two timer callbacks. */
723	uint64_t tsTimerLastCalledNs;
724	# endif
725	/** IRQ debugging information. */
726	struct
727	{
728	/** Timestamp (in ns) of last processed (asserted / deasserted) IRQ. */
729	uint64_t tsProcessedLastNs;
730	/** Timestamp (in ns) of last asserted IRQ. */
731	uint64_t tsAssertedNs;
732	# if 0 /* unused */
733	/** How many IRQs have been asserted already. */
734	uint64_t cAsserted;
735	/** Accumulated elapsed time (in ns) of all IRQ being asserted. */
736	uint64_t tsAssertedTotalNs;
737	/** Timestamp (in ns) of last deasserted IRQ. */
738	uint64_t tsDeassertedNs;
739	/** How many IRQs have been deasserted already. */
740	uint64_t cDeasserted;
741	/** Accumulated elapsed time (in ns) of all IRQ being deasserted. */
742	uint64_t tsDeassertedTotalNs;
743	# endif
744	} IRQ;
745	} Dbg;
746	#endif
747	/** This is for checking that the build was correctly configured in all contexts.
748	* This is set to HDASTATE_ALIGNMENT_CHECK_MAGIC. */
749	uint64_t uAlignmentCheckMagic;
750	} HDASTATE;
751	AssertCompileMemberAlignment(HDASTATE, aStreams, 64);
752	/** Pointer to a shared HDA device state. */
753	typedef HDASTATE *PHDASTATE;
754
755	/** Value for HDASTATE:uAlignmentCheckMagic. */
756	#define HDASTATE_ALIGNMENT_CHECK_MAGIC UINT64_C(0x1298afb75893e059)
757
758	/**
759	* Ring-0 ICH Intel HD audio controller state.
760	*/
761	typedef struct HDASTATER0
762	{
763	# if 0 /* Codec is not yet kosher enough for ring-0. @bugref{9890c64} */
764	/** Pointer to HDA codec to use. */
765	HDACODECR0 Codec;
766	# else
767	uint32_t u32Dummy;
768	# endif
769	} HDASTATER0;
770	/** Pointer to a ring-0 HDA device state. */
771	typedef HDASTATER0 *PHDASTATER0;
772
773	/**
774	* Ring-3 ICH Intel HD audio controller state.
775	*/
776	typedef struct HDASTATER3
777	{
778	/** Internal stream states. */
779	HDASTREAMR3 aStreams[HDA_MAX_STREAMS];
780	/** Mapping table between stream tags and stream states. */
781	HDATAG aTags[HDA_MAX_TAGS];
782	/** R3 Pointer to the device instance. */
783	PPDMDEVINSR3 pDevIns;
784	/** The base interface for LUN\#0. */
785	PDMIBASE IBase;
786	/** List of associated LUN drivers (HDADRIVER). */
787	RTLISTANCHORR3 lstDrv;
788	/** The device' software mixer. */
789	R3PTRTYPE(PAUDIOMIXER) pMixer;
790	/** HDA sink for (front) output. */
791	HDAMIXERSINK SinkFront;
792	#ifdef VBOX_WITH_AUDIO_HDA_51_SURROUND
793	/** HDA sink for center / LFE output. */
794	HDAMIXERSINK SinkCenterLFE;
795	/** HDA sink for rear output. */
796	HDAMIXERSINK SinkRear;
797	#endif
798	/** HDA mixer sink for line input. */
799	HDAMIXERSINK SinkLineIn;
800	#ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
801	/** Audio mixer sink for microphone input. */
802	HDAMIXERSINK SinkMicIn;
803	#endif
804	/** Debug stuff. */
805	struct
806	{
807	/** Whether debugging is enabled or not. */
808	bool fEnabled;
809	/** Path where to dump the debug output to.
810	* Can be NULL, in which the system's temporary directory will be used then. */
811	R3PTRTYPE(char *) pszOutPath;
812	} Dbg;
813	/** Align the codec state on a cache line. */
814	uint64_t au64Padding[3];
815	/** The HDA codec state. */
816	HDACODECR3 Codec;
817	} HDASTATER3;
818	AssertCompileMemberAlignment(HDASTATER3, Codec, 64);
819
820
821	/** Pointer to the context specific HDA state (HDASTATER3 or HDASTATER0). */
822	typedef CTX_SUFF(PHDASTATE) PHDASTATECC;
823
824
825	/** @def HDA_PROCESS_INTERRUPT
826	* Wrapper around hdaProcessInterrupt that supplies the source function name
827	* string in logging builds. */
828	#if defined(LOG_ENABLED) \|\| defined(DOXYGEN_RUNNING)
829	void hdaProcessInterrupt(PPDMDEVINS pDevIns, PHDASTATE pThis, const char *pszSource);
830	# define HDA_PROCESS_INTERRUPT(a_pDevIns, a_pThis) hdaProcessInterrupt((a_pDevIns), (a_pThis), __FUNCTION__)
831	#else
832	void hdaProcessInterrupt(PPDMDEVINS pDevIns, PHDASTATE pThis);
833	# define HDA_PROCESS_INTERRUPT(a_pDevIns, a_pThis) hdaProcessInterrupt((a_pDevIns), (a_pThis))
834	#endif
835
836	/**
837	* Returns the audio direction of a specified stream descriptor.
838	*
839	* The register layout specifies that input streams (SDI) come first,
840	* followed by the output streams (SDO). So every stream ID below HDA_MAX_SDI
841	* is an input stream, whereas everything >= HDA_MAX_SDI is an output stream.
842	*
843	* @note SDnFMT register does not provide that information, so we have to judge
844	* for ourselves.
845	*
846	* @return Audio direction.
847	* @param uSD The stream number.
848	*/
849	DECLINLINE(PDMAUDIODIR) hdaGetDirFromSD(uint8_t uSD)
850	{
851	if (uSD < HDA_MAX_SDI)
852	return PDMAUDIODIR_IN;
853	AssertReturn(uSD < HDA_MAX_STREAMS, PDMAUDIODIR_UNKNOWN);
854	return PDMAUDIODIR_OUT;
855	}
856
857	/* Used by hdaR3StreamSetUp: */
858	uint8_t hdaSDFIFOWToBytes(uint16_t u16RegFIFOW);
859
860	#if defined(VBOX_STRICT) && defined(VBOX_HDA_CAN_ACCESS_REG_MAP)
861	/* Only in DevHda.cpp: */
862	DECLINLINE(uint32_t *) hdaStrictRegAccessor(PHDASTATE pThis, uint32_t idxMap, uint32_t idxReg);
863	DECLINLINE(uint32_t *) hdaStrictStreamRegAccessor(PHDASTATE pThis, uint32_t idxMap0, uint32_t idxReg0, size_t idxStream);
864	#endif /* VBOX_STRICT && VBOX_HDA_CAN_ACCESS_REG_MAP */
865
866
867	/** @name HDA device functions used by the codec.
868	* @{ */
869	DECLHIDDEN(int) hdaR3MixerAddStream(PHDACODECR3 pCodec, PDMAUDIOMIXERCTL enmMixerCtl, PCPDMAUDIOSTREAMCFG pCfg);
870	DECLHIDDEN(int) hdaR3MixerRemoveStream(PHDACODECR3 pCodec, PDMAUDIOMIXERCTL enmMixerCtl, bool fImmediate);
871	DECLHIDDEN(int) hdaR3MixerControl(PHDACODECR3 pCodec, PDMAUDIOMIXERCTL enmMixerCtl, uint8_t uSD, uint8_t uChannel);
872	DECLHIDDEN(int) hdaR3MixerSetVolume(PHDACODECR3 pCodec, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOVOLUME pVol);
873	/** @} */
874
875
876	/** @name Saved state versions for the HDA device
877	* @{ */
878	/** The current staved state version.
879	* @note Only for the registration call. Never used for tests. */
880	#define HDA_SAVED_STATE_VERSION HDA_SAVED_STATE_WITHOUT_PERIOD
881
882	/** Removed period and redefined wall clock. */
883	#define HDA_SAVED_STATE_WITHOUT_PERIOD 8
884	/** Added (Controller): Current wall clock value (this independent from WALCLK register value).
885	* Added (Controller): Current IRQ level.
886	* Added (Per stream): Ring buffer. This is optional and can be skipped if (not) needed.
887	* Added (Per stream): Struct g_aSSMStreamStateFields7.
888	* Added (Per stream): Struct g_aSSMStreamPeriodFields7.
889	* Added (Current BDLE per stream): Struct g_aSSMBDLEDescFields7.
890	* Added (Current BDLE per stream): Struct g_aSSMBDLEStateFields7. */
891	#define HDA_SAVED_STATE_VERSION_7 7
892	/** Saves the current BDLE state.
893	* @since 5.0.14 (r104839) */
894	#define HDA_SAVED_STATE_VERSION_6 6
895	/** Introduced dynamic number of streams + stream identifiers for serialization.
896	* Bug: Did not save the BDLE states correctly.
897	* Those will be skipped on load then.
898	* @since 5.0.12 (r104520) */
899	#define HDA_SAVED_STATE_VERSION_5 5
900	/** Since this version the number of MMIO registers can be flexible. */
901	#define HDA_SAVED_STATE_VERSION_4 4
902	#define HDA_SAVED_STATE_VERSION_3 3
903	#define HDA_SAVED_STATE_VERSION_2 2
904	#define HDA_SAVED_STATE_VERSION_1 1
905	/** @} */
906
907	#endif /* !VBOX_INCLUDED_SRC_Audio_DevHda_h */
908

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source: vbox/trunk/src/VBox/Devices/Audio/DevHda.h@ 92348

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