DevHdaCodec.h@ 88466

Last change on this file since 88466 was 88235, checked in by vboxsync, 4 years ago
Audio: File header adjustments. bugref:9890
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1	/* $Id: DevHdaCodec.h 88235 2021-03-22 10:44:43Z vboxsync $ */
2	/** @file
3	* Intel HD Audio Controller Emulation - Codec, Sigmatel/IDT STAC9220.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	#ifndef VBOX_INCLUDED_SRC_Audio_DevHdaCodec_h
19	#define VBOX_INCLUDED_SRC_Audio_DevHdaCodec_h
20	#ifndef RT_WITHOUT_PRAGMA_ONCE
21	# pragma once
22	#endif
23
24	#include <iprt/list.h>
25
26	#include "AudioMixer.h"
27
28	/** Pointer to a shared HDA device state. */
29	typedef struct HDASTATE *PHDASTATE;
30	/** Pointer to a ring-3 HDA device state. */
31	typedef struct HDASTATER3 *PHDASTATER3;
32	/** The ICH HDA (Intel) common codec state. */
33	typedef struct HDACODEC *PHDACODEC;
34	/** The ICH HDA (Intel) ring-0 state. */
35	typedef struct HDACODECR0 *PHDACODECR0;
36	/** The ICH HDA (Intel) ring-3 state. */
37	typedef struct HDACODECR3 *PHDACODECR3;
38	/** The HDA host driver backend. */
39	typedef struct HDADRIVER *PHDADRIVER;
40
41	/**
42	* Enumeration specifying the codec type to use.
43	*/
44	typedef enum CODEC_TYPE
45	{
46	/** Invalid, do not use. */
47	CODEC_TYPE_INVALID = 0,
48	/** SigmaTel 9220 (922x). */
49	CODEC_TYPE_STAC9220,
50	/** Hack to blow the type up to 32-bit. */
51	CODEC_TYPE__32BIT_HACK = 0x7fffffff
52	} CODEC_TYPE;
53
54	/**
55	* Verb processor method.
56	*/
57	typedef DECLCALLBACKTYPE(int, FNHDACODECVERBPROCESSORR0,(PHDACODEC pThis, uint32_t cmd, uint64_t *pResp));
58	typedef FNHDACODECVERBPROCESSORR0 *PFNHDACODECVERBPROCESSORR0;
59	typedef DECLCALLBACKTYPE(int, FNHDACODECVERBPROCESSORR3,(PHDACODEC pThis, PHDACODECR3 pThisCC, uint32_t cmd, uint64_t *pResp));
60	typedef FNHDACODECVERBPROCESSORR3 *PFNHDACODECVERBPROCESSORR3;
61
62	/* PRM 5.3.1 */
63	/** Codec address mask. */
64	#define CODEC_CAD_MASK 0xF0000000
65	/** Codec address shift. */
66	#define CODEC_CAD_SHIFT 28
67	#define CODEC_DIRECT_MASK RT_BIT(27)
68	/** Node ID mask. */
69	#define CODEC_NID_MASK 0x07F00000
70	/** Node ID shift. */
71	#define CODEC_NID_SHIFT 20
72	#define CODEC_VERBDATA_MASK 0x000FFFFF
73	#define CODEC_VERB_4BIT_CMD 0x000FFFF0
74	#define CODEC_VERB_4BIT_DATA 0x0000000F
75	#define CODEC_VERB_8BIT_CMD 0x000FFF00
76	#define CODEC_VERB_8BIT_DATA 0x000000FF
77	#define CODEC_VERB_16BIT_CMD 0x000F0000
78	#define CODEC_VERB_16BIT_DATA 0x0000FFFF
79
80	#define CODEC_CAD(cmd) (((cmd) & CODEC_CAD_MASK) >> CODEC_CAD_SHIFT)
81	#define CODEC_DIRECT(cmd) ((cmd) & CODEC_DIRECT_MASK)
82	#define CODEC_NID(cmd) ((((cmd) & CODEC_NID_MASK)) >> CODEC_NID_SHIFT)
83	#define CODEC_VERBDATA(cmd) ((cmd) & CODEC_VERBDATA_MASK)
84	#define CODEC_VERB_CMD(cmd, mask, x) (((cmd) & (mask)) >> (x))
85	#define CODEC_VERB_CMD4(cmd) (CODEC_VERB_CMD((cmd), CODEC_VERB_4BIT_CMD, 4))
86	#define CODEC_VERB_CMD8(cmd) (CODEC_VERB_CMD((cmd), CODEC_VERB_8BIT_CMD, 8))
87	#define CODEC_VERB_CMD16(cmd) (CODEC_VERB_CMD((cmd), CODEC_VERB_16BIT_CMD, 16))
88	#define CODEC_VERB_PAYLOAD4(cmd) ((cmd) & CODEC_VERB_4BIT_DATA)
89	#define CODEC_VERB_PAYLOAD8(cmd) ((cmd) & CODEC_VERB_8BIT_DATA)
90	#define CODEC_VERB_PAYLOAD16(cmd) ((cmd) & CODEC_VERB_16BIT_DATA)
91
92	#define CODEC_VERB_GET_AMP_DIRECTION RT_BIT(15)
93	#define CODEC_VERB_GET_AMP_SIDE RT_BIT(13)
94	#define CODEC_VERB_GET_AMP_INDEX 0x7
95
96	/* HDA spec 7.3.3.7 NoteA */
97	#define CODEC_GET_AMP_DIRECTION(cmd) (((cmd) & CODEC_VERB_GET_AMP_DIRECTION) >> 15)
98	#define CODEC_GET_AMP_SIDE(cmd) (((cmd) & CODEC_VERB_GET_AMP_SIDE) >> 13)
99	#define CODEC_GET_AMP_INDEX(cmd) (CODEC_GET_AMP_DIRECTION(cmd) ? 0 : ((cmd) & CODEC_VERB_GET_AMP_INDEX))
100
101	/* HDA spec 7.3.3.7 NoteC */
102	#define CODEC_VERB_SET_AMP_OUT_DIRECTION RT_BIT(15)
103	#define CODEC_VERB_SET_AMP_IN_DIRECTION RT_BIT(14)
104	#define CODEC_VERB_SET_AMP_LEFT_SIDE RT_BIT(13)
105	#define CODEC_VERB_SET_AMP_RIGHT_SIDE RT_BIT(12)
106	#define CODEC_VERB_SET_AMP_INDEX (0x7 << 8)
107	#define CODEC_VERB_SET_AMP_MUTE RT_BIT(7)
108	/** Note: 7-bit value [6:0]. */
109	#define CODEC_VERB_SET_AMP_GAIN 0x7F
110
111	#define CODEC_SET_AMP_IS_OUT_DIRECTION(cmd) (((cmd) & CODEC_VERB_SET_AMP_OUT_DIRECTION) != 0)
112	#define CODEC_SET_AMP_IS_IN_DIRECTION(cmd) (((cmd) & CODEC_VERB_SET_AMP_IN_DIRECTION) != 0)
113	#define CODEC_SET_AMP_IS_LEFT_SIDE(cmd) (((cmd) & CODEC_VERB_SET_AMP_LEFT_SIDE) != 0)
114	#define CODEC_SET_AMP_IS_RIGHT_SIDE(cmd) (((cmd) & CODEC_VERB_SET_AMP_RIGHT_SIDE) != 0)
115	#define CODEC_SET_AMP_INDEX(cmd) (((cmd) & CODEC_VERB_SET_AMP_INDEX) >> 7)
116	#define CODEC_SET_AMP_MUTE(cmd) ((cmd) & CODEC_VERB_SET_AMP_MUTE)
117	#define CODEC_SET_AMP_GAIN(cmd) ((cmd) & CODEC_VERB_SET_AMP_GAIN)
118
119	/* HDA spec 7.3.3.1 defines layout of configuration registers/verbs (0xF00) */
120	/* VendorID (7.3.4.1) */
121	#define CODEC_MAKE_F00_00(vendorID, deviceID) (((vendorID) << 16) \| (deviceID))
122	#define CODEC_F00_00_VENDORID(f00_00) (((f00_00) >> 16) & 0xFFFF)
123	#define CODEC_F00_00_DEVICEID(f00_00) ((f00_00) & 0xFFFF)
124
125	/** RevisionID (7.3.4.2). */
126	#define CODEC_MAKE_F00_02(majRev, minRev, venFix, venProg, stepFix, stepProg) \
127	( (((majRev) & 0xF) << 20) \
128	\| (((minRev) & 0xF) << 16) \
129	\| (((venFix) & 0xF) << 12) \
130	\| (((venProg) & 0xF) << 8) \
131	\| (((stepFix) & 0xF) << 4) \
132	\| ((stepProg) & 0xF))
133
134	/** Subordinate node count (7.3.4.3). */
135	#define CODEC_MAKE_F00_04(startNodeNumber, totalNodeNumber) ((((startNodeNumber) & 0xFF) << 16)\|((totalNodeNumber) & 0xFF))
136	#define CODEC_F00_04_TO_START_NODE_NUMBER(f00_04) (((f00_04) >> 16) & 0xFF)
137	#define CODEC_F00_04_TO_NODE_COUNT(f00_04) ((f00_04) & 0xFF)
138	/*
139	* Function Group Type (7.3.4.4)
140	* 0 & [0x3-0x7f] are reserved types
141	* [0x80 - 0xff] are vendor defined function groups
142	*/
143	#define CODEC_MAKE_F00_05(UnSol, NodeType) (((UnSol) << 8)\|(NodeType))
144	#define CODEC_F00_05_UNSOL RT_BIT(8)
145	#define CODEC_F00_05_AFG (0x1)
146	#define CODEC_F00_05_MFG (0x2)
147	#define CODEC_F00_05_IS_UNSOL(f00_05) RT_BOOL((f00_05) & RT_BIT(8))
148	#define CODEC_F00_05_GROUP(f00_05) ((f00_05) & 0xff)
149	/* Audio Function Group capabilities (7.3.4.5). */
150	#define CODEC_MAKE_F00_08(BeepGen, InputDelay, OutputDelay) ((((BeepGen) & 0x1) << 16)\| (((InputDelay) & 0xF) << 8) \| ((OutputDelay) & 0xF))
151	#define CODEC_F00_08_BEEP_GEN(f00_08) ((f00_08) & RT_BIT(16)
152
153	/* Converter Stream, Channel (7.3.3.11). */
154	#define CODEC_F00_06_GET_STREAM_ID(cmd) (((cmd) >> 4) & 0x0F)
155	#define CODEC_F00_06_GET_CHANNEL_ID(cmd) (((cmd) & 0x0F))
156
157	/* Widget Capabilities (7.3.4.6). */
158	#define CODEC_MAKE_F00_09(type, delay, chan_ext) \
159	( (((type) & 0xF) << 20) \
160	\| (((delay) & 0xF) << 16) \
161	\| (((chan_ext) & 0xF) << 13))
162	/* note: types 0x8-0xe are reserved */
163	#define CODEC_F00_09_TYPE_AUDIO_OUTPUT (0x0)
164	#define CODEC_F00_09_TYPE_AUDIO_INPUT (0x1)
165	#define CODEC_F00_09_TYPE_AUDIO_MIXER (0x2)
166	#define CODEC_F00_09_TYPE_AUDIO_SELECTOR (0x3)
167	#define CODEC_F00_09_TYPE_PIN_COMPLEX (0x4)
168	#define CODEC_F00_09_TYPE_POWER_WIDGET (0x5)
169	#define CODEC_F00_09_TYPE_VOLUME_KNOB (0x6)
170	#define CODEC_F00_09_TYPE_BEEP_GEN (0x7)
171	#define CODEC_F00_09_TYPE_VENDOR_DEFINED (0xF)
172
173	#define CODEC_F00_09_CAP_CP RT_BIT(12)
174	#define CODEC_F00_09_CAP_L_R_SWAP RT_BIT(11)
175	#define CODEC_F00_09_CAP_POWER_CTRL RT_BIT(10)
176	#define CODEC_F00_09_CAP_DIGITAL RT_BIT(9)
177	#define CODEC_F00_09_CAP_CONNECTION_LIST RT_BIT(8)
178	#define CODEC_F00_09_CAP_UNSOL RT_BIT(7)
179	#define CODEC_F00_09_CAP_PROC_WIDGET RT_BIT(6)
180	#define CODEC_F00_09_CAP_STRIPE RT_BIT(5)
181	#define CODEC_F00_09_CAP_FMT_OVERRIDE RT_BIT(4)
182	#define CODEC_F00_09_CAP_AMP_FMT_OVERRIDE RT_BIT(3)
183	#define CODEC_F00_09_CAP_OUT_AMP_PRESENT RT_BIT(2)
184	#define CODEC_F00_09_CAP_IN_AMP_PRESENT RT_BIT(1)
185	#define CODEC_F00_09_CAP_STEREO RT_BIT(0)
186
187	#define CODEC_F00_09_TYPE(f00_09) (((f00_09) >> 20) & 0xF)
188
189	#define CODEC_F00_09_IS_CAP_CP(f00_09) RT_BOOL((f00_09) & RT_BIT(12))
190	#define CODEC_F00_09_IS_CAP_L_R_SWAP(f00_09) RT_BOOL((f00_09) & RT_BIT(11))
191	#define CODEC_F00_09_IS_CAP_POWER_CTRL(f00_09) RT_BOOL((f00_09) & RT_BIT(10))
192	#define CODEC_F00_09_IS_CAP_DIGITAL(f00_09) RT_BOOL((f00_09) & RT_BIT(9))
193	#define CODEC_F00_09_IS_CAP_CONNECTION_LIST(f00_09) RT_BOOL((f00_09) & RT_BIT(8))
194	#define CODEC_F00_09_IS_CAP_UNSOL(f00_09) RT_BOOL((f00_09) & RT_BIT(7))
195	#define CODEC_F00_09_IS_CAP_PROC_WIDGET(f00_09) RT_BOOL((f00_09) & RT_BIT(6))
196	#define CODEC_F00_09_IS_CAP_STRIPE(f00_09) RT_BOOL((f00_09) & RT_BIT(5))
197	#define CODEC_F00_09_IS_CAP_FMT_OVERRIDE(f00_09) RT_BOOL((f00_09) & RT_BIT(4))
198	#define CODEC_F00_09_IS_CAP_AMP_OVERRIDE(f00_09) RT_BOOL((f00_09) & RT_BIT(3))
199	#define CODEC_F00_09_IS_CAP_OUT_AMP_PRESENT(f00_09) RT_BOOL((f00_09) & RT_BIT(2))
200	#define CODEC_F00_09_IS_CAP_IN_AMP_PRESENT(f00_09) RT_BOOL((f00_09) & RT_BIT(1))
201	#define CODEC_F00_09_IS_CAP_LSB(f00_09) RT_BOOL((f00_09) & RT_BIT(0))
202
203	/* Supported PCM size, rates (7.3.4.7) */
204	#define CODEC_F00_0A_32_BIT RT_BIT(19)
205	#define CODEC_F00_0A_24_BIT RT_BIT(18)
206	#define CODEC_F00_0A_16_BIT RT_BIT(17)
207	#define CODEC_F00_0A_8_BIT RT_BIT(16)
208
209	#define CODEC_F00_0A_48KHZ_MULT_8X RT_BIT(11)
210	#define CODEC_F00_0A_48KHZ_MULT_4X RT_BIT(10)
211	#define CODEC_F00_0A_44_1KHZ_MULT_4X RT_BIT(9)
212	#define CODEC_F00_0A_48KHZ_MULT_2X RT_BIT(8)
213	#define CODEC_F00_0A_44_1KHZ_MULT_2X RT_BIT(7)
214	#define CODEC_F00_0A_48KHZ RT_BIT(6)
215	#define CODEC_F00_0A_44_1KHZ RT_BIT(5)
216	/* 2/3 * 48kHz */
217	#define CODEC_F00_0A_48KHZ_2_3X RT_BIT(4)
218	/* 1/2 * 44.1kHz */
219	#define CODEC_F00_0A_44_1KHZ_1_2X RT_BIT(3)
220	/* 1/3 * 48kHz */
221	#define CODEC_F00_0A_48KHZ_1_3X RT_BIT(2)
222	/* 1/4 * 44.1kHz */
223	#define CODEC_F00_0A_44_1KHZ_1_4X RT_BIT(1)
224	/* 1/6 * 48kHz */
225	#define CODEC_F00_0A_48KHZ_1_6X RT_BIT(0)
226
227	/* Supported streams formats (7.3.4.8) */
228	#define CODEC_F00_0B_AC3 RT_BIT(2)
229	#define CODEC_F00_0B_FLOAT32 RT_BIT(1)
230	#define CODEC_F00_0B_PCM RT_BIT(0)
231
232	/* Pin Capabilities (7.3.4.9)*/
233	#define CODEC_MAKE_F00_0C(vref_ctrl) (((vref_ctrl) & 0xFF) << 8)
234	#define CODEC_F00_0C_CAP_HBR RT_BIT(27)
235	#define CODEC_F00_0C_CAP_DP RT_BIT(24)
236	#define CODEC_F00_0C_CAP_EAPD RT_BIT(16)
237	#define CODEC_F00_0C_CAP_HDMI RT_BIT(7)
238	#define CODEC_F00_0C_CAP_BALANCED_IO RT_BIT(6)
239	#define CODEC_F00_0C_CAP_INPUT RT_BIT(5)
240	#define CODEC_F00_0C_CAP_OUTPUT RT_BIT(4)
241	#define CODEC_F00_0C_CAP_HEADPHONE_AMP RT_BIT(3)
242	#define CODEC_F00_0C_CAP_PRESENCE_DETECT RT_BIT(2)
243	#define CODEC_F00_0C_CAP_TRIGGER_REQUIRED RT_BIT(1)
244	#define CODEC_F00_0C_CAP_IMPENDANCE_SENSE RT_BIT(0)
245
246	#define CODEC_F00_0C_IS_CAP_HBR(f00_0c) ((f00_0c) & RT_BIT(27))
247	#define CODEC_F00_0C_IS_CAP_DP(f00_0c) ((f00_0c) & RT_BIT(24))
248	#define CODEC_F00_0C_IS_CAP_EAPD(f00_0c) ((f00_0c) & RT_BIT(16))
249	#define CODEC_F00_0C_IS_CAP_HDMI(f00_0c) ((f00_0c) & RT_BIT(7))
250	#define CODEC_F00_0C_IS_CAP_BALANCED_IO(f00_0c) ((f00_0c) & RT_BIT(6))
251	#define CODEC_F00_0C_IS_CAP_INPUT(f00_0c) ((f00_0c) & RT_BIT(5))
252	#define CODEC_F00_0C_IS_CAP_OUTPUT(f00_0c) ((f00_0c) & RT_BIT(4))
253	#define CODEC_F00_0C_IS_CAP_HP(f00_0c) ((f00_0c) & RT_BIT(3))
254	#define CODEC_F00_0C_IS_CAP_PRESENCE_DETECT(f00_0c) ((f00_0c) & RT_BIT(2))
255	#define CODEC_F00_0C_IS_CAP_TRIGGER_REQUIRED(f00_0c) ((f00_0c) & RT_BIT(1))
256	#define CODEC_F00_0C_IS_CAP_IMPENDANCE_SENSE(f00_0c) ((f00_0c) & RT_BIT(0))
257
258	/* Input Amplifier capabilities (7.3.4.10). */
259	#define CODEC_MAKE_F00_0D(mute_cap, step_size, num_steps, offset) \
260	( (((mute_cap) & UINT32_C(0x1)) << 31) \
261	\| (((step_size) & UINT32_C(0xFF)) << 16) \
262	\| (((num_steps) & UINT32_C(0xFF)) << 8) \
263	\| ((offset) & UINT32_C(0xFF)))
264
265	#define CODEC_F00_0D_CAP_MUTE RT_BIT(7)
266
267	#define CODEC_F00_0D_IS_CAP_MUTE(f00_0d) ( ( f00_0d) & RT_BIT(31))
268	#define CODEC_F00_0D_STEP_SIZE(f00_0d) ((( f00_0d) & (0x7F << 16)) >> 16)
269	#define CODEC_F00_0D_NUM_STEPS(f00_0d) ((((f00_0d) & (0x7F << 8)) >> 8) + 1)
270	#define CODEC_F00_0D_OFFSET(f00_0d) ( (f00_0d) & 0x7F)
271
272	/** Indicates that the amplifier can be muted. */
273	#define CODEC_AMP_CAP_MUTE 0x1
274	/** The amplifier's maximum number of steps. We want
275	* a ~90dB dynamic range, so 64 steps with 1.25dB each
276	* should do the trick.
277	*
278	* As we want to map our range to [0..128] values we can avoid
279	* multiplication and simply doing a shift later.
280	*
281	* Produces -96dB to +0dB.
282	* "0" indicates a step of 0.25dB, "127" indicates a step of 32dB.
283	*/
284	#define CODEC_AMP_NUM_STEPS 0x7F
285	/** The initial gain offset (and when doing a node reset). */
286	#define CODEC_AMP_OFF_INITIAL 0x7F
287	/** The amplifier's gain step size. */
288	#define CODEC_AMP_STEP_SIZE 0x2
289
290	/* Output Amplifier capabilities (7.3.4.10) */
291	#define CODEC_MAKE_F00_12 CODEC_MAKE_F00_0D
292
293	#define CODEC_F00_12_IS_CAP_MUTE(f00_12) CODEC_F00_0D_IS_CAP_MUTE(f00_12)
294	#define CODEC_F00_12_STEP_SIZE(f00_12) CODEC_F00_0D_STEP_SIZE(f00_12)
295	#define CODEC_F00_12_NUM_STEPS(f00_12) CODEC_F00_0D_NUM_STEPS(f00_12)
296	#define CODEC_F00_12_OFFSET(f00_12) CODEC_F00_0D_OFFSET(f00_12)
297
298	/* Connection list lenght (7.3.4.11). */
299	#define CODEC_MAKE_F00_0E(long_form, length) \
300	( (((long_form) & 0x1) << 7) \
301	\| ((length) & 0x7F))
302	/* Indicates short-form NIDs. */
303	#define CODEC_F00_0E_LIST_NID_SHORT 0
304	/* Indicates long-form NIDs. */
305	#define CODEC_F00_0E_LIST_NID_LONG 1
306	#define CODEC_F00_0E_IS_LONG(f00_0e) RT_BOOL((f00_0e) & RT_BIT(7))
307	#define CODEC_F00_0E_COUNT(f00_0e) ((f00_0e) & 0x7F)
308	/* Supported Power States (7.3.4.12) */
309	#define CODEC_F00_0F_EPSS RT_BIT(31)
310	#define CODEC_F00_0F_CLKSTOP RT_BIT(30)
311	#define CODEC_F00_0F_S3D3 RT_BIT(29)
312	#define CODEC_F00_0F_D3COLD RT_BIT(4)
313	#define CODEC_F00_0F_D3 RT_BIT(3)
314	#define CODEC_F00_0F_D2 RT_BIT(2)
315	#define CODEC_F00_0F_D1 RT_BIT(1)
316	#define CODEC_F00_0F_D0 RT_BIT(0)
317
318	/* Processing capabilities 7.3.4.13 */
319	#define CODEC_MAKE_F00_10(num, benign) ((((num) & 0xFF) << 8) \| ((benign) & 0x1))
320	#define CODEC_F00_10_NUM(f00_10) (((f00_10) & (0xFF << 8)) >> 8)
321	#define CODEC_F00_10_BENING(f00_10) ((f00_10) & 0x1)
322
323	/* GPIO count (7.3.4.14). */
324	#define CODEC_MAKE_F00_11(wake, unsol, numgpi, numgpo, numgpio) \
325	( (((wake) & UINT32_C(0x1)) << 31) \
326	\| (((unsol) & UINT32_C(0x1)) << 30) \
327	\| (((numgpi) & UINT32_C(0xFF)) << 16) \
328	\| (((numgpo) & UINT32_C(0xFF)) << 8) \
329	\| ((numgpio) & UINT32_C(0xFF)))
330
331	/* Processing States (7.3.3.4). */
332	#define CODEC_F03_OFF (0)
333	#define CODEC_F03_ON RT_BIT(0)
334	#define CODEC_F03_BENING RT_BIT(1)
335	/* Power States (7.3.3.10). */
336	#define CODEC_MAKE_F05(reset, stopok, error, act, set) \
337	( (((reset) & 0x1) << 10) \
338	\| (((stopok) & 0x1) << 9) \
339	\| (((error) & 0x1) << 8) \
340	\| (((act) & 0xF) << 4) \
341	\| ((set) & 0xF))
342	#define CODEC_F05_D3COLD (4)
343	#define CODEC_F05_D3 (3)
344	#define CODEC_F05_D2 (2)
345	#define CODEC_F05_D1 (1)
346	#define CODEC_F05_D0 (0)
347
348	#define CODEC_F05_IS_RESET(value) (((value) & RT_BIT(10)) != 0)
349	#define CODEC_F05_IS_STOPOK(value) (((value) & RT_BIT(9)) != 0)
350	#define CODEC_F05_IS_ERROR(value) (((value) & RT_BIT(8)) != 0)
351	#define CODEC_F05_ACT(value) (((value) & 0xF0) >> 4)
352	#define CODEC_F05_SET(value) (((value) & 0xF))
353
354	#define CODEC_F05_GE(p0, p1) ((p0) <= (p1))
355	#define CODEC_F05_LE(p0, p1) ((p0) >= (p1))
356
357	/* Converter Stream, Channel (7.3.3.11). */
358	#define CODEC_MAKE_F06(stream, channel) \
359	( (((stream) & 0xF) << 4) \
360	\| ((channel) & 0xF))
361	#define CODEC_F06_STREAM(value) ((value) & 0xF0)
362	#define CODEC_F06_CHANNEL(value) ((value) & 0xF)
363
364	/* Pin Widged Control (7.3.3.13). */
365	#define CODEC_F07_VREF_HIZ (0)
366	#define CODEC_F07_VREF_50 (0x1)
367	#define CODEC_F07_VREF_GROUND (0x2)
368	#define CODEC_F07_VREF_80 (0x4)
369	#define CODEC_F07_VREF_100 (0x5)
370	#define CODEC_F07_IN_ENABLE RT_BIT(5)
371	#define CODEC_F07_OUT_ENABLE RT_BIT(6)
372	#define CODEC_F07_OUT_H_ENABLE RT_BIT(7)
373
374	/* Volume Knob Control (7.3.3.29). */
375	#define CODEC_F0F_IS_DIRECT RT_BIT(7)
376	#define CODEC_F0F_VOLUME (0x7F)
377
378	/* Unsolicited enabled (7.3.3.14). */
379	#define CODEC_MAKE_F08(enable, tag) ((((enable) & 1) << 7) \| ((tag) & 0x3F))
380
381	/* Converter formats (7.3.3.8) and (3.7.1). */
382	/* This is the same format as SDnFMT. */
383	#define CODEC_MAKE_A HDA_SDFMT_MAKE
384
385	#define CODEC_A_TYPE HDA_SDFMT_TYPE
386	#define CODEC_A_TYPE_PCM HDA_SDFMT_TYPE_PCM
387	#define CODEC_A_TYPE_NON_PCM HDA_SDFMT_TYPE_NON_PCM
388
389	#define CODEC_A_BASE HDA_SDFMT_BASE
390	#define CODEC_A_BASE_48KHZ HDA_SDFMT_BASE_48KHZ
391	#define CODEC_A_BASE_44KHZ HDA_SDFMT_BASE_44KHZ
392
393	/* Pin Sense (7.3.3.15). */
394	#define CODEC_MAKE_F09_ANALOG(fPresent, impedance) \
395	( (((fPresent) & 0x1) << 31) \
396	\| (((impedance) & UINT32_C(0x7FFFFFFF))))
397	#define CODEC_F09_ANALOG_NA UINT32_C(0x7FFFFFFF)
398	#define CODEC_MAKE_F09_DIGITAL(fPresent, fELDValid) \
399	( (((fPresent) & UINT32_C(0x1)) << 31) \
400	\| (((fELDValid) & UINT32_C(0x1)) << 30))
401
402	#define CODEC_MAKE_F0C(lrswap, eapd, btl) ((((lrswap) & 1) << 2) \| (((eapd) & 1) << 1) \| ((btl) & 1))
403	#define CODEC_FOC_IS_LRSWAP(f0c) RT_BOOL((f0c) & RT_BIT(2))
404	#define CODEC_FOC_IS_EAPD(f0c) RT_BOOL((f0c) & RT_BIT(1))
405	#define CODEC_FOC_IS_BTL(f0c) RT_BOOL((f0c) & RT_BIT(0))
406	/* HDA spec 7.3.3.31 defines layout of configuration registers/verbs (0xF1C) */
407	/* Configuration's port connection */
408	#define CODEC_F1C_PORT_MASK (0x3)
409	#define CODEC_F1C_PORT_SHIFT (30)
410
411	#define CODEC_F1C_PORT_COMPLEX (0x0)
412	#define CODEC_F1C_PORT_NO_PHYS (0x1)
413	#define CODEC_F1C_PORT_FIXED (0x2)
414	#define CODEC_F1C_BOTH (0x3)
415
416	/* Configuration default: connection */
417	#define CODEC_F1C_PORT_MASK (0x3)
418	#define CODEC_F1C_PORT_SHIFT (30)
419
420	/* Connected to a jack (1/8", ATAPI, ...). */
421	#define CODEC_F1C_PORT_COMPLEX (0x0)
422	/* No physical connection. */
423	#define CODEC_F1C_PORT_NO_PHYS (0x1)
424	/* Fixed function device (integrated speaker, integrated mic, ...). */
425	#define CODEC_F1C_PORT_FIXED (0x2)
426	/* Both, a jack and an internal device are attached. */
427	#define CODEC_F1C_BOTH (0x3)
428
429	/* Configuration default: Location */
430	#define CODEC_F1C_LOCATION_MASK (0x3F)
431	#define CODEC_F1C_LOCATION_SHIFT (24)
432
433	/* [4:5] bits of location region means chassis attachment */
434	#define CODEC_F1C_LOCATION_PRIMARY_CHASSIS (0)
435	#define CODEC_F1C_LOCATION_INTERNAL RT_BIT(4)
436	#define CODEC_F1C_LOCATION_SECONDRARY_CHASSIS RT_BIT(5)
437	#define CODEC_F1C_LOCATION_OTHER RT_BIT(5)
438
439	/* [0:3] bits of location region means geometry location attachment */
440	#define CODEC_F1C_LOCATION_NA (0)
441	#define CODEC_F1C_LOCATION_REAR (0x1)
442	#define CODEC_F1C_LOCATION_FRONT (0x2)
443	#define CODEC_F1C_LOCATION_LEFT (0x3)
444	#define CODEC_F1C_LOCATION_RIGTH (0x4)
445	#define CODEC_F1C_LOCATION_TOP (0x5)
446	#define CODEC_F1C_LOCATION_BOTTOM (0x6)
447	#define CODEC_F1C_LOCATION_SPECIAL_0 (0x7)
448	#define CODEC_F1C_LOCATION_SPECIAL_1 (0x8)
449	#define CODEC_F1C_LOCATION_SPECIAL_2 (0x9)
450
451	/* Configuration default: Device type */
452	#define CODEC_F1C_DEVICE_MASK (0xF)
453	#define CODEC_F1C_DEVICE_SHIFT (20)
454	#define CODEC_F1C_DEVICE_LINE_OUT (0)
455	#define CODEC_F1C_DEVICE_SPEAKER (0x1)
456	#define CODEC_F1C_DEVICE_HP (0x2)
457	#define CODEC_F1C_DEVICE_CD (0x3)
458	#define CODEC_F1C_DEVICE_SPDIF_OUT (0x4)
459	#define CODEC_F1C_DEVICE_DIGITAL_OTHER_OUT (0x5)
460	#define CODEC_F1C_DEVICE_MODEM_LINE_SIDE (0x6)
461	#define CODEC_F1C_DEVICE_MODEM_HANDSET_SIDE (0x7)
462	#define CODEC_F1C_DEVICE_LINE_IN (0x8)
463	#define CODEC_F1C_DEVICE_AUX (0x9)
464	#define CODEC_F1C_DEVICE_MIC (0xA)
465	#define CODEC_F1C_DEVICE_PHONE (0xB)
466	#define CODEC_F1C_DEVICE_SPDIF_IN (0xC)
467	#define CODEC_F1C_DEVICE_RESERVED (0xE)
468	#define CODEC_F1C_DEVICE_OTHER (0xF)
469
470	/* Configuration default: Connection type */
471	#define CODEC_F1C_CONNECTION_TYPE_MASK (0xF)
472	#define CODEC_F1C_CONNECTION_TYPE_SHIFT (16)
473
474	#define CODEC_F1C_CONNECTION_TYPE_UNKNOWN (0)
475	#define CODEC_F1C_CONNECTION_TYPE_1_8INCHES (0x1)
476	#define CODEC_F1C_CONNECTION_TYPE_1_4INCHES (0x2)
477	#define CODEC_F1C_CONNECTION_TYPE_ATAPI (0x3)
478	#define CODEC_F1C_CONNECTION_TYPE_RCA (0x4)
479	#define CODEC_F1C_CONNECTION_TYPE_OPTICAL (0x5)
480	#define CODEC_F1C_CONNECTION_TYPE_OTHER_DIGITAL (0x6)
481	#define CODEC_F1C_CONNECTION_TYPE_ANALOG (0x7)
482	#define CODEC_F1C_CONNECTION_TYPE_DIN (0x8)
483	#define CODEC_F1C_CONNECTION_TYPE_XLR (0x9)
484	#define CODEC_F1C_CONNECTION_TYPE_RJ_11 (0xA)
485	#define CODEC_F1C_CONNECTION_TYPE_COMBO (0xB)
486	#define CODEC_F1C_CONNECTION_TYPE_OTHER (0xF)
487
488	/* Configuration's color */
489	#define CODEC_F1C_COLOR_MASK (0xF)
490	#define CODEC_F1C_COLOR_SHIFT (12)
491	#define CODEC_F1C_COLOR_UNKNOWN (0)
492	#define CODEC_F1C_COLOR_BLACK (0x1)
493	#define CODEC_F1C_COLOR_GREY (0x2)
494	#define CODEC_F1C_COLOR_BLUE (0x3)
495	#define CODEC_F1C_COLOR_GREEN (0x4)
496	#define CODEC_F1C_COLOR_RED (0x5)
497	#define CODEC_F1C_COLOR_ORANGE (0x6)
498	#define CODEC_F1C_COLOR_YELLOW (0x7)
499	#define CODEC_F1C_COLOR_PURPLE (0x8)
500	#define CODEC_F1C_COLOR_PINK (0x9)
501	#define CODEC_F1C_COLOR_RESERVED_0 (0xA)
502	#define CODEC_F1C_COLOR_RESERVED_1 (0xB)
503	#define CODEC_F1C_COLOR_RESERVED_2 (0xC)
504	#define CODEC_F1C_COLOR_RESERVED_3 (0xD)
505	#define CODEC_F1C_COLOR_WHITE (0xE)
506	#define CODEC_F1C_COLOR_OTHER (0xF)
507
508	/* Configuration's misc */
509	#define CODEC_F1C_MISC_MASK (0xF)
510	#define CODEC_F1C_MISC_SHIFT (8)
511	#define CODEC_F1C_MISC_NONE 0
512	#define CODEC_F1C_MISC_JACK_NO_PRESENCE_DETECT RT_BIT(0)
513	#define CODEC_F1C_MISC_RESERVED_0 RT_BIT(1)
514	#define CODEC_F1C_MISC_RESERVED_1 RT_BIT(2)
515	#define CODEC_F1C_MISC_RESERVED_2 RT_BIT(3)
516
517	/* Configuration default: Association */
518	#define CODEC_F1C_ASSOCIATION_MASK (0xF)
519	#define CODEC_F1C_ASSOCIATION_SHIFT (4)
520
521	/** Reserved; don't use. */
522	#define CODEC_F1C_ASSOCIATION_INVALID 0x0
523	#define CODEC_F1C_ASSOCIATION_GROUP_0 0x1
524	#define CODEC_F1C_ASSOCIATION_GROUP_1 0x2
525	#define CODEC_F1C_ASSOCIATION_GROUP_2 0x3
526	#define CODEC_F1C_ASSOCIATION_GROUP_3 0x4
527	#define CODEC_F1C_ASSOCIATION_GROUP_4 0x5
528	#define CODEC_F1C_ASSOCIATION_GROUP_5 0x6
529	#define CODEC_F1C_ASSOCIATION_GROUP_6 0x7
530	#define CODEC_F1C_ASSOCIATION_GROUP_7 0x8
531	/* Note: Windows OSes will treat group 15 (0xF) as single PIN devices.
532	* The sequence number associated with that group then will be ignored. */
533	#define CODEC_F1C_ASSOCIATION_GROUP_15 0xF
534
535	/* Configuration default: Association Sequence. */
536	#define CODEC_F1C_SEQ_MASK (0xF)
537	#define CODEC_F1C_SEQ_SHIFT (0)
538
539	/* Implementation identification (7.3.3.30). */
540	#define CODEC_MAKE_F20(bmid, bsku, aid) \
541	( (((bmid) & 0xFFFF) << 16) \
542	\| (((bsku) & 0xFF) << 8) \
543	\| (((aid) & 0xFF)) \
544	)
545
546	/* Macro definition helping in filling the configuration registers. */
547	#define CODEC_MAKE_F1C(port_connectivity, location, device, connection_type, color, misc, association, sequence) \
548	( (((port_connectivity) & 0xF) << CODEC_F1C_PORT_SHIFT) \
549	\| (((location) & 0xF) << CODEC_F1C_LOCATION_SHIFT) \
550	\| (((device) & 0xF) << CODEC_F1C_DEVICE_SHIFT) \
551	\| (((connection_type) & 0xF) << CODEC_F1C_CONNECTION_TYPE_SHIFT) \
552	\| (((color) & 0xF) << CODEC_F1C_COLOR_SHIFT) \
553	\| (((misc) & 0xF) << CODEC_F1C_MISC_SHIFT) \
554	\| (((association) & 0xF) << CODEC_F1C_ASSOCIATION_SHIFT) \
555	\| (((sequence) & 0xF)))
556
557
558	/*********************************************************************************************************************************
559	* Structures and Typedefs *
560	*********************************************************************************************************************************/
561	/** The F00 parameter length (in dwords). */
562	#define CODECNODE_F00_PARAM_LENGTH 20
563	/** The F02 parameter length (in dwords). */
564	#define CODECNODE_F02_PARAM_LENGTH 16
565
566	/* PRM 5.3.1 */
567	#define CODEC_RESPONSE_UNSOLICITED RT_BIT_64(34)
568
569	/**
570	* Structure for maintaining a codec verb implementation (ring-0).
571	*/
572	typedef struct CODECVERBR0
573	{
574	/** Verb. */
575	uint32_t verb;
576	/** Verb mask. */
577	uint32_t mask;
578	/** Function pointer for implementation callback. */
579	PFNHDACODECVERBPROCESSORR0 pfn;
580	/** Friendly name, for debugging. */
581	const char *pszName;
582	} CODECVERBR0;
583	/** Ponter to a codec verb implementation (ring-0). */
584	typedef CODECVERBR0 *PCODECVERBR0;
585
586	/**
587	* Structure for maintaining a codec verb implementation (ring-3).
588	*/
589	typedef struct CODECVERBR3
590	{
591	/** Verb. */
592	uint32_t verb;
593	/** Verb mask. */
594	uint32_t mask;
595	/** Function pointer for implementation callback. */
596	PFNHDACODECVERBPROCESSORR3 pfn;
597	/** Friendly name, for debugging. */
598	const char *pszName;
599	} CODECVERBR3;
600	/** Ponter to a codec verb implementation (ring-3). */
601	typedef CODECVERBR3 *PCODECVERBR3;
602
603	#define AMPLIFIER_SIZE 60
604
605	typedef uint32_t AMPLIFIER[AMPLIFIER_SIZE];
606
607	/**
608	* Common (or core) codec node structure.
609	*/
610	typedef struct CODECCOMMONNODE
611	{
612	/** The node's ID. */
613	uint8_t uID;
614	/** The node's name. */
615	/** The SDn ID this node is assigned to.
616	* 0 means not assigned, 1 is SDn0. */
617	uint8_t uSD;
618	/** The SDn's channel to use.
619	* Only valid if a valid SDn ID is set. */
620	uint8_t uChannel;
621	/* PRM 5.3.6 */
622	uint32_t au32F00_param[CODECNODE_F00_PARAM_LENGTH];
623	uint32_t au32F02_param[CODECNODE_F02_PARAM_LENGTH];
624	} CODECCOMMONNODE;
625	typedef CODECCOMMONNODE *PCODECCOMMONNODE;
626	AssertCompile(CODECNODE_F00_PARAM_LENGTH == 20); /* saved state */
627	AssertCompile(CODECNODE_F02_PARAM_LENGTH == 16); /* saved state */
628
629	/**
630	* Compile time assertion on the expected node size.
631	*/
632	#define AssertNodeSize(a_Node, a_cParams) \
633	AssertCompile((a_cParams) <= (60 + 6)); /* the max size - saved state */ \
634	AssertCompile( sizeof(a_Node) - sizeof(CODECCOMMONNODE) \
635	== ((a_cParams) * sizeof(uint32_t)) )
636
637	typedef struct ROOTCODECNODE
638	{
639	CODECCOMMONNODE node;
640	} ROOTCODECNODE, *PROOTCODECNODE;
641	AssertNodeSize(ROOTCODECNODE, 0);
642
643	typedef struct DACNODE
644	{
645	CODECCOMMONNODE node;
646	uint32_t u32F0d_param;
647	uint32_t u32F04_param;
648	uint32_t u32F05_param;
649	uint32_t u32F06_param;
650	uint32_t u32F0c_param;
651
652	uint32_t u32A_param;
653	AMPLIFIER B_params;
654
655	} DACNODE, *PDACNODE;
656	AssertNodeSize(DACNODE, 6 + 60);
657
658	typedef struct ADCNODE
659	{
660	CODECCOMMONNODE node;
661	uint32_t u32F01_param;
662	uint32_t u32F03_param;
663	uint32_t u32F05_param;
664	uint32_t u32F06_param;
665	uint32_t u32F09_param;
666
667	uint32_t u32A_param;
668	AMPLIFIER B_params;
669	} ADCNODE, *PADCNODE;
670	AssertNodeSize(DACNODE, 6 + 60);
671
672	typedef struct SPDIFOUTNODE
673	{
674	CODECCOMMONNODE node;
675	uint32_t u32F05_param;
676	uint32_t u32F06_param;
677	uint32_t u32F09_param;
678	uint32_t u32F0d_param;
679
680	uint32_t u32A_param;
681	AMPLIFIER B_params;
682	} SPDIFOUTNODE, *PSPDIFOUTNODE;
683	AssertNodeSize(SPDIFOUTNODE, 5 + 60);
684
685	typedef struct SPDIFINNODE
686	{
687	CODECCOMMONNODE node;
688	uint32_t u32F05_param;
689	uint32_t u32F06_param;
690	uint32_t u32F09_param;
691	uint32_t u32F0d_param;
692
693	uint32_t u32A_param;
694	AMPLIFIER B_params;
695	} SPDIFINNODE, *PSPDIFINNODE;
696	AssertNodeSize(SPDIFINNODE, 5 + 60);
697
698	typedef struct AFGCODECNODE
699	{
700	CODECCOMMONNODE node;
701	uint32_t u32F05_param;
702	uint32_t u32F08_param;
703	uint32_t u32F17_param;
704	uint32_t u32F20_param;
705	} AFGCODECNODE, *PAFGCODECNODE;
706	AssertNodeSize(AFGCODECNODE, 4);
707
708	typedef struct PORTNODE
709	{
710	CODECCOMMONNODE node;
711	uint32_t u32F01_param;
712	uint32_t u32F07_param;
713	uint32_t u32F08_param;
714	uint32_t u32F09_param;
715	uint32_t u32F1c_param;
716	AMPLIFIER B_params;
717	} PORTNODE, *PPORTNODE;
718	AssertNodeSize(PORTNODE, 5 + 60);
719
720	typedef struct DIGOUTNODE
721	{
722	CODECCOMMONNODE node;
723	uint32_t u32F01_param;
724	uint32_t u32F05_param;
725	uint32_t u32F07_param;
726	uint32_t u32F08_param;
727	uint32_t u32F09_param;
728	uint32_t u32F1c_param;
729	} DIGOUTNODE, *PDIGOUTNODE;
730	AssertNodeSize(DIGOUTNODE, 6);
731
732	typedef struct DIGINNODE
733	{
734	CODECCOMMONNODE node;
735	uint32_t u32F05_param;
736	uint32_t u32F07_param;
737	uint32_t u32F08_param;
738	uint32_t u32F09_param;
739	uint32_t u32F0c_param;
740	uint32_t u32F1c_param;
741	uint32_t u32F1e_param;
742	} DIGINNODE, *PDIGINNODE;
743	AssertNodeSize(DIGINNODE, 7);
744
745	typedef struct ADCMUXNODE
746	{
747	CODECCOMMONNODE node;
748	uint32_t u32F01_param;
749
750	uint32_t u32A_param;
751	AMPLIFIER B_params;
752	} ADCMUXNODE, *PADCMUXNODE;
753	AssertNodeSize(ADCMUXNODE, 2 + 60);
754
755	typedef struct PCBEEPNODE
756	{
757	CODECCOMMONNODE node;
758	uint32_t u32F07_param;
759	uint32_t u32F0a_param;
760
761	uint32_t u32A_param;
762	AMPLIFIER B_params;
763	uint32_t u32F1c_param;
764	} PCBEEPNODE, *PPCBEEPNODE;
765	AssertNodeSize(PCBEEPNODE, 3 + 60 + 1);
766
767	typedef struct CDNODE
768	{
769	CODECCOMMONNODE node;
770	uint32_t u32F07_param;
771	uint32_t u32F1c_param;
772	} CDNODE, *PCDNODE;
773	AssertNodeSize(CDNODE, 2);
774
775	typedef struct VOLUMEKNOBNODE
776	{
777	CODECCOMMONNODE node;
778	uint32_t u32F08_param;
779	uint32_t u32F0f_param;
780	} VOLUMEKNOBNODE, *PVOLUMEKNOBNODE;
781	AssertNodeSize(VOLUMEKNOBNODE, 2);
782
783	typedef struct ADCVOLNODE
784	{
785	CODECCOMMONNODE node;
786	uint32_t u32F0c_param;
787	uint32_t u32F01_param;
788	uint32_t u32A_params;
789	AMPLIFIER B_params;
790	} ADCVOLNODE, *PADCVOLNODE;
791	AssertNodeSize(ADCVOLNODE, 3 + 60);
792
793	typedef struct RESNODE
794	{
795	CODECCOMMONNODE node;
796	uint32_t u32F05_param;
797	uint32_t u32F06_param;
798	uint32_t u32F07_param;
799	uint32_t u32F1c_param;
800
801	uint32_t u32A_param;
802	} RESNODE, *PRESNODE;
803	AssertNodeSize(RESNODE, 5);
804
805	/**
806	* Used for the saved state.
807	*/
808	typedef struct CODECSAVEDSTATENODE
809	{
810	CODECCOMMONNODE Core;
811	uint32_t au32Params[60 + 6];
812	} CODECSAVEDSTATENODE;
813	AssertNodeSize(CODECSAVEDSTATENODE, 60 + 6);
814
815	typedef union CODECNODE
816	{
817	CODECCOMMONNODE node;
818	ROOTCODECNODE root;
819	AFGCODECNODE afg;
820	DACNODE dac;
821	ADCNODE adc;
822	SPDIFOUTNODE spdifout;
823	SPDIFINNODE spdifin;
824	PORTNODE port;
825	DIGOUTNODE digout;
826	DIGINNODE digin;
827	ADCMUXNODE adcmux;
828	PCBEEPNODE pcbeep;
829	CDNODE cdnode;
830	VOLUMEKNOBNODE volumeKnob;
831	ADCVOLNODE adcvol;
832	RESNODE reserved;
833	CODECSAVEDSTATENODE SavedState;
834	} CODECNODE, *PCODECNODE;
835	AssertNodeSize(CODECNODE, 60 + 6);
836
837	#define CODEC_VERBS_MAX 64
838	#define CODEC_NODES_MAX 32
839
840	/**
841	* HDA codec state (shared).
842	*/
843	typedef struct HDACODEC
844	{
845	/** Codec implementation type. */
846	CODEC_TYPE enmType;
847	/** Codec ID. */
848	uint16_t id;
849	uint16_t u16VendorId;
850	uint16_t u16DeviceId;
851	uint8_t u8BSKU;
852	uint8_t u8AssemblyId;
853
854	CODECNODE aNodes[CODEC_NODES_MAX];
855	size_t cNodes;
856
857	bool fInReset;
858	uint8_t abPadding1[3];
859
860	uint8_t cTotalNodes;
861	uint8_t u8AdcVolsLineIn;
862	uint8_t u8DacLineOut;
863	uint8_t bPadding2;
864
865	uint8_t au8Ports[CODEC_NODES_MAX];
866	uint8_t au8Dacs[CODEC_NODES_MAX];
867	uint8_t au8AdcVols[CODEC_NODES_MAX];
868	uint8_t au8Adcs[CODEC_NODES_MAX];
869	uint8_t au8AdcMuxs[CODEC_NODES_MAX];
870	uint8_t au8Pcbeeps[CODEC_NODES_MAX];
871	uint8_t au8SpdifIns[CODEC_NODES_MAX];
872	uint8_t au8SpdifOuts[CODEC_NODES_MAX];
873	uint8_t au8DigInPins[CODEC_NODES_MAX];
874	uint8_t au8DigOutPins[CODEC_NODES_MAX];
875	uint8_t au8Cds[CODEC_NODES_MAX];
876	uint8_t au8VolKnobs[CODEC_NODES_MAX];
877	uint8_t au8Reserveds[CODEC_NODES_MAX];
878	} HDACODEC;
879
880	/**
881	* HDA codec state (ring-0).
882	*/
883	typedef struct HDACODECR0
884	{
885	CODECVERBR0 aVerbs[CODEC_VERBS_MAX];
886	size_t cVerbs;
887
888	/** @name Public codec functions.
889	* @{ */
890	DECLR0CALLBACKMEMBER(void, pfnReset, (PHDACODEC pThis, PHDACODECR0 pThisCC));
891	DECLR0CALLBACKMEMBER(int, pfnNodeReset, (PHDACODEC pThis, uint8_t nID, PCODECNODE pNode));
892	DECLR0CALLBACKMEMBER(int, pfnLookup, (PHDACODEC pThis, PHDACODECR0 pThisCC, uint32_t uVerb, uint64_t *puResp));
893	/** @} */
894
895	#ifdef VBOX_WITH_STATISTICS
896	STAMCOUNTER StatLookupsR0;
897	#endif
898
899	} HDACODECR0;
900
901	int hdaR0CodecConstruct(PPDMDEVINS pDevIns, PHDACODEC pThis, PHDACODECR0 pThisCC);
902
903	/**
904	* HDA codec state (ring-3).
905	*/
906	typedef struct HDACODECR3
907	{
908	CODECVERBR3 aVerbs[CODEC_VERBS_MAX];
909	size_t cVerbs;
910
911	/** @name Public codec functions.
912	* @{ */
913	DECLR3CALLBACKMEMBER(int, pfnLookup, (PHDACODEC pThis, PHDACODECR3 pThisCC, uint32_t uVerb, uint64_t *puResp));
914	DECLR3CALLBACKMEMBER(void, pfnDbgListNodes, (PHDACODEC pThis, PHDACODECR3 pThisCC, PCDBGFINFOHLP pHlp, const char *pszArgs));
915	DECLR3CALLBACKMEMBER(void, pfnDbgSelector, (PHDACODEC pThis, PHDACODECR3 pThisCC, PCDBGFINFOHLP pHlp, const char *pszArgs));
916	/** @} */
917
918	/** The parent device instance. */
919	PPDMDEVINS pDevIns;
920
921	/** @name Callbacks to the HDA controller, mostly used for multiplexing to the
922	* various host backends.
923	* @{ */
924	/**
925	*
926	* Adds a new audio stream to a specific mixer control.
927	*
928	* Depending on the mixer control the stream then gets assigned to one of the
929	* internal mixer sinks, which in turn then handle the mixing of all connected
930	* streams to that sink.
931	*
932	* @return VBox status code.
933	* @param pDevIns The device instance.
934	* @param enmMixerCtl Mixer control to assign new stream to.
935	* @param pCfg Stream configuration for the new stream.
936	*/
937	DECLR3CALLBACKMEMBER(int, pfnCbMixerAddStream, (PPDMDEVINS pDevIns, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOSTREAMCFG pCfg));
938	/**
939	* Removes a specified mixer control from the HDA's mixer.
940	*
941	* @return VBox status code.
942	* @param pDevIns The device instance.
943	* @param enmMixerCtl Mixer control to remove.
944	*/
945	DECLR3CALLBACKMEMBER(int, pfnCbMixerRemoveStream, (PPDMDEVINS pDevIns, PDMAUDIOMIXERCTL enmMixerCtl));
946	/**
947	* Controls an input / output converter widget, that is, which converter is
948	* connected to which stream (and channel).
949	*
950	* @return VBox status code.
951	* @param pDevIns The device instance.
952	* @param enmMixerCtl Mixer control to set SD stream number and channel for.
953	* @param uSD SD stream number (number + 1) to set. Set to 0 for unassign.
954	* @param uChannel Channel to set. Only valid if a valid SD stream number is specified.
955	*/
956	DECLR3CALLBACKMEMBER(int, pfnCbMixerControl, (PPDMDEVINS pDevIns, PDMAUDIOMIXERCTL enmMixerCtl, uint8_t uSD, uint8_t uChannel));
957	/**
958	* Sets the volume of a specified mixer control.
959	*
960	* @return IPRT status code.
961	* @param pDevIns The device instance.
962	* @param enmMixerCtl Mixer control to set volume for.
963	* @param pVol Pointer to volume data to set.
964	*/
965	DECLR3CALLBACKMEMBER(int, pfnCbMixerSetVolume, (PPDMDEVINS pDevIns, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOVOLUME pVol));
966	/** @} */
967
968	#ifdef VBOX_WITH_STATISTICS
969	STAMCOUNTER StatLookupsR0;
970	STAMCOUNTER StatLookupsR3;
971	#endif
972
973	} HDACODECR3;
974
975	int hdaR3CodecConstruct(PPDMDEVINS pDevIns, PHDACODEC pThis, PHDACODECR3 pThisCC, uint16_t uLUN, PCFGMNODE pCfg);
976	void hdaR3CodecPowerOff(PHDACODECR3 pThisCC);
977	int hdaR3CodecLoadState(PPDMDEVINS pDevIns, PHDACODEC pThis, PHDACODECR3 pThisCC, PSSMHANDLE pSSM, uint32_t uVersion);
978	int hdaR3CodecAddStream(PHDACODECR3 pThisCC, PDMAUDIOMIXERCTL enmMixerCtl, PPDMAUDIOSTREAMCFG pCfg);
979	int hdaR3CodecRemoveStream(PHDACODECR3 pThisCC, PDMAUDIOMIXERCTL enmMixerCtl);
980
981	int hdaCodecSaveState(PPDMDEVINS pDevIns, PHDACODEC pThis, PSSMHANDLE pSSM);
982	void hdaCodecDestruct(PHDACODEC pThis);
983	void hdaCodecReset(PHDACODEC pThis);
984
985	/** @name DevHDA saved state versions
986	* @{ */
987	/** The current staved state version. */
988	#define HDA_SAVED_STATE_VERSION HDA_SAVED_STATE_WITHOUT_PERIOD
989
990	/** Removed period and redefined wall clock. */
991	#define HDA_SAVED_STATE_WITHOUT_PERIOD 8
992	/** Added (Controller): Current wall clock value (this independent from WALCLK register value).
993	* Added (Controller): Current IRQ level.
994	* Added (Per stream): Ring buffer. This is optional and can be skipped if (not) needed.
995	* Added (Per stream): Struct g_aSSMStreamStateFields7.
996	* Added (Per stream): Struct g_aSSMStreamPeriodFields7.
997	* Added (Current BDLE per stream): Struct g_aSSMBDLEDescFields7.
998	* Added (Current BDLE per stream): Struct g_aSSMBDLEStateFields7. */
999	#define HDA_SAVED_STATE_VERSION_7 7
1000	/** Saves the current BDLE state.
1001	* @since 5.0.14 (r104839) */
1002	#define HDA_SAVED_STATE_VERSION_6 6
1003	/** Introduced dynamic number of streams + stream identifiers for serialization.
1004	* Bug: Did not save the BDLE states correctly.
1005	* Those will be skipped on load then.
1006	* @since 5.0.12 (r104520) */
1007	#define HDA_SAVED_STATE_VERSION_5 5
1008	/** Since this version the number of MMIO registers can be flexible. */
1009	#define HDA_SAVED_STATE_VERSION_4 4
1010	#define HDA_SAVED_STATE_VERSION_3 3
1011	#define HDA_SAVED_STATE_VERSION_2 2
1012	#define HDA_SAVED_STATE_VERSION_1 1
1013	/** @} */
1014
1015	#endif /* !VBOX_INCLUDED_SRC_Audio_DevHdaCodec_h */
1016

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source: vbox/trunk/src/VBox/Devices/Audio/DevHdaCodec.h@ 88466

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