VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevHdaCommon.h@ 89877

Last change on this file since 89877 was 89874, checked in by vboxsync, 4 years ago

DevHda: Calculate cMsSchedulingHint based on the actual scheduling rather than some unused and obsolete timer frequency value. Removed the TimerHz config value. Cleanups. bugref:9890
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1/* $Id: DevHdaCommon.h 89874 2021-06-24 09:51:51Z vboxsync $ */
2/** @file
3 * Intel HD Audio Controller Emulation - Common stuff.
4 *
5 * @todo r=bird: Wtf is this? Do we have some other HDA implementations
6 * that I'm not aware of that shares this code?
7 */
8
9/*
10 * Copyright (C) 2016-2020 Oracle Corporation
11 *
12 * This file is part of VirtualBox Open Source Edition (OSE), as
13 * available from http://www.virtualbox.org. This file is free software;
14 * you can redistribute it and/or modify it under the terms of the GNU
15 * General Public License (GPL) as published by the Free Software
16 * Foundation, in version 2 as it comes in the "COPYING" file of the
17 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
18 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
19 */
20
21#ifndef VBOX_INCLUDED_SRC_Audio_DevHdaCommon_h
22#define VBOX_INCLUDED_SRC_Audio_DevHdaCommon_h
23#ifndef RT_WITHOUT_PRAGMA_ONCE
24# pragma once
25#endif
26
27#ifndef VBOX_INCLUDED_SRC_Audio_DevHda_h
28# error "Only include DevHda.h!"
29#endif
30
31#include "AudioMixer.h"
32#include <VBox/log.h> /* LOG_ENABLED */
33
34
35/** Read callback. */
36typedef VBOXSTRICTRC FNHDAREGREAD(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t *pu32Value);
37/** Write callback. */
38typedef VBOXSTRICTRC FNHDAREGWRITE(PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t iReg, uint32_t u32Value);
39
40/**
41 * HDA register descriptor.
42 *
43 * See 302349 p 6.2.
44 */
45typedef struct HDAREGDESC
46{
47 /** Register offset in the register space. */
48 uint32_t offset;
49 /** Size in bytes. Registers of size > 4 are in fact tables. */
50 uint32_t size;
51 /** Readable bits. */
52 uint32_t readable;
53 /** Writable bits. */
54 uint32_t writable;
55 /** Register descriptor (RD) flags of type HDA_RD_F_XXX. These are used to
56 * specify the handling (read/write) policy of the register. */
57 uint32_t fFlags;
58 /** Read callback. */
59 FNHDAREGREAD *pfnRead;
60 /** Write callback. */
61 FNHDAREGWRITE *pfnWrite;
62 /** Index into the register storage array. */
63 uint32_t mem_idx;
64 /** Abbreviated name. */
65 const char *abbrev;
66 /** Descripton. */
67 const char *desc;
68} HDAREGDESC;
69/** Pointer to a a const HDA register descriptor. */
70typedef HDAREGDESC const *PCHDAREGDESC;
71
72/**
73 * HDA register aliases (HDA spec 3.3.45).
74 * @remarks Sorted by offReg.
75 */
76typedef struct HDAREGALIAS
77{
78 /** The alias register offset. */
79 uint32_t offReg;
80 /** The register index. */
81 int idxAlias;
82} HDAREGALIAS;
83
84/**
85 * At the moment we support 4 input + 4 output streams max, which is 8 in total.
86 * Bidirectional streams are currently *not* supported.
87 *
88 * Note: When changing any of those values, be prepared for some saved state
89 * fixups / trouble!
90 */
91#define HDA_MAX_SDI 4
92#define HDA_MAX_SDO 4
93#define HDA_MAX_STREAMS (HDA_MAX_SDI + HDA_MAX_SDO)
94AssertCompile(HDA_MAX_SDI <= HDA_MAX_SDO);
95
96/** Number of general registers. */
97#define HDA_NUM_GENERAL_REGS 34
98/** Number of total registers in the HDA's register map. */
99#define HDA_NUM_REGS (HDA_NUM_GENERAL_REGS + (HDA_MAX_STREAMS * 10 /* Each stream descriptor has 10 registers */))
100/** Total number of stream tags (channels). Index 0 is reserved / invalid. */
101#define HDA_MAX_TAGS 16
102
103/**
104 * ICH6 datasheet defines limits for FIFOS registers (18.2.39).
105 * Formula: size - 1
106 * Other values not listed are not supported.
107 */
108
109/** Offset of the SD0 register map. */
110#define HDA_REG_DESC_SD0_BASE 0x80
111
112/** Turn a short global register name into an memory index and a stringized name. */
113#define HDA_REG_IDX(abbrev) HDA_MEM_IND_NAME(abbrev), #abbrev
114
115/** Turns a short stream register name into an memory index and a stringized name. */
116#define HDA_REG_IDX_STRM(reg, suff) HDA_MEM_IND_NAME(reg ## suff), #reg #suff
117
118/** Same as above for a register *not* stored in memory. */
119#define HDA_REG_IDX_NOMEM(abbrev) 0, #abbrev
120
121extern const HDAREGDESC g_aHdaRegMap[HDA_NUM_REGS];
122
123/**
124 * NB: Register values stored in memory (au32Regs[]) are indexed through
125 * the HDA_RMX_xxx macros (also HDA_MEM_IND_NAME()). On the other hand, the
126 * register descriptors in g_aHdaRegMap[] are indexed through the
127 * HDA_REG_xxx macros (also HDA_REG_IND_NAME()).
128 *
129 * The au32Regs[] layout is kept unchanged for saved state
130 * compatibility.
131 */
132
133/* Registers */
134#define HDA_REG_IND_NAME(x) HDA_REG_##x
135#define HDA_MEM_IND_NAME(x) HDA_RMX_##x
136#define HDA_REG_IND(pThis, x) ((pThis)->au32Regs[g_aHdaRegMap[x].mem_idx])
137#define HDA_REG(pThis, x) (HDA_REG_IND((pThis), HDA_REG_IND_NAME(x)))
138
139
140#define HDA_REG_GCAP 0 /* Range 0x00 - 0x01 */
141#define HDA_RMX_GCAP 0
142/**
143 * GCAP HDASpec 3.3.2 This macro encodes the following information about HDA in a compact manner:
144 *
145 * oss (15:12) - Number of output streams supported.
146 * iss (11:8) - Number of input streams supported.
147 * bss (7:3) - Number of bidirectional streams supported.
148 * bds (2:1) - Number of serial data out (SDO) signals supported.
149 * b64sup (0) - 64 bit addressing supported.
150 */
151#define HDA_MAKE_GCAP(oss, iss, bss, bds, b64sup) \
152 ( (((oss) & 0xF) << 12) \
153 | (((iss) & 0xF) << 8) \
154 | (((bss) & 0x1F) << 3) \
155 | (((bds) & 0x3) << 2) \
156 | ((b64sup) & 1))
157
158#define HDA_REG_VMIN 1 /* 0x02 */
159#define HDA_RMX_VMIN 1
160
161#define HDA_REG_VMAJ 2 /* 0x03 */
162#define HDA_RMX_VMAJ 2
163
164#define HDA_REG_OUTPAY 3 /* 0x04-0x05 */
165#define HDA_RMX_OUTPAY 3
166
167#define HDA_REG_INPAY 4 /* 0x06-0x07 */
168#define HDA_RMX_INPAY 4
169
170#define HDA_REG_GCTL 5 /* 0x08-0x0B */
171#define HDA_RMX_GCTL 5
172#define HDA_GCTL_UNSOL RT_BIT(8) /* Accept Unsolicited Response Enable */
173#define HDA_GCTL_FCNTRL RT_BIT(1) /* Flush Control */
174#define HDA_GCTL_CRST RT_BIT(0) /* Controller Reset */
175
176#define HDA_REG_WAKEEN 6 /* 0x0C */
177#define HDA_RMX_WAKEEN 6
178
179#define HDA_REG_STATESTS 7 /* 0x0E */
180#define HDA_RMX_STATESTS 7
181#define HDA_STATESTS_SCSF_MASK 0x7 /* State Change Status Flags (6.2.8). */
182
183#define HDA_REG_GSTS 8 /* 0x10-0x11*/
184#define HDA_RMX_GSTS 8
185#define HDA_GSTS_FSTS RT_BIT(1) /* Flush Status */
186
187#define HDA_REG_OUTSTRMPAY 9 /* 0x18 */
188#define HDA_RMX_OUTSTRMPAY 112
189
190#define HDA_REG_INSTRMPAY 10 /* 0x1a */
191#define HDA_RMX_INSTRMPAY 113
192
193#define HDA_REG_INTCTL 11 /* 0x20 */
194#define HDA_RMX_INTCTL 9
195#define HDA_INTCTL_GIE RT_BIT(31) /* Global Interrupt Enable */
196#define HDA_INTCTL_CIE RT_BIT(30) /* Controller Interrupt Enable */
197/** Bits 0-29 correspond to streams 0-29. */
198#define HDA_STRMINT_MASK 0xFF /* Streams 0-7 implemented. Applies to INTCTL and INTSTS. */
199
200#define HDA_REG_INTSTS 12 /* 0x24 */
201#define HDA_RMX_INTSTS 10
202#define HDA_INTSTS_GIS RT_BIT(31) /* Global Interrupt Status */
203#define HDA_INTSTS_CIS RT_BIT(30) /* Controller Interrupt Status */
204
205#define HDA_REG_WALCLK 13 /* 0x30 */
206/**NB: HDA_RMX_WALCLK is not defined because the register is not stored in memory. */
207
208/**
209 * Note: The HDA specification defines a SSYNC register at offset 0x38. The
210 * ICH6/ICH9 datahseet defines SSYNC at offset 0x34. The Linux HDA driver matches
211 * the datasheet.
212 */
213#define HDA_REG_SSYNC 14 /* 0x34 */
214#define HDA_RMX_SSYNC 12
215
216#define HDA_REG_CORBLBASE 15 /* 0x40 */
217#define HDA_RMX_CORBLBASE 13
218
219#define HDA_REG_CORBUBASE 16 /* 0x44 */
220#define HDA_RMX_CORBUBASE 14
221
222#define HDA_REG_CORBWP 17 /* 0x48 */
223#define HDA_RMX_CORBWP 15
224
225#define HDA_REG_CORBRP 18 /* 0x4A */
226#define HDA_RMX_CORBRP 16
227#define HDA_CORBRP_RST RT_BIT(15) /* CORB Read Pointer Reset */
228
229#define HDA_REG_CORBCTL 19 /* 0x4C */
230#define HDA_RMX_CORBCTL 17
231#define HDA_CORBCTL_DMA RT_BIT(1) /* Enable CORB DMA Engine */
232#define HDA_CORBCTL_CMEIE RT_BIT(0) /* CORB Memory Error Interrupt Enable */
233
234#define HDA_REG_CORBSTS 20 /* 0x4D */
235#define HDA_RMX_CORBSTS 18
236
237#define HDA_REG_CORBSIZE 21 /* 0x4E */
238#define HDA_RMX_CORBSIZE 19
239#define HDA_CORBSIZE_SZ_CAP 0xF0
240#define HDA_CORBSIZE_SZ 0x3
241
242/** Number of CORB buffer entries. */
243#define HDA_CORB_SIZE 256
244/** CORB element size (in bytes). */
245#define HDA_CORB_ELEMENT_SIZE 4
246/** Number of RIRB buffer entries. */
247#define HDA_RIRB_SIZE 256
248/** RIRB element size (in bytes). */
249#define HDA_RIRB_ELEMENT_SIZE 8
250
251#define HDA_REG_RIRBLBASE 22 /* 0x50 */
252#define HDA_RMX_RIRBLBASE 20
253
254#define HDA_REG_RIRBUBASE 23 /* 0x54 */
255#define HDA_RMX_RIRBUBASE 21
256
257#define HDA_REG_RIRBWP 24 /* 0x58 */
258#define HDA_RMX_RIRBWP 22
259#define HDA_RIRBWP_RST RT_BIT(15) /* RIRB Write Pointer Reset */
260
261#define HDA_REG_RINTCNT 25 /* 0x5A */
262#define HDA_RMX_RINTCNT 23
263
264/** Maximum number of Response Interrupts. */
265#define HDA_MAX_RINTCNT 256
266
267#define HDA_REG_RIRBCTL 26 /* 0x5C */
268#define HDA_RMX_RIRBCTL 24
269#define HDA_RIRBCTL_ROIC RT_BIT(2) /* Response Overrun Interrupt Control */
270#define HDA_RIRBCTL_RDMAEN RT_BIT(1) /* RIRB DMA Enable */
271#define HDA_RIRBCTL_RINTCTL RT_BIT(0) /* Response Interrupt Control */
272
273#define HDA_REG_RIRBSTS 27 /* 0x5D */
274#define HDA_RMX_RIRBSTS 25
275#define HDA_RIRBSTS_RIRBOIS RT_BIT(2) /* Response Overrun Interrupt Status */
276#define HDA_RIRBSTS_RINTFL RT_BIT(0) /* Response Interrupt Flag */
277
278#define HDA_REG_RIRBSIZE 28 /* 0x5E */
279#define HDA_RMX_RIRBSIZE 26
280
281#define HDA_REG_IC 29 /* 0x60 */
282#define HDA_RMX_IC 27
283
284#define HDA_REG_IR 30 /* 0x64 */
285#define HDA_RMX_IR 28
286
287#define HDA_REG_IRS 31 /* 0x68 */
288#define HDA_RMX_IRS 29
289#define HDA_IRS_IRV RT_BIT(1) /* Immediate Result Valid */
290#define HDA_IRS_ICB RT_BIT(0) /* Immediate Command Busy */
291
292#define HDA_REG_DPLBASE 32 /* 0x70 */
293#define HDA_RMX_DPLBASE 30
294
295#define HDA_REG_DPUBASE 33 /* 0x74 */
296#define HDA_RMX_DPUBASE 31
297
298#define DPBASE_ADDR_MASK (~(uint64_t)0x7f)
299
300#define HDA_STREAM_REG_DEF(name, num) (HDA_REG_SD##num##name)
301#define HDA_STREAM_RMX_DEF(name, num) (HDA_RMX_SD##num##name)
302/** Note: sdnum here _MUST_ be stream reg number [0,7]. */
303#define HDA_STREAM_REG(pThis, name, sdnum) (HDA_REG_IND((pThis), HDA_REG_SD0##name + (sdnum) * 10))
304
305#define HDA_SD_NUM_FROM_REG(pThis, func, reg) ((reg - HDA_STREAM_REG_DEF(func, 0)) / 10)
306
307/** @todo Condense marcos! */
308
309#define HDA_REG_SD0CTL HDA_NUM_GENERAL_REGS /* 0x80; other streams offset by 0x20 */
310#define HDA_RMX_SD0CTL 32
311#define HDA_RMX_SD1CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 10)
312#define HDA_RMX_SD2CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 20)
313#define HDA_RMX_SD3CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 30)
314#define HDA_RMX_SD4CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 40)
315#define HDA_RMX_SD5CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 50)
316#define HDA_RMX_SD6CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 60)
317#define HDA_RMX_SD7CTL (HDA_STREAM_RMX_DEF(CTL, 0) + 70)
318
319#define HDA_SDCTL_NUM_MASK 0xF
320#define HDA_SDCTL_NUM_SHIFT 20
321#define HDA_SDCTL_DIR RT_BIT(19) /* Direction (Bidirectional streams only!) */
322#define HDA_SDCTL_TP RT_BIT(18) /* Traffic Priority (PCI Express) */
323#define HDA_SDCTL_STRIPE_MASK 0x3
324#define HDA_SDCTL_STRIPE_SHIFT 16
325#define HDA_SDCTL_DEIE RT_BIT(4) /* Descriptor Error Interrupt Enable */
326#define HDA_SDCTL_FEIE RT_BIT(3) /* FIFO Error Interrupt Enable */
327#define HDA_SDCTL_IOCE RT_BIT(2) /* Interrupt On Completion Enable */
328#define HDA_SDCTL_RUN RT_BIT(1) /* Stream Run */
329#define HDA_SDCTL_SRST RT_BIT(0) /* Stream Reset */
330
331#define HDA_REG_SD0STS 35 /* 0x83; other streams offset by 0x20 */
332#define HDA_RMX_SD0STS 33
333#define HDA_RMX_SD1STS (HDA_STREAM_RMX_DEF(STS, 0) + 10)
334#define HDA_RMX_SD2STS (HDA_STREAM_RMX_DEF(STS, 0) + 20)
335#define HDA_RMX_SD3STS (HDA_STREAM_RMX_DEF(STS, 0) + 30)
336#define HDA_RMX_SD4STS (HDA_STREAM_RMX_DEF(STS, 0) + 40)
337#define HDA_RMX_SD5STS (HDA_STREAM_RMX_DEF(STS, 0) + 50)
338#define HDA_RMX_SD6STS (HDA_STREAM_RMX_DEF(STS, 0) + 60)
339#define HDA_RMX_SD7STS (HDA_STREAM_RMX_DEF(STS, 0) + 70)
340
341#define HDA_SDSTS_FIFORDY RT_BIT(5) /* FIFO Ready */
342#define HDA_SDSTS_DESE RT_BIT(4) /* Descriptor Error */
343#define HDA_SDSTS_FIFOE RT_BIT(3) /* FIFO Error */
344#define HDA_SDSTS_BCIS RT_BIT(2) /* Buffer Completion Interrupt Status */
345
346#define HDA_REG_SD0LPIB 36 /* 0x84; other streams offset by 0x20 */
347#define HDA_REG_SD1LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 10) /* 0xA4 */
348#define HDA_REG_SD2LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 20) /* 0xC4 */
349#define HDA_REG_SD3LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 30) /* 0xE4 */
350#define HDA_REG_SD4LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 40) /* 0x104 */
351#define HDA_REG_SD5LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 50) /* 0x124 */
352#define HDA_REG_SD6LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 60) /* 0x144 */
353#define HDA_REG_SD7LPIB (HDA_STREAM_REG_DEF(LPIB, 0) + 70) /* 0x164 */
354#define HDA_RMX_SD0LPIB 34
355#define HDA_RMX_SD1LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 10)
356#define HDA_RMX_SD2LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 20)
357#define HDA_RMX_SD3LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 30)
358#define HDA_RMX_SD4LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 40)
359#define HDA_RMX_SD5LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 50)
360#define HDA_RMX_SD6LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 60)
361#define HDA_RMX_SD7LPIB (HDA_STREAM_RMX_DEF(LPIB, 0) + 70)
362
363#define HDA_REG_SD0CBL 37 /* 0x88; other streams offset by 0x20 */
364#define HDA_RMX_SD0CBL 35
365#define HDA_RMX_SD1CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 10)
366#define HDA_RMX_SD2CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 20)
367#define HDA_RMX_SD3CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 30)
368#define HDA_RMX_SD4CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 40)
369#define HDA_RMX_SD5CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 50)
370#define HDA_RMX_SD6CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 60)
371#define HDA_RMX_SD7CBL (HDA_STREAM_RMX_DEF(CBL, 0) + 70)
372
373#define HDA_REG_SD0LVI 38 /* 0x8C; other streams offset by 0x20 */
374#define HDA_RMX_SD0LVI 36
375#define HDA_RMX_SD1LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 10)
376#define HDA_RMX_SD2LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 20)
377#define HDA_RMX_SD3LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 30)
378#define HDA_RMX_SD4LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 40)
379#define HDA_RMX_SD5LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 50)
380#define HDA_RMX_SD6LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 60)
381#define HDA_RMX_SD7LVI (HDA_STREAM_RMX_DEF(LVI, 0) + 70)
382
383#define HDA_REG_SD0FIFOW 39 /* 0x8E; other streams offset by 0x20 */
384#define HDA_RMX_SD0FIFOW 37
385#define HDA_RMX_SD1FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 10)
386#define HDA_RMX_SD2FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 20)
387#define HDA_RMX_SD3FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 30)
388#define HDA_RMX_SD4FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 40)
389#define HDA_RMX_SD5FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 50)
390#define HDA_RMX_SD6FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 60)
391#define HDA_RMX_SD7FIFOW (HDA_STREAM_RMX_DEF(FIFOW, 0) + 70)
392
393/*
394 * ICH6 datasheet defined limits for FIFOW values (18.2.38).
395 */
396#define HDA_SDFIFOW_8B 0x2
397#define HDA_SDFIFOW_16B 0x3
398#define HDA_SDFIFOW_32B 0x4
399
400#define HDA_REG_SD0FIFOS 40 /* 0x90; other streams offset by 0x20 */
401#define HDA_RMX_SD0FIFOS 38
402#define HDA_RMX_SD1FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 10)
403#define HDA_RMX_SD2FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 20)
404#define HDA_RMX_SD3FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 30)
405#define HDA_RMX_SD4FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 40)
406#define HDA_RMX_SD5FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 50)
407#define HDA_RMX_SD6FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 60)
408#define HDA_RMX_SD7FIFOS (HDA_STREAM_RMX_DEF(FIFOS, 0) + 70)
409
410#define HDA_SDIFIFO_120B 0x77 /* 8-, 16-, 20-, 24-, 32-bit Input Streams */
411#define HDA_SDIFIFO_160B 0x9F /* 20-, 24-bit Input Streams Streams */
412
413#define HDA_SDOFIFO_16B 0x0F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
414#define HDA_SDOFIFO_32B 0x1F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
415#define HDA_SDOFIFO_64B 0x3F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
416#define HDA_SDOFIFO_128B 0x7F /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
417#define HDA_SDOFIFO_192B 0xBF /* 8-, 16-, 20-, 24-, 32-bit Output Streams */
418#define HDA_SDOFIFO_256B 0xFF /* 20-, 24-bit Output Streams */
419
420#define HDA_REG_SD0FMT 41 /* 0x92; other streams offset by 0x20 */
421#define HDA_RMX_SD0FMT 39
422#define HDA_RMX_SD1FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 10)
423#define HDA_RMX_SD2FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 20)
424#define HDA_RMX_SD3FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 30)
425#define HDA_RMX_SD4FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 40)
426#define HDA_RMX_SD5FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 50)
427#define HDA_RMX_SD6FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 60)
428#define HDA_RMX_SD7FMT (HDA_STREAM_RMX_DEF(FMT, 0) + 70)
429
430#define HDA_REG_SD0BDPL 42 /* 0x98; other streams offset by 0x20 */
431#define HDA_RMX_SD0BDPL 40
432#define HDA_RMX_SD1BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 10)
433#define HDA_RMX_SD2BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 20)
434#define HDA_RMX_SD3BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 30)
435#define HDA_RMX_SD4BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 40)
436#define HDA_RMX_SD5BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 50)
437#define HDA_RMX_SD6BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 60)
438#define HDA_RMX_SD7BDPL (HDA_STREAM_RMX_DEF(BDPL, 0) + 70)
439
440#define HDA_REG_SD0BDPU 43 /* 0x9C; other streams offset by 0x20 */
441#define HDA_RMX_SD0BDPU 41
442#define HDA_RMX_SD1BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 10)
443#define HDA_RMX_SD2BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 20)
444#define HDA_RMX_SD3BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 30)
445#define HDA_RMX_SD4BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 40)
446#define HDA_RMX_SD5BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 50)
447#define HDA_RMX_SD6BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 60)
448#define HDA_RMX_SD7BDPU (HDA_STREAM_RMX_DEF(BDPU, 0) + 70)
449
450#define HDA_CODEC_CAD_SHIFT 28
451/** Encodes the (required) LUN into a codec command. */
452#define HDA_CODEC_CMD(cmd, lun) ((cmd) | (lun << HDA_CODEC_CAD_SHIFT))
453
454#define HDA_SDFMT_NON_PCM_SHIFT 15
455#define HDA_SDFMT_NON_PCM_MASK 0x1
456#define HDA_SDFMT_BASE_RATE_SHIFT 14
457#define HDA_SDFMT_BASE_RATE_MASK 0x1
458#define HDA_SDFMT_MULT_SHIFT 11
459#define HDA_SDFMT_MULT_MASK 0x7
460#define HDA_SDFMT_DIV_SHIFT 8
461#define HDA_SDFMT_DIV_MASK 0x7
462#define HDA_SDFMT_BITS_SHIFT 4
463#define HDA_SDFMT_BITS_MASK 0x7
464#define HDA_SDFMT_CHANNELS_MASK 0xF
465
466#define HDA_SDFMT_TYPE RT_BIT(15)
467#define HDA_SDFMT_TYPE_PCM (0)
468#define HDA_SDFMT_TYPE_NON_PCM (1)
469
470#define HDA_SDFMT_BASE RT_BIT(14)
471#define HDA_SDFMT_BASE_48KHZ (0)
472#define HDA_SDFMT_BASE_44KHZ (1)
473
474#define HDA_SDFMT_MULT_1X (0)
475#define HDA_SDFMT_MULT_2X (1)
476#define HDA_SDFMT_MULT_3X (2)
477#define HDA_SDFMT_MULT_4X (3)
478
479#define HDA_SDFMT_DIV_1X (0)
480#define HDA_SDFMT_DIV_2X (1)
481#define HDA_SDFMT_DIV_3X (2)
482#define HDA_SDFMT_DIV_4X (3)
483#define HDA_SDFMT_DIV_5X (4)
484#define HDA_SDFMT_DIV_6X (5)
485#define HDA_SDFMT_DIV_7X (6)
486#define HDA_SDFMT_DIV_8X (7)
487
488#define HDA_SDFMT_8_BIT (0)
489#define HDA_SDFMT_16_BIT (1)
490#define HDA_SDFMT_20_BIT (2)
491#define HDA_SDFMT_24_BIT (3)
492#define HDA_SDFMT_32_BIT (4)
493
494#define HDA_SDFMT_CHAN_MONO (0)
495#define HDA_SDFMT_CHAN_STEREO (1)
496
497/** Emits a SDnFMT register format.
498 * Also being used in the codec's converter format. */
499#define HDA_SDFMT_MAKE(_afNonPCM, _aBaseRate, _aMult, _aDiv, _aBits, _aChan) \
500 ( (((_afNonPCM) & HDA_SDFMT_NON_PCM_MASK) << HDA_SDFMT_NON_PCM_SHIFT) \
501 | (((_aBaseRate) & HDA_SDFMT_BASE_RATE_MASK) << HDA_SDFMT_BASE_RATE_SHIFT) \
502 | (((_aMult) & HDA_SDFMT_MULT_MASK) << HDA_SDFMT_MULT_SHIFT) \
503 | (((_aDiv) & HDA_SDFMT_DIV_MASK) << HDA_SDFMT_DIV_SHIFT) \
504 | (((_aBits) & HDA_SDFMT_BITS_MASK) << HDA_SDFMT_BITS_SHIFT) \
505 | ( (_aChan) & HDA_SDFMT_CHANNELS_MASK))
506
507/** Interrupt on completion (IOC) flag. */
508#define HDA_BDLE_F_IOC RT_BIT(0)
509
510
511
512/** Pointer to a shared HDA state. */
513typedef struct HDASTATE *PHDASTATE;
514/** Pointer to a HDA stream state. */
515typedef struct HDASTREAM *PHDASTREAM;
516/** Pointer to a mixer sink. */
517typedef struct HDAMIXERSINK *PHDAMIXERSINK;
518
519
520/**
521 * BDL description structure.
522 * Do not touch this, as this must match to the HDA specs.
523 */
524typedef struct HDABDLEDESC
525{
526 /** Starting address of the actual buffer. Must be 128-bit aligned. */
527 uint64_t u64BufAddr;
528 /** Size of the actual buffer (in bytes). */
529 uint32_t u32BufSize;
530 /** Bit 0: Interrupt on completion; the controller will generate
531 * an interrupt when the last byte of the buffer has been
532 * fetched by the DMA engine.
533 *
534 * Rest is reserved for further use and must be 0. */
535 uint32_t fFlags;
536} HDABDLEDESC, *PHDABDLEDESC;
537AssertCompileSize(HDABDLEDESC, 16); /* Always 16 byte. Also must be aligned on 128-byte boundary. */
538
539
540/** @name Object lookup functions.
541 * @{
542 */
543#ifdef IN_RING3
544PHDAMIXERSINK hdaR3GetDefaultSink(PHDASTATER3 pThisCC, uint8_t uSD);
545#endif
546PDMAUDIODIR hdaGetDirFromSD(uint8_t uSD);
547//PHDASTREAM hdaGetStreamFromSD(PHDASTATER3 pThisCC, uint8_t uSD);
548#ifdef IN_RING3
549PHDASTREAMR3 hdaR3GetR3StreamFromSink(PHDAMIXERSINK pSink);
550PHDASTREAM hdaR3GetSharedStreamFromSink(PHDAMIXERSINK pSink);
551#endif
552/** @} */
553
554/** @name Interrupt functions.
555 * @{
556 */
557#if defined(LOG_ENABLED) || defined(DOXYGEN_RUNNING)
558void hdaProcessInterrupt(PPDMDEVINS pDevIns, PHDASTATE pThis, const char *pszSource);
559# define HDA_PROCESS_INTERRUPT(a_pDevIns, a_pThis) hdaProcessInterrupt((a_pDevIns), (a_pThis), __FUNCTION__)
560#else
561void hdaProcessInterrupt(PPDMDEVINS pDevIns, PHDASTATE pThis);
562# define HDA_PROCESS_INTERRUPT(a_pDevIns, a_pThis) hdaProcessInterrupt((a_pDevIns), (a_pThis))
563#endif
564/** @} */
565
566/** @name Register utility functions.
567 * @{ */
568uint8_t hdaSDFIFOWToBytes(uint16_t u16RegFIFOW);
569/** @} */
570
571/** @name Register functions.
572 * @{
573 */
574uint32_t hdaGetINTSTS(PHDASTATE pThis);
575#ifdef IN_RING3
576int hdaR3SDFMTToPCMProps(uint16_t u16SDFMT, PPDMAUDIOPCMPROPS pProps);
577#endif /* IN_RING3 */
578/** @} */
579
580/** @name BDLE (Buffer Descriptor List Entry) functions.
581 * @{
582 */
583#ifdef IN_RING3
584# ifdef LOG_ENABLED
585void hdaR3BDLEDumpAll(PPDMDEVINS pDevIns, PHDASTATE pThis, uint64_t u64BDLBase, uint16_t cBDLE);
586# endif
587#endif /* IN_RING3 */
588/** @} */
589
590#endif /* !VBOX_INCLUDED_SRC_Audio_DevHdaCommon_h */
591
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