DevHdaStream.cpp@ 89864

Last change on this file since 89864 was 89864, checked in by vboxsync, 4 years ago
DevHda: Do LPIB updates more often. Experimental code for doing DMA work on LPIB read (disabled). [build fix] bugref:9890
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 113.6 KB

Line
1	/* $Id: DevHdaStream.cpp 89864 2021-06-23 14:40:16Z vboxsync $ */
2	/** @file
3	* Intel HD Audio Controller Emulation - Streams.
4	*/
5
6	/*
7	* Copyright (C) 2017-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_HDA
23	#include <VBox/log.h>
24
25	#include <iprt/mem.h>
26	#include <iprt/semaphore.h>
27
28	#include <VBox/AssertGuest.h>
29	#include <VBox/vmm/pdmdev.h>
30	#include <VBox/vmm/pdmaudioifs.h>
31	#include <VBox/vmm/pdmaudioinline.h>
32
33	#include "AudioHlp.h"
34
35	#include "DevHda.h"
36	#include "DevHdaStream.h"
37
38	#ifdef VBOX_WITH_DTRACE
39	# include "dtrace/VBoxDD.h"
40	#endif
41
42
43	/*********************************************************************************************************************************
44	* Internal Functions *
45	*********************************************************************************************************************************/
46	#if defined(IN_RING3) \|\| defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA)
47	static void hdaStreamSetPositionAbs(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uLPIB);
48	#endif
49	#ifdef IN_RING3
50	# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
51	static void hdaR3StreamFlushDmaBounceBufferOutput(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
52	# endif
53	static uint32_t hdaR3StreamHandleDmaBufferOverrun(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink,
54	uint32_t cbNeeded, uint64_t nsNow,
55	const char *pszCaller, uint32_t const cbStreamFree);
56	static void hdaR3StreamUpdateDma(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
57	PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
58	#endif
59
60
61	#ifdef IN_RING3
62
63	/**
64	* Creates an HDA stream.
65	*
66	* @returns VBox status code.
67	* @param pStreamShared The HDA stream to construct - shared bits.
68	* @param pStreamR3 The HDA stream to construct - ring-3 bits.
69	* @param pThis The shared HDA device instance.
70	* @param pThisCC The ring-3 HDA device instance.
71	* @param uSD Stream descriptor number to assign.
72	*/
73	int hdaR3StreamConstruct(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PHDASTATE pThis, PHDASTATER3 pThisCC, uint8_t uSD)
74	{
75	pStreamR3->u8SD = uSD;
76	pStreamShared->u8SD = uSD;
77	pStreamR3->pMixSink = NULL;
78	pStreamR3->pHDAStateShared = pThis;
79	pStreamR3->pHDAStateR3 = pThisCC;
80	Assert(pStreamShared->hTimer != NIL_TMTIMERHANDLE); /* hdaR3Construct initalized this one already. */
81
82	pStreamShared->State.fInReset = false;
83	pStreamShared->State.fRunning = false;
84	# ifdef HDA_USE_DMA_ACCESS_HANDLER
85	RTListInit(&pStreamR3->State.lstDMAHandlers);
86	# endif
87
88	AssertPtr(pStreamR3->pHDAStateR3);
89	AssertPtr(pStreamR3->pHDAStateR3->pDevIns);
90
91	# ifdef DEBUG
92	int rc = RTCritSectInit(&pStreamR3->Dbg.CritSect);
93	AssertRCReturn(rc, rc);
94	# endif
95
96	const bool fIsInput = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN;
97
98	if (fIsInput)
99	{
100	pStreamShared->State.Cfg.enmPath = PDMAUDIOPATH_UNKNOWN;
101	pStreamShared->State.Cfg.enmDir = PDMAUDIODIR_IN;
102	}
103	else
104	{
105	pStreamShared->State.Cfg.enmPath = PDMAUDIOPATH_UNKNOWN;
106	pStreamShared->State.Cfg.enmDir = PDMAUDIODIR_OUT;
107	}
108
109	pStreamR3->Dbg.Runtime.fEnabled = pThisCC->Dbg.fEnabled;
110
111	if (pStreamR3->Dbg.Runtime.fEnabled)
112	{
113	char szFile[64];
114	char szPath[RTPATH_MAX];
115
116	/* pFileStream */
117	if (fIsInput)
118	RTStrPrintf(szFile, sizeof(szFile), "hdaStreamWriteSD%RU8", uSD);
119	else
120	RTStrPrintf(szFile, sizeof(szFile), "hdaStreamReadSD%RU8", uSD);
121
122	int rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
123	0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
124	AssertRC(rc2);
125
126	rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileStream);
127	AssertRC(rc2);
128
129	/* pFileDMARaw */
130	if (fIsInput)
131	RTStrPrintf(szFile, sizeof(szFile), "hdaDMARawWriteSD%RU8", uSD);
132	else
133	RTStrPrintf(szFile, sizeof(szFile), "hdaDMARawReadSD%RU8", uSD);
134
135	rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
136	0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
137	AssertRC(rc2);
138
139	rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileDMARaw);
140	AssertRC(rc2);
141
142	/* pFileDMAMapped */
143	if (fIsInput)
144	RTStrPrintf(szFile, sizeof(szFile), "hdaDMAWriteMappedSD%RU8", uSD);
145	else
146	RTStrPrintf(szFile, sizeof(szFile), "hdaDMAReadMappedSD%RU8", uSD);
147
148	rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
149	0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
150	AssertRC(rc2);
151
152	rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileDMAMapped);
153	AssertRC(rc2);
154
155	/* Delete stale debugging files from a former run. */
156	AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileStream);
157	AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileDMARaw);
158	AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileDMAMapped);
159	}
160
161	return VINF_SUCCESS;
162	}
163
164	/**
165	* Destroys an HDA stream.
166	*
167	* @param pStreamR3 The HDA stream to destroy - ring-3 bits.
168	*/
169	void hdaR3StreamDestroy(PHDASTREAMR3 pStreamR3)
170	{
171	LogFlowFunc(("[SD%RU8] Destroying ...\n", pStreamR3->u8SD));
172	int rc2;
173
174	if (pStreamR3->State.pAioRegSink)
175	{
176	rc2 = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
177	AssertRC(rc2);
178	pStreamR3->State.pAioRegSink = NULL;
179	}
180
181	if (pStreamR3->State.pCircBuf)
182	{
183	RTCircBufDestroy(pStreamR3->State.pCircBuf);
184	pStreamR3->State.pCircBuf = NULL;
185	pStreamR3->State.StatDmaBufSize = 0;
186	pStreamR3->State.StatDmaBufUsed = 0;
187	}
188
189	# ifdef DEBUG
190	if (RTCritSectIsInitialized(&pStreamR3->Dbg.CritSect))
191	{
192	rc2 = RTCritSectDelete(&pStreamR3->Dbg.CritSect);
193	AssertRC(rc2);
194	}
195	# endif
196
197	if (pStreamR3->Dbg.Runtime.fEnabled)
198	{
199	AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileStream);
200	pStreamR3->Dbg.Runtime.pFileStream = NULL;
201
202	AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileDMARaw);
203	pStreamR3->Dbg.Runtime.pFileDMARaw = NULL;
204
205	AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileDMAMapped);
206	pStreamR3->Dbg.Runtime.pFileDMAMapped = NULL;
207	}
208
209	LogFlowFuncLeave();
210	}
211
212
213	/**
214	* Appends a item to the scheduler.
215	*
216	* @returns VBox status code.
217	* @param pStreamShared The stream which scheduler should be modified.
218	* @param cbCur The period length in guest bytes.
219	* @param cbMaxPeriod The max period in guest bytes.
220	* @param idxLastBdle The last BDLE in the period.
221	* @param pHostProps The host PCM properties.
222	* @param pGuestProps The guest PCM properties.
223	* @param pcbBorrow Where to account for bytes borrowed across buffers
224	* to align scheduling items on frame boundraries.
225	*/
226	static int hdaR3StreamAddScheduleItem(PHDASTREAM pStreamShared, uint32_t cbCur, uint32_t cbMaxPeriod, uint32_t idxLastBdle,
227	PCPDMAUDIOPCMPROPS pHostProps, PCPDMAUDIOPCMPROPS pGuestProps, uint32_t *pcbBorrow)
228	{
229	/* Check that we've got room (shouldn't ever be a problem). */
230	size_t idx = pStreamShared->State.cSchedule;
231	AssertLogRelReturn(idx + 1 < RT_ELEMENTS(pStreamShared->State.aSchedule), VERR_INTERNAL_ERROR_5);
232
233	/* Figure out the BDLE range for this period. */
234	uint32_t const idxFirstBdle = idx == 0 ? 0
235	: RT_MIN((uint32_t)( pStreamShared->State.aSchedule[idx - 1].idxFirst
236	+ pStreamShared->State.aSchedule[idx - 1].cEntries),
237	idxLastBdle);
238
239	pStreamShared->State.aSchedule[idx].idxFirst = (uint8_t)idxFirstBdle;
240	pStreamShared->State.aSchedule[idx].cEntries = idxLastBdle >= idxFirstBdle
241	? idxLastBdle - idxFirstBdle + 1
242	: pStreamShared->State.cBdles - idxFirstBdle + idxLastBdle + 1;
243
244	/* Deal with borrowing due to unaligned IOC buffers. */
245	uint32_t const cbBorrowed = *pcbBorrow;
246	if (cbBorrowed < cbCur)
247	cbCur -= cbBorrowed;
248	else
249	{
250	/* Note. We can probably gloss over this, but it's not a situation a sane guest would put us, so don't bother for now. */
251	ASSERT_GUEST_MSG_FAILED(("#%u: cbBorrow=%#x cbCur=%#x BDLE[%u..%u]\n",
252	pStreamShared->u8SD, cbBorrowed, cbCur, idxFirstBdle, idxLastBdle));
253	LogRelMax(32, ("HDA: Stream #%u has a scheduling error: cbBorrow=%#x cbCur=%#x BDLE[%u..%u]\n",
254	pStreamShared->u8SD, cbBorrowed, cbCur, idxFirstBdle, idxLastBdle));
255	return VERR_OUT_OF_RANGE;
256	}
257
258	uint32_t cbCurAligned = PDMAudioPropsRoundUpBytesToFrame(pGuestProps, cbCur);
259	*pcbBorrow = cbCurAligned - cbCur;
260
261	/* Do we need to split up the period? */
262	if (cbCurAligned <= cbMaxPeriod)
263	{
264	uint32_t cbHost = PDMAudioPropsFramesToBytes(pHostProps, PDMAudioPropsBytesToFrames(pGuestProps, cbCurAligned));
265	pStreamShared->State.aSchedule[idx].cbPeriod = cbHost;
266	pStreamShared->State.aSchedule[idx].cLoops = 1;
267	}
268	else
269	{
270	/* Reduce till we've below the threshold. */
271	uint32_t cbLoop = cbCurAligned;
272	do
273	cbLoop = cbCurAligned / 2;
274	while (cbLoop > cbMaxPeriod);
275	cbLoop = PDMAudioPropsRoundUpBytesToFrame(pGuestProps, cbLoop);
276
277	/* Complete the scheduling item. */
278	uint32_t cbHost = PDMAudioPropsFramesToBytes(pHostProps, PDMAudioPropsBytesToFrames(pGuestProps, cbLoop));
279	pStreamShared->State.aSchedule[idx].cbPeriod = cbHost;
280	pStreamShared->State.aSchedule[idx].cLoops = cbCurAligned / cbLoop;
281
282	/* If there is a remainder, add it as a separate entry (this is
283	why the schedule must be more than twice the size of the BDL).*/
284	cbCurAligned %= cbLoop;
285	if (cbCurAligned)
286	{
287	pStreamShared->State.aSchedule[idx + 1] = pStreamShared->State.aSchedule[idx];
288	idx++;
289	cbHost = PDMAudioPropsFramesToBytes(pHostProps, PDMAudioPropsBytesToFrames(pGuestProps, cbCurAligned));
290	pStreamShared->State.aSchedule[idx].cbPeriod = cbHost;
291	pStreamShared->State.aSchedule[idx].cLoops = 1;
292	}
293	}
294
295	/* Done. */
296	pStreamShared->State.cSchedule = (uint16_t)(idx + 1);
297
298	return VINF_SUCCESS;
299	}
300
301	/**
302	* Creates the DMA timer schedule for the stream
303	*
304	* This is called from the stream setup code.
305	*
306	* @returns VBox status code.
307	* @param pStreamShared The stream to create a schedule for. The BDL
308	* must be loaded.
309	* @param cSegments Number of BDL segments.
310	* @param cBufferIrqs Number of the BDLEs with IOC=1.
311	* @param cbTotal The total BDL length in guest bytes.
312	* @param cbMaxPeriod Max period in guest bytes. This is in case the
313	* guest want to play the whole "Der Ring des
314	* Nibelungen" cycle in one go.
315	* @param cTimerTicksPerSec The DMA timer frequency.
316	* @param pHostProps The host PCM properties.
317	* @param pGuestProps The guest PCM properties.
318	*/
319	static int hdaR3StreamCreateSchedule(PHDASTREAM pStreamShared, uint32_t cSegments, uint32_t cBufferIrqs, uint32_t cbTotal,
320	uint32_t cbMaxPeriod, uint64_t cTimerTicksPerSec,
321	PCPDMAUDIOPCMPROPS pHostProps, PCPDMAUDIOPCMPROPS pGuestProps)
322	{
323	int rc;
324
325	/*
326	* Reset scheduling state.
327	*/
328	RT_ZERO(pStreamShared->State.aSchedule);
329	pStreamShared->State.cSchedule = 0;
330	pStreamShared->State.cSchedulePrologue = 0;
331	pStreamShared->State.idxSchedule = 0;
332	pStreamShared->State.idxScheduleLoop = 0;
333
334	/*
335	* Do the basic schedule compilation.
336	*/
337	uint32_t cPotentialPrologue = 0;
338	uint32_t cbBorrow = 0;
339	uint32_t cbCur = 0;
340	uint32_t cbMin = UINT32_MAX;
341	pStreamShared->State.aSchedule[0].idxFirst = 0;
342	for (uint32_t i = 0; i < cSegments; i++)
343	{
344	cbCur += pStreamShared->State.aBdl[i].cb;
345	if (pStreamShared->State.aBdl[i].cb < cbMin)
346	cbMin = pStreamShared->State.aBdl[i].cb;
347	if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
348	{
349	rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur, cbMaxPeriod, i, pHostProps, pGuestProps, &cbBorrow);
350	ASSERT_GUEST_RC_RETURN(rc, rc);
351
352	if (cPotentialPrologue == 0)
353	cPotentialPrologue = pStreamShared->State.cSchedule;
354	cbCur = 0;
355	}
356	}
357	AssertLogRelMsgReturn(cbBorrow == 0, ("HDA: Internal scheduling error on stream #%u: cbBorrow=%#x cbTotal=%#x cbCur=%#x\n",
358	pStreamShared->u8SD, cbBorrow, cbTotal, cbCur),
359	VERR_INTERNAL_ERROR_3);
360
361	/*
362	* Deal with any loose ends.
363	*/
364	if (cbCur && cBufferIrqs == 0)
365	{
366	/*
367	* No IOC. Vista ends up here, typically with three buffers configured.
368	*
369	* The perferred option here is to aim at processing one average BDLE with
370	* each DMA timer period, since that best matches how we update LPIB at
371	* present.
372	*
373	* The second alternative is to divide the whole span up into 3-4 periods
374	* to try increase our chances of keeping ahead of the guest. We may need
375	* to pick this if there are too few buffer descriptor or they are too small.
376	*
377	* However, what we probably should be doing is to do real DMA work whenever
378	* the guest reads a DMA related register (like LPIB) and just do 3-4 DMA
379	* timer periods, however we'll be postponing the DMA timer every time we
380	* return to ring-3 and signal the AIO, so in the end we'd probably not use
381	* the timer callback at all. (This is assuming a small shared per-stream
382	* buffer for keeping the DMA data in and that it's size will force a return
383	* to ring-3 often enough to keep the AIO thread going at a reasonable rate.)
384	*/
385	Assert(cbCur == cbTotal);
386
387	/* Match the BDLEs 1:1 if there are 3 or more and that the smallest one
388	is at least 5ms big. */
389	if (cSegments >= 3 && PDMAudioPropsBytesToMilli(pGuestProps, cbMin) >= 5 /ms/)
390	{
391	for (uint32_t i = 0; i < cSegments; i++)
392	{
393	rc = hdaR3StreamAddScheduleItem(pStreamShared, pStreamShared->State.aBdl[i].cb, cbMaxPeriod,
394	i, pHostProps, pGuestProps, &cbBorrow);
395	ASSERT_GUEST_RC_RETURN(rc, rc);
396	}
397	}
398	/* Otherwise, just divide the work into 3 or 4 portions and hope for the best.
399	It seems, though, that this only really work for windows vista if we avoid
400	working accross buffer lines. */
401	/** @todo This can be simplified/relaxed/uncluttered if we do DMA work when LPIB
402	* is read, assuming ofc that LPIB is read before each buffer update. */
403	else
404	{
405	uint32_t const cPeriods = cSegments != 3 && PDMAudioPropsBytesToMilli(pGuestProps, cbCur) >= 4 * 5 /ms/
406	? 4 : cSegments != 2 ? 3 : 2;
407	uint32_t const cbPeriod = PDMAudioPropsFloorBytesToFrame(pGuestProps, cbCur / cPeriods);
408	uint32_t iBdle = 0;
409	uint32_t offBdle = 0;
410	for (uint32_t iPeriod = 0; iPeriod < cPeriods; iPeriod++)
411	{
412	if (iPeriod + 1 < cPeriods)
413	{
414	offBdle += cbPeriod;
415	while (iBdle < cSegments && offBdle >= pStreamShared->State.aBdl[iBdle].cb)
416	offBdle -= pStreamShared->State.aBdl[iBdle++].cb;
417	rc = hdaR3StreamAddScheduleItem(pStreamShared, cbPeriod, cbMaxPeriod, offBdle != 0 ? iBdle : iBdle - 1,
418	pHostProps, pGuestProps, &cbBorrow);
419	}
420	else
421	rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur - iPeriod * cbPeriod, cbMaxPeriod, cSegments - 1,
422	pHostProps, pGuestProps, &cbBorrow);
423	ASSERT_GUEST_RC_RETURN(rc, rc);
424	}
425
426	}
427	Assert(cbBorrow == 0);
428	}
429	else if (cbCur)
430	{
431	/* The last BDLE didn't have IOC set, so we must continue processing
432	from the start till we hit one that has. */
433	uint32_t i;
434	for (i = 0; i < cSegments; i++)
435	{
436	cbCur += pStreamShared->State.aBdl[i].cb;
437	if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
438	break;
439	}
440	rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur, cbMaxPeriod, i, pHostProps, pGuestProps, &cbBorrow);
441	ASSERT_GUEST_RC_RETURN(rc, rc);
442
443	/* The initial scheduling items covering the wrap around area are
444	considered a prologue and must not repeated later. */
445	Assert(cPotentialPrologue);
446	pStreamShared->State.cSchedulePrologue = (uint8_t)cPotentialPrologue;
447	}
448
449	/*
450	* If there is just one BDLE with IOC set, we have to make sure
451	* we've got at least two periods scheduled, otherwise there is
452	* a very good chance the guest will overwrite the start of the
453	* buffer before we ever get around to reading it.
454	*/
455	if (cBufferIrqs == 1)
456	{
457	uint32_t i = pStreamShared->State.cSchedulePrologue;
458	Assert(i < pStreamShared->State.cSchedule);
459	if ( i + 1 == pStreamShared->State.cSchedule
460	&& pStreamShared->State.aSchedule[i].cLoops == 1)
461	{
462	uint32_t const cbFirstHalf = PDMAudioPropsFloorBytesToFrame(pHostProps, pStreamShared->State.aSchedule[i].cbPeriod / 2);
463	uint32_t const cbOtherHalf = pStreamShared->State.aSchedule[i].cbPeriod - cbFirstHalf;
464	pStreamShared->State.aSchedule[i].cbPeriod = cbFirstHalf;
465	if (cbFirstHalf == cbOtherHalf)
466	pStreamShared->State.aSchedule[i].cLoops = 2;
467	else
468	{
469	pStreamShared->State.aSchedule[i + 1] = pStreamShared->State.aSchedule[i];
470	pStreamShared->State.aSchedule[i].cbPeriod = cbOtherHalf;
471	pStreamShared->State.cSchedule++;
472	}
473	}
474	}
475
476	/*
477	* Go over the schduling entries and calculate the timer ticks for each period.
478	*/
479	LogRel2(("HDA: Stream #%u schedule: %u items, %u prologue\n",
480	pStreamShared->u8SD, pStreamShared->State.cSchedule, pStreamShared->State.cSchedulePrologue));
481	uint64_t const cbHostPerSec = PDMAudioPropsFramesToBytes(pHostProps, pHostProps->uHz);
482	for (uint32_t i = 0; i < pStreamShared->State.cSchedule; i++)
483	{
484	uint64_t const cTicks = ASMMultU64ByU32DivByU32(cTimerTicksPerSec, pStreamShared->State.aSchedule[i].cbPeriod,
485	cbHostPerSec);
486	AssertLogRelMsgReturn((uint32_t)cTicks == cTicks, ("cTicks=%RU64 (%#RX64)\n", cTicks, cTicks), VERR_INTERNAL_ERROR_4);
487	pStreamShared->State.aSchedule[i].cPeriodTicks = RT_MAX((uint32_t)cTicks, 16);
488	LogRel2(("HDA: #%u: %u ticks / %u bytes, %u loops, BDLE%u L %u\n", i, pStreamShared->State.aSchedule[i].cPeriodTicks,
489	pStreamShared->State.aSchedule[i].cbPeriod, pStreamShared->State.aSchedule[i].cLoops,
490	pStreamShared->State.aSchedule[i].idxFirst, pStreamShared->State.aSchedule[i].cEntries));
491	}
492
493	return VINF_SUCCESS;
494	}
495
496
497	/**
498	* Sets up ((re-)iniitalizes) an HDA stream.
499	*
500	* @returns VBox status code. VINF_NO_CHANGE if the stream does not need
501	* be set-up again because the stream's (hardware) parameters did
502	* not change.
503	* @param pDevIns The device instance.
504	* @param pThis The shared HDA device state (for HW register
505	* parameters).
506	* @param pStreamShared HDA stream to set up, shared portion.
507	* @param pStreamR3 HDA stream to set up, ring-3 portion.
508	* @param uSD Stream descriptor number to assign it.
509	*/
510	int hdaR3StreamSetUp(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD)
511	{
512	/* This must be valid all times. */
513	AssertReturn(uSD < HDA_MAX_STREAMS, VERR_INVALID_PARAMETER);
514
515	/* These member can only change on data corruption, despite what the code does further down (bird). */
516	AssertReturn(pStreamShared->u8SD == uSD, VERR_WRONG_ORDER);
517	AssertReturn(pStreamR3->u8SD == uSD, VERR_WRONG_ORDER);
518
519	const uint64_t u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, uSD),
520	HDA_STREAM_REG(pThis, BDPU, uSD));
521	const uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, uSD);
522	const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, uSD);
523	const uint8_t u8FIFOS = HDA_STREAM_REG(pThis, FIFOS, uSD) + 1;
524	uint8_t u8FIFOW = hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, uSD));
525	const uint16_t u16FMT = HDA_STREAM_REG(pThis, FMT, uSD);
526
527	/* Is the bare minimum set of registers configured for the stream?
528	* If not, bail out early, as there's nothing to do here for us (yet). */
529	if ( !u64BDLBase
530	\|\| !u16LVI
531	\|\| !u32CBL
532	\|\| !u8FIFOS
533	\|\| !u8FIFOW
534	\|\| !u16FMT)
535	{
536	LogFunc(("[SD%RU8] Registers not set up yet, skipping (re-)initialization\n", uSD));
537	return VINF_SUCCESS;
538	}
539
540	/*
541	* Convert the config to PDM PCM properties and configure the stream.
542	*/
543	PPDMAUDIOSTREAMCFG pCfg = &pStreamShared->State.Cfg;
544	int rc = hdaR3SDFMTToPCMProps(u16FMT, &pCfg->Props);
545	if (RT_SUCCESS(rc))
546	pCfg->enmDir = hdaGetDirFromSD(uSD);
547	else
548	{
549	LogRelMax(32, ("HDA: Warning: Format 0x%x for stream #%RU8 not supported\n", HDA_STREAM_REG(pThis, FMT, uSD), uSD));
550	return rc;
551	}
552
553	ASSERT_GUEST_LOGREL_MSG_RETURN( PDMAudioPropsFrameSize(&pCfg->Props) > 0
554	&& u32CBL % PDMAudioPropsFrameSize(&pCfg->Props) == 0,
555	("CBL for stream #%RU8 does not align to frame size (u32CBL=%u cbFrameSize=%u)\n",
556	uSD, u32CBL, PDMAudioPropsFrameSize(&pCfg->Props)),
557	VERR_INVALID_PARAMETER);
558
559	/* Make sure the guest behaves regarding the stream's FIFO. */
560	ASSERT_GUEST_LOGREL_MSG_STMT(u8FIFOW <= u8FIFOS,
561	("Guest tried setting a bigger FIFOW (%RU8) than FIFOS (%RU8), limiting\n", u8FIFOW, u8FIFOS),
562	u8FIFOW = u8FIFOS /* ASSUMES that u8FIFOS has been validated. */);
563
564	pStreamShared->u8SD = uSD;
565
566	/* Update all register copies so that we later know that something has changed. */
567	pStreamShared->u64BDLBase = u64BDLBase;
568	pStreamShared->u16LVI = u16LVI;
569	pStreamShared->u32CBL = u32CBL;
570	pStreamShared->u8FIFOS = u8FIFOS;
571	pStreamShared->u8FIFOW = u8FIFOW;
572	pStreamShared->u16FMT = u16FMT;
573
574	/* The the stream's name, based on the direction. */
575	switch (pCfg->enmDir)
576	{
577	case PDMAUDIODIR_IN:
578	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
579	# error "Implement me!"
580	# else
581	pCfg->enmPath = PDMAUDIOPATH_IN_LINE;
582	RTStrCopy(pCfg->szName, sizeof(pCfg->szName), "Line In");
583	# endif
584	break;
585
586	case PDMAUDIODIR_OUT:
587	/* Destination(s) will be set in hdaR3AddStreamOut(),
588	* based on the channels / stream layout. */
589	break;
590
591	default:
592	AssertFailedReturn(VERR_NOT_SUPPORTED);
593	break;
594	}
595
596	LogRel2(("HDA: Stream #%RU8 DMA @ 0x%x (%RU32 bytes = %RU64ms total)\n", uSD, pStreamShared->u64BDLBase,
597	pStreamShared->u32CBL, PDMAudioPropsBytesToMilli(&pCfg->Props, pStreamShared->u32CBL)));
598
599	/*
600	* Load the buffer descriptor list.
601	*
602	* Section 3.6.2 states that "the BDL should not be modified unless the RUN
603	* bit is 0", so it should be within the specs to read it once here and not
604	* re-read any BDLEs later.
605	*/
606	/* Reset BDL state. */
607	RT_ZERO(pStreamShared->State.aBdl);
608	pStreamShared->State.offCurBdle = 0;
609	pStreamShared->State.idxCurBdle = 0;
610
611	uint32_t /const/ cTransferFragments = (pStreamShared->u16LVI & 0xff) + 1;
612	if (cTransferFragments <= 1)
613	LogRel(("HDA: Warning: Stream #%RU8 transfer buffer count invalid: (%RU16)! Buggy guest audio driver!\n", uSD, pStreamShared->u16LVI));
614	AssertLogRelReturn(cTransferFragments <= RT_ELEMENTS(pStreamShared->State.aBdl), VERR_INTERNAL_ERROR_5);
615	pStreamShared->State.cBdles = cTransferFragments;
616
617	/* Load them. */
618	rc = PDMDevHlpPCIPhysRead(pDevIns, u64BDLBase, pStreamShared->State.aBdl,
619	sizeof(pStreamShared->State.aBdl[0]) * cTransferFragments);
620	AssertRC(rc);
621
622	/* Check what we just loaded. Refuse overly large buffer lists. */
623	uint64_t cbTotal = 0;
624	uint32_t cBufferIrqs = 0;
625	for (uint32_t i = 0; i < cTransferFragments; i++)
626	{
627	if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
628	cBufferIrqs++;
629	cbTotal += pStreamShared->State.aBdl[i].cb;
630	}
631	ASSERT_GUEST_STMT_RETURN(cbTotal < _2G,
632	LogRelMax(32, ("HDA: Error: Stream #%u is configured with an insane amount of buffer space - refusing do work with it: %RU64 (%#RX64) bytes.\n",
633	uSD, cbTotal, cbTotal)),
634	VERR_NOT_SUPPORTED);
635	ASSERT_GUEST_STMT_RETURN(cbTotal == u32CBL,
636	LogRelMax(32, ("HDA: Warning: Stream #%u has a mismatch between CBL and configured buffer space: %RU32 (%#RX32) vs %RU64 (%#RX64)\n",
637	uSD, u32CBL, u32CBL, cbTotal, cbTotal)),
638	VERR_NOT_SUPPORTED);
639
640	/*
641	* Create a DMA timer schedule.
642	*/
643	/** @todo clean up this, pGuestProps and pHostProps are the same now. */
644	rc = hdaR3StreamCreateSchedule(pStreamShared, cTransferFragments, cBufferIrqs, (uint32_t)cbTotal,
645	PDMAudioPropsMilliToBytes(&pCfg->Props, 100 /** @todo make configurable */),
646	PDMDevHlpTimerGetFreq(pDevIns, pStreamShared->hTimer),
647	&pCfg->Props, &pCfg->Props);
648	if (RT_FAILURE(rc))
649	return rc;
650
651	pStreamShared->State.cbTransferSize = pStreamShared->State.aSchedule[0].cbPeriod;
652
653	/*
654	* Calculate the transfer Hz for use in the circular buffer calculation.
655	*/
656	uint32_t cbMaxPeriod = 0;
657	uint32_t cbMinPeriod = UINT32_MAX;
658	uint32_t cPeriods = 0;
659	for (uint32_t i = 0; i < pStreamShared->State.cSchedule; i++)
660	{
661	uint32_t cbPeriod = pStreamShared->State.aSchedule[i].cbPeriod;
662	cbMaxPeriod = RT_MAX(cbMaxPeriod, cbPeriod);
663	cbMinPeriod = RT_MIN(cbMinPeriod, cbPeriod);
664	cPeriods += pStreamShared->State.aSchedule[i].cLoops;
665	}
666	uint64_t const cbTransferPerSec = RT_MAX(PDMAudioPropsFramesToBytes(&pCfg->Props, pCfg->Props.uHz),
667	4096 /* zero div prevention: min is 6kHz, picked 4k in case I'm mistaken */);
668	unsigned uTransferHz = cbTransferPerSec * 1000 / cbMaxPeriod;
669	LogRel2(("HDA: Stream #%RU8 needs a %u.%03u Hz timer rate (period: %u..%u host bytes)\n",
670	uSD, uTransferHz / 1000, uTransferHz % 1000, cbMinPeriod, cbMaxPeriod));
671	uTransferHz /= 1000;
672
673	if (uTransferHz > 400) /* Anything above 400 Hz looks fishy -- tell the user. */
674	LogRelMax(32, ("HDA: Warning: Calculated transfer Hz rate for stream #%RU8 looks incorrect (%u), please re-run with audio debug mode and report a bug\n",
675	uSD, uTransferHz));
676
677	pStreamShared->State.cbAvgTransfer = (uint32_t)(cbTotal + cPeriods - 1) / cPeriods;
678
679	/* For input streams we must determin a pre-buffering requirement.
680	We use the initial delay as a basis here, though we must have at
681	least two max periods worth of data queued up due to the way we
682	work the AIO thread. */
683	pStreamShared->State.fInputPreBuffered = false;
684	pStreamShared->State.cbInputPreBuffer = PDMAudioPropsMilliToBytes(&pCfg->Props, pThis->msInitialDelay);
685	pStreamShared->State.cbInputPreBuffer = RT_MIN(cbMaxPeriod * 2, pStreamShared->State.cbInputPreBuffer);
686
687	/*
688	* Set up data transfer stuff.
689	*/
690
691	/* Assign the global device rate to the stream I/O timer as default. */
692	pStreamShared->State.uTimerIoHz = pThis->uTimerHz;
693	ASSERT_GUEST_LOGREL_MSG_STMT(pStreamShared->State.uTimerIoHz,
694	("I/O timer Hz rate for stream #%RU8 is invalid\n", uSD),
695	pStreamShared->State.uTimerIoHz = HDA_TIMER_HZ_DEFAULT);
696
697	/* Set I/O scheduling hint for the backends. */
698	/** @todo r=bird: derive this from the schedule instead of using the
699	* uTimerIoHz, as that's almost pure non-sense now. */
700	pCfg->Device.cMsSchedulingHint = RT_MS_1SEC / pStreamShared->State.uTimerIoHz;
701	LogRel2(("HDA: Stream #%RU8 set scheduling hint for the backends to %RU32ms\n", uSD, pCfg->Device.cMsSchedulingHint));
702
703
704	/* Make sure to also update the stream's DMA counter (based on its current LPIB value). */
705	/** @todo r=bird: We use LPIB as-is here, so if it's not zero we have to
706	* locate the right place in the schedule and whatnot... */
707	if (HDA_STREAM_REG(pThis, LPIB, uSD) != 0)
708	LogRel2(("HDA: Warning! Stream #%RU8 is set up with LPIB=%#RX32 instead of zero!\n", uSD, HDA_STREAM_REG(pThis, LPIB, uSD)));
709	hdaStreamSetPositionAbs(pStreamShared, pDevIns, pThis, HDA_STREAM_REG(pThis, LPIB, uSD));
710
711	# ifdef LOG_ENABLED
712	hdaR3BDLEDumpAll(pDevIns, pThis, pStreamShared->u64BDLBase, pStreamShared->u16LVI + 1);
713	# endif
714
715	/*
716	* Set up internal ring buffer.
717	*/
718
719	/* (Re-)Allocate the stream's internal DMA buffer,
720	* based on the timing and PCM properties we just got above. */
721	if (pStreamR3->State.pCircBuf)
722	{
723	RTCircBufDestroy(pStreamR3->State.pCircBuf);
724	pStreamR3->State.pCircBuf = NULL;
725	pStreamR3->State.StatDmaBufSize = 0;
726	pStreamR3->State.StatDmaBufUsed = 0;
727	}
728	pStreamShared->State.offWrite = 0;
729	pStreamShared->State.offRead = 0;
730
731	/*
732	* The default internal ring buffer size must be:
733	*
734	* - Large enough for at least three periodic DMA transfers.
735	*
736	* It is critically important that we don't experience underruns
737	* in the DMA OUT code, because it will cause the buffer processing
738	* to get skewed and possibly overlap with what the guest is updating.
739	* At the time of writing (2021-03-05) there is no code for getting
740	* back into sync there.
741	*
742	* - Large enough for at least three I/O scheduling hints.
743	*
744	* We want to lag behind a DMA period or two, but there must be
745	* sufficent space for the AIO thread to get schedule and shuffle
746	* data thru the mixer and onto the host audio hardware.
747	*
748	* - Both above with plenty to spare.
749	*
750	* So, just take the longest of the two periods and multipling it by 6.
751	* We aren't not talking about very large base buffers heres, so size isn't
752	* an issue.
753	*
754	* Note: Use pCfg->Props as PCM properties here, as we only want to store the
755	* samples we actually need, in other words, skipping the interleaved
756	* channels we don't support / need to save space.
757	*/
758	uint32_t msCircBuf = RT_MS_1SEC * 6 / RT_MIN(uTransferHz, pStreamShared->State.uTimerIoHz);
759	msCircBuf = RT_MAX(msCircBuf, pThis->msInitialDelay + RT_MS_1SEC * 6 / uTransferHz);
760
761	uint32_t cbCircBuf = PDMAudioPropsMilliToBytes(&pCfg->Props, msCircBuf);
762	LogRel2(("HDA: Stream #%RU8 default ring buffer size is %RU32 bytes / %RU64 ms\n",
763	uSD, cbCircBuf, PDMAudioPropsBytesToMilli(&pCfg->Props, cbCircBuf)));
764
765	uint32_t msCircBufCfg = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? pThis->cMsCircBufIn : pThis->cMsCircBufOut;
766	if (msCircBufCfg) /* Anything set via CFGM? */
767	{
768	cbCircBuf = PDMAudioPropsMilliToBytes(&pCfg->Props, msCircBufCfg);
769	LogRel2(("HDA: Stream #%RU8 is using a custom ring buffer size of %RU32 bytes / %RU64 ms\n",
770	uSD, cbCircBuf, PDMAudioPropsBytesToMilli(&pCfg->Props, cbCircBuf)));
771	}
772
773	/* Serious paranoia: */
774	ASSERT_GUEST_LOGREL_MSG_STMT(cbCircBuf % PDMAudioPropsFrameSize(&pCfg->Props) == 0,
775	("Ring buffer size (%RU32) for stream #%RU8 not aligned to the (host) frame size (%RU8)\n",
776	cbCircBuf, uSD, PDMAudioPropsFrameSize(&pCfg->Props)),
777	rc = VERR_INVALID_PARAMETER);
778	ASSERT_GUEST_LOGREL_MSG_STMT(cbCircBuf, ("Ring buffer size for stream #%RU8 is invalid\n", uSD),
779	rc = VERR_INVALID_PARAMETER);
780	if (RT_SUCCESS(rc))
781	{
782	rc = RTCircBufCreate(&pStreamR3->State.pCircBuf, cbCircBuf);
783	if (RT_SUCCESS(rc))
784	{
785	pStreamR3->State.StatDmaBufSize = cbCircBuf;
786
787	/*
788	* Forward the timer frequency hint to TM as well for better accuracy on
789	* systems w/o preemption timers (also good for 'info timers').
790	*/
791	PDMDevHlpTimerSetFrequencyHint(pDevIns, pStreamShared->hTimer, uTransferHz);
792	}
793	}
794
795	if (RT_FAILURE(rc))
796	LogRelMax(32, ("HDA: Initializing stream #%RU8 failed with %Rrc\n", uSD, rc));
797
798	# ifdef VBOX_WITH_DTRACE
799	VBOXDD_HDA_STREAM_SETUP((uint32_t)uSD, rc, pStreamShared->State.Cfg.Props.uHz,
800	pStreamShared->State.aSchedule[pStreamShared->State.cSchedule - 1].cPeriodTicks,
801	pStreamShared->State.aSchedule[pStreamShared->State.cSchedule - 1].cbPeriod);
802	# endif
803	return rc;
804	}
805
806	/**
807	* Resets an HDA stream.
808	*
809	* @param pThis The shared HDA device state.
810	* @param pThisCC The ring-3 HDA device state.
811	* @param pStreamShared HDA stream to reset (shared).
812	* @param pStreamR3 HDA stream to reset (ring-3).
813	* @param uSD Stream descriptor (SD) number to use for this stream.
814	*/
815	void hdaR3StreamReset(PHDASTATE pThis, PHDASTATER3 pThisCC, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD)
816	{
817	LogFunc(("[SD%RU8] Reset\n", uSD));
818
819	/*
820	* Assert some sanity.
821	*/
822	AssertPtr(pThis);
823	AssertPtr(pStreamShared);
824	AssertPtr(pStreamR3);
825	Assert(uSD < HDA_MAX_STREAMS);
826	Assert(pStreamShared->u8SD == uSD);
827	Assert(pStreamR3->u8SD == uSD);
828	AssertMsg(!pStreamShared->State.fRunning, ("[SD%RU8] Cannot reset stream while in running state\n", uSD));
829
830	/*
831	* Set reset state.
832	*/
833	Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false); /* No nested calls. */
834	ASMAtomicXchgBool(&pStreamShared->State.fInReset, true);
835
836	/*
837	* Second, initialize the registers.
838	*/
839	/* See 6.2.33: Clear on reset. */
840	HDA_STREAM_REG(pThis, STS, uSD) = 0;
841	/* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
842	* bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
843	HDA_STREAM_REG(pThis, CTL, uSD) = HDA_SDCTL_TP \| (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_SDCTL_SRST);
844	/* ICH6 defines default values (120 bytes for input and 192 bytes for output descriptors) of FIFO size. 18.2.39. */
845	HDA_STREAM_REG(pThis, FIFOS, uSD) = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? HDA_SDIFIFO_120B : HDA_SDOFIFO_192B;
846	/* See 18.2.38: Always defaults to 0x4 (32 bytes). */
847	HDA_STREAM_REG(pThis, FIFOW, uSD) = HDA_SDFIFOW_32B;
848	HDA_STREAM_REG(pThis, LPIB, uSD) = 0;
849	HDA_STREAM_REG(pThis, CBL, uSD) = 0;
850	HDA_STREAM_REG(pThis, LVI, uSD) = 0;
851	HDA_STREAM_REG(pThis, FMT, uSD) = 0;
852	HDA_STREAM_REG(pThis, BDPU, uSD) = 0;
853	HDA_STREAM_REG(pThis, BDPL, uSD) = 0;
854
855	# ifdef HDA_USE_DMA_ACCESS_HANDLER
856	hdaR3StreamUnregisterDMAHandlers(pThis, pStream);
857	# endif
858
859	/* Assign the default mixer sink to the stream. */
860	pStreamR3->pMixSink = hdaR3GetDefaultSink(pThisCC, uSD);
861	if (pStreamR3->State.pAioRegSink)
862	{
863	int rc2 = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
864	AssertRC(rc2);
865	pStreamR3->State.pAioRegSink = NULL;
866	}
867
868	/* Reset transfer stuff. */
869	pStreamShared->State.cTransferPendingInterrupts = 0;
870	pStreamShared->State.tsTransferLast = 0;
871	pStreamShared->State.tsTransferNext = 0;
872
873	/* Initialize timestamps. */
874	pStreamShared->State.tsLastTransferNs = 0;
875	pStreamShared->State.tsLastReadNs = 0;
876	pStreamShared->State.tsAioDelayEnd = UINT64_MAX;
877	pStreamShared->State.tsStart = 0;
878
879	RT_ZERO(pStreamShared->State.aBdl);
880	RT_ZERO(pStreamShared->State.aSchedule);
881	pStreamShared->State.offCurBdle = 0;
882	pStreamShared->State.cBdles = 0;
883	pStreamShared->State.idxCurBdle = 0;
884	pStreamShared->State.cSchedulePrologue = 0;
885	pStreamShared->State.cSchedule = 0;
886	pStreamShared->State.idxSchedule = 0;
887	pStreamShared->State.idxScheduleLoop = 0;
888	pStreamShared->State.fInputPreBuffered = false;
889
890	if (pStreamR3->State.pCircBuf)
891	RTCircBufReset(pStreamR3->State.pCircBuf);
892	pStreamShared->State.offWrite = 0;
893	pStreamShared->State.offRead = 0;
894
895	# ifdef DEBUG
896	pStreamR3->Dbg.cReadsTotal = 0;
897	pStreamR3->Dbg.cbReadTotal = 0;
898	pStreamR3->Dbg.tsLastReadNs = 0;
899	pStreamR3->Dbg.cWritesTotal = 0;
900	pStreamR3->Dbg.cbWrittenTotal = 0;
901	pStreamR3->Dbg.cWritesHz = 0;
902	pStreamR3->Dbg.cbWrittenHz = 0;
903	pStreamR3->Dbg.tsWriteSlotBegin = 0;
904	# endif
905
906	/* Report that we're done resetting this stream. */
907	HDA_STREAM_REG(pThis, CTL, uSD) = 0;
908
909	# ifdef VBOX_WITH_DTRACE
910	VBOXDD_HDA_STREAM_RESET((uint32_t)uSD);
911	# endif
912	LogFunc(("[SD%RU8] Reset\n", uSD));
913
914	/* Exit reset mode. */
915	ASMAtomicXchgBool(&pStreamShared->State.fInReset, false);
916	}
917
918	/**
919	* Enables or disables an HDA audio stream.
920	*
921	* @returns VBox status code.
922	* @param pThis The shared HDA device state.
923	* @param pStreamShared HDA stream to enable or disable - shared bits.
924	* @param pStreamR3 HDA stream to enable or disable - ring-3 bits.
925	* @param fEnable Whether to enable or disble the stream.
926	*/
927	int hdaR3StreamEnable(PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, bool fEnable)
928	{
929	AssertPtr(pStreamR3);
930	AssertPtr(pStreamShared);
931
932	LogFunc(("[SD%RU8] fEnable=%RTbool, pMixSink=%p\n", pStreamShared->u8SD, fEnable, pStreamR3->pMixSink));
933
934	/* First, enable or disable the stream and the stream's sink, if any. */
935	int rc = VINF_SUCCESS;
936	PAUDMIXSINK const pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
937	if (pSink)
938	{
939	if (fEnable)
940	{
941	if (pStreamR3->State.pAioRegSink != pSink)
942	{
943	if (pStreamR3->State.pAioRegSink)
944	{
945	rc = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
946	AssertRC(rc);
947	}
948	rc = AudioMixerSinkAddUpdateJob(pSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3,
949	pStreamShared->State.Cfg.Device.cMsSchedulingHint);
950	AssertLogRelRC(rc);
951	pStreamR3->State.pAioRegSink = RT_SUCCESS(rc) ? pSink : NULL;
952	}
953	rc = AudioMixerSinkStart(pSink);
954	}
955	else
956	rc = AudioMixerSinkDrainAndStop(pSink,
957	pStreamR3->State.pCircBuf ? (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf) : 0);
958	}
959	if ( RT_SUCCESS(rc)
960	&& fEnable
961	&& pStreamR3->Dbg.Runtime.fEnabled)
962	{
963	Assert(AudioHlpPcmPropsAreValid(&pStreamShared->State.Cfg.Props));
964
965	if (fEnable)
966	{
967	if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileStream))
968	{
969	int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileStream, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
970	&pStreamShared->State.Cfg.Props);
971	AssertRC(rc2);
972	}
973
974	if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileDMARaw))
975	{
976	int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileDMARaw, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
977	&pStreamShared->State.Cfg.Props);
978	AssertRC(rc2);
979	}
980
981	if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileDMAMapped))
982	{
983	int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileDMAMapped, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
984	&pStreamShared->State.Cfg.Props);
985	AssertRC(rc2);
986	}
987	}
988	}
989
990	if (RT_SUCCESS(rc))
991	{
992	if (fEnable)
993	pStreamShared->State.tsTransferLast = 0; /* Make sure it's not stale and messes up WALCLK calculations. */
994	pStreamShared->State.fRunning = fEnable;
995
996	/*
997	* Set the FIFORDY bit when we start running and clear it when stopping.
998	*
999	* This prevents Linux from timing out in snd_hdac_stream_sync when starting
1000	* a stream. Technically, Linux also uses the SSYNC feature there, but we
1001	* can get away with just setting the FIFORDY bit for now.
1002	*/
1003	if (fEnable)
1004	HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) \|= HDA_SDSTS_FIFORDY;
1005	else
1006	HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) &= ~HDA_SDSTS_FIFORDY;
1007	}
1008
1009	LogFunc(("[SD%RU8] rc=%Rrc\n", pStreamShared->u8SD, rc));
1010	return rc;
1011	}
1012
1013	/**
1014	* Marks the stream as started.
1015	*
1016	* Used after the stream has been enabled and the DMA timer has been armed.
1017	*/
1018	void hdaR3StreamMarkStarted(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint64_t tsNow)
1019	{
1020	pStreamShared->State.tsLastReadNs = RTTimeNanoTS();
1021	pStreamShared->State.tsStart = tsNow;
1022	pStreamShared->State.tsAioDelayEnd = tsNow + PDMDevHlpTimerFromMilli(pDevIns, pStreamShared->hTimer, pThis->msInitialDelay);
1023	Log3Func(("#%u: tsStart=%RU64 tsAioDelayEnd=%RU64 tsLastReadNs=%RU64\n", pStreamShared->u8SD,
1024	pStreamShared->State.tsStart, pStreamShared->State.tsAioDelayEnd, pStreamShared->State.tsLastReadNs));
1025
1026	}
1027
1028	/**
1029	* Marks the stream as stopped.
1030	*/
1031	void hdaR3StreamMarkStopped(PHDASTREAM pStreamShared)
1032	{
1033	Log3Func(("#%u\n", pStreamShared->u8SD));
1034	pStreamShared->State.tsAioDelayEnd = UINT64_MAX;
1035	}
1036
1037	#endif /* IN_RING3 */
1038	#if defined(IN_RING3) \|\| defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA)
1039
1040	/**
1041	* Updates an HDA stream's current read or write buffer position (depending on the stream type) by
1042	* setting its associated LPIB register and DMA position buffer (if enabled) to an absolute value.
1043	*
1044	* @param pStreamShared HDA stream to update read / write position for (shared).
1045	* @param pDevIns The device instance.
1046	* @param pThis The shared HDA device state.
1047	* @param uLPIB Absolute position (in bytes) to set current read / write position to.
1048	*/
1049	static void hdaStreamSetPositionAbs(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uLPIB)
1050	{
1051	AssertPtrReturnVoid(pStreamShared);
1052	AssertMsgStmt(uLPIB <= pStreamShared->u32CBL, ("%#x\n", uLPIB), uLPIB = pStreamShared->u32CBL);
1053
1054	Log3Func(("[SD%RU8] LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n", pStreamShared->u8SD, uLPIB, pThis->fDMAPosition));
1055
1056	/* Update LPIB in any case. */
1057	HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) = uLPIB;
1058
1059	/* Do we need to tell the current DMA position? */
1060	if (pThis->fDMAPosition)
1061	{
1062	/*
1063	* Linux switched to using the position buffers some time during 2.6.x.
1064	* 2.6.12 used LPIB, 2.6.17 defaulted to DMA position buffers, between
1065	* the two version things were being changing quite a bit.
1066	*
1067	* Since 2.6.17, they will treat a zero DMA position value during the first
1068	* period/IRQ as reason to fall back to LPIB mode (see azx_position_ok in
1069	* 2.6.27+, and azx_pcm_pointer before that). They later also added
1070	* UINT32_MAX to the values causing same.
1071	*
1072	* Since 2.6.35 azx_position_ok will read the wall clock register before
1073	* determining the position.
1074	*/
1075	int rc2 = PDMDevHlpPCIPhysWrite(pDevIns,
1076	pThis->u64DPBase + (pStreamShared->u8SD * 2 * sizeof(uint32_t)),
1077	(void *)&uLPIB, sizeof(uint32_t));
1078	AssertRC(rc2);
1079	}
1080	}
1081
1082
1083	/**
1084	* Updates an HDA stream's current read or write buffer position (depending on the stream type) by
1085	* adding a value to its associated LPIB register and DMA position buffer (if enabled).
1086	*
1087	* @note Handles automatic CBL wrap-around.
1088	*
1089	* @param pStreamShared HDA stream to update read / write position for (shared).
1090	* @param pDevIns The device instance.
1091	* @param pThis The shared HDA device state.
1092	* @param cbToAdd Position (in bytes) to add to the current read / write position.
1093	*/
1094	static void hdaStreamSetPositionAdd(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t cbToAdd)
1095	{
1096	if (cbToAdd) /* No need to update anything if 0. */
1097	{
1098	uint32_t const uCBL = pStreamShared->u32CBL;
1099	if (uCBL) /* paranoia */
1100	{
1101	uint32_t uNewLpid = HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) + cbToAdd;
1102	# if 1 /** @todo r=bird: this is wrong according to the spec */
1103	uNewLpid %= uCBL;
1104	# else
1105	/* The spec says it goes to CBL then wraps arpimd to 1, not back to zero. See 3.3.37. */
1106	if (uNewLpid > uCBL)
1107	uNewLpid %= uCBL;
1108	# endif
1109	hdaStreamSetPositionAbs(pStreamShared, pDevIns, pThis, uNewLpid);
1110	}
1111	}
1112	}
1113
1114	#endif /* IN_RING3 \|\| VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
1115	#ifdef IN_RING3
1116
1117	/**
1118	* Retrieves the available size of (buffered) audio data (in bytes) of a given HDA stream.
1119	*
1120	* @returns Available data (in bytes).
1121	* @param pStreamR3 HDA stream to retrieve size for (ring-3).
1122	*/
1123	static uint32_t hdaR3StreamGetUsed(PHDASTREAMR3 pStreamR3)
1124	{
1125	AssertPtrReturn(pStreamR3, 0);
1126
1127	if (pStreamR3->State.pCircBuf)
1128	return (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1129	return 0;
1130	}
1131
1132	/**
1133	* Retrieves the free size of audio data (in bytes) of a given HDA stream.
1134	*
1135	* @returns Free data (in bytes).
1136	* @param pStreamR3 HDA stream to retrieve size for (ring-3).
1137	*/
1138	static uint32_t hdaR3StreamGetFree(PHDASTREAMR3 pStreamR3)
1139	{
1140	AssertPtrReturn(pStreamR3, 0);
1141
1142	if (pStreamR3->State.pCircBuf)
1143	return (uint32_t)RTCircBufFree(pStreamR3->State.pCircBuf);
1144	return 0;
1145	}
1146
1147	#endif /* IN_RING3 */
1148	#if defined(IN_RING3) \|\| defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA)
1149
1150	/**
1151	* Get the current address and number of bytes left in the current BDLE.
1152	*
1153	* @returns The current physical address.
1154	* @param pStreamShared The stream to check.
1155	* @param pcbLeft The number of bytes left at the returned address.
1156	*/
1157	DECLINLINE(RTGCPHYS) hdaStreamDmaBufGet(PHDASTREAM pStreamShared, uint32_t *pcbLeft)
1158	{
1159	uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1160	AssertStmt(idxBdle < pStreamShared->State.cBdles, idxBdle = 0);
1161
1162	uint32_t const cbCurBdl = pStreamShared->State.aBdl[idxBdle].cb;
1163	uint32_t offCurBdle = pStreamShared->State.offCurBdle;
1164	AssertStmt(pStreamShared->State.offCurBdle <= cbCurBdl, offCurBdle = cbCurBdl);
1165
1166	*pcbLeft = cbCurBdl - offCurBdle;
1167	return pStreamShared->State.aBdl[idxBdle].GCPhys + offCurBdle;
1168	}
1169
1170	/**
1171	* Get the size of the current BDLE.
1172	*
1173	* @returns The size (in bytes).
1174	* @param pStreamShared The stream to check.
1175	*/
1176	DECLINLINE(RTGCPHYS) hdaStreamDmaBufGetSize(PHDASTREAM pStreamShared)
1177	{
1178	uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1179	AssertStmt(idxBdle < pStreamShared->State.cBdles, idxBdle = 0);
1180	return pStreamShared->State.aBdl[idxBdle].cb;
1181	}
1182
1183	/**
1184	* Checks if the current BDLE is completed.
1185	*
1186	* @retval true if complete
1187	* @retval false if not.
1188	* @param pStreamShared The stream to check.
1189	*/
1190	DECLINLINE(bool) hdaStreamDmaBufIsComplete(PHDASTREAM pStreamShared)
1191	{
1192	uint8_t const idxBdle = pStreamShared->State.idxCurBdle;
1193	AssertReturn(idxBdle < pStreamShared->State.cBdles, true);
1194
1195	uint32_t const cbCurBdl = pStreamShared->State.aBdl[idxBdle].cb;
1196	uint32_t const offCurBdle = pStreamShared->State.offCurBdle;
1197	Assert(offCurBdle <= cbCurBdl);
1198	return offCurBdle >= cbCurBdl;
1199	}
1200
1201	/**
1202	* Checks if the current BDLE needs a completion IRQ.
1203	*
1204	* @retval true if IRQ is needed.
1205	* @retval false if not.
1206	* @param pStreamShared The stream to check.
1207	*/
1208	DECLINLINE(bool) hdaStreamDmaBufNeedsIrq(PHDASTREAM pStreamShared)
1209	{
1210	uint8_t const idxBdle = pStreamShared->State.idxCurBdle;
1211	AssertReturn(idxBdle < pStreamShared->State.cBdles, false);
1212	return (pStreamShared->State.aBdl[idxBdle].fFlags & HDA_BDLE_F_IOC) != 0;
1213	}
1214
1215	/**
1216	* Advances the DMA engine to the next BDLE.
1217	*
1218	* @param pStreamShared The stream which DMA engine is to be updated.
1219	*/
1220	DECLINLINE(void) hdaStreamDmaBufAdvanceToNext(PHDASTREAM pStreamShared)
1221	{
1222	uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1223	Assert(pStreamShared->State.offCurBdle == pStreamShared->State.aBdl[idxBdle].cb);
1224
1225	if (idxBdle < pStreamShared->State.cBdles - 1)
1226	idxBdle++;
1227	else
1228	idxBdle = 0;
1229	pStreamShared->State.idxCurBdle = idxBdle;
1230	pStreamShared->State.offCurBdle = 0;
1231	}
1232
1233	#endif /* defined(IN_RING3) \|\| defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA) */
1234	#ifdef IN_RING3
1235
1236	/**
1237	* Common do-DMA prologue code.
1238	*
1239	* @retval true if DMA processing can take place
1240	* @retval false if caller should return immediately.
1241	* @param pThis The shared HDA device state.
1242	* @param pStreamShared HDA stream to update (shared).
1243	* @param pStreamR3 HDA stream to update (ring-3).
1244	* @param uSD The stream ID (for asserting).
1245	* @param tsNowNs The current RTTimeNano() value.
1246	* @param pszFunction The function name (for logging).
1247	*/
1248	DECLINLINE(bool) hdaR3StreamDoDmaPrologue(PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD,
1249	uint64_t tsNowNs, const char *pszFunction)
1250	{
1251	RT_NOREF(uSD, pszFunction);
1252
1253	/*
1254	* Check if we should skip town...
1255	*/
1256	/* Stream not running (anymore)? */
1257	if (pStreamShared->State.fRunning)
1258	{ /* likely */ }
1259	else
1260	{
1261	Log3(("%s: [SD%RU8] Not running, skipping transfer\n", pszFunction, uSD));
1262	return false;
1263	}
1264
1265	if (!(HDA_STREAM_REG(pThis, STS, uSD) & HDA_SDSTS_BCIS))
1266	{ /* likely */ }
1267	else
1268	{
1269	/** @todo r=bird: This is a bit fishy. We should make effort the reschedule
1270	* the transfer immediately after the guest clears the interrupt.
1271	* The same fishy code is present in AC'97 with just a little
1272	* explanation as here, see @bugref{9890#c95}.
1273	*
1274	* The reasoning is probably that the developer noticed some windows
1275	* versions don't like having their BCIS interrupts bundled. There were
1276	* comments to that effect elsewhere, probably as a result of a fixed
1277	* uTimerHz approach to DMA scheduling. However, pausing DMA for a
1278	* period isn't going to help us with the host backends, as they don't
1279	* pause and will want samples ASAP. So, we should at least unpause
1280	* DMA as quickly as we possible when BCIS is cleared. We might even
1281	* not skip it iff the DMA work here doesn't involve raising any IOC,
1282	* which is possible although unlikely. */
1283	Log3(("%s: [SD%RU8] BCIS bit set, skipping transfer\n", pszFunction, uSD));
1284	STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaSkippedPendingBcis);
1285	Log(("%s: [SD%RU8] BCIS bit set, skipping transfer\n", pszFunction, uSD));
1286	# ifdef HDA_STRICT
1287	/* Timing emulation bug or guest is misbehaving -- let me know. */
1288	AssertMsgFailed(("%s: BCIS bit for stream #%RU8 still set when it shouldn't\n", pszFunction, uSD));
1289	# endif
1290	return false;
1291	}
1292
1293	/*
1294	* Stream sanity checks.
1295	*/
1296	/* Register sanity checks. */
1297	Assert(uSD < HDA_MAX_STREAMS);
1298	Assert(pStreamShared->u64BDLBase);
1299	Assert(pStreamShared->u32CBL);
1300	Assert(pStreamShared->u8FIFOS);
1301
1302	/* State sanity checks. */
1303	Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false);
1304	Assert(ASMAtomicReadBool(&pStreamShared->State.fRunning));
1305
1306	/*
1307	* Some timestamp stuff for logging/debugging.
1308	*/
1309	/const uint64_t tsNowNs = RTTimeNanoTS();/
1310	Log3(("%s: [SD%RU8] tsDeltaNs=%'RU64 ns\n", pszFunction, uSD, tsNowNs - pStreamShared->State.tsLastTransferNs));
1311	pStreamShared->State.tsLastTransferNs = tsNowNs;
1312
1313	return true;
1314	}
1315
1316	/**
1317	* Common do-DMA epilogue.
1318	*
1319	* @param pDevIns The device instance.
1320	* @param pStreamShared The HDA stream (shared).
1321	* @param pStreamR3 The HDA stream (ring-3).
1322	*/
1323	DECLINLINE(void) hdaR3StreamDoDmaEpilogue(PPDMDEVINS pDevIns, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
1324	{
1325	/*
1326	* We must update this in the epilogue rather than in the prologue
1327	* as it is used for WALCLK calculation and we must make sure the
1328	* guest doesn't think we've processed the current period till we
1329	* actually have.
1330	*/
1331	pStreamShared->State.tsTransferLast = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer);
1332
1333	/*
1334	* Update the buffer statistics.
1335	*/
1336	pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1337	}
1338
1339	#endif /* IN_RING3 */
1340
1341	#if defined(IN_RING3) \|\| defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA)
1342	/**
1343	* Completes a BDLE at the end of a DMA loop iteration, if possible.
1344	*
1345	* @retval true if buffer completed and new loaded.
1346	* @retval false if buffer not completed.
1347	* @param pDevIns The device instance.
1348	* @param pThis The shared HDA device state.
1349	* @param pStreamShared HDA stream to update (shared).
1350	* @param pszFunction The function name (for logging).
1351	*/
1352	DECLINLINE(bool) hdaStreamDoDmaMaybeCompleteBuffer(PPDMDEVINS pDevIns, PHDASTATE pThis,
1353	PHDASTREAM pStreamShared, const char *pszFunction)
1354	{
1355	RT_NOREF(pszFunction);
1356
1357	/*
1358	* Is the buffer descriptor complete.
1359	*/
1360	if (hdaStreamDmaBufIsComplete(pStreamShared))
1361	{
1362	Log3(("%s: [SD%RU8] Completed BDLE%u %#RX64 LB %#RX32 fFlags=%#x\n", pszFunction, pStreamShared->u8SD,
1363	pStreamShared->State.idxCurBdle, pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].GCPhys,
1364	pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].cb,
1365	pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].fFlags));
1366
1367	#if 0 /* Moved to the transfer loops */
1368	/*
1369	* Update the stream's current position.
1370	*
1371	* Do this as accurate and close to the actual data transfer as possible.
1372	* All guests rely on this, depending on the mechanism they use (LPIB register or DMA counters).
1373	*
1374	* Note for Windows 10: The OS' driver is very picky about when the (DMA) positions get updated!
1375	* Not doing this at the right time will result in ugly sound crackles!
1376	*/
1377	hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, hdaStreamDmaBufGetSize(pStreamShared));
1378	#endif
1379
1380	/* Does the current BDLE require an interrupt to be sent? */
1381	if (hdaStreamDmaBufNeedsIrq(pStreamShared))
1382	{
1383	/* If the IOCE ("Interrupt On Completion Enable") bit of the SDCTL
1384	register is set we need to generate an interrupt. */
1385	if (HDA_STREAM_REG(pThis, CTL, pStreamShared->u8SD) & HDA_SDCTL_IOCE)
1386	{
1387	/* Assert the interrupt before actually fetching the next BDLE below. */
1388	pStreamShared->State.cTransferPendingInterrupts = 1;
1389	Log3(("%s: [SD%RU8] Scheduling interrupt\n", pszFunction, pStreamShared->u8SD));
1390
1391	/* Trigger an interrupt first and let hdaRegWriteSDSTS() deal with
1392	* ending / beginning of a period. */
1393	/** @todo r=bird: What does the above comment mean? */
1394	HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) \|= HDA_SDSTS_BCIS;
1395	HDA_PROCESS_INTERRUPT(pDevIns, pThis);
1396	}
1397	}
1398
1399	/*
1400	* Advance to the next BDLE.
1401	*/
1402	hdaStreamDmaBufAdvanceToNext(pStreamShared);
1403	return true;
1404	}
1405
1406	Log3(("%s: [SD%RU8] Incomplete BDLE%u %#RX64 LB %#RX32 fFlags=%#x: off=%#RX32\n", pszFunction, pStreamShared->u8SD,
1407	pStreamShared->State.idxCurBdle, pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].GCPhys,
1408	pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].cb,
1409	pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].fFlags, pStreamShared->State.offCurBdle));
1410	return false;
1411	}
1412	#endif /* IN_RING3 \|\| VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
1413
1414
1415	#ifdef IN_RING3
1416
1417	/**
1418	* Does DMA transfer for an HDA input stream.
1419	*
1420	* Reads audio data from the HDA stream's internal DMA buffer and writing to
1421	* guest memory.
1422	*
1423	* @param pDevIns The device instance.
1424	* @param pThis The shared HDA device state.
1425	* @param pStreamShared HDA stream to update (shared).
1426	* @param pStreamR3 HDA stream to update (ring-3).
1427	* @param cbToConsume The max amount of data to consume from the
1428	* internal DMA buffer. The caller will make sure
1429	* this is always the transfer size fo the current
1430	* period (unless something is seriously wrong).
1431	* @param fWriteSilence Whether to feed the guest silence rather than
1432	* fetching bytes from the internal DMA buffer.
1433	* This is set initially while we pre-buffer a
1434	* little bit of input, so we can better handle
1435	* time catch-ups and other schduling fun.
1436	* @param tsNowNs The current RTTimeNano() value.
1437	*
1438	* @remarks Caller owns the stream lock.
1439	*/
1440	static void hdaR3StreamDoDmaInput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
1441	PHDASTREAMR3 pStreamR3, uint32_t const cbToConsume, bool fWriteSilence, uint64_t tsNowNs)
1442	{
1443	uint8_t const uSD = pStreamShared->u8SD;
1444	LogFlowFunc(("ENTER - #%u cbToConsume=%#x%s\n", uSD, cbToConsume, fWriteSilence ? " silence" : ""));
1445
1446	/*
1447	* Common prologue.
1448	*/
1449	if (hdaR3StreamDoDmaPrologue(pThis, pStreamShared, pStreamR3, uSD, tsNowNs, "hdaR3StreamDoDmaInput"))
1450	{ /* likely */ }
1451	else
1452	return;
1453
1454	/*
1455	*
1456	* The DMA copy loop.
1457	*
1458	*/
1459	uint8_t abBounce[4096 + 128]; /* Most guest does at most 4KB BDLE. So, 4KB + space for a partial frame to reduce loops. */
1460	uint32_t cbBounce = 0; /* in case of incomplete frames between buffer segments */
1461	PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1462	uint32_t cbLeft = cbToConsume;
1463	Assert(cbLeft == pStreamShared->State.cbTransferSize);
1464	Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1465
1466	while (cbLeft > 0)
1467	{
1468	STAM_PROFILE_START(&pThis->StatIn, a);
1469
1470	/*
1471	* Figure out how much we can read & write in this iteration.
1472	*/
1473	uint32_t cbChunk = 0;
1474	RTGCPHYS GCPhys = hdaStreamDmaBufGet(pStreamShared, &cbChunk);
1475
1476	/* If we're writing silence. */
1477	uint32_t cbWritten = 0;
1478	if (!fWriteSilence)
1479	{
1480	if (cbChunk <= cbLeft)
1481	{ /* very likely */ }
1482	else
1483	cbChunk = cbLeft;
1484
1485	/*
1486	* Write the host data directly into the guest buffers.
1487	*/
1488	while (cbChunk > 0)
1489	{
1490	/* Grab internal DMA buffer space and read into it. */
1491	void /const/ *pvBufSrc;
1492	size_t cbBufSrc;
1493	RTCircBufAcquireReadBlock(pCircBuf, cbChunk, &pvBufSrc, &cbBufSrc);
1494	AssertBreakStmt(cbBufSrc, RTCircBufReleaseReadBlock(pCircBuf, 0));
1495
1496	int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, GCPhys, pvBufSrc, cbBufSrc);
1497	AssertRC(rc2);
1498
1499	# ifdef HDA_DEBUG_SILENCE
1500	fix me if relevant;
1501	# endif
1502	if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1503	{ /* likely */ }
1504	else
1505	AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufSrc, cbBufSrc, 0 /* fFlags */);
1506
1507	# ifdef VBOX_WITH_DTRACE
1508	VBOXDD_HDA_STREAM_DMA_IN((uint32_t)uSD, (uint32_t)cbBufSrc, pStreamShared->State.offRead);
1509	# endif
1510	pStreamShared->State.offRead += cbBufSrc;
1511	RTCircBufReleaseReadBlock(pCircBuf, cbBufSrc);
1512	STAM_COUNTER_ADD(&pThis->StatBytesWritten, cbBufSrc);
1513
1514	/* advance */
1515	cbChunk -= (uint32_t)cbBufSrc;
1516	cbWritten += (uint32_t)cbBufSrc;
1517	GCPhys += cbBufSrc;
1518	pStreamShared->State.offCurBdle += (uint32_t)cbBufSrc;
1519	}
1520	}
1521	/*
1522	* We've got some initial silence to write, or we need to do
1523	* channel mapping. We produce guest output into the bounce buffer,
1524	* which is then copied into guest memory. The bounce buffer may keep
1525	* partial frames there for the next BDLE, if an BDLE isn't frame aligned.
1526	*
1527	* Note! cbLeft is relative to the input (host) frame size.
1528	* cbChunk OTOH is relative to output (guest) size.
1529	*/
1530	else
1531	{
1532	/** @todo clean up host/guest props distinction, they're the same now w/o the
1533	* mapping done by the mixer rather than us. */
1534	PCPDMAUDIOPCMPROPS pGuestProps = &pStreamShared->State.Cfg.Props;
1535	Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1536	uint32_t const cbLeftGuest = PDMAudioPropsFramesToBytes(pGuestProps,
1537	PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props,
1538	cbLeft));
1539	if (cbChunk <= cbLeftGuest)
1540	{ /* very likely */ }
1541	else
1542	cbChunk = cbLeftGuest;
1543
1544	/*
1545	* Work till we've covered the chunk.
1546	*/
1547	Log5Func(("loop0: GCPhys=%RGp cbChunk=%#x + cbBounce=%#x\n", GCPhys, cbChunk, cbBounce));
1548	while (cbChunk > 0)
1549	{
1550	/* Figure out how much we need to convert into the bounce buffer: */
1551	uint32_t cbGuest = PDMAudioPropsRoundUpBytesToFrame(pGuestProps, cbChunk - cbBounce);
1552	uint32_t cFrames = PDMAudioPropsBytesToFrames(pGuestProps, RT_MIN(cbGuest, sizeof(abBounce) - cbBounce));
1553
1554	cbGuest = PDMAudioPropsFramesToBytes(pGuestProps, cFrames);
1555	PDMAudioPropsClearBuffer(pGuestProps, &abBounce[cbBounce], cbGuest, cFrames);
1556	cbGuest += cbBounce;
1557
1558	/* Write it to the guest buffer. */
1559	uint32_t cbGuestActual = RT_MIN(cbGuest, cbChunk);
1560	int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, GCPhys, abBounce, cbGuestActual);
1561	AssertRC(rc2);
1562	STAM_COUNTER_ADD(&pThis->StatBytesWritten, cbGuestActual);
1563
1564	/* advance */
1565	cbWritten += cbGuestActual;
1566	cbChunk -= cbGuestActual;
1567	GCPhys += cbGuestActual;
1568	pStreamShared->State.offCurBdle += cbGuestActual;
1569
1570	cbBounce = cbGuest - cbGuestActual;
1571	if (cbBounce)
1572	memmove(abBounce, &abBounce[cbGuestActual], cbBounce);
1573
1574	Log5Func((" loop1: GCPhys=%RGp cbGuestActual=%#x cbBounce=%#x cFrames=%#x\n", GCPhys, cbGuestActual, cbBounce, cFrames));
1575	}
1576	Log5Func(("loop0: GCPhys=%RGp cbBounce=%#x cbLeft=%#x\n", GCPhys, cbBounce, cbLeft - cbWritten));
1577	}
1578
1579	cbLeft -= cbWritten;
1580	STAM_PROFILE_STOP(&pThis->StatIn, a);
1581
1582	/*
1583	* Complete the buffer if necessary (common with the output DMA code).
1584	*
1585	* Must update the DMA position before we do this as the buffer IRQ may
1586	* fire on another vCPU and run in parallel to us, although it is very
1587	* unlikely it can make much progress as long as we're sitting on the
1588	* lock, it could still read the DMA position (Linux won't, as it reads
1589	* WALCLK and possibly SDnSTS before the DMA position).
1590	*/
1591	hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, cbWritten);
1592	hdaStreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaR3StreamDoDmaInput");
1593	}
1594
1595	Assert(cbLeft == 0); /* There shall be no break statements in the above loop, so cbLeft is always zero here! */
1596	AssertMsg(cbBounce == 0, ("%#x\n", cbBounce));
1597
1598	/*
1599	* Common epilogue.
1600	*/
1601	hdaR3StreamDoDmaEpilogue(pDevIns, pStreamShared, pStreamR3);
1602
1603	/*
1604	* Log and leave.
1605	*/
1606	Log3Func(("LEAVE - [SD%RU8] %#RX32/%#RX32 @ %#RX64 - cTransferPendingInterrupts=%RU8\n",
1607	uSD, cbToConsume, pStreamShared->State.cbTransferSize, pStreamShared->State.offRead - cbToConsume,
1608	pStreamShared->State.cTransferPendingInterrupts));
1609	}
1610
1611
1612	/**
1613	* Input streams: Pulls data from the mixer, putting it in the internal DMA
1614	* buffer.
1615	*
1616	* @param pStreamShared HDA stream to update (shared).
1617	* @param pStreamR3 HDA stream to update (ring-3 bits).
1618	* @param pSink The mixer sink to pull from.
1619	*/
1620	static void hdaR3StreamPullFromMixer(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink)
1621	{
1622	# ifdef LOG_ENABLED
1623	uint64_t const offWriteOld = pStreamShared->State.offWrite;
1624	# endif
1625	pStreamShared->State.offWrite = AudioMixerSinkTransferToCircBuf(pSink,
1626	pStreamR3->State.pCircBuf,
1627	pStreamShared->State.offWrite,
1628	pStreamR3->u8SD,
1629	pStreamR3->Dbg.Runtime.fEnabled
1630	? pStreamR3->Dbg.Runtime.pFileStream : NULL);
1631
1632	Log3Func(("[SD%RU8] transferred=%#RX64 bytes -> @%#RX64\n", pStreamR3->u8SD,
1633	pStreamShared->State.offWrite - offWriteOld, pStreamShared->State.offWrite));
1634
1635	/* Update buffer stats. */
1636	pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1637	}
1638
1639
1640	/**
1641	* Does DMA transfer for an HDA output stream.
1642	*
1643	* This transfers one DMA timer period worth of data from the guest and into the
1644	* internal DMA buffer.
1645	*
1646	* @param pDevIns The device instance.
1647	* @param pThis The shared HDA device state.
1648	* @param pStreamShared HDA stream to update (shared).
1649	* @param pStreamR3 HDA stream to update (ring-3).
1650	* @param cbToProduce The max amount of data to produce (i.e. put into
1651	* the circular buffer). Unless something is going
1652	* seriously wrong, this will always be transfer
1653	* size for the current period.
1654	* @param tsNowNs The current RTTimeNano() value.
1655	*
1656	* @remarks Caller owns the stream lock.
1657	*/
1658	static void hdaR3StreamDoDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
1659	PHDASTREAMR3 pStreamR3, uint32_t const cbToProduce, uint64_t tsNowNs)
1660	{
1661	uint8_t const uSD = pStreamShared->u8SD;
1662	LogFlowFunc(("ENTER - #%u cbToProduce=%#x\n", uSD, cbToProduce));
1663
1664	/*
1665	* Common prologue.
1666	*/
1667	if (hdaR3StreamDoDmaPrologue(pThis, pStreamShared, pStreamR3, uSD, tsNowNs, "hdaR3StreamDoDmaOutput"))
1668	{ /* likely */ }
1669	else
1670	return;
1671
1672	/*
1673	*
1674	* The DMA copy loop.
1675	*
1676	*/
1677	# if 0
1678	uint8_t abBounce[4096 + 128]; /* Most guest does at most 4KB BDLE. So, 4KB + space for a partial frame to reduce loops. */
1679	uint32_t cbBounce = 0; /* in case of incomplete frames between buffer segments */
1680	# endif
1681	PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1682	uint32_t cbLeft = cbToProduce;
1683	# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
1684	Assert(cbLeft <= pStreamShared->State.cbTransferSize); /* a little pointless with the DMA'ing on LPIB read. */
1685	# else
1686	Assert(cbLeft == pStreamShared->State.cbTransferSize);
1687	# endif
1688	Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1689
1690	while (cbLeft > 0)
1691	{
1692	STAM_PROFILE_START(&pThis->StatOut, a);
1693
1694	/*
1695	* Figure out how much we can read & write in this iteration.
1696	*/
1697	uint32_t cbChunk = 0;
1698	RTGCPHYS GCPhys = hdaStreamDmaBufGet(pStreamShared, &cbChunk);
1699
1700	/* Need to diverge if the BDLEs contain misaligned entries. */
1701	uint32_t cbRead = 0;
1702	# if 0
1703	if (/** @todo pStreamShared->State.fFrameAlignedBuffers */)
1704	# endif
1705	{
1706	if (cbChunk <= cbLeft)
1707	{ /* very likely */ }
1708	else
1709	cbChunk = cbLeft;
1710
1711	/*
1712	* Read the guest data directly into the internal DMA buffer.
1713	*/
1714	while (cbChunk > 0)
1715	{
1716	/* Grab internal DMA buffer space and read into it. */
1717	void *pvBufDst;
1718	size_t cbBufDst;
1719	RTCircBufAcquireWriteBlock(pCircBuf, cbChunk, &pvBufDst, &cbBufDst);
1720	AssertBreakStmt(cbBufDst, RTCircBufReleaseWriteBlock(pCircBuf, 0));
1721
1722	int rc2 = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, pvBufDst, cbBufDst);
1723	AssertRC(rc2);
1724
1725	# ifdef HDA_DEBUG_SILENCE
1726	fix me if relevant;
1727	# endif
1728	if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1729	{ /* likely */ }
1730	else
1731	AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst, 0 /* fFlags */);
1732
1733	# ifdef VBOX_WITH_DTRACE
1734	VBOXDD_HDA_STREAM_DMA_OUT((uint32_t)uSD, (uint32_t)cbBufDst, pStreamShared->State.offWrite);
1735	# endif
1736	pStreamShared->State.offWrite += cbBufDst;
1737	RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
1738	STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBufDst);
1739
1740	/* advance */
1741	cbChunk -= (uint32_t)cbBufDst;
1742	cbRead += (uint32_t)cbBufDst;
1743	GCPhys += cbBufDst;
1744	pStreamShared->State.offCurBdle += (uint32_t)cbBufDst;
1745	}
1746	}
1747	# if 0
1748	/*
1749	* Need to map the frame content, so we need to read the guest data
1750	* into a temporary buffer, though the output can be directly written
1751	* into the internal buffer as it is assumed to be frame aligned.
1752	*
1753	* Note! cbLeft is relative to the output frame size.
1754	* cbChunk OTOH is relative to input size.
1755	*/
1756	else
1757	{
1758	/** @todo clean up host/guest props distinction, they're the same now w/o the
1759	* mapping done by the mixer rather than us. */
1760	PCPDMAUDIOPCMPROPS pGuestProps = &pStreamShared->State.Cfg.Props;
1761	Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1762	uint32_t const cbLeftGuest = PDMAudioPropsFramesToBytes(pGuestProps,
1763	PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props,
1764	cbLeft));
1765	if (cbChunk <= cbLeftGuest)
1766	{ /* very likely */ }
1767	else
1768	cbChunk = cbLeftGuest;
1769
1770	/*
1771	* Loop till we've covered the chunk.
1772	*/
1773	Log5Func(("loop0: GCPhys=%RGp cbChunk=%#x + cbBounce=%#x\n", GCPhys, cbChunk, cbBounce));
1774	while (cbChunk > 0)
1775	{
1776	/* Read into the bounce buffer. */
1777	uint32_t const cbToRead = RT_MIN(cbChunk, sizeof(abBounce) - cbBounce);
1778	int rc2 = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &abBounce[cbBounce], cbToRead);
1779	AssertRC(rc2);
1780	cbBounce += cbToRead;
1781
1782	/* Convert the size to whole frames and a remainder. */
1783	uint32_t cFrames = PDMAudioPropsBytesToFrames(pGuestProps, cbBounce);
1784	uint32_t const cbRemainder = cbBounce - PDMAudioPropsFramesToBytes(pGuestProps, cFrames);
1785	Log5Func((" loop1: GCPhys=%RGp cbToRead=%#x cbBounce=%#x cFrames=%#x\n", GCPhys, cbToRead, cbBounce, cFrames));
1786
1787	/*
1788	* Convert from the bounce buffer and into the internal DMA buffer.
1789	*/
1790	uint32_t offBounce = 0;
1791	while (cFrames > 0)
1792	{
1793	void *pvBufDst;
1794	size_t cbBufDst;
1795	RTCircBufAcquireWriteBlock(pCircBuf, PDMAudioPropsFramesToBytes(&pStreamShared->State.Cfg.Props, cFrames),
1796	&pvBufDst, &cbBufDst);
1797
1798	uint32_t const cFramesToConvert = PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props, (uint32_t)cbBufDst);
1799	Assert(PDMAudioPropsFramesToBytes(&pStreamShared->State.Cfg.Props, cFramesToConvert) == cbBufDst);
1800	Assert(cFramesToConvert > 0);
1801	Assert(cFramesToConvert <= cFrames);
1802
1803	pStreamR3->State.Mapping.pfnGuestToHost(pvBufDst, &abBounce[offBounce], cFramesToConvert,
1804	&pStreamR3->State.Mapping);
1805	Log5Func((" loop2: offBounce=%#05x cFramesToConvert=%#05x cbBufDst=%#x%s\n",
1806	offBounce, cFramesToConvert, cbBufDst, ASMMemIsZero(pvBufDst, cbBufDst) ? " all zero" : ""));
1807
1808	# ifdef HDA_DEBUG_SILENCE
1809	fix me if relevant;
1810	# endif
1811	if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1812	{ /* likely */ }
1813	else
1814	AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst, 0 /* fFlags */);
1815
1816	pStreamR3->State.offWrite += cbBufDst;
1817	RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
1818	STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBufDst);
1819
1820	/* advance */
1821	cbLeft -= (uint32_t)cbBufDst;
1822	cFrames -= cFramesToConvert;
1823	offBounce += PDMAudioPropsFramesToBytes(pGuestProps, cFramesToConvert);
1824	}
1825
1826	/* advance */
1827	cbChunk -= cbToRead;
1828	GCPhys += cbToRead;
1829	pStreamShared->State.offCurBdle += cbToRead;
1830	if (cbRemainder)
1831	memmove(&abBounce[0], &abBounce[cbBounce - cbRemainder], cbRemainder);
1832	cbBounce = cbRemainder;
1833	}
1834	Log5Func(("loop0: GCPhys=%RGp cbBounce=%#x cbLeft=%#x\n", GCPhys, cbBounce, cbLeft));
1835	}
1836	# endif
1837
1838	cbLeft -= cbRead;
1839	STAM_PROFILE_STOP(&pThis->StatOut, a);
1840
1841	/*
1842	* Complete the buffer if necessary (common with the input DMA code).
1843	*
1844	* Must update the DMA position before we do this as the buffer IRQ may
1845	* fire on another vCPU and run in parallel to us, although it is very
1846	* unlikely it can make much progress as long as we're sitting on the
1847	* lock, it could still read the DMA position (Linux won't, as it reads
1848	* WALCLK and possibly SDnSTS before the DMA position).
1849	*/
1850	hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, cbRead);
1851	hdaStreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaR3StreamDoDmaOutput");
1852	}
1853
1854	Assert(cbLeft == 0); /* There shall be no break statements in the above loop, so cbLeft is always zero here! */
1855	# if 0
1856	AssertMsg(cbBounce == 0, ("%#x\n", cbBounce));
1857	# endif
1858
1859	/*
1860	* Common epilogue.
1861	*/
1862	hdaR3StreamDoDmaEpilogue(pDevIns, pStreamShared, pStreamR3);
1863
1864	/*
1865	* Log and leave.
1866	*/
1867	Log3Func(("LEAVE - [SD%RU8] %#RX32/%#RX32 @ %#RX64 - cTransferPendingInterrupts=%RU8\n",
1868	uSD, cbToProduce, pStreamShared->State.cbTransferSize, pStreamShared->State.offWrite - cbToProduce,
1869	pStreamShared->State.cTransferPendingInterrupts));
1870	}
1871
1872	#endif /* IN_RING3 */
1873
1874	#ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
1875	/**
1876	* Do DMA output transfer on LPIB register access.
1877	*
1878	* @returns VINF_SUCCESS or VINF_IOM_R3_MMIO_READ.
1879	* @param pDevIns The device instance.
1880	* @param pThis The shared instance data.
1881	* @param pStreamShared The shared stream data.
1882	* @param cbToTransfer How much to transfer.
1883	*/
1884	VBOXSTRICTRC hdaStreamDoOnAccessDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint32_t cbToTransfer)
1885	{
1886	AssertReturn(cbToTransfer > 0, VINF_SUCCESS);
1887	int rc = VINF_SUCCESS;
1888
1889	/*
1890	* Check if we're exceeding the available buffer, go to ring-3 to
1891	* handle that (we would perhaps always take this path when in ring-3).
1892	*/
1893	uint32_t cbDma = pStreamShared->State.cbDma;
1894	ASMCompilerBarrier();
1895	if ( cbDma >= sizeof(pStreamShared->State.abDma) /* paranoia */
1896	\|\| cbToTransfer >= sizeof(pStreamShared->State.abDma) /* paranoia */
1897	\|\| cbDma + cbToTransfer > sizeof(pStreamShared->State.abDma))
1898	{
1899	# ifndef IN_RING3
1900	STAM_REL_COUNTER_INC(&pThis->StatAccessDmaOutputToR3);
1901	LogFlowFunc(("[SD%RU8] out of DMA buffer space (%#x, need %#x) -> VINF_IOM_R3_MMIO_READ\n",
1902	pStreamShared->u8SD, sizeof(pStreamShared->State.abDma) - pStreamShared->State.cbDma, cbToTransfer));
1903	return VINF_IOM_R3_MMIO_READ;
1904	# else /* IN_RING3 */
1905	/*
1906	* Flush the bounce buffer, then do direct transfers to the
1907	* internal DMA buffer (updates LPIB).
1908	*/
1909	PHDASTATER3 const pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
1910	uintptr_t const idxStream = pStreamShared->u8SD;
1911	AssertReturn(idxStream < RT_ELEMENTS(pThisCC->aStreams), VERR_INTERNAL_ERROR_4);
1912	PHDASTREAMR3 const pStreamR3 = &pThisCC->aStreams[idxStream];
1913
1914	hdaR3StreamFlushDmaBounceBufferOutput(pStreamShared, pStreamR3);
1915
1916	uint32_t cbStreamFree = hdaR3StreamGetFree(pStreamR3);
1917	if (cbStreamFree >= cbToTransfer)
1918	{ /* likely */ }
1919	else
1920	{
1921	PAUDMIXSINK pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
1922	if (pSink)
1923	cbStreamFree = hdaR3StreamHandleDmaBufferOverrun(pStreamShared, pStreamR3, pSink, cbToTransfer, RTTimeNanoTS(),
1924	"hdaStreamDoOnAccessDmaOutput", cbStreamFree);
1925	else
1926	{
1927	LogFunc(("[SD%RU8] No sink and insufficient internal DMA buffer space (%#x) - won't do anything\n",
1928	pStreamShared->u8SD, cbStreamFree));
1929	return VINF_SUCCESS;
1930	}
1931	cbToTransfer = RT_MIN(cbToTransfer, cbStreamFree);
1932	if (cbToTransfer < PDMAudioPropsFrameSize(&pStreamShared->State.Cfg.Props))
1933	{
1934	LogFunc(("[SD%RU8] No internal DMA buffer space (%#x) - won't do anything\n", pStreamShared->u8SD, cbStreamFree));
1935	return VINF_SUCCESS;
1936	}
1937	}
1938	hdaR3StreamDoDmaOutput(pDevIns, pThis, pStreamShared, pStreamR3, cbToTransfer, RTTimeNanoTS());
1939	pStreamShared->State.cbDmaTotal += cbToTransfer;
1940	# endif /* IN_RING3 */
1941	}
1942	else
1943	{
1944	/*
1945	* Transfer into the DMA bounce buffer.
1946	*/
1947	LogFlowFunc(("[SD%RU8] Transfering %#x bytes to DMA bounce buffer (cbDma=%#x cbDmaTotal=%#x) (%p/%u)\n",
1948	pStreamShared->u8SD, cbToTransfer, cbDma, pStreamShared->State.cbDmaTotal, pStreamShared, pStreamShared->u8SD));
1949	uint32_t cbLeft = cbToTransfer;
1950	do
1951	{
1952	uint32_t cbChunk = 0;
1953	RTGCPHYS GCPhys = hdaStreamDmaBufGet(pStreamShared, &cbChunk);
1954
1955	bool fMustAdvanceBuffer;
1956	if (cbLeft < cbChunk)
1957	{
1958	fMustAdvanceBuffer = false;
1959	cbChunk = cbLeft;
1960	}
1961	else
1962	fMustAdvanceBuffer = true;
1963
1964	/* Read the guest data directly into the DMA bounce buffer. */
1965	int rc2 = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &pStreamShared->State.abDma[cbDma], cbChunk);
1966	AssertRC(rc2);
1967
1968	/* We update offWrite and StatBytesRead here even if we haven't moved the data
1969	to the internal DMA buffer yet, because we want the dtrace even to fire here. */
1970	# ifdef VBOX_WITH_DTRACE
1971	VBOXDD_HDA_STREAM_DMA_OUT((uint32_t)pStreamShared->u8SD, cbChunk, pStreamShared->State.offWrite);
1972	# endif
1973	pStreamShared->State.offWrite += cbChunk;
1974	STAM_COUNTER_ADD(&pThis->StatBytesRead, cbChunk);
1975
1976	/* advance */
1977	pStreamShared->State.offCurBdle += cbChunk;
1978	pStreamShared->State.cbDmaTotal += cbChunk;
1979	cbDma += cbChunk;
1980	pStreamShared->State.cbDma = cbDma;
1981	cbLeft -= cbChunk;
1982	Log6Func(("cbLeft=%#x cbDma=%#x cbDmaTotal=%#x offCurBdle=%#x idxCurBdle=%#x (%p/%u)\n",
1983	cbLeft, cbDma, pStreamShared->State.cbDmaTotal, pStreamShared->State.offCurBdle,
1984	pStreamShared->State.idxCurBdle, pStreamShared, pStreamShared->u8SD));
1985
1986	/* Next buffer. */
1987	bool fAdvanced = hdaStreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaStreamDoOnAccessDmaOutput");
1988	AssertMsgStmt(fMustAdvanceBuffer == fAdvanced, ("%d %d\n", fMustAdvanceBuffer, fAdvanced), rc = VERR_INTERNAL_ERROR_3);
1989	} while (cbLeft > 0);
1990
1991	/*
1992	* Advance LPIB.
1993	*/
1994	hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, cbToTransfer - cbLeft);
1995	}
1996
1997	# ifdef VBOX_STRICT
1998	uint32_t idxSched = pStreamShared->State.idxSchedule;
1999	AssertStmt(idxSched < RT_MIN(RT_ELEMENTS(pStreamShared->State.aSchedule), pStreamShared->State.cSchedule), idxSched = 0);
2000	uint32_t const cbPeriod = pStreamShared->State.aSchedule[idxSched].cbPeriod;
2001	AssertMsg(pStreamShared->State.cbDmaTotal < cbPeriod, ("%#x vs %#x\n", pStreamShared->State.cbDmaTotal, cbPeriod));
2002	# endif
2003
2004	STAM_REL_COUNTER_INC(&pThis->StatAccessDmaOutput);
2005	return rc;
2006	}
2007	#endif /* VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
2008
2009
2010	#ifdef IN_RING3
2011
2012	/**
2013	* Output streams: Pushes data to the mixer.
2014	*
2015	* @param pStreamShared HDA stream to update (shared bits).
2016	* @param pStreamR3 HDA stream to update (ring-3 bits).
2017	* @param pSink The mixer sink to push to.
2018	* @param nsNow The current RTTimeNanoTS() value.
2019	*/
2020	static void hdaR3StreamPushToMixer(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink, uint64_t nsNow)
2021	{
2022	# ifdef LOG_ENABLED
2023	uint64_t const offReadOld = pStreamShared->State.offRead;
2024	# endif
2025	pStreamShared->State.offRead = AudioMixerSinkTransferFromCircBuf(pSink,
2026	pStreamR3->State.pCircBuf,
2027	pStreamShared->State.offRead,
2028	pStreamR3->u8SD,
2029	pStreamR3->Dbg.Runtime.fEnabled
2030	? pStreamR3->Dbg.Runtime.pFileStream : NULL);
2031
2032	Assert(nsNow >= pStreamShared->State.tsLastReadNs);
2033	Log3Func(("[SD%RU8] nsDeltaLastRead=%RI64 transferred=%#RX64 bytes -> @%#RX64\n", pStreamR3->u8SD,
2034	nsNow - pStreamShared->State.tsLastReadNs, pStreamShared->State.offRead - offReadOld, pStreamShared->State.offRead));
2035	RT_NOREF(pStreamShared, nsNow);
2036
2037	/* Update buffer stats. */
2038	pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
2039	}
2040
2041
2042	/**
2043	* Deals with a DMA buffer overrun.
2044	*
2045	* Makes sure we return with @a cbNeeded bytes of free space in pCircBuf.
2046	*
2047	* @returns Number of bytes free in the internal DMA buffer.
2048	* @param pStreamShared The shared data for the HDA stream.
2049	* @param pStreamR3 The ring-3 data for the HDA stream.
2050	* @param pSink The mixer sink (valid).
2051	* @param cbNeeded How much space we need (in bytes).
2052	* @param nsNow Current RTNanoTimeTS() timestamp.
2053	* @param cbStreamFree The current amount of free buffer space.
2054	* @param pszCaller The caller (for logging).
2055	*/
2056	static uint32_t hdaR3StreamHandleDmaBufferOverrun(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink,
2057	uint32_t cbNeeded, uint64_t nsNow,
2058	const char *pszCaller, uint32_t const cbStreamFree)
2059	{
2060	STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowProblems);
2061	Log(("%s: Warning! Stream #%u has insufficient space free: %#x bytes, need %#x. Will try move data out of the buffer...\n",
2062	pszCaller, pStreamShared->u8SD, cbStreamFree, cbNeeded));
2063	RT_NOREF(pszCaller, cbStreamFree);
2064
2065	int rc = AudioMixerSinkTryLock(pSink);
2066	if (RT_SUCCESS(rc))
2067	{
2068	hdaR3StreamPushToMixer(pStreamShared, pStreamR3, pSink, nsNow);
2069	AudioMixerSinkUpdate(pSink, 0, 0);
2070	AudioMixerSinkUnlock(pSink);
2071	}
2072	else
2073	RTThreadYield();
2074
2075	uint32_t const cbRet = hdaR3StreamGetFree(pStreamR3);
2076	Log(("%s: Gained %u bytes.\n", pszCaller, cbRet - cbStreamFree));
2077	if (cbRet >= cbNeeded)
2078	return cbRet;
2079
2080	/*
2081	* Unable to make sufficient space. Drop the whole buffer content.
2082	*
2083	* This is needed in order to keep the device emulation running at a
2084	* constant rate, at the cost of losing valid (but too much) data.
2085	*/
2086	STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowErrors);
2087	LogRel2(("HDA: Warning: Hit stream #%RU8 overflow, dropping %u bytes of audio data (%s)\n",
2088	pStreamShared->u8SD, hdaR3StreamGetUsed(pStreamR3), pszCaller));
2089	# ifdef HDA_STRICT
2090	AssertMsgFailed(("Hit stream #%RU8 overflow -- timing bug?\n", pStreamShared->u8SD));
2091	# endif
2092	/**
2093	*
2094	* @todo r=bird: I don't think RTCircBufReset is entirely safe w/o
2095	* owning the AIO lock. See the note in the documentation about it not being
2096	* multi-threading aware (safe). Wish I'd verified this code much earlier.
2097	* Sigh^3!
2098	*
2099	*/
2100	RTCircBufReset(pStreamR3->State.pCircBuf);
2101	pStreamShared->State.offWrite = 0;
2102	pStreamShared->State.offRead = 0;
2103	return hdaR3StreamGetFree(pStreamR3);
2104	}
2105
2106
2107	# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
2108	/**
2109	* Flushes the DMA bounce buffer content to the internal DMA buffer.
2110	*
2111	* @param pStreamShared The shared data of the stream to have its DMA bounce
2112	* buffer flushed.
2113	* @param pStreamR3 The ring-3 stream data for same.
2114	*/
2115	static void hdaR3StreamFlushDmaBounceBufferOutput(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
2116	{
2117	uint32_t cbDma = pStreamShared->State.cbDma;
2118	LogFlowFunc(("cbDma=%#x\n", cbDma));
2119	if (cbDma)
2120	{
2121	AssertReturnVoid(cbDma <= sizeof(pStreamShared->State.abDma));
2122	PRTCIRCBUF const pCircBuf = pStreamR3->State.pCircBuf;
2123	if (pCircBuf)
2124	{
2125	uint32_t offDma = 0;
2126	while (offDma < cbDma)
2127	{
2128	uint32_t const cbSrcLeft = cbDma - offDma;
2129
2130	/*
2131	* Grab a chunk of the internal DMA buffer.
2132	*/
2133	void *pvBufDst = NULL;
2134	size_t cbBufDst = 0;
2135	RTCircBufAcquireWriteBlock(pCircBuf, cbSrcLeft, &pvBufDst, &cbBufDst);
2136	if (cbBufDst > 0)
2137	{ /* likely */ }
2138	else
2139	{
2140	/* We've got buffering trouble. */
2141	RTCircBufReleaseWriteBlock(pCircBuf, 0);
2142
2143	PAUDMIXSINK pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
2144	if (pSink)
2145	hdaR3StreamHandleDmaBufferOverrun(pStreamShared, pStreamR3, pSink, cbSrcLeft, RTTimeNanoTS(),
2146	"hdaR3StreamFlushDmaBounceBufferOutput", 0 /cbStreamFree/);
2147	else
2148	{
2149	LogFunc(("Stream #%u has no sink. Dropping the rest of the data\n", pStreamR3->u8SD));
2150	break;
2151	}
2152
2153	RTCircBufAcquireWriteBlock(pCircBuf, cbSrcLeft, &pvBufDst, &cbBufDst);
2154	AssertBreakStmt(cbBufDst, RTCircBufReleaseWriteBlock(pCircBuf, 0));
2155	}
2156
2157	/*
2158	* Copy the samples into it and write it to the debug file if open.
2159	*
2160	* We do not fire the dtrace probe here nor update offRead as that was
2161	* done already (not sure that was a good idea?).
2162	*/
2163	memcpy(pvBufDst, &pStreamShared->State.abDma[offDma], cbBufDst);
2164
2165	if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
2166	{ /* likely */ }
2167	else
2168	AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst, 0 /* fFlags */);
2169
2170	RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
2171
2172	offDma += (uint32_t)cbBufDst;
2173	}
2174	}
2175
2176	/*
2177	* Mark the buffer empty.
2178	*/
2179	pStreamShared->State.cbDma = 0;
2180	}
2181	}
2182	# endif /* VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
2183
2184
2185	/**
2186	* The stream's main function when called by the timer.
2187	*
2188	* @note This function also will be called without timer invocation when
2189	* starting (enabling) the stream to minimize startup latency.
2190	*
2191	* @returns Current timer time if the timer is enabled, otherwise zero.
2192	* @param pDevIns The device instance.
2193	* @param pThis The shared HDA device state.
2194	* @param pThisCC The ring-3 HDA device state.
2195	* @param pStreamShared HDA stream to update (shared bits).
2196	* @param pStreamR3 HDA stream to update (ring-3 bits).
2197	*/
2198	uint64_t hdaR3StreamTimerMain(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
2199	PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
2200	{
2201	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2202	Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pStreamShared->hTimer));
2203
2204	/* Do the work: */
2205	hdaR3StreamUpdateDma(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3);
2206
2207	/* Re-arm the timer if the sink is still active: */
2208	if ( pStreamShared->State.fRunning
2209	&& pStreamR3->pMixSink
2210	&& AudioMixerSinkIsActive(pStreamR3->pMixSink->pMixSink))
2211	{
2212	/* Advance the schduling: */
2213	uint32_t idxSched = pStreamShared->State.idxSchedule;
2214	AssertStmt(idxSched < RT_ELEMENTS(pStreamShared->State.aSchedule), idxSched = 0);
2215	uint32_t idxLoop = pStreamShared->State.idxScheduleLoop + 1;
2216	if (idxLoop >= pStreamShared->State.aSchedule[idxSched].cLoops)
2217	{
2218	idxSched += 1;
2219	if ( idxSched >= pStreamShared->State.cSchedule
2220	\|\| idxSched >= RT_ELEMENTS(pStreamShared->State.aSchedule) /paranoia^2/)
2221	{
2222	idxSched = pStreamShared->State.cSchedulePrologue;
2223	AssertStmt(idxSched < RT_ELEMENTS(pStreamShared->State.aSchedule), idxSched = 0);
2224	}
2225	pStreamShared->State.idxSchedule = idxSched;
2226	idxLoop = 0;
2227	}
2228	pStreamShared->State.idxScheduleLoop = (uint16_t)idxLoop;
2229
2230	/* Do the actual timer re-arming. */
2231	uint64_t const tsNow = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer); /* (For virtual sync this remains the same for the whole callout IIRC) */
2232	uint64_t const tsTransferNext = tsNow + pStreamShared->State.aSchedule[idxSched].cPeriodTicks;
2233	Log3Func(("[SD%RU8] fSinkActive=true, tsTransferNext=%RU64 (in %RU64)\n",
2234	pStreamShared->u8SD, tsTransferNext, tsTransferNext - tsNow));
2235	int rc = PDMDevHlpTimerSet(pDevIns, pStreamShared->hTimer, tsTransferNext);
2236	AssertRC(rc);
2237
2238	/* Some legacy stuff: */
2239	pStreamShared->State.tsTransferNext = tsTransferNext;
2240	pStreamShared->State.cbTransferSize = pStreamShared->State.aSchedule[idxSched].cbPeriod;
2241
2242	return tsNow;
2243	}
2244
2245	Log3Func(("[SD%RU8] fSinkActive=false\n", pStreamShared->u8SD));
2246	return 0;
2247	}
2248
2249
2250	/**
2251	* Updates a HDA stream by doing DMA transfers.
2252	*
2253	* Will do mixer transfers too to try fix an overrun/underrun situation.
2254	*
2255	* The host sink(s) set the overall pace (bird: no it doesn't, the DMA timer
2256	* does - we just hope like heck it matches the speed at which the backend
2257	* host audio driver processes samples).
2258	*
2259	* @param pDevIns The device instance.
2260	* @param pThis The shared HDA device state.
2261	* @param pThisCC The ring-3 HDA device state.
2262	* @param pStreamShared HDA stream to update (shared bits).
2263	* @param pStreamR3 HDA stream to update (ring-3 bits).
2264	*/
2265	static void hdaR3StreamUpdateDma(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
2266	PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
2267	{
2268	RT_NOREF(pThisCC);
2269	int rc2;
2270
2271	/*
2272	* Make sure we're running and got an active mixer sink.
2273	*/
2274	if (RT_LIKELY(pStreamShared->State.fRunning))
2275	{ /* likely */ }
2276	else
2277	return;
2278
2279	PAUDMIXSINK pSink = NULL;
2280	if (pStreamR3->pMixSink)
2281	pSink = pStreamR3->pMixSink->pMixSink;
2282	if (RT_LIKELY(AudioMixerSinkIsActive(pSink)))
2283	{ /* likely */ }
2284	else
2285	return;
2286
2287	/*
2288	* Get scheduling info common to both input and output streams.
2289	*/
2290	const uint64_t tsNowNs = RTTimeNanoTS();
2291	uint32_t idxSched = pStreamShared->State.idxSchedule;
2292	AssertStmt(idxSched < RT_MIN(RT_ELEMENTS(pStreamShared->State.aSchedule), pStreamShared->State.cSchedule), idxSched = 0);
2293	uint32_t cbPeriod = pStreamShared->State.aSchedule[idxSched].cbPeriod;
2294
2295	/*
2296	* Output streams (SDO).
2297	*/
2298	if (hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_OUT)
2299	{
2300	# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
2301	/* Subtract already transferred bytes and flush the DMA bounce buffer. */
2302	uint32_t cbDmaTotal = pStreamShared->State.cbDmaTotal;
2303	if (cbDmaTotal > 0)
2304	{
2305	AssertStmt(cbDmaTotal < cbPeriod, cbDmaTotal = cbPeriod);
2306	cbPeriod -= cbDmaTotal;
2307	pStreamShared->State.cbDmaTotal = 0;
2308	hdaR3StreamFlushDmaBounceBufferOutput(pStreamShared, pStreamR3);
2309	}
2310	else
2311	Assert(pStreamShared->State.cbDma == 0);
2312	# endif
2313
2314	/*
2315	* Check how much room we have in our DMA buffer. There should be at
2316	* least one period worth of space there or we're in an overflow situation.
2317	*/
2318	uint32_t cbStreamFree = hdaR3StreamGetFree(pStreamR3);
2319	if (cbStreamFree >= cbPeriod)
2320	{ /* likely */ }
2321	else
2322	cbStreamFree = hdaR3StreamHandleDmaBufferOverrun(pStreamShared, pStreamR3, pSink, cbPeriod, tsNowNs,
2323	"hdaR3StreamUpdateDma", cbStreamFree);
2324
2325	/*
2326	* Do the DMA transfer.
2327	*/
2328	uint64_t const offWriteBefore = pStreamShared->State.offWrite;
2329	hdaR3StreamDoDmaOutput(pDevIns, pThis, pStreamShared, pStreamR3, RT_MIN(cbStreamFree, cbPeriod), tsNowNs);
2330
2331	/*
2332	* Should we push data to down thru the mixer to and to the host drivers?
2333	*
2334	* We initially delay this by pThis->msInitialDelay, but after than we'll
2335	* kick the AIO thread every time we've put more data in the buffer (which is
2336	* every time) as the host audio device needs to get data in a timely manner.
2337	*
2338	* (We used to try only wake up the AIO thread according to pThis->uIoTimer
2339	* and host wall clock, but that meant we would miss a wakup after the DMA
2340	* timer was called a little late or if TM entered into catch-up mode.)
2341	*/
2342	bool fKickAioThread;
2343	if (!pStreamShared->State.tsAioDelayEnd)
2344	fKickAioThread = pStreamShared->State.offWrite > offWriteBefore
2345	\|\| hdaR3StreamGetFree(pStreamR3) < pStreamShared->State.cbAvgTransfer * 2;
2346	else if (PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer) >= pStreamShared->State.tsAioDelayEnd)
2347	{
2348	Log3Func(("Initial delay done: Passed tsAioDelayEnd.\n"));
2349	pStreamShared->State.tsAioDelayEnd = 0;
2350	fKickAioThread = true;
2351	}
2352	else if (hdaR3StreamGetFree(pStreamR3) < pStreamShared->State.cbAvgTransfer * 2)
2353	{
2354	Log3Func(("Initial delay done: Passed running short on buffer.\n"));
2355	pStreamShared->State.tsAioDelayEnd = 0;
2356	fKickAioThread = true;
2357	}
2358	else
2359	{
2360	Log3Func(("Initial delay pending...\n"));
2361	fKickAioThread = false;
2362	}
2363
2364	Log3Func(("msDelta=%RU64 (vs %u) cbStreamFree=%#x (vs %#x) => fKickAioThread=%RTbool\n",
2365	(tsNowNs - pStreamShared->State.tsLastReadNs) / RT_NS_1MS,
2366	pStreamShared->State.Cfg.Device.cMsSchedulingHint, cbStreamFree,
2367	pStreamShared->State.cbAvgTransfer * 2, fKickAioThread));
2368
2369	if (fKickAioThread)
2370	{
2371	/* Notify the async I/O worker thread that there's work to do. */
2372	Log5Func(("Notifying AIO thread\n"));
2373	rc2 = AudioMixerSinkSignalUpdateJob(pSink);
2374	AssertRC(rc2);
2375	/* Update last read timestamp for logging/debugging. */
2376	pStreamShared->State.tsLastReadNs = tsNowNs;
2377	}
2378	}
2379	/*
2380	* Input stream (SDI).
2381	*/
2382	else
2383	{
2384	Assert(hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_IN);
2385
2386	/*
2387	* See how much data we've got buffered...
2388	*/
2389	bool fWriteSilence = false;
2390	uint32_t cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2391	if (pStreamShared->State.fInputPreBuffered && cbStreamUsed >= cbPeriod)
2392	{ /likely/ }
2393	/*
2394	* Because it may take a while for the input stream to get going (at
2395	* least with pulseaudio), we feed the guest silence till we've
2396	* pre-buffer a reasonable amount of audio.
2397	*/
2398	else if (!pStreamShared->State.fInputPreBuffered)
2399	{
2400	if (cbStreamUsed < pStreamShared->State.cbInputPreBuffer)
2401	{
2402	Log3(("hdaR3StreamUpdateDma: Pre-buffering (got %#x out of %#x bytes)...\n",
2403	cbStreamUsed, pStreamShared->State.cbInputPreBuffer));
2404	fWriteSilence = true;
2405	}
2406	else
2407	{
2408	Log3(("hdaR3StreamUpdateDma: Completed pre-buffering (got %#x, needed %#x bytes).\n",
2409	cbStreamUsed, pStreamShared->State.cbInputPreBuffer));
2410	pStreamShared->State.fInputPreBuffered = true;
2411	fWriteSilence = true; /* For now, just do the most conservative thing. */
2412	}
2413	cbStreamUsed = cbPeriod;
2414	}
2415	/*
2416	* When we're low on data, we must really try fetch some ourselves
2417	* as buffer underruns must not happen.
2418	*/
2419	else
2420	{
2421	/** @todo We're ending up here to frequently with pulse audio at least (just
2422	* watch the stream stats in the statistcs viewer, and way to often we
2423	* have to inject silence bytes. I suspect part of the problem is
2424	* that the HDA device require a much better latency than what the
2425	* pulse audio is configured for by default (10 ms vs 150ms). */
2426	STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowProblems);
2427	Log(("hdaR3StreamUpdateDma: Warning! Stream #%u has insufficient data available: %u bytes, need %u. Will try move pull more data into the buffer...\n",
2428	pStreamShared->u8SD, cbStreamUsed, cbPeriod));
2429	int rc = AudioMixerSinkTryLock(pSink);
2430	if (RT_SUCCESS(rc))
2431	{
2432	AudioMixerSinkUpdate(pSink, cbStreamUsed, cbPeriod);
2433	hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2434	AudioMixerSinkUnlock(pSink);
2435	}
2436	else
2437	RTThreadYield();
2438	Log(("hdaR3StreamUpdateDma: Gained %u bytes.\n", hdaR3StreamGetUsed(pStreamR3) - cbStreamUsed));
2439	cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2440	if (cbStreamUsed < cbPeriod)
2441	{
2442	/* Unable to find sufficient input data by simple prodding.
2443	In order to keep a constant byte stream following thru the DMA
2444	engine into the guest, we will try again and then fall back on
2445	filling the gap with silence. */
2446	uint32_t cbSilence = 0;
2447	do
2448	{
2449	AudioMixerSinkLock(pSink);
2450
2451	cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2452	if (cbStreamUsed < cbPeriod)
2453	{
2454	hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2455	cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2456	while (cbStreamUsed < cbPeriod)
2457	{
2458	void *pvDstBuf;
2459	size_t cbDstBuf;
2460	RTCircBufAcquireWriteBlock(pStreamR3->State.pCircBuf, cbPeriod - cbStreamUsed,
2461	&pvDstBuf, &cbDstBuf);
2462	RT_BZERO(pvDstBuf, cbDstBuf);
2463	RTCircBufReleaseWriteBlock(pStreamR3->State.pCircBuf, cbDstBuf);
2464	cbSilence += (uint32_t)cbDstBuf;
2465	cbStreamUsed += (uint32_t)cbDstBuf;
2466	}
2467	}
2468
2469	AudioMixerSinkUnlock(pSink);
2470	} while (cbStreamUsed < cbPeriod);
2471	if (cbSilence > 0)
2472	{
2473	STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowErrors);
2474	STAM_REL_COUNTER_ADD(&pStreamR3->State.StatDmaFlowErrorBytes, cbSilence);
2475	LogRel2(("HDA: Warning: Stream #%RU8 underrun, added %u bytes of silence (%u us)\n", pStreamShared->u8SD,
2476	cbSilence, PDMAudioPropsBytesToMicro(&pStreamShared->State.Cfg.Props, cbSilence)));
2477	}
2478	}
2479	}
2480
2481	/*
2482	* Do the DMA'ing.
2483	*/
2484	if (cbStreamUsed)
2485	hdaR3StreamDoDmaInput(pDevIns, pThis, pStreamShared, pStreamR3,
2486	RT_MIN(cbStreamUsed, cbPeriod), fWriteSilence, tsNowNs);
2487
2488	/*
2489	* We should always kick the AIO thread.
2490	*/
2491	/** @todo This isn't entirely ideal. If we get into an underrun situation,
2492	* we ideally want the AIO thread to run right before the DMA timer
2493	* rather than right after it ran. */
2494	Log5Func(("Notifying AIO thread\n"));
2495	rc2 = AudioMixerSinkSignalUpdateJob(pSink);
2496	AssertRC(rc2);
2497	pStreamShared->State.tsLastReadNs = tsNowNs;
2498	}
2499	}
2500
2501
2502	/**
2503	* @callback_method_impl{FNAUDMIXSINKUPDATE}
2504	*
2505	* For output streams this moves data from the internal DMA buffer (in which
2506	* hdaR3StreamUpdateDma put it), thru the mixer and to the various backend audio
2507	* devices.
2508	*
2509	* For input streams this pulls data from the backend audio device(s), thru the
2510	* mixer and puts it in the internal DMA buffer ready for hdaR3StreamUpdateDma
2511	* to pump into guest memory.
2512	*/
2513	DECLCALLBACK(void) hdaR3StreamUpdateAsyncIoJob(PPDMDEVINS pDevIns, PAUDMIXSINK pSink, void *pvUser)
2514	{
2515	PHDASTATE const pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
2516	PHDASTATER3 const pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
2517	PHDASTREAMR3 const pStreamR3 = (PHDASTREAMR3)pvUser;
2518	PHDASTREAM const pStreamShared = &pThis->aStreams[pStreamR3 - &pThisCC->aStreams[0]];
2519	Assert(pStreamR3 - &pThisCC->aStreams[0] == pStreamR3->u8SD);
2520	Assert(pStreamShared->u8SD == pStreamR3->u8SD);
2521	RT_NOREF(pSink);
2522
2523	/*
2524	* Make sure we haven't change sink and that it's still active (it
2525	* should be or we wouldn't have been called).
2526	*/
2527	AssertReturnVoid(pStreamR3->pMixSink && pSink == pStreamR3->pMixSink->pMixSink);
2528	AssertReturnVoid(AudioMixerSinkIsActive(pSink));
2529
2530	/*
2531	* Output streams (SDO).
2532	*/
2533	if (hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_OUT)
2534	hdaR3StreamPushToMixer(pStreamShared, pStreamR3, pSink, RTTimeNanoTS());
2535	/*
2536	* Input stream (SDI).
2537	*/
2538	else
2539	{
2540	Assert(hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_IN);
2541	hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2542	}
2543	}
2544
2545
2546	# if 0 /* unused - no prototype even */
2547	/**
2548	* Updates an HDA stream's current read or write buffer position (depending on the stream type) by
2549	* updating its associated LPIB register and DMA position buffer (if enabled).
2550	*
2551	* @returns Set LPIB value.
2552	* @param pDevIns The device instance.
2553	* @param pStream HDA stream to update read / write position for.
2554	* @param u32LPIB New LPIB (position) value to set.
2555	*/
2556	uint32_t hdaR3StreamUpdateLPIB(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint32_t u32LPIB)
2557	{
2558	AssertMsg(u32LPIB <= pStreamShared->u32CBL,
2559	("[SD%RU8] New LPIB (%RU32) exceeds CBL (%RU32)\n", pStreamShared->u8SD, u32LPIB, pStreamShared->u32CBL));
2560
2561	u32LPIB = RT_MIN(u32LPIB, pStreamShared->u32CBL);
2562
2563	LogFlowFunc(("[SD%RU8] LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n",
2564	pStreamShared->u8SD, u32LPIB, pThis->fDMAPosition));
2565
2566	/* Update LPIB in any case. */
2567	HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) = u32LPIB;
2568
2569	/* Do we need to tell the current DMA position? */
2570	if (pThis->fDMAPosition)
2571	{
2572	int rc2 = PDMDevHlpPCIPhysWrite(pDevIns,
2573	pThis->u64DPBase + (pStreamShared->u8SD * 2 * sizeof(uint32_t)),
2574	(void *)&u32LPIB, sizeof(uint32_t));
2575	AssertRC(rc2);
2576	}
2577
2578	return u32LPIB;
2579	}
2580	# endif
2581
2582	# ifdef HDA_USE_DMA_ACCESS_HANDLER
2583	/**
2584	* Registers access handlers for a stream's BDLE DMA accesses.
2585	*
2586	* @returns true if registration was successful, false if not.
2587	* @param pStream HDA stream to register BDLE access handlers for.
2588	*/
2589	bool hdaR3StreamRegisterDMAHandlers(PHDASTREAM pStream)
2590	{
2591	/* At least LVI and the BDL base must be set. */
2592	if ( !pStreamShared->u16LVI
2593	\|\| !pStreamShared->u64BDLBase)
2594	{
2595	return false;
2596	}
2597
2598	hdaR3StreamUnregisterDMAHandlers(pStream);
2599
2600	LogFunc(("Registering ...\n"));
2601
2602	int rc = VINF_SUCCESS;
2603
2604	/*
2605	* Create BDLE ranges.
2606	*/
2607
2608	struct BDLERANGE
2609	{
2610	RTGCPHYS uAddr;
2611	uint32_t uSize;
2612	} arrRanges[16]; /** @todo Use a define. */
2613
2614	size_t cRanges = 0;
2615
2616	for (uint16_t i = 0; i < pStreamShared->u16LVI + 1; i++)
2617	{
2618	HDABDLE BDLE;
2619	rc = hdaR3BDLEFetch(pDevIns, &BDLE, pStreamShared->u64BDLBase, i /* Index */);
2620	if (RT_FAILURE(rc))
2621	break;
2622
2623	bool fAddRange = true;
2624	BDLERANGE *pRange;
2625
2626	if (cRanges)
2627	{
2628	pRange = &arrRanges[cRanges - 1];
2629
2630	/* Is the current range a direct neighbor of the current BLDE? */
2631	if ((pRange->uAddr + pRange->uSize) == BDLE.Desc.u64BufAddr)
2632	{
2633	/* Expand the current range by the current BDLE's size. */
2634	pRange->uSize += BDLE.Desc.u32BufSize;
2635
2636	/* Adding a new range in this case is not needed anymore. */
2637	fAddRange = false;
2638
2639	LogFunc(("Expanding range %zu by %RU32 (%RU32 total now)\n", cRanges - 1, BDLE.Desc.u32BufSize, pRange->uSize));
2640	}
2641	}
2642
2643	/* Do we need to add a new range? */
2644	if ( fAddRange
2645	&& cRanges < RT_ELEMENTS(arrRanges))
2646	{
2647	pRange = &arrRanges[cRanges];
2648
2649	pRange->uAddr = BDLE.Desc.u64BufAddr;
2650	pRange->uSize = BDLE.Desc.u32BufSize;
2651
2652	LogFunc(("Adding range %zu - 0x%x (%RU32)\n", cRanges, pRange->uAddr, pRange->uSize));
2653
2654	cRanges++;
2655	}
2656	}
2657
2658	LogFunc(("%zu ranges total\n", cRanges));
2659
2660	/*
2661	* Register all ranges as DMA access handlers.
2662	*/
2663
2664	for (size_t i = 0; i < cRanges; i++)
2665	{
2666	BDLERANGE *pRange = &arrRanges[i];
2667
2668	PHDADMAACCESSHANDLER pHandler = (PHDADMAACCESSHANDLER)RTMemAllocZ(sizeof(HDADMAACCESSHANDLER));
2669	if (!pHandler)
2670	{
2671	rc = VERR_NO_MEMORY;
2672	break;
2673	}
2674
2675	RTListAppend(&pStream->State.lstDMAHandlers, &pHandler->Node);
2676
2677	pHandler->pStream = pStream; /* Save a back reference to the owner. */
2678
2679	char szDesc[32];
2680	RTStrPrintf(szDesc, sizeof(szDesc), "HDA[SD%RU8 - RANGE%02zu]", pStream->u8SD, i);
2681
2682	int rc2 = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
2683	hdaDMAAccessHandler,
2684	NULL, NULL, NULL,
2685	NULL, NULL, NULL,
2686	szDesc, &pHandler->hAccessHandlerType);
2687	AssertRCBreak(rc2);
2688
2689	pHandler->BDLEAddr = pRange->uAddr;
2690	pHandler->BDLESize = pRange->uSize;
2691
2692	/* Get first and last pages of the BDLE range. */
2693	RTGCPHYS pgFirst = pRange->uAddr & ~PAGE_OFFSET_MASK;
2694	RTGCPHYS pgLast = RT_ALIGN(pgFirst + pRange->uSize, PAGE_SIZE);
2695
2696	/* Calculate the region size (in pages). */
2697	RTGCPHYS regionSize = RT_ALIGN(pgLast - pgFirst, PAGE_SIZE);
2698
2699	pHandler->GCPhysFirst = pgFirst;
2700	pHandler->GCPhysLast = pHandler->GCPhysFirst + (regionSize - 1);
2701
2702	LogFunc((" Registering region '%s': %#RGp - %#RGp (region size: %#zx)\n",
2703	szDesc, pHandler->GCPhysFirst, pHandler->GCPhysLast, regionSize));
2704	LogFunc((" BDLE @ %#RGp - %#RGp (%#RX32)\n",
2705	pHandler->BDLEAddr, pHandler->BDLEAddr + pHandler->BDLESize, pHandler->BDLESize));
2706
2707	rc2 = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3),
2708	pHandler->GCPhysFirst, pHandler->GCPhysLast,
2709	pHandler->hAccessHandlerType, pHandler, NIL_RTR0PTR, NIL_RTRCPTR,
2710	szDesc);
2711	AssertRCBreak(rc2);
2712
2713	pHandler->fRegistered = true;
2714	}
2715
2716	LogFunc(("Registration ended with rc=%Rrc\n", rc));
2717
2718	return RT_SUCCESS(rc);
2719	}
2720
2721	/**
2722	* Unregisters access handlers of a stream's BDLEs.
2723	*
2724	* @param pStream HDA stream to unregister BDLE access handlers for.
2725	*/
2726	void hdaR3StreamUnregisterDMAHandlers(PHDASTREAM pStream)
2727	{
2728	LogFunc(("\n"));
2729
2730	PHDADMAACCESSHANDLER pHandler, pHandlerNext;
2731	RTListForEachSafe(&pStream->State.lstDMAHandlers, pHandler, pHandlerNext, HDADMAACCESSHANDLER, Node)
2732	{
2733	if (!pHandler->fRegistered) /* Handler not registered? Skip. */
2734	continue;
2735
2736	LogFunc(("Unregistering 0x%x - 0x%x (%zu)\n",
2737	pHandler->GCPhysFirst, pHandler->GCPhysLast, pHandler->GCPhysLast - pHandler->GCPhysFirst));
2738
2739	int rc2 = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3),
2740	pHandler->GCPhysFirst);
2741	AssertRC(rc2);
2742
2743	RTListNodeRemove(&pHandler->Node);
2744
2745	RTMemFree(pHandler);
2746	pHandler = NULL;
2747	}
2748
2749	Assert(RTListIsEmpty(&pStream->State.lstDMAHandlers));
2750	}
2751
2752	# endif /* HDA_USE_DMA_ACCESS_HANDLER */
2753
2754	#endif /* IN_RING3 */

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/Devices/Audio/DevHdaStream.cpp@ 89864

Download in other formats: