VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevHdaStream.cpp@ 89830

Last change on this file since 89830 was 89826, checked in by vboxsync, 4 years ago

DevHda: Partial vista fix. Must avoid chopping up the buffers in an odd manner. bugref:9890
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1/* $Id: DevHdaStream.cpp 89826 2021-06-21 21:41:38Z vboxsync $ */
2/** @file
3 * Intel HD Audio Controller Emulation - Streams.
4 */
5
6/*
7 * Copyright (C) 2017-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_HDA
23#include <VBox/log.h>
24
25#include <iprt/mem.h>
26#include <iprt/semaphore.h>
27
28#include <VBox/AssertGuest.h>
29#include <VBox/vmm/pdmdev.h>
30#include <VBox/vmm/pdmaudioifs.h>
31#include <VBox/vmm/pdmaudioinline.h>
32
33#include "AudioHlp.h"
34
35#include "DevHda.h"
36#include "DevHdaStream.h"
37
38#ifdef VBOX_WITH_DTRACE
39# include "dtrace/VBoxDD.h"
40#endif
41
42#ifdef IN_RING3 /* whole file */
43
44
45/*********************************************************************************************************************************
46* Internal Functions *
47*********************************************************************************************************************************/
48static void hdaR3StreamSetPositionAbs(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uLPIB);
49static void hdaR3StreamUpdateDma(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
50 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
51
52
53
54/**
55 * Creates an HDA stream.
56 *
57 * @returns VBox status code.
58 * @param pStreamShared The HDA stream to construct - shared bits.
59 * @param pStreamR3 The HDA stream to construct - ring-3 bits.
60 * @param pThis The shared HDA device instance.
61 * @param pThisCC The ring-3 HDA device instance.
62 * @param uSD Stream descriptor number to assign.
63 */
64int hdaR3StreamConstruct(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PHDASTATE pThis, PHDASTATER3 pThisCC, uint8_t uSD)
65{
66 int rc;
67
68 pStreamR3->u8SD = uSD;
69 pStreamShared->u8SD = uSD;
70 pStreamR3->pMixSink = NULL;
71 pStreamR3->pHDAStateShared = pThis;
72 pStreamR3->pHDAStateR3 = pThisCC;
73 Assert(pStreamShared->hTimer != NIL_TMTIMERHANDLE); /* hdaR3Construct initalized this one already. */
74
75 pStreamShared->State.fInReset = false;
76 pStreamShared->State.fRunning = false;
77#ifdef HDA_USE_DMA_ACCESS_HANDLER
78 RTListInit(&pStreamR3->State.lstDMAHandlers);
79#endif
80
81 AssertPtr(pStreamR3->pHDAStateR3);
82 AssertPtr(pStreamR3->pHDAStateR3->pDevIns);
83 rc = PDMDevHlpCritSectInit(pStreamR3->pHDAStateR3->pDevIns, &pStreamShared->CritSect,
84 RT_SRC_POS, "hda_sd#%RU8", pStreamShared->u8SD);
85 AssertRCReturn(rc, rc);
86
87#ifdef DEBUG
88 rc = RTCritSectInit(&pStreamR3->Dbg.CritSect);
89 AssertRCReturn(rc, rc);
90#endif
91
92 const bool fIsInput = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN;
93
94 if (fIsInput)
95 {
96 pStreamShared->State.Cfg.enmPath = PDMAUDIOPATH_UNKNOWN;
97 pStreamShared->State.Cfg.enmDir = PDMAUDIODIR_IN;
98 }
99 else
100 {
101 pStreamShared->State.Cfg.enmPath = PDMAUDIOPATH_UNKNOWN;
102 pStreamShared->State.Cfg.enmDir = PDMAUDIODIR_OUT;
103 }
104
105 pStreamR3->Dbg.Runtime.fEnabled = pThisCC->Dbg.fEnabled;
106
107 if (pStreamR3->Dbg.Runtime.fEnabled)
108 {
109 char szFile[64];
110 char szPath[RTPATH_MAX];
111
112 /* pFileStream */
113 if (fIsInput)
114 RTStrPrintf(szFile, sizeof(szFile), "hdaStreamWriteSD%RU8", uSD);
115 else
116 RTStrPrintf(szFile, sizeof(szFile), "hdaStreamReadSD%RU8", uSD);
117
118 int rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
119 0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
120 AssertRC(rc2);
121
122 rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileStream);
123 AssertRC(rc2);
124
125 /* pFileDMARaw */
126 if (fIsInput)
127 RTStrPrintf(szFile, sizeof(szFile), "hdaDMARawWriteSD%RU8", uSD);
128 else
129 RTStrPrintf(szFile, sizeof(szFile), "hdaDMARawReadSD%RU8", uSD);
130
131 rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
132 0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
133 AssertRC(rc2);
134
135 rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileDMARaw);
136 AssertRC(rc2);
137
138 /* pFileDMAMapped */
139 if (fIsInput)
140 RTStrPrintf(szFile, sizeof(szFile), "hdaDMAWriteMappedSD%RU8", uSD);
141 else
142 RTStrPrintf(szFile, sizeof(szFile), "hdaDMAReadMappedSD%RU8", uSD);
143
144 rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
145 0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
146 AssertRC(rc2);
147
148 rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileDMAMapped);
149 AssertRC(rc2);
150
151 /* Delete stale debugging files from a former run. */
152 AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileStream);
153 AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileDMARaw);
154 AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileDMAMapped);
155 }
156
157 return rc;
158}
159
160/**
161 * Destroys an HDA stream.
162 *
163 * @param pStreamShared The HDA stream to destroy - shared bits.
164 * @param pStreamR3 The HDA stream to destroy - ring-3 bits.
165 */
166void hdaR3StreamDestroy(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
167{
168 LogFlowFunc(("[SD%RU8] Destroying ...\n", pStreamShared->u8SD));
169 int rc2;
170
171 if (pStreamR3->State.pAioRegSink)
172 {
173 rc2 = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
174 AssertRC(rc2);
175 pStreamR3->State.pAioRegSink = NULL;
176 }
177
178 if (PDMCritSectIsInitialized(&pStreamShared->CritSect))
179 {
180 rc2 = PDMR3CritSectDelete(&pStreamShared->CritSect);
181 AssertRC(rc2);
182 }
183
184 if (pStreamR3->State.pCircBuf)
185 {
186 RTCircBufDestroy(pStreamR3->State.pCircBuf);
187 pStreamR3->State.pCircBuf = NULL;
188 pStreamR3->State.StatDmaBufSize = 0;
189 pStreamR3->State.StatDmaBufUsed = 0;
190 }
191
192#ifdef DEBUG
193 if (RTCritSectIsInitialized(&pStreamR3->Dbg.CritSect))
194 {
195 rc2 = RTCritSectDelete(&pStreamR3->Dbg.CritSect);
196 AssertRC(rc2);
197 }
198#endif
199
200 if (pStreamR3->Dbg.Runtime.fEnabled)
201 {
202 AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileStream);
203 pStreamR3->Dbg.Runtime.pFileStream = NULL;
204
205 AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileDMARaw);
206 pStreamR3->Dbg.Runtime.pFileDMARaw = NULL;
207
208 AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileDMAMapped);
209 pStreamR3->Dbg.Runtime.pFileDMAMapped = NULL;
210 }
211
212 LogFlowFuncLeave();
213}
214
215
216/**
217 * Appends a item to the scheduler.
218 *
219 * @returns VBox status code.
220 * @param pStreamShared The stream which scheduler should be modified.
221 * @param cbCur The period length in guest bytes.
222 * @param cbMaxPeriod The max period in guest bytes.
223 * @param idxLastBdle The last BDLE in the period.
224 * @param pHostProps The host PCM properties.
225 * @param pGuestProps The guest PCM properties.
226 * @param pcbBorrow Where to account for bytes borrowed across buffers
227 * to align scheduling items on frame boundraries.
228 */
229static int hdaR3StreamAddScheduleItem(PHDASTREAM pStreamShared, uint32_t cbCur, uint32_t cbMaxPeriod, uint32_t idxLastBdle,
230 PCPDMAUDIOPCMPROPS pHostProps, PCPDMAUDIOPCMPROPS pGuestProps, uint32_t *pcbBorrow)
231{
232 /* Check that we've got room (shouldn't ever be a problem). */
233 size_t idx = pStreamShared->State.cSchedule;
234 AssertLogRelReturn(idx + 1 < RT_ELEMENTS(pStreamShared->State.aSchedule), VERR_INTERNAL_ERROR_5);
235
236 /* Figure out the BDLE range for this period. */
237 uint32_t const idxFirstBdle = idx == 0 ? 0
238 : RT_MIN((uint32_t)( pStreamShared->State.aSchedule[idx - 1].idxFirst
239 + pStreamShared->State.aSchedule[idx - 1].cEntries),
240 idxLastBdle);
241
242 pStreamShared->State.aSchedule[idx].idxFirst = (uint8_t)idxFirstBdle;
243 pStreamShared->State.aSchedule[idx].cEntries = idxLastBdle >= idxFirstBdle
244 ? idxLastBdle - idxFirstBdle + 1
245 : pStreamShared->State.cBdles - idxFirstBdle + idxLastBdle + 1;
246
247 /* Deal with borrowing due to unaligned IOC buffers. */
248 uint32_t const cbBorrowed = *pcbBorrow;
249 if (cbBorrowed < cbCur)
250 cbCur -= cbBorrowed;
251 else
252 {
253 /* Note. We can probably gloss over this, but it's not a situation a sane guest would put us, so don't bother for now. */
254 ASSERT_GUEST_MSG_FAILED(("#%u: cbBorrow=%#x cbCur=%#x BDLE[%u..%u]\n",
255 pStreamShared->u8SD, cbBorrowed, cbCur, idxFirstBdle, idxLastBdle));
256 LogRelMax(32, ("HDA: Stream #%u has a scheduling error: cbBorrow=%#x cbCur=%#x BDLE[%u..%u]\n",
257 pStreamShared->u8SD, cbBorrowed, cbCur, idxFirstBdle, idxLastBdle));
258 return VERR_OUT_OF_RANGE;
259 }
260
261 uint32_t cbCurAligned = PDMAudioPropsRoundUpBytesToFrame(pGuestProps, cbCur);
262 *pcbBorrow = cbCurAligned - cbCur;
263
264 /* Do we need to split up the period? */
265 if (cbCurAligned <= cbMaxPeriod)
266 {
267 uint32_t cbHost = PDMAudioPropsFramesToBytes(pHostProps, PDMAudioPropsBytesToFrames(pGuestProps, cbCurAligned));
268 pStreamShared->State.aSchedule[idx].cbPeriod = cbHost;
269 pStreamShared->State.aSchedule[idx].cLoops = 1;
270 }
271 else
272 {
273 /* Reduce till we've below the threshold. */
274 uint32_t cbLoop = cbCurAligned;
275 do
276 cbLoop = cbCurAligned / 2;
277 while (cbLoop > cbMaxPeriod);
278 cbLoop = PDMAudioPropsRoundUpBytesToFrame(pGuestProps, cbLoop);
279
280 /* Complete the scheduling item. */
281 uint32_t cbHost = PDMAudioPropsFramesToBytes(pHostProps, PDMAudioPropsBytesToFrames(pGuestProps, cbLoop));
282 pStreamShared->State.aSchedule[idx].cbPeriod = cbHost;
283 pStreamShared->State.aSchedule[idx].cLoops = cbCurAligned / cbLoop;
284
285 /* If there is a remainder, add it as a separate entry (this is
286 why the schedule must be more than twice the size of the BDL).*/
287 cbCurAligned %= cbLoop;
288 if (cbCurAligned)
289 {
290 pStreamShared->State.aSchedule[idx + 1] = pStreamShared->State.aSchedule[idx];
291 idx++;
292 cbHost = PDMAudioPropsFramesToBytes(pHostProps, PDMAudioPropsBytesToFrames(pGuestProps, cbCurAligned));
293 pStreamShared->State.aSchedule[idx].cbPeriod = cbHost;
294 pStreamShared->State.aSchedule[idx].cLoops = 1;
295 }
296 }
297
298 /* Done. */
299 pStreamShared->State.cSchedule = (uint16_t)(idx + 1);
300
301 return VINF_SUCCESS;
302}
303
304/**
305 * Creates the DMA timer schedule for the stream
306 *
307 * This is called from the stream setup code.
308 *
309 * @returns VBox status code.
310 * @param pStreamShared The stream to create a schedule for. The BDL
311 * must be loaded.
312 * @param cSegments Number of BDL segments.
313 * @param cBufferIrqs Number of the BDLEs with IOC=1.
314 * @param cbTotal The total BDL length in guest bytes.
315 * @param cbMaxPeriod Max period in guest bytes. This is in case the
316 * guest want to play the whole "Der Ring des
317 * Nibelungen" cycle in one go.
318 * @param cTimerTicksPerSec The DMA timer frequency.
319 * @param pHostProps The host PCM properties.
320 * @param pGuestProps The guest PCM properties.
321 */
322static int hdaR3StreamCreateSchedule(PHDASTREAM pStreamShared, uint32_t cSegments, uint32_t cBufferIrqs, uint32_t cbTotal,
323 uint32_t cbMaxPeriod, uint64_t cTimerTicksPerSec,
324 PCPDMAUDIOPCMPROPS pHostProps, PCPDMAUDIOPCMPROPS pGuestProps)
325{
326 int rc;
327
328 /*
329 * Reset scheduling state.
330 */
331 RT_ZERO(pStreamShared->State.aSchedule);
332 pStreamShared->State.cSchedule = 0;
333 pStreamShared->State.cSchedulePrologue = 0;
334 pStreamShared->State.idxSchedule = 0;
335 pStreamShared->State.idxScheduleLoop = 0;
336
337 /*
338 * Do the basic schedule compilation.
339 */
340 uint32_t cPotentialPrologue = 0;
341 uint32_t cbBorrow = 0;
342 uint32_t cbCur = 0;
343 uint32_t cbMin = UINT32_MAX;
344 pStreamShared->State.aSchedule[0].idxFirst = 0;
345 for (uint32_t i = 0; i < cSegments; i++)
346 {
347 cbCur += pStreamShared->State.aBdl[i].cb;
348 if (pStreamShared->State.aBdl[i].cb < cbMin)
349 cbMin = pStreamShared->State.aBdl[i].cb;
350 if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
351 {
352 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur, cbMaxPeriod, i, pHostProps, pGuestProps, &cbBorrow);
353 ASSERT_GUEST_RC_RETURN(rc, rc);
354
355 if (cPotentialPrologue == 0)
356 cPotentialPrologue = pStreamShared->State.cSchedule;
357 cbCur = 0;
358 }
359 }
360 AssertLogRelMsgReturn(cbBorrow == 0, ("HDA: Internal scheduling error on stream #%u: cbBorrow=%#x cbTotal=%#x cbCur=%#x\n",
361 pStreamShared->u8SD, cbBorrow, cbTotal, cbCur),
362 VERR_INTERNAL_ERROR_3);
363
364 /*
365 * Deal with any loose ends.
366 */
367 if (cbCur && cBufferIrqs == 0)
368 {
369 /*
370 * No IOC. Vista ends up here, typically with three buffers configured.
371 *
372 * The perferred option here is to aim at processing one average BDLE with
373 * each DMA timer period, since that best matches how we update LPIB at
374 * present.
375 *
376 * The second alternative is to divide the whole span up into 3-4 periods
377 * to try increase our chances of keeping ahead of the guest. We may need
378 * to pick this if there are too few buffer descriptor or they are too small.
379 *
380 * However, what we probably should be doing is to do real DMA work whenever
381 * the guest reads a DMA related register (like LPIB) and just do 3-4 DMA
382 * timer periods, however we'll be postponing the DMA timer every time we
383 * return to ring-3 and signal the AIO, so in the end we'd probably not use
384 * the timer callback at all. (This is assuming a small shared per-stream
385 * buffer for keeping the DMA data in and that it's size will force a return
386 * to ring-3 often enough to keep the AIO thread going at a reasonable rate.)
387 */
388 Assert(cbCur == cbTotal);
389
390 /* Match the BDLEs 1:1 if there are 3 or more and that the smallest one
391 is at least 5ms big. */
392 if (cSegments >= 3 && PDMAudioPropsBytesToMilli(pGuestProps, cbMin) >= 5 /*ms*/)
393 {
394 for (uint32_t i = 0; i < cSegments; i++)
395 {
396 rc = hdaR3StreamAddScheduleItem(pStreamShared, pStreamShared->State.aBdl[i].cb, cbMaxPeriod,
397 i, pHostProps, pGuestProps, &cbBorrow);
398 ASSERT_GUEST_RC_RETURN(rc, rc);
399 }
400 }
401 /* Otherwise, just divide the work into 3 or 4 portions and hope for the best.
402 It seems, though, that this only really work for windows vista if we avoid
403 working accross buffer lines. */
404 /** @todo This can be simplified/relaxed/uncluttered if we do DMA work when LPIB
405 * is read, assuming ofc that LPIB is read before each buffer update. */
406 else
407 {
408 uint32_t const cPeriods = cSegments != 3 && PDMAudioPropsBytesToMilli(pGuestProps, cbCur) >= 4 * 5 /*ms*/
409 ? 4 : cSegments != 2 ? 3 : 2;
410 uint32_t const cbPeriod = PDMAudioPropsFloorBytesToFrame(pGuestProps, cbCur / cPeriods);
411 uint32_t iBdle = 0;
412 uint32_t offBdle = 0;
413 for (uint32_t iPeriod = 0; iPeriod < cPeriods; iPeriod++)
414 {
415 if (iPeriod + 1 < cPeriods)
416 {
417 offBdle += cbPeriod;
418 while (iBdle < cSegments && offBdle >= pStreamShared->State.aBdl[iBdle].cb)
419 offBdle -= pStreamShared->State.aBdl[iBdle++].cb;
420 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbPeriod, cbMaxPeriod, offBdle != 0 ? iBdle : iBdle - 1,
421 pHostProps, pGuestProps, &cbBorrow);
422 }
423 else
424 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur - iPeriod * cbPeriod, cbMaxPeriod, cSegments - 1,
425 pHostProps, pGuestProps, &cbBorrow);
426 ASSERT_GUEST_RC_RETURN(rc, rc);
427 }
428
429 }
430 Assert(cbBorrow == 0);
431 }
432 else if (cbCur)
433 {
434 /* The last BDLE didn't have IOC set, so we must continue processing
435 from the start till we hit one that has. */
436 uint32_t i;
437 for (i = 0; i < cSegments; i++)
438 {
439 cbCur += pStreamShared->State.aBdl[i].cb;
440 if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
441 break;
442 }
443 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur, cbMaxPeriod, i, pHostProps, pGuestProps, &cbBorrow);
444 ASSERT_GUEST_RC_RETURN(rc, rc);
445
446 /* The initial scheduling items covering the wrap around area are
447 considered a prologue and must not repeated later. */
448 Assert(cPotentialPrologue);
449 pStreamShared->State.cSchedulePrologue = (uint8_t)cPotentialPrologue;
450 }
451
452 /*
453 * If there is just one BDLE with IOC set, we have to make sure
454 * we've got at least two periods scheduled, otherwise there is
455 * a very good chance the guest will overwrite the start of the
456 * buffer before we ever get around to reading it.
457 */
458 if (cBufferIrqs == 1)
459 {
460 uint32_t i = pStreamShared->State.cSchedulePrologue;
461 Assert(i < pStreamShared->State.cSchedule);
462 if ( i + 1 == pStreamShared->State.cSchedule
463 && pStreamShared->State.aSchedule[i].cLoops == 1)
464 {
465 uint32_t const cbFirstHalf = PDMAudioPropsFloorBytesToFrame(pHostProps, pStreamShared->State.aSchedule[i].cbPeriod / 2);
466 uint32_t const cbOtherHalf = pStreamShared->State.aSchedule[i].cbPeriod - cbFirstHalf;
467 pStreamShared->State.aSchedule[i].cbPeriod = cbFirstHalf;
468 if (cbFirstHalf == cbOtherHalf)
469 pStreamShared->State.aSchedule[i].cLoops = 2;
470 else
471 {
472 pStreamShared->State.aSchedule[i + 1] = pStreamShared->State.aSchedule[i];
473 pStreamShared->State.aSchedule[i].cbPeriod = cbOtherHalf;
474 pStreamShared->State.cSchedule++;
475 }
476 }
477 }
478
479 /*
480 * Go over the schduling entries and calculate the timer ticks for each period.
481 */
482 LogRel2(("HDA: Stream #%u schedule: %u items, %u prologue\n",
483 pStreamShared->u8SD, pStreamShared->State.cSchedule, pStreamShared->State.cSchedulePrologue));
484 uint64_t const cbHostPerSec = PDMAudioPropsFramesToBytes(pHostProps, pHostProps->uHz);
485 for (uint32_t i = 0; i < pStreamShared->State.cSchedule; i++)
486 {
487 uint64_t const cTicks = ASMMultU64ByU32DivByU32(cTimerTicksPerSec, pStreamShared->State.aSchedule[i].cbPeriod,
488 cbHostPerSec);
489 AssertLogRelMsgReturn((uint32_t)cTicks == cTicks, ("cTicks=%RU64 (%#RX64)\n", cTicks, cTicks), VERR_INTERNAL_ERROR_4);
490 pStreamShared->State.aSchedule[i].cPeriodTicks = RT_MAX((uint32_t)cTicks, 16);
491 LogRel2(("HDA: #%u: %u ticks / %u bytes, %u loops, BDLE%u L %u\n", i, pStreamShared->State.aSchedule[i].cPeriodTicks,
492 pStreamShared->State.aSchedule[i].cbPeriod, pStreamShared->State.aSchedule[i].cLoops,
493 pStreamShared->State.aSchedule[i].idxFirst, pStreamShared->State.aSchedule[i].cEntries));
494 }
495
496 return VINF_SUCCESS;
497}
498
499
500/**
501 * Sets up ((re-)iniitalizes) an HDA stream.
502 *
503 * @returns VBox status code. VINF_NO_CHANGE if the stream does not need
504 * be set-up again because the stream's (hardware) parameters did
505 * not change.
506 * @param pDevIns The device instance.
507 * @param pThis The shared HDA device state (for HW register
508 * parameters).
509 * @param pStreamShared HDA stream to set up, shared portion.
510 * @param pStreamR3 HDA stream to set up, ring-3 portion.
511 * @param uSD Stream descriptor number to assign it.
512 */
513int hdaR3StreamSetUp(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD)
514{
515 /* This must be valid all times. */
516 AssertReturn(uSD < HDA_MAX_STREAMS, VERR_INVALID_PARAMETER);
517
518 /* These member can only change on data corruption, despite what the code does further down (bird). */
519 AssertReturn(pStreamShared->u8SD == uSD, VERR_WRONG_ORDER);
520 AssertReturn(pStreamR3->u8SD == uSD, VERR_WRONG_ORDER);
521
522 const uint64_t u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, uSD),
523 HDA_STREAM_REG(pThis, BDPU, uSD));
524 const uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, uSD);
525 const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, uSD);
526 const uint8_t u8FIFOS = HDA_STREAM_REG(pThis, FIFOS, uSD) + 1;
527 uint8_t u8FIFOW = hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, uSD));
528 const uint16_t u16FMT = HDA_STREAM_REG(pThis, FMT, uSD);
529
530 /* Is the bare minimum set of registers configured for the stream?
531 * If not, bail out early, as there's nothing to do here for us (yet). */
532 if ( !u64BDLBase
533 || !u16LVI
534 || !u32CBL
535 || !u8FIFOS
536 || !u8FIFOW
537 || !u16FMT)
538 {
539 LogFunc(("[SD%RU8] Registers not set up yet, skipping (re-)initialization\n", uSD));
540 return VINF_SUCCESS;
541 }
542
543 /*
544 * Convert the config to PDM PCM properties and configure the stream.
545 */
546 PPDMAUDIOSTREAMCFG pCfg = &pStreamShared->State.Cfg;
547 int rc = hdaR3SDFMTToPCMProps(u16FMT, &pCfg->Props);
548 if (RT_SUCCESS(rc))
549 pCfg->enmDir = hdaGetDirFromSD(uSD);
550 else
551 {
552 LogRelMax(32, ("HDA: Warning: Format 0x%x for stream #%RU8 not supported\n", HDA_STREAM_REG(pThis, FMT, uSD), uSD));
553 return rc;
554 }
555
556 ASSERT_GUEST_LOGREL_MSG_RETURN( PDMAudioPropsFrameSize(&pCfg->Props) > 0
557 && u32CBL % PDMAudioPropsFrameSize(&pCfg->Props) == 0,
558 ("CBL for stream #%RU8 does not align to frame size (u32CBL=%u cbFrameSize=%u)\n",
559 uSD, u32CBL, PDMAudioPropsFrameSize(&pCfg->Props)),
560 VERR_INVALID_PARAMETER);
561
562 /* Make sure the guest behaves regarding the stream's FIFO. */
563 ASSERT_GUEST_LOGREL_MSG_STMT(u8FIFOW <= u8FIFOS,
564 ("Guest tried setting a bigger FIFOW (%RU8) than FIFOS (%RU8), limiting\n", u8FIFOW, u8FIFOS),
565 u8FIFOW = u8FIFOS /* ASSUMES that u8FIFOS has been validated. */);
566
567 pStreamShared->u8SD = uSD;
568
569 /* Update all register copies so that we later know that something has changed. */
570 pStreamShared->u64BDLBase = u64BDLBase;
571 pStreamShared->u16LVI = u16LVI;
572 pStreamShared->u32CBL = u32CBL;
573 pStreamShared->u8FIFOS = u8FIFOS;
574 pStreamShared->u8FIFOW = u8FIFOW;
575 pStreamShared->u16FMT = u16FMT;
576
577 /* The the stream's name, based on the direction. */
578 switch (pCfg->enmDir)
579 {
580 case PDMAUDIODIR_IN:
581# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
582# error "Implement me!"
583# else
584 pCfg->enmPath = PDMAUDIOPATH_IN_LINE;
585 RTStrCopy(pCfg->szName, sizeof(pCfg->szName), "Line In");
586# endif
587 break;
588
589 case PDMAUDIODIR_OUT:
590 /* Destination(s) will be set in hdaR3AddStreamOut(),
591 * based on the channels / stream layout. */
592 break;
593
594 default:
595 AssertFailedReturn(VERR_NOT_SUPPORTED);
596 break;
597 }
598
599 LogRel2(("HDA: Stream #%RU8 DMA @ 0x%x (%RU32 bytes = %RU64ms total)\n", uSD, pStreamShared->u64BDLBase,
600 pStreamShared->u32CBL, PDMAudioPropsBytesToMilli(&pCfg->Props, pStreamShared->u32CBL)));
601
602 /*
603 * Load the buffer descriptor list.
604 *
605 * Section 3.6.2 states that "the BDL should not be modified unless the RUN
606 * bit is 0", so it should be within the specs to read it once here and not
607 * re-read any BDLEs later.
608 */
609 /* Reset BDL state. */
610 RT_ZERO(pStreamShared->State.aBdl);
611 pStreamShared->State.offCurBdle = 0;
612 pStreamShared->State.idxCurBdle = 0;
613
614 uint32_t /*const*/ cTransferFragments = (pStreamShared->u16LVI & 0xff) + 1;
615 if (cTransferFragments <= 1)
616 LogRel(("HDA: Warning: Stream #%RU8 transfer buffer count invalid: (%RU16)! Buggy guest audio driver!\n", uSD, pStreamShared->u16LVI));
617 AssertLogRelReturn(cTransferFragments <= RT_ELEMENTS(pStreamShared->State.aBdl), VERR_INTERNAL_ERROR_5);
618 pStreamShared->State.cBdles = cTransferFragments;
619
620 /* Load them. */
621 rc = PDMDevHlpPCIPhysRead(pDevIns, u64BDLBase, pStreamShared->State.aBdl,
622 sizeof(pStreamShared->State.aBdl[0]) * cTransferFragments);
623 AssertRC(rc);
624
625 /* Check what we just loaded. Refuse overly large buffer lists. */
626 uint64_t cbTotal = 0;
627 uint32_t cBufferIrqs = 0;
628 for (uint32_t i = 0; i < cTransferFragments; i++)
629 {
630 if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
631 cBufferIrqs++;
632 cbTotal += pStreamShared->State.aBdl[i].cb;
633 }
634 ASSERT_GUEST_STMT_RETURN(cbTotal < _2G,
635 LogRelMax(32, ("HDA: Error: Stream #%u is configured with an insane amount of buffer space - refusing do work with it: %RU64 (%#RX64) bytes.\n",
636 uSD, cbTotal, cbTotal)),
637 VERR_NOT_SUPPORTED);
638 ASSERT_GUEST_STMT_RETURN(cbTotal == u32CBL,
639 LogRelMax(32, ("HDA: Warning: Stream #%u has a mismatch between CBL and configured buffer space: %RU32 (%#RX32) vs %RU64 (%#RX64)\n",
640 uSD, u32CBL, u32CBL, cbTotal, cbTotal)),
641 VERR_NOT_SUPPORTED);
642
643 /*
644 * Create a DMA timer schedule.
645 */
646 /** @todo clean up this, pGuestProps and pHostProps are the same now. */
647 rc = hdaR3StreamCreateSchedule(pStreamShared, cTransferFragments, cBufferIrqs, (uint32_t)cbTotal,
648 PDMAudioPropsMilliToBytes(&pCfg->Props, 100 /** @todo make configurable */),
649 PDMDevHlpTimerGetFreq(pDevIns, pStreamShared->hTimer),
650 &pCfg->Props, &pCfg->Props);
651 if (RT_FAILURE(rc))
652 return rc;
653
654 pStreamShared->State.cbTransferSize = pStreamShared->State.aSchedule[0].cbPeriod;
655
656 /*
657 * Calculate the transfer Hz for use in the circular buffer calculation.
658 */
659 uint32_t cbMaxPeriod = 0;
660 uint32_t cbMinPeriod = UINT32_MAX;
661 uint32_t cPeriods = 0;
662 for (uint32_t i = 0; i < pStreamShared->State.cSchedule; i++)
663 {
664 uint32_t cbPeriod = pStreamShared->State.aSchedule[i].cbPeriod;
665 cbMaxPeriod = RT_MAX(cbMaxPeriod, cbPeriod);
666 cbMinPeriod = RT_MIN(cbMinPeriod, cbPeriod);
667 cPeriods += pStreamShared->State.aSchedule[i].cLoops;
668 }
669 uint64_t const cbTransferPerSec = RT_MAX(PDMAudioPropsFramesToBytes(&pCfg->Props, pCfg->Props.uHz),
670 4096 /* zero div prevention: min is 6kHz, picked 4k in case I'm mistaken */);
671 unsigned uTransferHz = cbTransferPerSec * 1000 / cbMaxPeriod;
672 LogRel2(("HDA: Stream #%RU8 needs a %u.%03u Hz timer rate (period: %u..%u host bytes)\n",
673 uSD, uTransferHz / 1000, uTransferHz % 1000, cbMinPeriod, cbMaxPeriod));
674 uTransferHz /= 1000;
675
676 if (uTransferHz > 400) /* Anything above 400 Hz looks fishy -- tell the user. */
677 LogRelMax(32, ("HDA: Warning: Calculated transfer Hz rate for stream #%RU8 looks incorrect (%u), please re-run with audio debug mode and report a bug\n",
678 uSD, uTransferHz));
679
680 pStreamShared->State.cbAvgTransfer = (uint32_t)(cbTotal + cPeriods - 1) / cPeriods;
681
682 /* For input streams we must determin a pre-buffering requirement.
683 We use the initial delay as a basis here, though we must have at
684 least two max periods worth of data queued up due to the way we
685 work the AIO thread. */
686 pStreamShared->State.fInputPreBuffered = false;
687 pStreamShared->State.cbInputPreBuffer = PDMAudioPropsMilliToBytes(&pCfg->Props, pThis->msInitialDelay);
688 pStreamShared->State.cbInputPreBuffer = RT_MIN(cbMaxPeriod * 2, pStreamShared->State.cbInputPreBuffer);
689
690 /*
691 * Set up data transfer stuff.
692 */
693
694 /* Assign the global device rate to the stream I/O timer as default. */
695 pStreamShared->State.uTimerIoHz = pThis->uTimerHz;
696 ASSERT_GUEST_LOGREL_MSG_STMT(pStreamShared->State.uTimerIoHz,
697 ("I/O timer Hz rate for stream #%RU8 is invalid\n", uSD),
698 pStreamShared->State.uTimerIoHz = HDA_TIMER_HZ_DEFAULT);
699
700 /* Set I/O scheduling hint for the backends. */
701 /** @todo r=bird: This is in the 'Device' portion, yet it's used by the
702 * audio driver. You would think stuff in the 'Device' part is
703 * private to the device. */
704 pCfg->Device.cMsSchedulingHint = RT_MS_1SEC / pStreamShared->State.uTimerIoHz;
705 LogRel2(("HDA: Stream #%RU8 set scheduling hint for the backends to %RU32ms\n", uSD, pCfg->Device.cMsSchedulingHint));
706
707
708 /* Make sure to also update the stream's DMA counter (based on its current LPIB value). */
709 hdaR3StreamSetPositionAbs(pStreamShared, pDevIns, pThis, HDA_STREAM_REG(pThis, LPIB, uSD));
710
711#ifdef LOG_ENABLED
712 hdaR3BDLEDumpAll(pDevIns, pThis, pStreamShared->u64BDLBase, pStreamShared->u16LVI + 1);
713#endif
714
715 /*
716 * Set up internal ring buffer.
717 */
718
719 /* (Re-)Allocate the stream's internal DMA buffer,
720 * based on the timing *and* PCM properties we just got above. */
721 if (pStreamR3->State.pCircBuf)
722 {
723 RTCircBufDestroy(pStreamR3->State.pCircBuf);
724 pStreamR3->State.pCircBuf = NULL;
725 pStreamR3->State.StatDmaBufSize = 0;
726 pStreamR3->State.StatDmaBufUsed = 0;
727 }
728 pStreamR3->State.offWrite = 0;
729 pStreamR3->State.offRead = 0;
730
731 /*
732 * The default internal ring buffer size must be:
733 *
734 * - Large enough for at least three periodic DMA transfers.
735 *
736 * It is critically important that we don't experience underruns
737 * in the DMA OUT code, because it will cause the buffer processing
738 * to get skewed and possibly overlap with what the guest is updating.
739 * At the time of writing (2021-03-05) there is no code for getting
740 * back into sync there.
741 *
742 * - Large enough for at least three I/O scheduling hints.
743 *
744 * We want to lag behind a DMA period or two, but there must be
745 * sufficent space for the AIO thread to get schedule and shuffle
746 * data thru the mixer and onto the host audio hardware.
747 *
748 * - Both above with plenty to spare.
749 *
750 * So, just take the longest of the two periods and multipling it by 6.
751 * We aren't not talking about very large base buffers heres, so size isn't
752 * an issue.
753 *
754 * Note: Use pCfg->Props as PCM properties here, as we only want to store the
755 * samples we actually need, in other words, skipping the interleaved
756 * channels we don't support / need to save space.
757 */
758 uint32_t msCircBuf = RT_MS_1SEC * 6 / RT_MIN(uTransferHz, pStreamShared->State.uTimerIoHz);
759 msCircBuf = RT_MAX(msCircBuf, pThis->msInitialDelay + RT_MS_1SEC * 6 / uTransferHz);
760
761 uint32_t cbCircBuf = PDMAudioPropsMilliToBytes(&pCfg->Props, msCircBuf);
762 LogRel2(("HDA: Stream #%RU8 default ring buffer size is %RU32 bytes / %RU64 ms\n",
763 uSD, cbCircBuf, PDMAudioPropsBytesToMilli(&pCfg->Props, cbCircBuf)));
764
765 uint32_t msCircBufCfg = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? pThis->cMsCircBufIn : pThis->cMsCircBufOut;
766 if (msCircBufCfg) /* Anything set via CFGM? */
767 {
768 cbCircBuf = PDMAudioPropsMilliToBytes(&pCfg->Props, msCircBufCfg);
769 LogRel2(("HDA: Stream #%RU8 is using a custom ring buffer size of %RU32 bytes / %RU64 ms\n",
770 uSD, cbCircBuf, PDMAudioPropsBytesToMilli(&pCfg->Props, cbCircBuf)));
771 }
772
773 /* Serious paranoia: */
774 ASSERT_GUEST_LOGREL_MSG_STMT(cbCircBuf % PDMAudioPropsFrameSize(&pCfg->Props) == 0,
775 ("Ring buffer size (%RU32) for stream #%RU8 not aligned to the (host) frame size (%RU8)\n",
776 cbCircBuf, uSD, PDMAudioPropsFrameSize(&pCfg->Props)),
777 rc = VERR_INVALID_PARAMETER);
778 ASSERT_GUEST_LOGREL_MSG_STMT(cbCircBuf, ("Ring buffer size for stream #%RU8 is invalid\n", uSD),
779 rc = VERR_INVALID_PARAMETER);
780 if (RT_SUCCESS(rc))
781 {
782 rc = RTCircBufCreate(&pStreamR3->State.pCircBuf, cbCircBuf);
783 if (RT_SUCCESS(rc))
784 {
785 pStreamR3->State.StatDmaBufSize = cbCircBuf;
786
787 /*
788 * Forward the timer frequency hint to TM as well for better accuracy on
789 * systems w/o preemption timers (also good for 'info timers').
790 */
791 PDMDevHlpTimerSetFrequencyHint(pDevIns, pStreamShared->hTimer, uTransferHz);
792 }
793 }
794
795 if (RT_FAILURE(rc))
796 LogRelMax(32, ("HDA: Initializing stream #%RU8 failed with %Rrc\n", uSD, rc));
797
798#ifdef VBOX_WITH_DTRACE
799 VBOXDD_HDA_STREAM_SETUP((uint32_t)uSD, rc, pStreamShared->State.Cfg.Props.uHz,
800 pStreamShared->State.aSchedule[pStreamShared->State.cSchedule - 1].cPeriodTicks,
801 pStreamShared->State.aSchedule[pStreamShared->State.cSchedule - 1].cbPeriod);
802#endif
803 return rc;
804}
805
806/**
807 * Resets an HDA stream.
808 *
809 * @param pThis The shared HDA device state.
810 * @param pThisCC The ring-3 HDA device state.
811 * @param pStreamShared HDA stream to reset (shared).
812 * @param pStreamR3 HDA stream to reset (ring-3).
813 * @param uSD Stream descriptor (SD) number to use for this stream.
814 */
815void hdaR3StreamReset(PHDASTATE pThis, PHDASTATER3 pThisCC, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD)
816{
817 LogFunc(("[SD%RU8] Reset\n", uSD));
818
819 /*
820 * Assert some sanity.
821 */
822 AssertPtr(pThis);
823 AssertPtr(pStreamShared);
824 AssertPtr(pStreamR3);
825 Assert(uSD < HDA_MAX_STREAMS);
826 Assert(pStreamShared->u8SD == uSD);
827 Assert(pStreamR3->u8SD == uSD);
828 AssertMsg(!pStreamShared->State.fRunning, ("[SD%RU8] Cannot reset stream while in running state\n", uSD));
829
830 /*
831 * Set reset state.
832 */
833 Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false); /* No nested calls. */
834 ASMAtomicXchgBool(&pStreamShared->State.fInReset, true);
835
836 /*
837 * Second, initialize the registers.
838 */
839 /* See 6.2.33: Clear on reset. */
840 HDA_STREAM_REG(pThis, STS, uSD) = 0;
841 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
842 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
843 HDA_STREAM_REG(pThis, CTL, uSD) = HDA_SDCTL_TP | (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_SDCTL_SRST);
844 /* ICH6 defines default values (120 bytes for input and 192 bytes for output descriptors) of FIFO size. 18.2.39. */
845 HDA_STREAM_REG(pThis, FIFOS, uSD) = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? HDA_SDIFIFO_120B : HDA_SDOFIFO_192B;
846 /* See 18.2.38: Always defaults to 0x4 (32 bytes). */
847 HDA_STREAM_REG(pThis, FIFOW, uSD) = HDA_SDFIFOW_32B;
848 HDA_STREAM_REG(pThis, LPIB, uSD) = 0;
849 HDA_STREAM_REG(pThis, CBL, uSD) = 0;
850 HDA_STREAM_REG(pThis, LVI, uSD) = 0;
851 HDA_STREAM_REG(pThis, FMT, uSD) = 0;
852 HDA_STREAM_REG(pThis, BDPU, uSD) = 0;
853 HDA_STREAM_REG(pThis, BDPL, uSD) = 0;
854
855#ifdef HDA_USE_DMA_ACCESS_HANDLER
856 hdaR3StreamUnregisterDMAHandlers(pThis, pStream);
857#endif
858
859 /* Assign the default mixer sink to the stream. */
860 pStreamR3->pMixSink = hdaR3GetDefaultSink(pThisCC, uSD);
861 if (pStreamR3->State.pAioRegSink)
862 {
863 int rc2 = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
864 AssertRC(rc2);
865 pStreamR3->State.pAioRegSink = NULL;
866 }
867
868 /* Reset transfer stuff. */
869 pStreamShared->State.cTransferPendingInterrupts = 0;
870 pStreamShared->State.tsTransferLast = 0;
871 pStreamShared->State.tsTransferNext = 0;
872
873 /* Initialize timestamps. */
874 pStreamShared->State.tsLastTransferNs = 0;
875 pStreamShared->State.tsLastReadNs = 0;
876 pStreamShared->State.tsAioDelayEnd = UINT64_MAX;
877 pStreamShared->State.tsStart = 0;
878
879 RT_ZERO(pStreamShared->State.aBdl);
880 RT_ZERO(pStreamShared->State.aSchedule);
881 pStreamShared->State.offCurBdle = 0;
882 pStreamShared->State.cBdles = 0;
883 pStreamShared->State.idxCurBdle = 0;
884 pStreamShared->State.cSchedulePrologue = 0;
885 pStreamShared->State.cSchedule = 0;
886 pStreamShared->State.idxSchedule = 0;
887 pStreamShared->State.idxScheduleLoop = 0;
888 pStreamShared->State.fInputPreBuffered = false;
889
890 if (pStreamR3->State.pCircBuf)
891 RTCircBufReset(pStreamR3->State.pCircBuf);
892 pStreamR3->State.offWrite = 0;
893 pStreamR3->State.offRead = 0;
894
895#ifdef DEBUG
896 pStreamR3->Dbg.cReadsTotal = 0;
897 pStreamR3->Dbg.cbReadTotal = 0;
898 pStreamR3->Dbg.tsLastReadNs = 0;
899 pStreamR3->Dbg.cWritesTotal = 0;
900 pStreamR3->Dbg.cbWrittenTotal = 0;
901 pStreamR3->Dbg.cWritesHz = 0;
902 pStreamR3->Dbg.cbWrittenHz = 0;
903 pStreamR3->Dbg.tsWriteSlotBegin = 0;
904#endif
905
906 /* Report that we're done resetting this stream. */
907 HDA_STREAM_REG(pThis, CTL, uSD) = 0;
908
909#ifdef VBOX_WITH_DTRACE
910 VBOXDD_HDA_STREAM_RESET((uint32_t)uSD);
911#endif
912 LogFunc(("[SD%RU8] Reset\n", uSD));
913
914 /* Exit reset mode. */
915 ASMAtomicXchgBool(&pStreamShared->State.fInReset, false);
916}
917
918/**
919 * Enables or disables an HDA audio stream.
920 *
921 * @returns VBox status code.
922 * @param pThis The shared HDA device state.
923 * @param pStreamShared HDA stream to enable or disable - shared bits.
924 * @param pStreamR3 HDA stream to enable or disable - ring-3 bits.
925 * @param fEnable Whether to enable or disble the stream.
926 */
927int hdaR3StreamEnable(PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, bool fEnable)
928{
929 AssertPtr(pStreamR3);
930 AssertPtr(pStreamShared);
931
932 LogFunc(("[SD%RU8] fEnable=%RTbool, pMixSink=%p\n", pStreamShared->u8SD, fEnable, pStreamR3->pMixSink));
933
934 /* First, enable or disable the stream and the stream's sink, if any. */
935 int rc = VINF_SUCCESS;
936 PAUDMIXSINK const pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
937 if (pSink)
938 {
939 if (fEnable)
940 {
941 if (pStreamR3->State.pAioRegSink != pSink)
942 {
943 if (pStreamR3->State.pAioRegSink)
944 {
945 rc = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
946 AssertRC(rc);
947 }
948 rc = AudioMixerSinkAddUpdateJob(pSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3,
949 pStreamShared->State.Cfg.Device.cMsSchedulingHint);
950 AssertLogRelRC(rc);
951 pStreamR3->State.pAioRegSink = RT_SUCCESS(rc) ? pSink : NULL;
952 }
953 rc = AudioMixerSinkStart(pSink);
954 }
955 else
956 rc = AudioMixerSinkDrainAndStop(pSink,
957 pStreamR3->State.pCircBuf ? (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf) : 0);
958 }
959 if ( RT_SUCCESS(rc)
960 && fEnable
961 && pStreamR3->Dbg.Runtime.fEnabled)
962 {
963 Assert(AudioHlpPcmPropsAreValid(&pStreamShared->State.Cfg.Props));
964
965 if (fEnable)
966 {
967 if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileStream))
968 {
969 int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileStream, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
970 &pStreamShared->State.Cfg.Props);
971 AssertRC(rc2);
972 }
973
974 if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileDMARaw))
975 {
976 int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileDMARaw, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
977 &pStreamShared->State.Cfg.Props);
978 AssertRC(rc2);
979 }
980
981 if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileDMAMapped))
982 {
983 int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileDMAMapped, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
984 &pStreamShared->State.Cfg.Props);
985 AssertRC(rc2);
986 }
987 }
988 }
989
990 if (RT_SUCCESS(rc))
991 {
992 if (fEnable)
993 pStreamShared->State.tsTransferLast = 0; /* Make sure it's not stale and messes up WALCLK calculations. */
994 pStreamShared->State.fRunning = fEnable;
995
996 /*
997 * Set the FIFORDY bit when we start running and clear it when stopping.
998 *
999 * This prevents Linux from timing out in snd_hdac_stream_sync when starting
1000 * a stream. Technically, Linux also uses the SSYNC feature there, but we
1001 * can get away with just setting the FIFORDY bit for now.
1002 */
1003 if (fEnable)
1004 HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) |= HDA_SDSTS_FIFORDY;
1005 else
1006 HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) &= ~HDA_SDSTS_FIFORDY;
1007 }
1008
1009 LogFunc(("[SD%RU8] rc=%Rrc\n", pStreamShared->u8SD, rc));
1010 return rc;
1011}
1012
1013/**
1014 * Marks the stream as started.
1015 *
1016 * Used after the stream has been enabled and the DMA timer has been armed.
1017 */
1018void hdaR3StreamMarkStarted(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint64_t tsNow)
1019{
1020 pStreamShared->State.tsLastReadNs = RTTimeNanoTS();
1021 pStreamShared->State.tsStart = tsNow;
1022 pStreamShared->State.tsAioDelayEnd = tsNow + PDMDevHlpTimerFromMilli(pDevIns, pStreamShared->hTimer, pThis->msInitialDelay);
1023 Log3Func(("#%u: tsStart=%RU64 tsAioDelayEnd=%RU64 tsLastReadNs=%RU64\n", pStreamShared->u8SD,
1024 pStreamShared->State.tsStart, pStreamShared->State.tsAioDelayEnd, pStreamShared->State.tsLastReadNs));
1025
1026}
1027
1028/**
1029 * Marks the stream as stopped.
1030 */
1031void hdaR3StreamMarkStopped(PHDASTREAM pStreamShared)
1032{
1033 Log3Func(("#%u\n", pStreamShared->u8SD));
1034 pStreamShared->State.tsAioDelayEnd = UINT64_MAX;
1035}
1036
1037
1038#if 0 /* Not used atm. */
1039static uint32_t hdaR3StreamGetPosition(PHDASTATE pThis, PHDASTREAM pStreamShared)
1040{
1041 return HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD);
1042}
1043#endif
1044
1045/**
1046 * Updates an HDA stream's current read or write buffer position (depending on the stream type) by
1047 * setting its associated LPIB register and DMA position buffer (if enabled) to an absolute value.
1048 *
1049 * @param pStreamShared HDA stream to update read / write position for (shared).
1050 * @param pDevIns The device instance.
1051 * @param pThis The shared HDA device state.
1052 * @param uLPIB Absolute position (in bytes) to set current read / write position to.
1053 */
1054static void hdaR3StreamSetPositionAbs(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uLPIB)
1055{
1056 AssertPtrReturnVoid(pStreamShared);
1057 AssertMsgStmt(uLPIB <= pStreamShared->u32CBL, ("%#x\n", uLPIB), uLPIB = pStreamShared->u32CBL);
1058
1059 Log3Func(("[SD%RU8] LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n", pStreamShared->u8SD, uLPIB, pThis->fDMAPosition));
1060
1061 /* Update LPIB in any case. */
1062 HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) = uLPIB;
1063
1064 /* Do we need to tell the current DMA position? */
1065 if (pThis->fDMAPosition)
1066 {
1067 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns,
1068 pThis->u64DPBase + (pStreamShared->u8SD * 2 * sizeof(uint32_t)),
1069 (void *)&uLPIB, sizeof(uint32_t));
1070 AssertRC(rc2);
1071 }
1072}
1073
1074/**
1075 * Updates an HDA stream's current read or write buffer position (depending on the stream type) by
1076 * adding a value to its associated LPIB register and DMA position buffer (if enabled).
1077 *
1078 * @note Handles automatic CBL wrap-around.
1079 *
1080 * @param pStreamShared HDA stream to update read / write position for (shared).
1081 * @param pDevIns The device instance.
1082 * @param pThis The shared HDA device state.
1083 * @param cbToAdd Position (in bytes) to add to the current read / write position.
1084 */
1085static void hdaR3StreamSetPositionAdd(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t cbToAdd)
1086{
1087 if (cbToAdd) /* No need to update anything if 0. */
1088 {
1089 uint32_t const uCBL = pStreamShared->u32CBL;
1090 if (uCBL) /* paranoia */
1091 {
1092 uint32_t uNewLpid = HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) + cbToAdd;
1093#if 1 /** @todo r=bird: this is wrong according to the spec */
1094 uNewLpid %= uCBL;
1095#else
1096 /* The spec says it goes to CBL then wraps arpimd to 1, not back to zero. See 3.3.37. */
1097 if (uNewLpid > uCBL)
1098 uNewLpid %= uCBL;
1099#endif
1100 hdaR3StreamSetPositionAbs(pStreamShared, pDevIns, pThis, uNewLpid);
1101 }
1102 }
1103}
1104
1105/**
1106 * Retrieves the available size of (buffered) audio data (in bytes) of a given HDA stream.
1107 *
1108 * @returns Available data (in bytes).
1109 * @param pStreamR3 HDA stream to retrieve size for (ring-3).
1110 */
1111static uint32_t hdaR3StreamGetUsed(PHDASTREAMR3 pStreamR3)
1112{
1113 AssertPtrReturn(pStreamR3, 0);
1114
1115 if (pStreamR3->State.pCircBuf)
1116 return (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1117 return 0;
1118}
1119
1120/**
1121 * Retrieves the free size of audio data (in bytes) of a given HDA stream.
1122 *
1123 * @returns Free data (in bytes).
1124 * @param pStreamR3 HDA stream to retrieve size for (ring-3).
1125 */
1126static uint32_t hdaR3StreamGetFree(PHDASTREAMR3 pStreamR3)
1127{
1128 AssertPtrReturn(pStreamR3, 0);
1129
1130 if (pStreamR3->State.pCircBuf)
1131 return (uint32_t)RTCircBufFree(pStreamR3->State.pCircBuf);
1132 return 0;
1133}
1134
1135/**
1136 * Get the current address and number of bytes left in the current BDLE.
1137 *
1138 * @returns The current physical address.
1139 * @param pStreamShared The stream to check.
1140 * @param pcbLeft The number of bytes left at the returned address.
1141 */
1142DECLINLINE(RTGCPHYS) hdaR3StreamDmaBufGet(PHDASTREAM pStreamShared, uint32_t *pcbLeft)
1143{
1144 uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1145 AssertStmt(idxBdle < pStreamShared->State.cBdles, idxBdle = 0);
1146
1147 uint32_t const cbCurBdl = pStreamShared->State.aBdl[idxBdle].cb;
1148 uint32_t offCurBdle = pStreamShared->State.offCurBdle;
1149 AssertStmt(pStreamShared->State.offCurBdle <= cbCurBdl, offCurBdle = cbCurBdl);
1150
1151 *pcbLeft = cbCurBdl - offCurBdle;
1152 return pStreamShared->State.aBdl[idxBdle].GCPhys + offCurBdle;
1153}
1154
1155/**
1156 * Get the size of the current BDLE.
1157 *
1158 * @returns The size (in bytes).
1159 * @param pStreamShared The stream to check.
1160 */
1161DECLINLINE(RTGCPHYS) hdaR3StreamDmaBufGetSize(PHDASTREAM pStreamShared)
1162{
1163 uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1164 AssertStmt(idxBdle < pStreamShared->State.cBdles, idxBdle = 0);
1165 return pStreamShared->State.aBdl[idxBdle].cb;
1166}
1167
1168/**
1169 * Checks if the current BDLE is completed.
1170 *
1171 * @retval true if complete
1172 * @retval false if not.
1173 * @param pStreamShared The stream to check.
1174 */
1175DECLINLINE(bool) hdaR3StreamDmaBufIsComplete(PHDASTREAM pStreamShared)
1176{
1177 uint8_t const idxBdle = pStreamShared->State.idxCurBdle;
1178 AssertReturn(idxBdle < pStreamShared->State.cBdles, true);
1179
1180 uint32_t const cbCurBdl = pStreamShared->State.aBdl[idxBdle].cb;
1181 uint32_t const offCurBdle = pStreamShared->State.offCurBdle;
1182 Assert(offCurBdle <= cbCurBdl);
1183 return offCurBdle >= cbCurBdl;
1184}
1185
1186/**
1187 * Checks if the current BDLE needs a completion IRQ.
1188 *
1189 * @retval true if IRQ is needed.
1190 * @retval false if not.
1191 * @param pStreamShared The stream to check.
1192 */
1193DECLINLINE(bool) hdaR3StreamDmaBufNeedsIrq(PHDASTREAM pStreamShared)
1194{
1195 uint8_t const idxBdle = pStreamShared->State.idxCurBdle;
1196 AssertReturn(idxBdle < pStreamShared->State.cBdles, false);
1197 return (pStreamShared->State.aBdl[idxBdle].fFlags & HDA_BDLE_F_IOC) != 0;
1198}
1199
1200/**
1201 * Advances the DMA engine to the next BDLE.
1202 *
1203 * @param pStreamShared The stream which DMA engine is to be updated.
1204 */
1205DECLINLINE(void) hdaR3StreamDmaBufAdvanceToNext(PHDASTREAM pStreamShared)
1206{
1207 uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1208 Assert(pStreamShared->State.offCurBdle == pStreamShared->State.aBdl[idxBdle].cb);
1209
1210 if (idxBdle < pStreamShared->State.cBdles - 1)
1211 idxBdle++;
1212 else
1213 idxBdle = 0;
1214 pStreamShared->State.idxCurBdle = idxBdle;
1215 pStreamShared->State.offCurBdle = 0;
1216}
1217
1218/**
1219 * Common do-DMA prologue code.
1220 *
1221 * @retval true if DMA processing can take place
1222 * @retval false if caller should return immediately.
1223 * @param pThis The shared HDA device state.
1224 * @param pStreamShared HDA stream to update (shared).
1225 * @param uSD The stream ID (for asserting).
1226 * @param tsNowNs The current RTTimeNano() value.
1227 * @param pszFunction The function name (for logging).
1228 */
1229DECLINLINE(bool) hdaR3StreamDoDmaPrologue(PHDASTATE pThis, PHDASTREAM pStreamShared, uint8_t uSD,
1230 uint64_t tsNowNs, const char *pszFunction)
1231{
1232 RT_NOREF(uSD, pszFunction);
1233
1234 /*
1235 * Check if we should skip town...
1236 */
1237 /* Stream not running (anymore)? */
1238 if (pStreamShared->State.fRunning)
1239 { /* likely */ }
1240 else
1241 {
1242 Log3(("%s: [SD%RU8] Not running, skipping transfer\n", pszFunction, uSD));
1243 return false;
1244 }
1245
1246 if (!(HDA_STREAM_REG(pThis, STS, uSD) & HDA_SDSTS_BCIS))
1247 { /* likely */ }
1248 else
1249 {
1250 Log3(("%s: [SD%RU8] BCIS bit set, skipping transfer\n", pszFunction, uSD));
1251#ifdef HDA_STRICT
1252 /* Timing emulation bug or guest is misbehaving -- let me know. */
1253 AssertMsgFailed(("%s: BCIS bit for stream #%RU8 still set when it shouldn't\n", pszFunction, uSD));
1254#endif
1255 return false;
1256 }
1257
1258 /*
1259 * Stream sanity checks.
1260 */
1261 /* Register sanity checks. */
1262 Assert(uSD < HDA_MAX_STREAMS);
1263 Assert(pStreamShared->u64BDLBase);
1264 Assert(pStreamShared->u32CBL);
1265 Assert(pStreamShared->u8FIFOS);
1266
1267 /* State sanity checks. */
1268 Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false);
1269 Assert(ASMAtomicReadBool(&pStreamShared->State.fRunning));
1270
1271 /*
1272 * Some timestamp stuff for logging/debugging.
1273 */
1274 /*const uint64_t tsNowNs = RTTimeNanoTS();*/
1275 Log3(("%s: [SD%RU8] tsDeltaNs=%'RU64 ns\n", pszFunction, uSD, tsNowNs - pStreamShared->State.tsLastTransferNs));
1276 pStreamShared->State.tsLastTransferNs = tsNowNs;
1277
1278 return true;
1279}
1280
1281/**
1282 * Common do-DMA epilogue.
1283 *
1284 * @param pDevIns The device instance.
1285 * @param pStreamShared The HDA stream (shared).
1286 * @param pStreamR3 The HDA stream (ring-3).
1287 */
1288DECLINLINE(void) hdaR3StreamDoDmaEpilogue(PPDMDEVINS pDevIns, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
1289{
1290 /*
1291 * We must update this in the epilogue rather than in the prologue
1292 * as it is used for WALCLK calculation and we must make sure the
1293 * guest doesn't think we've processed the current period till we
1294 * actually have.
1295 */
1296 pStreamShared->State.tsTransferLast = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer);
1297
1298 /*
1299 * Update the buffer statistics.
1300 */
1301 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1302}
1303
1304/**
1305 * Completes a BDLE at the end of a DMA loop iteration, if possible.
1306 *
1307 * @param pDevIns The device instance.
1308 * @param pThis The shared HDA device state.
1309 * @param pStreamShared HDA stream to update (shared).
1310 * @param pszFunction The function name (for logging).
1311 */
1312DECLINLINE(void) hdaR3StreamDoDmaMaybeCompleteBuffer(PPDMDEVINS pDevIns, PHDASTATE pThis,
1313 PHDASTREAM pStreamShared, const char *pszFunction)
1314{
1315 RT_NOREF(pszFunction);
1316
1317 /*
1318 * Is the buffer descriptor complete.
1319 */
1320 if (hdaR3StreamDmaBufIsComplete(pStreamShared))
1321 {
1322 Log3(("%s: [SD%RU8] Completed BDLE%u %#RX64 LB %#RX32 fFlags=%#x\n", pszFunction, pStreamShared->u8SD,
1323 pStreamShared->State.idxCurBdle, pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].GCPhys,
1324 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].cb,
1325 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].fFlags));
1326
1327 /*
1328 * Update the stream's current position.
1329 *
1330 * Do this as accurate and close to the actual data transfer as possible.
1331 * All guests rely on this, depending on the mechanism they use (LPIB register or DMA counters).
1332 *
1333 * Note for Windows 10: The OS' driver is *very* picky about *when* the (DMA) positions get updated!
1334 * Not doing this at the right time will result in ugly sound crackles!
1335 */
1336 hdaR3StreamSetPositionAdd(pStreamShared, pDevIns, pThis, hdaR3StreamDmaBufGetSize(pStreamShared));
1337
1338 /* Does the current BDLE require an interrupt to be sent? */
1339 if (hdaR3StreamDmaBufNeedsIrq(pStreamShared))
1340 {
1341 /* If the IOCE ("Interrupt On Completion Enable") bit of the SDCTL
1342 register is set we need to generate an interrupt. */
1343 if (HDA_STREAM_REG(pThis, CTL, pStreamShared->u8SD) & HDA_SDCTL_IOCE)
1344 {
1345 /* Assert the interrupt before actually fetching the next BDLE below. */
1346 pStreamShared->State.cTransferPendingInterrupts = 1;
1347 Log3(("%s: [SD%RU8] Scheduling interrupt\n", pszFunction, pStreamShared->u8SD));
1348
1349 /* Trigger an interrupt first and let hdaRegWriteSDSTS() deal with
1350 * ending / beginning of a period. */
1351 /** @todo r=bird: What does the above comment mean? */
1352 HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) |= HDA_SDSTS_BCIS;
1353 HDA_PROCESS_INTERRUPT(pDevIns, pThis);
1354 }
1355 }
1356
1357 /*
1358 * Advance to the next BDLE.
1359 */
1360 hdaR3StreamDmaBufAdvanceToNext(pStreamShared);
1361 }
1362 else
1363 Log3(("%s: [SD%RU8] Not completed BDLE%u %#RX64 LB %#RX32 fFlags=%#x: off=%#RX32\n", pszFunction, pStreamShared->u8SD,
1364 pStreamShared->State.idxCurBdle, pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].GCPhys,
1365 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].cb,
1366 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].fFlags, pStreamShared->State.offCurBdle));
1367}
1368
1369/**
1370 * Does DMA transfer for an HDA input stream.
1371 *
1372 * Reads audio data from the HDA stream's internal DMA buffer and writing to
1373 * guest memory.
1374 *
1375 * @param pDevIns The device instance.
1376 * @param pThis The shared HDA device state.
1377 * @param pStreamShared HDA stream to update (shared).
1378 * @param pStreamR3 HDA stream to update (ring-3).
1379 * @param cbToConsume The max amount of data to consume from the
1380 * internal DMA buffer. The caller will make sure
1381 * this is always the transfer size fo the current
1382 * period (unless something is seriously wrong).
1383 * @param fWriteSilence Whether to feed the guest silence rather than
1384 * fetching bytes from the internal DMA buffer.
1385 * This is set initially while we pre-buffer a
1386 * little bit of input, so we can better handle
1387 * time catch-ups and other schduling fun.
1388 * @param tsNowNs The current RTTimeNano() value.
1389 *
1390 * @remarks Caller owns the stream lock.
1391 */
1392static void hdaR3StreamDoDmaInput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
1393 PHDASTREAMR3 pStreamR3, uint32_t cbToConsume, bool fWriteSilence, uint64_t tsNowNs)
1394{
1395 uint8_t const uSD = pStreamShared->u8SD;
1396 LogFlowFunc(("ENTER - #%u cbToConsume=%#x%s\n", uSD, cbToConsume, fWriteSilence ? " silence" : ""));
1397
1398 /*
1399 * Common prologue.
1400 */
1401 if (hdaR3StreamDoDmaPrologue(pThis, pStreamShared, uSD, tsNowNs, "hdaR3StreamDoDmaInput"))
1402 { /* likely */ }
1403 else
1404 return;
1405
1406 /*
1407 *
1408 * The DMA copy loop.
1409 *
1410 */
1411 uint8_t abBounce[4096 + 128]; /* Most guest does at most 4KB BDLE. So, 4KB + space for a partial frame to reduce loops. */
1412 uint32_t cbBounce = 0; /* in case of incomplete frames between buffer segments */
1413 PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1414 uint32_t cbLeft = cbToConsume;
1415 Assert(cbLeft == pStreamShared->State.cbTransferSize);
1416 Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1417
1418 while (cbLeft > 0)
1419 {
1420 STAM_PROFILE_START(&pThis->StatIn, a);
1421
1422 /*
1423 * Figure out how much we can read & write in this iteration.
1424 */
1425 uint32_t cbChunk = 0;
1426 RTGCPHYS GCPhys = hdaR3StreamDmaBufGet(pStreamShared, &cbChunk);
1427
1428 /* If we're writing silence. */
1429 if (!fWriteSilence)
1430 {
1431 if (cbChunk <= cbLeft)
1432 { /* very likely */ }
1433 else
1434 cbChunk = cbLeft;
1435
1436 /*
1437 * Write the host data directly into the guest buffers.
1438 */
1439 while (cbChunk > 0)
1440 {
1441 /* Grab internal DMA buffer space and read into it. */
1442 void /*const*/ *pvBufSrc;
1443 size_t cbBufSrc;
1444 RTCircBufAcquireReadBlock(pCircBuf, cbChunk, &pvBufSrc, &cbBufSrc);
1445 AssertBreakStmt(cbBufSrc, RTCircBufReleaseReadBlock(pCircBuf, 0));
1446
1447 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, GCPhys, pvBufSrc, cbBufSrc);
1448 AssertRC(rc2);
1449
1450#ifdef HDA_DEBUG_SILENCE
1451 fix me if relevant;
1452#endif
1453 if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1454 { /* likely */ }
1455 else
1456 AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufSrc, cbBufSrc, 0 /* fFlags */);
1457
1458#ifdef VBOX_WITH_DTRACE
1459 VBOXDD_HDA_STREAM_DMA_IN((uint32_t)uSD, (uint32_t)cbBufSrc, pStreamR3->State.offRead);
1460#endif
1461 pStreamR3->State.offRead += cbBufSrc;
1462 RTCircBufReleaseReadBlock(pCircBuf, cbBufSrc);
1463 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBufSrc);
1464
1465 /* advance */
1466 cbChunk -= (uint32_t)cbBufSrc;
1467 GCPhys += cbBufSrc;
1468 cbLeft -= (uint32_t)cbBufSrc;
1469 pStreamShared->State.offCurBdle += (uint32_t)cbBufSrc;
1470 }
1471 }
1472 /*
1473 * We've got some initial silence to write, or we need to do
1474 * channel mapping. We produce guest output into the bounce buffer,
1475 * which is then copied into guest memory. The bounce buffer may keep
1476 * partial frames there for the next BDLE, if an BDLE isn't frame aligned.
1477 *
1478 * Note! cbLeft is relative to the input (host) frame size.
1479 * cbChunk OTOH is relative to output (guest) size.
1480 */
1481 else
1482 {
1483/** @todo clean up host/guest props distinction, they're the same now w/o the
1484 * mapping done by the mixer rather than us. */
1485 PCPDMAUDIOPCMPROPS pGuestProps = &pStreamShared->State.Cfg.Props;
1486 Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1487 uint32_t const cbLeftGuest = PDMAudioPropsFramesToBytes(pGuestProps,
1488 PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props,
1489 cbLeft));
1490 if (cbChunk <= cbLeftGuest)
1491 { /* very likely */ }
1492 else
1493 cbChunk = cbLeftGuest;
1494
1495 /*
1496 * Work till we've covered the chunk.
1497 */
1498 Log5Func(("loop0: GCPhys=%RGp cbChunk=%#x + cbBounce=%#x\n", GCPhys, cbChunk, cbBounce));
1499 while (cbChunk > 0)
1500 {
1501 /* Figure out how much we need to convert into the bounce buffer: */
1502 uint32_t cbGuest = PDMAudioPropsRoundUpBytesToFrame(pGuestProps, cbChunk - cbBounce);
1503 uint32_t cFrames = PDMAudioPropsBytesToFrames(pGuestProps, RT_MIN(cbGuest, sizeof(abBounce) - cbBounce));
1504
1505 size_t cbBufSrc = PDMAudioPropsFramesToBytes(&pStreamShared->State.Cfg.Props, cFrames);
1506 cbGuest = PDMAudioPropsFramesToBytes(pGuestProps, cFrames);
1507 PDMAudioPropsClearBuffer(pGuestProps, &abBounce[cbBounce], cbGuest, cFrames);
1508 cbGuest += cbBounce;
1509
1510 /* Write it to the guest buffer. */
1511 uint32_t cbGuestActual = RT_MIN(cbGuest, cbChunk);
1512 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, GCPhys, abBounce, cbGuestActual);
1513 AssertRC(rc2);
1514 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbGuestActual);
1515
1516 /* advance */
1517 cbLeft -= (uint32_t)cbBufSrc;
1518 cbChunk -= cbGuestActual;
1519 GCPhys += cbGuestActual;
1520 pStreamShared->State.offCurBdle += cbGuestActual;
1521
1522 cbBounce = cbGuest - cbGuestActual;
1523 if (cbBounce)
1524 memmove(abBounce, &abBounce[cbGuestActual], cbBounce);
1525
1526 Log5Func((" loop1: GCPhys=%RGp cbGuestActual=%#x cbBounce=%#x cFrames=%#x\n", GCPhys, cbGuestActual, cbBounce, cFrames));
1527 }
1528 Log5Func(("loop0: GCPhys=%RGp cbBounce=%#x cbLeft=%#x\n", GCPhys, cbBounce, cbLeft));
1529 }
1530
1531 STAM_PROFILE_STOP(&pThis->StatIn, a);
1532
1533 /*
1534 * Complete the buffer if necessary (common with the output DMA code).
1535 */
1536 hdaR3StreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaR3StreamDoDmaInput");
1537 }
1538
1539 Assert(cbLeft == 0); /* There shall be no break statements in the above loop, so cbLeft is always zero here! */
1540 AssertMsg(cbBounce == 0, ("%#x\n", cbBounce));
1541
1542 /*
1543 * Common epilogue.
1544 */
1545 hdaR3StreamDoDmaEpilogue(pDevIns, pStreamShared, pStreamR3);
1546
1547 /*
1548 * Log and leave.
1549 */
1550 Log3Func(("LEAVE - [SD%RU8] %#RX32/%#RX32 @ %#RX64 - cTransferPendingInterrupts=%RU8\n",
1551 uSD, cbToConsume, pStreamShared->State.cbTransferSize, pStreamR3->State.offRead - cbToConsume,
1552 pStreamShared->State.cTransferPendingInterrupts));
1553}
1554
1555
1556/**
1557 * Input streams: Pulls data from the mixer, putting it in the internal DMA
1558 * buffer.
1559 *
1560 * @param pStreamR3 HDA stream to update (ring-3 bits).
1561 * @param pSink The mixer sink to pull from.
1562 */
1563static void hdaR3StreamPullFromMixer(PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink)
1564{
1565#ifdef LOG_ENABLED
1566 uint64_t const offWriteOld = pStreamR3->State.offWrite;
1567#endif
1568 pStreamR3->State.offWrite = AudioMixerSinkTransferToCircBuf(pSink,
1569 pStreamR3->State.pCircBuf,
1570 pStreamR3->State.offWrite,
1571 pStreamR3->u8SD,
1572 pStreamR3->Dbg.Runtime.fEnabled
1573 ? pStreamR3->Dbg.Runtime.pFileStream : NULL);
1574
1575 Log3Func(("[SD%RU8] transferred=%#RX64 bytes -> @%#RX64\n", pStreamR3->u8SD,
1576 pStreamR3->State.offWrite - offWriteOld, pStreamR3->State.offWrite));
1577
1578 /* Update buffer stats. */
1579 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1580}
1581
1582
1583/**
1584 * Does DMA transfer for an HDA output stream.
1585 *
1586 * This transfers one DMA timer period worth of data from the guest and into the
1587 * internal DMA buffer.
1588 *
1589 * @param pDevIns The device instance.
1590 * @param pThis The shared HDA device state.
1591 * @param pStreamShared HDA stream to update (shared).
1592 * @param pStreamR3 HDA stream to update (ring-3).
1593 * @param cbToProduce The max amount of data to produce (i.e. put into
1594 * the circular buffer). Unless something is going
1595 * seriously wrong, this will always be transfer
1596 * size for the current period.
1597 * @param tsNowNs The current RTTimeNano() value.
1598 *
1599 * @remarks Caller owns the stream lock.
1600 */
1601static void hdaR3StreamDoDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
1602 PHDASTREAMR3 pStreamR3, uint32_t cbToProduce, uint64_t tsNowNs)
1603{
1604 uint8_t const uSD = pStreamShared->u8SD;
1605 LogFlowFunc(("ENTER - #%u cbToProduce=%#x\n", uSD, cbToProduce));
1606
1607 /*
1608 * Common prologue.
1609 */
1610 if (hdaR3StreamDoDmaPrologue(pThis, pStreamShared, uSD, tsNowNs, "hdaR3StreamDoDmaOutput"))
1611 { /* likely */ }
1612 else
1613 return;
1614
1615 /*
1616 *
1617 * The DMA copy loop.
1618 *
1619 */
1620#if 0
1621 uint8_t abBounce[4096 + 128]; /* Most guest does at most 4KB BDLE. So, 4KB + space for a partial frame to reduce loops. */
1622 uint32_t cbBounce = 0; /* in case of incomplete frames between buffer segments */
1623#endif
1624 PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1625 uint32_t cbLeft = cbToProduce;
1626 Assert(cbLeft == pStreamShared->State.cbTransferSize);
1627 Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1628
1629 while (cbLeft > 0)
1630 {
1631 STAM_PROFILE_START(&pThis->StatOut, a);
1632
1633 /*
1634 * Figure out how much we can read & write in this iteration.
1635 */
1636 uint32_t cbChunk = 0;
1637 RTGCPHYS GCPhys = hdaR3StreamDmaBufGet(pStreamShared, &cbChunk);
1638
1639 /* Need to diverge if the BDLEs contain misaligned entries. */
1640#if 0
1641 if (/** @todo pStreamShared->State.fFrameAlignedBuffers */)
1642#endif
1643 {
1644 if (cbChunk <= cbLeft)
1645 { /* very likely */ }
1646 else
1647 cbChunk = cbLeft;
1648
1649 /*
1650 * Read the guest data directly into the internal DMA buffer.
1651 */
1652 while (cbChunk > 0)
1653 {
1654 /* Grab internal DMA buffer space and read into it. */
1655 void *pvBufDst;
1656 size_t cbBufDst;
1657 RTCircBufAcquireWriteBlock(pCircBuf, cbChunk, &pvBufDst, &cbBufDst);
1658 AssertBreakStmt(cbBufDst, RTCircBufReleaseWriteBlock(pCircBuf, 0));
1659
1660 int rc2 = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, pvBufDst, cbBufDst);
1661 AssertRC(rc2);
1662
1663#ifdef HDA_DEBUG_SILENCE
1664 fix me if relevant;
1665#endif
1666 if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1667 { /* likely */ }
1668 else
1669 AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst, 0 /* fFlags */);
1670
1671#ifdef VBOX_WITH_DTRACE
1672 VBOXDD_HDA_STREAM_DMA_OUT((uint32_t)uSD, (uint32_t)cbBufDst, pStreamR3->State.offWrite);
1673#endif
1674 pStreamR3->State.offWrite += cbBufDst;
1675 RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
1676 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBufDst);
1677
1678 /* advance */
1679 cbChunk -= (uint32_t)cbBufDst;
1680 GCPhys += cbBufDst;
1681 cbLeft -= (uint32_t)cbBufDst;
1682 pStreamShared->State.offCurBdle += (uint32_t)cbBufDst;
1683 }
1684 }
1685#if 0
1686 /*
1687 * Need to map the frame content, so we need to read the guest data
1688 * into a temporary buffer, though the output can be directly written
1689 * into the internal buffer as it is assumed to be frame aligned.
1690 *
1691 * Note! cbLeft is relative to the output frame size.
1692 * cbChunk OTOH is relative to input size.
1693 */
1694 else
1695 {
1696/** @todo clean up host/guest props distinction, they're the same now w/o the
1697 * mapping done by the mixer rather than us. */
1698 PCPDMAUDIOPCMPROPS pGuestProps = &pStreamShared->State.Cfg.Props;
1699 Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1700 uint32_t const cbLeftGuest = PDMAudioPropsFramesToBytes(pGuestProps,
1701 PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props,
1702 cbLeft));
1703 if (cbChunk <= cbLeftGuest)
1704 { /* very likely */ }
1705 else
1706 cbChunk = cbLeftGuest;
1707
1708 /*
1709 * Loop till we've covered the chunk.
1710 */
1711 Log5Func(("loop0: GCPhys=%RGp cbChunk=%#x + cbBounce=%#x\n", GCPhys, cbChunk, cbBounce));
1712 while (cbChunk > 0)
1713 {
1714 /* Read into the bounce buffer. */
1715 uint32_t const cbToRead = RT_MIN(cbChunk, sizeof(abBounce) - cbBounce);
1716 int rc2 = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &abBounce[cbBounce], cbToRead);
1717 AssertRC(rc2);
1718 cbBounce += cbToRead;
1719
1720 /* Convert the size to whole frames and a remainder. */
1721 uint32_t cFrames = PDMAudioPropsBytesToFrames(pGuestProps, cbBounce);
1722 uint32_t const cbRemainder = cbBounce - PDMAudioPropsFramesToBytes(pGuestProps, cFrames);
1723 Log5Func((" loop1: GCPhys=%RGp cbToRead=%#x cbBounce=%#x cFrames=%#x\n", GCPhys, cbToRead, cbBounce, cFrames));
1724
1725 /*
1726 * Convert from the bounce buffer and into the internal DMA buffer.
1727 */
1728 uint32_t offBounce = 0;
1729 while (cFrames > 0)
1730 {
1731 void *pvBufDst;
1732 size_t cbBufDst;
1733 RTCircBufAcquireWriteBlock(pCircBuf, PDMAudioPropsFramesToBytes(&pStreamShared->State.Cfg.Props, cFrames),
1734 &pvBufDst, &cbBufDst);
1735
1736 uint32_t const cFramesToConvert = PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props, (uint32_t)cbBufDst);
1737 Assert(PDMAudioPropsFramesToBytes(&pStreamShared->State.Cfg.Props, cFramesToConvert) == cbBufDst);
1738 Assert(cFramesToConvert > 0);
1739 Assert(cFramesToConvert <= cFrames);
1740
1741 pStreamR3->State.Mapping.pfnGuestToHost(pvBufDst, &abBounce[offBounce], cFramesToConvert,
1742 &pStreamR3->State.Mapping);
1743 Log5Func((" loop2: offBounce=%#05x cFramesToConvert=%#05x cbBufDst=%#x%s\n",
1744 offBounce, cFramesToConvert, cbBufDst, ASMMemIsZero(pvBufDst, cbBufDst) ? " all zero" : ""));
1745
1746# ifdef HDA_DEBUG_SILENCE
1747 fix me if relevant;
1748# endif
1749 if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1750 { /* likely */ }
1751 else
1752 AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst, 0 /* fFlags */);
1753
1754 pStreamR3->State.offWrite += cbBufDst;
1755 RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
1756 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBufDst);
1757
1758 /* advance */
1759 cbLeft -= (uint32_t)cbBufDst;
1760 cFrames -= cFramesToConvert;
1761 offBounce += PDMAudioPropsFramesToBytes(pGuestProps, cFramesToConvert);
1762 }
1763
1764 /* advance */
1765 cbChunk -= cbToRead;
1766 GCPhys += cbToRead;
1767 pStreamShared->State.offCurBdle += cbToRead;
1768 if (cbRemainder)
1769 memmove(&abBounce[0], &abBounce[cbBounce - cbRemainder], cbRemainder);
1770 cbBounce = cbRemainder;
1771 }
1772 Log5Func(("loop0: GCPhys=%RGp cbBounce=%#x cbLeft=%#x\n", GCPhys, cbBounce, cbLeft));
1773 }
1774#endif
1775
1776 STAM_PROFILE_STOP(&pThis->StatOut, a);
1777
1778 /*
1779 * Complete the buffer if necessary (common with the output DMA code).
1780 */
1781 hdaR3StreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaR3StreamDoDmaOutput");
1782 }
1783
1784 Assert(cbLeft == 0); /* There shall be no break statements in the above loop, so cbLeft is always zero here! */
1785#if 0
1786 AssertMsg(cbBounce == 0, ("%#x\n", cbBounce));
1787#endif
1788
1789 /*
1790 * Common epilogue.
1791 */
1792 hdaR3StreamDoDmaEpilogue(pDevIns, pStreamShared, pStreamR3);
1793
1794 /*
1795 * Log and leave.
1796 */
1797 Log3Func(("LEAVE - [SD%RU8] %#RX32/%#RX32 @ %#RX64 - cTransferPendingInterrupts=%RU8\n",
1798 uSD, cbToProduce, pStreamShared->State.cbTransferSize, pStreamR3->State.offWrite - cbToProduce,
1799 pStreamShared->State.cTransferPendingInterrupts));
1800}
1801
1802
1803/**
1804 * Output streams: Pushes data to the mixer.
1805 *
1806 * @param pStreamShared HDA stream to update (shared bits).
1807 * @param pStreamR3 HDA stream to update (ring-3 bits).
1808 * @param pSink The mixer sink to push to.
1809 * @param nsNow The current RTTimeNanoTS() value.
1810 */
1811static void hdaR3StreamPushToMixer(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink, uint64_t nsNow)
1812{
1813#ifdef LOG_ENABLED
1814 uint64_t const offReadOld = pStreamR3->State.offRead;
1815#endif
1816 pStreamR3->State.offRead = AudioMixerSinkTransferFromCircBuf(pSink,
1817 pStreamR3->State.pCircBuf,
1818 pStreamR3->State.offRead,
1819 pStreamR3->u8SD,
1820 pStreamR3->Dbg.Runtime.fEnabled
1821 ? pStreamR3->Dbg.Runtime.pFileStream : NULL);
1822
1823 Assert(nsNow >= pStreamShared->State.tsLastReadNs);
1824 Log3Func(("[SD%RU8] nsDeltaLastRead=%RI64 transferred=%#RX64 bytes -> @%#RX64\n", pStreamR3->u8SD,
1825 nsNow - pStreamShared->State.tsLastReadNs, pStreamR3->State.offRead - offReadOld, pStreamR3->State.offRead));
1826 RT_NOREF(pStreamShared, nsNow);
1827
1828 /* Update buffer stats. */
1829 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1830}
1831
1832
1833/**
1834 * The stream's main function when called by the timer.
1835 *
1836 * @note This function also will be called without timer invocation when
1837 * starting (enabling) the stream to minimize startup latency.
1838 *
1839 * @returns Current timer time if the timer is enabled, otherwise zero.
1840 * @param pDevIns The device instance.
1841 * @param pThis The shared HDA device state.
1842 * @param pThisCC The ring-3 HDA device state.
1843 * @param pStreamShared HDA stream to update (shared bits).
1844 * @param pStreamR3 HDA stream to update (ring-3 bits).
1845 */
1846uint64_t hdaR3StreamTimerMain(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
1847 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
1848{
1849 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
1850 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pStreamShared->hTimer));
1851
1852 /* Do the work: */
1853 hdaR3StreamUpdateDma(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3);
1854
1855 /* Re-arm the timer if the sink is still active: */
1856 if ( pStreamShared->State.fRunning
1857 && pStreamR3->pMixSink
1858 && AudioMixerSinkIsActive(pStreamR3->pMixSink->pMixSink))
1859 {
1860 /* Advance the schduling: */
1861 uint32_t idxSched = pStreamShared->State.idxSchedule;
1862 AssertStmt(idxSched < RT_ELEMENTS(pStreamShared->State.aSchedule), idxSched = 0);
1863 uint32_t idxLoop = pStreamShared->State.idxScheduleLoop + 1;
1864 if (idxLoop >= pStreamShared->State.aSchedule[idxSched].cLoops)
1865 {
1866 idxSched += 1;
1867 if ( idxSched >= pStreamShared->State.cSchedule
1868 || idxSched >= RT_ELEMENTS(pStreamShared->State.aSchedule) /*paranoia^2*/)
1869 {
1870 idxSched = pStreamShared->State.cSchedulePrologue;
1871 AssertStmt(idxSched < RT_ELEMENTS(pStreamShared->State.aSchedule), idxSched = 0);
1872 }
1873 pStreamShared->State.idxSchedule = idxSched;
1874 idxLoop = 0;
1875 }
1876 pStreamShared->State.idxScheduleLoop = (uint16_t)idxLoop;
1877
1878 /* Do the actual timer re-arming. */
1879 uint64_t const tsNow = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer); /* (For virtual sync this remains the same for the whole callout IIRC) */
1880 uint64_t const tsTransferNext = tsNow + pStreamShared->State.aSchedule[idxSched].cPeriodTicks;
1881 Log3Func(("[SD%RU8] fSinkActive=true, tsTransferNext=%RU64 (in %RU64)\n",
1882 pStreamShared->u8SD, tsTransferNext, tsTransferNext - tsNow));
1883 int rc = PDMDevHlpTimerSet(pDevIns, pStreamShared->hTimer, tsTransferNext);
1884 AssertRC(rc);
1885
1886 /* Some legacy stuff: */
1887 pStreamShared->State.tsTransferNext = tsTransferNext;
1888 pStreamShared->State.cbTransferSize = pStreamShared->State.aSchedule[idxSched].cbPeriod;
1889
1890 return tsNow;
1891 }
1892
1893 Log3Func(("[SD%RU8] fSinkActive=false\n", pStreamShared->u8SD));
1894 return 0;
1895}
1896
1897
1898/**
1899 * Updates a HDA stream by doing DMA transfers.
1900 *
1901 * Will do mixer transfers too to try fix an overrun/underrun situation.
1902 *
1903 * The host sink(s) set the overall pace (bird: no it doesn't, the DMA timer
1904 * does - we just hope like heck it matches the speed at which the *backend*
1905 * host audio driver processes samples).
1906 *
1907 * @param pDevIns The device instance.
1908 * @param pThis The shared HDA device state.
1909 * @param pThisCC The ring-3 HDA device state.
1910 * @param pStreamShared HDA stream to update (shared bits).
1911 * @param pStreamR3 HDA stream to update (ring-3 bits).
1912 */
1913static void hdaR3StreamUpdateDma(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
1914 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
1915{
1916 RT_NOREF(pThisCC);
1917 int rc2;
1918
1919 /*
1920 * Make sure we're running and got an active mixer sink.
1921 */
1922 if (RT_LIKELY(pStreamShared->State.fRunning))
1923 { /* likely */ }
1924 else
1925 return;
1926
1927 PAUDMIXSINK pSink = NULL;
1928 if (pStreamR3->pMixSink)
1929 pSink = pStreamR3->pMixSink->pMixSink;
1930 if (RT_LIKELY(AudioMixerSinkIsActive(pSink)))
1931 { /* likely */ }
1932 else
1933 return;
1934
1935 /*
1936 * Get scheduling info common to both input and output streams.
1937 */
1938 const uint64_t tsNowNs = RTTimeNanoTS();
1939 uint32_t idxSched = pStreamShared->State.idxSchedule;
1940 AssertStmt(idxSched < RT_MIN(RT_ELEMENTS(pStreamShared->State.aSchedule), pStreamShared->State.cSchedule), idxSched = 0);
1941 uint32_t const cbPeriod = pStreamShared->State.aSchedule[idxSched].cbPeriod;
1942
1943 /*
1944 * Output streams (SDO).
1945 */
1946 if (hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_OUT)
1947 {
1948 /*
1949 * Check how much room we have in our DMA buffer. There should be at
1950 * least one period worth of space there or we're in an overflow situation.
1951 */
1952 uint32_t cbStreamFree = hdaR3StreamGetFree(pStreamR3);
1953 if (cbStreamFree >= cbPeriod)
1954 { /* likely */ }
1955 else
1956 {
1957 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowProblems);
1958 Log(("hdaR3StreamUpdateDma: Warning! Stream #%u has insufficient space free: %u bytes, need %u. Will try move data out of the buffer...\n",
1959 pStreamShared->u8SD, cbStreamFree, cbPeriod));
1960 int rc = AudioMixerSinkTryLock(pSink);
1961 if (RT_SUCCESS(rc))
1962 {
1963 hdaR3StreamPushToMixer(pStreamShared, pStreamR3, pSink, tsNowNs);
1964 AudioMixerSinkUpdate(pSink, 0, 0);
1965 AudioMixerSinkUnlock(pSink);
1966 }
1967 else
1968 RTThreadYield();
1969 Log(("hdaR3StreamUpdateDma: Gained %u bytes.\n", hdaR3StreamGetFree(pStreamR3) - cbStreamFree));
1970
1971 cbStreamFree = hdaR3StreamGetFree(pStreamR3);
1972 if (cbStreamFree < cbPeriod)
1973 {
1974 /* Unable to make sufficient space. Drop the whole buffer content.
1975 * This is needed in order to keep the device emulation running at a constant rate,
1976 * at the cost of losing valid (but too much) data. */
1977 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowErrors);
1978 LogRel2(("HDA: Warning: Hit stream #%RU8 overflow, dropping %u bytes of audio data\n",
1979 pStreamShared->u8SD, hdaR3StreamGetUsed(pStreamR3)));
1980# ifdef HDA_STRICT
1981 AssertMsgFailed(("Hit stream #%RU8 overflow -- timing bug?\n", pStreamShared->u8SD));
1982# endif
1983 RTCircBufReset(pStreamR3->State.pCircBuf);
1984 pStreamR3->State.offWrite = 0;
1985 pStreamR3->State.offRead = 0;
1986 cbStreamFree = hdaR3StreamGetFree(pStreamR3);
1987 }
1988 }
1989
1990 /*
1991 * Do the DMA transfer.
1992 */
1993 rc2 = PDMDevHlpCritSectEnter(pDevIns, &pStreamShared->CritSect, VERR_IGNORED);
1994 AssertRC(rc2);
1995
1996 uint64_t const offWriteBefore = pStreamR3->State.offWrite;
1997 hdaR3StreamDoDmaOutput(pDevIns, pThis, pStreamShared, pStreamR3, RT_MIN(cbStreamFree, cbPeriod), tsNowNs);
1998
1999 rc2 = PDMDevHlpCritSectLeave(pDevIns, &pStreamShared->CritSect);
2000 AssertRC(rc2);
2001
2002 /*
2003 * Should we push data to down thru the mixer to and to the host drivers?
2004 *
2005 * We initially delay this by pThis->msInitialDelay, but after than we'll
2006 * kick the AIO thread every time we've put more data in the buffer (which is
2007 * every time) as the host audio device needs to get data in a timely manner.
2008 *
2009 * (We used to try only wake up the AIO thread according to pThis->uIoTimer
2010 * and host wall clock, but that meant we would miss a wakup after the DMA
2011 * timer was called a little late or if TM entered into catch-up mode.)
2012 */
2013 bool fKickAioThread;
2014 if (!pStreamShared->State.tsAioDelayEnd)
2015 fKickAioThread = pStreamR3->State.offWrite > offWriteBefore
2016 || hdaR3StreamGetFree(pStreamR3) < pStreamShared->State.cbAvgTransfer * 2;
2017 else if (PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer) >= pStreamShared->State.tsAioDelayEnd)
2018 {
2019 Log3Func(("Initial delay done: Passed tsAioDelayEnd.\n"));
2020 pStreamShared->State.tsAioDelayEnd = 0;
2021 fKickAioThread = true;
2022 }
2023 else if (hdaR3StreamGetFree(pStreamR3) < pStreamShared->State.cbAvgTransfer * 2)
2024 {
2025 Log3Func(("Initial delay done: Passed running short on buffer.\n"));
2026 pStreamShared->State.tsAioDelayEnd = 0;
2027 fKickAioThread = true;
2028 }
2029 else
2030 {
2031 Log3Func(("Initial delay pending...\n"));
2032 fKickAioThread = false;
2033 }
2034
2035 Log3Func(("msDelta=%RU64 (vs %u) cbStreamFree=%#x (vs %#x) => fKickAioThread=%RTbool\n",
2036 (tsNowNs - pStreamShared->State.tsLastReadNs) / RT_NS_1MS,
2037 pStreamShared->State.Cfg.Device.cMsSchedulingHint, cbStreamFree,
2038 pStreamShared->State.cbAvgTransfer * 2, fKickAioThread));
2039
2040 if (fKickAioThread)
2041 {
2042 /* Notify the async I/O worker thread that there's work to do. */
2043 Log5Func(("Notifying AIO thread\n"));
2044 rc2 = AudioMixerSinkSignalUpdateJob(pSink);
2045 AssertRC(rc2);
2046 /* Update last read timestamp for logging/debugging. */
2047 pStreamShared->State.tsLastReadNs = tsNowNs;
2048 }
2049 }
2050 /*
2051 * Input stream (SDI).
2052 */
2053 else
2054 {
2055 Assert(hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_IN);
2056
2057 /*
2058 * See how much data we've got buffered...
2059 */
2060 bool fWriteSilence = false;
2061 uint32_t cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2062 if (pStreamShared->State.fInputPreBuffered && cbStreamUsed >= cbPeriod)
2063 { /*likely*/ }
2064 /*
2065 * Because it may take a while for the input stream to get going (at
2066 * least with pulseaudio), we feed the guest silence till we've
2067 * pre-buffer a reasonable amount of audio.
2068 */
2069 else if (!pStreamShared->State.fInputPreBuffered)
2070 {
2071 if (cbStreamUsed < pStreamShared->State.cbInputPreBuffer)
2072 {
2073 Log3(("hdaR3StreamUpdateDma: Pre-buffering (got %#x out of %#x bytes)...\n",
2074 cbStreamUsed, pStreamShared->State.cbInputPreBuffer));
2075 fWriteSilence = true;
2076 }
2077 else
2078 {
2079 Log3(("hdaR3StreamUpdateDma: Completed pre-buffering (got %#x, needed %#x bytes).\n",
2080 cbStreamUsed, pStreamShared->State.cbInputPreBuffer));
2081 pStreamShared->State.fInputPreBuffered = true;
2082 fWriteSilence = true; /* For now, just do the most conservative thing. */
2083 }
2084 cbStreamUsed = cbPeriod;
2085 }
2086 /*
2087 * When we're low on data, we must really try fetch some ourselves
2088 * as buffer underruns must not happen.
2089 */
2090 else
2091 {
2092 /** @todo We're ending up here to frequently with pulse audio at least (just
2093 * watch the stream stats in the statistcs viewer, and way to often we
2094 * have to inject silence bytes. I suspect part of the problem is
2095 * that the HDA device require a much better latency than what the
2096 * pulse audio is configured for by default (10 ms vs 150ms). */
2097 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowProblems);
2098 Log(("hdaR3StreamUpdateDma: Warning! Stream #%u has insufficient data available: %u bytes, need %u. Will try move pull more data into the buffer...\n",
2099 pStreamShared->u8SD, cbStreamUsed, cbPeriod));
2100 int rc = AudioMixerSinkTryLock(pSink);
2101 if (RT_SUCCESS(rc))
2102 {
2103 AudioMixerSinkUpdate(pSink, cbStreamUsed, cbPeriod);
2104 hdaR3StreamPullFromMixer(pStreamR3, pSink);
2105 AudioMixerSinkUnlock(pSink);
2106 }
2107 else
2108 RTThreadYield();
2109 Log(("hdaR3StreamUpdateDma: Gained %u bytes.\n", hdaR3StreamGetUsed(pStreamR3) - cbStreamUsed));
2110 cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2111 if (cbStreamUsed < cbPeriod)
2112 {
2113 /* Unable to find sufficient input data by simple prodding.
2114 In order to keep a constant byte stream following thru the DMA
2115 engine into the guest, we will try again and then fall back on
2116 filling the gap with silence. */
2117 uint32_t cbSilence = 0;
2118 do
2119 {
2120 AudioMixerSinkLock(pSink);
2121
2122 cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2123 if (cbStreamUsed < cbPeriod)
2124 {
2125 hdaR3StreamPullFromMixer(pStreamR3, pSink);
2126 cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2127 while (cbStreamUsed < cbPeriod)
2128 {
2129 void *pvDstBuf;
2130 size_t cbDstBuf;
2131 RTCircBufAcquireWriteBlock(pStreamR3->State.pCircBuf, cbPeriod - cbStreamUsed,
2132 &pvDstBuf, &cbDstBuf);
2133 RT_BZERO(pvDstBuf, cbDstBuf);
2134 RTCircBufReleaseWriteBlock(pStreamR3->State.pCircBuf, cbDstBuf);
2135 cbSilence += (uint32_t)cbDstBuf;
2136 cbStreamUsed += (uint32_t)cbDstBuf;
2137 }
2138 }
2139
2140 AudioMixerSinkUnlock(pSink);
2141 } while (cbStreamUsed < cbPeriod);
2142 if (cbSilence > 0)
2143 {
2144 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowErrors);
2145 STAM_REL_COUNTER_ADD(&pStreamR3->State.StatDmaFlowErrorBytes, cbSilence);
2146 LogRel2(("HDA: Warning: Stream #%RU8 underrun, added %u bytes of silence (%u us)\n", pStreamShared->u8SD,
2147 cbSilence, PDMAudioPropsBytesToMicro(&pStreamShared->State.Cfg.Props, cbSilence)));
2148 }
2149 }
2150 }
2151
2152 /*
2153 * Do the DMA'ing.
2154 */
2155 if (cbStreamUsed)
2156 {
2157 rc2 = PDMDevHlpCritSectEnter(pDevIns, &pStreamShared->CritSect, VERR_IGNORED);
2158 AssertRC(rc2);
2159
2160 hdaR3StreamDoDmaInput(pDevIns, pThis, pStreamShared, pStreamR3,
2161 RT_MIN(cbStreamUsed, cbPeriod), fWriteSilence, tsNowNs);
2162
2163 rc2 = PDMDevHlpCritSectLeave(pDevIns, &pStreamShared->CritSect);
2164 AssertRC(rc2);
2165 }
2166
2167 /*
2168 * We should always kick the AIO thread.
2169 */
2170 /** @todo This isn't entirely ideal. If we get into an underrun situation,
2171 * we ideally want the AIO thread to run right before the DMA timer
2172 * rather than right after it ran. */
2173 Log5Func(("Notifying AIO thread\n"));
2174 rc2 = AudioMixerSinkSignalUpdateJob(pSink);
2175 AssertRC(rc2);
2176 pStreamShared->State.tsLastReadNs = tsNowNs;
2177 }
2178}
2179
2180
2181/**
2182 * @callback_method_impl{FNAUDMIXSINKUPDATE}
2183 *
2184 * For output streams this moves data from the internal DMA buffer (in which
2185 * hdaR3StreamUpdateDma put it), thru the mixer and to the various backend audio
2186 * devices.
2187 *
2188 * For input streams this pulls data from the backend audio device(s), thru the
2189 * mixer and puts it in the internal DMA buffer ready for hdaR3StreamUpdateDma
2190 * to pump into guest memory.
2191 */
2192DECLCALLBACK(void) hdaR3StreamUpdateAsyncIoJob(PPDMDEVINS pDevIns, PAUDMIXSINK pSink, void *pvUser)
2193{
2194 PHDASTATE const pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
2195 PHDASTATER3 const pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
2196 PHDASTREAMR3 const pStreamR3 = (PHDASTREAMR3)pvUser;
2197 PHDASTREAM const pStreamShared = &pThis->aStreams[pStreamR3 - &pThisCC->aStreams[0]];
2198 Assert(pStreamR3 - &pThisCC->aStreams[0] == pStreamR3->u8SD);
2199 Assert(pStreamShared->u8SD == pStreamR3->u8SD);
2200 RT_NOREF(pSink);
2201
2202 /*
2203 * Make sure we haven't change sink and that it's still active (it
2204 * should be or we wouldn't have been called).
2205 */
2206 AssertReturnVoid(pStreamR3->pMixSink && pSink == pStreamR3->pMixSink->pMixSink);
2207 AssertReturnVoid(AudioMixerSinkIsActive(pSink));
2208
2209 /*
2210 * Output streams (SDO).
2211 */
2212 if (hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_OUT)
2213 hdaR3StreamPushToMixer(pStreamShared, pStreamR3, pSink, RTTimeNanoTS());
2214 /*
2215 * Input stream (SDI).
2216 */
2217 else
2218 {
2219 Assert(hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_IN);
2220 hdaR3StreamPullFromMixer(pStreamR3, pSink);
2221 }
2222}
2223
2224#endif /* IN_RING3 */
2225
2226/**
2227 * Locks an HDA stream for serialized access.
2228 *
2229 * @returns VBox status code.
2230 * @param pStreamShared HDA stream to lock (shared bits).
2231 */
2232void hdaStreamLock(PHDASTREAM pStreamShared)
2233{
2234 AssertPtrReturnVoid(pStreamShared);
2235 int rc2 = PDMCritSectEnter(&pStreamShared->CritSect, VINF_SUCCESS);
2236 AssertRC(rc2);
2237}
2238
2239/**
2240 * Unlocks a formerly locked HDA stream.
2241 *
2242 * @returns VBox status code.
2243 * @param pStreamShared HDA stream to unlock (shared bits).
2244 */
2245void hdaStreamUnlock(PHDASTREAM pStreamShared)
2246{
2247 AssertPtrReturnVoid(pStreamShared);
2248 int rc2 = PDMCritSectLeave(&pStreamShared->CritSect);
2249 AssertRC(rc2);
2250}
2251
2252#ifdef IN_RING3
2253
2254#if 0 /* unused - no prototype even */
2255/**
2256 * Updates an HDA stream's current read or write buffer position (depending on the stream type) by
2257 * updating its associated LPIB register and DMA position buffer (if enabled).
2258 *
2259 * @returns Set LPIB value.
2260 * @param pDevIns The device instance.
2261 * @param pStream HDA stream to update read / write position for.
2262 * @param u32LPIB New LPIB (position) value to set.
2263 */
2264uint32_t hdaR3StreamUpdateLPIB(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint32_t u32LPIB)
2265{
2266 AssertMsg(u32LPIB <= pStreamShared->u32CBL,
2267 ("[SD%RU8] New LPIB (%RU32) exceeds CBL (%RU32)\n", pStreamShared->u8SD, u32LPIB, pStreamShared->u32CBL));
2268
2269 u32LPIB = RT_MIN(u32LPIB, pStreamShared->u32CBL);
2270
2271 LogFlowFunc(("[SD%RU8] LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n",
2272 pStreamShared->u8SD, u32LPIB, pThis->fDMAPosition));
2273
2274 /* Update LPIB in any case. */
2275 HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) = u32LPIB;
2276
2277 /* Do we need to tell the current DMA position? */
2278 if (pThis->fDMAPosition)
2279 {
2280 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns,
2281 pThis->u64DPBase + (pStreamShared->u8SD * 2 * sizeof(uint32_t)),
2282 (void *)&u32LPIB, sizeof(uint32_t));
2283 AssertRC(rc2);
2284 }
2285
2286 return u32LPIB;
2287}
2288#endif
2289
2290# ifdef HDA_USE_DMA_ACCESS_HANDLER
2291/**
2292 * Registers access handlers for a stream's BDLE DMA accesses.
2293 *
2294 * @returns true if registration was successful, false if not.
2295 * @param pStream HDA stream to register BDLE access handlers for.
2296 */
2297bool hdaR3StreamRegisterDMAHandlers(PHDASTREAM pStream)
2298{
2299 /* At least LVI and the BDL base must be set. */
2300 if ( !pStreamShared->u16LVI
2301 || !pStreamShared->u64BDLBase)
2302 {
2303 return false;
2304 }
2305
2306 hdaR3StreamUnregisterDMAHandlers(pStream);
2307
2308 LogFunc(("Registering ...\n"));
2309
2310 int rc = VINF_SUCCESS;
2311
2312 /*
2313 * Create BDLE ranges.
2314 */
2315
2316 struct BDLERANGE
2317 {
2318 RTGCPHYS uAddr;
2319 uint32_t uSize;
2320 } arrRanges[16]; /** @todo Use a define. */
2321
2322 size_t cRanges = 0;
2323
2324 for (uint16_t i = 0; i < pStreamShared->u16LVI + 1; i++)
2325 {
2326 HDABDLE BDLE;
2327 rc = hdaR3BDLEFetch(pDevIns, &BDLE, pStreamShared->u64BDLBase, i /* Index */);
2328 if (RT_FAILURE(rc))
2329 break;
2330
2331 bool fAddRange = true;
2332 BDLERANGE *pRange;
2333
2334 if (cRanges)
2335 {
2336 pRange = &arrRanges[cRanges - 1];
2337
2338 /* Is the current range a direct neighbor of the current BLDE? */
2339 if ((pRange->uAddr + pRange->uSize) == BDLE.Desc.u64BufAddr)
2340 {
2341 /* Expand the current range by the current BDLE's size. */
2342 pRange->uSize += BDLE.Desc.u32BufSize;
2343
2344 /* Adding a new range in this case is not needed anymore. */
2345 fAddRange = false;
2346
2347 LogFunc(("Expanding range %zu by %RU32 (%RU32 total now)\n", cRanges - 1, BDLE.Desc.u32BufSize, pRange->uSize));
2348 }
2349 }
2350
2351 /* Do we need to add a new range? */
2352 if ( fAddRange
2353 && cRanges < RT_ELEMENTS(arrRanges))
2354 {
2355 pRange = &arrRanges[cRanges];
2356
2357 pRange->uAddr = BDLE.Desc.u64BufAddr;
2358 pRange->uSize = BDLE.Desc.u32BufSize;
2359
2360 LogFunc(("Adding range %zu - 0x%x (%RU32)\n", cRanges, pRange->uAddr, pRange->uSize));
2361
2362 cRanges++;
2363 }
2364 }
2365
2366 LogFunc(("%zu ranges total\n", cRanges));
2367
2368 /*
2369 * Register all ranges as DMA access handlers.
2370 */
2371
2372 for (size_t i = 0; i < cRanges; i++)
2373 {
2374 BDLERANGE *pRange = &arrRanges[i];
2375
2376 PHDADMAACCESSHANDLER pHandler = (PHDADMAACCESSHANDLER)RTMemAllocZ(sizeof(HDADMAACCESSHANDLER));
2377 if (!pHandler)
2378 {
2379 rc = VERR_NO_MEMORY;
2380 break;
2381 }
2382
2383 RTListAppend(&pStream->State.lstDMAHandlers, &pHandler->Node);
2384
2385 pHandler->pStream = pStream; /* Save a back reference to the owner. */
2386
2387 char szDesc[32];
2388 RTStrPrintf(szDesc, sizeof(szDesc), "HDA[SD%RU8 - RANGE%02zu]", pStream->u8SD, i);
2389
2390 int rc2 = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
2391 hdaDMAAccessHandler,
2392 NULL, NULL, NULL,
2393 NULL, NULL, NULL,
2394 szDesc, &pHandler->hAccessHandlerType);
2395 AssertRCBreak(rc2);
2396
2397 pHandler->BDLEAddr = pRange->uAddr;
2398 pHandler->BDLESize = pRange->uSize;
2399
2400 /* Get first and last pages of the BDLE range. */
2401 RTGCPHYS pgFirst = pRange->uAddr & ~PAGE_OFFSET_MASK;
2402 RTGCPHYS pgLast = RT_ALIGN(pgFirst + pRange->uSize, PAGE_SIZE);
2403
2404 /* Calculate the region size (in pages). */
2405 RTGCPHYS regionSize = RT_ALIGN(pgLast - pgFirst, PAGE_SIZE);
2406
2407 pHandler->GCPhysFirst = pgFirst;
2408 pHandler->GCPhysLast = pHandler->GCPhysFirst + (regionSize - 1);
2409
2410 LogFunc(("\tRegistering region '%s': 0x%x - 0x%x (region size: %zu)\n",
2411 szDesc, pHandler->GCPhysFirst, pHandler->GCPhysLast, regionSize));
2412 LogFunc(("\tBDLE @ 0x%x - 0x%x (%RU32)\n",
2413 pHandler->BDLEAddr, pHandler->BDLEAddr + pHandler->BDLESize, pHandler->BDLESize));
2414
2415 rc2 = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3),
2416 pHandler->GCPhysFirst, pHandler->GCPhysLast,
2417 pHandler->hAccessHandlerType, pHandler, NIL_RTR0PTR, NIL_RTRCPTR,
2418 szDesc);
2419 AssertRCBreak(rc2);
2420
2421 pHandler->fRegistered = true;
2422 }
2423
2424 LogFunc(("Registration ended with rc=%Rrc\n", rc));
2425
2426 return RT_SUCCESS(rc);
2427}
2428
2429/**
2430 * Unregisters access handlers of a stream's BDLEs.
2431 *
2432 * @param pStream HDA stream to unregister BDLE access handlers for.
2433 */
2434void hdaR3StreamUnregisterDMAHandlers(PHDASTREAM pStream)
2435{
2436 LogFunc(("\n"));
2437
2438 PHDADMAACCESSHANDLER pHandler, pHandlerNext;
2439 RTListForEachSafe(&pStream->State.lstDMAHandlers, pHandler, pHandlerNext, HDADMAACCESSHANDLER, Node)
2440 {
2441 if (!pHandler->fRegistered) /* Handler not registered? Skip. */
2442 continue;
2443
2444 LogFunc(("Unregistering 0x%x - 0x%x (%zu)\n",
2445 pHandler->GCPhysFirst, pHandler->GCPhysLast, pHandler->GCPhysLast - pHandler->GCPhysFirst));
2446
2447 int rc2 = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3),
2448 pHandler->GCPhysFirst);
2449 AssertRC(rc2);
2450
2451 RTListNodeRemove(&pHandler->Node);
2452
2453 RTMemFree(pHandler);
2454 pHandler = NULL;
2455 }
2456
2457 Assert(RTListIsEmpty(&pStream->State.lstDMAHandlers));
2458}
2459
2460# endif /* HDA_USE_DMA_ACCESS_HANDLER */
2461
2462#endif /* IN_RING3 */
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