VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevHdaStream.cpp@ 89861

Last change on this file since 89861 was 89861, checked in by vboxsync, 4 years ago

DevHda: Do LPIB updates more often. Experimental code for doing DMA work on LPIB read (disabled). bugref:9890
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File size: 113.1 KB
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1/* $Id: DevHdaStream.cpp 89861 2021-06-23 14:23:42Z vboxsync $ */
2/** @file
3 * Intel HD Audio Controller Emulation - Streams.
4 */
5
6/*
7 * Copyright (C) 2017-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_HDA
23#include <VBox/log.h>
24
25#include <iprt/mem.h>
26#include <iprt/semaphore.h>
27
28#include <VBox/AssertGuest.h>
29#include <VBox/vmm/pdmdev.h>
30#include <VBox/vmm/pdmaudioifs.h>
31#include <VBox/vmm/pdmaudioinline.h>
32
33#include "AudioHlp.h"
34
35#include "DevHda.h"
36#include "DevHdaStream.h"
37
38#ifdef VBOX_WITH_DTRACE
39# include "dtrace/VBoxDD.h"
40#endif
41
42
43/*********************************************************************************************************************************
44* Internal Functions *
45*********************************************************************************************************************************/
46static void hdaStreamSetPositionAbs(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uLPIB);
47#ifdef IN_RING3
48# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
49static void hdaR3StreamFlushDmaBounceBufferOutput(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
50# endif
51static uint32_t hdaR3StreamHandleDmaBufferOverrun(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink,
52 uint32_t cbNeeded, uint64_t nsNow,
53 const char *pszCaller, uint32_t const cbStreamFree);
54static void hdaR3StreamUpdateDma(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
55 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
56#endif
57
58
59#ifdef IN_RING3
60
61/**
62 * Creates an HDA stream.
63 *
64 * @returns VBox status code.
65 * @param pStreamShared The HDA stream to construct - shared bits.
66 * @param pStreamR3 The HDA stream to construct - ring-3 bits.
67 * @param pThis The shared HDA device instance.
68 * @param pThisCC The ring-3 HDA device instance.
69 * @param uSD Stream descriptor number to assign.
70 */
71int hdaR3StreamConstruct(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PHDASTATE pThis, PHDASTATER3 pThisCC, uint8_t uSD)
72{
73 pStreamR3->u8SD = uSD;
74 pStreamShared->u8SD = uSD;
75 pStreamR3->pMixSink = NULL;
76 pStreamR3->pHDAStateShared = pThis;
77 pStreamR3->pHDAStateR3 = pThisCC;
78 Assert(pStreamShared->hTimer != NIL_TMTIMERHANDLE); /* hdaR3Construct initalized this one already. */
79
80 pStreamShared->State.fInReset = false;
81 pStreamShared->State.fRunning = false;
82# ifdef HDA_USE_DMA_ACCESS_HANDLER
83 RTListInit(&pStreamR3->State.lstDMAHandlers);
84# endif
85
86 AssertPtr(pStreamR3->pHDAStateR3);
87 AssertPtr(pStreamR3->pHDAStateR3->pDevIns);
88
89# ifdef DEBUG
90 int rc = RTCritSectInit(&pStreamR3->Dbg.CritSect);
91 AssertRCReturn(rc, rc);
92# endif
93
94 const bool fIsInput = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN;
95
96 if (fIsInput)
97 {
98 pStreamShared->State.Cfg.enmPath = PDMAUDIOPATH_UNKNOWN;
99 pStreamShared->State.Cfg.enmDir = PDMAUDIODIR_IN;
100 }
101 else
102 {
103 pStreamShared->State.Cfg.enmPath = PDMAUDIOPATH_UNKNOWN;
104 pStreamShared->State.Cfg.enmDir = PDMAUDIODIR_OUT;
105 }
106
107 pStreamR3->Dbg.Runtime.fEnabled = pThisCC->Dbg.fEnabled;
108
109 if (pStreamR3->Dbg.Runtime.fEnabled)
110 {
111 char szFile[64];
112 char szPath[RTPATH_MAX];
113
114 /* pFileStream */
115 if (fIsInput)
116 RTStrPrintf(szFile, sizeof(szFile), "hdaStreamWriteSD%RU8", uSD);
117 else
118 RTStrPrintf(szFile, sizeof(szFile), "hdaStreamReadSD%RU8", uSD);
119
120 int rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
121 0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
122 AssertRC(rc2);
123
124 rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileStream);
125 AssertRC(rc2);
126
127 /* pFileDMARaw */
128 if (fIsInput)
129 RTStrPrintf(szFile, sizeof(szFile), "hdaDMARawWriteSD%RU8", uSD);
130 else
131 RTStrPrintf(szFile, sizeof(szFile), "hdaDMARawReadSD%RU8", uSD);
132
133 rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
134 0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
135 AssertRC(rc2);
136
137 rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileDMARaw);
138 AssertRC(rc2);
139
140 /* pFileDMAMapped */
141 if (fIsInput)
142 RTStrPrintf(szFile, sizeof(szFile), "hdaDMAWriteMappedSD%RU8", uSD);
143 else
144 RTStrPrintf(szFile, sizeof(szFile), "hdaDMAReadMappedSD%RU8", uSD);
145
146 rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
147 0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
148 AssertRC(rc2);
149
150 rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileDMAMapped);
151 AssertRC(rc2);
152
153 /* Delete stale debugging files from a former run. */
154 AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileStream);
155 AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileDMARaw);
156 AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileDMAMapped);
157 }
158
159 return VINF_SUCCESS;
160}
161
162/**
163 * Destroys an HDA stream.
164 *
165 * @param pStreamR3 The HDA stream to destroy - ring-3 bits.
166 */
167void hdaR3StreamDestroy(PHDASTREAMR3 pStreamR3)
168{
169 LogFlowFunc(("[SD%RU8] Destroying ...\n", pStreamR3->u8SD));
170 int rc2;
171
172 if (pStreamR3->State.pAioRegSink)
173 {
174 rc2 = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
175 AssertRC(rc2);
176 pStreamR3->State.pAioRegSink = NULL;
177 }
178
179 if (pStreamR3->State.pCircBuf)
180 {
181 RTCircBufDestroy(pStreamR3->State.pCircBuf);
182 pStreamR3->State.pCircBuf = NULL;
183 pStreamR3->State.StatDmaBufSize = 0;
184 pStreamR3->State.StatDmaBufUsed = 0;
185 }
186
187# ifdef DEBUG
188 if (RTCritSectIsInitialized(&pStreamR3->Dbg.CritSect))
189 {
190 rc2 = RTCritSectDelete(&pStreamR3->Dbg.CritSect);
191 AssertRC(rc2);
192 }
193# endif
194
195 if (pStreamR3->Dbg.Runtime.fEnabled)
196 {
197 AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileStream);
198 pStreamR3->Dbg.Runtime.pFileStream = NULL;
199
200 AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileDMARaw);
201 pStreamR3->Dbg.Runtime.pFileDMARaw = NULL;
202
203 AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileDMAMapped);
204 pStreamR3->Dbg.Runtime.pFileDMAMapped = NULL;
205 }
206
207 LogFlowFuncLeave();
208}
209
210
211/**
212 * Appends a item to the scheduler.
213 *
214 * @returns VBox status code.
215 * @param pStreamShared The stream which scheduler should be modified.
216 * @param cbCur The period length in guest bytes.
217 * @param cbMaxPeriod The max period in guest bytes.
218 * @param idxLastBdle The last BDLE in the period.
219 * @param pHostProps The host PCM properties.
220 * @param pGuestProps The guest PCM properties.
221 * @param pcbBorrow Where to account for bytes borrowed across buffers
222 * to align scheduling items on frame boundraries.
223 */
224static int hdaR3StreamAddScheduleItem(PHDASTREAM pStreamShared, uint32_t cbCur, uint32_t cbMaxPeriod, uint32_t idxLastBdle,
225 PCPDMAUDIOPCMPROPS pHostProps, PCPDMAUDIOPCMPROPS pGuestProps, uint32_t *pcbBorrow)
226{
227 /* Check that we've got room (shouldn't ever be a problem). */
228 size_t idx = pStreamShared->State.cSchedule;
229 AssertLogRelReturn(idx + 1 < RT_ELEMENTS(pStreamShared->State.aSchedule), VERR_INTERNAL_ERROR_5);
230
231 /* Figure out the BDLE range for this period. */
232 uint32_t const idxFirstBdle = idx == 0 ? 0
233 : RT_MIN((uint32_t)( pStreamShared->State.aSchedule[idx - 1].idxFirst
234 + pStreamShared->State.aSchedule[idx - 1].cEntries),
235 idxLastBdle);
236
237 pStreamShared->State.aSchedule[idx].idxFirst = (uint8_t)idxFirstBdle;
238 pStreamShared->State.aSchedule[idx].cEntries = idxLastBdle >= idxFirstBdle
239 ? idxLastBdle - idxFirstBdle + 1
240 : pStreamShared->State.cBdles - idxFirstBdle + idxLastBdle + 1;
241
242 /* Deal with borrowing due to unaligned IOC buffers. */
243 uint32_t const cbBorrowed = *pcbBorrow;
244 if (cbBorrowed < cbCur)
245 cbCur -= cbBorrowed;
246 else
247 {
248 /* Note. We can probably gloss over this, but it's not a situation a sane guest would put us, so don't bother for now. */
249 ASSERT_GUEST_MSG_FAILED(("#%u: cbBorrow=%#x cbCur=%#x BDLE[%u..%u]\n",
250 pStreamShared->u8SD, cbBorrowed, cbCur, idxFirstBdle, idxLastBdle));
251 LogRelMax(32, ("HDA: Stream #%u has a scheduling error: cbBorrow=%#x cbCur=%#x BDLE[%u..%u]\n",
252 pStreamShared->u8SD, cbBorrowed, cbCur, idxFirstBdle, idxLastBdle));
253 return VERR_OUT_OF_RANGE;
254 }
255
256 uint32_t cbCurAligned = PDMAudioPropsRoundUpBytesToFrame(pGuestProps, cbCur);
257 *pcbBorrow = cbCurAligned - cbCur;
258
259 /* Do we need to split up the period? */
260 if (cbCurAligned <= cbMaxPeriod)
261 {
262 uint32_t cbHost = PDMAudioPropsFramesToBytes(pHostProps, PDMAudioPropsBytesToFrames(pGuestProps, cbCurAligned));
263 pStreamShared->State.aSchedule[idx].cbPeriod = cbHost;
264 pStreamShared->State.aSchedule[idx].cLoops = 1;
265 }
266 else
267 {
268 /* Reduce till we've below the threshold. */
269 uint32_t cbLoop = cbCurAligned;
270 do
271 cbLoop = cbCurAligned / 2;
272 while (cbLoop > cbMaxPeriod);
273 cbLoop = PDMAudioPropsRoundUpBytesToFrame(pGuestProps, cbLoop);
274
275 /* Complete the scheduling item. */
276 uint32_t cbHost = PDMAudioPropsFramesToBytes(pHostProps, PDMAudioPropsBytesToFrames(pGuestProps, cbLoop));
277 pStreamShared->State.aSchedule[idx].cbPeriod = cbHost;
278 pStreamShared->State.aSchedule[idx].cLoops = cbCurAligned / cbLoop;
279
280 /* If there is a remainder, add it as a separate entry (this is
281 why the schedule must be more than twice the size of the BDL).*/
282 cbCurAligned %= cbLoop;
283 if (cbCurAligned)
284 {
285 pStreamShared->State.aSchedule[idx + 1] = pStreamShared->State.aSchedule[idx];
286 idx++;
287 cbHost = PDMAudioPropsFramesToBytes(pHostProps, PDMAudioPropsBytesToFrames(pGuestProps, cbCurAligned));
288 pStreamShared->State.aSchedule[idx].cbPeriod = cbHost;
289 pStreamShared->State.aSchedule[idx].cLoops = 1;
290 }
291 }
292
293 /* Done. */
294 pStreamShared->State.cSchedule = (uint16_t)(idx + 1);
295
296 return VINF_SUCCESS;
297}
298
299/**
300 * Creates the DMA timer schedule for the stream
301 *
302 * This is called from the stream setup code.
303 *
304 * @returns VBox status code.
305 * @param pStreamShared The stream to create a schedule for. The BDL
306 * must be loaded.
307 * @param cSegments Number of BDL segments.
308 * @param cBufferIrqs Number of the BDLEs with IOC=1.
309 * @param cbTotal The total BDL length in guest bytes.
310 * @param cbMaxPeriod Max period in guest bytes. This is in case the
311 * guest want to play the whole "Der Ring des
312 * Nibelungen" cycle in one go.
313 * @param cTimerTicksPerSec The DMA timer frequency.
314 * @param pHostProps The host PCM properties.
315 * @param pGuestProps The guest PCM properties.
316 */
317static int hdaR3StreamCreateSchedule(PHDASTREAM pStreamShared, uint32_t cSegments, uint32_t cBufferIrqs, uint32_t cbTotal,
318 uint32_t cbMaxPeriod, uint64_t cTimerTicksPerSec,
319 PCPDMAUDIOPCMPROPS pHostProps, PCPDMAUDIOPCMPROPS pGuestProps)
320{
321 int rc;
322
323 /*
324 * Reset scheduling state.
325 */
326 RT_ZERO(pStreamShared->State.aSchedule);
327 pStreamShared->State.cSchedule = 0;
328 pStreamShared->State.cSchedulePrologue = 0;
329 pStreamShared->State.idxSchedule = 0;
330 pStreamShared->State.idxScheduleLoop = 0;
331
332 /*
333 * Do the basic schedule compilation.
334 */
335 uint32_t cPotentialPrologue = 0;
336 uint32_t cbBorrow = 0;
337 uint32_t cbCur = 0;
338 uint32_t cbMin = UINT32_MAX;
339 pStreamShared->State.aSchedule[0].idxFirst = 0;
340 for (uint32_t i = 0; i < cSegments; i++)
341 {
342 cbCur += pStreamShared->State.aBdl[i].cb;
343 if (pStreamShared->State.aBdl[i].cb < cbMin)
344 cbMin = pStreamShared->State.aBdl[i].cb;
345 if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
346 {
347 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur, cbMaxPeriod, i, pHostProps, pGuestProps, &cbBorrow);
348 ASSERT_GUEST_RC_RETURN(rc, rc);
349
350 if (cPotentialPrologue == 0)
351 cPotentialPrologue = pStreamShared->State.cSchedule;
352 cbCur = 0;
353 }
354 }
355 AssertLogRelMsgReturn(cbBorrow == 0, ("HDA: Internal scheduling error on stream #%u: cbBorrow=%#x cbTotal=%#x cbCur=%#x\n",
356 pStreamShared->u8SD, cbBorrow, cbTotal, cbCur),
357 VERR_INTERNAL_ERROR_3);
358
359 /*
360 * Deal with any loose ends.
361 */
362 if (cbCur && cBufferIrqs == 0)
363 {
364 /*
365 * No IOC. Vista ends up here, typically with three buffers configured.
366 *
367 * The perferred option here is to aim at processing one average BDLE with
368 * each DMA timer period, since that best matches how we update LPIB at
369 * present.
370 *
371 * The second alternative is to divide the whole span up into 3-4 periods
372 * to try increase our chances of keeping ahead of the guest. We may need
373 * to pick this if there are too few buffer descriptor or they are too small.
374 *
375 * However, what we probably should be doing is to do real DMA work whenever
376 * the guest reads a DMA related register (like LPIB) and just do 3-4 DMA
377 * timer periods, however we'll be postponing the DMA timer every time we
378 * return to ring-3 and signal the AIO, so in the end we'd probably not use
379 * the timer callback at all. (This is assuming a small shared per-stream
380 * buffer for keeping the DMA data in and that it's size will force a return
381 * to ring-3 often enough to keep the AIO thread going at a reasonable rate.)
382 */
383 Assert(cbCur == cbTotal);
384
385 /* Match the BDLEs 1:1 if there are 3 or more and that the smallest one
386 is at least 5ms big. */
387 if (cSegments >= 3 && PDMAudioPropsBytesToMilli(pGuestProps, cbMin) >= 5 /*ms*/)
388 {
389 for (uint32_t i = 0; i < cSegments; i++)
390 {
391 rc = hdaR3StreamAddScheduleItem(pStreamShared, pStreamShared->State.aBdl[i].cb, cbMaxPeriod,
392 i, pHostProps, pGuestProps, &cbBorrow);
393 ASSERT_GUEST_RC_RETURN(rc, rc);
394 }
395 }
396 /* Otherwise, just divide the work into 3 or 4 portions and hope for the best.
397 It seems, though, that this only really work for windows vista if we avoid
398 working accross buffer lines. */
399 /** @todo This can be simplified/relaxed/uncluttered if we do DMA work when LPIB
400 * is read, assuming ofc that LPIB is read before each buffer update. */
401 else
402 {
403 uint32_t const cPeriods = cSegments != 3 && PDMAudioPropsBytesToMilli(pGuestProps, cbCur) >= 4 * 5 /*ms*/
404 ? 4 : cSegments != 2 ? 3 : 2;
405 uint32_t const cbPeriod = PDMAudioPropsFloorBytesToFrame(pGuestProps, cbCur / cPeriods);
406 uint32_t iBdle = 0;
407 uint32_t offBdle = 0;
408 for (uint32_t iPeriod = 0; iPeriod < cPeriods; iPeriod++)
409 {
410 if (iPeriod + 1 < cPeriods)
411 {
412 offBdle += cbPeriod;
413 while (iBdle < cSegments && offBdle >= pStreamShared->State.aBdl[iBdle].cb)
414 offBdle -= pStreamShared->State.aBdl[iBdle++].cb;
415 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbPeriod, cbMaxPeriod, offBdle != 0 ? iBdle : iBdle - 1,
416 pHostProps, pGuestProps, &cbBorrow);
417 }
418 else
419 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur - iPeriod * cbPeriod, cbMaxPeriod, cSegments - 1,
420 pHostProps, pGuestProps, &cbBorrow);
421 ASSERT_GUEST_RC_RETURN(rc, rc);
422 }
423
424 }
425 Assert(cbBorrow == 0);
426 }
427 else if (cbCur)
428 {
429 /* The last BDLE didn't have IOC set, so we must continue processing
430 from the start till we hit one that has. */
431 uint32_t i;
432 for (i = 0; i < cSegments; i++)
433 {
434 cbCur += pStreamShared->State.aBdl[i].cb;
435 if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
436 break;
437 }
438 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur, cbMaxPeriod, i, pHostProps, pGuestProps, &cbBorrow);
439 ASSERT_GUEST_RC_RETURN(rc, rc);
440
441 /* The initial scheduling items covering the wrap around area are
442 considered a prologue and must not repeated later. */
443 Assert(cPotentialPrologue);
444 pStreamShared->State.cSchedulePrologue = (uint8_t)cPotentialPrologue;
445 }
446
447 /*
448 * If there is just one BDLE with IOC set, we have to make sure
449 * we've got at least two periods scheduled, otherwise there is
450 * a very good chance the guest will overwrite the start of the
451 * buffer before we ever get around to reading it.
452 */
453 if (cBufferIrqs == 1)
454 {
455 uint32_t i = pStreamShared->State.cSchedulePrologue;
456 Assert(i < pStreamShared->State.cSchedule);
457 if ( i + 1 == pStreamShared->State.cSchedule
458 && pStreamShared->State.aSchedule[i].cLoops == 1)
459 {
460 uint32_t const cbFirstHalf = PDMAudioPropsFloorBytesToFrame(pHostProps, pStreamShared->State.aSchedule[i].cbPeriod / 2);
461 uint32_t const cbOtherHalf = pStreamShared->State.aSchedule[i].cbPeriod - cbFirstHalf;
462 pStreamShared->State.aSchedule[i].cbPeriod = cbFirstHalf;
463 if (cbFirstHalf == cbOtherHalf)
464 pStreamShared->State.aSchedule[i].cLoops = 2;
465 else
466 {
467 pStreamShared->State.aSchedule[i + 1] = pStreamShared->State.aSchedule[i];
468 pStreamShared->State.aSchedule[i].cbPeriod = cbOtherHalf;
469 pStreamShared->State.cSchedule++;
470 }
471 }
472 }
473
474 /*
475 * Go over the schduling entries and calculate the timer ticks for each period.
476 */
477 LogRel2(("HDA: Stream #%u schedule: %u items, %u prologue\n",
478 pStreamShared->u8SD, pStreamShared->State.cSchedule, pStreamShared->State.cSchedulePrologue));
479 uint64_t const cbHostPerSec = PDMAudioPropsFramesToBytes(pHostProps, pHostProps->uHz);
480 for (uint32_t i = 0; i < pStreamShared->State.cSchedule; i++)
481 {
482 uint64_t const cTicks = ASMMultU64ByU32DivByU32(cTimerTicksPerSec, pStreamShared->State.aSchedule[i].cbPeriod,
483 cbHostPerSec);
484 AssertLogRelMsgReturn((uint32_t)cTicks == cTicks, ("cTicks=%RU64 (%#RX64)\n", cTicks, cTicks), VERR_INTERNAL_ERROR_4);
485 pStreamShared->State.aSchedule[i].cPeriodTicks = RT_MAX((uint32_t)cTicks, 16);
486 LogRel2(("HDA: #%u: %u ticks / %u bytes, %u loops, BDLE%u L %u\n", i, pStreamShared->State.aSchedule[i].cPeriodTicks,
487 pStreamShared->State.aSchedule[i].cbPeriod, pStreamShared->State.aSchedule[i].cLoops,
488 pStreamShared->State.aSchedule[i].idxFirst, pStreamShared->State.aSchedule[i].cEntries));
489 }
490
491 return VINF_SUCCESS;
492}
493
494
495/**
496 * Sets up ((re-)iniitalizes) an HDA stream.
497 *
498 * @returns VBox status code. VINF_NO_CHANGE if the stream does not need
499 * be set-up again because the stream's (hardware) parameters did
500 * not change.
501 * @param pDevIns The device instance.
502 * @param pThis The shared HDA device state (for HW register
503 * parameters).
504 * @param pStreamShared HDA stream to set up, shared portion.
505 * @param pStreamR3 HDA stream to set up, ring-3 portion.
506 * @param uSD Stream descriptor number to assign it.
507 */
508int hdaR3StreamSetUp(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD)
509{
510 /* This must be valid all times. */
511 AssertReturn(uSD < HDA_MAX_STREAMS, VERR_INVALID_PARAMETER);
512
513 /* These member can only change on data corruption, despite what the code does further down (bird). */
514 AssertReturn(pStreamShared->u8SD == uSD, VERR_WRONG_ORDER);
515 AssertReturn(pStreamR3->u8SD == uSD, VERR_WRONG_ORDER);
516
517 const uint64_t u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, uSD),
518 HDA_STREAM_REG(pThis, BDPU, uSD));
519 const uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, uSD);
520 const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, uSD);
521 const uint8_t u8FIFOS = HDA_STREAM_REG(pThis, FIFOS, uSD) + 1;
522 uint8_t u8FIFOW = hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, uSD));
523 const uint16_t u16FMT = HDA_STREAM_REG(pThis, FMT, uSD);
524
525 /* Is the bare minimum set of registers configured for the stream?
526 * If not, bail out early, as there's nothing to do here for us (yet). */
527 if ( !u64BDLBase
528 || !u16LVI
529 || !u32CBL
530 || !u8FIFOS
531 || !u8FIFOW
532 || !u16FMT)
533 {
534 LogFunc(("[SD%RU8] Registers not set up yet, skipping (re-)initialization\n", uSD));
535 return VINF_SUCCESS;
536 }
537
538 /*
539 * Convert the config to PDM PCM properties and configure the stream.
540 */
541 PPDMAUDIOSTREAMCFG pCfg = &pStreamShared->State.Cfg;
542 int rc = hdaR3SDFMTToPCMProps(u16FMT, &pCfg->Props);
543 if (RT_SUCCESS(rc))
544 pCfg->enmDir = hdaGetDirFromSD(uSD);
545 else
546 {
547 LogRelMax(32, ("HDA: Warning: Format 0x%x for stream #%RU8 not supported\n", HDA_STREAM_REG(pThis, FMT, uSD), uSD));
548 return rc;
549 }
550
551 ASSERT_GUEST_LOGREL_MSG_RETURN( PDMAudioPropsFrameSize(&pCfg->Props) > 0
552 && u32CBL % PDMAudioPropsFrameSize(&pCfg->Props) == 0,
553 ("CBL for stream #%RU8 does not align to frame size (u32CBL=%u cbFrameSize=%u)\n",
554 uSD, u32CBL, PDMAudioPropsFrameSize(&pCfg->Props)),
555 VERR_INVALID_PARAMETER);
556
557 /* Make sure the guest behaves regarding the stream's FIFO. */
558 ASSERT_GUEST_LOGREL_MSG_STMT(u8FIFOW <= u8FIFOS,
559 ("Guest tried setting a bigger FIFOW (%RU8) than FIFOS (%RU8), limiting\n", u8FIFOW, u8FIFOS),
560 u8FIFOW = u8FIFOS /* ASSUMES that u8FIFOS has been validated. */);
561
562 pStreamShared->u8SD = uSD;
563
564 /* Update all register copies so that we later know that something has changed. */
565 pStreamShared->u64BDLBase = u64BDLBase;
566 pStreamShared->u16LVI = u16LVI;
567 pStreamShared->u32CBL = u32CBL;
568 pStreamShared->u8FIFOS = u8FIFOS;
569 pStreamShared->u8FIFOW = u8FIFOW;
570 pStreamShared->u16FMT = u16FMT;
571
572 /* The the stream's name, based on the direction. */
573 switch (pCfg->enmDir)
574 {
575 case PDMAUDIODIR_IN:
576# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
577# error "Implement me!"
578# else
579 pCfg->enmPath = PDMAUDIOPATH_IN_LINE;
580 RTStrCopy(pCfg->szName, sizeof(pCfg->szName), "Line In");
581# endif
582 break;
583
584 case PDMAUDIODIR_OUT:
585 /* Destination(s) will be set in hdaR3AddStreamOut(),
586 * based on the channels / stream layout. */
587 break;
588
589 default:
590 AssertFailedReturn(VERR_NOT_SUPPORTED);
591 break;
592 }
593
594 LogRel2(("HDA: Stream #%RU8 DMA @ 0x%x (%RU32 bytes = %RU64ms total)\n", uSD, pStreamShared->u64BDLBase,
595 pStreamShared->u32CBL, PDMAudioPropsBytesToMilli(&pCfg->Props, pStreamShared->u32CBL)));
596
597 /*
598 * Load the buffer descriptor list.
599 *
600 * Section 3.6.2 states that "the BDL should not be modified unless the RUN
601 * bit is 0", so it should be within the specs to read it once here and not
602 * re-read any BDLEs later.
603 */
604 /* Reset BDL state. */
605 RT_ZERO(pStreamShared->State.aBdl);
606 pStreamShared->State.offCurBdle = 0;
607 pStreamShared->State.idxCurBdle = 0;
608
609 uint32_t /*const*/ cTransferFragments = (pStreamShared->u16LVI & 0xff) + 1;
610 if (cTransferFragments <= 1)
611 LogRel(("HDA: Warning: Stream #%RU8 transfer buffer count invalid: (%RU16)! Buggy guest audio driver!\n", uSD, pStreamShared->u16LVI));
612 AssertLogRelReturn(cTransferFragments <= RT_ELEMENTS(pStreamShared->State.aBdl), VERR_INTERNAL_ERROR_5);
613 pStreamShared->State.cBdles = cTransferFragments;
614
615 /* Load them. */
616 rc = PDMDevHlpPCIPhysRead(pDevIns, u64BDLBase, pStreamShared->State.aBdl,
617 sizeof(pStreamShared->State.aBdl[0]) * cTransferFragments);
618 AssertRC(rc);
619
620 /* Check what we just loaded. Refuse overly large buffer lists. */
621 uint64_t cbTotal = 0;
622 uint32_t cBufferIrqs = 0;
623 for (uint32_t i = 0; i < cTransferFragments; i++)
624 {
625 if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
626 cBufferIrqs++;
627 cbTotal += pStreamShared->State.aBdl[i].cb;
628 }
629 ASSERT_GUEST_STMT_RETURN(cbTotal < _2G,
630 LogRelMax(32, ("HDA: Error: Stream #%u is configured with an insane amount of buffer space - refusing do work with it: %RU64 (%#RX64) bytes.\n",
631 uSD, cbTotal, cbTotal)),
632 VERR_NOT_SUPPORTED);
633 ASSERT_GUEST_STMT_RETURN(cbTotal == u32CBL,
634 LogRelMax(32, ("HDA: Warning: Stream #%u has a mismatch between CBL and configured buffer space: %RU32 (%#RX32) vs %RU64 (%#RX64)\n",
635 uSD, u32CBL, u32CBL, cbTotal, cbTotal)),
636 VERR_NOT_SUPPORTED);
637
638 /*
639 * Create a DMA timer schedule.
640 */
641 /** @todo clean up this, pGuestProps and pHostProps are the same now. */
642 rc = hdaR3StreamCreateSchedule(pStreamShared, cTransferFragments, cBufferIrqs, (uint32_t)cbTotal,
643 PDMAudioPropsMilliToBytes(&pCfg->Props, 100 /** @todo make configurable */),
644 PDMDevHlpTimerGetFreq(pDevIns, pStreamShared->hTimer),
645 &pCfg->Props, &pCfg->Props);
646 if (RT_FAILURE(rc))
647 return rc;
648
649 pStreamShared->State.cbTransferSize = pStreamShared->State.aSchedule[0].cbPeriod;
650
651 /*
652 * Calculate the transfer Hz for use in the circular buffer calculation.
653 */
654 uint32_t cbMaxPeriod = 0;
655 uint32_t cbMinPeriod = UINT32_MAX;
656 uint32_t cPeriods = 0;
657 for (uint32_t i = 0; i < pStreamShared->State.cSchedule; i++)
658 {
659 uint32_t cbPeriod = pStreamShared->State.aSchedule[i].cbPeriod;
660 cbMaxPeriod = RT_MAX(cbMaxPeriod, cbPeriod);
661 cbMinPeriod = RT_MIN(cbMinPeriod, cbPeriod);
662 cPeriods += pStreamShared->State.aSchedule[i].cLoops;
663 }
664 uint64_t const cbTransferPerSec = RT_MAX(PDMAudioPropsFramesToBytes(&pCfg->Props, pCfg->Props.uHz),
665 4096 /* zero div prevention: min is 6kHz, picked 4k in case I'm mistaken */);
666 unsigned uTransferHz = cbTransferPerSec * 1000 / cbMaxPeriod;
667 LogRel2(("HDA: Stream #%RU8 needs a %u.%03u Hz timer rate (period: %u..%u host bytes)\n",
668 uSD, uTransferHz / 1000, uTransferHz % 1000, cbMinPeriod, cbMaxPeriod));
669 uTransferHz /= 1000;
670
671 if (uTransferHz > 400) /* Anything above 400 Hz looks fishy -- tell the user. */
672 LogRelMax(32, ("HDA: Warning: Calculated transfer Hz rate for stream #%RU8 looks incorrect (%u), please re-run with audio debug mode and report a bug\n",
673 uSD, uTransferHz));
674
675 pStreamShared->State.cbAvgTransfer = (uint32_t)(cbTotal + cPeriods - 1) / cPeriods;
676
677 /* For input streams we must determin a pre-buffering requirement.
678 We use the initial delay as a basis here, though we must have at
679 least two max periods worth of data queued up due to the way we
680 work the AIO thread. */
681 pStreamShared->State.fInputPreBuffered = false;
682 pStreamShared->State.cbInputPreBuffer = PDMAudioPropsMilliToBytes(&pCfg->Props, pThis->msInitialDelay);
683 pStreamShared->State.cbInputPreBuffer = RT_MIN(cbMaxPeriod * 2, pStreamShared->State.cbInputPreBuffer);
684
685 /*
686 * Set up data transfer stuff.
687 */
688
689 /* Assign the global device rate to the stream I/O timer as default. */
690 pStreamShared->State.uTimerIoHz = pThis->uTimerHz;
691 ASSERT_GUEST_LOGREL_MSG_STMT(pStreamShared->State.uTimerIoHz,
692 ("I/O timer Hz rate for stream #%RU8 is invalid\n", uSD),
693 pStreamShared->State.uTimerIoHz = HDA_TIMER_HZ_DEFAULT);
694
695 /* Set I/O scheduling hint for the backends. */
696 /** @todo r=bird: derive this from the schedule instead of using the
697 * uTimerIoHz, as that's almost pure non-sense now. */
698 pCfg->Device.cMsSchedulingHint = RT_MS_1SEC / pStreamShared->State.uTimerIoHz;
699 LogRel2(("HDA: Stream #%RU8 set scheduling hint for the backends to %RU32ms\n", uSD, pCfg->Device.cMsSchedulingHint));
700
701
702 /* Make sure to also update the stream's DMA counter (based on its current LPIB value). */
703 /** @todo r=bird: We use LPIB as-is here, so if it's not zero we have to
704 * locate the right place in the schedule and whatnot... */
705 if (HDA_STREAM_REG(pThis, LPIB, uSD) != 0)
706 LogRel2(("HDA: Warning! Stream #%RU8 is set up with LPIB=%#RX32 instead of zero!\n", uSD, HDA_STREAM_REG(pThis, LPIB, uSD)));
707 hdaStreamSetPositionAbs(pStreamShared, pDevIns, pThis, HDA_STREAM_REG(pThis, LPIB, uSD));
708
709# ifdef LOG_ENABLED
710 hdaR3BDLEDumpAll(pDevIns, pThis, pStreamShared->u64BDLBase, pStreamShared->u16LVI + 1);
711# endif
712
713 /*
714 * Set up internal ring buffer.
715 */
716
717 /* (Re-)Allocate the stream's internal DMA buffer,
718 * based on the timing *and* PCM properties we just got above. */
719 if (pStreamR3->State.pCircBuf)
720 {
721 RTCircBufDestroy(pStreamR3->State.pCircBuf);
722 pStreamR3->State.pCircBuf = NULL;
723 pStreamR3->State.StatDmaBufSize = 0;
724 pStreamR3->State.StatDmaBufUsed = 0;
725 }
726 pStreamShared->State.offWrite = 0;
727 pStreamShared->State.offRead = 0;
728
729 /*
730 * The default internal ring buffer size must be:
731 *
732 * - Large enough for at least three periodic DMA transfers.
733 *
734 * It is critically important that we don't experience underruns
735 * in the DMA OUT code, because it will cause the buffer processing
736 * to get skewed and possibly overlap with what the guest is updating.
737 * At the time of writing (2021-03-05) there is no code for getting
738 * back into sync there.
739 *
740 * - Large enough for at least three I/O scheduling hints.
741 *
742 * We want to lag behind a DMA period or two, but there must be
743 * sufficent space for the AIO thread to get schedule and shuffle
744 * data thru the mixer and onto the host audio hardware.
745 *
746 * - Both above with plenty to spare.
747 *
748 * So, just take the longest of the two periods and multipling it by 6.
749 * We aren't not talking about very large base buffers heres, so size isn't
750 * an issue.
751 *
752 * Note: Use pCfg->Props as PCM properties here, as we only want to store the
753 * samples we actually need, in other words, skipping the interleaved
754 * channels we don't support / need to save space.
755 */
756 uint32_t msCircBuf = RT_MS_1SEC * 6 / RT_MIN(uTransferHz, pStreamShared->State.uTimerIoHz);
757 msCircBuf = RT_MAX(msCircBuf, pThis->msInitialDelay + RT_MS_1SEC * 6 / uTransferHz);
758
759 uint32_t cbCircBuf = PDMAudioPropsMilliToBytes(&pCfg->Props, msCircBuf);
760 LogRel2(("HDA: Stream #%RU8 default ring buffer size is %RU32 bytes / %RU64 ms\n",
761 uSD, cbCircBuf, PDMAudioPropsBytesToMilli(&pCfg->Props, cbCircBuf)));
762
763 uint32_t msCircBufCfg = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? pThis->cMsCircBufIn : pThis->cMsCircBufOut;
764 if (msCircBufCfg) /* Anything set via CFGM? */
765 {
766 cbCircBuf = PDMAudioPropsMilliToBytes(&pCfg->Props, msCircBufCfg);
767 LogRel2(("HDA: Stream #%RU8 is using a custom ring buffer size of %RU32 bytes / %RU64 ms\n",
768 uSD, cbCircBuf, PDMAudioPropsBytesToMilli(&pCfg->Props, cbCircBuf)));
769 }
770
771 /* Serious paranoia: */
772 ASSERT_GUEST_LOGREL_MSG_STMT(cbCircBuf % PDMAudioPropsFrameSize(&pCfg->Props) == 0,
773 ("Ring buffer size (%RU32) for stream #%RU8 not aligned to the (host) frame size (%RU8)\n",
774 cbCircBuf, uSD, PDMAudioPropsFrameSize(&pCfg->Props)),
775 rc = VERR_INVALID_PARAMETER);
776 ASSERT_GUEST_LOGREL_MSG_STMT(cbCircBuf, ("Ring buffer size for stream #%RU8 is invalid\n", uSD),
777 rc = VERR_INVALID_PARAMETER);
778 if (RT_SUCCESS(rc))
779 {
780 rc = RTCircBufCreate(&pStreamR3->State.pCircBuf, cbCircBuf);
781 if (RT_SUCCESS(rc))
782 {
783 pStreamR3->State.StatDmaBufSize = cbCircBuf;
784
785 /*
786 * Forward the timer frequency hint to TM as well for better accuracy on
787 * systems w/o preemption timers (also good for 'info timers').
788 */
789 PDMDevHlpTimerSetFrequencyHint(pDevIns, pStreamShared->hTimer, uTransferHz);
790 }
791 }
792
793 if (RT_FAILURE(rc))
794 LogRelMax(32, ("HDA: Initializing stream #%RU8 failed with %Rrc\n", uSD, rc));
795
796# ifdef VBOX_WITH_DTRACE
797 VBOXDD_HDA_STREAM_SETUP((uint32_t)uSD, rc, pStreamShared->State.Cfg.Props.uHz,
798 pStreamShared->State.aSchedule[pStreamShared->State.cSchedule - 1].cPeriodTicks,
799 pStreamShared->State.aSchedule[pStreamShared->State.cSchedule - 1].cbPeriod);
800# endif
801 return rc;
802}
803
804/**
805 * Resets an HDA stream.
806 *
807 * @param pThis The shared HDA device state.
808 * @param pThisCC The ring-3 HDA device state.
809 * @param pStreamShared HDA stream to reset (shared).
810 * @param pStreamR3 HDA stream to reset (ring-3).
811 * @param uSD Stream descriptor (SD) number to use for this stream.
812 */
813void hdaR3StreamReset(PHDASTATE pThis, PHDASTATER3 pThisCC, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD)
814{
815 LogFunc(("[SD%RU8] Reset\n", uSD));
816
817 /*
818 * Assert some sanity.
819 */
820 AssertPtr(pThis);
821 AssertPtr(pStreamShared);
822 AssertPtr(pStreamR3);
823 Assert(uSD < HDA_MAX_STREAMS);
824 Assert(pStreamShared->u8SD == uSD);
825 Assert(pStreamR3->u8SD == uSD);
826 AssertMsg(!pStreamShared->State.fRunning, ("[SD%RU8] Cannot reset stream while in running state\n", uSD));
827
828 /*
829 * Set reset state.
830 */
831 Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false); /* No nested calls. */
832 ASMAtomicXchgBool(&pStreamShared->State.fInReset, true);
833
834 /*
835 * Second, initialize the registers.
836 */
837 /* See 6.2.33: Clear on reset. */
838 HDA_STREAM_REG(pThis, STS, uSD) = 0;
839 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
840 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
841 HDA_STREAM_REG(pThis, CTL, uSD) = HDA_SDCTL_TP | (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_SDCTL_SRST);
842 /* ICH6 defines default values (120 bytes for input and 192 bytes for output descriptors) of FIFO size. 18.2.39. */
843 HDA_STREAM_REG(pThis, FIFOS, uSD) = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? HDA_SDIFIFO_120B : HDA_SDOFIFO_192B;
844 /* See 18.2.38: Always defaults to 0x4 (32 bytes). */
845 HDA_STREAM_REG(pThis, FIFOW, uSD) = HDA_SDFIFOW_32B;
846 HDA_STREAM_REG(pThis, LPIB, uSD) = 0;
847 HDA_STREAM_REG(pThis, CBL, uSD) = 0;
848 HDA_STREAM_REG(pThis, LVI, uSD) = 0;
849 HDA_STREAM_REG(pThis, FMT, uSD) = 0;
850 HDA_STREAM_REG(pThis, BDPU, uSD) = 0;
851 HDA_STREAM_REG(pThis, BDPL, uSD) = 0;
852
853# ifdef HDA_USE_DMA_ACCESS_HANDLER
854 hdaR3StreamUnregisterDMAHandlers(pThis, pStream);
855# endif
856
857 /* Assign the default mixer sink to the stream. */
858 pStreamR3->pMixSink = hdaR3GetDefaultSink(pThisCC, uSD);
859 if (pStreamR3->State.pAioRegSink)
860 {
861 int rc2 = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
862 AssertRC(rc2);
863 pStreamR3->State.pAioRegSink = NULL;
864 }
865
866 /* Reset transfer stuff. */
867 pStreamShared->State.cTransferPendingInterrupts = 0;
868 pStreamShared->State.tsTransferLast = 0;
869 pStreamShared->State.tsTransferNext = 0;
870
871 /* Initialize timestamps. */
872 pStreamShared->State.tsLastTransferNs = 0;
873 pStreamShared->State.tsLastReadNs = 0;
874 pStreamShared->State.tsAioDelayEnd = UINT64_MAX;
875 pStreamShared->State.tsStart = 0;
876
877 RT_ZERO(pStreamShared->State.aBdl);
878 RT_ZERO(pStreamShared->State.aSchedule);
879 pStreamShared->State.offCurBdle = 0;
880 pStreamShared->State.cBdles = 0;
881 pStreamShared->State.idxCurBdle = 0;
882 pStreamShared->State.cSchedulePrologue = 0;
883 pStreamShared->State.cSchedule = 0;
884 pStreamShared->State.idxSchedule = 0;
885 pStreamShared->State.idxScheduleLoop = 0;
886 pStreamShared->State.fInputPreBuffered = false;
887
888 if (pStreamR3->State.pCircBuf)
889 RTCircBufReset(pStreamR3->State.pCircBuf);
890 pStreamShared->State.offWrite = 0;
891 pStreamShared->State.offRead = 0;
892
893# ifdef DEBUG
894 pStreamR3->Dbg.cReadsTotal = 0;
895 pStreamR3->Dbg.cbReadTotal = 0;
896 pStreamR3->Dbg.tsLastReadNs = 0;
897 pStreamR3->Dbg.cWritesTotal = 0;
898 pStreamR3->Dbg.cbWrittenTotal = 0;
899 pStreamR3->Dbg.cWritesHz = 0;
900 pStreamR3->Dbg.cbWrittenHz = 0;
901 pStreamR3->Dbg.tsWriteSlotBegin = 0;
902# endif
903
904 /* Report that we're done resetting this stream. */
905 HDA_STREAM_REG(pThis, CTL, uSD) = 0;
906
907# ifdef VBOX_WITH_DTRACE
908 VBOXDD_HDA_STREAM_RESET((uint32_t)uSD);
909# endif
910 LogFunc(("[SD%RU8] Reset\n", uSD));
911
912 /* Exit reset mode. */
913 ASMAtomicXchgBool(&pStreamShared->State.fInReset, false);
914}
915
916/**
917 * Enables or disables an HDA audio stream.
918 *
919 * @returns VBox status code.
920 * @param pThis The shared HDA device state.
921 * @param pStreamShared HDA stream to enable or disable - shared bits.
922 * @param pStreamR3 HDA stream to enable or disable - ring-3 bits.
923 * @param fEnable Whether to enable or disble the stream.
924 */
925int hdaR3StreamEnable(PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, bool fEnable)
926{
927 AssertPtr(pStreamR3);
928 AssertPtr(pStreamShared);
929
930 LogFunc(("[SD%RU8] fEnable=%RTbool, pMixSink=%p\n", pStreamShared->u8SD, fEnable, pStreamR3->pMixSink));
931
932 /* First, enable or disable the stream and the stream's sink, if any. */
933 int rc = VINF_SUCCESS;
934 PAUDMIXSINK const pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
935 if (pSink)
936 {
937 if (fEnable)
938 {
939 if (pStreamR3->State.pAioRegSink != pSink)
940 {
941 if (pStreamR3->State.pAioRegSink)
942 {
943 rc = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
944 AssertRC(rc);
945 }
946 rc = AudioMixerSinkAddUpdateJob(pSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3,
947 pStreamShared->State.Cfg.Device.cMsSchedulingHint);
948 AssertLogRelRC(rc);
949 pStreamR3->State.pAioRegSink = RT_SUCCESS(rc) ? pSink : NULL;
950 }
951 rc = AudioMixerSinkStart(pSink);
952 }
953 else
954 rc = AudioMixerSinkDrainAndStop(pSink,
955 pStreamR3->State.pCircBuf ? (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf) : 0);
956 }
957 if ( RT_SUCCESS(rc)
958 && fEnable
959 && pStreamR3->Dbg.Runtime.fEnabled)
960 {
961 Assert(AudioHlpPcmPropsAreValid(&pStreamShared->State.Cfg.Props));
962
963 if (fEnable)
964 {
965 if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileStream))
966 {
967 int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileStream, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
968 &pStreamShared->State.Cfg.Props);
969 AssertRC(rc2);
970 }
971
972 if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileDMARaw))
973 {
974 int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileDMARaw, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
975 &pStreamShared->State.Cfg.Props);
976 AssertRC(rc2);
977 }
978
979 if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileDMAMapped))
980 {
981 int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileDMAMapped, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
982 &pStreamShared->State.Cfg.Props);
983 AssertRC(rc2);
984 }
985 }
986 }
987
988 if (RT_SUCCESS(rc))
989 {
990 if (fEnable)
991 pStreamShared->State.tsTransferLast = 0; /* Make sure it's not stale and messes up WALCLK calculations. */
992 pStreamShared->State.fRunning = fEnable;
993
994 /*
995 * Set the FIFORDY bit when we start running and clear it when stopping.
996 *
997 * This prevents Linux from timing out in snd_hdac_stream_sync when starting
998 * a stream. Technically, Linux also uses the SSYNC feature there, but we
999 * can get away with just setting the FIFORDY bit for now.
1000 */
1001 if (fEnable)
1002 HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) |= HDA_SDSTS_FIFORDY;
1003 else
1004 HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) &= ~HDA_SDSTS_FIFORDY;
1005 }
1006
1007 LogFunc(("[SD%RU8] rc=%Rrc\n", pStreamShared->u8SD, rc));
1008 return rc;
1009}
1010
1011/**
1012 * Marks the stream as started.
1013 *
1014 * Used after the stream has been enabled and the DMA timer has been armed.
1015 */
1016void hdaR3StreamMarkStarted(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint64_t tsNow)
1017{
1018 pStreamShared->State.tsLastReadNs = RTTimeNanoTS();
1019 pStreamShared->State.tsStart = tsNow;
1020 pStreamShared->State.tsAioDelayEnd = tsNow + PDMDevHlpTimerFromMilli(pDevIns, pStreamShared->hTimer, pThis->msInitialDelay);
1021 Log3Func(("#%u: tsStart=%RU64 tsAioDelayEnd=%RU64 tsLastReadNs=%RU64\n", pStreamShared->u8SD,
1022 pStreamShared->State.tsStart, pStreamShared->State.tsAioDelayEnd, pStreamShared->State.tsLastReadNs));
1023
1024}
1025
1026/**
1027 * Marks the stream as stopped.
1028 */
1029void hdaR3StreamMarkStopped(PHDASTREAM pStreamShared)
1030{
1031 Log3Func(("#%u\n", pStreamShared->u8SD));
1032 pStreamShared->State.tsAioDelayEnd = UINT64_MAX;
1033}
1034
1035#endif /* IN_RING3 */
1036
1037/**
1038 * Updates an HDA stream's current read or write buffer position (depending on the stream type) by
1039 * setting its associated LPIB register and DMA position buffer (if enabled) to an absolute value.
1040 *
1041 * @param pStreamShared HDA stream to update read / write position for (shared).
1042 * @param pDevIns The device instance.
1043 * @param pThis The shared HDA device state.
1044 * @param uLPIB Absolute position (in bytes) to set current read / write position to.
1045 */
1046static void hdaStreamSetPositionAbs(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uLPIB)
1047{
1048 AssertPtrReturnVoid(pStreamShared);
1049 AssertMsgStmt(uLPIB <= pStreamShared->u32CBL, ("%#x\n", uLPIB), uLPIB = pStreamShared->u32CBL);
1050
1051 Log3Func(("[SD%RU8] LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n", pStreamShared->u8SD, uLPIB, pThis->fDMAPosition));
1052
1053 /* Update LPIB in any case. */
1054 HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) = uLPIB;
1055
1056 /* Do we need to tell the current DMA position? */
1057 if (pThis->fDMAPosition)
1058 {
1059 /*
1060 * Linux switched to using the position buffers some time during 2.6.x.
1061 * 2.6.12 used LPIB, 2.6.17 defaulted to DMA position buffers, between
1062 * the two version things were being changing quite a bit.
1063 *
1064 * Since 2.6.17, they will treat a zero DMA position value during the first
1065 * period/IRQ as reason to fall back to LPIB mode (see azx_position_ok in
1066 * 2.6.27+, and azx_pcm_pointer before that). They later also added
1067 * UINT32_MAX to the values causing same.
1068 *
1069 * Since 2.6.35 azx_position_ok will read the wall clock register before
1070 * determining the position.
1071 */
1072 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns,
1073 pThis->u64DPBase + (pStreamShared->u8SD * 2 * sizeof(uint32_t)),
1074 (void *)&uLPIB, sizeof(uint32_t));
1075 AssertRC(rc2);
1076 }
1077}
1078
1079/**
1080 * Updates an HDA stream's current read or write buffer position (depending on the stream type) by
1081 * adding a value to its associated LPIB register and DMA position buffer (if enabled).
1082 *
1083 * @note Handles automatic CBL wrap-around.
1084 *
1085 * @param pStreamShared HDA stream to update read / write position for (shared).
1086 * @param pDevIns The device instance.
1087 * @param pThis The shared HDA device state.
1088 * @param cbToAdd Position (in bytes) to add to the current read / write position.
1089 */
1090static void hdaStreamSetPositionAdd(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t cbToAdd)
1091{
1092 if (cbToAdd) /* No need to update anything if 0. */
1093 {
1094 uint32_t const uCBL = pStreamShared->u32CBL;
1095 if (uCBL) /* paranoia */
1096 {
1097 uint32_t uNewLpid = HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) + cbToAdd;
1098#if 1 /** @todo r=bird: this is wrong according to the spec */
1099 uNewLpid %= uCBL;
1100#else
1101 /* The spec says it goes to CBL then wraps arpimd to 1, not back to zero. See 3.3.37. */
1102 if (uNewLpid > uCBL)
1103 uNewLpid %= uCBL;
1104#endif
1105 hdaStreamSetPositionAbs(pStreamShared, pDevIns, pThis, uNewLpid);
1106 }
1107 }
1108}
1109
1110#ifdef IN_RING3
1111
1112/**
1113 * Retrieves the available size of (buffered) audio data (in bytes) of a given HDA stream.
1114 *
1115 * @returns Available data (in bytes).
1116 * @param pStreamR3 HDA stream to retrieve size for (ring-3).
1117 */
1118static uint32_t hdaR3StreamGetUsed(PHDASTREAMR3 pStreamR3)
1119{
1120 AssertPtrReturn(pStreamR3, 0);
1121
1122 if (pStreamR3->State.pCircBuf)
1123 return (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1124 return 0;
1125}
1126
1127/**
1128 * Retrieves the free size of audio data (in bytes) of a given HDA stream.
1129 *
1130 * @returns Free data (in bytes).
1131 * @param pStreamR3 HDA stream to retrieve size for (ring-3).
1132 */
1133static uint32_t hdaR3StreamGetFree(PHDASTREAMR3 pStreamR3)
1134{
1135 AssertPtrReturn(pStreamR3, 0);
1136
1137 if (pStreamR3->State.pCircBuf)
1138 return (uint32_t)RTCircBufFree(pStreamR3->State.pCircBuf);
1139 return 0;
1140}
1141
1142#endif /* IN_RING3 */
1143
1144/**
1145 * Get the current address and number of bytes left in the current BDLE.
1146 *
1147 * @returns The current physical address.
1148 * @param pStreamShared The stream to check.
1149 * @param pcbLeft The number of bytes left at the returned address.
1150 */
1151DECLINLINE(RTGCPHYS) hdaStreamDmaBufGet(PHDASTREAM pStreamShared, uint32_t *pcbLeft)
1152{
1153 uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1154 AssertStmt(idxBdle < pStreamShared->State.cBdles, idxBdle = 0);
1155
1156 uint32_t const cbCurBdl = pStreamShared->State.aBdl[idxBdle].cb;
1157 uint32_t offCurBdle = pStreamShared->State.offCurBdle;
1158 AssertStmt(pStreamShared->State.offCurBdle <= cbCurBdl, offCurBdle = cbCurBdl);
1159
1160 *pcbLeft = cbCurBdl - offCurBdle;
1161 return pStreamShared->State.aBdl[idxBdle].GCPhys + offCurBdle;
1162}
1163
1164/**
1165 * Get the size of the current BDLE.
1166 *
1167 * @returns The size (in bytes).
1168 * @param pStreamShared The stream to check.
1169 */
1170DECLINLINE(RTGCPHYS) hdaStreamDmaBufGetSize(PHDASTREAM pStreamShared)
1171{
1172 uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1173 AssertStmt(idxBdle < pStreamShared->State.cBdles, idxBdle = 0);
1174 return pStreamShared->State.aBdl[idxBdle].cb;
1175}
1176
1177/**
1178 * Checks if the current BDLE is completed.
1179 *
1180 * @retval true if complete
1181 * @retval false if not.
1182 * @param pStreamShared The stream to check.
1183 */
1184DECLINLINE(bool) hdaStreamDmaBufIsComplete(PHDASTREAM pStreamShared)
1185{
1186 uint8_t const idxBdle = pStreamShared->State.idxCurBdle;
1187 AssertReturn(idxBdle < pStreamShared->State.cBdles, true);
1188
1189 uint32_t const cbCurBdl = pStreamShared->State.aBdl[idxBdle].cb;
1190 uint32_t const offCurBdle = pStreamShared->State.offCurBdle;
1191 Assert(offCurBdle <= cbCurBdl);
1192 return offCurBdle >= cbCurBdl;
1193}
1194
1195/**
1196 * Checks if the current BDLE needs a completion IRQ.
1197 *
1198 * @retval true if IRQ is needed.
1199 * @retval false if not.
1200 * @param pStreamShared The stream to check.
1201 */
1202DECLINLINE(bool) hdaStreamDmaBufNeedsIrq(PHDASTREAM pStreamShared)
1203{
1204 uint8_t const idxBdle = pStreamShared->State.idxCurBdle;
1205 AssertReturn(idxBdle < pStreamShared->State.cBdles, false);
1206 return (pStreamShared->State.aBdl[idxBdle].fFlags & HDA_BDLE_F_IOC) != 0;
1207}
1208
1209/**
1210 * Advances the DMA engine to the next BDLE.
1211 *
1212 * @param pStreamShared The stream which DMA engine is to be updated.
1213 */
1214DECLINLINE(void) hdaStreamDmaBufAdvanceToNext(PHDASTREAM pStreamShared)
1215{
1216 uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1217 Assert(pStreamShared->State.offCurBdle == pStreamShared->State.aBdl[idxBdle].cb);
1218
1219 if (idxBdle < pStreamShared->State.cBdles - 1)
1220 idxBdle++;
1221 else
1222 idxBdle = 0;
1223 pStreamShared->State.idxCurBdle = idxBdle;
1224 pStreamShared->State.offCurBdle = 0;
1225}
1226
1227#ifdef IN_RING3
1228
1229/**
1230 * Common do-DMA prologue code.
1231 *
1232 * @retval true if DMA processing can take place
1233 * @retval false if caller should return immediately.
1234 * @param pThis The shared HDA device state.
1235 * @param pStreamShared HDA stream to update (shared).
1236 * @param pStreamR3 HDA stream to update (ring-3).
1237 * @param uSD The stream ID (for asserting).
1238 * @param tsNowNs The current RTTimeNano() value.
1239 * @param pszFunction The function name (for logging).
1240 */
1241DECLINLINE(bool) hdaR3StreamDoDmaPrologue(PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD,
1242 uint64_t tsNowNs, const char *pszFunction)
1243{
1244 RT_NOREF(uSD, pszFunction);
1245
1246 /*
1247 * Check if we should skip town...
1248 */
1249 /* Stream not running (anymore)? */
1250 if (pStreamShared->State.fRunning)
1251 { /* likely */ }
1252 else
1253 {
1254 Log3(("%s: [SD%RU8] Not running, skipping transfer\n", pszFunction, uSD));
1255 return false;
1256 }
1257
1258 if (!(HDA_STREAM_REG(pThis, STS, uSD) & HDA_SDSTS_BCIS))
1259 { /* likely */ }
1260 else
1261 {
1262 /** @todo r=bird: This is a bit fishy. We should make effort the reschedule
1263 * the transfer immediately after the guest clears the interrupt.
1264 * The same fishy code is present in AC'97 with just a little
1265 * explanation as here, see @bugref{9890#c95}.
1266 *
1267 * The reasoning is probably that the developer noticed some windows
1268 * versions don't like having their BCIS interrupts bundled. There were
1269 * comments to that effect elsewhere, probably as a result of a fixed
1270 * uTimerHz approach to DMA scheduling. However, pausing DMA for a
1271 * period isn't going to help us with the host backends, as they don't
1272 * pause and will want samples ASAP. So, we should at least unpause
1273 * DMA as quickly as we possible when BCIS is cleared. We might even
1274 * not skip it iff the DMA work here doesn't involve raising any IOC,
1275 * which is possible although unlikely. */
1276 Log3(("%s: [SD%RU8] BCIS bit set, skipping transfer\n", pszFunction, uSD));
1277 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaSkippedPendingBcis);
1278 Log(("%s: [SD%RU8] BCIS bit set, skipping transfer\n", pszFunction, uSD));
1279# ifdef HDA_STRICT
1280 /* Timing emulation bug or guest is misbehaving -- let me know. */
1281 AssertMsgFailed(("%s: BCIS bit for stream #%RU8 still set when it shouldn't\n", pszFunction, uSD));
1282# endif
1283 return false;
1284 }
1285
1286 /*
1287 * Stream sanity checks.
1288 */
1289 /* Register sanity checks. */
1290 Assert(uSD < HDA_MAX_STREAMS);
1291 Assert(pStreamShared->u64BDLBase);
1292 Assert(pStreamShared->u32CBL);
1293 Assert(pStreamShared->u8FIFOS);
1294
1295 /* State sanity checks. */
1296 Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false);
1297 Assert(ASMAtomicReadBool(&pStreamShared->State.fRunning));
1298
1299 /*
1300 * Some timestamp stuff for logging/debugging.
1301 */
1302 /*const uint64_t tsNowNs = RTTimeNanoTS();*/
1303 Log3(("%s: [SD%RU8] tsDeltaNs=%'RU64 ns\n", pszFunction, uSD, tsNowNs - pStreamShared->State.tsLastTransferNs));
1304 pStreamShared->State.tsLastTransferNs = tsNowNs;
1305
1306 return true;
1307}
1308
1309/**
1310 * Common do-DMA epilogue.
1311 *
1312 * @param pDevIns The device instance.
1313 * @param pStreamShared The HDA stream (shared).
1314 * @param pStreamR3 The HDA stream (ring-3).
1315 */
1316DECLINLINE(void) hdaR3StreamDoDmaEpilogue(PPDMDEVINS pDevIns, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
1317{
1318 /*
1319 * We must update this in the epilogue rather than in the prologue
1320 * as it is used for WALCLK calculation and we must make sure the
1321 * guest doesn't think we've processed the current period till we
1322 * actually have.
1323 */
1324 pStreamShared->State.tsTransferLast = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer);
1325
1326 /*
1327 * Update the buffer statistics.
1328 */
1329 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1330}
1331
1332#endif /* IN_RING3 */
1333
1334/**
1335 * Completes a BDLE at the end of a DMA loop iteration, if possible.
1336 *
1337 * @retval true if buffer completed and new loaded.
1338 * @retval false if buffer not completed.
1339 * @param pDevIns The device instance.
1340 * @param pThis The shared HDA device state.
1341 * @param pStreamShared HDA stream to update (shared).
1342 * @param pszFunction The function name (for logging).
1343 */
1344DECLINLINE(bool) hdaStreamDoDmaMaybeCompleteBuffer(PPDMDEVINS pDevIns, PHDASTATE pThis,
1345 PHDASTREAM pStreamShared, const char *pszFunction)
1346{
1347 RT_NOREF(pszFunction);
1348
1349 /*
1350 * Is the buffer descriptor complete.
1351 */
1352 if (hdaStreamDmaBufIsComplete(pStreamShared))
1353 {
1354 Log3(("%s: [SD%RU8] Completed BDLE%u %#RX64 LB %#RX32 fFlags=%#x\n", pszFunction, pStreamShared->u8SD,
1355 pStreamShared->State.idxCurBdle, pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].GCPhys,
1356 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].cb,
1357 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].fFlags));
1358
1359#if 0 /* Moved to the transfer loops */
1360 /*
1361 * Update the stream's current position.
1362 *
1363 * Do this as accurate and close to the actual data transfer as possible.
1364 * All guests rely on this, depending on the mechanism they use (LPIB register or DMA counters).
1365 *
1366 * Note for Windows 10: The OS' driver is *very* picky about *when* the (DMA) positions get updated!
1367 * Not doing this at the right time will result in ugly sound crackles!
1368 */
1369 hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, hdaStreamDmaBufGetSize(pStreamShared));
1370#endif
1371
1372 /* Does the current BDLE require an interrupt to be sent? */
1373 if (hdaStreamDmaBufNeedsIrq(pStreamShared))
1374 {
1375 /* If the IOCE ("Interrupt On Completion Enable") bit of the SDCTL
1376 register is set we need to generate an interrupt. */
1377 if (HDA_STREAM_REG(pThis, CTL, pStreamShared->u8SD) & HDA_SDCTL_IOCE)
1378 {
1379 /* Assert the interrupt before actually fetching the next BDLE below. */
1380 pStreamShared->State.cTransferPendingInterrupts = 1;
1381 Log3(("%s: [SD%RU8] Scheduling interrupt\n", pszFunction, pStreamShared->u8SD));
1382
1383 /* Trigger an interrupt first and let hdaRegWriteSDSTS() deal with
1384 * ending / beginning of a period. */
1385 /** @todo r=bird: What does the above comment mean? */
1386 HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) |= HDA_SDSTS_BCIS;
1387 HDA_PROCESS_INTERRUPT(pDevIns, pThis);
1388 }
1389 }
1390
1391 /*
1392 * Advance to the next BDLE.
1393 */
1394 hdaStreamDmaBufAdvanceToNext(pStreamShared);
1395 return true;
1396 }
1397
1398 Log3(("%s: [SD%RU8] Incomplete BDLE%u %#RX64 LB %#RX32 fFlags=%#x: off=%#RX32\n", pszFunction, pStreamShared->u8SD,
1399 pStreamShared->State.idxCurBdle, pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].GCPhys,
1400 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].cb,
1401 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].fFlags, pStreamShared->State.offCurBdle));
1402 return false;
1403}
1404
1405#ifdef IN_RING3
1406
1407/**
1408 * Does DMA transfer for an HDA input stream.
1409 *
1410 * Reads audio data from the HDA stream's internal DMA buffer and writing to
1411 * guest memory.
1412 *
1413 * @param pDevIns The device instance.
1414 * @param pThis The shared HDA device state.
1415 * @param pStreamShared HDA stream to update (shared).
1416 * @param pStreamR3 HDA stream to update (ring-3).
1417 * @param cbToConsume The max amount of data to consume from the
1418 * internal DMA buffer. The caller will make sure
1419 * this is always the transfer size fo the current
1420 * period (unless something is seriously wrong).
1421 * @param fWriteSilence Whether to feed the guest silence rather than
1422 * fetching bytes from the internal DMA buffer.
1423 * This is set initially while we pre-buffer a
1424 * little bit of input, so we can better handle
1425 * time catch-ups and other schduling fun.
1426 * @param tsNowNs The current RTTimeNano() value.
1427 *
1428 * @remarks Caller owns the stream lock.
1429 */
1430static void hdaR3StreamDoDmaInput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
1431 PHDASTREAMR3 pStreamR3, uint32_t const cbToConsume, bool fWriteSilence, uint64_t tsNowNs)
1432{
1433 uint8_t const uSD = pStreamShared->u8SD;
1434 LogFlowFunc(("ENTER - #%u cbToConsume=%#x%s\n", uSD, cbToConsume, fWriteSilence ? " silence" : ""));
1435
1436 /*
1437 * Common prologue.
1438 */
1439 if (hdaR3StreamDoDmaPrologue(pThis, pStreamShared, pStreamR3, uSD, tsNowNs, "hdaR3StreamDoDmaInput"))
1440 { /* likely */ }
1441 else
1442 return;
1443
1444 /*
1445 *
1446 * The DMA copy loop.
1447 *
1448 */
1449 uint8_t abBounce[4096 + 128]; /* Most guest does at most 4KB BDLE. So, 4KB + space for a partial frame to reduce loops. */
1450 uint32_t cbBounce = 0; /* in case of incomplete frames between buffer segments */
1451 PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1452 uint32_t cbLeft = cbToConsume;
1453 Assert(cbLeft == pStreamShared->State.cbTransferSize);
1454 Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1455
1456 while (cbLeft > 0)
1457 {
1458 STAM_PROFILE_START(&pThis->StatIn, a);
1459
1460 /*
1461 * Figure out how much we can read & write in this iteration.
1462 */
1463 uint32_t cbChunk = 0;
1464 RTGCPHYS GCPhys = hdaStreamDmaBufGet(pStreamShared, &cbChunk);
1465
1466 /* If we're writing silence. */
1467 uint32_t cbWritten = 0;
1468 if (!fWriteSilence)
1469 {
1470 if (cbChunk <= cbLeft)
1471 { /* very likely */ }
1472 else
1473 cbChunk = cbLeft;
1474
1475 /*
1476 * Write the host data directly into the guest buffers.
1477 */
1478 while (cbChunk > 0)
1479 {
1480 /* Grab internal DMA buffer space and read into it. */
1481 void /*const*/ *pvBufSrc;
1482 size_t cbBufSrc;
1483 RTCircBufAcquireReadBlock(pCircBuf, cbChunk, &pvBufSrc, &cbBufSrc);
1484 AssertBreakStmt(cbBufSrc, RTCircBufReleaseReadBlock(pCircBuf, 0));
1485
1486 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, GCPhys, pvBufSrc, cbBufSrc);
1487 AssertRC(rc2);
1488
1489# ifdef HDA_DEBUG_SILENCE
1490 fix me if relevant;
1491# endif
1492 if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1493 { /* likely */ }
1494 else
1495 AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufSrc, cbBufSrc, 0 /* fFlags */);
1496
1497# ifdef VBOX_WITH_DTRACE
1498 VBOXDD_HDA_STREAM_DMA_IN((uint32_t)uSD, (uint32_t)cbBufSrc, pStreamShared->State.offRead);
1499# endif
1500 pStreamShared->State.offRead += cbBufSrc;
1501 RTCircBufReleaseReadBlock(pCircBuf, cbBufSrc);
1502 STAM_COUNTER_ADD(&pThis->StatBytesWritten, cbBufSrc);
1503
1504 /* advance */
1505 cbChunk -= (uint32_t)cbBufSrc;
1506 cbWritten += (uint32_t)cbBufSrc;
1507 GCPhys += cbBufSrc;
1508 pStreamShared->State.offCurBdle += (uint32_t)cbBufSrc;
1509 }
1510 }
1511 /*
1512 * We've got some initial silence to write, or we need to do
1513 * channel mapping. We produce guest output into the bounce buffer,
1514 * which is then copied into guest memory. The bounce buffer may keep
1515 * partial frames there for the next BDLE, if an BDLE isn't frame aligned.
1516 *
1517 * Note! cbLeft is relative to the input (host) frame size.
1518 * cbChunk OTOH is relative to output (guest) size.
1519 */
1520 else
1521 {
1522/** @todo clean up host/guest props distinction, they're the same now w/o the
1523 * mapping done by the mixer rather than us. */
1524 PCPDMAUDIOPCMPROPS pGuestProps = &pStreamShared->State.Cfg.Props;
1525 Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1526 uint32_t const cbLeftGuest = PDMAudioPropsFramesToBytes(pGuestProps,
1527 PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props,
1528 cbLeft));
1529 if (cbChunk <= cbLeftGuest)
1530 { /* very likely */ }
1531 else
1532 cbChunk = cbLeftGuest;
1533
1534 /*
1535 * Work till we've covered the chunk.
1536 */
1537 Log5Func(("loop0: GCPhys=%RGp cbChunk=%#x + cbBounce=%#x\n", GCPhys, cbChunk, cbBounce));
1538 while (cbChunk > 0)
1539 {
1540 /* Figure out how much we need to convert into the bounce buffer: */
1541 uint32_t cbGuest = PDMAudioPropsRoundUpBytesToFrame(pGuestProps, cbChunk - cbBounce);
1542 uint32_t cFrames = PDMAudioPropsBytesToFrames(pGuestProps, RT_MIN(cbGuest, sizeof(abBounce) - cbBounce));
1543
1544 cbGuest = PDMAudioPropsFramesToBytes(pGuestProps, cFrames);
1545 PDMAudioPropsClearBuffer(pGuestProps, &abBounce[cbBounce], cbGuest, cFrames);
1546 cbGuest += cbBounce;
1547
1548 /* Write it to the guest buffer. */
1549 uint32_t cbGuestActual = RT_MIN(cbGuest, cbChunk);
1550 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, GCPhys, abBounce, cbGuestActual);
1551 AssertRC(rc2);
1552 STAM_COUNTER_ADD(&pThis->StatBytesWritten, cbGuestActual);
1553
1554 /* advance */
1555 cbWritten += cbGuestActual;
1556 cbChunk -= cbGuestActual;
1557 GCPhys += cbGuestActual;
1558 pStreamShared->State.offCurBdle += cbGuestActual;
1559
1560 cbBounce = cbGuest - cbGuestActual;
1561 if (cbBounce)
1562 memmove(abBounce, &abBounce[cbGuestActual], cbBounce);
1563
1564 Log5Func((" loop1: GCPhys=%RGp cbGuestActual=%#x cbBounce=%#x cFrames=%#x\n", GCPhys, cbGuestActual, cbBounce, cFrames));
1565 }
1566 Log5Func(("loop0: GCPhys=%RGp cbBounce=%#x cbLeft=%#x\n", GCPhys, cbBounce, cbLeft - cbWritten));
1567 }
1568
1569 cbLeft -= cbWritten;
1570 STAM_PROFILE_STOP(&pThis->StatIn, a);
1571
1572 /*
1573 * Complete the buffer if necessary (common with the output DMA code).
1574 *
1575 * Must update the DMA position before we do this as the buffer IRQ may
1576 * fire on another vCPU and run in parallel to us, although it is very
1577 * unlikely it can make much progress as long as we're sitting on the
1578 * lock, it could still read the DMA position (Linux won't, as it reads
1579 * WALCLK and possibly SDnSTS before the DMA position).
1580 */
1581 hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, cbWritten);
1582 hdaStreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaR3StreamDoDmaInput");
1583 }
1584
1585 Assert(cbLeft == 0); /* There shall be no break statements in the above loop, so cbLeft is always zero here! */
1586 AssertMsg(cbBounce == 0, ("%#x\n", cbBounce));
1587
1588 /*
1589 * Common epilogue.
1590 */
1591 hdaR3StreamDoDmaEpilogue(pDevIns, pStreamShared, pStreamR3);
1592
1593 /*
1594 * Log and leave.
1595 */
1596 Log3Func(("LEAVE - [SD%RU8] %#RX32/%#RX32 @ %#RX64 - cTransferPendingInterrupts=%RU8\n",
1597 uSD, cbToConsume, pStreamShared->State.cbTransferSize, pStreamShared->State.offRead - cbToConsume,
1598 pStreamShared->State.cTransferPendingInterrupts));
1599}
1600
1601
1602/**
1603 * Input streams: Pulls data from the mixer, putting it in the internal DMA
1604 * buffer.
1605 *
1606 * @param pStreamShared HDA stream to update (shared).
1607 * @param pStreamR3 HDA stream to update (ring-3 bits).
1608 * @param pSink The mixer sink to pull from.
1609 */
1610static void hdaR3StreamPullFromMixer(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink)
1611{
1612# ifdef LOG_ENABLED
1613 uint64_t const offWriteOld = pStreamShared->State.offWrite;
1614# endif
1615 pStreamShared->State.offWrite = AudioMixerSinkTransferToCircBuf(pSink,
1616 pStreamR3->State.pCircBuf,
1617 pStreamShared->State.offWrite,
1618 pStreamR3->u8SD,
1619 pStreamR3->Dbg.Runtime.fEnabled
1620 ? pStreamR3->Dbg.Runtime.pFileStream : NULL);
1621
1622 Log3Func(("[SD%RU8] transferred=%#RX64 bytes -> @%#RX64\n", pStreamR3->u8SD,
1623 pStreamShared->State.offWrite - offWriteOld, pStreamShared->State.offWrite));
1624
1625 /* Update buffer stats. */
1626 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1627}
1628
1629
1630/**
1631 * Does DMA transfer for an HDA output stream.
1632 *
1633 * This transfers one DMA timer period worth of data from the guest and into the
1634 * internal DMA buffer.
1635 *
1636 * @param pDevIns The device instance.
1637 * @param pThis The shared HDA device state.
1638 * @param pStreamShared HDA stream to update (shared).
1639 * @param pStreamR3 HDA stream to update (ring-3).
1640 * @param cbToProduce The max amount of data to produce (i.e. put into
1641 * the circular buffer). Unless something is going
1642 * seriously wrong, this will always be transfer
1643 * size for the current period.
1644 * @param tsNowNs The current RTTimeNano() value.
1645 *
1646 * @remarks Caller owns the stream lock.
1647 */
1648static void hdaR3StreamDoDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
1649 PHDASTREAMR3 pStreamR3, uint32_t const cbToProduce, uint64_t tsNowNs)
1650{
1651 uint8_t const uSD = pStreamShared->u8SD;
1652 LogFlowFunc(("ENTER - #%u cbToProduce=%#x\n", uSD, cbToProduce));
1653
1654 /*
1655 * Common prologue.
1656 */
1657 if (hdaR3StreamDoDmaPrologue(pThis, pStreamShared, pStreamR3, uSD, tsNowNs, "hdaR3StreamDoDmaOutput"))
1658 { /* likely */ }
1659 else
1660 return;
1661
1662 /*
1663 *
1664 * The DMA copy loop.
1665 *
1666 */
1667# if 0
1668 uint8_t abBounce[4096 + 128]; /* Most guest does at most 4KB BDLE. So, 4KB + space for a partial frame to reduce loops. */
1669 uint32_t cbBounce = 0; /* in case of incomplete frames between buffer segments */
1670# endif
1671 PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1672 uint32_t cbLeft = cbToProduce;
1673# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
1674 Assert(cbLeft <= pStreamShared->State.cbTransferSize); /* a little pointless with the DMA'ing on LPIB read. */
1675# else
1676 Assert(cbLeft == pStreamShared->State.cbTransferSize);
1677# endif
1678 Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1679
1680 while (cbLeft > 0)
1681 {
1682 STAM_PROFILE_START(&pThis->StatOut, a);
1683
1684 /*
1685 * Figure out how much we can read & write in this iteration.
1686 */
1687 uint32_t cbChunk = 0;
1688 RTGCPHYS GCPhys = hdaStreamDmaBufGet(pStreamShared, &cbChunk);
1689
1690 /* Need to diverge if the BDLEs contain misaligned entries. */
1691 uint32_t cbRead = 0;
1692# if 0
1693 if (/** @todo pStreamShared->State.fFrameAlignedBuffers */)
1694# endif
1695 {
1696 if (cbChunk <= cbLeft)
1697 { /* very likely */ }
1698 else
1699 cbChunk = cbLeft;
1700
1701 /*
1702 * Read the guest data directly into the internal DMA buffer.
1703 */
1704 while (cbChunk > 0)
1705 {
1706 /* Grab internal DMA buffer space and read into it. */
1707 void *pvBufDst;
1708 size_t cbBufDst;
1709 RTCircBufAcquireWriteBlock(pCircBuf, cbChunk, &pvBufDst, &cbBufDst);
1710 AssertBreakStmt(cbBufDst, RTCircBufReleaseWriteBlock(pCircBuf, 0));
1711
1712 int rc2 = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, pvBufDst, cbBufDst);
1713 AssertRC(rc2);
1714
1715# ifdef HDA_DEBUG_SILENCE
1716 fix me if relevant;
1717# endif
1718 if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1719 { /* likely */ }
1720 else
1721 AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst, 0 /* fFlags */);
1722
1723# ifdef VBOX_WITH_DTRACE
1724 VBOXDD_HDA_STREAM_DMA_OUT((uint32_t)uSD, (uint32_t)cbBufDst, pStreamShared->State.offWrite);
1725# endif
1726 pStreamShared->State.offWrite += cbBufDst;
1727 RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
1728 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBufDst);
1729
1730 /* advance */
1731 cbChunk -= (uint32_t)cbBufDst;
1732 cbRead += (uint32_t)cbBufDst;
1733 GCPhys += cbBufDst;
1734 pStreamShared->State.offCurBdle += (uint32_t)cbBufDst;
1735 }
1736 }
1737# if 0
1738 /*
1739 * Need to map the frame content, so we need to read the guest data
1740 * into a temporary buffer, though the output can be directly written
1741 * into the internal buffer as it is assumed to be frame aligned.
1742 *
1743 * Note! cbLeft is relative to the output frame size.
1744 * cbChunk OTOH is relative to input size.
1745 */
1746 else
1747 {
1748/** @todo clean up host/guest props distinction, they're the same now w/o the
1749 * mapping done by the mixer rather than us. */
1750 PCPDMAUDIOPCMPROPS pGuestProps = &pStreamShared->State.Cfg.Props;
1751 Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1752 uint32_t const cbLeftGuest = PDMAudioPropsFramesToBytes(pGuestProps,
1753 PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props,
1754 cbLeft));
1755 if (cbChunk <= cbLeftGuest)
1756 { /* very likely */ }
1757 else
1758 cbChunk = cbLeftGuest;
1759
1760 /*
1761 * Loop till we've covered the chunk.
1762 */
1763 Log5Func(("loop0: GCPhys=%RGp cbChunk=%#x + cbBounce=%#x\n", GCPhys, cbChunk, cbBounce));
1764 while (cbChunk > 0)
1765 {
1766 /* Read into the bounce buffer. */
1767 uint32_t const cbToRead = RT_MIN(cbChunk, sizeof(abBounce) - cbBounce);
1768 int rc2 = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &abBounce[cbBounce], cbToRead);
1769 AssertRC(rc2);
1770 cbBounce += cbToRead;
1771
1772 /* Convert the size to whole frames and a remainder. */
1773 uint32_t cFrames = PDMAudioPropsBytesToFrames(pGuestProps, cbBounce);
1774 uint32_t const cbRemainder = cbBounce - PDMAudioPropsFramesToBytes(pGuestProps, cFrames);
1775 Log5Func((" loop1: GCPhys=%RGp cbToRead=%#x cbBounce=%#x cFrames=%#x\n", GCPhys, cbToRead, cbBounce, cFrames));
1776
1777 /*
1778 * Convert from the bounce buffer and into the internal DMA buffer.
1779 */
1780 uint32_t offBounce = 0;
1781 while (cFrames > 0)
1782 {
1783 void *pvBufDst;
1784 size_t cbBufDst;
1785 RTCircBufAcquireWriteBlock(pCircBuf, PDMAudioPropsFramesToBytes(&pStreamShared->State.Cfg.Props, cFrames),
1786 &pvBufDst, &cbBufDst);
1787
1788 uint32_t const cFramesToConvert = PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props, (uint32_t)cbBufDst);
1789 Assert(PDMAudioPropsFramesToBytes(&pStreamShared->State.Cfg.Props, cFramesToConvert) == cbBufDst);
1790 Assert(cFramesToConvert > 0);
1791 Assert(cFramesToConvert <= cFrames);
1792
1793 pStreamR3->State.Mapping.pfnGuestToHost(pvBufDst, &abBounce[offBounce], cFramesToConvert,
1794 &pStreamR3->State.Mapping);
1795 Log5Func((" loop2: offBounce=%#05x cFramesToConvert=%#05x cbBufDst=%#x%s\n",
1796 offBounce, cFramesToConvert, cbBufDst, ASMMemIsZero(pvBufDst, cbBufDst) ? " all zero" : ""));
1797
1798# ifdef HDA_DEBUG_SILENCE
1799 fix me if relevant;
1800# endif
1801 if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1802 { /* likely */ }
1803 else
1804 AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst, 0 /* fFlags */);
1805
1806 pStreamR3->State.offWrite += cbBufDst;
1807 RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
1808 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBufDst);
1809
1810 /* advance */
1811 cbLeft -= (uint32_t)cbBufDst;
1812 cFrames -= cFramesToConvert;
1813 offBounce += PDMAudioPropsFramesToBytes(pGuestProps, cFramesToConvert);
1814 }
1815
1816 /* advance */
1817 cbChunk -= cbToRead;
1818 GCPhys += cbToRead;
1819 pStreamShared->State.offCurBdle += cbToRead;
1820 if (cbRemainder)
1821 memmove(&abBounce[0], &abBounce[cbBounce - cbRemainder], cbRemainder);
1822 cbBounce = cbRemainder;
1823 }
1824 Log5Func(("loop0: GCPhys=%RGp cbBounce=%#x cbLeft=%#x\n", GCPhys, cbBounce, cbLeft));
1825 }
1826# endif
1827
1828 cbLeft -= cbRead;
1829 STAM_PROFILE_STOP(&pThis->StatOut, a);
1830
1831 /*
1832 * Complete the buffer if necessary (common with the input DMA code).
1833 *
1834 * Must update the DMA position before we do this as the buffer IRQ may
1835 * fire on another vCPU and run in parallel to us, although it is very
1836 * unlikely it can make much progress as long as we're sitting on the
1837 * lock, it could still read the DMA position (Linux won't, as it reads
1838 * WALCLK and possibly SDnSTS before the DMA position).
1839 */
1840 hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, cbRead);
1841 hdaStreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaR3StreamDoDmaOutput");
1842 }
1843
1844 Assert(cbLeft == 0); /* There shall be no break statements in the above loop, so cbLeft is always zero here! */
1845# if 0
1846 AssertMsg(cbBounce == 0, ("%#x\n", cbBounce));
1847# endif
1848
1849 /*
1850 * Common epilogue.
1851 */
1852 hdaR3StreamDoDmaEpilogue(pDevIns, pStreamShared, pStreamR3);
1853
1854 /*
1855 * Log and leave.
1856 */
1857 Log3Func(("LEAVE - [SD%RU8] %#RX32/%#RX32 @ %#RX64 - cTransferPendingInterrupts=%RU8\n",
1858 uSD, cbToProduce, pStreamShared->State.cbTransferSize, pStreamShared->State.offWrite - cbToProduce,
1859 pStreamShared->State.cTransferPendingInterrupts));
1860}
1861
1862#endif /* IN_RING3 */
1863
1864#ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
1865/**
1866 * Do DMA output transfer on LPIB register access.
1867 *
1868 * @returns VINF_SUCCESS or VINF_IOM_R3_MMIO_READ.
1869 * @param pDevIns The device instance.
1870 * @param pThis The shared instance data.
1871 * @param pStreamShared The shared stream data.
1872 * @param cbToTransfer How much to transfer.
1873 */
1874VBOXSTRICTRC hdaStreamDoOnAccessDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint32_t cbToTransfer)
1875{
1876 AssertReturn(cbToTransfer > 0, VINF_SUCCESS);
1877 int rc = VINF_SUCCESS;
1878
1879 /*
1880 * Check if we're exceeding the available buffer, go to ring-3 to
1881 * handle that (we would perhaps always take this path when in ring-3).
1882 */
1883 uint32_t cbDma = pStreamShared->State.cbDma;
1884 ASMCompilerBarrier();
1885 if ( cbDma >= sizeof(pStreamShared->State.abDma) /* paranoia */
1886 || cbToTransfer >= sizeof(pStreamShared->State.abDma) /* paranoia */
1887 || cbDma + cbToTransfer > sizeof(pStreamShared->State.abDma))
1888 {
1889# ifndef IN_RING3
1890 STAM_REL_COUNTER_INC(&pThis->StatAccessDmaOutputToR3);
1891 LogFlowFunc(("[SD%RU8] out of DMA buffer space (%#x, need %#x) -> VINF_IOM_R3_MMIO_READ\n",
1892 pStreamShared->u8SD, sizeof(pStreamShared->State.abDma) - pStreamShared->State.cbDma, cbToTransfer));
1893 return VINF_IOM_R3_MMIO_READ;
1894# else /* IN_RING3 */
1895 /*
1896 * Flush the bounce buffer, then do direct transfers to the
1897 * internal DMA buffer (updates LPIB).
1898 */
1899 PHDASTATER3 const pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
1900 uintptr_t const idxStream = pStreamShared->u8SD;
1901 AssertReturn(idxStream < RT_ELEMENTS(pThisCC->aStreams), VERR_INTERNAL_ERROR_4);
1902 PHDASTREAMR3 const pStreamR3 = &pThisCC->aStreams[idxStream];
1903
1904 hdaR3StreamFlushDmaBounceBufferOutput(pStreamShared, pStreamR3);
1905
1906 uint32_t cbStreamFree = hdaR3StreamGetFree(pStreamR3);
1907 if (cbStreamFree >= cbToTransfer)
1908 { /* likely */ }
1909 else
1910 {
1911 PAUDMIXSINK pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
1912 if (pSink)
1913 cbStreamFree = hdaR3StreamHandleDmaBufferOverrun(pStreamShared, pStreamR3, pSink, cbToTransfer, RTTimeNanoTS(),
1914 "hdaStreamDoOnAccessDmaOutput", cbStreamFree);
1915 else
1916 {
1917 LogFunc(("[SD%RU8] No sink and insufficient internal DMA buffer space (%#x) - won't do anything\n",
1918 pStreamShared->u8SD, cbStreamFree));
1919 return VINF_SUCCESS;
1920 }
1921 cbToTransfer = RT_MIN(cbToTransfer, cbStreamFree);
1922 if (cbToTransfer < PDMAudioPropsFrameSize(&pStreamShared->State.Cfg.Props))
1923 {
1924 LogFunc(("[SD%RU8] No internal DMA buffer space (%#x) - won't do anything\n", pStreamShared->u8SD, cbStreamFree));
1925 return VINF_SUCCESS;
1926 }
1927 }
1928 hdaR3StreamDoDmaOutput(pDevIns, pThis, pStreamShared, pStreamR3, cbToTransfer, RTTimeNanoTS());
1929 pStreamShared->State.cbDmaTotal += cbToTransfer;
1930# endif /* IN_RING3 */
1931 }
1932 else
1933 {
1934 /*
1935 * Transfer into the DMA bounce buffer.
1936 */
1937 LogFlowFunc(("[SD%RU8] Transfering %#x bytes to DMA bounce buffer (cbDma=%#x cbDmaTotal=%#x) (%p/%u)\n",
1938 pStreamShared->u8SD, cbToTransfer, cbDma, pStreamShared->State.cbDmaTotal, pStreamShared, pStreamShared->u8SD));
1939 uint32_t cbLeft = cbToTransfer;
1940 do
1941 {
1942 uint32_t cbChunk = 0;
1943 RTGCPHYS GCPhys = hdaStreamDmaBufGet(pStreamShared, &cbChunk);
1944
1945 bool fMustAdvanceBuffer;
1946 if (cbLeft < cbChunk)
1947 {
1948 fMustAdvanceBuffer = false;
1949 cbChunk = cbLeft;
1950 }
1951 else
1952 fMustAdvanceBuffer = true;
1953
1954 /* Read the guest data directly into the DMA bounce buffer. */
1955 int rc2 = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &pStreamShared->State.abDma[cbDma], cbChunk);
1956 AssertRC(rc2);
1957
1958 /* We update offWrite and StatBytesRead here even if we haven't moved the data
1959 to the internal DMA buffer yet, because we want the dtrace even to fire here. */
1960# ifdef VBOX_WITH_DTRACE
1961 VBOXDD_HDA_STREAM_DMA_OUT((uint32_t)pStreamShared->u8SD, cbChunk, pStreamShared->State.offWrite);
1962# endif
1963 pStreamShared->State.offWrite += cbChunk;
1964 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbChunk);
1965
1966 /* advance */
1967 pStreamShared->State.offCurBdle += cbChunk;
1968 pStreamShared->State.cbDmaTotal += cbChunk;
1969 cbDma += cbChunk;
1970 pStreamShared->State.cbDma = cbDma;
1971 cbLeft -= cbChunk;
1972 Log6Func(("cbLeft=%#x cbDma=%#x cbDmaTotal=%#x offCurBdle=%#x idxCurBdle=%#x (%p/%u)\n",
1973 cbLeft, cbDma, pStreamShared->State.cbDmaTotal, pStreamShared->State.offCurBdle,
1974 pStreamShared->State.idxCurBdle, pStreamShared, pStreamShared->u8SD));
1975
1976 /* Next buffer. */
1977 bool fAdvanced = hdaStreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaStreamDoOnAccessDmaOutput");
1978 AssertMsgStmt(fMustAdvanceBuffer == fAdvanced, ("%d %d\n", fMustAdvanceBuffer, fAdvanced), rc = VERR_INTERNAL_ERROR_3);
1979 } while (cbLeft > 0);
1980
1981 /*
1982 * Advance LPIB.
1983 */
1984 hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, cbToTransfer - cbLeft);
1985 }
1986
1987# ifdef VBOX_STRICT
1988 uint32_t idxSched = pStreamShared->State.idxSchedule;
1989 AssertStmt(idxSched < RT_MIN(RT_ELEMENTS(pStreamShared->State.aSchedule), pStreamShared->State.cSchedule), idxSched = 0);
1990 uint32_t const cbPeriod = pStreamShared->State.aSchedule[idxSched].cbPeriod;
1991 AssertMsg(pStreamShared->State.cbDmaTotal < cbPeriod, ("%#x vs %#x\n", pStreamShared->State.cbDmaTotal, cbPeriod));
1992# endif
1993
1994 STAM_REL_COUNTER_INC(&pThis->StatAccessDmaOutput);
1995 return rc;
1996}
1997#endif /* VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
1998
1999
2000#ifdef IN_RING3
2001
2002/**
2003 * Output streams: Pushes data to the mixer.
2004 *
2005 * @param pStreamShared HDA stream to update (shared bits).
2006 * @param pStreamR3 HDA stream to update (ring-3 bits).
2007 * @param pSink The mixer sink to push to.
2008 * @param nsNow The current RTTimeNanoTS() value.
2009 */
2010static void hdaR3StreamPushToMixer(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink, uint64_t nsNow)
2011{
2012# ifdef LOG_ENABLED
2013 uint64_t const offReadOld = pStreamShared->State.offRead;
2014# endif
2015 pStreamShared->State.offRead = AudioMixerSinkTransferFromCircBuf(pSink,
2016 pStreamR3->State.pCircBuf,
2017 pStreamShared->State.offRead,
2018 pStreamR3->u8SD,
2019 pStreamR3->Dbg.Runtime.fEnabled
2020 ? pStreamR3->Dbg.Runtime.pFileStream : NULL);
2021
2022 Assert(nsNow >= pStreamShared->State.tsLastReadNs);
2023 Log3Func(("[SD%RU8] nsDeltaLastRead=%RI64 transferred=%#RX64 bytes -> @%#RX64\n", pStreamR3->u8SD,
2024 nsNow - pStreamShared->State.tsLastReadNs, pStreamShared->State.offRead - offReadOld, pStreamShared->State.offRead));
2025 RT_NOREF(pStreamShared, nsNow);
2026
2027 /* Update buffer stats. */
2028 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
2029}
2030
2031
2032/**
2033 * Deals with a DMA buffer overrun.
2034 *
2035 * Makes sure we return with @a cbNeeded bytes of free space in pCircBuf.
2036 *
2037 * @returns Number of bytes free in the internal DMA buffer.
2038 * @param pStreamShared The shared data for the HDA stream.
2039 * @param pStreamR3 The ring-3 data for the HDA stream.
2040 * @param pSink The mixer sink (valid).
2041 * @param cbNeeded How much space we need (in bytes).
2042 * @param nsNow Current RTNanoTimeTS() timestamp.
2043 * @param cbStreamFree The current amount of free buffer space.
2044 * @param pszCaller The caller (for logging).
2045 */
2046static uint32_t hdaR3StreamHandleDmaBufferOverrun(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink,
2047 uint32_t cbNeeded, uint64_t nsNow,
2048 const char *pszCaller, uint32_t const cbStreamFree)
2049{
2050 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowProblems);
2051 Log(("%s: Warning! Stream #%u has insufficient space free: %#x bytes, need %#x. Will try move data out of the buffer...\n",
2052 pszCaller, pStreamShared->u8SD, cbStreamFree, cbNeeded));
2053 RT_NOREF(pszCaller, cbStreamFree);
2054
2055 int rc = AudioMixerSinkTryLock(pSink);
2056 if (RT_SUCCESS(rc))
2057 {
2058 hdaR3StreamPushToMixer(pStreamShared, pStreamR3, pSink, nsNow);
2059 AudioMixerSinkUpdate(pSink, 0, 0);
2060 AudioMixerSinkUnlock(pSink);
2061 }
2062 else
2063 RTThreadYield();
2064
2065 uint32_t const cbRet = hdaR3StreamGetFree(pStreamR3);
2066 Log(("%s: Gained %u bytes.\n", pszCaller, cbRet - cbStreamFree));
2067 if (cbRet >= cbNeeded)
2068 return cbRet;
2069
2070 /*
2071 * Unable to make sufficient space. Drop the whole buffer content.
2072 *
2073 * This is needed in order to keep the device emulation running at a
2074 * constant rate, at the cost of losing valid (but too much) data.
2075 */
2076 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowErrors);
2077 LogRel2(("HDA: Warning: Hit stream #%RU8 overflow, dropping %u bytes of audio data (%s)\n",
2078 pStreamShared->u8SD, hdaR3StreamGetUsed(pStreamR3), pszCaller));
2079# ifdef HDA_STRICT
2080 AssertMsgFailed(("Hit stream #%RU8 overflow -- timing bug?\n", pStreamShared->u8SD));
2081# endif
2082/**
2083 *
2084 * @todo r=bird: I don't think RTCircBufReset is entirely safe w/o
2085 * owning the AIO lock. See the note in the documentation about it not being
2086 * multi-threading aware (safe). Wish I'd verified this code much earlier.
2087 * Sigh^3!
2088 *
2089 */
2090 RTCircBufReset(pStreamR3->State.pCircBuf);
2091 pStreamShared->State.offWrite = 0;
2092 pStreamShared->State.offRead = 0;
2093 return hdaR3StreamGetFree(pStreamR3);
2094}
2095
2096
2097# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
2098/**
2099 * Flushes the DMA bounce buffer content to the internal DMA buffer.
2100 *
2101 * @param pStreamShared The shared data of the stream to have its DMA bounce
2102 * buffer flushed.
2103 * @param pStreamR3 The ring-3 stream data for same.
2104 */
2105static void hdaR3StreamFlushDmaBounceBufferOutput(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
2106{
2107 uint32_t cbDma = pStreamShared->State.cbDma;
2108 LogFlowFunc(("cbDma=%#x\n", cbDma));
2109 if (cbDma)
2110 {
2111 AssertReturnVoid(cbDma <= sizeof(pStreamShared->State.abDma));
2112 PRTCIRCBUF const pCircBuf = pStreamR3->State.pCircBuf;
2113 if (pCircBuf)
2114 {
2115 uint32_t offDma = 0;
2116 while (offDma < cbDma)
2117 {
2118 uint32_t const cbSrcLeft = cbDma - offDma;
2119
2120 /*
2121 * Grab a chunk of the internal DMA buffer.
2122 */
2123 void *pvBufDst = NULL;
2124 size_t cbBufDst = 0;
2125 RTCircBufAcquireWriteBlock(pCircBuf, cbSrcLeft, &pvBufDst, &cbBufDst);
2126 if (cbBufDst > 0)
2127 { /* likely */ }
2128 else
2129 {
2130 /* We've got buffering trouble. */
2131 RTCircBufReleaseWriteBlock(pCircBuf, 0);
2132
2133 PAUDMIXSINK pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
2134 if (pSink)
2135 hdaR3StreamHandleDmaBufferOverrun(pStreamShared, pStreamR3, pSink, cbSrcLeft, RTTimeNanoTS(),
2136 "hdaR3StreamFlushDmaBounceBufferOutput", 0 /*cbStreamFree*/);
2137 else
2138 {
2139 LogFunc(("Stream #%u has no sink. Dropping the rest of the data\n", pStreamR3->u8SD));
2140 break;
2141 }
2142
2143 RTCircBufAcquireWriteBlock(pCircBuf, cbSrcLeft, &pvBufDst, &cbBufDst);
2144 AssertBreakStmt(cbBufDst, RTCircBufReleaseWriteBlock(pCircBuf, 0));
2145 }
2146
2147 /*
2148 * Copy the samples into it and write it to the debug file if open.
2149 *
2150 * We do not fire the dtrace probe here nor update offRead as that was
2151 * done already (not sure that was a good idea?).
2152 */
2153 memcpy(pvBufDst, &pStreamShared->State.abDma[offDma], cbBufDst);
2154
2155 if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
2156 { /* likely */ }
2157 else
2158 AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst, 0 /* fFlags */);
2159
2160 RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
2161
2162 offDma += (uint32_t)cbBufDst;
2163 }
2164 }
2165
2166 /*
2167 * Mark the buffer empty.
2168 */
2169 pStreamShared->State.cbDma = 0;
2170 }
2171}
2172# endif /* VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
2173
2174
2175/**
2176 * The stream's main function when called by the timer.
2177 *
2178 * @note This function also will be called without timer invocation when
2179 * starting (enabling) the stream to minimize startup latency.
2180 *
2181 * @returns Current timer time if the timer is enabled, otherwise zero.
2182 * @param pDevIns The device instance.
2183 * @param pThis The shared HDA device state.
2184 * @param pThisCC The ring-3 HDA device state.
2185 * @param pStreamShared HDA stream to update (shared bits).
2186 * @param pStreamR3 HDA stream to update (ring-3 bits).
2187 */
2188uint64_t hdaR3StreamTimerMain(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
2189 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
2190{
2191 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2192 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pStreamShared->hTimer));
2193
2194 /* Do the work: */
2195 hdaR3StreamUpdateDma(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3);
2196
2197 /* Re-arm the timer if the sink is still active: */
2198 if ( pStreamShared->State.fRunning
2199 && pStreamR3->pMixSink
2200 && AudioMixerSinkIsActive(pStreamR3->pMixSink->pMixSink))
2201 {
2202 /* Advance the schduling: */
2203 uint32_t idxSched = pStreamShared->State.idxSchedule;
2204 AssertStmt(idxSched < RT_ELEMENTS(pStreamShared->State.aSchedule), idxSched = 0);
2205 uint32_t idxLoop = pStreamShared->State.idxScheduleLoop + 1;
2206 if (idxLoop >= pStreamShared->State.aSchedule[idxSched].cLoops)
2207 {
2208 idxSched += 1;
2209 if ( idxSched >= pStreamShared->State.cSchedule
2210 || idxSched >= RT_ELEMENTS(pStreamShared->State.aSchedule) /*paranoia^2*/)
2211 {
2212 idxSched = pStreamShared->State.cSchedulePrologue;
2213 AssertStmt(idxSched < RT_ELEMENTS(pStreamShared->State.aSchedule), idxSched = 0);
2214 }
2215 pStreamShared->State.idxSchedule = idxSched;
2216 idxLoop = 0;
2217 }
2218 pStreamShared->State.idxScheduleLoop = (uint16_t)idxLoop;
2219
2220 /* Do the actual timer re-arming. */
2221 uint64_t const tsNow = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer); /* (For virtual sync this remains the same for the whole callout IIRC) */
2222 uint64_t const tsTransferNext = tsNow + pStreamShared->State.aSchedule[idxSched].cPeriodTicks;
2223 Log3Func(("[SD%RU8] fSinkActive=true, tsTransferNext=%RU64 (in %RU64)\n",
2224 pStreamShared->u8SD, tsTransferNext, tsTransferNext - tsNow));
2225 int rc = PDMDevHlpTimerSet(pDevIns, pStreamShared->hTimer, tsTransferNext);
2226 AssertRC(rc);
2227
2228 /* Some legacy stuff: */
2229 pStreamShared->State.tsTransferNext = tsTransferNext;
2230 pStreamShared->State.cbTransferSize = pStreamShared->State.aSchedule[idxSched].cbPeriod;
2231
2232 return tsNow;
2233 }
2234
2235 Log3Func(("[SD%RU8] fSinkActive=false\n", pStreamShared->u8SD));
2236 return 0;
2237}
2238
2239
2240/**
2241 * Updates a HDA stream by doing DMA transfers.
2242 *
2243 * Will do mixer transfers too to try fix an overrun/underrun situation.
2244 *
2245 * The host sink(s) set the overall pace (bird: no it doesn't, the DMA timer
2246 * does - we just hope like heck it matches the speed at which the *backend*
2247 * host audio driver processes samples).
2248 *
2249 * @param pDevIns The device instance.
2250 * @param pThis The shared HDA device state.
2251 * @param pThisCC The ring-3 HDA device state.
2252 * @param pStreamShared HDA stream to update (shared bits).
2253 * @param pStreamR3 HDA stream to update (ring-3 bits).
2254 */
2255static void hdaR3StreamUpdateDma(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
2256 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
2257{
2258 RT_NOREF(pThisCC);
2259 int rc2;
2260
2261 /*
2262 * Make sure we're running and got an active mixer sink.
2263 */
2264 if (RT_LIKELY(pStreamShared->State.fRunning))
2265 { /* likely */ }
2266 else
2267 return;
2268
2269 PAUDMIXSINK pSink = NULL;
2270 if (pStreamR3->pMixSink)
2271 pSink = pStreamR3->pMixSink->pMixSink;
2272 if (RT_LIKELY(AudioMixerSinkIsActive(pSink)))
2273 { /* likely */ }
2274 else
2275 return;
2276
2277 /*
2278 * Get scheduling info common to both input and output streams.
2279 */
2280 const uint64_t tsNowNs = RTTimeNanoTS();
2281 uint32_t idxSched = pStreamShared->State.idxSchedule;
2282 AssertStmt(idxSched < RT_MIN(RT_ELEMENTS(pStreamShared->State.aSchedule), pStreamShared->State.cSchedule), idxSched = 0);
2283 uint32_t cbPeriod = pStreamShared->State.aSchedule[idxSched].cbPeriod;
2284
2285 /*
2286 * Output streams (SDO).
2287 */
2288 if (hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_OUT)
2289 {
2290# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
2291 /* Subtract already transferred bytes and flush the DMA bounce buffer. */
2292 uint32_t cbDmaTotal = pStreamShared->State.cbDmaTotal;
2293 if (cbDmaTotal > 0)
2294 {
2295 AssertStmt(cbDmaTotal < cbPeriod, cbDmaTotal = cbPeriod);
2296 cbPeriod -= cbDmaTotal;
2297 pStreamShared->State.cbDmaTotal = 0;
2298 hdaR3StreamFlushDmaBounceBufferOutput(pStreamShared, pStreamR3);
2299 }
2300 else
2301 Assert(pStreamShared->State.cbDma == 0);
2302# endif
2303
2304 /*
2305 * Check how much room we have in our DMA buffer. There should be at
2306 * least one period worth of space there or we're in an overflow situation.
2307 */
2308 uint32_t cbStreamFree = hdaR3StreamGetFree(pStreamR3);
2309 if (cbStreamFree >= cbPeriod)
2310 { /* likely */ }
2311 else
2312 cbStreamFree = hdaR3StreamHandleDmaBufferOverrun(pStreamShared, pStreamR3, pSink, cbPeriod, tsNowNs,
2313 "hdaR3StreamUpdateDma", cbStreamFree);
2314
2315 /*
2316 * Do the DMA transfer.
2317 */
2318 uint64_t const offWriteBefore = pStreamShared->State.offWrite;
2319 hdaR3StreamDoDmaOutput(pDevIns, pThis, pStreamShared, pStreamR3, RT_MIN(cbStreamFree, cbPeriod), tsNowNs);
2320
2321 /*
2322 * Should we push data to down thru the mixer to and to the host drivers?
2323 *
2324 * We initially delay this by pThis->msInitialDelay, but after than we'll
2325 * kick the AIO thread every time we've put more data in the buffer (which is
2326 * every time) as the host audio device needs to get data in a timely manner.
2327 *
2328 * (We used to try only wake up the AIO thread according to pThis->uIoTimer
2329 * and host wall clock, but that meant we would miss a wakup after the DMA
2330 * timer was called a little late or if TM entered into catch-up mode.)
2331 */
2332 bool fKickAioThread;
2333 if (!pStreamShared->State.tsAioDelayEnd)
2334 fKickAioThread = pStreamShared->State.offWrite > offWriteBefore
2335 || hdaR3StreamGetFree(pStreamR3) < pStreamShared->State.cbAvgTransfer * 2;
2336 else if (PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer) >= pStreamShared->State.tsAioDelayEnd)
2337 {
2338 Log3Func(("Initial delay done: Passed tsAioDelayEnd.\n"));
2339 pStreamShared->State.tsAioDelayEnd = 0;
2340 fKickAioThread = true;
2341 }
2342 else if (hdaR3StreamGetFree(pStreamR3) < pStreamShared->State.cbAvgTransfer * 2)
2343 {
2344 Log3Func(("Initial delay done: Passed running short on buffer.\n"));
2345 pStreamShared->State.tsAioDelayEnd = 0;
2346 fKickAioThread = true;
2347 }
2348 else
2349 {
2350 Log3Func(("Initial delay pending...\n"));
2351 fKickAioThread = false;
2352 }
2353
2354 Log3Func(("msDelta=%RU64 (vs %u) cbStreamFree=%#x (vs %#x) => fKickAioThread=%RTbool\n",
2355 (tsNowNs - pStreamShared->State.tsLastReadNs) / RT_NS_1MS,
2356 pStreamShared->State.Cfg.Device.cMsSchedulingHint, cbStreamFree,
2357 pStreamShared->State.cbAvgTransfer * 2, fKickAioThread));
2358
2359 if (fKickAioThread)
2360 {
2361 /* Notify the async I/O worker thread that there's work to do. */
2362 Log5Func(("Notifying AIO thread\n"));
2363 rc2 = AudioMixerSinkSignalUpdateJob(pSink);
2364 AssertRC(rc2);
2365 /* Update last read timestamp for logging/debugging. */
2366 pStreamShared->State.tsLastReadNs = tsNowNs;
2367 }
2368 }
2369 /*
2370 * Input stream (SDI).
2371 */
2372 else
2373 {
2374 Assert(hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_IN);
2375
2376 /*
2377 * See how much data we've got buffered...
2378 */
2379 bool fWriteSilence = false;
2380 uint32_t cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2381 if (pStreamShared->State.fInputPreBuffered && cbStreamUsed >= cbPeriod)
2382 { /*likely*/ }
2383 /*
2384 * Because it may take a while for the input stream to get going (at
2385 * least with pulseaudio), we feed the guest silence till we've
2386 * pre-buffer a reasonable amount of audio.
2387 */
2388 else if (!pStreamShared->State.fInputPreBuffered)
2389 {
2390 if (cbStreamUsed < pStreamShared->State.cbInputPreBuffer)
2391 {
2392 Log3(("hdaR3StreamUpdateDma: Pre-buffering (got %#x out of %#x bytes)...\n",
2393 cbStreamUsed, pStreamShared->State.cbInputPreBuffer));
2394 fWriteSilence = true;
2395 }
2396 else
2397 {
2398 Log3(("hdaR3StreamUpdateDma: Completed pre-buffering (got %#x, needed %#x bytes).\n",
2399 cbStreamUsed, pStreamShared->State.cbInputPreBuffer));
2400 pStreamShared->State.fInputPreBuffered = true;
2401 fWriteSilence = true; /* For now, just do the most conservative thing. */
2402 }
2403 cbStreamUsed = cbPeriod;
2404 }
2405 /*
2406 * When we're low on data, we must really try fetch some ourselves
2407 * as buffer underruns must not happen.
2408 */
2409 else
2410 {
2411 /** @todo We're ending up here to frequently with pulse audio at least (just
2412 * watch the stream stats in the statistcs viewer, and way to often we
2413 * have to inject silence bytes. I suspect part of the problem is
2414 * that the HDA device require a much better latency than what the
2415 * pulse audio is configured for by default (10 ms vs 150ms). */
2416 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowProblems);
2417 Log(("hdaR3StreamUpdateDma: Warning! Stream #%u has insufficient data available: %u bytes, need %u. Will try move pull more data into the buffer...\n",
2418 pStreamShared->u8SD, cbStreamUsed, cbPeriod));
2419 int rc = AudioMixerSinkTryLock(pSink);
2420 if (RT_SUCCESS(rc))
2421 {
2422 AudioMixerSinkUpdate(pSink, cbStreamUsed, cbPeriod);
2423 hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2424 AudioMixerSinkUnlock(pSink);
2425 }
2426 else
2427 RTThreadYield();
2428 Log(("hdaR3StreamUpdateDma: Gained %u bytes.\n", hdaR3StreamGetUsed(pStreamR3) - cbStreamUsed));
2429 cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2430 if (cbStreamUsed < cbPeriod)
2431 {
2432 /* Unable to find sufficient input data by simple prodding.
2433 In order to keep a constant byte stream following thru the DMA
2434 engine into the guest, we will try again and then fall back on
2435 filling the gap with silence. */
2436 uint32_t cbSilence = 0;
2437 do
2438 {
2439 AudioMixerSinkLock(pSink);
2440
2441 cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2442 if (cbStreamUsed < cbPeriod)
2443 {
2444 hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2445 cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2446 while (cbStreamUsed < cbPeriod)
2447 {
2448 void *pvDstBuf;
2449 size_t cbDstBuf;
2450 RTCircBufAcquireWriteBlock(pStreamR3->State.pCircBuf, cbPeriod - cbStreamUsed,
2451 &pvDstBuf, &cbDstBuf);
2452 RT_BZERO(pvDstBuf, cbDstBuf);
2453 RTCircBufReleaseWriteBlock(pStreamR3->State.pCircBuf, cbDstBuf);
2454 cbSilence += (uint32_t)cbDstBuf;
2455 cbStreamUsed += (uint32_t)cbDstBuf;
2456 }
2457 }
2458
2459 AudioMixerSinkUnlock(pSink);
2460 } while (cbStreamUsed < cbPeriod);
2461 if (cbSilence > 0)
2462 {
2463 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowErrors);
2464 STAM_REL_COUNTER_ADD(&pStreamR3->State.StatDmaFlowErrorBytes, cbSilence);
2465 LogRel2(("HDA: Warning: Stream #%RU8 underrun, added %u bytes of silence (%u us)\n", pStreamShared->u8SD,
2466 cbSilence, PDMAudioPropsBytesToMicro(&pStreamShared->State.Cfg.Props, cbSilence)));
2467 }
2468 }
2469 }
2470
2471 /*
2472 * Do the DMA'ing.
2473 */
2474 if (cbStreamUsed)
2475 hdaR3StreamDoDmaInput(pDevIns, pThis, pStreamShared, pStreamR3,
2476 RT_MIN(cbStreamUsed, cbPeriod), fWriteSilence, tsNowNs);
2477
2478 /*
2479 * We should always kick the AIO thread.
2480 */
2481 /** @todo This isn't entirely ideal. If we get into an underrun situation,
2482 * we ideally want the AIO thread to run right before the DMA timer
2483 * rather than right after it ran. */
2484 Log5Func(("Notifying AIO thread\n"));
2485 rc2 = AudioMixerSinkSignalUpdateJob(pSink);
2486 AssertRC(rc2);
2487 pStreamShared->State.tsLastReadNs = tsNowNs;
2488 }
2489}
2490
2491
2492/**
2493 * @callback_method_impl{FNAUDMIXSINKUPDATE}
2494 *
2495 * For output streams this moves data from the internal DMA buffer (in which
2496 * hdaR3StreamUpdateDma put it), thru the mixer and to the various backend audio
2497 * devices.
2498 *
2499 * For input streams this pulls data from the backend audio device(s), thru the
2500 * mixer and puts it in the internal DMA buffer ready for hdaR3StreamUpdateDma
2501 * to pump into guest memory.
2502 */
2503DECLCALLBACK(void) hdaR3StreamUpdateAsyncIoJob(PPDMDEVINS pDevIns, PAUDMIXSINK pSink, void *pvUser)
2504{
2505 PHDASTATE const pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
2506 PHDASTATER3 const pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
2507 PHDASTREAMR3 const pStreamR3 = (PHDASTREAMR3)pvUser;
2508 PHDASTREAM const pStreamShared = &pThis->aStreams[pStreamR3 - &pThisCC->aStreams[0]];
2509 Assert(pStreamR3 - &pThisCC->aStreams[0] == pStreamR3->u8SD);
2510 Assert(pStreamShared->u8SD == pStreamR3->u8SD);
2511 RT_NOREF(pSink);
2512
2513 /*
2514 * Make sure we haven't change sink and that it's still active (it
2515 * should be or we wouldn't have been called).
2516 */
2517 AssertReturnVoid(pStreamR3->pMixSink && pSink == pStreamR3->pMixSink->pMixSink);
2518 AssertReturnVoid(AudioMixerSinkIsActive(pSink));
2519
2520 /*
2521 * Output streams (SDO).
2522 */
2523 if (hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_OUT)
2524 hdaR3StreamPushToMixer(pStreamShared, pStreamR3, pSink, RTTimeNanoTS());
2525 /*
2526 * Input stream (SDI).
2527 */
2528 else
2529 {
2530 Assert(hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_IN);
2531 hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2532 }
2533}
2534
2535
2536# if 0 /* unused - no prototype even */
2537/**
2538 * Updates an HDA stream's current read or write buffer position (depending on the stream type) by
2539 * updating its associated LPIB register and DMA position buffer (if enabled).
2540 *
2541 * @returns Set LPIB value.
2542 * @param pDevIns The device instance.
2543 * @param pStream HDA stream to update read / write position for.
2544 * @param u32LPIB New LPIB (position) value to set.
2545 */
2546uint32_t hdaR3StreamUpdateLPIB(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint32_t u32LPIB)
2547{
2548 AssertMsg(u32LPIB <= pStreamShared->u32CBL,
2549 ("[SD%RU8] New LPIB (%RU32) exceeds CBL (%RU32)\n", pStreamShared->u8SD, u32LPIB, pStreamShared->u32CBL));
2550
2551 u32LPIB = RT_MIN(u32LPIB, pStreamShared->u32CBL);
2552
2553 LogFlowFunc(("[SD%RU8] LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n",
2554 pStreamShared->u8SD, u32LPIB, pThis->fDMAPosition));
2555
2556 /* Update LPIB in any case. */
2557 HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) = u32LPIB;
2558
2559 /* Do we need to tell the current DMA position? */
2560 if (pThis->fDMAPosition)
2561 {
2562 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns,
2563 pThis->u64DPBase + (pStreamShared->u8SD * 2 * sizeof(uint32_t)),
2564 (void *)&u32LPIB, sizeof(uint32_t));
2565 AssertRC(rc2);
2566 }
2567
2568 return u32LPIB;
2569}
2570# endif
2571
2572# ifdef HDA_USE_DMA_ACCESS_HANDLER
2573/**
2574 * Registers access handlers for a stream's BDLE DMA accesses.
2575 *
2576 * @returns true if registration was successful, false if not.
2577 * @param pStream HDA stream to register BDLE access handlers for.
2578 */
2579bool hdaR3StreamRegisterDMAHandlers(PHDASTREAM pStream)
2580{
2581 /* At least LVI and the BDL base must be set. */
2582 if ( !pStreamShared->u16LVI
2583 || !pStreamShared->u64BDLBase)
2584 {
2585 return false;
2586 }
2587
2588 hdaR3StreamUnregisterDMAHandlers(pStream);
2589
2590 LogFunc(("Registering ...\n"));
2591
2592 int rc = VINF_SUCCESS;
2593
2594 /*
2595 * Create BDLE ranges.
2596 */
2597
2598 struct BDLERANGE
2599 {
2600 RTGCPHYS uAddr;
2601 uint32_t uSize;
2602 } arrRanges[16]; /** @todo Use a define. */
2603
2604 size_t cRanges = 0;
2605
2606 for (uint16_t i = 0; i < pStreamShared->u16LVI + 1; i++)
2607 {
2608 HDABDLE BDLE;
2609 rc = hdaR3BDLEFetch(pDevIns, &BDLE, pStreamShared->u64BDLBase, i /* Index */);
2610 if (RT_FAILURE(rc))
2611 break;
2612
2613 bool fAddRange = true;
2614 BDLERANGE *pRange;
2615
2616 if (cRanges)
2617 {
2618 pRange = &arrRanges[cRanges - 1];
2619
2620 /* Is the current range a direct neighbor of the current BLDE? */
2621 if ((pRange->uAddr + pRange->uSize) == BDLE.Desc.u64BufAddr)
2622 {
2623 /* Expand the current range by the current BDLE's size. */
2624 pRange->uSize += BDLE.Desc.u32BufSize;
2625
2626 /* Adding a new range in this case is not needed anymore. */
2627 fAddRange = false;
2628
2629 LogFunc(("Expanding range %zu by %RU32 (%RU32 total now)\n", cRanges - 1, BDLE.Desc.u32BufSize, pRange->uSize));
2630 }
2631 }
2632
2633 /* Do we need to add a new range? */
2634 if ( fAddRange
2635 && cRanges < RT_ELEMENTS(arrRanges))
2636 {
2637 pRange = &arrRanges[cRanges];
2638
2639 pRange->uAddr = BDLE.Desc.u64BufAddr;
2640 pRange->uSize = BDLE.Desc.u32BufSize;
2641
2642 LogFunc(("Adding range %zu - 0x%x (%RU32)\n", cRanges, pRange->uAddr, pRange->uSize));
2643
2644 cRanges++;
2645 }
2646 }
2647
2648 LogFunc(("%zu ranges total\n", cRanges));
2649
2650 /*
2651 * Register all ranges as DMA access handlers.
2652 */
2653
2654 for (size_t i = 0; i < cRanges; i++)
2655 {
2656 BDLERANGE *pRange = &arrRanges[i];
2657
2658 PHDADMAACCESSHANDLER pHandler = (PHDADMAACCESSHANDLER)RTMemAllocZ(sizeof(HDADMAACCESSHANDLER));
2659 if (!pHandler)
2660 {
2661 rc = VERR_NO_MEMORY;
2662 break;
2663 }
2664
2665 RTListAppend(&pStream->State.lstDMAHandlers, &pHandler->Node);
2666
2667 pHandler->pStream = pStream; /* Save a back reference to the owner. */
2668
2669 char szDesc[32];
2670 RTStrPrintf(szDesc, sizeof(szDesc), "HDA[SD%RU8 - RANGE%02zu]", pStream->u8SD, i);
2671
2672 int rc2 = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
2673 hdaDMAAccessHandler,
2674 NULL, NULL, NULL,
2675 NULL, NULL, NULL,
2676 szDesc, &pHandler->hAccessHandlerType);
2677 AssertRCBreak(rc2);
2678
2679 pHandler->BDLEAddr = pRange->uAddr;
2680 pHandler->BDLESize = pRange->uSize;
2681
2682 /* Get first and last pages of the BDLE range. */
2683 RTGCPHYS pgFirst = pRange->uAddr & ~PAGE_OFFSET_MASK;
2684 RTGCPHYS pgLast = RT_ALIGN(pgFirst + pRange->uSize, PAGE_SIZE);
2685
2686 /* Calculate the region size (in pages). */
2687 RTGCPHYS regionSize = RT_ALIGN(pgLast - pgFirst, PAGE_SIZE);
2688
2689 pHandler->GCPhysFirst = pgFirst;
2690 pHandler->GCPhysLast = pHandler->GCPhysFirst + (regionSize - 1);
2691
2692 LogFunc((" Registering region '%s': %#RGp - %#RGp (region size: %#zx)\n",
2693 szDesc, pHandler->GCPhysFirst, pHandler->GCPhysLast, regionSize));
2694 LogFunc((" BDLE @ %#RGp - %#RGp (%#RX32)\n",
2695 pHandler->BDLEAddr, pHandler->BDLEAddr + pHandler->BDLESize, pHandler->BDLESize));
2696
2697 rc2 = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3),
2698 pHandler->GCPhysFirst, pHandler->GCPhysLast,
2699 pHandler->hAccessHandlerType, pHandler, NIL_RTR0PTR, NIL_RTRCPTR,
2700 szDesc);
2701 AssertRCBreak(rc2);
2702
2703 pHandler->fRegistered = true;
2704 }
2705
2706 LogFunc(("Registration ended with rc=%Rrc\n", rc));
2707
2708 return RT_SUCCESS(rc);
2709}
2710
2711/**
2712 * Unregisters access handlers of a stream's BDLEs.
2713 *
2714 * @param pStream HDA stream to unregister BDLE access handlers for.
2715 */
2716void hdaR3StreamUnregisterDMAHandlers(PHDASTREAM pStream)
2717{
2718 LogFunc(("\n"));
2719
2720 PHDADMAACCESSHANDLER pHandler, pHandlerNext;
2721 RTListForEachSafe(&pStream->State.lstDMAHandlers, pHandler, pHandlerNext, HDADMAACCESSHANDLER, Node)
2722 {
2723 if (!pHandler->fRegistered) /* Handler not registered? Skip. */
2724 continue;
2725
2726 LogFunc(("Unregistering 0x%x - 0x%x (%zu)\n",
2727 pHandler->GCPhysFirst, pHandler->GCPhysLast, pHandler->GCPhysLast - pHandler->GCPhysFirst));
2728
2729 int rc2 = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3),
2730 pHandler->GCPhysFirst);
2731 AssertRC(rc2);
2732
2733 RTListNodeRemove(&pHandler->Node);
2734
2735 RTMemFree(pHandler);
2736 pHandler = NULL;
2737 }
2738
2739 Assert(RTListIsEmpty(&pStream->State.lstDMAHandlers));
2740}
2741
2742# endif /* HDA_USE_DMA_ACCESS_HANDLER */
2743
2744#endif /* IN_RING3 */
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