VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevHdaStream.cpp@ 89862

Last change on this file since 89862 was 89862, checked in by vboxsync, 3 years ago

DevHda: Do LPIB updates more often. Experimental code for doing DMA work on LPIB read (disabled). [build fix] bugref:9890
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1/* $Id: DevHdaStream.cpp 89862 2021-06-23 14:28:25Z vboxsync $ */
2/** @file
3 * Intel HD Audio Controller Emulation - Streams.
4 */
5
6/*
7 * Copyright (C) 2017-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_HDA
23#include <VBox/log.h>
24
25#include <iprt/mem.h>
26#include <iprt/semaphore.h>
27
28#include <VBox/AssertGuest.h>
29#include <VBox/vmm/pdmdev.h>
30#include <VBox/vmm/pdmaudioifs.h>
31#include <VBox/vmm/pdmaudioinline.h>
32
33#include "AudioHlp.h"
34
35#include "DevHda.h"
36#include "DevHdaStream.h"
37
38#ifdef VBOX_WITH_DTRACE
39# include "dtrace/VBoxDD.h"
40#endif
41
42
43/*********************************************************************************************************************************
44* Internal Functions *
45*********************************************************************************************************************************/
46static void hdaStreamSetPositionAbs(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uLPIB);
47#ifdef IN_RING3
48# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
49static void hdaR3StreamFlushDmaBounceBufferOutput(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
50# endif
51static uint32_t hdaR3StreamHandleDmaBufferOverrun(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink,
52 uint32_t cbNeeded, uint64_t nsNow,
53 const char *pszCaller, uint32_t const cbStreamFree);
54static void hdaR3StreamUpdateDma(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
55 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
56#endif
57
58
59#ifdef IN_RING3
60
61/**
62 * Creates an HDA stream.
63 *
64 * @returns VBox status code.
65 * @param pStreamShared The HDA stream to construct - shared bits.
66 * @param pStreamR3 The HDA stream to construct - ring-3 bits.
67 * @param pThis The shared HDA device instance.
68 * @param pThisCC The ring-3 HDA device instance.
69 * @param uSD Stream descriptor number to assign.
70 */
71int hdaR3StreamConstruct(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PHDASTATE pThis, PHDASTATER3 pThisCC, uint8_t uSD)
72{
73 pStreamR3->u8SD = uSD;
74 pStreamShared->u8SD = uSD;
75 pStreamR3->pMixSink = NULL;
76 pStreamR3->pHDAStateShared = pThis;
77 pStreamR3->pHDAStateR3 = pThisCC;
78 Assert(pStreamShared->hTimer != NIL_TMTIMERHANDLE); /* hdaR3Construct initalized this one already. */
79
80 pStreamShared->State.fInReset = false;
81 pStreamShared->State.fRunning = false;
82# ifdef HDA_USE_DMA_ACCESS_HANDLER
83 RTListInit(&pStreamR3->State.lstDMAHandlers);
84# endif
85
86 AssertPtr(pStreamR3->pHDAStateR3);
87 AssertPtr(pStreamR3->pHDAStateR3->pDevIns);
88
89# ifdef DEBUG
90 int rc = RTCritSectInit(&pStreamR3->Dbg.CritSect);
91 AssertRCReturn(rc, rc);
92# endif
93
94 const bool fIsInput = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN;
95
96 if (fIsInput)
97 {
98 pStreamShared->State.Cfg.enmPath = PDMAUDIOPATH_UNKNOWN;
99 pStreamShared->State.Cfg.enmDir = PDMAUDIODIR_IN;
100 }
101 else
102 {
103 pStreamShared->State.Cfg.enmPath = PDMAUDIOPATH_UNKNOWN;
104 pStreamShared->State.Cfg.enmDir = PDMAUDIODIR_OUT;
105 }
106
107 pStreamR3->Dbg.Runtime.fEnabled = pThisCC->Dbg.fEnabled;
108
109 if (pStreamR3->Dbg.Runtime.fEnabled)
110 {
111 char szFile[64];
112 char szPath[RTPATH_MAX];
113
114 /* pFileStream */
115 if (fIsInput)
116 RTStrPrintf(szFile, sizeof(szFile), "hdaStreamWriteSD%RU8", uSD);
117 else
118 RTStrPrintf(szFile, sizeof(szFile), "hdaStreamReadSD%RU8", uSD);
119
120 int rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
121 0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
122 AssertRC(rc2);
123
124 rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileStream);
125 AssertRC(rc2);
126
127 /* pFileDMARaw */
128 if (fIsInput)
129 RTStrPrintf(szFile, sizeof(szFile), "hdaDMARawWriteSD%RU8", uSD);
130 else
131 RTStrPrintf(szFile, sizeof(szFile), "hdaDMARawReadSD%RU8", uSD);
132
133 rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
134 0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
135 AssertRC(rc2);
136
137 rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileDMARaw);
138 AssertRC(rc2);
139
140 /* pFileDMAMapped */
141 if (fIsInput)
142 RTStrPrintf(szFile, sizeof(szFile), "hdaDMAWriteMappedSD%RU8", uSD);
143 else
144 RTStrPrintf(szFile, sizeof(szFile), "hdaDMAReadMappedSD%RU8", uSD);
145
146 rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
147 0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
148 AssertRC(rc2);
149
150 rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileDMAMapped);
151 AssertRC(rc2);
152
153 /* Delete stale debugging files from a former run. */
154 AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileStream);
155 AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileDMARaw);
156 AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileDMAMapped);
157 }
158
159 return VINF_SUCCESS;
160}
161
162/**
163 * Destroys an HDA stream.
164 *
165 * @param pStreamR3 The HDA stream to destroy - ring-3 bits.
166 */
167void hdaR3StreamDestroy(PHDASTREAMR3 pStreamR3)
168{
169 LogFlowFunc(("[SD%RU8] Destroying ...\n", pStreamR3->u8SD));
170 int rc2;
171
172 if (pStreamR3->State.pAioRegSink)
173 {
174 rc2 = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
175 AssertRC(rc2);
176 pStreamR3->State.pAioRegSink = NULL;
177 }
178
179 if (pStreamR3->State.pCircBuf)
180 {
181 RTCircBufDestroy(pStreamR3->State.pCircBuf);
182 pStreamR3->State.pCircBuf = NULL;
183 pStreamR3->State.StatDmaBufSize = 0;
184 pStreamR3->State.StatDmaBufUsed = 0;
185 }
186
187# ifdef DEBUG
188 if (RTCritSectIsInitialized(&pStreamR3->Dbg.CritSect))
189 {
190 rc2 = RTCritSectDelete(&pStreamR3->Dbg.CritSect);
191 AssertRC(rc2);
192 }
193# endif
194
195 if (pStreamR3->Dbg.Runtime.fEnabled)
196 {
197 AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileStream);
198 pStreamR3->Dbg.Runtime.pFileStream = NULL;
199
200 AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileDMARaw);
201 pStreamR3->Dbg.Runtime.pFileDMARaw = NULL;
202
203 AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileDMAMapped);
204 pStreamR3->Dbg.Runtime.pFileDMAMapped = NULL;
205 }
206
207 LogFlowFuncLeave();
208}
209
210
211/**
212 * Appends a item to the scheduler.
213 *
214 * @returns VBox status code.
215 * @param pStreamShared The stream which scheduler should be modified.
216 * @param cbCur The period length in guest bytes.
217 * @param cbMaxPeriod The max period in guest bytes.
218 * @param idxLastBdle The last BDLE in the period.
219 * @param pHostProps The host PCM properties.
220 * @param pGuestProps The guest PCM properties.
221 * @param pcbBorrow Where to account for bytes borrowed across buffers
222 * to align scheduling items on frame boundraries.
223 */
224static int hdaR3StreamAddScheduleItem(PHDASTREAM pStreamShared, uint32_t cbCur, uint32_t cbMaxPeriod, uint32_t idxLastBdle,
225 PCPDMAUDIOPCMPROPS pHostProps, PCPDMAUDIOPCMPROPS pGuestProps, uint32_t *pcbBorrow)
226{
227 /* Check that we've got room (shouldn't ever be a problem). */
228 size_t idx = pStreamShared->State.cSchedule;
229 AssertLogRelReturn(idx + 1 < RT_ELEMENTS(pStreamShared->State.aSchedule), VERR_INTERNAL_ERROR_5);
230
231 /* Figure out the BDLE range for this period. */
232 uint32_t const idxFirstBdle = idx == 0 ? 0
233 : RT_MIN((uint32_t)( pStreamShared->State.aSchedule[idx - 1].idxFirst
234 + pStreamShared->State.aSchedule[idx - 1].cEntries),
235 idxLastBdle);
236
237 pStreamShared->State.aSchedule[idx].idxFirst = (uint8_t)idxFirstBdle;
238 pStreamShared->State.aSchedule[idx].cEntries = idxLastBdle >= idxFirstBdle
239 ? idxLastBdle - idxFirstBdle + 1
240 : pStreamShared->State.cBdles - idxFirstBdle + idxLastBdle + 1;
241
242 /* Deal with borrowing due to unaligned IOC buffers. */
243 uint32_t const cbBorrowed = *pcbBorrow;
244 if (cbBorrowed < cbCur)
245 cbCur -= cbBorrowed;
246 else
247 {
248 /* Note. We can probably gloss over this, but it's not a situation a sane guest would put us, so don't bother for now. */
249 ASSERT_GUEST_MSG_FAILED(("#%u: cbBorrow=%#x cbCur=%#x BDLE[%u..%u]\n",
250 pStreamShared->u8SD, cbBorrowed, cbCur, idxFirstBdle, idxLastBdle));
251 LogRelMax(32, ("HDA: Stream #%u has a scheduling error: cbBorrow=%#x cbCur=%#x BDLE[%u..%u]\n",
252 pStreamShared->u8SD, cbBorrowed, cbCur, idxFirstBdle, idxLastBdle));
253 return VERR_OUT_OF_RANGE;
254 }
255
256 uint32_t cbCurAligned = PDMAudioPropsRoundUpBytesToFrame(pGuestProps, cbCur);
257 *pcbBorrow = cbCurAligned - cbCur;
258
259 /* Do we need to split up the period? */
260 if (cbCurAligned <= cbMaxPeriod)
261 {
262 uint32_t cbHost = PDMAudioPropsFramesToBytes(pHostProps, PDMAudioPropsBytesToFrames(pGuestProps, cbCurAligned));
263 pStreamShared->State.aSchedule[idx].cbPeriod = cbHost;
264 pStreamShared->State.aSchedule[idx].cLoops = 1;
265 }
266 else
267 {
268 /* Reduce till we've below the threshold. */
269 uint32_t cbLoop = cbCurAligned;
270 do
271 cbLoop = cbCurAligned / 2;
272 while (cbLoop > cbMaxPeriod);
273 cbLoop = PDMAudioPropsRoundUpBytesToFrame(pGuestProps, cbLoop);
274
275 /* Complete the scheduling item. */
276 uint32_t cbHost = PDMAudioPropsFramesToBytes(pHostProps, PDMAudioPropsBytesToFrames(pGuestProps, cbLoop));
277 pStreamShared->State.aSchedule[idx].cbPeriod = cbHost;
278 pStreamShared->State.aSchedule[idx].cLoops = cbCurAligned / cbLoop;
279
280 /* If there is a remainder, add it as a separate entry (this is
281 why the schedule must be more than twice the size of the BDL).*/
282 cbCurAligned %= cbLoop;
283 if (cbCurAligned)
284 {
285 pStreamShared->State.aSchedule[idx + 1] = pStreamShared->State.aSchedule[idx];
286 idx++;
287 cbHost = PDMAudioPropsFramesToBytes(pHostProps, PDMAudioPropsBytesToFrames(pGuestProps, cbCurAligned));
288 pStreamShared->State.aSchedule[idx].cbPeriod = cbHost;
289 pStreamShared->State.aSchedule[idx].cLoops = 1;
290 }
291 }
292
293 /* Done. */
294 pStreamShared->State.cSchedule = (uint16_t)(idx + 1);
295
296 return VINF_SUCCESS;
297}
298
299/**
300 * Creates the DMA timer schedule for the stream
301 *
302 * This is called from the stream setup code.
303 *
304 * @returns VBox status code.
305 * @param pStreamShared The stream to create a schedule for. The BDL
306 * must be loaded.
307 * @param cSegments Number of BDL segments.
308 * @param cBufferIrqs Number of the BDLEs with IOC=1.
309 * @param cbTotal The total BDL length in guest bytes.
310 * @param cbMaxPeriod Max period in guest bytes. This is in case the
311 * guest want to play the whole "Der Ring des
312 * Nibelungen" cycle in one go.
313 * @param cTimerTicksPerSec The DMA timer frequency.
314 * @param pHostProps The host PCM properties.
315 * @param pGuestProps The guest PCM properties.
316 */
317static int hdaR3StreamCreateSchedule(PHDASTREAM pStreamShared, uint32_t cSegments, uint32_t cBufferIrqs, uint32_t cbTotal,
318 uint32_t cbMaxPeriod, uint64_t cTimerTicksPerSec,
319 PCPDMAUDIOPCMPROPS pHostProps, PCPDMAUDIOPCMPROPS pGuestProps)
320{
321 int rc;
322
323 /*
324 * Reset scheduling state.
325 */
326 RT_ZERO(pStreamShared->State.aSchedule);
327 pStreamShared->State.cSchedule = 0;
328 pStreamShared->State.cSchedulePrologue = 0;
329 pStreamShared->State.idxSchedule = 0;
330 pStreamShared->State.idxScheduleLoop = 0;
331
332 /*
333 * Do the basic schedule compilation.
334 */
335 uint32_t cPotentialPrologue = 0;
336 uint32_t cbBorrow = 0;
337 uint32_t cbCur = 0;
338 uint32_t cbMin = UINT32_MAX;
339 pStreamShared->State.aSchedule[0].idxFirst = 0;
340 for (uint32_t i = 0; i < cSegments; i++)
341 {
342 cbCur += pStreamShared->State.aBdl[i].cb;
343 if (pStreamShared->State.aBdl[i].cb < cbMin)
344 cbMin = pStreamShared->State.aBdl[i].cb;
345 if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
346 {
347 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur, cbMaxPeriod, i, pHostProps, pGuestProps, &cbBorrow);
348 ASSERT_GUEST_RC_RETURN(rc, rc);
349
350 if (cPotentialPrologue == 0)
351 cPotentialPrologue = pStreamShared->State.cSchedule;
352 cbCur = 0;
353 }
354 }
355 AssertLogRelMsgReturn(cbBorrow == 0, ("HDA: Internal scheduling error on stream #%u: cbBorrow=%#x cbTotal=%#x cbCur=%#x\n",
356 pStreamShared->u8SD, cbBorrow, cbTotal, cbCur),
357 VERR_INTERNAL_ERROR_3);
358
359 /*
360 * Deal with any loose ends.
361 */
362 if (cbCur && cBufferIrqs == 0)
363 {
364 /*
365 * No IOC. Vista ends up here, typically with three buffers configured.
366 *
367 * The perferred option here is to aim at processing one average BDLE with
368 * each DMA timer period, since that best matches how we update LPIB at
369 * present.
370 *
371 * The second alternative is to divide the whole span up into 3-4 periods
372 * to try increase our chances of keeping ahead of the guest. We may need
373 * to pick this if there are too few buffer descriptor or they are too small.
374 *
375 * However, what we probably should be doing is to do real DMA work whenever
376 * the guest reads a DMA related register (like LPIB) and just do 3-4 DMA
377 * timer periods, however we'll be postponing the DMA timer every time we
378 * return to ring-3 and signal the AIO, so in the end we'd probably not use
379 * the timer callback at all. (This is assuming a small shared per-stream
380 * buffer for keeping the DMA data in and that it's size will force a return
381 * to ring-3 often enough to keep the AIO thread going at a reasonable rate.)
382 */
383 Assert(cbCur == cbTotal);
384
385 /* Match the BDLEs 1:1 if there are 3 or more and that the smallest one
386 is at least 5ms big. */
387 if (cSegments >= 3 && PDMAudioPropsBytesToMilli(pGuestProps, cbMin) >= 5 /*ms*/)
388 {
389 for (uint32_t i = 0; i < cSegments; i++)
390 {
391 rc = hdaR3StreamAddScheduleItem(pStreamShared, pStreamShared->State.aBdl[i].cb, cbMaxPeriod,
392 i, pHostProps, pGuestProps, &cbBorrow);
393 ASSERT_GUEST_RC_RETURN(rc, rc);
394 }
395 }
396 /* Otherwise, just divide the work into 3 or 4 portions and hope for the best.
397 It seems, though, that this only really work for windows vista if we avoid
398 working accross buffer lines. */
399 /** @todo This can be simplified/relaxed/uncluttered if we do DMA work when LPIB
400 * is read, assuming ofc that LPIB is read before each buffer update. */
401 else
402 {
403 uint32_t const cPeriods = cSegments != 3 && PDMAudioPropsBytesToMilli(pGuestProps, cbCur) >= 4 * 5 /*ms*/
404 ? 4 : cSegments != 2 ? 3 : 2;
405 uint32_t const cbPeriod = PDMAudioPropsFloorBytesToFrame(pGuestProps, cbCur / cPeriods);
406 uint32_t iBdle = 0;
407 uint32_t offBdle = 0;
408 for (uint32_t iPeriod = 0; iPeriod < cPeriods; iPeriod++)
409 {
410 if (iPeriod + 1 < cPeriods)
411 {
412 offBdle += cbPeriod;
413 while (iBdle < cSegments && offBdle >= pStreamShared->State.aBdl[iBdle].cb)
414 offBdle -= pStreamShared->State.aBdl[iBdle++].cb;
415 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbPeriod, cbMaxPeriod, offBdle != 0 ? iBdle : iBdle - 1,
416 pHostProps, pGuestProps, &cbBorrow);
417 }
418 else
419 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur - iPeriod * cbPeriod, cbMaxPeriod, cSegments - 1,
420 pHostProps, pGuestProps, &cbBorrow);
421 ASSERT_GUEST_RC_RETURN(rc, rc);
422 }
423
424 }
425 Assert(cbBorrow == 0);
426 }
427 else if (cbCur)
428 {
429 /* The last BDLE didn't have IOC set, so we must continue processing
430 from the start till we hit one that has. */
431 uint32_t i;
432 for (i = 0; i < cSegments; i++)
433 {
434 cbCur += pStreamShared->State.aBdl[i].cb;
435 if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
436 break;
437 }
438 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur, cbMaxPeriod, i, pHostProps, pGuestProps, &cbBorrow);
439 ASSERT_GUEST_RC_RETURN(rc, rc);
440
441 /* The initial scheduling items covering the wrap around area are
442 considered a prologue and must not repeated later. */
443 Assert(cPotentialPrologue);
444 pStreamShared->State.cSchedulePrologue = (uint8_t)cPotentialPrologue;
445 }
446
447 /*
448 * If there is just one BDLE with IOC set, we have to make sure
449 * we've got at least two periods scheduled, otherwise there is
450 * a very good chance the guest will overwrite the start of the
451 * buffer before we ever get around to reading it.
452 */
453 if (cBufferIrqs == 1)
454 {
455 uint32_t i = pStreamShared->State.cSchedulePrologue;
456 Assert(i < pStreamShared->State.cSchedule);
457 if ( i + 1 == pStreamShared->State.cSchedule
458 && pStreamShared->State.aSchedule[i].cLoops == 1)
459 {
460 uint32_t const cbFirstHalf = PDMAudioPropsFloorBytesToFrame(pHostProps, pStreamShared->State.aSchedule[i].cbPeriod / 2);
461 uint32_t const cbOtherHalf = pStreamShared->State.aSchedule[i].cbPeriod - cbFirstHalf;
462 pStreamShared->State.aSchedule[i].cbPeriod = cbFirstHalf;
463 if (cbFirstHalf == cbOtherHalf)
464 pStreamShared->State.aSchedule[i].cLoops = 2;
465 else
466 {
467 pStreamShared->State.aSchedule[i + 1] = pStreamShared->State.aSchedule[i];
468 pStreamShared->State.aSchedule[i].cbPeriod = cbOtherHalf;
469 pStreamShared->State.cSchedule++;
470 }
471 }
472 }
473
474 /*
475 * Go over the schduling entries and calculate the timer ticks for each period.
476 */
477 LogRel2(("HDA: Stream #%u schedule: %u items, %u prologue\n",
478 pStreamShared->u8SD, pStreamShared->State.cSchedule, pStreamShared->State.cSchedulePrologue));
479 uint64_t const cbHostPerSec = PDMAudioPropsFramesToBytes(pHostProps, pHostProps->uHz);
480 for (uint32_t i = 0; i < pStreamShared->State.cSchedule; i++)
481 {
482 uint64_t const cTicks = ASMMultU64ByU32DivByU32(cTimerTicksPerSec, pStreamShared->State.aSchedule[i].cbPeriod,
483 cbHostPerSec);
484 AssertLogRelMsgReturn((uint32_t)cTicks == cTicks, ("cTicks=%RU64 (%#RX64)\n", cTicks, cTicks), VERR_INTERNAL_ERROR_4);
485 pStreamShared->State.aSchedule[i].cPeriodTicks = RT_MAX((uint32_t)cTicks, 16);
486 LogRel2(("HDA: #%u: %u ticks / %u bytes, %u loops, BDLE%u L %u\n", i, pStreamShared->State.aSchedule[i].cPeriodTicks,
487 pStreamShared->State.aSchedule[i].cbPeriod, pStreamShared->State.aSchedule[i].cLoops,
488 pStreamShared->State.aSchedule[i].idxFirst, pStreamShared->State.aSchedule[i].cEntries));
489 }
490
491 return VINF_SUCCESS;
492}
493
494
495/**
496 * Sets up ((re-)iniitalizes) an HDA stream.
497 *
498 * @returns VBox status code. VINF_NO_CHANGE if the stream does not need
499 * be set-up again because the stream's (hardware) parameters did
500 * not change.
501 * @param pDevIns The device instance.
502 * @param pThis The shared HDA device state (for HW register
503 * parameters).
504 * @param pStreamShared HDA stream to set up, shared portion.
505 * @param pStreamR3 HDA stream to set up, ring-3 portion.
506 * @param uSD Stream descriptor number to assign it.
507 */
508int hdaR3StreamSetUp(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD)
509{
510 /* This must be valid all times. */
511 AssertReturn(uSD < HDA_MAX_STREAMS, VERR_INVALID_PARAMETER);
512
513 /* These member can only change on data corruption, despite what the code does further down (bird). */
514 AssertReturn(pStreamShared->u8SD == uSD, VERR_WRONG_ORDER);
515 AssertReturn(pStreamR3->u8SD == uSD, VERR_WRONG_ORDER);
516
517 const uint64_t u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, uSD),
518 HDA_STREAM_REG(pThis, BDPU, uSD));
519 const uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, uSD);
520 const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, uSD);
521 const uint8_t u8FIFOS = HDA_STREAM_REG(pThis, FIFOS, uSD) + 1;
522 uint8_t u8FIFOW = hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, uSD));
523 const uint16_t u16FMT = HDA_STREAM_REG(pThis, FMT, uSD);
524
525 /* Is the bare minimum set of registers configured for the stream?
526 * If not, bail out early, as there's nothing to do here for us (yet). */
527 if ( !u64BDLBase
528 || !u16LVI
529 || !u32CBL
530 || !u8FIFOS
531 || !u8FIFOW
532 || !u16FMT)
533 {
534 LogFunc(("[SD%RU8] Registers not set up yet, skipping (re-)initialization\n", uSD));
535 return VINF_SUCCESS;
536 }
537
538 /*
539 * Convert the config to PDM PCM properties and configure the stream.
540 */
541 PPDMAUDIOSTREAMCFG pCfg = &pStreamShared->State.Cfg;
542 int rc = hdaR3SDFMTToPCMProps(u16FMT, &pCfg->Props);
543 if (RT_SUCCESS(rc))
544 pCfg->enmDir = hdaGetDirFromSD(uSD);
545 else
546 {
547 LogRelMax(32, ("HDA: Warning: Format 0x%x for stream #%RU8 not supported\n", HDA_STREAM_REG(pThis, FMT, uSD), uSD));
548 return rc;
549 }
550
551 ASSERT_GUEST_LOGREL_MSG_RETURN( PDMAudioPropsFrameSize(&pCfg->Props) > 0
552 && u32CBL % PDMAudioPropsFrameSize(&pCfg->Props) == 0,
553 ("CBL for stream #%RU8 does not align to frame size (u32CBL=%u cbFrameSize=%u)\n",
554 uSD, u32CBL, PDMAudioPropsFrameSize(&pCfg->Props)),
555 VERR_INVALID_PARAMETER);
556
557 /* Make sure the guest behaves regarding the stream's FIFO. */
558 ASSERT_GUEST_LOGREL_MSG_STMT(u8FIFOW <= u8FIFOS,
559 ("Guest tried setting a bigger FIFOW (%RU8) than FIFOS (%RU8), limiting\n", u8FIFOW, u8FIFOS),
560 u8FIFOW = u8FIFOS /* ASSUMES that u8FIFOS has been validated. */);
561
562 pStreamShared->u8SD = uSD;
563
564 /* Update all register copies so that we later know that something has changed. */
565 pStreamShared->u64BDLBase = u64BDLBase;
566 pStreamShared->u16LVI = u16LVI;
567 pStreamShared->u32CBL = u32CBL;
568 pStreamShared->u8FIFOS = u8FIFOS;
569 pStreamShared->u8FIFOW = u8FIFOW;
570 pStreamShared->u16FMT = u16FMT;
571
572 /* The the stream's name, based on the direction. */
573 switch (pCfg->enmDir)
574 {
575 case PDMAUDIODIR_IN:
576# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
577# error "Implement me!"
578# else
579 pCfg->enmPath = PDMAUDIOPATH_IN_LINE;
580 RTStrCopy(pCfg->szName, sizeof(pCfg->szName), "Line In");
581# endif
582 break;
583
584 case PDMAUDIODIR_OUT:
585 /* Destination(s) will be set in hdaR3AddStreamOut(),
586 * based on the channels / stream layout. */
587 break;
588
589 default:
590 AssertFailedReturn(VERR_NOT_SUPPORTED);
591 break;
592 }
593
594 LogRel2(("HDA: Stream #%RU8 DMA @ 0x%x (%RU32 bytes = %RU64ms total)\n", uSD, pStreamShared->u64BDLBase,
595 pStreamShared->u32CBL, PDMAudioPropsBytesToMilli(&pCfg->Props, pStreamShared->u32CBL)));
596
597 /*
598 * Load the buffer descriptor list.
599 *
600 * Section 3.6.2 states that "the BDL should not be modified unless the RUN
601 * bit is 0", so it should be within the specs to read it once here and not
602 * re-read any BDLEs later.
603 */
604 /* Reset BDL state. */
605 RT_ZERO(pStreamShared->State.aBdl);
606 pStreamShared->State.offCurBdle = 0;
607 pStreamShared->State.idxCurBdle = 0;
608
609 uint32_t /*const*/ cTransferFragments = (pStreamShared->u16LVI & 0xff) + 1;
610 if (cTransferFragments <= 1)
611 LogRel(("HDA: Warning: Stream #%RU8 transfer buffer count invalid: (%RU16)! Buggy guest audio driver!\n", uSD, pStreamShared->u16LVI));
612 AssertLogRelReturn(cTransferFragments <= RT_ELEMENTS(pStreamShared->State.aBdl), VERR_INTERNAL_ERROR_5);
613 pStreamShared->State.cBdles = cTransferFragments;
614
615 /* Load them. */
616 rc = PDMDevHlpPCIPhysRead(pDevIns, u64BDLBase, pStreamShared->State.aBdl,
617 sizeof(pStreamShared->State.aBdl[0]) * cTransferFragments);
618 AssertRC(rc);
619
620 /* Check what we just loaded. Refuse overly large buffer lists. */
621 uint64_t cbTotal = 0;
622 uint32_t cBufferIrqs = 0;
623 for (uint32_t i = 0; i < cTransferFragments; i++)
624 {
625 if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
626 cBufferIrqs++;
627 cbTotal += pStreamShared->State.aBdl[i].cb;
628 }
629 ASSERT_GUEST_STMT_RETURN(cbTotal < _2G,
630 LogRelMax(32, ("HDA: Error: Stream #%u is configured with an insane amount of buffer space - refusing do work with it: %RU64 (%#RX64) bytes.\n",
631 uSD, cbTotal, cbTotal)),
632 VERR_NOT_SUPPORTED);
633 ASSERT_GUEST_STMT_RETURN(cbTotal == u32CBL,
634 LogRelMax(32, ("HDA: Warning: Stream #%u has a mismatch between CBL and configured buffer space: %RU32 (%#RX32) vs %RU64 (%#RX64)\n",
635 uSD, u32CBL, u32CBL, cbTotal, cbTotal)),
636 VERR_NOT_SUPPORTED);
637
638 /*
639 * Create a DMA timer schedule.
640 */
641 /** @todo clean up this, pGuestProps and pHostProps are the same now. */
642 rc = hdaR3StreamCreateSchedule(pStreamShared, cTransferFragments, cBufferIrqs, (uint32_t)cbTotal,
643 PDMAudioPropsMilliToBytes(&pCfg->Props, 100 /** @todo make configurable */),
644 PDMDevHlpTimerGetFreq(pDevIns, pStreamShared->hTimer),
645 &pCfg->Props, &pCfg->Props);
646 if (RT_FAILURE(rc))
647 return rc;
648
649 pStreamShared->State.cbTransferSize = pStreamShared->State.aSchedule[0].cbPeriod;
650
651 /*
652 * Calculate the transfer Hz for use in the circular buffer calculation.
653 */
654 uint32_t cbMaxPeriod = 0;
655 uint32_t cbMinPeriod = UINT32_MAX;
656 uint32_t cPeriods = 0;
657 for (uint32_t i = 0; i < pStreamShared->State.cSchedule; i++)
658 {
659 uint32_t cbPeriod = pStreamShared->State.aSchedule[i].cbPeriod;
660 cbMaxPeriod = RT_MAX(cbMaxPeriod, cbPeriod);
661 cbMinPeriod = RT_MIN(cbMinPeriod, cbPeriod);
662 cPeriods += pStreamShared->State.aSchedule[i].cLoops;
663 }
664 uint64_t const cbTransferPerSec = RT_MAX(PDMAudioPropsFramesToBytes(&pCfg->Props, pCfg->Props.uHz),
665 4096 /* zero div prevention: min is 6kHz, picked 4k in case I'm mistaken */);
666 unsigned uTransferHz = cbTransferPerSec * 1000 / cbMaxPeriod;
667 LogRel2(("HDA: Stream #%RU8 needs a %u.%03u Hz timer rate (period: %u..%u host bytes)\n",
668 uSD, uTransferHz / 1000, uTransferHz % 1000, cbMinPeriod, cbMaxPeriod));
669 uTransferHz /= 1000;
670
671 if (uTransferHz > 400) /* Anything above 400 Hz looks fishy -- tell the user. */
672 LogRelMax(32, ("HDA: Warning: Calculated transfer Hz rate for stream #%RU8 looks incorrect (%u), please re-run with audio debug mode and report a bug\n",
673 uSD, uTransferHz));
674
675 pStreamShared->State.cbAvgTransfer = (uint32_t)(cbTotal + cPeriods - 1) / cPeriods;
676
677 /* For input streams we must determin a pre-buffering requirement.
678 We use the initial delay as a basis here, though we must have at
679 least two max periods worth of data queued up due to the way we
680 work the AIO thread. */
681 pStreamShared->State.fInputPreBuffered = false;
682 pStreamShared->State.cbInputPreBuffer = PDMAudioPropsMilliToBytes(&pCfg->Props, pThis->msInitialDelay);
683 pStreamShared->State.cbInputPreBuffer = RT_MIN(cbMaxPeriod * 2, pStreamShared->State.cbInputPreBuffer);
684
685 /*
686 * Set up data transfer stuff.
687 */
688
689 /* Assign the global device rate to the stream I/O timer as default. */
690 pStreamShared->State.uTimerIoHz = pThis->uTimerHz;
691 ASSERT_GUEST_LOGREL_MSG_STMT(pStreamShared->State.uTimerIoHz,
692 ("I/O timer Hz rate for stream #%RU8 is invalid\n", uSD),
693 pStreamShared->State.uTimerIoHz = HDA_TIMER_HZ_DEFAULT);
694
695 /* Set I/O scheduling hint for the backends. */
696 /** @todo r=bird: derive this from the schedule instead of using the
697 * uTimerIoHz, as that's almost pure non-sense now. */
698 pCfg->Device.cMsSchedulingHint = RT_MS_1SEC / pStreamShared->State.uTimerIoHz;
699 LogRel2(("HDA: Stream #%RU8 set scheduling hint for the backends to %RU32ms\n", uSD, pCfg->Device.cMsSchedulingHint));
700
701
702 /* Make sure to also update the stream's DMA counter (based on its current LPIB value). */
703 /** @todo r=bird: We use LPIB as-is here, so if it's not zero we have to
704 * locate the right place in the schedule and whatnot... */
705 if (HDA_STREAM_REG(pThis, LPIB, uSD) != 0)
706 LogRel2(("HDA: Warning! Stream #%RU8 is set up with LPIB=%#RX32 instead of zero!\n", uSD, HDA_STREAM_REG(pThis, LPIB, uSD)));
707 hdaStreamSetPositionAbs(pStreamShared, pDevIns, pThis, HDA_STREAM_REG(pThis, LPIB, uSD));
708
709# ifdef LOG_ENABLED
710 hdaR3BDLEDumpAll(pDevIns, pThis, pStreamShared->u64BDLBase, pStreamShared->u16LVI + 1);
711# endif
712
713 /*
714 * Set up internal ring buffer.
715 */
716
717 /* (Re-)Allocate the stream's internal DMA buffer,
718 * based on the timing *and* PCM properties we just got above. */
719 if (pStreamR3->State.pCircBuf)
720 {
721 RTCircBufDestroy(pStreamR3->State.pCircBuf);
722 pStreamR3->State.pCircBuf = NULL;
723 pStreamR3->State.StatDmaBufSize = 0;
724 pStreamR3->State.StatDmaBufUsed = 0;
725 }
726 pStreamShared->State.offWrite = 0;
727 pStreamShared->State.offRead = 0;
728
729 /*
730 * The default internal ring buffer size must be:
731 *
732 * - Large enough for at least three periodic DMA transfers.
733 *
734 * It is critically important that we don't experience underruns
735 * in the DMA OUT code, because it will cause the buffer processing
736 * to get skewed and possibly overlap with what the guest is updating.
737 * At the time of writing (2021-03-05) there is no code for getting
738 * back into sync there.
739 *
740 * - Large enough for at least three I/O scheduling hints.
741 *
742 * We want to lag behind a DMA period or two, but there must be
743 * sufficent space for the AIO thread to get schedule and shuffle
744 * data thru the mixer and onto the host audio hardware.
745 *
746 * - Both above with plenty to spare.
747 *
748 * So, just take the longest of the two periods and multipling it by 6.
749 * We aren't not talking about very large base buffers heres, so size isn't
750 * an issue.
751 *
752 * Note: Use pCfg->Props as PCM properties here, as we only want to store the
753 * samples we actually need, in other words, skipping the interleaved
754 * channels we don't support / need to save space.
755 */
756 uint32_t msCircBuf = RT_MS_1SEC * 6 / RT_MIN(uTransferHz, pStreamShared->State.uTimerIoHz);
757 msCircBuf = RT_MAX(msCircBuf, pThis->msInitialDelay + RT_MS_1SEC * 6 / uTransferHz);
758
759 uint32_t cbCircBuf = PDMAudioPropsMilliToBytes(&pCfg->Props, msCircBuf);
760 LogRel2(("HDA: Stream #%RU8 default ring buffer size is %RU32 bytes / %RU64 ms\n",
761 uSD, cbCircBuf, PDMAudioPropsBytesToMilli(&pCfg->Props, cbCircBuf)));
762
763 uint32_t msCircBufCfg = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? pThis->cMsCircBufIn : pThis->cMsCircBufOut;
764 if (msCircBufCfg) /* Anything set via CFGM? */
765 {
766 cbCircBuf = PDMAudioPropsMilliToBytes(&pCfg->Props, msCircBufCfg);
767 LogRel2(("HDA: Stream #%RU8 is using a custom ring buffer size of %RU32 bytes / %RU64 ms\n",
768 uSD, cbCircBuf, PDMAudioPropsBytesToMilli(&pCfg->Props, cbCircBuf)));
769 }
770
771 /* Serious paranoia: */
772 ASSERT_GUEST_LOGREL_MSG_STMT(cbCircBuf % PDMAudioPropsFrameSize(&pCfg->Props) == 0,
773 ("Ring buffer size (%RU32) for stream #%RU8 not aligned to the (host) frame size (%RU8)\n",
774 cbCircBuf, uSD, PDMAudioPropsFrameSize(&pCfg->Props)),
775 rc = VERR_INVALID_PARAMETER);
776 ASSERT_GUEST_LOGREL_MSG_STMT(cbCircBuf, ("Ring buffer size for stream #%RU8 is invalid\n", uSD),
777 rc = VERR_INVALID_PARAMETER);
778 if (RT_SUCCESS(rc))
779 {
780 rc = RTCircBufCreate(&pStreamR3->State.pCircBuf, cbCircBuf);
781 if (RT_SUCCESS(rc))
782 {
783 pStreamR3->State.StatDmaBufSize = cbCircBuf;
784
785 /*
786 * Forward the timer frequency hint to TM as well for better accuracy on
787 * systems w/o preemption timers (also good for 'info timers').
788 */
789 PDMDevHlpTimerSetFrequencyHint(pDevIns, pStreamShared->hTimer, uTransferHz);
790 }
791 }
792
793 if (RT_FAILURE(rc))
794 LogRelMax(32, ("HDA: Initializing stream #%RU8 failed with %Rrc\n", uSD, rc));
795
796# ifdef VBOX_WITH_DTRACE
797 VBOXDD_HDA_STREAM_SETUP((uint32_t)uSD, rc, pStreamShared->State.Cfg.Props.uHz,
798 pStreamShared->State.aSchedule[pStreamShared->State.cSchedule - 1].cPeriodTicks,
799 pStreamShared->State.aSchedule[pStreamShared->State.cSchedule - 1].cbPeriod);
800# endif
801 return rc;
802}
803
804/**
805 * Resets an HDA stream.
806 *
807 * @param pThis The shared HDA device state.
808 * @param pThisCC The ring-3 HDA device state.
809 * @param pStreamShared HDA stream to reset (shared).
810 * @param pStreamR3 HDA stream to reset (ring-3).
811 * @param uSD Stream descriptor (SD) number to use for this stream.
812 */
813void hdaR3StreamReset(PHDASTATE pThis, PHDASTATER3 pThisCC, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD)
814{
815 LogFunc(("[SD%RU8] Reset\n", uSD));
816
817 /*
818 * Assert some sanity.
819 */
820 AssertPtr(pThis);
821 AssertPtr(pStreamShared);
822 AssertPtr(pStreamR3);
823 Assert(uSD < HDA_MAX_STREAMS);
824 Assert(pStreamShared->u8SD == uSD);
825 Assert(pStreamR3->u8SD == uSD);
826 AssertMsg(!pStreamShared->State.fRunning, ("[SD%RU8] Cannot reset stream while in running state\n", uSD));
827
828 /*
829 * Set reset state.
830 */
831 Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false); /* No nested calls. */
832 ASMAtomicXchgBool(&pStreamShared->State.fInReset, true);
833
834 /*
835 * Second, initialize the registers.
836 */
837 /* See 6.2.33: Clear on reset. */
838 HDA_STREAM_REG(pThis, STS, uSD) = 0;
839 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
840 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
841 HDA_STREAM_REG(pThis, CTL, uSD) = HDA_SDCTL_TP | (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_SDCTL_SRST);
842 /* ICH6 defines default values (120 bytes for input and 192 bytes for output descriptors) of FIFO size. 18.2.39. */
843 HDA_STREAM_REG(pThis, FIFOS, uSD) = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? HDA_SDIFIFO_120B : HDA_SDOFIFO_192B;
844 /* See 18.2.38: Always defaults to 0x4 (32 bytes). */
845 HDA_STREAM_REG(pThis, FIFOW, uSD) = HDA_SDFIFOW_32B;
846 HDA_STREAM_REG(pThis, LPIB, uSD) = 0;
847 HDA_STREAM_REG(pThis, CBL, uSD) = 0;
848 HDA_STREAM_REG(pThis, LVI, uSD) = 0;
849 HDA_STREAM_REG(pThis, FMT, uSD) = 0;
850 HDA_STREAM_REG(pThis, BDPU, uSD) = 0;
851 HDA_STREAM_REG(pThis, BDPL, uSD) = 0;
852
853# ifdef HDA_USE_DMA_ACCESS_HANDLER
854 hdaR3StreamUnregisterDMAHandlers(pThis, pStream);
855# endif
856
857 /* Assign the default mixer sink to the stream. */
858 pStreamR3->pMixSink = hdaR3GetDefaultSink(pThisCC, uSD);
859 if (pStreamR3->State.pAioRegSink)
860 {
861 int rc2 = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
862 AssertRC(rc2);
863 pStreamR3->State.pAioRegSink = NULL;
864 }
865
866 /* Reset transfer stuff. */
867 pStreamShared->State.cTransferPendingInterrupts = 0;
868 pStreamShared->State.tsTransferLast = 0;
869 pStreamShared->State.tsTransferNext = 0;
870
871 /* Initialize timestamps. */
872 pStreamShared->State.tsLastTransferNs = 0;
873 pStreamShared->State.tsLastReadNs = 0;
874 pStreamShared->State.tsAioDelayEnd = UINT64_MAX;
875 pStreamShared->State.tsStart = 0;
876
877 RT_ZERO(pStreamShared->State.aBdl);
878 RT_ZERO(pStreamShared->State.aSchedule);
879 pStreamShared->State.offCurBdle = 0;
880 pStreamShared->State.cBdles = 0;
881 pStreamShared->State.idxCurBdle = 0;
882 pStreamShared->State.cSchedulePrologue = 0;
883 pStreamShared->State.cSchedule = 0;
884 pStreamShared->State.idxSchedule = 0;
885 pStreamShared->State.idxScheduleLoop = 0;
886 pStreamShared->State.fInputPreBuffered = false;
887
888 if (pStreamR3->State.pCircBuf)
889 RTCircBufReset(pStreamR3->State.pCircBuf);
890 pStreamShared->State.offWrite = 0;
891 pStreamShared->State.offRead = 0;
892
893# ifdef DEBUG
894 pStreamR3->Dbg.cReadsTotal = 0;
895 pStreamR3->Dbg.cbReadTotal = 0;
896 pStreamR3->Dbg.tsLastReadNs = 0;
897 pStreamR3->Dbg.cWritesTotal = 0;
898 pStreamR3->Dbg.cbWrittenTotal = 0;
899 pStreamR3->Dbg.cWritesHz = 0;
900 pStreamR3->Dbg.cbWrittenHz = 0;
901 pStreamR3->Dbg.tsWriteSlotBegin = 0;
902# endif
903
904 /* Report that we're done resetting this stream. */
905 HDA_STREAM_REG(pThis, CTL, uSD) = 0;
906
907# ifdef VBOX_WITH_DTRACE
908 VBOXDD_HDA_STREAM_RESET((uint32_t)uSD);
909# endif
910 LogFunc(("[SD%RU8] Reset\n", uSD));
911
912 /* Exit reset mode. */
913 ASMAtomicXchgBool(&pStreamShared->State.fInReset, false);
914}
915
916/**
917 * Enables or disables an HDA audio stream.
918 *
919 * @returns VBox status code.
920 * @param pThis The shared HDA device state.
921 * @param pStreamShared HDA stream to enable or disable - shared bits.
922 * @param pStreamR3 HDA stream to enable or disable - ring-3 bits.
923 * @param fEnable Whether to enable or disble the stream.
924 */
925int hdaR3StreamEnable(PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, bool fEnable)
926{
927 AssertPtr(pStreamR3);
928 AssertPtr(pStreamShared);
929
930 LogFunc(("[SD%RU8] fEnable=%RTbool, pMixSink=%p\n", pStreamShared->u8SD, fEnable, pStreamR3->pMixSink));
931
932 /* First, enable or disable the stream and the stream's sink, if any. */
933 int rc = VINF_SUCCESS;
934 PAUDMIXSINK const pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
935 if (pSink)
936 {
937 if (fEnable)
938 {
939 if (pStreamR3->State.pAioRegSink != pSink)
940 {
941 if (pStreamR3->State.pAioRegSink)
942 {
943 rc = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
944 AssertRC(rc);
945 }
946 rc = AudioMixerSinkAddUpdateJob(pSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3,
947 pStreamShared->State.Cfg.Device.cMsSchedulingHint);
948 AssertLogRelRC(rc);
949 pStreamR3->State.pAioRegSink = RT_SUCCESS(rc) ? pSink : NULL;
950 }
951 rc = AudioMixerSinkStart(pSink);
952 }
953 else
954 rc = AudioMixerSinkDrainAndStop(pSink,
955 pStreamR3->State.pCircBuf ? (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf) : 0);
956 }
957 if ( RT_SUCCESS(rc)
958 && fEnable
959 && pStreamR3->Dbg.Runtime.fEnabled)
960 {
961 Assert(AudioHlpPcmPropsAreValid(&pStreamShared->State.Cfg.Props));
962
963 if (fEnable)
964 {
965 if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileStream))
966 {
967 int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileStream, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
968 &pStreamShared->State.Cfg.Props);
969 AssertRC(rc2);
970 }
971
972 if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileDMARaw))
973 {
974 int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileDMARaw, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
975 &pStreamShared->State.Cfg.Props);
976 AssertRC(rc2);
977 }
978
979 if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileDMAMapped))
980 {
981 int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileDMAMapped, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
982 &pStreamShared->State.Cfg.Props);
983 AssertRC(rc2);
984 }
985 }
986 }
987
988 if (RT_SUCCESS(rc))
989 {
990 if (fEnable)
991 pStreamShared->State.tsTransferLast = 0; /* Make sure it's not stale and messes up WALCLK calculations. */
992 pStreamShared->State.fRunning = fEnable;
993
994 /*
995 * Set the FIFORDY bit when we start running and clear it when stopping.
996 *
997 * This prevents Linux from timing out in snd_hdac_stream_sync when starting
998 * a stream. Technically, Linux also uses the SSYNC feature there, but we
999 * can get away with just setting the FIFORDY bit for now.
1000 */
1001 if (fEnable)
1002 HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) |= HDA_SDSTS_FIFORDY;
1003 else
1004 HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) &= ~HDA_SDSTS_FIFORDY;
1005 }
1006
1007 LogFunc(("[SD%RU8] rc=%Rrc\n", pStreamShared->u8SD, rc));
1008 return rc;
1009}
1010
1011/**
1012 * Marks the stream as started.
1013 *
1014 * Used after the stream has been enabled and the DMA timer has been armed.
1015 */
1016void hdaR3StreamMarkStarted(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint64_t tsNow)
1017{
1018 pStreamShared->State.tsLastReadNs = RTTimeNanoTS();
1019 pStreamShared->State.tsStart = tsNow;
1020 pStreamShared->State.tsAioDelayEnd = tsNow + PDMDevHlpTimerFromMilli(pDevIns, pStreamShared->hTimer, pThis->msInitialDelay);
1021 Log3Func(("#%u: tsStart=%RU64 tsAioDelayEnd=%RU64 tsLastReadNs=%RU64\n", pStreamShared->u8SD,
1022 pStreamShared->State.tsStart, pStreamShared->State.tsAioDelayEnd, pStreamShared->State.tsLastReadNs));
1023
1024}
1025
1026/**
1027 * Marks the stream as stopped.
1028 */
1029void hdaR3StreamMarkStopped(PHDASTREAM pStreamShared)
1030{
1031 Log3Func(("#%u\n", pStreamShared->u8SD));
1032 pStreamShared->State.tsAioDelayEnd = UINT64_MAX;
1033}
1034
1035#endif /* IN_RING3 */
1036
1037/**
1038 * Updates an HDA stream's current read or write buffer position (depending on the stream type) by
1039 * setting its associated LPIB register and DMA position buffer (if enabled) to an absolute value.
1040 *
1041 * @param pStreamShared HDA stream to update read / write position for (shared).
1042 * @param pDevIns The device instance.
1043 * @param pThis The shared HDA device state.
1044 * @param uLPIB Absolute position (in bytes) to set current read / write position to.
1045 */
1046static void hdaStreamSetPositionAbs(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uLPIB)
1047{
1048 AssertPtrReturnVoid(pStreamShared);
1049 AssertMsgStmt(uLPIB <= pStreamShared->u32CBL, ("%#x\n", uLPIB), uLPIB = pStreamShared->u32CBL);
1050
1051 Log3Func(("[SD%RU8] LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n", pStreamShared->u8SD, uLPIB, pThis->fDMAPosition));
1052
1053 /* Update LPIB in any case. */
1054 HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) = uLPIB;
1055
1056 /* Do we need to tell the current DMA position? */
1057 if (pThis->fDMAPosition)
1058 {
1059 /*
1060 * Linux switched to using the position buffers some time during 2.6.x.
1061 * 2.6.12 used LPIB, 2.6.17 defaulted to DMA position buffers, between
1062 * the two version things were being changing quite a bit.
1063 *
1064 * Since 2.6.17, they will treat a zero DMA position value during the first
1065 * period/IRQ as reason to fall back to LPIB mode (see azx_position_ok in
1066 * 2.6.27+, and azx_pcm_pointer before that). They later also added
1067 * UINT32_MAX to the values causing same.
1068 *
1069 * Since 2.6.35 azx_position_ok will read the wall clock register before
1070 * determining the position.
1071 */
1072 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns,
1073 pThis->u64DPBase + (pStreamShared->u8SD * 2 * sizeof(uint32_t)),
1074 (void *)&uLPIB, sizeof(uint32_t));
1075 AssertRC(rc2);
1076 }
1077}
1078
1079
1080#if defined(IN_RING3) || defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA)
1081/**
1082 * Updates an HDA stream's current read or write buffer position (depending on the stream type) by
1083 * adding a value to its associated LPIB register and DMA position buffer (if enabled).
1084 *
1085 * @note Handles automatic CBL wrap-around.
1086 *
1087 * @param pStreamShared HDA stream to update read / write position for (shared).
1088 * @param pDevIns The device instance.
1089 * @param pThis The shared HDA device state.
1090 * @param cbToAdd Position (in bytes) to add to the current read / write position.
1091 */
1092static void hdaStreamSetPositionAdd(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t cbToAdd)
1093{
1094 if (cbToAdd) /* No need to update anything if 0. */
1095 {
1096 uint32_t const uCBL = pStreamShared->u32CBL;
1097 if (uCBL) /* paranoia */
1098 {
1099 uint32_t uNewLpid = HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) + cbToAdd;
1100# if 1 /** @todo r=bird: this is wrong according to the spec */
1101 uNewLpid %= uCBL;
1102# else
1103 /* The spec says it goes to CBL then wraps arpimd to 1, not back to zero. See 3.3.37. */
1104 if (uNewLpid > uCBL)
1105 uNewLpid %= uCBL;
1106# endif
1107 hdaStreamSetPositionAbs(pStreamShared, pDevIns, pThis, uNewLpid);
1108 }
1109 }
1110}
1111#endif /* IN_RING3 || VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
1112
1113#ifdef IN_RING3
1114
1115/**
1116 * Retrieves the available size of (buffered) audio data (in bytes) of a given HDA stream.
1117 *
1118 * @returns Available data (in bytes).
1119 * @param pStreamR3 HDA stream to retrieve size for (ring-3).
1120 */
1121static uint32_t hdaR3StreamGetUsed(PHDASTREAMR3 pStreamR3)
1122{
1123 AssertPtrReturn(pStreamR3, 0);
1124
1125 if (pStreamR3->State.pCircBuf)
1126 return (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1127 return 0;
1128}
1129
1130/**
1131 * Retrieves the free size of audio data (in bytes) of a given HDA stream.
1132 *
1133 * @returns Free data (in bytes).
1134 * @param pStreamR3 HDA stream to retrieve size for (ring-3).
1135 */
1136static uint32_t hdaR3StreamGetFree(PHDASTREAMR3 pStreamR3)
1137{
1138 AssertPtrReturn(pStreamR3, 0);
1139
1140 if (pStreamR3->State.pCircBuf)
1141 return (uint32_t)RTCircBufFree(pStreamR3->State.pCircBuf);
1142 return 0;
1143}
1144
1145#endif /* IN_RING3 */
1146
1147/**
1148 * Get the current address and number of bytes left in the current BDLE.
1149 *
1150 * @returns The current physical address.
1151 * @param pStreamShared The stream to check.
1152 * @param pcbLeft The number of bytes left at the returned address.
1153 */
1154DECLINLINE(RTGCPHYS) hdaStreamDmaBufGet(PHDASTREAM pStreamShared, uint32_t *pcbLeft)
1155{
1156 uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1157 AssertStmt(idxBdle < pStreamShared->State.cBdles, idxBdle = 0);
1158
1159 uint32_t const cbCurBdl = pStreamShared->State.aBdl[idxBdle].cb;
1160 uint32_t offCurBdle = pStreamShared->State.offCurBdle;
1161 AssertStmt(pStreamShared->State.offCurBdle <= cbCurBdl, offCurBdle = cbCurBdl);
1162
1163 *pcbLeft = cbCurBdl - offCurBdle;
1164 return pStreamShared->State.aBdl[idxBdle].GCPhys + offCurBdle;
1165}
1166
1167/**
1168 * Get the size of the current BDLE.
1169 *
1170 * @returns The size (in bytes).
1171 * @param pStreamShared The stream to check.
1172 */
1173DECLINLINE(RTGCPHYS) hdaStreamDmaBufGetSize(PHDASTREAM pStreamShared)
1174{
1175 uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1176 AssertStmt(idxBdle < pStreamShared->State.cBdles, idxBdle = 0);
1177 return pStreamShared->State.aBdl[idxBdle].cb;
1178}
1179
1180/**
1181 * Checks if the current BDLE is completed.
1182 *
1183 * @retval true if complete
1184 * @retval false if not.
1185 * @param pStreamShared The stream to check.
1186 */
1187DECLINLINE(bool) hdaStreamDmaBufIsComplete(PHDASTREAM pStreamShared)
1188{
1189 uint8_t const idxBdle = pStreamShared->State.idxCurBdle;
1190 AssertReturn(idxBdle < pStreamShared->State.cBdles, true);
1191
1192 uint32_t const cbCurBdl = pStreamShared->State.aBdl[idxBdle].cb;
1193 uint32_t const offCurBdle = pStreamShared->State.offCurBdle;
1194 Assert(offCurBdle <= cbCurBdl);
1195 return offCurBdle >= cbCurBdl;
1196}
1197
1198/**
1199 * Checks if the current BDLE needs a completion IRQ.
1200 *
1201 * @retval true if IRQ is needed.
1202 * @retval false if not.
1203 * @param pStreamShared The stream to check.
1204 */
1205DECLINLINE(bool) hdaStreamDmaBufNeedsIrq(PHDASTREAM pStreamShared)
1206{
1207 uint8_t const idxBdle = pStreamShared->State.idxCurBdle;
1208 AssertReturn(idxBdle < pStreamShared->State.cBdles, false);
1209 return (pStreamShared->State.aBdl[idxBdle].fFlags & HDA_BDLE_F_IOC) != 0;
1210}
1211
1212/**
1213 * Advances the DMA engine to the next BDLE.
1214 *
1215 * @param pStreamShared The stream which DMA engine is to be updated.
1216 */
1217DECLINLINE(void) hdaStreamDmaBufAdvanceToNext(PHDASTREAM pStreamShared)
1218{
1219 uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1220 Assert(pStreamShared->State.offCurBdle == pStreamShared->State.aBdl[idxBdle].cb);
1221
1222 if (idxBdle < pStreamShared->State.cBdles - 1)
1223 idxBdle++;
1224 else
1225 idxBdle = 0;
1226 pStreamShared->State.idxCurBdle = idxBdle;
1227 pStreamShared->State.offCurBdle = 0;
1228}
1229
1230#ifdef IN_RING3
1231
1232/**
1233 * Common do-DMA prologue code.
1234 *
1235 * @retval true if DMA processing can take place
1236 * @retval false if caller should return immediately.
1237 * @param pThis The shared HDA device state.
1238 * @param pStreamShared HDA stream to update (shared).
1239 * @param pStreamR3 HDA stream to update (ring-3).
1240 * @param uSD The stream ID (for asserting).
1241 * @param tsNowNs The current RTTimeNano() value.
1242 * @param pszFunction The function name (for logging).
1243 */
1244DECLINLINE(bool) hdaR3StreamDoDmaPrologue(PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD,
1245 uint64_t tsNowNs, const char *pszFunction)
1246{
1247 RT_NOREF(uSD, pszFunction);
1248
1249 /*
1250 * Check if we should skip town...
1251 */
1252 /* Stream not running (anymore)? */
1253 if (pStreamShared->State.fRunning)
1254 { /* likely */ }
1255 else
1256 {
1257 Log3(("%s: [SD%RU8] Not running, skipping transfer\n", pszFunction, uSD));
1258 return false;
1259 }
1260
1261 if (!(HDA_STREAM_REG(pThis, STS, uSD) & HDA_SDSTS_BCIS))
1262 { /* likely */ }
1263 else
1264 {
1265 /** @todo r=bird: This is a bit fishy. We should make effort the reschedule
1266 * the transfer immediately after the guest clears the interrupt.
1267 * The same fishy code is present in AC'97 with just a little
1268 * explanation as here, see @bugref{9890#c95}.
1269 *
1270 * The reasoning is probably that the developer noticed some windows
1271 * versions don't like having their BCIS interrupts bundled. There were
1272 * comments to that effect elsewhere, probably as a result of a fixed
1273 * uTimerHz approach to DMA scheduling. However, pausing DMA for a
1274 * period isn't going to help us with the host backends, as they don't
1275 * pause and will want samples ASAP. So, we should at least unpause
1276 * DMA as quickly as we possible when BCIS is cleared. We might even
1277 * not skip it iff the DMA work here doesn't involve raising any IOC,
1278 * which is possible although unlikely. */
1279 Log3(("%s: [SD%RU8] BCIS bit set, skipping transfer\n", pszFunction, uSD));
1280 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaSkippedPendingBcis);
1281 Log(("%s: [SD%RU8] BCIS bit set, skipping transfer\n", pszFunction, uSD));
1282# ifdef HDA_STRICT
1283 /* Timing emulation bug or guest is misbehaving -- let me know. */
1284 AssertMsgFailed(("%s: BCIS bit for stream #%RU8 still set when it shouldn't\n", pszFunction, uSD));
1285# endif
1286 return false;
1287 }
1288
1289 /*
1290 * Stream sanity checks.
1291 */
1292 /* Register sanity checks. */
1293 Assert(uSD < HDA_MAX_STREAMS);
1294 Assert(pStreamShared->u64BDLBase);
1295 Assert(pStreamShared->u32CBL);
1296 Assert(pStreamShared->u8FIFOS);
1297
1298 /* State sanity checks. */
1299 Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false);
1300 Assert(ASMAtomicReadBool(&pStreamShared->State.fRunning));
1301
1302 /*
1303 * Some timestamp stuff for logging/debugging.
1304 */
1305 /*const uint64_t tsNowNs = RTTimeNanoTS();*/
1306 Log3(("%s: [SD%RU8] tsDeltaNs=%'RU64 ns\n", pszFunction, uSD, tsNowNs - pStreamShared->State.tsLastTransferNs));
1307 pStreamShared->State.tsLastTransferNs = tsNowNs;
1308
1309 return true;
1310}
1311
1312/**
1313 * Common do-DMA epilogue.
1314 *
1315 * @param pDevIns The device instance.
1316 * @param pStreamShared The HDA stream (shared).
1317 * @param pStreamR3 The HDA stream (ring-3).
1318 */
1319DECLINLINE(void) hdaR3StreamDoDmaEpilogue(PPDMDEVINS pDevIns, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
1320{
1321 /*
1322 * We must update this in the epilogue rather than in the prologue
1323 * as it is used for WALCLK calculation and we must make sure the
1324 * guest doesn't think we've processed the current period till we
1325 * actually have.
1326 */
1327 pStreamShared->State.tsTransferLast = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer);
1328
1329 /*
1330 * Update the buffer statistics.
1331 */
1332 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1333}
1334
1335#endif /* IN_RING3 */
1336
1337/**
1338 * Completes a BDLE at the end of a DMA loop iteration, if possible.
1339 *
1340 * @retval true if buffer completed and new loaded.
1341 * @retval false if buffer not completed.
1342 * @param pDevIns The device instance.
1343 * @param pThis The shared HDA device state.
1344 * @param pStreamShared HDA stream to update (shared).
1345 * @param pszFunction The function name (for logging).
1346 */
1347DECLINLINE(bool) hdaStreamDoDmaMaybeCompleteBuffer(PPDMDEVINS pDevIns, PHDASTATE pThis,
1348 PHDASTREAM pStreamShared, const char *pszFunction)
1349{
1350 RT_NOREF(pszFunction);
1351
1352 /*
1353 * Is the buffer descriptor complete.
1354 */
1355 if (hdaStreamDmaBufIsComplete(pStreamShared))
1356 {
1357 Log3(("%s: [SD%RU8] Completed BDLE%u %#RX64 LB %#RX32 fFlags=%#x\n", pszFunction, pStreamShared->u8SD,
1358 pStreamShared->State.idxCurBdle, pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].GCPhys,
1359 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].cb,
1360 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].fFlags));
1361
1362#if 0 /* Moved to the transfer loops */
1363 /*
1364 * Update the stream's current position.
1365 *
1366 * Do this as accurate and close to the actual data transfer as possible.
1367 * All guests rely on this, depending on the mechanism they use (LPIB register or DMA counters).
1368 *
1369 * Note for Windows 10: The OS' driver is *very* picky about *when* the (DMA) positions get updated!
1370 * Not doing this at the right time will result in ugly sound crackles!
1371 */
1372 hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, hdaStreamDmaBufGetSize(pStreamShared));
1373#endif
1374
1375 /* Does the current BDLE require an interrupt to be sent? */
1376 if (hdaStreamDmaBufNeedsIrq(pStreamShared))
1377 {
1378 /* If the IOCE ("Interrupt On Completion Enable") bit of the SDCTL
1379 register is set we need to generate an interrupt. */
1380 if (HDA_STREAM_REG(pThis, CTL, pStreamShared->u8SD) & HDA_SDCTL_IOCE)
1381 {
1382 /* Assert the interrupt before actually fetching the next BDLE below. */
1383 pStreamShared->State.cTransferPendingInterrupts = 1;
1384 Log3(("%s: [SD%RU8] Scheduling interrupt\n", pszFunction, pStreamShared->u8SD));
1385
1386 /* Trigger an interrupt first and let hdaRegWriteSDSTS() deal with
1387 * ending / beginning of a period. */
1388 /** @todo r=bird: What does the above comment mean? */
1389 HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) |= HDA_SDSTS_BCIS;
1390 HDA_PROCESS_INTERRUPT(pDevIns, pThis);
1391 }
1392 }
1393
1394 /*
1395 * Advance to the next BDLE.
1396 */
1397 hdaStreamDmaBufAdvanceToNext(pStreamShared);
1398 return true;
1399 }
1400
1401 Log3(("%s: [SD%RU8] Incomplete BDLE%u %#RX64 LB %#RX32 fFlags=%#x: off=%#RX32\n", pszFunction, pStreamShared->u8SD,
1402 pStreamShared->State.idxCurBdle, pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].GCPhys,
1403 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].cb,
1404 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].fFlags, pStreamShared->State.offCurBdle));
1405 return false;
1406}
1407
1408#ifdef IN_RING3
1409
1410/**
1411 * Does DMA transfer for an HDA input stream.
1412 *
1413 * Reads audio data from the HDA stream's internal DMA buffer and writing to
1414 * guest memory.
1415 *
1416 * @param pDevIns The device instance.
1417 * @param pThis The shared HDA device state.
1418 * @param pStreamShared HDA stream to update (shared).
1419 * @param pStreamR3 HDA stream to update (ring-3).
1420 * @param cbToConsume The max amount of data to consume from the
1421 * internal DMA buffer. The caller will make sure
1422 * this is always the transfer size fo the current
1423 * period (unless something is seriously wrong).
1424 * @param fWriteSilence Whether to feed the guest silence rather than
1425 * fetching bytes from the internal DMA buffer.
1426 * This is set initially while we pre-buffer a
1427 * little bit of input, so we can better handle
1428 * time catch-ups and other schduling fun.
1429 * @param tsNowNs The current RTTimeNano() value.
1430 *
1431 * @remarks Caller owns the stream lock.
1432 */
1433static void hdaR3StreamDoDmaInput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
1434 PHDASTREAMR3 pStreamR3, uint32_t const cbToConsume, bool fWriteSilence, uint64_t tsNowNs)
1435{
1436 uint8_t const uSD = pStreamShared->u8SD;
1437 LogFlowFunc(("ENTER - #%u cbToConsume=%#x%s\n", uSD, cbToConsume, fWriteSilence ? " silence" : ""));
1438
1439 /*
1440 * Common prologue.
1441 */
1442 if (hdaR3StreamDoDmaPrologue(pThis, pStreamShared, pStreamR3, uSD, tsNowNs, "hdaR3StreamDoDmaInput"))
1443 { /* likely */ }
1444 else
1445 return;
1446
1447 /*
1448 *
1449 * The DMA copy loop.
1450 *
1451 */
1452 uint8_t abBounce[4096 + 128]; /* Most guest does at most 4KB BDLE. So, 4KB + space for a partial frame to reduce loops. */
1453 uint32_t cbBounce = 0; /* in case of incomplete frames between buffer segments */
1454 PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1455 uint32_t cbLeft = cbToConsume;
1456 Assert(cbLeft == pStreamShared->State.cbTransferSize);
1457 Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1458
1459 while (cbLeft > 0)
1460 {
1461 STAM_PROFILE_START(&pThis->StatIn, a);
1462
1463 /*
1464 * Figure out how much we can read & write in this iteration.
1465 */
1466 uint32_t cbChunk = 0;
1467 RTGCPHYS GCPhys = hdaStreamDmaBufGet(pStreamShared, &cbChunk);
1468
1469 /* If we're writing silence. */
1470 uint32_t cbWritten = 0;
1471 if (!fWriteSilence)
1472 {
1473 if (cbChunk <= cbLeft)
1474 { /* very likely */ }
1475 else
1476 cbChunk = cbLeft;
1477
1478 /*
1479 * Write the host data directly into the guest buffers.
1480 */
1481 while (cbChunk > 0)
1482 {
1483 /* Grab internal DMA buffer space and read into it. */
1484 void /*const*/ *pvBufSrc;
1485 size_t cbBufSrc;
1486 RTCircBufAcquireReadBlock(pCircBuf, cbChunk, &pvBufSrc, &cbBufSrc);
1487 AssertBreakStmt(cbBufSrc, RTCircBufReleaseReadBlock(pCircBuf, 0));
1488
1489 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, GCPhys, pvBufSrc, cbBufSrc);
1490 AssertRC(rc2);
1491
1492# ifdef HDA_DEBUG_SILENCE
1493 fix me if relevant;
1494# endif
1495 if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1496 { /* likely */ }
1497 else
1498 AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufSrc, cbBufSrc, 0 /* fFlags */);
1499
1500# ifdef VBOX_WITH_DTRACE
1501 VBOXDD_HDA_STREAM_DMA_IN((uint32_t)uSD, (uint32_t)cbBufSrc, pStreamShared->State.offRead);
1502# endif
1503 pStreamShared->State.offRead += cbBufSrc;
1504 RTCircBufReleaseReadBlock(pCircBuf, cbBufSrc);
1505 STAM_COUNTER_ADD(&pThis->StatBytesWritten, cbBufSrc);
1506
1507 /* advance */
1508 cbChunk -= (uint32_t)cbBufSrc;
1509 cbWritten += (uint32_t)cbBufSrc;
1510 GCPhys += cbBufSrc;
1511 pStreamShared->State.offCurBdle += (uint32_t)cbBufSrc;
1512 }
1513 }
1514 /*
1515 * We've got some initial silence to write, or we need to do
1516 * channel mapping. We produce guest output into the bounce buffer,
1517 * which is then copied into guest memory. The bounce buffer may keep
1518 * partial frames there for the next BDLE, if an BDLE isn't frame aligned.
1519 *
1520 * Note! cbLeft is relative to the input (host) frame size.
1521 * cbChunk OTOH is relative to output (guest) size.
1522 */
1523 else
1524 {
1525/** @todo clean up host/guest props distinction, they're the same now w/o the
1526 * mapping done by the mixer rather than us. */
1527 PCPDMAUDIOPCMPROPS pGuestProps = &pStreamShared->State.Cfg.Props;
1528 Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1529 uint32_t const cbLeftGuest = PDMAudioPropsFramesToBytes(pGuestProps,
1530 PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props,
1531 cbLeft));
1532 if (cbChunk <= cbLeftGuest)
1533 { /* very likely */ }
1534 else
1535 cbChunk = cbLeftGuest;
1536
1537 /*
1538 * Work till we've covered the chunk.
1539 */
1540 Log5Func(("loop0: GCPhys=%RGp cbChunk=%#x + cbBounce=%#x\n", GCPhys, cbChunk, cbBounce));
1541 while (cbChunk > 0)
1542 {
1543 /* Figure out how much we need to convert into the bounce buffer: */
1544 uint32_t cbGuest = PDMAudioPropsRoundUpBytesToFrame(pGuestProps, cbChunk - cbBounce);
1545 uint32_t cFrames = PDMAudioPropsBytesToFrames(pGuestProps, RT_MIN(cbGuest, sizeof(abBounce) - cbBounce));
1546
1547 cbGuest = PDMAudioPropsFramesToBytes(pGuestProps, cFrames);
1548 PDMAudioPropsClearBuffer(pGuestProps, &abBounce[cbBounce], cbGuest, cFrames);
1549 cbGuest += cbBounce;
1550
1551 /* Write it to the guest buffer. */
1552 uint32_t cbGuestActual = RT_MIN(cbGuest, cbChunk);
1553 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, GCPhys, abBounce, cbGuestActual);
1554 AssertRC(rc2);
1555 STAM_COUNTER_ADD(&pThis->StatBytesWritten, cbGuestActual);
1556
1557 /* advance */
1558 cbWritten += cbGuestActual;
1559 cbChunk -= cbGuestActual;
1560 GCPhys += cbGuestActual;
1561 pStreamShared->State.offCurBdle += cbGuestActual;
1562
1563 cbBounce = cbGuest - cbGuestActual;
1564 if (cbBounce)
1565 memmove(abBounce, &abBounce[cbGuestActual], cbBounce);
1566
1567 Log5Func((" loop1: GCPhys=%RGp cbGuestActual=%#x cbBounce=%#x cFrames=%#x\n", GCPhys, cbGuestActual, cbBounce, cFrames));
1568 }
1569 Log5Func(("loop0: GCPhys=%RGp cbBounce=%#x cbLeft=%#x\n", GCPhys, cbBounce, cbLeft - cbWritten));
1570 }
1571
1572 cbLeft -= cbWritten;
1573 STAM_PROFILE_STOP(&pThis->StatIn, a);
1574
1575 /*
1576 * Complete the buffer if necessary (common with the output DMA code).
1577 *
1578 * Must update the DMA position before we do this as the buffer IRQ may
1579 * fire on another vCPU and run in parallel to us, although it is very
1580 * unlikely it can make much progress as long as we're sitting on the
1581 * lock, it could still read the DMA position (Linux won't, as it reads
1582 * WALCLK and possibly SDnSTS before the DMA position).
1583 */
1584 hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, cbWritten);
1585 hdaStreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaR3StreamDoDmaInput");
1586 }
1587
1588 Assert(cbLeft == 0); /* There shall be no break statements in the above loop, so cbLeft is always zero here! */
1589 AssertMsg(cbBounce == 0, ("%#x\n", cbBounce));
1590
1591 /*
1592 * Common epilogue.
1593 */
1594 hdaR3StreamDoDmaEpilogue(pDevIns, pStreamShared, pStreamR3);
1595
1596 /*
1597 * Log and leave.
1598 */
1599 Log3Func(("LEAVE - [SD%RU8] %#RX32/%#RX32 @ %#RX64 - cTransferPendingInterrupts=%RU8\n",
1600 uSD, cbToConsume, pStreamShared->State.cbTransferSize, pStreamShared->State.offRead - cbToConsume,
1601 pStreamShared->State.cTransferPendingInterrupts));
1602}
1603
1604
1605/**
1606 * Input streams: Pulls data from the mixer, putting it in the internal DMA
1607 * buffer.
1608 *
1609 * @param pStreamShared HDA stream to update (shared).
1610 * @param pStreamR3 HDA stream to update (ring-3 bits).
1611 * @param pSink The mixer sink to pull from.
1612 */
1613static void hdaR3StreamPullFromMixer(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink)
1614{
1615# ifdef LOG_ENABLED
1616 uint64_t const offWriteOld = pStreamShared->State.offWrite;
1617# endif
1618 pStreamShared->State.offWrite = AudioMixerSinkTransferToCircBuf(pSink,
1619 pStreamR3->State.pCircBuf,
1620 pStreamShared->State.offWrite,
1621 pStreamR3->u8SD,
1622 pStreamR3->Dbg.Runtime.fEnabled
1623 ? pStreamR3->Dbg.Runtime.pFileStream : NULL);
1624
1625 Log3Func(("[SD%RU8] transferred=%#RX64 bytes -> @%#RX64\n", pStreamR3->u8SD,
1626 pStreamShared->State.offWrite - offWriteOld, pStreamShared->State.offWrite));
1627
1628 /* Update buffer stats. */
1629 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1630}
1631
1632
1633/**
1634 * Does DMA transfer for an HDA output stream.
1635 *
1636 * This transfers one DMA timer period worth of data from the guest and into the
1637 * internal DMA buffer.
1638 *
1639 * @param pDevIns The device instance.
1640 * @param pThis The shared HDA device state.
1641 * @param pStreamShared HDA stream to update (shared).
1642 * @param pStreamR3 HDA stream to update (ring-3).
1643 * @param cbToProduce The max amount of data to produce (i.e. put into
1644 * the circular buffer). Unless something is going
1645 * seriously wrong, this will always be transfer
1646 * size for the current period.
1647 * @param tsNowNs The current RTTimeNano() value.
1648 *
1649 * @remarks Caller owns the stream lock.
1650 */
1651static void hdaR3StreamDoDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
1652 PHDASTREAMR3 pStreamR3, uint32_t const cbToProduce, uint64_t tsNowNs)
1653{
1654 uint8_t const uSD = pStreamShared->u8SD;
1655 LogFlowFunc(("ENTER - #%u cbToProduce=%#x\n", uSD, cbToProduce));
1656
1657 /*
1658 * Common prologue.
1659 */
1660 if (hdaR3StreamDoDmaPrologue(pThis, pStreamShared, pStreamR3, uSD, tsNowNs, "hdaR3StreamDoDmaOutput"))
1661 { /* likely */ }
1662 else
1663 return;
1664
1665 /*
1666 *
1667 * The DMA copy loop.
1668 *
1669 */
1670# if 0
1671 uint8_t abBounce[4096 + 128]; /* Most guest does at most 4KB BDLE. So, 4KB + space for a partial frame to reduce loops. */
1672 uint32_t cbBounce = 0; /* in case of incomplete frames between buffer segments */
1673# endif
1674 PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1675 uint32_t cbLeft = cbToProduce;
1676# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
1677 Assert(cbLeft <= pStreamShared->State.cbTransferSize); /* a little pointless with the DMA'ing on LPIB read. */
1678# else
1679 Assert(cbLeft == pStreamShared->State.cbTransferSize);
1680# endif
1681 Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1682
1683 while (cbLeft > 0)
1684 {
1685 STAM_PROFILE_START(&pThis->StatOut, a);
1686
1687 /*
1688 * Figure out how much we can read & write in this iteration.
1689 */
1690 uint32_t cbChunk = 0;
1691 RTGCPHYS GCPhys = hdaStreamDmaBufGet(pStreamShared, &cbChunk);
1692
1693 /* Need to diverge if the BDLEs contain misaligned entries. */
1694 uint32_t cbRead = 0;
1695# if 0
1696 if (/** @todo pStreamShared->State.fFrameAlignedBuffers */)
1697# endif
1698 {
1699 if (cbChunk <= cbLeft)
1700 { /* very likely */ }
1701 else
1702 cbChunk = cbLeft;
1703
1704 /*
1705 * Read the guest data directly into the internal DMA buffer.
1706 */
1707 while (cbChunk > 0)
1708 {
1709 /* Grab internal DMA buffer space and read into it. */
1710 void *pvBufDst;
1711 size_t cbBufDst;
1712 RTCircBufAcquireWriteBlock(pCircBuf, cbChunk, &pvBufDst, &cbBufDst);
1713 AssertBreakStmt(cbBufDst, RTCircBufReleaseWriteBlock(pCircBuf, 0));
1714
1715 int rc2 = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, pvBufDst, cbBufDst);
1716 AssertRC(rc2);
1717
1718# ifdef HDA_DEBUG_SILENCE
1719 fix me if relevant;
1720# endif
1721 if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1722 { /* likely */ }
1723 else
1724 AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst, 0 /* fFlags */);
1725
1726# ifdef VBOX_WITH_DTRACE
1727 VBOXDD_HDA_STREAM_DMA_OUT((uint32_t)uSD, (uint32_t)cbBufDst, pStreamShared->State.offWrite);
1728# endif
1729 pStreamShared->State.offWrite += cbBufDst;
1730 RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
1731 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBufDst);
1732
1733 /* advance */
1734 cbChunk -= (uint32_t)cbBufDst;
1735 cbRead += (uint32_t)cbBufDst;
1736 GCPhys += cbBufDst;
1737 pStreamShared->State.offCurBdle += (uint32_t)cbBufDst;
1738 }
1739 }
1740# if 0
1741 /*
1742 * Need to map the frame content, so we need to read the guest data
1743 * into a temporary buffer, though the output can be directly written
1744 * into the internal buffer as it is assumed to be frame aligned.
1745 *
1746 * Note! cbLeft is relative to the output frame size.
1747 * cbChunk OTOH is relative to input size.
1748 */
1749 else
1750 {
1751/** @todo clean up host/guest props distinction, they're the same now w/o the
1752 * mapping done by the mixer rather than us. */
1753 PCPDMAUDIOPCMPROPS pGuestProps = &pStreamShared->State.Cfg.Props;
1754 Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1755 uint32_t const cbLeftGuest = PDMAudioPropsFramesToBytes(pGuestProps,
1756 PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props,
1757 cbLeft));
1758 if (cbChunk <= cbLeftGuest)
1759 { /* very likely */ }
1760 else
1761 cbChunk = cbLeftGuest;
1762
1763 /*
1764 * Loop till we've covered the chunk.
1765 */
1766 Log5Func(("loop0: GCPhys=%RGp cbChunk=%#x + cbBounce=%#x\n", GCPhys, cbChunk, cbBounce));
1767 while (cbChunk > 0)
1768 {
1769 /* Read into the bounce buffer. */
1770 uint32_t const cbToRead = RT_MIN(cbChunk, sizeof(abBounce) - cbBounce);
1771 int rc2 = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &abBounce[cbBounce], cbToRead);
1772 AssertRC(rc2);
1773 cbBounce += cbToRead;
1774
1775 /* Convert the size to whole frames and a remainder. */
1776 uint32_t cFrames = PDMAudioPropsBytesToFrames(pGuestProps, cbBounce);
1777 uint32_t const cbRemainder = cbBounce - PDMAudioPropsFramesToBytes(pGuestProps, cFrames);
1778 Log5Func((" loop1: GCPhys=%RGp cbToRead=%#x cbBounce=%#x cFrames=%#x\n", GCPhys, cbToRead, cbBounce, cFrames));
1779
1780 /*
1781 * Convert from the bounce buffer and into the internal DMA buffer.
1782 */
1783 uint32_t offBounce = 0;
1784 while (cFrames > 0)
1785 {
1786 void *pvBufDst;
1787 size_t cbBufDst;
1788 RTCircBufAcquireWriteBlock(pCircBuf, PDMAudioPropsFramesToBytes(&pStreamShared->State.Cfg.Props, cFrames),
1789 &pvBufDst, &cbBufDst);
1790
1791 uint32_t const cFramesToConvert = PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props, (uint32_t)cbBufDst);
1792 Assert(PDMAudioPropsFramesToBytes(&pStreamShared->State.Cfg.Props, cFramesToConvert) == cbBufDst);
1793 Assert(cFramesToConvert > 0);
1794 Assert(cFramesToConvert <= cFrames);
1795
1796 pStreamR3->State.Mapping.pfnGuestToHost(pvBufDst, &abBounce[offBounce], cFramesToConvert,
1797 &pStreamR3->State.Mapping);
1798 Log5Func((" loop2: offBounce=%#05x cFramesToConvert=%#05x cbBufDst=%#x%s\n",
1799 offBounce, cFramesToConvert, cbBufDst, ASMMemIsZero(pvBufDst, cbBufDst) ? " all zero" : ""));
1800
1801# ifdef HDA_DEBUG_SILENCE
1802 fix me if relevant;
1803# endif
1804 if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1805 { /* likely */ }
1806 else
1807 AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst, 0 /* fFlags */);
1808
1809 pStreamR3->State.offWrite += cbBufDst;
1810 RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
1811 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBufDst);
1812
1813 /* advance */
1814 cbLeft -= (uint32_t)cbBufDst;
1815 cFrames -= cFramesToConvert;
1816 offBounce += PDMAudioPropsFramesToBytes(pGuestProps, cFramesToConvert);
1817 }
1818
1819 /* advance */
1820 cbChunk -= cbToRead;
1821 GCPhys += cbToRead;
1822 pStreamShared->State.offCurBdle += cbToRead;
1823 if (cbRemainder)
1824 memmove(&abBounce[0], &abBounce[cbBounce - cbRemainder], cbRemainder);
1825 cbBounce = cbRemainder;
1826 }
1827 Log5Func(("loop0: GCPhys=%RGp cbBounce=%#x cbLeft=%#x\n", GCPhys, cbBounce, cbLeft));
1828 }
1829# endif
1830
1831 cbLeft -= cbRead;
1832 STAM_PROFILE_STOP(&pThis->StatOut, a);
1833
1834 /*
1835 * Complete the buffer if necessary (common with the input DMA code).
1836 *
1837 * Must update the DMA position before we do this as the buffer IRQ may
1838 * fire on another vCPU and run in parallel to us, although it is very
1839 * unlikely it can make much progress as long as we're sitting on the
1840 * lock, it could still read the DMA position (Linux won't, as it reads
1841 * WALCLK and possibly SDnSTS before the DMA position).
1842 */
1843 hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, cbRead);
1844 hdaStreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaR3StreamDoDmaOutput");
1845 }
1846
1847 Assert(cbLeft == 0); /* There shall be no break statements in the above loop, so cbLeft is always zero here! */
1848# if 0
1849 AssertMsg(cbBounce == 0, ("%#x\n", cbBounce));
1850# endif
1851
1852 /*
1853 * Common epilogue.
1854 */
1855 hdaR3StreamDoDmaEpilogue(pDevIns, pStreamShared, pStreamR3);
1856
1857 /*
1858 * Log and leave.
1859 */
1860 Log3Func(("LEAVE - [SD%RU8] %#RX32/%#RX32 @ %#RX64 - cTransferPendingInterrupts=%RU8\n",
1861 uSD, cbToProduce, pStreamShared->State.cbTransferSize, pStreamShared->State.offWrite - cbToProduce,
1862 pStreamShared->State.cTransferPendingInterrupts));
1863}
1864
1865#endif /* IN_RING3 */
1866
1867#ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
1868/**
1869 * Do DMA output transfer on LPIB register access.
1870 *
1871 * @returns VINF_SUCCESS or VINF_IOM_R3_MMIO_READ.
1872 * @param pDevIns The device instance.
1873 * @param pThis The shared instance data.
1874 * @param pStreamShared The shared stream data.
1875 * @param cbToTransfer How much to transfer.
1876 */
1877VBOXSTRICTRC hdaStreamDoOnAccessDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint32_t cbToTransfer)
1878{
1879 AssertReturn(cbToTransfer > 0, VINF_SUCCESS);
1880 int rc = VINF_SUCCESS;
1881
1882 /*
1883 * Check if we're exceeding the available buffer, go to ring-3 to
1884 * handle that (we would perhaps always take this path when in ring-3).
1885 */
1886 uint32_t cbDma = pStreamShared->State.cbDma;
1887 ASMCompilerBarrier();
1888 if ( cbDma >= sizeof(pStreamShared->State.abDma) /* paranoia */
1889 || cbToTransfer >= sizeof(pStreamShared->State.abDma) /* paranoia */
1890 || cbDma + cbToTransfer > sizeof(pStreamShared->State.abDma))
1891 {
1892# ifndef IN_RING3
1893 STAM_REL_COUNTER_INC(&pThis->StatAccessDmaOutputToR3);
1894 LogFlowFunc(("[SD%RU8] out of DMA buffer space (%#x, need %#x) -> VINF_IOM_R3_MMIO_READ\n",
1895 pStreamShared->u8SD, sizeof(pStreamShared->State.abDma) - pStreamShared->State.cbDma, cbToTransfer));
1896 return VINF_IOM_R3_MMIO_READ;
1897# else /* IN_RING3 */
1898 /*
1899 * Flush the bounce buffer, then do direct transfers to the
1900 * internal DMA buffer (updates LPIB).
1901 */
1902 PHDASTATER3 const pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
1903 uintptr_t const idxStream = pStreamShared->u8SD;
1904 AssertReturn(idxStream < RT_ELEMENTS(pThisCC->aStreams), VERR_INTERNAL_ERROR_4);
1905 PHDASTREAMR3 const pStreamR3 = &pThisCC->aStreams[idxStream];
1906
1907 hdaR3StreamFlushDmaBounceBufferOutput(pStreamShared, pStreamR3);
1908
1909 uint32_t cbStreamFree = hdaR3StreamGetFree(pStreamR3);
1910 if (cbStreamFree >= cbToTransfer)
1911 { /* likely */ }
1912 else
1913 {
1914 PAUDMIXSINK pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
1915 if (pSink)
1916 cbStreamFree = hdaR3StreamHandleDmaBufferOverrun(pStreamShared, pStreamR3, pSink, cbToTransfer, RTTimeNanoTS(),
1917 "hdaStreamDoOnAccessDmaOutput", cbStreamFree);
1918 else
1919 {
1920 LogFunc(("[SD%RU8] No sink and insufficient internal DMA buffer space (%#x) - won't do anything\n",
1921 pStreamShared->u8SD, cbStreamFree));
1922 return VINF_SUCCESS;
1923 }
1924 cbToTransfer = RT_MIN(cbToTransfer, cbStreamFree);
1925 if (cbToTransfer < PDMAudioPropsFrameSize(&pStreamShared->State.Cfg.Props))
1926 {
1927 LogFunc(("[SD%RU8] No internal DMA buffer space (%#x) - won't do anything\n", pStreamShared->u8SD, cbStreamFree));
1928 return VINF_SUCCESS;
1929 }
1930 }
1931 hdaR3StreamDoDmaOutput(pDevIns, pThis, pStreamShared, pStreamR3, cbToTransfer, RTTimeNanoTS());
1932 pStreamShared->State.cbDmaTotal += cbToTransfer;
1933# endif /* IN_RING3 */
1934 }
1935 else
1936 {
1937 /*
1938 * Transfer into the DMA bounce buffer.
1939 */
1940 LogFlowFunc(("[SD%RU8] Transfering %#x bytes to DMA bounce buffer (cbDma=%#x cbDmaTotal=%#x) (%p/%u)\n",
1941 pStreamShared->u8SD, cbToTransfer, cbDma, pStreamShared->State.cbDmaTotal, pStreamShared, pStreamShared->u8SD));
1942 uint32_t cbLeft = cbToTransfer;
1943 do
1944 {
1945 uint32_t cbChunk = 0;
1946 RTGCPHYS GCPhys = hdaStreamDmaBufGet(pStreamShared, &cbChunk);
1947
1948 bool fMustAdvanceBuffer;
1949 if (cbLeft < cbChunk)
1950 {
1951 fMustAdvanceBuffer = false;
1952 cbChunk = cbLeft;
1953 }
1954 else
1955 fMustAdvanceBuffer = true;
1956
1957 /* Read the guest data directly into the DMA bounce buffer. */
1958 int rc2 = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &pStreamShared->State.abDma[cbDma], cbChunk);
1959 AssertRC(rc2);
1960
1961 /* We update offWrite and StatBytesRead here even if we haven't moved the data
1962 to the internal DMA buffer yet, because we want the dtrace even to fire here. */
1963# ifdef VBOX_WITH_DTRACE
1964 VBOXDD_HDA_STREAM_DMA_OUT((uint32_t)pStreamShared->u8SD, cbChunk, pStreamShared->State.offWrite);
1965# endif
1966 pStreamShared->State.offWrite += cbChunk;
1967 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbChunk);
1968
1969 /* advance */
1970 pStreamShared->State.offCurBdle += cbChunk;
1971 pStreamShared->State.cbDmaTotal += cbChunk;
1972 cbDma += cbChunk;
1973 pStreamShared->State.cbDma = cbDma;
1974 cbLeft -= cbChunk;
1975 Log6Func(("cbLeft=%#x cbDma=%#x cbDmaTotal=%#x offCurBdle=%#x idxCurBdle=%#x (%p/%u)\n",
1976 cbLeft, cbDma, pStreamShared->State.cbDmaTotal, pStreamShared->State.offCurBdle,
1977 pStreamShared->State.idxCurBdle, pStreamShared, pStreamShared->u8SD));
1978
1979 /* Next buffer. */
1980 bool fAdvanced = hdaStreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaStreamDoOnAccessDmaOutput");
1981 AssertMsgStmt(fMustAdvanceBuffer == fAdvanced, ("%d %d\n", fMustAdvanceBuffer, fAdvanced), rc = VERR_INTERNAL_ERROR_3);
1982 } while (cbLeft > 0);
1983
1984 /*
1985 * Advance LPIB.
1986 */
1987 hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, cbToTransfer - cbLeft);
1988 }
1989
1990# ifdef VBOX_STRICT
1991 uint32_t idxSched = pStreamShared->State.idxSchedule;
1992 AssertStmt(idxSched < RT_MIN(RT_ELEMENTS(pStreamShared->State.aSchedule), pStreamShared->State.cSchedule), idxSched = 0);
1993 uint32_t const cbPeriod = pStreamShared->State.aSchedule[idxSched].cbPeriod;
1994 AssertMsg(pStreamShared->State.cbDmaTotal < cbPeriod, ("%#x vs %#x\n", pStreamShared->State.cbDmaTotal, cbPeriod));
1995# endif
1996
1997 STAM_REL_COUNTER_INC(&pThis->StatAccessDmaOutput);
1998 return rc;
1999}
2000#endif /* VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
2001
2002
2003#ifdef IN_RING3
2004
2005/**
2006 * Output streams: Pushes data to the mixer.
2007 *
2008 * @param pStreamShared HDA stream to update (shared bits).
2009 * @param pStreamR3 HDA stream to update (ring-3 bits).
2010 * @param pSink The mixer sink to push to.
2011 * @param nsNow The current RTTimeNanoTS() value.
2012 */
2013static void hdaR3StreamPushToMixer(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink, uint64_t nsNow)
2014{
2015# ifdef LOG_ENABLED
2016 uint64_t const offReadOld = pStreamShared->State.offRead;
2017# endif
2018 pStreamShared->State.offRead = AudioMixerSinkTransferFromCircBuf(pSink,
2019 pStreamR3->State.pCircBuf,
2020 pStreamShared->State.offRead,
2021 pStreamR3->u8SD,
2022 pStreamR3->Dbg.Runtime.fEnabled
2023 ? pStreamR3->Dbg.Runtime.pFileStream : NULL);
2024
2025 Assert(nsNow >= pStreamShared->State.tsLastReadNs);
2026 Log3Func(("[SD%RU8] nsDeltaLastRead=%RI64 transferred=%#RX64 bytes -> @%#RX64\n", pStreamR3->u8SD,
2027 nsNow - pStreamShared->State.tsLastReadNs, pStreamShared->State.offRead - offReadOld, pStreamShared->State.offRead));
2028 RT_NOREF(pStreamShared, nsNow);
2029
2030 /* Update buffer stats. */
2031 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
2032}
2033
2034
2035/**
2036 * Deals with a DMA buffer overrun.
2037 *
2038 * Makes sure we return with @a cbNeeded bytes of free space in pCircBuf.
2039 *
2040 * @returns Number of bytes free in the internal DMA buffer.
2041 * @param pStreamShared The shared data for the HDA stream.
2042 * @param pStreamR3 The ring-3 data for the HDA stream.
2043 * @param pSink The mixer sink (valid).
2044 * @param cbNeeded How much space we need (in bytes).
2045 * @param nsNow Current RTNanoTimeTS() timestamp.
2046 * @param cbStreamFree The current amount of free buffer space.
2047 * @param pszCaller The caller (for logging).
2048 */
2049static uint32_t hdaR3StreamHandleDmaBufferOverrun(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink,
2050 uint32_t cbNeeded, uint64_t nsNow,
2051 const char *pszCaller, uint32_t const cbStreamFree)
2052{
2053 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowProblems);
2054 Log(("%s: Warning! Stream #%u has insufficient space free: %#x bytes, need %#x. Will try move data out of the buffer...\n",
2055 pszCaller, pStreamShared->u8SD, cbStreamFree, cbNeeded));
2056 RT_NOREF(pszCaller, cbStreamFree);
2057
2058 int rc = AudioMixerSinkTryLock(pSink);
2059 if (RT_SUCCESS(rc))
2060 {
2061 hdaR3StreamPushToMixer(pStreamShared, pStreamR3, pSink, nsNow);
2062 AudioMixerSinkUpdate(pSink, 0, 0);
2063 AudioMixerSinkUnlock(pSink);
2064 }
2065 else
2066 RTThreadYield();
2067
2068 uint32_t const cbRet = hdaR3StreamGetFree(pStreamR3);
2069 Log(("%s: Gained %u bytes.\n", pszCaller, cbRet - cbStreamFree));
2070 if (cbRet >= cbNeeded)
2071 return cbRet;
2072
2073 /*
2074 * Unable to make sufficient space. Drop the whole buffer content.
2075 *
2076 * This is needed in order to keep the device emulation running at a
2077 * constant rate, at the cost of losing valid (but too much) data.
2078 */
2079 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowErrors);
2080 LogRel2(("HDA: Warning: Hit stream #%RU8 overflow, dropping %u bytes of audio data (%s)\n",
2081 pStreamShared->u8SD, hdaR3StreamGetUsed(pStreamR3), pszCaller));
2082# ifdef HDA_STRICT
2083 AssertMsgFailed(("Hit stream #%RU8 overflow -- timing bug?\n", pStreamShared->u8SD));
2084# endif
2085/**
2086 *
2087 * @todo r=bird: I don't think RTCircBufReset is entirely safe w/o
2088 * owning the AIO lock. See the note in the documentation about it not being
2089 * multi-threading aware (safe). Wish I'd verified this code much earlier.
2090 * Sigh^3!
2091 *
2092 */
2093 RTCircBufReset(pStreamR3->State.pCircBuf);
2094 pStreamShared->State.offWrite = 0;
2095 pStreamShared->State.offRead = 0;
2096 return hdaR3StreamGetFree(pStreamR3);
2097}
2098
2099
2100# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
2101/**
2102 * Flushes the DMA bounce buffer content to the internal DMA buffer.
2103 *
2104 * @param pStreamShared The shared data of the stream to have its DMA bounce
2105 * buffer flushed.
2106 * @param pStreamR3 The ring-3 stream data for same.
2107 */
2108static void hdaR3StreamFlushDmaBounceBufferOutput(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
2109{
2110 uint32_t cbDma = pStreamShared->State.cbDma;
2111 LogFlowFunc(("cbDma=%#x\n", cbDma));
2112 if (cbDma)
2113 {
2114 AssertReturnVoid(cbDma <= sizeof(pStreamShared->State.abDma));
2115 PRTCIRCBUF const pCircBuf = pStreamR3->State.pCircBuf;
2116 if (pCircBuf)
2117 {
2118 uint32_t offDma = 0;
2119 while (offDma < cbDma)
2120 {
2121 uint32_t const cbSrcLeft = cbDma - offDma;
2122
2123 /*
2124 * Grab a chunk of the internal DMA buffer.
2125 */
2126 void *pvBufDst = NULL;
2127 size_t cbBufDst = 0;
2128 RTCircBufAcquireWriteBlock(pCircBuf, cbSrcLeft, &pvBufDst, &cbBufDst);
2129 if (cbBufDst > 0)
2130 { /* likely */ }
2131 else
2132 {
2133 /* We've got buffering trouble. */
2134 RTCircBufReleaseWriteBlock(pCircBuf, 0);
2135
2136 PAUDMIXSINK pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
2137 if (pSink)
2138 hdaR3StreamHandleDmaBufferOverrun(pStreamShared, pStreamR3, pSink, cbSrcLeft, RTTimeNanoTS(),
2139 "hdaR3StreamFlushDmaBounceBufferOutput", 0 /*cbStreamFree*/);
2140 else
2141 {
2142 LogFunc(("Stream #%u has no sink. Dropping the rest of the data\n", pStreamR3->u8SD));
2143 break;
2144 }
2145
2146 RTCircBufAcquireWriteBlock(pCircBuf, cbSrcLeft, &pvBufDst, &cbBufDst);
2147 AssertBreakStmt(cbBufDst, RTCircBufReleaseWriteBlock(pCircBuf, 0));
2148 }
2149
2150 /*
2151 * Copy the samples into it and write it to the debug file if open.
2152 *
2153 * We do not fire the dtrace probe here nor update offRead as that was
2154 * done already (not sure that was a good idea?).
2155 */
2156 memcpy(pvBufDst, &pStreamShared->State.abDma[offDma], cbBufDst);
2157
2158 if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
2159 { /* likely */ }
2160 else
2161 AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst, 0 /* fFlags */);
2162
2163 RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
2164
2165 offDma += (uint32_t)cbBufDst;
2166 }
2167 }
2168
2169 /*
2170 * Mark the buffer empty.
2171 */
2172 pStreamShared->State.cbDma = 0;
2173 }
2174}
2175# endif /* VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
2176
2177
2178/**
2179 * The stream's main function when called by the timer.
2180 *
2181 * @note This function also will be called without timer invocation when
2182 * starting (enabling) the stream to minimize startup latency.
2183 *
2184 * @returns Current timer time if the timer is enabled, otherwise zero.
2185 * @param pDevIns The device instance.
2186 * @param pThis The shared HDA device state.
2187 * @param pThisCC The ring-3 HDA device state.
2188 * @param pStreamShared HDA stream to update (shared bits).
2189 * @param pStreamR3 HDA stream to update (ring-3 bits).
2190 */
2191uint64_t hdaR3StreamTimerMain(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
2192 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
2193{
2194 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2195 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pStreamShared->hTimer));
2196
2197 /* Do the work: */
2198 hdaR3StreamUpdateDma(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3);
2199
2200 /* Re-arm the timer if the sink is still active: */
2201 if ( pStreamShared->State.fRunning
2202 && pStreamR3->pMixSink
2203 && AudioMixerSinkIsActive(pStreamR3->pMixSink->pMixSink))
2204 {
2205 /* Advance the schduling: */
2206 uint32_t idxSched = pStreamShared->State.idxSchedule;
2207 AssertStmt(idxSched < RT_ELEMENTS(pStreamShared->State.aSchedule), idxSched = 0);
2208 uint32_t idxLoop = pStreamShared->State.idxScheduleLoop + 1;
2209 if (idxLoop >= pStreamShared->State.aSchedule[idxSched].cLoops)
2210 {
2211 idxSched += 1;
2212 if ( idxSched >= pStreamShared->State.cSchedule
2213 || idxSched >= RT_ELEMENTS(pStreamShared->State.aSchedule) /*paranoia^2*/)
2214 {
2215 idxSched = pStreamShared->State.cSchedulePrologue;
2216 AssertStmt(idxSched < RT_ELEMENTS(pStreamShared->State.aSchedule), idxSched = 0);
2217 }
2218 pStreamShared->State.idxSchedule = idxSched;
2219 idxLoop = 0;
2220 }
2221 pStreamShared->State.idxScheduleLoop = (uint16_t)idxLoop;
2222
2223 /* Do the actual timer re-arming. */
2224 uint64_t const tsNow = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer); /* (For virtual sync this remains the same for the whole callout IIRC) */
2225 uint64_t const tsTransferNext = tsNow + pStreamShared->State.aSchedule[idxSched].cPeriodTicks;
2226 Log3Func(("[SD%RU8] fSinkActive=true, tsTransferNext=%RU64 (in %RU64)\n",
2227 pStreamShared->u8SD, tsTransferNext, tsTransferNext - tsNow));
2228 int rc = PDMDevHlpTimerSet(pDevIns, pStreamShared->hTimer, tsTransferNext);
2229 AssertRC(rc);
2230
2231 /* Some legacy stuff: */
2232 pStreamShared->State.tsTransferNext = tsTransferNext;
2233 pStreamShared->State.cbTransferSize = pStreamShared->State.aSchedule[idxSched].cbPeriod;
2234
2235 return tsNow;
2236 }
2237
2238 Log3Func(("[SD%RU8] fSinkActive=false\n", pStreamShared->u8SD));
2239 return 0;
2240}
2241
2242
2243/**
2244 * Updates a HDA stream by doing DMA transfers.
2245 *
2246 * Will do mixer transfers too to try fix an overrun/underrun situation.
2247 *
2248 * The host sink(s) set the overall pace (bird: no it doesn't, the DMA timer
2249 * does - we just hope like heck it matches the speed at which the *backend*
2250 * host audio driver processes samples).
2251 *
2252 * @param pDevIns The device instance.
2253 * @param pThis The shared HDA device state.
2254 * @param pThisCC The ring-3 HDA device state.
2255 * @param pStreamShared HDA stream to update (shared bits).
2256 * @param pStreamR3 HDA stream to update (ring-3 bits).
2257 */
2258static void hdaR3StreamUpdateDma(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
2259 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
2260{
2261 RT_NOREF(pThisCC);
2262 int rc2;
2263
2264 /*
2265 * Make sure we're running and got an active mixer sink.
2266 */
2267 if (RT_LIKELY(pStreamShared->State.fRunning))
2268 { /* likely */ }
2269 else
2270 return;
2271
2272 PAUDMIXSINK pSink = NULL;
2273 if (pStreamR3->pMixSink)
2274 pSink = pStreamR3->pMixSink->pMixSink;
2275 if (RT_LIKELY(AudioMixerSinkIsActive(pSink)))
2276 { /* likely */ }
2277 else
2278 return;
2279
2280 /*
2281 * Get scheduling info common to both input and output streams.
2282 */
2283 const uint64_t tsNowNs = RTTimeNanoTS();
2284 uint32_t idxSched = pStreamShared->State.idxSchedule;
2285 AssertStmt(idxSched < RT_MIN(RT_ELEMENTS(pStreamShared->State.aSchedule), pStreamShared->State.cSchedule), idxSched = 0);
2286 uint32_t cbPeriod = pStreamShared->State.aSchedule[idxSched].cbPeriod;
2287
2288 /*
2289 * Output streams (SDO).
2290 */
2291 if (hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_OUT)
2292 {
2293# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
2294 /* Subtract already transferred bytes and flush the DMA bounce buffer. */
2295 uint32_t cbDmaTotal = pStreamShared->State.cbDmaTotal;
2296 if (cbDmaTotal > 0)
2297 {
2298 AssertStmt(cbDmaTotal < cbPeriod, cbDmaTotal = cbPeriod);
2299 cbPeriod -= cbDmaTotal;
2300 pStreamShared->State.cbDmaTotal = 0;
2301 hdaR3StreamFlushDmaBounceBufferOutput(pStreamShared, pStreamR3);
2302 }
2303 else
2304 Assert(pStreamShared->State.cbDma == 0);
2305# endif
2306
2307 /*
2308 * Check how much room we have in our DMA buffer. There should be at
2309 * least one period worth of space there or we're in an overflow situation.
2310 */
2311 uint32_t cbStreamFree = hdaR3StreamGetFree(pStreamR3);
2312 if (cbStreamFree >= cbPeriod)
2313 { /* likely */ }
2314 else
2315 cbStreamFree = hdaR3StreamHandleDmaBufferOverrun(pStreamShared, pStreamR3, pSink, cbPeriod, tsNowNs,
2316 "hdaR3StreamUpdateDma", cbStreamFree);
2317
2318 /*
2319 * Do the DMA transfer.
2320 */
2321 uint64_t const offWriteBefore = pStreamShared->State.offWrite;
2322 hdaR3StreamDoDmaOutput(pDevIns, pThis, pStreamShared, pStreamR3, RT_MIN(cbStreamFree, cbPeriod), tsNowNs);
2323
2324 /*
2325 * Should we push data to down thru the mixer to and to the host drivers?
2326 *
2327 * We initially delay this by pThis->msInitialDelay, but after than we'll
2328 * kick the AIO thread every time we've put more data in the buffer (which is
2329 * every time) as the host audio device needs to get data in a timely manner.
2330 *
2331 * (We used to try only wake up the AIO thread according to pThis->uIoTimer
2332 * and host wall clock, but that meant we would miss a wakup after the DMA
2333 * timer was called a little late or if TM entered into catch-up mode.)
2334 */
2335 bool fKickAioThread;
2336 if (!pStreamShared->State.tsAioDelayEnd)
2337 fKickAioThread = pStreamShared->State.offWrite > offWriteBefore
2338 || hdaR3StreamGetFree(pStreamR3) < pStreamShared->State.cbAvgTransfer * 2;
2339 else if (PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer) >= pStreamShared->State.tsAioDelayEnd)
2340 {
2341 Log3Func(("Initial delay done: Passed tsAioDelayEnd.\n"));
2342 pStreamShared->State.tsAioDelayEnd = 0;
2343 fKickAioThread = true;
2344 }
2345 else if (hdaR3StreamGetFree(pStreamR3) < pStreamShared->State.cbAvgTransfer * 2)
2346 {
2347 Log3Func(("Initial delay done: Passed running short on buffer.\n"));
2348 pStreamShared->State.tsAioDelayEnd = 0;
2349 fKickAioThread = true;
2350 }
2351 else
2352 {
2353 Log3Func(("Initial delay pending...\n"));
2354 fKickAioThread = false;
2355 }
2356
2357 Log3Func(("msDelta=%RU64 (vs %u) cbStreamFree=%#x (vs %#x) => fKickAioThread=%RTbool\n",
2358 (tsNowNs - pStreamShared->State.tsLastReadNs) / RT_NS_1MS,
2359 pStreamShared->State.Cfg.Device.cMsSchedulingHint, cbStreamFree,
2360 pStreamShared->State.cbAvgTransfer * 2, fKickAioThread));
2361
2362 if (fKickAioThread)
2363 {
2364 /* Notify the async I/O worker thread that there's work to do. */
2365 Log5Func(("Notifying AIO thread\n"));
2366 rc2 = AudioMixerSinkSignalUpdateJob(pSink);
2367 AssertRC(rc2);
2368 /* Update last read timestamp for logging/debugging. */
2369 pStreamShared->State.tsLastReadNs = tsNowNs;
2370 }
2371 }
2372 /*
2373 * Input stream (SDI).
2374 */
2375 else
2376 {
2377 Assert(hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_IN);
2378
2379 /*
2380 * See how much data we've got buffered...
2381 */
2382 bool fWriteSilence = false;
2383 uint32_t cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2384 if (pStreamShared->State.fInputPreBuffered && cbStreamUsed >= cbPeriod)
2385 { /*likely*/ }
2386 /*
2387 * Because it may take a while for the input stream to get going (at
2388 * least with pulseaudio), we feed the guest silence till we've
2389 * pre-buffer a reasonable amount of audio.
2390 */
2391 else if (!pStreamShared->State.fInputPreBuffered)
2392 {
2393 if (cbStreamUsed < pStreamShared->State.cbInputPreBuffer)
2394 {
2395 Log3(("hdaR3StreamUpdateDma: Pre-buffering (got %#x out of %#x bytes)...\n",
2396 cbStreamUsed, pStreamShared->State.cbInputPreBuffer));
2397 fWriteSilence = true;
2398 }
2399 else
2400 {
2401 Log3(("hdaR3StreamUpdateDma: Completed pre-buffering (got %#x, needed %#x bytes).\n",
2402 cbStreamUsed, pStreamShared->State.cbInputPreBuffer));
2403 pStreamShared->State.fInputPreBuffered = true;
2404 fWriteSilence = true; /* For now, just do the most conservative thing. */
2405 }
2406 cbStreamUsed = cbPeriod;
2407 }
2408 /*
2409 * When we're low on data, we must really try fetch some ourselves
2410 * as buffer underruns must not happen.
2411 */
2412 else
2413 {
2414 /** @todo We're ending up here to frequently with pulse audio at least (just
2415 * watch the stream stats in the statistcs viewer, and way to often we
2416 * have to inject silence bytes. I suspect part of the problem is
2417 * that the HDA device require a much better latency than what the
2418 * pulse audio is configured for by default (10 ms vs 150ms). */
2419 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowProblems);
2420 Log(("hdaR3StreamUpdateDma: Warning! Stream #%u has insufficient data available: %u bytes, need %u. Will try move pull more data into the buffer...\n",
2421 pStreamShared->u8SD, cbStreamUsed, cbPeriod));
2422 int rc = AudioMixerSinkTryLock(pSink);
2423 if (RT_SUCCESS(rc))
2424 {
2425 AudioMixerSinkUpdate(pSink, cbStreamUsed, cbPeriod);
2426 hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2427 AudioMixerSinkUnlock(pSink);
2428 }
2429 else
2430 RTThreadYield();
2431 Log(("hdaR3StreamUpdateDma: Gained %u bytes.\n", hdaR3StreamGetUsed(pStreamR3) - cbStreamUsed));
2432 cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2433 if (cbStreamUsed < cbPeriod)
2434 {
2435 /* Unable to find sufficient input data by simple prodding.
2436 In order to keep a constant byte stream following thru the DMA
2437 engine into the guest, we will try again and then fall back on
2438 filling the gap with silence. */
2439 uint32_t cbSilence = 0;
2440 do
2441 {
2442 AudioMixerSinkLock(pSink);
2443
2444 cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2445 if (cbStreamUsed < cbPeriod)
2446 {
2447 hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2448 cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2449 while (cbStreamUsed < cbPeriod)
2450 {
2451 void *pvDstBuf;
2452 size_t cbDstBuf;
2453 RTCircBufAcquireWriteBlock(pStreamR3->State.pCircBuf, cbPeriod - cbStreamUsed,
2454 &pvDstBuf, &cbDstBuf);
2455 RT_BZERO(pvDstBuf, cbDstBuf);
2456 RTCircBufReleaseWriteBlock(pStreamR3->State.pCircBuf, cbDstBuf);
2457 cbSilence += (uint32_t)cbDstBuf;
2458 cbStreamUsed += (uint32_t)cbDstBuf;
2459 }
2460 }
2461
2462 AudioMixerSinkUnlock(pSink);
2463 } while (cbStreamUsed < cbPeriod);
2464 if (cbSilence > 0)
2465 {
2466 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowErrors);
2467 STAM_REL_COUNTER_ADD(&pStreamR3->State.StatDmaFlowErrorBytes, cbSilence);
2468 LogRel2(("HDA: Warning: Stream #%RU8 underrun, added %u bytes of silence (%u us)\n", pStreamShared->u8SD,
2469 cbSilence, PDMAudioPropsBytesToMicro(&pStreamShared->State.Cfg.Props, cbSilence)));
2470 }
2471 }
2472 }
2473
2474 /*
2475 * Do the DMA'ing.
2476 */
2477 if (cbStreamUsed)
2478 hdaR3StreamDoDmaInput(pDevIns, pThis, pStreamShared, pStreamR3,
2479 RT_MIN(cbStreamUsed, cbPeriod), fWriteSilence, tsNowNs);
2480
2481 /*
2482 * We should always kick the AIO thread.
2483 */
2484 /** @todo This isn't entirely ideal. If we get into an underrun situation,
2485 * we ideally want the AIO thread to run right before the DMA timer
2486 * rather than right after it ran. */
2487 Log5Func(("Notifying AIO thread\n"));
2488 rc2 = AudioMixerSinkSignalUpdateJob(pSink);
2489 AssertRC(rc2);
2490 pStreamShared->State.tsLastReadNs = tsNowNs;
2491 }
2492}
2493
2494
2495/**
2496 * @callback_method_impl{FNAUDMIXSINKUPDATE}
2497 *
2498 * For output streams this moves data from the internal DMA buffer (in which
2499 * hdaR3StreamUpdateDma put it), thru the mixer and to the various backend audio
2500 * devices.
2501 *
2502 * For input streams this pulls data from the backend audio device(s), thru the
2503 * mixer and puts it in the internal DMA buffer ready for hdaR3StreamUpdateDma
2504 * to pump into guest memory.
2505 */
2506DECLCALLBACK(void) hdaR3StreamUpdateAsyncIoJob(PPDMDEVINS pDevIns, PAUDMIXSINK pSink, void *pvUser)
2507{
2508 PHDASTATE const pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
2509 PHDASTATER3 const pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
2510 PHDASTREAMR3 const pStreamR3 = (PHDASTREAMR3)pvUser;
2511 PHDASTREAM const pStreamShared = &pThis->aStreams[pStreamR3 - &pThisCC->aStreams[0]];
2512 Assert(pStreamR3 - &pThisCC->aStreams[0] == pStreamR3->u8SD);
2513 Assert(pStreamShared->u8SD == pStreamR3->u8SD);
2514 RT_NOREF(pSink);
2515
2516 /*
2517 * Make sure we haven't change sink and that it's still active (it
2518 * should be or we wouldn't have been called).
2519 */
2520 AssertReturnVoid(pStreamR3->pMixSink && pSink == pStreamR3->pMixSink->pMixSink);
2521 AssertReturnVoid(AudioMixerSinkIsActive(pSink));
2522
2523 /*
2524 * Output streams (SDO).
2525 */
2526 if (hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_OUT)
2527 hdaR3StreamPushToMixer(pStreamShared, pStreamR3, pSink, RTTimeNanoTS());
2528 /*
2529 * Input stream (SDI).
2530 */
2531 else
2532 {
2533 Assert(hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_IN);
2534 hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2535 }
2536}
2537
2538
2539# if 0 /* unused - no prototype even */
2540/**
2541 * Updates an HDA stream's current read or write buffer position (depending on the stream type) by
2542 * updating its associated LPIB register and DMA position buffer (if enabled).
2543 *
2544 * @returns Set LPIB value.
2545 * @param pDevIns The device instance.
2546 * @param pStream HDA stream to update read / write position for.
2547 * @param u32LPIB New LPIB (position) value to set.
2548 */
2549uint32_t hdaR3StreamUpdateLPIB(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint32_t u32LPIB)
2550{
2551 AssertMsg(u32LPIB <= pStreamShared->u32CBL,
2552 ("[SD%RU8] New LPIB (%RU32) exceeds CBL (%RU32)\n", pStreamShared->u8SD, u32LPIB, pStreamShared->u32CBL));
2553
2554 u32LPIB = RT_MIN(u32LPIB, pStreamShared->u32CBL);
2555
2556 LogFlowFunc(("[SD%RU8] LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n",
2557 pStreamShared->u8SD, u32LPIB, pThis->fDMAPosition));
2558
2559 /* Update LPIB in any case. */
2560 HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) = u32LPIB;
2561
2562 /* Do we need to tell the current DMA position? */
2563 if (pThis->fDMAPosition)
2564 {
2565 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns,
2566 pThis->u64DPBase + (pStreamShared->u8SD * 2 * sizeof(uint32_t)),
2567 (void *)&u32LPIB, sizeof(uint32_t));
2568 AssertRC(rc2);
2569 }
2570
2571 return u32LPIB;
2572}
2573# endif
2574
2575# ifdef HDA_USE_DMA_ACCESS_HANDLER
2576/**
2577 * Registers access handlers for a stream's BDLE DMA accesses.
2578 *
2579 * @returns true if registration was successful, false if not.
2580 * @param pStream HDA stream to register BDLE access handlers for.
2581 */
2582bool hdaR3StreamRegisterDMAHandlers(PHDASTREAM pStream)
2583{
2584 /* At least LVI and the BDL base must be set. */
2585 if ( !pStreamShared->u16LVI
2586 || !pStreamShared->u64BDLBase)
2587 {
2588 return false;
2589 }
2590
2591 hdaR3StreamUnregisterDMAHandlers(pStream);
2592
2593 LogFunc(("Registering ...\n"));
2594
2595 int rc = VINF_SUCCESS;
2596
2597 /*
2598 * Create BDLE ranges.
2599 */
2600
2601 struct BDLERANGE
2602 {
2603 RTGCPHYS uAddr;
2604 uint32_t uSize;
2605 } arrRanges[16]; /** @todo Use a define. */
2606
2607 size_t cRanges = 0;
2608
2609 for (uint16_t i = 0; i < pStreamShared->u16LVI + 1; i++)
2610 {
2611 HDABDLE BDLE;
2612 rc = hdaR3BDLEFetch(pDevIns, &BDLE, pStreamShared->u64BDLBase, i /* Index */);
2613 if (RT_FAILURE(rc))
2614 break;
2615
2616 bool fAddRange = true;
2617 BDLERANGE *pRange;
2618
2619 if (cRanges)
2620 {
2621 pRange = &arrRanges[cRanges - 1];
2622
2623 /* Is the current range a direct neighbor of the current BLDE? */
2624 if ((pRange->uAddr + pRange->uSize) == BDLE.Desc.u64BufAddr)
2625 {
2626 /* Expand the current range by the current BDLE's size. */
2627 pRange->uSize += BDLE.Desc.u32BufSize;
2628
2629 /* Adding a new range in this case is not needed anymore. */
2630 fAddRange = false;
2631
2632 LogFunc(("Expanding range %zu by %RU32 (%RU32 total now)\n", cRanges - 1, BDLE.Desc.u32BufSize, pRange->uSize));
2633 }
2634 }
2635
2636 /* Do we need to add a new range? */
2637 if ( fAddRange
2638 && cRanges < RT_ELEMENTS(arrRanges))
2639 {
2640 pRange = &arrRanges[cRanges];
2641
2642 pRange->uAddr = BDLE.Desc.u64BufAddr;
2643 pRange->uSize = BDLE.Desc.u32BufSize;
2644
2645 LogFunc(("Adding range %zu - 0x%x (%RU32)\n", cRanges, pRange->uAddr, pRange->uSize));
2646
2647 cRanges++;
2648 }
2649 }
2650
2651 LogFunc(("%zu ranges total\n", cRanges));
2652
2653 /*
2654 * Register all ranges as DMA access handlers.
2655 */
2656
2657 for (size_t i = 0; i < cRanges; i++)
2658 {
2659 BDLERANGE *pRange = &arrRanges[i];
2660
2661 PHDADMAACCESSHANDLER pHandler = (PHDADMAACCESSHANDLER)RTMemAllocZ(sizeof(HDADMAACCESSHANDLER));
2662 if (!pHandler)
2663 {
2664 rc = VERR_NO_MEMORY;
2665 break;
2666 }
2667
2668 RTListAppend(&pStream->State.lstDMAHandlers, &pHandler->Node);
2669
2670 pHandler->pStream = pStream; /* Save a back reference to the owner. */
2671
2672 char szDesc[32];
2673 RTStrPrintf(szDesc, sizeof(szDesc), "HDA[SD%RU8 - RANGE%02zu]", pStream->u8SD, i);
2674
2675 int rc2 = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
2676 hdaDMAAccessHandler,
2677 NULL, NULL, NULL,
2678 NULL, NULL, NULL,
2679 szDesc, &pHandler->hAccessHandlerType);
2680 AssertRCBreak(rc2);
2681
2682 pHandler->BDLEAddr = pRange->uAddr;
2683 pHandler->BDLESize = pRange->uSize;
2684
2685 /* Get first and last pages of the BDLE range. */
2686 RTGCPHYS pgFirst = pRange->uAddr & ~PAGE_OFFSET_MASK;
2687 RTGCPHYS pgLast = RT_ALIGN(pgFirst + pRange->uSize, PAGE_SIZE);
2688
2689 /* Calculate the region size (in pages). */
2690 RTGCPHYS regionSize = RT_ALIGN(pgLast - pgFirst, PAGE_SIZE);
2691
2692 pHandler->GCPhysFirst = pgFirst;
2693 pHandler->GCPhysLast = pHandler->GCPhysFirst + (regionSize - 1);
2694
2695 LogFunc((" Registering region '%s': %#RGp - %#RGp (region size: %#zx)\n",
2696 szDesc, pHandler->GCPhysFirst, pHandler->GCPhysLast, regionSize));
2697 LogFunc((" BDLE @ %#RGp - %#RGp (%#RX32)\n",
2698 pHandler->BDLEAddr, pHandler->BDLEAddr + pHandler->BDLESize, pHandler->BDLESize));
2699
2700 rc2 = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3),
2701 pHandler->GCPhysFirst, pHandler->GCPhysLast,
2702 pHandler->hAccessHandlerType, pHandler, NIL_RTR0PTR, NIL_RTRCPTR,
2703 szDesc);
2704 AssertRCBreak(rc2);
2705
2706 pHandler->fRegistered = true;
2707 }
2708
2709 LogFunc(("Registration ended with rc=%Rrc\n", rc));
2710
2711 return RT_SUCCESS(rc);
2712}
2713
2714/**
2715 * Unregisters access handlers of a stream's BDLEs.
2716 *
2717 * @param pStream HDA stream to unregister BDLE access handlers for.
2718 */
2719void hdaR3StreamUnregisterDMAHandlers(PHDASTREAM pStream)
2720{
2721 LogFunc(("\n"));
2722
2723 PHDADMAACCESSHANDLER pHandler, pHandlerNext;
2724 RTListForEachSafe(&pStream->State.lstDMAHandlers, pHandler, pHandlerNext, HDADMAACCESSHANDLER, Node)
2725 {
2726 if (!pHandler->fRegistered) /* Handler not registered? Skip. */
2727 continue;
2728
2729 LogFunc(("Unregistering 0x%x - 0x%x (%zu)\n",
2730 pHandler->GCPhysFirst, pHandler->GCPhysLast, pHandler->GCPhysLast - pHandler->GCPhysFirst));
2731
2732 int rc2 = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3),
2733 pHandler->GCPhysFirst);
2734 AssertRC(rc2);
2735
2736 RTListNodeRemove(&pHandler->Node);
2737
2738 RTMemFree(pHandler);
2739 pHandler = NULL;
2740 }
2741
2742 Assert(RTListIsEmpty(&pStream->State.lstDMAHandlers));
2743}
2744
2745# endif /* HDA_USE_DMA_ACCESS_HANDLER */
2746
2747#endif /* IN_RING3 */
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