DevHdaStream.cpp@ 89874

Last change on this file since 89874 was 89874, checked in by vboxsync, 4 years ago
DevHda: Calculate cMsSchedulingHint based on the actual scheduling rather than some unused and obsolete timer frequency value. Removed the TimerHz config value. Cleanups. bugref:9890
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File size: 117.7 KB

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1	/* $Id: DevHdaStream.cpp 89874 2021-06-24 09:51:51Z vboxsync $ */
2	/** @file
3	* Intel HD Audio Controller Emulation - Streams.
4	*/
5
6	/*
7	* Copyright (C) 2017-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DEV_HDA
23	#include <VBox/log.h>
24
25	#include <iprt/mem.h>
26	#include <iprt/semaphore.h>
27
28	#include <VBox/AssertGuest.h>
29	#include <VBox/vmm/pdmdev.h>
30	#include <VBox/vmm/pdmaudioifs.h>
31	#include <VBox/vmm/pdmaudioinline.h>
32
33	#include "AudioHlp.h"
34
35	#include "DevHda.h"
36
37	#ifdef VBOX_WITH_DTRACE
38	# include "dtrace/VBoxDD.h"
39	#endif
40
41
42	/*********************************************************************************************************************************
43	* Internal Functions *
44	*********************************************************************************************************************************/
45	#if defined(IN_RING3) \|\| defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA)
46	static void hdaStreamSetPositionAbs(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uLPIB);
47	#endif
48	#ifdef IN_RING3
49	# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
50	static void hdaR3StreamFlushDmaBounceBufferOutput(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
51	# endif
52	static uint32_t hdaR3StreamHandleDmaBufferOverrun(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink,
53	uint32_t cbNeeded, uint64_t nsNow,
54	const char *pszCaller, uint32_t const cbStreamFree);
55	static void hdaR3StreamUpdateDma(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
56	PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
57	#endif
58
59
60	#ifdef IN_RING3
61
62	/**
63	* Creates an HDA stream.
64	*
65	* @returns VBox status code.
66	* @param pStreamShared The HDA stream to construct - shared bits.
67	* @param pStreamR3 The HDA stream to construct - ring-3 bits.
68	* @param pThis The shared HDA device instance.
69	* @param pThisCC The ring-3 HDA device instance.
70	* @param uSD Stream descriptor number to assign.
71	*/
72	int hdaR3StreamConstruct(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PHDASTATE pThis, PHDASTATER3 pThisCC, uint8_t uSD)
73	{
74	pStreamR3->u8SD = uSD;
75	pStreamShared->u8SD = uSD;
76	pStreamR3->pMixSink = NULL;
77	pStreamR3->pHDAStateShared = pThis;
78	pStreamR3->pHDAStateR3 = pThisCC;
79	Assert(pStreamShared->hTimer != NIL_TMTIMERHANDLE); /* hdaR3Construct initalized this one already. */
80
81	pStreamShared->State.fInReset = false;
82	pStreamShared->State.fRunning = false;
83	# ifdef HDA_USE_DMA_ACCESS_HANDLER
84	RTListInit(&pStreamR3->State.lstDMAHandlers);
85	# endif
86
87	AssertPtr(pStreamR3->pHDAStateR3);
88	AssertPtr(pStreamR3->pHDAStateR3->pDevIns);
89
90	# ifdef DEBUG
91	int rc = RTCritSectInit(&pStreamR3->Dbg.CritSect);
92	AssertRCReturn(rc, rc);
93	# endif
94
95	const bool fIsInput = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN;
96
97	if (fIsInput)
98	{
99	pStreamShared->State.Cfg.enmPath = PDMAUDIOPATH_UNKNOWN;
100	pStreamShared->State.Cfg.enmDir = PDMAUDIODIR_IN;
101	}
102	else
103	{
104	pStreamShared->State.Cfg.enmPath = PDMAUDIOPATH_UNKNOWN;
105	pStreamShared->State.Cfg.enmDir = PDMAUDIODIR_OUT;
106	}
107
108	pStreamR3->Dbg.Runtime.fEnabled = pThisCC->Dbg.fEnabled;
109
110	if (pStreamR3->Dbg.Runtime.fEnabled)
111	{
112	char szFile[64];
113	char szPath[RTPATH_MAX];
114
115	/* pFileStream */
116	if (fIsInput)
117	RTStrPrintf(szFile, sizeof(szFile), "hdaStreamWriteSD%RU8", uSD);
118	else
119	RTStrPrintf(szFile, sizeof(szFile), "hdaStreamReadSD%RU8", uSD);
120
121	int rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
122	0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
123	AssertRC(rc2);
124
125	rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileStream);
126	AssertRC(rc2);
127
128	/* pFileDMARaw */
129	if (fIsInput)
130	RTStrPrintf(szFile, sizeof(szFile), "hdaDMARawWriteSD%RU8", uSD);
131	else
132	RTStrPrintf(szFile, sizeof(szFile), "hdaDMARawReadSD%RU8", uSD);
133
134	rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
135	0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
136	AssertRC(rc2);
137
138	rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileDMARaw);
139	AssertRC(rc2);
140
141	/* pFileDMAMapped */
142	if (fIsInput)
143	RTStrPrintf(szFile, sizeof(szFile), "hdaDMAWriteMappedSD%RU8", uSD);
144	else
145	RTStrPrintf(szFile, sizeof(szFile), "hdaDMAReadMappedSD%RU8", uSD);
146
147	rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
148	0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
149	AssertRC(rc2);
150
151	rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileDMAMapped);
152	AssertRC(rc2);
153
154	/* Delete stale debugging files from a former run. */
155	AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileStream);
156	AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileDMARaw);
157	AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileDMAMapped);
158	}
159
160	return VINF_SUCCESS;
161	}
162
163	/**
164	* Destroys an HDA stream.
165	*
166	* @param pStreamR3 The HDA stream to destroy - ring-3 bits.
167	*/
168	void hdaR3StreamDestroy(PHDASTREAMR3 pStreamR3)
169	{
170	LogFlowFunc(("[SD%RU8] Destroying ...\n", pStreamR3->u8SD));
171	int rc2;
172
173	if (pStreamR3->State.pAioRegSink)
174	{
175	rc2 = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
176	AssertRC(rc2);
177	pStreamR3->State.pAioRegSink = NULL;
178	}
179
180	if (pStreamR3->State.pCircBuf)
181	{
182	RTCircBufDestroy(pStreamR3->State.pCircBuf);
183	pStreamR3->State.pCircBuf = NULL;
184	pStreamR3->State.StatDmaBufSize = 0;
185	pStreamR3->State.StatDmaBufUsed = 0;
186	}
187
188	# ifdef DEBUG
189	if (RTCritSectIsInitialized(&pStreamR3->Dbg.CritSect))
190	{
191	rc2 = RTCritSectDelete(&pStreamR3->Dbg.CritSect);
192	AssertRC(rc2);
193	}
194	# endif
195
196	if (pStreamR3->Dbg.Runtime.fEnabled)
197	{
198	AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileStream);
199	pStreamR3->Dbg.Runtime.pFileStream = NULL;
200
201	AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileDMARaw);
202	pStreamR3->Dbg.Runtime.pFileDMARaw = NULL;
203
204	AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileDMAMapped);
205	pStreamR3->Dbg.Runtime.pFileDMAMapped = NULL;
206	}
207
208	LogFlowFuncLeave();
209	}
210
211
212	/**
213	* Appends a item to the scheduler.
214	*
215	* @returns VBox status code.
216	* @param pStreamShared The stream which scheduler should be modified.
217	* @param cbCur The period length in guest bytes.
218	* @param cbMaxPeriod The max period in guest bytes.
219	* @param idxLastBdle The last BDLE in the period.
220	* @param pHostProps The host PCM properties.
221	* @param pGuestProps The guest PCM properties.
222	* @param pcbBorrow Where to account for bytes borrowed across buffers
223	* to align scheduling items on frame boundraries.
224	*/
225	static int hdaR3StreamAddScheduleItem(PHDASTREAM pStreamShared, uint32_t cbCur, uint32_t cbMaxPeriod, uint32_t idxLastBdle,
226	PCPDMAUDIOPCMPROPS pHostProps, PCPDMAUDIOPCMPROPS pGuestProps, uint32_t *pcbBorrow)
227	{
228	/* Check that we've got room (shouldn't ever be a problem). */
229	size_t idx = pStreamShared->State.cSchedule;
230	AssertLogRelReturn(idx + 1 < RT_ELEMENTS(pStreamShared->State.aSchedule), VERR_INTERNAL_ERROR_5);
231
232	/* Figure out the BDLE range for this period. */
233	uint32_t const idxFirstBdle = idx == 0 ? 0
234	: RT_MIN((uint32_t)( pStreamShared->State.aSchedule[idx - 1].idxFirst
235	+ pStreamShared->State.aSchedule[idx - 1].cEntries),
236	idxLastBdle);
237
238	pStreamShared->State.aSchedule[idx].idxFirst = (uint8_t)idxFirstBdle;
239	pStreamShared->State.aSchedule[idx].cEntries = idxLastBdle >= idxFirstBdle
240	? idxLastBdle - idxFirstBdle + 1
241	: pStreamShared->State.cBdles - idxFirstBdle + idxLastBdle + 1;
242
243	/* Deal with borrowing due to unaligned IOC buffers. */
244	uint32_t const cbBorrowed = *pcbBorrow;
245	if (cbBorrowed < cbCur)
246	cbCur -= cbBorrowed;
247	else
248	{
249	/* Note. We can probably gloss over this, but it's not a situation a sane guest would put us, so don't bother for now. */
250	ASSERT_GUEST_MSG_FAILED(("#%u: cbBorrow=%#x cbCur=%#x BDLE[%u..%u]\n",
251	pStreamShared->u8SD, cbBorrowed, cbCur, idxFirstBdle, idxLastBdle));
252	LogRelMax(32, ("HDA: Stream #%u has a scheduling error: cbBorrow=%#x cbCur=%#x BDLE[%u..%u]\n",
253	pStreamShared->u8SD, cbBorrowed, cbCur, idxFirstBdle, idxLastBdle));
254	return VERR_OUT_OF_RANGE;
255	}
256
257	uint32_t cbCurAligned = PDMAudioPropsRoundUpBytesToFrame(pGuestProps, cbCur);
258	*pcbBorrow = cbCurAligned - cbCur;
259
260	/* Do we need to split up the period? */
261	if (cbCurAligned <= cbMaxPeriod)
262	{
263	uint32_t cbHost = PDMAudioPropsFramesToBytes(pHostProps, PDMAudioPropsBytesToFrames(pGuestProps, cbCurAligned));
264	pStreamShared->State.aSchedule[idx].cbPeriod = cbHost;
265	pStreamShared->State.aSchedule[idx].cLoops = 1;
266	}
267	else
268	{
269	/* Reduce till we've below the threshold. */
270	uint32_t cbLoop = cbCurAligned;
271	do
272	cbLoop = cbCurAligned / 2;
273	while (cbLoop > cbMaxPeriod);
274	cbLoop = PDMAudioPropsRoundUpBytesToFrame(pGuestProps, cbLoop);
275
276	/* Complete the scheduling item. */
277	uint32_t cbHost = PDMAudioPropsFramesToBytes(pHostProps, PDMAudioPropsBytesToFrames(pGuestProps, cbLoop));
278	pStreamShared->State.aSchedule[idx].cbPeriod = cbHost;
279	pStreamShared->State.aSchedule[idx].cLoops = cbCurAligned / cbLoop;
280
281	/* If there is a remainder, add it as a separate entry (this is
282	why the schedule must be more than twice the size of the BDL).*/
283	cbCurAligned %= cbLoop;
284	if (cbCurAligned)
285	{
286	pStreamShared->State.aSchedule[idx + 1] = pStreamShared->State.aSchedule[idx];
287	idx++;
288	cbHost = PDMAudioPropsFramesToBytes(pHostProps, PDMAudioPropsBytesToFrames(pGuestProps, cbCurAligned));
289	pStreamShared->State.aSchedule[idx].cbPeriod = cbHost;
290	pStreamShared->State.aSchedule[idx].cLoops = 1;
291	}
292	}
293
294	/* Done. */
295	pStreamShared->State.cSchedule = (uint16_t)(idx + 1);
296
297	return VINF_SUCCESS;
298	}
299
300	/**
301	* Creates the DMA timer schedule for the stream
302	*
303	* This is called from the stream setup code.
304	*
305	* @returns VBox status code.
306	* @param pStreamShared The stream to create a schedule for. The BDL
307	* must be loaded.
308	* @param cSegments Number of BDL segments.
309	* @param cBufferIrqs Number of the BDLEs with IOC=1.
310	* @param cbTotal The total BDL length in guest bytes.
311	* @param cbMaxPeriod Max period in guest bytes. This is in case the
312	* guest want to play the whole "Der Ring des
313	* Nibelungen" cycle in one go.
314	* @param cTimerTicksPerSec The DMA timer frequency.
315	* @param pHostProps The host PCM properties.
316	* @param pGuestProps The guest PCM properties.
317	*/
318	static int hdaR3StreamCreateSchedule(PHDASTREAM pStreamShared, uint32_t cSegments, uint32_t cBufferIrqs, uint32_t cbTotal,
319	uint32_t cbMaxPeriod, uint64_t cTimerTicksPerSec,
320	PCPDMAUDIOPCMPROPS pHostProps, PCPDMAUDIOPCMPROPS pGuestProps)
321	{
322	int rc;
323
324	/*
325	* Reset scheduling state.
326	*/
327	RT_ZERO(pStreamShared->State.aSchedule);
328	pStreamShared->State.cSchedule = 0;
329	pStreamShared->State.cSchedulePrologue = 0;
330	pStreamShared->State.idxSchedule = 0;
331	pStreamShared->State.idxScheduleLoop = 0;
332
333	/*
334	* Do the basic schedule compilation.
335	*/
336	uint32_t cPotentialPrologue = 0;
337	uint32_t cbBorrow = 0;
338	uint32_t cbCur = 0;
339	uint32_t cbMin = UINT32_MAX;
340	pStreamShared->State.aSchedule[0].idxFirst = 0;
341	for (uint32_t i = 0; i < cSegments; i++)
342	{
343	cbCur += pStreamShared->State.aBdl[i].cb;
344	if (pStreamShared->State.aBdl[i].cb < cbMin)
345	cbMin = pStreamShared->State.aBdl[i].cb;
346	if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
347	{
348	rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur, cbMaxPeriod, i, pHostProps, pGuestProps, &cbBorrow);
349	ASSERT_GUEST_RC_RETURN(rc, rc);
350
351	if (cPotentialPrologue == 0)
352	cPotentialPrologue = pStreamShared->State.cSchedule;
353	cbCur = 0;
354	}
355	}
356	AssertLogRelMsgReturn(cbBorrow == 0, ("HDA: Internal scheduling error on stream #%u: cbBorrow=%#x cbTotal=%#x cbCur=%#x\n",
357	pStreamShared->u8SD, cbBorrow, cbTotal, cbCur),
358	VERR_INTERNAL_ERROR_3);
359
360	/*
361	* Deal with any loose ends.
362	*/
363	if (cbCur && cBufferIrqs == 0)
364	{
365	/*
366	* No IOC. Vista ends up here, typically with three buffers configured.
367	*
368	* The perferred option here is to aim at processing one average BDLE with
369	* each DMA timer period, since that best matches how we update LPIB at
370	* present.
371	*
372	* The second alternative is to divide the whole span up into 3-4 periods
373	* to try increase our chances of keeping ahead of the guest. We may need
374	* to pick this if there are too few buffer descriptor or they are too small.
375	*
376	* However, what we probably should be doing is to do real DMA work whenever
377	* the guest reads a DMA related register (like LPIB) and just do 3-4 DMA
378	* timer periods, however we'll be postponing the DMA timer every time we
379	* return to ring-3 and signal the AIO, so in the end we'd probably not use
380	* the timer callback at all. (This is assuming a small shared per-stream
381	* buffer for keeping the DMA data in and that it's size will force a return
382	* to ring-3 often enough to keep the AIO thread going at a reasonable rate.)
383	*/
384	Assert(cbCur == cbTotal);
385
386	/* Match the BDLEs 1:1 if there are 3 or more and that the smallest one
387	is at least 5ms big. */
388	if (cSegments >= 3 && PDMAudioPropsBytesToMilli(pGuestProps, cbMin) >= 5 /ms/)
389	{
390	for (uint32_t i = 0; i < cSegments; i++)
391	{
392	rc = hdaR3StreamAddScheduleItem(pStreamShared, pStreamShared->State.aBdl[i].cb, cbMaxPeriod,
393	i, pHostProps, pGuestProps, &cbBorrow);
394	ASSERT_GUEST_RC_RETURN(rc, rc);
395	}
396	}
397	/* Otherwise, just divide the work into 3 or 4 portions and hope for the best.
398	It seems, though, that this only really work for windows vista if we avoid
399	working accross buffer lines. */
400	/** @todo This can be simplified/relaxed/uncluttered if we do DMA work when LPIB
401	* is read, assuming ofc that LPIB is read before each buffer update. */
402	else
403	{
404	uint32_t const cPeriods = cSegments != 3 && PDMAudioPropsBytesToMilli(pGuestProps, cbCur) >= 4 * 5 /ms/
405	? 4 : cSegments != 2 ? 3 : 2;
406	uint32_t const cbPeriod = PDMAudioPropsFloorBytesToFrame(pGuestProps, cbCur / cPeriods);
407	uint32_t iBdle = 0;
408	uint32_t offBdle = 0;
409	for (uint32_t iPeriod = 0; iPeriod < cPeriods; iPeriod++)
410	{
411	if (iPeriod + 1 < cPeriods)
412	{
413	offBdle += cbPeriod;
414	while (iBdle < cSegments && offBdle >= pStreamShared->State.aBdl[iBdle].cb)
415	offBdle -= pStreamShared->State.aBdl[iBdle++].cb;
416	rc = hdaR3StreamAddScheduleItem(pStreamShared, cbPeriod, cbMaxPeriod, offBdle != 0 ? iBdle : iBdle - 1,
417	pHostProps, pGuestProps, &cbBorrow);
418	}
419	else
420	rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur - iPeriod * cbPeriod, cbMaxPeriod, cSegments - 1,
421	pHostProps, pGuestProps, &cbBorrow);
422	ASSERT_GUEST_RC_RETURN(rc, rc);
423	}
424
425	}
426	Assert(cbBorrow == 0);
427	}
428	else if (cbCur)
429	{
430	/* The last BDLE didn't have IOC set, so we must continue processing
431	from the start till we hit one that has. */
432	uint32_t i;
433	for (i = 0; i < cSegments; i++)
434	{
435	cbCur += pStreamShared->State.aBdl[i].cb;
436	if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
437	break;
438	}
439	rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur, cbMaxPeriod, i, pHostProps, pGuestProps, &cbBorrow);
440	ASSERT_GUEST_RC_RETURN(rc, rc);
441
442	/* The initial scheduling items covering the wrap around area are
443	considered a prologue and must not repeated later. */
444	Assert(cPotentialPrologue);
445	pStreamShared->State.cSchedulePrologue = (uint8_t)cPotentialPrologue;
446	}
447
448	/*
449	* If there is just one BDLE with IOC set, we have to make sure
450	* we've got at least two periods scheduled, otherwise there is
451	* a very good chance the guest will overwrite the start of the
452	* buffer before we ever get around to reading it.
453	*/
454	if (cBufferIrqs == 1)
455	{
456	uint32_t i = pStreamShared->State.cSchedulePrologue;
457	Assert(i < pStreamShared->State.cSchedule);
458	if ( i + 1 == pStreamShared->State.cSchedule
459	&& pStreamShared->State.aSchedule[i].cLoops == 1)
460	{
461	uint32_t const cbFirstHalf = PDMAudioPropsFloorBytesToFrame(pHostProps, pStreamShared->State.aSchedule[i].cbPeriod / 2);
462	uint32_t const cbOtherHalf = pStreamShared->State.aSchedule[i].cbPeriod - cbFirstHalf;
463	pStreamShared->State.aSchedule[i].cbPeriod = cbFirstHalf;
464	if (cbFirstHalf == cbOtherHalf)
465	pStreamShared->State.aSchedule[i].cLoops = 2;
466	else
467	{
468	pStreamShared->State.aSchedule[i + 1] = pStreamShared->State.aSchedule[i];
469	pStreamShared->State.aSchedule[i].cbPeriod = cbOtherHalf;
470	pStreamShared->State.cSchedule++;
471	}
472	}
473	}
474
475	/*
476	* Go over the schduling entries and calculate the timer ticks for each period.
477	*/
478	LogRel2(("HDA: Stream #%u schedule: %u items, %u prologue\n",
479	pStreamShared->u8SD, pStreamShared->State.cSchedule, pStreamShared->State.cSchedulePrologue));
480	uint64_t const cbHostPerSec = PDMAudioPropsFramesToBytes(pHostProps, pHostProps->uHz);
481	for (uint32_t i = 0; i < pStreamShared->State.cSchedule; i++)
482	{
483	uint64_t const cTicks = ASMMultU64ByU32DivByU32(cTimerTicksPerSec, pStreamShared->State.aSchedule[i].cbPeriod,
484	cbHostPerSec);
485	AssertLogRelMsgReturn((uint32_t)cTicks == cTicks, ("cTicks=%RU64 (%#RX64)\n", cTicks, cTicks), VERR_INTERNAL_ERROR_4);
486	pStreamShared->State.aSchedule[i].cPeriodTicks = RT_MAX((uint32_t)cTicks, 16);
487	LogRel2(("HDA: #%u: %u ticks / %u bytes, %u loops, BDLE%u L %u\n", i, pStreamShared->State.aSchedule[i].cPeriodTicks,
488	pStreamShared->State.aSchedule[i].cbPeriod, pStreamShared->State.aSchedule[i].cLoops,
489	pStreamShared->State.aSchedule[i].idxFirst, pStreamShared->State.aSchedule[i].cEntries));
490	}
491
492	return VINF_SUCCESS;
493	}
494
495
496	/**
497	* Sets up ((re-)iniitalizes) an HDA stream.
498	*
499	* @returns VBox status code. VINF_NO_CHANGE if the stream does not need
500	* be set-up again because the stream's (hardware) parameters did
501	* not change.
502	* @param pDevIns The device instance.
503	* @param pThis The shared HDA device state (for HW register
504	* parameters).
505	* @param pStreamShared HDA stream to set up, shared portion.
506	* @param pStreamR3 HDA stream to set up, ring-3 portion.
507	* @param uSD Stream descriptor number to assign it.
508	*/
509	int hdaR3StreamSetUp(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD)
510	{
511	/* This must be valid all times. */
512	AssertReturn(uSD < HDA_MAX_STREAMS, VERR_INVALID_PARAMETER);
513
514	/* These member can only change on data corruption, despite what the code does further down (bird). */
515	AssertReturn(pStreamShared->u8SD == uSD, VERR_WRONG_ORDER);
516	AssertReturn(pStreamR3->u8SD == uSD, VERR_WRONG_ORDER);
517
518	const uint64_t u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, uSD),
519	HDA_STREAM_REG(pThis, BDPU, uSD));
520	const uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, uSD);
521	const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, uSD);
522	const uint8_t u8FIFOS = HDA_STREAM_REG(pThis, FIFOS, uSD) + 1;
523	uint8_t u8FIFOW = hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, uSD));
524	const uint16_t u16FMT = HDA_STREAM_REG(pThis, FMT, uSD);
525
526	/* Is the bare minimum set of registers configured for the stream?
527	* If not, bail out early, as there's nothing to do here for us (yet). */
528	if ( !u64BDLBase
529	\|\| !u16LVI
530	\|\| !u32CBL
531	\|\| !u8FIFOS
532	\|\| !u8FIFOW
533	\|\| !u16FMT)
534	{
535	LogFunc(("[SD%RU8] Registers not set up yet, skipping (re-)initialization\n", uSD));
536	return VINF_SUCCESS;
537	}
538
539	/*
540	* Convert the config to PDM PCM properties and configure the stream.
541	*/
542	PPDMAUDIOSTREAMCFG pCfg = &pStreamShared->State.Cfg;
543	int rc = hdaR3SDFMTToPCMProps(u16FMT, &pCfg->Props);
544	if (RT_SUCCESS(rc))
545	pCfg->enmDir = hdaGetDirFromSD(uSD);
546	else
547	{
548	LogRelMax(32, ("HDA: Warning: Format 0x%x for stream #%RU8 not supported\n", HDA_STREAM_REG(pThis, FMT, uSD), uSD));
549	return rc;
550	}
551
552	ASSERT_GUEST_LOGREL_MSG_RETURN( PDMAudioPropsFrameSize(&pCfg->Props) > 0
553	&& u32CBL % PDMAudioPropsFrameSize(&pCfg->Props) == 0,
554	("CBL for stream #%RU8 does not align to frame size (u32CBL=%u cbFrameSize=%u)\n",
555	uSD, u32CBL, PDMAudioPropsFrameSize(&pCfg->Props)),
556	VERR_INVALID_PARAMETER);
557
558	/* Make sure the guest behaves regarding the stream's FIFO. */
559	ASSERT_GUEST_LOGREL_MSG_STMT(u8FIFOW <= u8FIFOS,
560	("Guest tried setting a bigger FIFOW (%RU8) than FIFOS (%RU8), limiting\n", u8FIFOW, u8FIFOS),
561	u8FIFOW = u8FIFOS /* ASSUMES that u8FIFOS has been validated. */);
562
563	pStreamShared->u8SD = uSD;
564
565	/* Update all register copies so that we later know that something has changed. */
566	pStreamShared->u64BDLBase = u64BDLBase;
567	pStreamShared->u16LVI = u16LVI;
568	pStreamShared->u32CBL = u32CBL;
569	pStreamShared->u8FIFOS = u8FIFOS;
570	pStreamShared->u8FIFOW = u8FIFOW;
571	pStreamShared->u16FMT = u16FMT;
572
573	/* The the stream's name, based on the direction. */
574	switch (pCfg->enmDir)
575	{
576	case PDMAUDIODIR_IN:
577	# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
578	# error "Implement me!"
579	# else
580	pCfg->enmPath = PDMAUDIOPATH_IN_LINE;
581	RTStrCopy(pCfg->szName, sizeof(pCfg->szName), "Line In");
582	# endif
583	break;
584
585	case PDMAUDIODIR_OUT:
586	/* Destination(s) will be set in hdaR3AddStreamOut(),
587	* based on the channels / stream layout. */
588	break;
589
590	default:
591	AssertFailedReturn(VERR_NOT_SUPPORTED);
592	break;
593	}
594
595	LogRel2(("HDA: Stream #%RU8 DMA @ 0x%x (%RU32 bytes = %RU64ms total)\n", uSD, pStreamShared->u64BDLBase,
596	pStreamShared->u32CBL, PDMAudioPropsBytesToMilli(&pCfg->Props, pStreamShared->u32CBL)));
597
598	/*
599	* Load the buffer descriptor list.
600	*
601	* Section 3.6.2 states that "the BDL should not be modified unless the RUN
602	* bit is 0", so it should be within the specs to read it once here and not
603	* re-read any BDLEs later.
604	*/
605	/* Reset BDL state. */
606	RT_ZERO(pStreamShared->State.aBdl);
607	pStreamShared->State.offCurBdle = 0;
608	pStreamShared->State.idxCurBdle = 0;
609
610	uint32_t /const/ cTransferFragments = (pStreamShared->u16LVI & 0xff) + 1;
611	if (cTransferFragments <= 1)
612	LogRel(("HDA: Warning: Stream #%RU8 transfer buffer count invalid: (%RU16)! Buggy guest audio driver!\n", uSD, pStreamShared->u16LVI));
613	AssertLogRelReturn(cTransferFragments <= RT_ELEMENTS(pStreamShared->State.aBdl), VERR_INTERNAL_ERROR_5);
614	pStreamShared->State.cBdles = cTransferFragments;
615
616	/* Load them. */
617	rc = PDMDevHlpPCIPhysRead(pDevIns, u64BDLBase, pStreamShared->State.aBdl,
618	sizeof(pStreamShared->State.aBdl[0]) * cTransferFragments);
619	AssertRC(rc);
620
621	/* Check what we just loaded. Refuse overly large buffer lists. */
622	uint64_t cbTotal = 0;
623	uint32_t cBufferIrqs = 0;
624	for (uint32_t i = 0; i < cTransferFragments; i++)
625	{
626	if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
627	cBufferIrqs++;
628	cbTotal += pStreamShared->State.aBdl[i].cb;
629	}
630	ASSERT_GUEST_STMT_RETURN(cbTotal < _2G,
631	LogRelMax(32, ("HDA: Error: Stream #%u is configured with an insane amount of buffer space - refusing do work with it: %RU64 (%#RX64) bytes.\n",
632	uSD, cbTotal, cbTotal)),
633	VERR_NOT_SUPPORTED);
634	ASSERT_GUEST_STMT_RETURN(cbTotal == u32CBL,
635	LogRelMax(32, ("HDA: Warning: Stream #%u has a mismatch between CBL and configured buffer space: %RU32 (%#RX32) vs %RU64 (%#RX64)\n",
636	uSD, u32CBL, u32CBL, cbTotal, cbTotal)),
637	VERR_NOT_SUPPORTED);
638
639	/*
640	* Create a DMA timer schedule.
641	*/
642	/** @todo clean up this, pGuestProps and pHostProps are the same now. */
643	rc = hdaR3StreamCreateSchedule(pStreamShared, cTransferFragments, cBufferIrqs, (uint32_t)cbTotal,
644	PDMAudioPropsMilliToBytes(&pCfg->Props, 100 /** @todo make configurable */),
645	PDMDevHlpTimerGetFreq(pDevIns, pStreamShared->hTimer),
646	&pCfg->Props, &pCfg->Props);
647	if (RT_FAILURE(rc))
648	return rc;
649
650	pStreamShared->State.cbCurDmaPeriod = pStreamShared->State.aSchedule[0].cbPeriod;
651
652	/*
653	* Calculate the transfer Hz for use in the circular buffer calculation
654	* and the average period for the scheduling hint.
655	*/
656	uint32_t cbMaxPeriod = 0;
657	uint32_t cbMinPeriod = UINT32_MAX;
658	uint64_t cTicks = 0;
659	uint32_t cPeriods = 0;
660	for (uint32_t i = pStreamShared->State.cSchedulePrologue; i < pStreamShared->State.cSchedule; i++)
661	{
662	uint32_t cbPeriod = pStreamShared->State.aSchedule[i].cbPeriod;
663	cbMaxPeriod = RT_MAX(cbMaxPeriod, cbPeriod);
664	cbMinPeriod = RT_MIN(cbMinPeriod, cbPeriod);
665	cPeriods += pStreamShared->State.aSchedule[i].cLoops;
666	cTicks += pStreamShared->State.aSchedule[i].cPeriodTicks * pStreamShared->State.aSchedule[i].cLoops;
667	}
668	/* Only consider the prologue in relation to the max period. */
669	for (uint32_t i = 0; i < pStreamShared->State.cSchedulePrologue; i++)
670	cbMaxPeriod = RT_MAX(cbMaxPeriod, pStreamShared->State.aSchedule[i].cbPeriod);
671
672	AssertLogRelReturn(cPeriods > 0, VERR_INTERNAL_ERROR_3);
673	uint64_t const cbTransferPerSec = RT_MAX(PDMAudioPropsFramesToBytes(&pCfg->Props, pCfg->Props.uHz),
674	4096 /* zero div prevention: min is 6kHz, picked 4k in case I'm mistaken */);
675	unsigned uTransferHz = cbTransferPerSec * 1000 / cbMaxPeriod;
676	LogRel2(("HDA: Stream #%RU8 needs a %u.%03u Hz timer rate (period: %u..%u host bytes)\n",
677	uSD, uTransferHz / 1000, uTransferHz % 1000, cbMinPeriod, cbMaxPeriod));
678	uTransferHz /= 1000;
679
680	if (uTransferHz > 400) /* Anything above 400 Hz looks fishy -- tell the user. */
681	LogRelMax(32, ("HDA: Warning: Calculated transfer Hz rate for stream #%RU8 looks incorrect (%u), please re-run with audio debug mode and report a bug\n",
682	uSD, uTransferHz));
683
684	pStreamShared->State.cbAvgTransfer = (uint32_t)(cbTotal + cPeriods - 1) / cPeriods;
685
686	/* Calculate the average scheduling period length in nanoseconds. */
687	uint64_t const cTimerResolution = PDMDevHlpTimerGetFreq(pDevIns, pStreamShared->hTimer);
688	Assert(cTimerResolution <= UINT32_MAX);
689	uint64_t const cNsPerPeriod = ASMMultU64ByU32DivByU32(cTicks / cPeriods, RT_NS_1SEC, cTimerResolution);
690	AssertLogRelReturn(cNsPerPeriod > 0, VERR_INTERNAL_ERROR_3);
691
692	/* For input streams we must determin a pre-buffering requirement.
693	We use the initial delay as a basis here, though we must have at
694	least two max periods worth of data queued up due to the way we
695	work the AIO thread. */
696	pStreamShared->State.fInputPreBuffered = false;
697	pStreamShared->State.cbInputPreBuffer = PDMAudioPropsMilliToBytes(&pCfg->Props, pThis->msInitialDelay);
698	pStreamShared->State.cbInputPreBuffer = RT_MIN(cbMaxPeriod * 2, pStreamShared->State.cbInputPreBuffer);
699
700	/*
701	* Set up data transfer stuff.
702	*/
703	/* Set I/O scheduling hint for the backends. */
704	pCfg->Device.cMsSchedulingHint = cNsPerPeriod > RT_NS_1MS ? (cNsPerPeriod + RT_NS_1MS / 2) / RT_NS_1MS : 1;
705	LogRel2(("HDA: Stream #%RU8 set scheduling hint for the backends to %RU32ms\n", uSD, pCfg->Device.cMsSchedulingHint));
706
707	/* Make sure to also update the stream's DMA counter (based on its current LPIB value). */
708	/** @todo r=bird: We use LPIB as-is here, so if it's not zero we have to
709	* locate the right place in the schedule and whatnot...
710	*
711	* This is a similar scenario as when loading state saved, btw.
712	*/
713	if (HDA_STREAM_REG(pThis, LPIB, uSD) != 0)
714	LogRel2(("HDA: Warning! Stream #%RU8 is set up with LPIB=%#RX32 instead of zero!\n", uSD, HDA_STREAM_REG(pThis, LPIB, uSD)));
715	hdaStreamSetPositionAbs(pStreamShared, pDevIns, pThis, HDA_STREAM_REG(pThis, LPIB, uSD));
716
717	# ifdef LOG_ENABLED
718	hdaR3BDLEDumpAll(pDevIns, pThis, pStreamShared->u64BDLBase, pStreamShared->u16LVI + 1);
719	# endif
720
721	/*
722	* Set up internal ring buffer.
723	*/
724
725	/* (Re-)Allocate the stream's internal DMA buffer,
726	* based on the timing and PCM properties we just got above. */
727	if (pStreamR3->State.pCircBuf)
728	{
729	RTCircBufDestroy(pStreamR3->State.pCircBuf);
730	pStreamR3->State.pCircBuf = NULL;
731	pStreamR3->State.StatDmaBufSize = 0;
732	pStreamR3->State.StatDmaBufUsed = 0;
733	}
734	pStreamShared->State.offWrite = 0;
735	pStreamShared->State.offRead = 0;
736
737	/*
738	* The default internal ring buffer size must be:
739	*
740	* - Large enough for at least three periodic DMA transfers.
741	*
742	* It is critically important that we don't experience underruns
743	* in the DMA OUT code, because it will cause the buffer processing
744	* to get skewed and possibly overlap with what the guest is updating.
745	* At the time of writing (2021-03-05) there is no code for getting
746	* back into sync there.
747	*
748	* - Large enough for at least three I/O scheduling hints.
749	*
750	* We want to lag behind a DMA period or two, but there must be
751	* sufficent space for the AIO thread to get schedule and shuffle
752	* data thru the mixer and onto the host audio hardware.
753	*
754	* - Both above with plenty to spare.
755	*
756	* So, just take the longest of the two periods and multipling it by 6.
757	* We aren't not talking about very large base buffers heres, so size isn't
758	* an issue.
759	*
760	* Note: Use pCfg->Props as PCM properties here, as we only want to store the
761	* samples we actually need, in other words, skipping the interleaved
762	* channels we don't support / need to save space.
763	*/
764	uint32_t cbCircBuf = PDMAudioPropsMilliToBytes(&pCfg->Props, pThis->msInitialDelay + RT_MS_1SEC * 6 / uTransferHz);
765	LogRel2(("HDA: Stream #%RU8 default ring buffer size is %RU32 bytes / %RU64 ms\n",
766	uSD, cbCircBuf, PDMAudioPropsBytesToMilli(&pCfg->Props, cbCircBuf)));
767
768	uint32_t msCircBufCfg = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? pThis->cMsCircBufIn : pThis->cMsCircBufOut;
769	if (msCircBufCfg) /* Anything set via CFGM? */
770	{
771	cbCircBuf = PDMAudioPropsMilliToBytes(&pCfg->Props, msCircBufCfg);
772	LogRel2(("HDA: Stream #%RU8 is using a custom ring buffer size of %RU32 bytes / %RU64 ms\n",
773	uSD, cbCircBuf, PDMAudioPropsBytesToMilli(&pCfg->Props, cbCircBuf)));
774	}
775
776	/* Serious paranoia: */
777	ASSERT_GUEST_LOGREL_MSG_STMT(cbCircBuf % PDMAudioPropsFrameSize(&pCfg->Props) == 0,
778	("Ring buffer size (%RU32) for stream #%RU8 not aligned to the (host) frame size (%RU8)\n",
779	cbCircBuf, uSD, PDMAudioPropsFrameSize(&pCfg->Props)),
780	rc = VERR_INVALID_PARAMETER);
781	ASSERT_GUEST_LOGREL_MSG_STMT(cbCircBuf, ("Ring buffer size for stream #%RU8 is invalid\n", uSD),
782	rc = VERR_INVALID_PARAMETER);
783	if (RT_SUCCESS(rc))
784	{
785	rc = RTCircBufCreate(&pStreamR3->State.pCircBuf, cbCircBuf);
786	if (RT_SUCCESS(rc))
787	{
788	pStreamR3->State.StatDmaBufSize = cbCircBuf;
789
790	/*
791	* Forward the timer frequency hint to TM as well for better accuracy on
792	* systems w/o preemption timers (also good for 'info timers').
793	*/
794	PDMDevHlpTimerSetFrequencyHint(pDevIns, pStreamShared->hTimer, uTransferHz);
795	}
796	}
797
798	if (RT_FAILURE(rc))
799	LogRelMax(32, ("HDA: Initializing stream #%RU8 failed with %Rrc\n", uSD, rc));
800
801	# ifdef VBOX_WITH_DTRACE
802	VBOXDD_HDA_STREAM_SETUP((uint32_t)uSD, rc, pStreamShared->State.Cfg.Props.uHz,
803	pStreamShared->State.aSchedule[pStreamShared->State.cSchedule - 1].cPeriodTicks,
804	pStreamShared->State.aSchedule[pStreamShared->State.cSchedule - 1].cbPeriod);
805	# endif
806	return rc;
807	}
808
809	/**
810	* Resets an HDA stream.
811	*
812	* @param pThis The shared HDA device state.
813	* @param pThisCC The ring-3 HDA device state.
814	* @param pStreamShared HDA stream to reset (shared).
815	* @param pStreamR3 HDA stream to reset (ring-3).
816	* @param uSD Stream descriptor (SD) number to use for this stream.
817	*/
818	void hdaR3StreamReset(PHDASTATE pThis, PHDASTATER3 pThisCC, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD)
819	{
820	LogFunc(("[SD%RU8] Reset\n", uSD));
821
822	/*
823	* Assert some sanity.
824	*/
825	AssertPtr(pThis);
826	AssertPtr(pStreamShared);
827	AssertPtr(pStreamR3);
828	Assert(uSD < HDA_MAX_STREAMS);
829	Assert(pStreamShared->u8SD == uSD);
830	Assert(pStreamR3->u8SD == uSD);
831	AssertMsg(!pStreamShared->State.fRunning, ("[SD%RU8] Cannot reset stream while in running state\n", uSD));
832
833	/*
834	* Set reset state.
835	*/
836	Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false); /* No nested calls. */
837	ASMAtomicXchgBool(&pStreamShared->State.fInReset, true);
838
839	/*
840	* Second, initialize the registers.
841	*/
842	/* See 6.2.33: Clear on reset. */
843	HDA_STREAM_REG(pThis, STS, uSD) = 0;
844	/* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
845	* bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
846	HDA_STREAM_REG(pThis, CTL, uSD) = HDA_SDCTL_TP \| (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_SDCTL_SRST);
847	/* ICH6 defines default values (120 bytes for input and 192 bytes for output descriptors) of FIFO size. 18.2.39. */
848	HDA_STREAM_REG(pThis, FIFOS, uSD) = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? HDA_SDIFIFO_120B : HDA_SDOFIFO_192B;
849	/* See 18.2.38: Always defaults to 0x4 (32 bytes). */
850	HDA_STREAM_REG(pThis, FIFOW, uSD) = HDA_SDFIFOW_32B;
851	HDA_STREAM_REG(pThis, LPIB, uSD) = 0;
852	HDA_STREAM_REG(pThis, CBL, uSD) = 0;
853	HDA_STREAM_REG(pThis, LVI, uSD) = 0;
854	HDA_STREAM_REG(pThis, FMT, uSD) = 0;
855	HDA_STREAM_REG(pThis, BDPU, uSD) = 0;
856	HDA_STREAM_REG(pThis, BDPL, uSD) = 0;
857
858	# ifdef HDA_USE_DMA_ACCESS_HANDLER
859	hdaR3StreamUnregisterDMAHandlers(pThis, pStream);
860	# endif
861
862	/* Assign the default mixer sink to the stream. */
863	pStreamR3->pMixSink = hdaR3GetDefaultSink(pThisCC, uSD);
864	if (pStreamR3->State.pAioRegSink)
865	{
866	int rc2 = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
867	AssertRC(rc2);
868	pStreamR3->State.pAioRegSink = NULL;
869	}
870
871	/* Reset transfer stuff. */
872	pStreamShared->State.cTransferPendingInterrupts = 0;
873	pStreamShared->State.tsTransferLast = 0;
874	pStreamShared->State.tsTransferNext = 0;
875
876	/* Initialize timestamps. */
877	pStreamShared->State.tsLastTransferNs = 0;
878	pStreamShared->State.tsLastReadNs = 0;
879	pStreamShared->State.tsAioDelayEnd = UINT64_MAX;
880	pStreamShared->State.tsStart = 0;
881
882	RT_ZERO(pStreamShared->State.aBdl);
883	RT_ZERO(pStreamShared->State.aSchedule);
884	pStreamShared->State.offCurBdle = 0;
885	pStreamShared->State.cBdles = 0;
886	pStreamShared->State.idxCurBdle = 0;
887	pStreamShared->State.cSchedulePrologue = 0;
888	pStreamShared->State.cSchedule = 0;
889	pStreamShared->State.idxSchedule = 0;
890	pStreamShared->State.idxScheduleLoop = 0;
891	pStreamShared->State.fInputPreBuffered = false;
892
893	if (pStreamR3->State.pCircBuf)
894	RTCircBufReset(pStreamR3->State.pCircBuf);
895	pStreamShared->State.offWrite = 0;
896	pStreamShared->State.offRead = 0;
897
898	# ifdef DEBUG
899	pStreamR3->Dbg.cReadsTotal = 0;
900	pStreamR3->Dbg.cbReadTotal = 0;
901	pStreamR3->Dbg.tsLastReadNs = 0;
902	pStreamR3->Dbg.cWritesTotal = 0;
903	pStreamR3->Dbg.cbWrittenTotal = 0;
904	pStreamR3->Dbg.cWritesHz = 0;
905	pStreamR3->Dbg.cbWrittenHz = 0;
906	pStreamR3->Dbg.tsWriteSlotBegin = 0;
907	# endif
908
909	/* Report that we're done resetting this stream. */
910	HDA_STREAM_REG(pThis, CTL, uSD) = 0;
911
912	# ifdef VBOX_WITH_DTRACE
913	VBOXDD_HDA_STREAM_RESET((uint32_t)uSD);
914	# endif
915	LogFunc(("[SD%RU8] Reset\n", uSD));
916
917	/* Exit reset mode. */
918	ASMAtomicXchgBool(&pStreamShared->State.fInReset, false);
919	}
920
921	/**
922	* Enables or disables an HDA audio stream.
923	*
924	* @returns VBox status code.
925	* @param pThis The shared HDA device state.
926	* @param pStreamShared HDA stream to enable or disable - shared bits.
927	* @param pStreamR3 HDA stream to enable or disable - ring-3 bits.
928	* @param fEnable Whether to enable or disble the stream.
929	*/
930	int hdaR3StreamEnable(PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, bool fEnable)
931	{
932	AssertPtr(pStreamR3);
933	AssertPtr(pStreamShared);
934
935	LogFunc(("[SD%RU8] fEnable=%RTbool, pMixSink=%p\n", pStreamShared->u8SD, fEnable, pStreamR3->pMixSink));
936
937	/* First, enable or disable the stream and the stream's sink, if any. */
938	int rc = VINF_SUCCESS;
939	PAUDMIXSINK const pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
940	if (pSink)
941	{
942	if (fEnable)
943	{
944	if (pStreamR3->State.pAioRegSink != pSink)
945	{
946	if (pStreamR3->State.pAioRegSink)
947	{
948	rc = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
949	AssertRC(rc);
950	}
951	rc = AudioMixerSinkAddUpdateJob(pSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3,
952	pStreamShared->State.Cfg.Device.cMsSchedulingHint);
953	AssertLogRelRC(rc);
954	pStreamR3->State.pAioRegSink = RT_SUCCESS(rc) ? pSink : NULL;
955	}
956	rc = AudioMixerSinkStart(pSink);
957	}
958	else
959	rc = AudioMixerSinkDrainAndStop(pSink,
960	pStreamR3->State.pCircBuf ? (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf) : 0);
961	}
962	if ( RT_SUCCESS(rc)
963	&& fEnable
964	&& pStreamR3->Dbg.Runtime.fEnabled)
965	{
966	Assert(AudioHlpPcmPropsAreValid(&pStreamShared->State.Cfg.Props));
967
968	if (fEnable)
969	{
970	if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileStream))
971	{
972	int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileStream, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
973	&pStreamShared->State.Cfg.Props);
974	AssertRC(rc2);
975	}
976
977	if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileDMARaw))
978	{
979	int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileDMARaw, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
980	&pStreamShared->State.Cfg.Props);
981	AssertRC(rc2);
982	}
983
984	if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileDMAMapped))
985	{
986	int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileDMAMapped, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
987	&pStreamShared->State.Cfg.Props);
988	AssertRC(rc2);
989	}
990	}
991	}
992
993	if (RT_SUCCESS(rc))
994	{
995	if (fEnable)
996	pStreamShared->State.tsTransferLast = 0; /* Make sure it's not stale and messes up WALCLK calculations. */
997	pStreamShared->State.fRunning = fEnable;
998
999	/*
1000	* Set the FIFORDY bit when we start running and clear it when stopping.
1001	*
1002	* This prevents Linux from timing out in snd_hdac_stream_sync when starting
1003	* a stream. Technically, Linux also uses the SSYNC feature there, but we
1004	* can get away with just setting the FIFORDY bit for now.
1005	*/
1006	if (fEnable)
1007	HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) \|= HDA_SDSTS_FIFORDY;
1008	else
1009	HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) &= ~HDA_SDSTS_FIFORDY;
1010	}
1011
1012	LogFunc(("[SD%RU8] rc=%Rrc\n", pStreamShared->u8SD, rc));
1013	return rc;
1014	}
1015
1016	/**
1017	* Marks the stream as started.
1018	*
1019	* Used after the stream has been enabled and the DMA timer has been armed.
1020	*/
1021	void hdaR3StreamMarkStarted(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint64_t tsNow)
1022	{
1023	pStreamShared->State.tsLastReadNs = RTTimeNanoTS();
1024	pStreamShared->State.tsStart = tsNow;
1025	pStreamShared->State.tsAioDelayEnd = tsNow + PDMDevHlpTimerFromMilli(pDevIns, pStreamShared->hTimer, pThis->msInitialDelay);
1026	Log3Func(("#%u: tsStart=%RU64 tsAioDelayEnd=%RU64 tsLastReadNs=%RU64\n", pStreamShared->u8SD,
1027	pStreamShared->State.tsStart, pStreamShared->State.tsAioDelayEnd, pStreamShared->State.tsLastReadNs));
1028
1029	}
1030
1031	/**
1032	* Marks the stream as stopped.
1033	*/
1034	void hdaR3StreamMarkStopped(PHDASTREAM pStreamShared)
1035	{
1036	Log3Func(("#%u\n", pStreamShared->u8SD));
1037	pStreamShared->State.tsAioDelayEnd = UINT64_MAX;
1038	}
1039
1040	#endif /* IN_RING3 */
1041	#if defined(IN_RING3) \|\| defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA)
1042
1043	/**
1044	* Updates an HDA stream's current read or write buffer position (depending on the stream type) by
1045	* setting its associated LPIB register and DMA position buffer (if enabled) to an absolute value.
1046	*
1047	* @param pStreamShared HDA stream to update read / write position for (shared).
1048	* @param pDevIns The device instance.
1049	* @param pThis The shared HDA device state.
1050	* @param uLPIB Absolute position (in bytes) to set current read / write position to.
1051	*/
1052	static void hdaStreamSetPositionAbs(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uLPIB)
1053	{
1054	AssertPtrReturnVoid(pStreamShared);
1055	AssertMsgStmt(uLPIB <= pStreamShared->u32CBL, ("%#x\n", uLPIB), uLPIB = pStreamShared->u32CBL);
1056
1057	Log3Func(("[SD%RU8] LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n", pStreamShared->u8SD, uLPIB, pThis->fDMAPosition));
1058
1059	/* Update LPIB in any case. */
1060	HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) = uLPIB;
1061
1062	/* Do we need to tell the current DMA position? */
1063	if (pThis->fDMAPosition)
1064	{
1065	/*
1066	* Linux switched to using the position buffers some time during 2.6.x.
1067	* 2.6.12 used LPIB, 2.6.17 defaulted to DMA position buffers, between
1068	* the two version things were being changing quite a bit.
1069	*
1070	* Since 2.6.17, they will treat a zero DMA position value during the first
1071	* period/IRQ as reason to fall back to LPIB mode (see azx_position_ok in
1072	* 2.6.27+, and azx_pcm_pointer before that). They later also added
1073	* UINT32_MAX to the values causing same.
1074	*
1075	* Since 2.6.35 azx_position_ok will read the wall clock register before
1076	* determining the position.
1077	*/
1078	int rc2 = PDMDevHlpPCIPhysWrite(pDevIns,
1079	pThis->u64DPBase + (pStreamShared->u8SD * 2 * sizeof(uint32_t)),
1080	(void *)&uLPIB, sizeof(uint32_t));
1081	AssertRC(rc2);
1082	}
1083	}
1084
1085
1086	/**
1087	* Updates an HDA stream's current read or write buffer position (depending on the stream type) by
1088	* adding a value to its associated LPIB register and DMA position buffer (if enabled).
1089	*
1090	* @note Handles automatic CBL wrap-around.
1091	*
1092	* @param pStreamShared HDA stream to update read / write position for (shared).
1093	* @param pDevIns The device instance.
1094	* @param pThis The shared HDA device state.
1095	* @param cbToAdd Position (in bytes) to add to the current read / write position.
1096	*/
1097	static void hdaStreamSetPositionAdd(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t cbToAdd)
1098	{
1099	if (cbToAdd) /* No need to update anything if 0. */
1100	{
1101	uint32_t const uCBL = pStreamShared->u32CBL;
1102	if (uCBL) /* paranoia */
1103	{
1104	uint32_t uNewLpid = HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) + cbToAdd;
1105	# if 1 /** @todo r=bird: this is wrong according to the spec */
1106	uNewLpid %= uCBL;
1107	# else
1108	/* The spec says it goes to CBL then wraps arpimd to 1, not back to zero. See 3.3.37. */
1109	if (uNewLpid > uCBL)
1110	uNewLpid %= uCBL;
1111	# endif
1112	hdaStreamSetPositionAbs(pStreamShared, pDevIns, pThis, uNewLpid);
1113	}
1114	}
1115	}
1116
1117	#endif /* IN_RING3 \|\| VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
1118	#ifdef IN_RING3
1119
1120	/**
1121	* Retrieves the available size of (buffered) audio data (in bytes) of a given HDA stream.
1122	*
1123	* @returns Available data (in bytes).
1124	* @param pStreamR3 HDA stream to retrieve size for (ring-3).
1125	*/
1126	static uint32_t hdaR3StreamGetUsed(PHDASTREAMR3 pStreamR3)
1127	{
1128	AssertPtrReturn(pStreamR3, 0);
1129
1130	if (pStreamR3->State.pCircBuf)
1131	return (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1132	return 0;
1133	}
1134
1135	/**
1136	* Retrieves the free size of audio data (in bytes) of a given HDA stream.
1137	*
1138	* @returns Free data (in bytes).
1139	* @param pStreamR3 HDA stream to retrieve size for (ring-3).
1140	*/
1141	static uint32_t hdaR3StreamGetFree(PHDASTREAMR3 pStreamR3)
1142	{
1143	AssertPtrReturn(pStreamR3, 0);
1144
1145	if (pStreamR3->State.pCircBuf)
1146	return (uint32_t)RTCircBufFree(pStreamR3->State.pCircBuf);
1147	return 0;
1148	}
1149
1150	#endif /* IN_RING3 */
1151	#if defined(IN_RING3) \|\| defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA)
1152
1153	/**
1154	* Get the current address and number of bytes left in the current BDLE.
1155	*
1156	* @returns The current physical address.
1157	* @param pStreamShared The stream to check.
1158	* @param pcbLeft The number of bytes left at the returned address.
1159	*/
1160	DECLINLINE(RTGCPHYS) hdaStreamDmaBufGet(PHDASTREAM pStreamShared, uint32_t *pcbLeft)
1161	{
1162	uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1163	AssertStmt(idxBdle < pStreamShared->State.cBdles, idxBdle = 0);
1164
1165	uint32_t const cbCurBdl = pStreamShared->State.aBdl[idxBdle].cb;
1166	uint32_t offCurBdle = pStreamShared->State.offCurBdle;
1167	AssertStmt(pStreamShared->State.offCurBdle <= cbCurBdl, offCurBdle = cbCurBdl);
1168
1169	*pcbLeft = cbCurBdl - offCurBdle;
1170	return pStreamShared->State.aBdl[idxBdle].GCPhys + offCurBdle;
1171	}
1172
1173	#if 0 /* unused */
1174	/**
1175	* Get the size of the current BDLE.
1176	*
1177	* @returns The size (in bytes).
1178	* @param pStreamShared The stream to check.
1179	*/
1180	DECLINLINE(RTGCPHYS) hdaStreamDmaBufGetSize(PHDASTREAM pStreamShared)
1181	{
1182	uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1183	AssertStmt(idxBdle < pStreamShared->State.cBdles, idxBdle = 0);
1184	return pStreamShared->State.aBdl[idxBdle].cb;
1185	}
1186	#endif
1187
1188	/**
1189	* Checks if the current BDLE is completed.
1190	*
1191	* @retval true if complete
1192	* @retval false if not.
1193	* @param pStreamShared The stream to check.
1194	*/
1195	DECLINLINE(bool) hdaStreamDmaBufIsComplete(PHDASTREAM pStreamShared)
1196	{
1197	uint8_t const idxBdle = pStreamShared->State.idxCurBdle;
1198	AssertReturn(idxBdle < pStreamShared->State.cBdles, true);
1199
1200	uint32_t const cbCurBdl = pStreamShared->State.aBdl[idxBdle].cb;
1201	uint32_t const offCurBdle = pStreamShared->State.offCurBdle;
1202	Assert(offCurBdle <= cbCurBdl);
1203	return offCurBdle >= cbCurBdl;
1204	}
1205
1206	/**
1207	* Checks if the current BDLE needs a completion IRQ.
1208	*
1209	* @retval true if IRQ is needed.
1210	* @retval false if not.
1211	* @param pStreamShared The stream to check.
1212	*/
1213	DECLINLINE(bool) hdaStreamDmaBufNeedsIrq(PHDASTREAM pStreamShared)
1214	{
1215	uint8_t const idxBdle = pStreamShared->State.idxCurBdle;
1216	AssertReturn(idxBdle < pStreamShared->State.cBdles, false);
1217	return (pStreamShared->State.aBdl[idxBdle].fFlags & HDA_BDLE_F_IOC) != 0;
1218	}
1219
1220	/**
1221	* Advances the DMA engine to the next BDLE.
1222	*
1223	* @param pStreamShared The stream which DMA engine is to be updated.
1224	*/
1225	DECLINLINE(void) hdaStreamDmaBufAdvanceToNext(PHDASTREAM pStreamShared)
1226	{
1227	uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1228	Assert(pStreamShared->State.offCurBdle == pStreamShared->State.aBdl[idxBdle].cb);
1229
1230	if (idxBdle < pStreamShared->State.cBdles - 1)
1231	idxBdle++;
1232	else
1233	idxBdle = 0;
1234	pStreamShared->State.idxCurBdle = idxBdle;
1235	pStreamShared->State.offCurBdle = 0;
1236	}
1237
1238	#endif /* defined(IN_RING3) \|\| defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA) */
1239	#ifdef IN_RING3
1240
1241	/**
1242	* Common do-DMA prologue code.
1243	*
1244	* @retval true if DMA processing can take place
1245	* @retval false if caller should return immediately.
1246	* @param pThis The shared HDA device state.
1247	* @param pStreamShared HDA stream to update (shared).
1248	* @param pStreamR3 HDA stream to update (ring-3).
1249	* @param uSD The stream ID (for asserting).
1250	* @param tsNowNs The current RTTimeNano() value.
1251	* @param pszFunction The function name (for logging).
1252	*/
1253	DECLINLINE(bool) hdaR3StreamDoDmaPrologue(PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD,
1254	uint64_t tsNowNs, const char *pszFunction)
1255	{
1256	RT_NOREF(uSD, pszFunction);
1257
1258	/*
1259	* Check if we should skip town...
1260	*/
1261	/* Stream not running (anymore)? */
1262	if (pStreamShared->State.fRunning)
1263	{ /* likely */ }
1264	else
1265	{
1266	Log3(("%s: [SD%RU8] Not running, skipping transfer\n", pszFunction, uSD));
1267	return false;
1268	}
1269
1270	if (!(HDA_STREAM_REG(pThis, STS, uSD) & HDA_SDSTS_BCIS))
1271	{ /* likely */ }
1272	else
1273	{
1274	/** @todo r=bird: This is a bit fishy. We should make effort the reschedule
1275	* the transfer immediately after the guest clears the interrupt.
1276	* The same fishy code is present in AC'97 with just a little
1277	* explanation as here, see @bugref{9890#c95}.
1278	*
1279	* The reasoning is probably that the developer noticed some windows
1280	* versions don't like having their BCIS interrupts bundled. There were
1281	* comments to that effect elsewhere, probably as a result of a fixed
1282	* uTimerHz approach to DMA scheduling. However, pausing DMA for a
1283	* period isn't going to help us with the host backends, as they don't
1284	* pause and will want samples ASAP. So, we should at least unpause
1285	* DMA as quickly as we possible when BCIS is cleared. We might even
1286	* not skip it iff the DMA work here doesn't involve raising any IOC,
1287	* which is possible although unlikely. */
1288	Log3(("%s: [SD%RU8] BCIS bit set, skipping transfer\n", pszFunction, uSD));
1289	STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaSkippedPendingBcis);
1290	Log(("%s: [SD%RU8] BCIS bit set, skipping transfer\n", pszFunction, uSD));
1291	# ifdef HDA_STRICT
1292	/* Timing emulation bug or guest is misbehaving -- let me know. */
1293	AssertMsgFailed(("%s: BCIS bit for stream #%RU8 still set when it shouldn't\n", pszFunction, uSD));
1294	# endif
1295	return false;
1296	}
1297
1298	/*
1299	* Stream sanity checks.
1300	*/
1301	/* Register sanity checks. */
1302	Assert(uSD < HDA_MAX_STREAMS);
1303	Assert(pStreamShared->u64BDLBase);
1304	Assert(pStreamShared->u32CBL);
1305	Assert(pStreamShared->u8FIFOS);
1306
1307	/* State sanity checks. */
1308	Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false);
1309	Assert(ASMAtomicReadBool(&pStreamShared->State.fRunning));
1310
1311	/*
1312	* Some timestamp stuff for logging/debugging.
1313	*/
1314	/const uint64_t tsNowNs = RTTimeNanoTS();/
1315	Log3(("%s: [SD%RU8] tsDeltaNs=%'RU64 ns\n", pszFunction, uSD, tsNowNs - pStreamShared->State.tsLastTransferNs));
1316	pStreamShared->State.tsLastTransferNs = tsNowNs;
1317
1318	return true;
1319	}
1320
1321	/**
1322	* Common do-DMA epilogue.
1323	*
1324	* @param pDevIns The device instance.
1325	* @param pStreamShared The HDA stream (shared).
1326	* @param pStreamR3 The HDA stream (ring-3).
1327	*/
1328	DECLINLINE(void) hdaR3StreamDoDmaEpilogue(PPDMDEVINS pDevIns, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
1329	{
1330	/*
1331	* We must update this in the epilogue rather than in the prologue
1332	* as it is used for WALCLK calculation and we must make sure the
1333	* guest doesn't think we've processed the current period till we
1334	* actually have.
1335	*/
1336	pStreamShared->State.tsTransferLast = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer);
1337
1338	/*
1339	* Update the buffer statistics.
1340	*/
1341	pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1342	}
1343
1344	#endif /* IN_RING3 */
1345
1346	#if defined(IN_RING3) \|\| defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA)
1347	/**
1348	* Completes a BDLE at the end of a DMA loop iteration, if possible.
1349	*
1350	* @retval true if buffer completed and new loaded.
1351	* @retval false if buffer not completed.
1352	* @param pDevIns The device instance.
1353	* @param pThis The shared HDA device state.
1354	* @param pStreamShared HDA stream to update (shared).
1355	* @param pszFunction The function name (for logging).
1356	*/
1357	DECLINLINE(bool) hdaStreamDoDmaMaybeCompleteBuffer(PPDMDEVINS pDevIns, PHDASTATE pThis,
1358	PHDASTREAM pStreamShared, const char *pszFunction)
1359	{
1360	RT_NOREF(pszFunction);
1361
1362	/*
1363	* Is the buffer descriptor complete.
1364	*/
1365	if (hdaStreamDmaBufIsComplete(pStreamShared))
1366	{
1367	Log3(("%s: [SD%RU8] Completed BDLE%u %#RX64 LB %#RX32 fFlags=%#x\n", pszFunction, pStreamShared->u8SD,
1368	pStreamShared->State.idxCurBdle, pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].GCPhys,
1369	pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].cb,
1370	pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].fFlags));
1371
1372	#if 0 /* Moved to the transfer loops */
1373	/*
1374	* Update the stream's current position.
1375	*
1376	* Do this as accurate and close to the actual data transfer as possible.
1377	* All guests rely on this, depending on the mechanism they use (LPIB register or DMA counters).
1378	*
1379	* Note for Windows 10: The OS' driver is very picky about when the (DMA) positions get updated!
1380	* Not doing this at the right time will result in ugly sound crackles!
1381	*/
1382	hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, hdaStreamDmaBufGetSize(pStreamShared));
1383	#endif
1384
1385	/* Does the current BDLE require an interrupt to be sent? */
1386	if (hdaStreamDmaBufNeedsIrq(pStreamShared))
1387	{
1388	/* If the IOCE ("Interrupt On Completion Enable") bit of the SDCTL
1389	register is set we need to generate an interrupt. */
1390	if (HDA_STREAM_REG(pThis, CTL, pStreamShared->u8SD) & HDA_SDCTL_IOCE)
1391	{
1392	/* Assert the interrupt before actually fetching the next BDLE below. */
1393	pStreamShared->State.cTransferPendingInterrupts = 1;
1394	Log3(("%s: [SD%RU8] Scheduling interrupt\n", pszFunction, pStreamShared->u8SD));
1395
1396	/* Trigger an interrupt first and let hdaRegWriteSDSTS() deal with
1397	* ending / beginning of a period. */
1398	/** @todo r=bird: What does the above comment mean? */
1399	HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) \|= HDA_SDSTS_BCIS;
1400	HDA_PROCESS_INTERRUPT(pDevIns, pThis);
1401	}
1402	}
1403
1404	/*
1405	* Advance to the next BDLE.
1406	*/
1407	hdaStreamDmaBufAdvanceToNext(pStreamShared);
1408	return true;
1409	}
1410
1411	Log3(("%s: [SD%RU8] Incomplete BDLE%u %#RX64 LB %#RX32 fFlags=%#x: off=%#RX32\n", pszFunction, pStreamShared->u8SD,
1412	pStreamShared->State.idxCurBdle, pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].GCPhys,
1413	pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].cb,
1414	pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].fFlags, pStreamShared->State.offCurBdle));
1415	return false;
1416	}
1417	#endif /* IN_RING3 \|\| VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
1418
1419
1420	#ifdef IN_RING3
1421
1422	/**
1423	* Does DMA transfer for an HDA input stream.
1424	*
1425	* Reads audio data from the HDA stream's internal DMA buffer and writing to
1426	* guest memory.
1427	*
1428	* @param pDevIns The device instance.
1429	* @param pThis The shared HDA device state.
1430	* @param pStreamShared HDA stream to update (shared).
1431	* @param pStreamR3 HDA stream to update (ring-3).
1432	* @param cbToConsume The max amount of data to consume from the
1433	* internal DMA buffer. The caller will make sure
1434	* this is always the transfer size fo the current
1435	* period (unless something is seriously wrong).
1436	* @param fWriteSilence Whether to feed the guest silence rather than
1437	* fetching bytes from the internal DMA buffer.
1438	* This is set initially while we pre-buffer a
1439	* little bit of input, so we can better handle
1440	* time catch-ups and other schduling fun.
1441	* @param tsNowNs The current RTTimeNano() value.
1442	*
1443	* @remarks Caller owns the stream lock.
1444	*/
1445	static void hdaR3StreamDoDmaInput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
1446	PHDASTREAMR3 pStreamR3, uint32_t const cbToConsume, bool fWriteSilence, uint64_t tsNowNs)
1447	{
1448	uint8_t const uSD = pStreamShared->u8SD;
1449	LogFlowFunc(("ENTER - #%u cbToConsume=%#x%s\n", uSD, cbToConsume, fWriteSilence ? " silence" : ""));
1450
1451	/*
1452	* Common prologue.
1453	*/
1454	if (hdaR3StreamDoDmaPrologue(pThis, pStreamShared, pStreamR3, uSD, tsNowNs, "hdaR3StreamDoDmaInput"))
1455	{ /* likely */ }
1456	else
1457	return;
1458
1459	/*
1460	*
1461	* The DMA copy loop.
1462	*
1463	*/
1464	uint8_t abBounce[4096 + 128]; /* Most guest does at most 4KB BDLE. So, 4KB + space for a partial frame to reduce loops. */
1465	uint32_t cbBounce = 0; /* in case of incomplete frames between buffer segments */
1466	PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1467	uint32_t cbLeft = cbToConsume;
1468	Assert(cbLeft == pStreamShared->State.cbCurDmaPeriod);
1469	Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1470
1471	while (cbLeft > 0)
1472	{
1473	STAM_PROFILE_START(&pThis->StatIn, a);
1474
1475	/*
1476	* Figure out how much we can read & write in this iteration.
1477	*/
1478	uint32_t cbChunk = 0;
1479	RTGCPHYS GCPhys = hdaStreamDmaBufGet(pStreamShared, &cbChunk);
1480
1481	/* If we're writing silence. */
1482	uint32_t cbWritten = 0;
1483	if (!fWriteSilence)
1484	{
1485	if (cbChunk <= cbLeft)
1486	{ /* very likely */ }
1487	else
1488	cbChunk = cbLeft;
1489
1490	/*
1491	* Write the host data directly into the guest buffers.
1492	*/
1493	while (cbChunk > 0)
1494	{
1495	/* Grab internal DMA buffer space and read into it. */
1496	void /const/ *pvBufSrc;
1497	size_t cbBufSrc;
1498	RTCircBufAcquireReadBlock(pCircBuf, cbChunk, &pvBufSrc, &cbBufSrc);
1499	AssertBreakStmt(cbBufSrc, RTCircBufReleaseReadBlock(pCircBuf, 0));
1500
1501	int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, GCPhys, pvBufSrc, cbBufSrc);
1502	AssertRC(rc2);
1503
1504	# ifdef HDA_DEBUG_SILENCE
1505	fix me if relevant;
1506	# endif
1507	if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1508	{ /* likely */ }
1509	else
1510	AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufSrc, cbBufSrc, 0 /* fFlags */);
1511
1512	# ifdef VBOX_WITH_DTRACE
1513	VBOXDD_HDA_STREAM_DMA_IN((uint32_t)uSD, (uint32_t)cbBufSrc, pStreamShared->State.offRead);
1514	# endif
1515	pStreamShared->State.offRead += cbBufSrc;
1516	RTCircBufReleaseReadBlock(pCircBuf, cbBufSrc);
1517	STAM_COUNTER_ADD(&pThis->StatBytesWritten, cbBufSrc);
1518
1519	/* advance */
1520	cbChunk -= (uint32_t)cbBufSrc;
1521	cbWritten += (uint32_t)cbBufSrc;
1522	GCPhys += cbBufSrc;
1523	pStreamShared->State.offCurBdle += (uint32_t)cbBufSrc;
1524	}
1525	}
1526	/*
1527	* We've got some initial silence to write, or we need to do
1528	* channel mapping. We produce guest output into the bounce buffer,
1529	* which is then copied into guest memory. The bounce buffer may keep
1530	* partial frames there for the next BDLE, if an BDLE isn't frame aligned.
1531	*
1532	* Note! cbLeft is relative to the input (host) frame size.
1533	* cbChunk OTOH is relative to output (guest) size.
1534	*/
1535	else
1536	{
1537	/** @todo clean up host/guest props distinction, they're the same now w/o the
1538	* mapping done by the mixer rather than us. */
1539	PCPDMAUDIOPCMPROPS pGuestProps = &pStreamShared->State.Cfg.Props;
1540	Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1541	uint32_t const cbLeftGuest = PDMAudioPropsFramesToBytes(pGuestProps,
1542	PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props,
1543	cbLeft));
1544	if (cbChunk <= cbLeftGuest)
1545	{ /* very likely */ }
1546	else
1547	cbChunk = cbLeftGuest;
1548
1549	/*
1550	* Work till we've covered the chunk.
1551	*/
1552	Log5Func(("loop0: GCPhys=%RGp cbChunk=%#x + cbBounce=%#x\n", GCPhys, cbChunk, cbBounce));
1553	while (cbChunk > 0)
1554	{
1555	/* Figure out how much we need to convert into the bounce buffer: */
1556	uint32_t cbGuest = PDMAudioPropsRoundUpBytesToFrame(pGuestProps, cbChunk - cbBounce);
1557	uint32_t cFrames = PDMAudioPropsBytesToFrames(pGuestProps, RT_MIN(cbGuest, sizeof(abBounce) - cbBounce));
1558
1559	cbGuest = PDMAudioPropsFramesToBytes(pGuestProps, cFrames);
1560	PDMAudioPropsClearBuffer(pGuestProps, &abBounce[cbBounce], cbGuest, cFrames);
1561	cbGuest += cbBounce;
1562
1563	/* Write it to the guest buffer. */
1564	uint32_t cbGuestActual = RT_MIN(cbGuest, cbChunk);
1565	int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, GCPhys, abBounce, cbGuestActual);
1566	AssertRC(rc2);
1567	STAM_COUNTER_ADD(&pThis->StatBytesWritten, cbGuestActual);
1568
1569	/* advance */
1570	cbWritten += cbGuestActual;
1571	cbChunk -= cbGuestActual;
1572	GCPhys += cbGuestActual;
1573	pStreamShared->State.offCurBdle += cbGuestActual;
1574
1575	cbBounce = cbGuest - cbGuestActual;
1576	if (cbBounce)
1577	memmove(abBounce, &abBounce[cbGuestActual], cbBounce);
1578
1579	Log5Func((" loop1: GCPhys=%RGp cbGuestActual=%#x cbBounce=%#x cFrames=%#x\n", GCPhys, cbGuestActual, cbBounce, cFrames));
1580	}
1581	Log5Func(("loop0: GCPhys=%RGp cbBounce=%#x cbLeft=%#x\n", GCPhys, cbBounce, cbLeft - cbWritten));
1582	}
1583
1584	cbLeft -= cbWritten;
1585	STAM_PROFILE_STOP(&pThis->StatIn, a);
1586
1587	/*
1588	* Complete the buffer if necessary (common with the output DMA code).
1589	*
1590	* Must update the DMA position before we do this as the buffer IRQ may
1591	* fire on another vCPU and run in parallel to us, although it is very
1592	* unlikely it can make much progress as long as we're sitting on the
1593	* lock, it could still read the DMA position (Linux won't, as it reads
1594	* WALCLK and possibly SDnSTS before the DMA position).
1595	*/
1596	hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, cbWritten);
1597	hdaStreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaR3StreamDoDmaInput");
1598	}
1599
1600	Assert(cbLeft == 0); /* There shall be no break statements in the above loop, so cbLeft is always zero here! */
1601	AssertMsg(cbBounce == 0, ("%#x\n", cbBounce));
1602
1603	/*
1604	* Common epilogue.
1605	*/
1606	hdaR3StreamDoDmaEpilogue(pDevIns, pStreamShared, pStreamR3);
1607
1608	/*
1609	* Log and leave.
1610	*/
1611	Log3Func(("LEAVE - [SD%RU8] %#RX32/%#RX32 @ %#RX64 - cTransferPendingInterrupts=%RU8\n",
1612	uSD, cbToConsume, pStreamShared->State.cbCurDmaPeriod, pStreamShared->State.offRead - cbToConsume,
1613	pStreamShared->State.cTransferPendingInterrupts));
1614	}
1615
1616
1617	/**
1618	* Input streams: Pulls data from the mixer, putting it in the internal DMA
1619	* buffer.
1620	*
1621	* @param pStreamShared HDA stream to update (shared).
1622	* @param pStreamR3 HDA stream to update (ring-3 bits).
1623	* @param pSink The mixer sink to pull from.
1624	*/
1625	static void hdaR3StreamPullFromMixer(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink)
1626	{
1627	# ifdef LOG_ENABLED
1628	uint64_t const offWriteOld = pStreamShared->State.offWrite;
1629	# endif
1630	pStreamShared->State.offWrite = AudioMixerSinkTransferToCircBuf(pSink,
1631	pStreamR3->State.pCircBuf,
1632	pStreamShared->State.offWrite,
1633	pStreamR3->u8SD,
1634	pStreamR3->Dbg.Runtime.fEnabled
1635	? pStreamR3->Dbg.Runtime.pFileStream : NULL);
1636
1637	Log3Func(("[SD%RU8] transferred=%#RX64 bytes -> @%#RX64\n", pStreamR3->u8SD,
1638	pStreamShared->State.offWrite - offWriteOld, pStreamShared->State.offWrite));
1639
1640	/* Update buffer stats. */
1641	pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1642	}
1643
1644
1645	/**
1646	* Does DMA transfer for an HDA output stream.
1647	*
1648	* This transfers one DMA timer period worth of data from the guest and into the
1649	* internal DMA buffer.
1650	*
1651	* @param pDevIns The device instance.
1652	* @param pThis The shared HDA device state.
1653	* @param pStreamShared HDA stream to update (shared).
1654	* @param pStreamR3 HDA stream to update (ring-3).
1655	* @param cbToProduce The max amount of data to produce (i.e. put into
1656	* the circular buffer). Unless something is going
1657	* seriously wrong, this will always be transfer
1658	* size for the current period.
1659	* @param tsNowNs The current RTTimeNano() value.
1660	*
1661	* @remarks Caller owns the stream lock.
1662	*/
1663	static void hdaR3StreamDoDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
1664	PHDASTREAMR3 pStreamR3, uint32_t const cbToProduce, uint64_t tsNowNs)
1665	{
1666	uint8_t const uSD = pStreamShared->u8SD;
1667	LogFlowFunc(("ENTER - #%u cbToProduce=%#x\n", uSD, cbToProduce));
1668
1669	/*
1670	* Common prologue.
1671	*/
1672	if (hdaR3StreamDoDmaPrologue(pThis, pStreamShared, pStreamR3, uSD, tsNowNs, "hdaR3StreamDoDmaOutput"))
1673	{ /* likely */ }
1674	else
1675	return;
1676
1677	/*
1678	*
1679	* The DMA copy loop.
1680	*
1681	*/
1682	# if 0
1683	uint8_t abBounce[4096 + 128]; /* Most guest does at most 4KB BDLE. So, 4KB + space for a partial frame to reduce loops. */
1684	uint32_t cbBounce = 0; /* in case of incomplete frames between buffer segments */
1685	# endif
1686	PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1687	uint32_t cbLeft = cbToProduce;
1688	# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
1689	Assert(cbLeft <= pStreamShared->State.cbCurDmaPeriod); /* a little pointless with the DMA'ing on LPIB read. */
1690	# else
1691	Assert(cbLeft == pStreamShared->State.cbCurDmaPeriod);
1692	# endif
1693	Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1694
1695	while (cbLeft > 0)
1696	{
1697	STAM_PROFILE_START(&pThis->StatOut, a);
1698
1699	/*
1700	* Figure out how much we can read & write in this iteration.
1701	*/
1702	uint32_t cbChunk = 0;
1703	RTGCPHYS GCPhys = hdaStreamDmaBufGet(pStreamShared, &cbChunk);
1704
1705	/* Need to diverge if the BDLEs contain misaligned entries. */
1706	uint32_t cbRead = 0;
1707	# if 0
1708	if (/** @todo pStreamShared->State.fFrameAlignedBuffers */)
1709	# endif
1710	{
1711	if (cbChunk <= cbLeft)
1712	{ /* very likely */ }
1713	else
1714	cbChunk = cbLeft;
1715
1716	/*
1717	* Read the guest data directly into the internal DMA buffer.
1718	*/
1719	while (cbChunk > 0)
1720	{
1721	/* Grab internal DMA buffer space and read into it. */
1722	void *pvBufDst;
1723	size_t cbBufDst;
1724	RTCircBufAcquireWriteBlock(pCircBuf, cbChunk, &pvBufDst, &cbBufDst);
1725	AssertBreakStmt(cbBufDst, RTCircBufReleaseWriteBlock(pCircBuf, 0));
1726
1727	int rc2 = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, pvBufDst, cbBufDst);
1728	AssertRC(rc2);
1729
1730	# ifdef HDA_DEBUG_SILENCE
1731	fix me if relevant;
1732	# endif
1733	if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1734	{ /* likely */ }
1735	else
1736	AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst, 0 /* fFlags */);
1737
1738	# ifdef VBOX_WITH_DTRACE
1739	VBOXDD_HDA_STREAM_DMA_OUT((uint32_t)uSD, (uint32_t)cbBufDst, pStreamShared->State.offWrite);
1740	# endif
1741	pStreamShared->State.offWrite += cbBufDst;
1742	RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
1743	STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBufDst);
1744
1745	/* advance */
1746	cbChunk -= (uint32_t)cbBufDst;
1747	cbRead += (uint32_t)cbBufDst;
1748	GCPhys += cbBufDst;
1749	pStreamShared->State.offCurBdle += (uint32_t)cbBufDst;
1750	}
1751	}
1752	# if 0
1753	/*
1754	* Need to map the frame content, so we need to read the guest data
1755	* into a temporary buffer, though the output can be directly written
1756	* into the internal buffer as it is assumed to be frame aligned.
1757	*
1758	* Note! cbLeft is relative to the output frame size.
1759	* cbChunk OTOH is relative to input size.
1760	*/
1761	else
1762	{
1763	/** @todo clean up host/guest props distinction, they're the same now w/o the
1764	* mapping done by the mixer rather than us. */
1765	PCPDMAUDIOPCMPROPS pGuestProps = &pStreamShared->State.Cfg.Props;
1766	Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1767	uint32_t const cbLeftGuest = PDMAudioPropsFramesToBytes(pGuestProps,
1768	PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props,
1769	cbLeft));
1770	if (cbChunk <= cbLeftGuest)
1771	{ /* very likely */ }
1772	else
1773	cbChunk = cbLeftGuest;
1774
1775	/*
1776	* Loop till we've covered the chunk.
1777	*/
1778	Log5Func(("loop0: GCPhys=%RGp cbChunk=%#x + cbBounce=%#x\n", GCPhys, cbChunk, cbBounce));
1779	while (cbChunk > 0)
1780	{
1781	/* Read into the bounce buffer. */
1782	uint32_t const cbToRead = RT_MIN(cbChunk, sizeof(abBounce) - cbBounce);
1783	int rc2 = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &abBounce[cbBounce], cbToRead);
1784	AssertRC(rc2);
1785	cbBounce += cbToRead;
1786
1787	/* Convert the size to whole frames and a remainder. */
1788	uint32_t cFrames = PDMAudioPropsBytesToFrames(pGuestProps, cbBounce);
1789	uint32_t const cbRemainder = cbBounce - PDMAudioPropsFramesToBytes(pGuestProps, cFrames);
1790	Log5Func((" loop1: GCPhys=%RGp cbToRead=%#x cbBounce=%#x cFrames=%#x\n", GCPhys, cbToRead, cbBounce, cFrames));
1791
1792	/*
1793	* Convert from the bounce buffer and into the internal DMA buffer.
1794	*/
1795	uint32_t offBounce = 0;
1796	while (cFrames > 0)
1797	{
1798	void *pvBufDst;
1799	size_t cbBufDst;
1800	RTCircBufAcquireWriteBlock(pCircBuf, PDMAudioPropsFramesToBytes(&pStreamShared->State.Cfg.Props, cFrames),
1801	&pvBufDst, &cbBufDst);
1802
1803	uint32_t const cFramesToConvert = PDMAudioPropsBytesToFrames(&pStreamShared->State.Cfg.Props, (uint32_t)cbBufDst);
1804	Assert(PDMAudioPropsFramesToBytes(&pStreamShared->State.Cfg.Props, cFramesToConvert) == cbBufDst);
1805	Assert(cFramesToConvert > 0);
1806	Assert(cFramesToConvert <= cFrames);
1807
1808	pStreamR3->State.Mapping.pfnGuestToHost(pvBufDst, &abBounce[offBounce], cFramesToConvert,
1809	&pStreamR3->State.Mapping);
1810	Log5Func((" loop2: offBounce=%#05x cFramesToConvert=%#05x cbBufDst=%#x%s\n",
1811	offBounce, cFramesToConvert, cbBufDst, ASMMemIsZero(pvBufDst, cbBufDst) ? " all zero" : ""));
1812
1813	# ifdef HDA_DEBUG_SILENCE
1814	fix me if relevant;
1815	# endif
1816	if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1817	{ /* likely */ }
1818	else
1819	AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst, 0 /* fFlags */);
1820
1821	pStreamR3->State.offWrite += cbBufDst;
1822	RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
1823	STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBufDst);
1824
1825	/* advance */
1826	cbLeft -= (uint32_t)cbBufDst;
1827	cFrames -= cFramesToConvert;
1828	offBounce += PDMAudioPropsFramesToBytes(pGuestProps, cFramesToConvert);
1829	}
1830
1831	/* advance */
1832	cbChunk -= cbToRead;
1833	GCPhys += cbToRead;
1834	pStreamShared->State.offCurBdle += cbToRead;
1835	if (cbRemainder)
1836	memmove(&abBounce[0], &abBounce[cbBounce - cbRemainder], cbRemainder);
1837	cbBounce = cbRemainder;
1838	}
1839	Log5Func(("loop0: GCPhys=%RGp cbBounce=%#x cbLeft=%#x\n", GCPhys, cbBounce, cbLeft));
1840	}
1841	# endif
1842
1843	cbLeft -= cbRead;
1844	STAM_PROFILE_STOP(&pThis->StatOut, a);
1845
1846	/*
1847	* Complete the buffer if necessary (common with the input DMA code).
1848	*
1849	* Must update the DMA position before we do this as the buffer IRQ may
1850	* fire on another vCPU and run in parallel to us, although it is very
1851	* unlikely it can make much progress as long as we're sitting on the
1852	* lock, it could still read the DMA position (Linux won't, as it reads
1853	* WALCLK and possibly SDnSTS before the DMA position).
1854	*/
1855	hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, cbRead);
1856	hdaStreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaR3StreamDoDmaOutput");
1857	}
1858
1859	Assert(cbLeft == 0); /* There shall be no break statements in the above loop, so cbLeft is always zero here! */
1860	# if 0
1861	AssertMsg(cbBounce == 0, ("%#x\n", cbBounce));
1862	# endif
1863
1864	/*
1865	* Common epilogue.
1866	*/
1867	hdaR3StreamDoDmaEpilogue(pDevIns, pStreamShared, pStreamR3);
1868
1869	/*
1870	* Log and leave.
1871	*/
1872	Log3Func(("LEAVE - [SD%RU8] %#RX32/%#RX32 @ %#RX64 - cTransferPendingInterrupts=%RU8\n",
1873	uSD, cbToProduce, pStreamShared->State.cbCurDmaPeriod, pStreamShared->State.offWrite - cbToProduce,
1874	pStreamShared->State.cTransferPendingInterrupts));
1875	}
1876
1877	#endif /* IN_RING3 */
1878	#ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
1879
1880	/**
1881	* Do DMA output transfer on LPIB/WALCLK register access.
1882	*
1883	* @returns VINF_SUCCESS or VINF_IOM_R3_MMIO_READ.
1884	* @param pDevIns The device instance.
1885	* @param pThis The shared instance data.
1886	* @param pStreamShared The shared stream data.
1887	* @param tsNow The current time on the timer clock.
1888	* @param cbToTransfer How much to transfer.
1889	*/
1890	VBOXSTRICTRC hdaStreamDoOnAccessDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
1891	uint64_t tsNow, uint32_t cbToTransfer)
1892	{
1893	AssertReturn(cbToTransfer > 0, VINF_SUCCESS);
1894	int rc = VINF_SUCCESS;
1895
1896	/*
1897	* Check if we're exceeding the available buffer, go to ring-3 to
1898	* handle that (we would perhaps always take this path when in ring-3).
1899	*/
1900	uint32_t cbDma = pStreamShared->State.cbDma;
1901	ASMCompilerBarrier();
1902	if ( cbDma >= sizeof(pStreamShared->State.abDma) /* paranoia */
1903	\|\| cbToTransfer >= sizeof(pStreamShared->State.abDma) /* paranoia */
1904	\|\| cbDma + cbToTransfer > sizeof(pStreamShared->State.abDma))
1905	{
1906	# ifndef IN_RING3
1907	STAM_REL_COUNTER_INC(&pThis->StatAccessDmaOutputToR3);
1908	LogFlowFunc(("[SD%RU8] out of DMA buffer space (%#x, need %#x) -> VINF_IOM_R3_MMIO_READ\n",
1909	pStreamShared->u8SD, sizeof(pStreamShared->State.abDma) - pStreamShared->State.cbDma, cbToTransfer));
1910	return VINF_IOM_R3_MMIO_READ;
1911	# else /* IN_RING3 */
1912	/*
1913	* Flush the bounce buffer, then do direct transfers to the
1914	* internal DMA buffer (updates LPIB).
1915	*/
1916	PHDASTATER3 const pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
1917	uintptr_t const idxStream = pStreamShared->u8SD;
1918	AssertReturn(idxStream < RT_ELEMENTS(pThisCC->aStreams), VERR_INTERNAL_ERROR_4);
1919	PHDASTREAMR3 const pStreamR3 = &pThisCC->aStreams[idxStream];
1920
1921	hdaR3StreamFlushDmaBounceBufferOutput(pStreamShared, pStreamR3);
1922
1923	uint32_t cbStreamFree = hdaR3StreamGetFree(pStreamR3);
1924	if (cbStreamFree >= cbToTransfer)
1925	{ /* likely */ }
1926	else
1927	{
1928	PAUDMIXSINK pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
1929	if (pSink)
1930	cbStreamFree = hdaR3StreamHandleDmaBufferOverrun(pStreamShared, pStreamR3, pSink, cbToTransfer, RTTimeNanoTS(),
1931	"hdaStreamDoOnAccessDmaOutput", cbStreamFree);
1932	else
1933	{
1934	LogFunc(("[SD%RU8] No sink and insufficient internal DMA buffer space (%#x) - won't do anything\n",
1935	pStreamShared->u8SD, cbStreamFree));
1936	return VINF_SUCCESS;
1937	}
1938	cbToTransfer = RT_MIN(cbToTransfer, cbStreamFree);
1939	if (cbToTransfer < PDMAudioPropsFrameSize(&pStreamShared->State.Cfg.Props))
1940	{
1941	LogFunc(("[SD%RU8] No internal DMA buffer space (%#x) - won't do anything\n", pStreamShared->u8SD, cbStreamFree));
1942	return VINF_SUCCESS;
1943	}
1944	}
1945	hdaR3StreamDoDmaOutput(pDevIns, pThis, pStreamShared, pStreamR3, cbToTransfer, RTTimeNanoTS());
1946	pStreamShared->State.cbDmaTotal += cbToTransfer;
1947	# endif /* IN_RING3 */
1948	}
1949	else
1950	{
1951	/*
1952	* Transfer into the DMA bounce buffer.
1953	*/
1954	LogFlowFunc(("[SD%RU8] Transfering %#x bytes to DMA bounce buffer (cbDma=%#x cbDmaTotal=%#x) (%p/%u)\n",
1955	pStreamShared->u8SD, cbToTransfer, cbDma, pStreamShared->State.cbDmaTotal, pStreamShared, pStreamShared->u8SD));
1956	uint32_t cbLeft = cbToTransfer;
1957	do
1958	{
1959	uint32_t cbChunk = 0;
1960	RTGCPHYS GCPhys = hdaStreamDmaBufGet(pStreamShared, &cbChunk);
1961
1962	bool fMustAdvanceBuffer;
1963	if (cbLeft < cbChunk)
1964	{
1965	fMustAdvanceBuffer = false;
1966	cbChunk = cbLeft;
1967	}
1968	else
1969	fMustAdvanceBuffer = true;
1970
1971	/* Read the guest data directly into the DMA bounce buffer. */
1972	int rc2 = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &pStreamShared->State.abDma[cbDma], cbChunk);
1973	AssertRC(rc2);
1974
1975	/* We update offWrite and StatBytesRead here even if we haven't moved the data
1976	to the internal DMA buffer yet, because we want the dtrace even to fire here. */
1977	# ifdef VBOX_WITH_DTRACE
1978	VBOXDD_HDA_STREAM_DMA_OUT((uint32_t)pStreamShared->u8SD, cbChunk, pStreamShared->State.offWrite);
1979	# endif
1980	pStreamShared->State.offWrite += cbChunk;
1981	STAM_COUNTER_ADD(&pThis->StatBytesRead, cbChunk);
1982
1983	/* advance */
1984	pStreamShared->State.offCurBdle += cbChunk;
1985	pStreamShared->State.cbDmaTotal += cbChunk;
1986	cbDma += cbChunk;
1987	pStreamShared->State.cbDma = cbDma;
1988	cbLeft -= cbChunk;
1989	Log6Func(("cbLeft=%#x cbDma=%#x cbDmaTotal=%#x offCurBdle=%#x idxCurBdle=%#x (%p/%u)\n",
1990	cbLeft, cbDma, pStreamShared->State.cbDmaTotal, pStreamShared->State.offCurBdle,
1991	pStreamShared->State.idxCurBdle, pStreamShared, pStreamShared->u8SD));
1992
1993	/* Next buffer. */
1994	bool fAdvanced = hdaStreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaStreamDoOnAccessDmaOutput");
1995	AssertMsgStmt(fMustAdvanceBuffer == fAdvanced, ("%d %d\n", fMustAdvanceBuffer, fAdvanced), rc = VERR_INTERNAL_ERROR_3);
1996	} while (cbLeft > 0);
1997
1998	/*
1999	* Advance LPIB and update the last transfer time (for WALCLK).
2000	*/
2001	pStreamShared->State.tsTransferLast = tsNow;
2002	hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, cbToTransfer - cbLeft);
2003	}
2004
2005	# ifdef VBOX_STRICT
2006	uint32_t idxSched = pStreamShared->State.idxSchedule;
2007	AssertStmt(idxSched < RT_MIN(RT_ELEMENTS(pStreamShared->State.aSchedule), pStreamShared->State.cSchedule), idxSched = 0);
2008	uint32_t const cbPeriod = pStreamShared->State.aSchedule[idxSched].cbPeriod;
2009	AssertMsg(pStreamShared->State.cbDmaTotal < cbPeriod, ("%#x vs %#x\n", pStreamShared->State.cbDmaTotal, cbPeriod));
2010	# endif
2011
2012	STAM_REL_COUNTER_INC(&pThis->StatAccessDmaOutput);
2013	return rc;
2014	}
2015
2016
2017	/**
2018	* Consider doing DMA output transfer on LPIB/WALCLK register access.
2019	*
2020	* @returns VINF_SUCCESS or VINF_IOM_R3_MMIO_READ.
2021	* @param pDevIns The device instance.
2022	* @param pThis The shared instance data.
2023	* @param pStreamShared The shared stream data.
2024	* @param tsNow The current time on the timer clock. Used to do the
2025	* calculation.
2026	*/
2027	VBOXSTRICTRC hdaStreamMaybeDoOnAccessDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint64_t tsNow)
2028	{
2029	Assert(pStreamShared->State.fRunning); /* caller should check this */
2030
2031	/*
2032	* Calculate where the DMA engine should be according to the clock, if we can.
2033	*/
2034	uint32_t const cbFrame = PDMAudioPropsFrameSize(&pStreamShared->State.Cfg.Props);
2035	uint32_t const cbPeriod = pStreamShared->State.cbCurDmaPeriod;
2036	if (cbPeriod > cbFrame)
2037	{
2038	AssertMsg(pStreamShared->State.cbDmaTotal < cbPeriod, ("%#x vs %#x\n", pStreamShared->State.cbDmaTotal, cbPeriod));
2039	uint64_t const tsTransferNext = pStreamShared->State.tsTransferNext;
2040	uint32_t cbFuture;
2041	if (tsNow < tsTransferNext)
2042	{
2043	/** @todo ASSUMES nanosecond clock ticks, need to make this
2044	* resolution independent. */
2045	cbFuture = PDMAudioPropsNanoToBytes(&pStreamShared->State.Cfg.Props, tsTransferNext - tsNow);
2046	cbFuture = RT_MIN(cbFuture, cbPeriod - cbFrame);
2047	}
2048	else
2049	{
2050	/* We've hit/overshot the timer deadline. Return to ring-3 if we're
2051	not already there to increase the chance that we'll help expidite
2052	the timer. If we're already in ring-3, do all but the last frame. */
2053	# ifndef IN_RING3
2054	LogFunc(("[SD%RU8] DMA period expired: tsNow=%RU64 >= tsTransferNext=%RU64 -> VINF_IOM_R3_MMIO_READ\n",
2055	tsNow, tsTransferNext));
2056	return VINF_IOM_R3_MMIO_READ;
2057	# else
2058	cbFuture = cbPeriod - cbFrame;
2059	LogFunc(("[SD%RU8] DMA period expired: tsNow=%RU64 >= tsTransferNext=%RU64 -> cbFuture=%#x (cbPeriod=%#x - cbFrame=%#x)\n",
2060	tsNow, tsTransferNext, cbFuture, cbPeriod, cbFrame));
2061	# endif
2062	}
2063	uint32_t const offNow = PDMAudioPropsFloorBytesToFrame(&pStreamShared->State.Cfg.Props, cbPeriod - cbFuture);
2064
2065	/*
2066	* Should we transfer a little? Minimum is 64 bytes (semi-random,
2067	* suspect real hardware might be doing some cache aligned stuff,
2068	* which might soon get complicated if you take unaligned buffers
2069	* into consideration and which cache line size (128 bytes is just
2070	* as likely as 64 or 32 bytes)).
2071	*/
2072	uint32_t cbDmaTotal = pStreamShared->State.cbDmaTotal;
2073	if (cbDmaTotal + 64 <= offNow)
2074	{
2075	# ifdef LOG_ENABLED
2076	uint32_t const uOldLpib = HDA_STREAM_REG(pThis, CBL, pStreamShared->u8SD);
2077	# endif
2078	VBOXSTRICTRC rcStrict = hdaStreamDoOnAccessDmaOutput(pDevIns, pThis, pStreamShared, tsNow, offNow - cbDmaTotal);
2079	LogFlowFunc(("[SD%RU8] LPIB=%#RX32 -> LPIB=%#RX32 offNow=%#x rcStrict=%Rrc\n", pStreamShared->u8SD,
2080	uOldLpib, HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD), offNow, VBOXSTRICTRC_VAL(rcStrict) ));
2081	return rcStrict;
2082	}
2083
2084	/*
2085	* Do nothing.
2086	*/
2087	LogFlowFunc(("[SD%RU8] Skipping DMA transfer: cbDmaTotal=%#x offNow=%#x\n", pStreamShared->u8SD, cbDmaTotal, offNow));
2088	}
2089	else
2090	LogFunc(("[SD%RU8] cbPeriod=%#x <= cbFrame=%#x\n", pStreamShared->u8SD, cbPeriod, cbFrame));
2091	return VINF_SUCCESS;
2092	}
2093
2094	#endif /* VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
2095	#ifdef IN_RING3
2096
2097	/**
2098	* Output streams: Pushes data to the mixer.
2099	*
2100	* @param pStreamShared HDA stream to update (shared bits).
2101	* @param pStreamR3 HDA stream to update (ring-3 bits).
2102	* @param pSink The mixer sink to push to.
2103	* @param nsNow The current RTTimeNanoTS() value.
2104	*/
2105	static void hdaR3StreamPushToMixer(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink, uint64_t nsNow)
2106	{
2107	# ifdef LOG_ENABLED
2108	uint64_t const offReadOld = pStreamShared->State.offRead;
2109	# endif
2110	pStreamShared->State.offRead = AudioMixerSinkTransferFromCircBuf(pSink,
2111	pStreamR3->State.pCircBuf,
2112	pStreamShared->State.offRead,
2113	pStreamR3->u8SD,
2114	pStreamR3->Dbg.Runtime.fEnabled
2115	? pStreamR3->Dbg.Runtime.pFileStream : NULL);
2116
2117	Assert(nsNow >= pStreamShared->State.tsLastReadNs);
2118	Log3Func(("[SD%RU8] nsDeltaLastRead=%RI64 transferred=%#RX64 bytes -> @%#RX64\n", pStreamR3->u8SD,
2119	nsNow - pStreamShared->State.tsLastReadNs, pStreamShared->State.offRead - offReadOld, pStreamShared->State.offRead));
2120	RT_NOREF(pStreamShared, nsNow);
2121
2122	/* Update buffer stats. */
2123	pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
2124	}
2125
2126
2127	/**
2128	* Deals with a DMA buffer overrun.
2129	*
2130	* Makes sure we return with @a cbNeeded bytes of free space in pCircBuf.
2131	*
2132	* @returns Number of bytes free in the internal DMA buffer.
2133	* @param pStreamShared The shared data for the HDA stream.
2134	* @param pStreamR3 The ring-3 data for the HDA stream.
2135	* @param pSink The mixer sink (valid).
2136	* @param cbNeeded How much space we need (in bytes).
2137	* @param nsNow Current RTNanoTimeTS() timestamp.
2138	* @param cbStreamFree The current amount of free buffer space.
2139	* @param pszCaller The caller (for logging).
2140	*/
2141	static uint32_t hdaR3StreamHandleDmaBufferOverrun(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink,
2142	uint32_t cbNeeded, uint64_t nsNow,
2143	const char *pszCaller, uint32_t const cbStreamFree)
2144	{
2145	STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowProblems);
2146	Log(("%s: Warning! Stream #%u has insufficient space free: %#x bytes, need %#x. Will try move data out of the buffer...\n",
2147	pszCaller, pStreamShared->u8SD, cbStreamFree, cbNeeded));
2148	RT_NOREF(pszCaller, cbStreamFree);
2149
2150	int rc = AudioMixerSinkTryLock(pSink);
2151	if (RT_SUCCESS(rc))
2152	{
2153	hdaR3StreamPushToMixer(pStreamShared, pStreamR3, pSink, nsNow);
2154	AudioMixerSinkUpdate(pSink, 0, 0);
2155	AudioMixerSinkUnlock(pSink);
2156	}
2157	else
2158	RTThreadYield();
2159
2160	uint32_t const cbRet = hdaR3StreamGetFree(pStreamR3);
2161	Log(("%s: Gained %u bytes.\n", pszCaller, cbRet - cbStreamFree));
2162	if (cbRet >= cbNeeded)
2163	return cbRet;
2164
2165	/*
2166	* Unable to make sufficient space. Drop the whole buffer content.
2167	*
2168	* This is needed in order to keep the device emulation running at a
2169	* constant rate, at the cost of losing valid (but too much) data.
2170	*/
2171	STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowErrors);
2172	LogRel2(("HDA: Warning: Hit stream #%RU8 overflow, dropping %u bytes of audio data (%s)\n",
2173	pStreamShared->u8SD, hdaR3StreamGetUsed(pStreamR3), pszCaller));
2174	# ifdef HDA_STRICT
2175	AssertMsgFailed(("Hit stream #%RU8 overflow -- timing bug?\n", pStreamShared->u8SD));
2176	# endif
2177	/**
2178	*
2179	* @todo r=bird: I don't think RTCircBufReset is entirely safe w/o
2180	* owning the AIO lock. See the note in the documentation about it not being
2181	* multi-threading aware (safe). Wish I'd verified this code much earlier.
2182	* Sigh^3!
2183	*
2184	*/
2185	RTCircBufReset(pStreamR3->State.pCircBuf);
2186	pStreamShared->State.offWrite = 0;
2187	pStreamShared->State.offRead = 0;
2188	return hdaR3StreamGetFree(pStreamR3);
2189	}
2190
2191
2192	# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
2193	/**
2194	* Flushes the DMA bounce buffer content to the internal DMA buffer.
2195	*
2196	* @param pStreamShared The shared data of the stream to have its DMA bounce
2197	* buffer flushed.
2198	* @param pStreamR3 The ring-3 stream data for same.
2199	*/
2200	static void hdaR3StreamFlushDmaBounceBufferOutput(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
2201	{
2202	uint32_t cbDma = pStreamShared->State.cbDma;
2203	LogFlowFunc(("cbDma=%#x\n", cbDma));
2204	if (cbDma)
2205	{
2206	AssertReturnVoid(cbDma <= sizeof(pStreamShared->State.abDma));
2207	PRTCIRCBUF const pCircBuf = pStreamR3->State.pCircBuf;
2208	if (pCircBuf)
2209	{
2210	uint32_t offDma = 0;
2211	while (offDma < cbDma)
2212	{
2213	uint32_t const cbSrcLeft = cbDma - offDma;
2214
2215	/*
2216	* Grab a chunk of the internal DMA buffer.
2217	*/
2218	void *pvBufDst = NULL;
2219	size_t cbBufDst = 0;
2220	RTCircBufAcquireWriteBlock(pCircBuf, cbSrcLeft, &pvBufDst, &cbBufDst);
2221	if (cbBufDst > 0)
2222	{ /* likely */ }
2223	else
2224	{
2225	/* We've got buffering trouble. */
2226	RTCircBufReleaseWriteBlock(pCircBuf, 0);
2227
2228	PAUDMIXSINK pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
2229	if (pSink)
2230	hdaR3StreamHandleDmaBufferOverrun(pStreamShared, pStreamR3, pSink, cbSrcLeft, RTTimeNanoTS(),
2231	"hdaR3StreamFlushDmaBounceBufferOutput", 0 /cbStreamFree/);
2232	else
2233	{
2234	LogFunc(("Stream #%u has no sink. Dropping the rest of the data\n", pStreamR3->u8SD));
2235	break;
2236	}
2237
2238	RTCircBufAcquireWriteBlock(pCircBuf, cbSrcLeft, &pvBufDst, &cbBufDst);
2239	AssertBreakStmt(cbBufDst, RTCircBufReleaseWriteBlock(pCircBuf, 0));
2240	}
2241
2242	/*
2243	* Copy the samples into it and write it to the debug file if open.
2244	*
2245	* We do not fire the dtrace probe here nor update offRead as that was
2246	* done already (not sure that was a good idea?).
2247	*/
2248	memcpy(pvBufDst, &pStreamShared->State.abDma[offDma], cbBufDst);
2249
2250	if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
2251	{ /* likely */ }
2252	else
2253	AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst, 0 /* fFlags */);
2254
2255	RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
2256
2257	offDma += (uint32_t)cbBufDst;
2258	}
2259	}
2260
2261	/*
2262	* Mark the buffer empty.
2263	*/
2264	pStreamShared->State.cbDma = 0;
2265	}
2266	}
2267	# endif /* VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
2268
2269
2270	/**
2271	* The stream's main function when called by the timer.
2272	*
2273	* @note This function also will be called without timer invocation when
2274	* starting (enabling) the stream to minimize startup latency.
2275	*
2276	* @returns Current timer time if the timer is enabled, otherwise zero.
2277	* @param pDevIns The device instance.
2278	* @param pThis The shared HDA device state.
2279	* @param pThisCC The ring-3 HDA device state.
2280	* @param pStreamShared HDA stream to update (shared bits).
2281	* @param pStreamR3 HDA stream to update (ring-3 bits).
2282	*/
2283	uint64_t hdaR3StreamTimerMain(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
2284	PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
2285	{
2286	Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2287	Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pStreamShared->hTimer));
2288
2289	/* Do the work: */
2290	hdaR3StreamUpdateDma(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3);
2291
2292	/* Re-arm the timer if the sink is still active: */
2293	if ( pStreamShared->State.fRunning
2294	&& pStreamR3->pMixSink
2295	&& AudioMixerSinkIsActive(pStreamR3->pMixSink->pMixSink))
2296	{
2297	/* Advance the schduling: */
2298	uint32_t idxSched = pStreamShared->State.idxSchedule;
2299	AssertStmt(idxSched < RT_ELEMENTS(pStreamShared->State.aSchedule), idxSched = 0);
2300	uint32_t idxLoop = pStreamShared->State.idxScheduleLoop + 1;
2301	if (idxLoop >= pStreamShared->State.aSchedule[idxSched].cLoops)
2302	{
2303	idxSched += 1;
2304	if ( idxSched >= pStreamShared->State.cSchedule
2305	\|\| idxSched >= RT_ELEMENTS(pStreamShared->State.aSchedule) /paranoia^2/)
2306	{
2307	idxSched = pStreamShared->State.cSchedulePrologue;
2308	AssertStmt(idxSched < RT_ELEMENTS(pStreamShared->State.aSchedule), idxSched = 0);
2309	}
2310	pStreamShared->State.idxSchedule = idxSched;
2311	idxLoop = 0;
2312	}
2313	pStreamShared->State.idxScheduleLoop = (uint16_t)idxLoop;
2314
2315	/* Do the actual timer re-arming. */
2316	uint64_t const tsNow = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer); /* (For virtual sync this remains the same for the whole callout IIRC) */
2317	uint64_t const tsTransferNext = tsNow + pStreamShared->State.aSchedule[idxSched].cPeriodTicks;
2318	Log3Func(("[SD%RU8] fSinkActive=true, tsTransferNext=%RU64 (in %RU64)\n",
2319	pStreamShared->u8SD, tsTransferNext, tsTransferNext - tsNow));
2320	int rc = PDMDevHlpTimerSet(pDevIns, pStreamShared->hTimer, tsTransferNext);
2321	AssertRC(rc);
2322
2323	/* Some legacy stuff: */
2324	pStreamShared->State.tsTransferNext = tsTransferNext;
2325	pStreamShared->State.cbCurDmaPeriod = pStreamShared->State.aSchedule[idxSched].cbPeriod;
2326
2327	return tsNow;
2328	}
2329
2330	Log3Func(("[SD%RU8] fSinkActive=false\n", pStreamShared->u8SD));
2331	return 0;
2332	}
2333
2334
2335	/**
2336	* Updates a HDA stream by doing DMA transfers.
2337	*
2338	* Will do mixer transfers too to try fix an overrun/underrun situation.
2339	*
2340	* The host sink(s) set the overall pace (bird: no it doesn't, the DMA timer
2341	* does - we just hope like heck it matches the speed at which the backend
2342	* host audio driver processes samples).
2343	*
2344	* @param pDevIns The device instance.
2345	* @param pThis The shared HDA device state.
2346	* @param pThisCC The ring-3 HDA device state.
2347	* @param pStreamShared HDA stream to update (shared bits).
2348	* @param pStreamR3 HDA stream to update (ring-3 bits).
2349	*/
2350	static void hdaR3StreamUpdateDma(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
2351	PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
2352	{
2353	RT_NOREF(pThisCC);
2354	int rc2;
2355
2356	/*
2357	* Make sure we're running and got an active mixer sink.
2358	*/
2359	if (RT_LIKELY(pStreamShared->State.fRunning))
2360	{ /* likely */ }
2361	else
2362	return;
2363
2364	PAUDMIXSINK pSink = NULL;
2365	if (pStreamR3->pMixSink)
2366	pSink = pStreamR3->pMixSink->pMixSink;
2367	if (RT_LIKELY(AudioMixerSinkIsActive(pSink)))
2368	{ /* likely */ }
2369	else
2370	return;
2371
2372	/*
2373	* Get scheduling info common to both input and output streams.
2374	*/
2375	const uint64_t tsNowNs = RTTimeNanoTS();
2376	uint32_t idxSched = pStreamShared->State.idxSchedule;
2377	AssertStmt(idxSched < RT_MIN(RT_ELEMENTS(pStreamShared->State.aSchedule), pStreamShared->State.cSchedule), idxSched = 0);
2378	uint32_t cbPeriod = pStreamShared->State.aSchedule[idxSched].cbPeriod;
2379
2380	/*
2381	* Output streams (SDO).
2382	*/
2383	if (hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_OUT)
2384	{
2385	# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
2386	/* Subtract already transferred bytes and flush the DMA bounce buffer. */
2387	uint32_t cbDmaTotal = pStreamShared->State.cbDmaTotal;
2388	if (cbDmaTotal > 0)
2389	{
2390	AssertStmt(cbDmaTotal < cbPeriod, cbDmaTotal = cbPeriod);
2391	cbPeriod -= cbDmaTotal;
2392	pStreamShared->State.cbDmaTotal = 0;
2393	hdaR3StreamFlushDmaBounceBufferOutput(pStreamShared, pStreamR3);
2394	}
2395	else
2396	Assert(pStreamShared->State.cbDma == 0);
2397	# endif
2398
2399	/*
2400	* Check how much room we have in our DMA buffer. There should be at
2401	* least one period worth of space there or we're in an overflow situation.
2402	*/
2403	uint32_t cbStreamFree = hdaR3StreamGetFree(pStreamR3);
2404	if (cbStreamFree >= cbPeriod)
2405	{ /* likely */ }
2406	else
2407	cbStreamFree = hdaR3StreamHandleDmaBufferOverrun(pStreamShared, pStreamR3, pSink, cbPeriod, tsNowNs,
2408	"hdaR3StreamUpdateDma", cbStreamFree);
2409
2410	/*
2411	* Do the DMA transfer.
2412	*/
2413	uint64_t const offWriteBefore = pStreamShared->State.offWrite;
2414	hdaR3StreamDoDmaOutput(pDevIns, pThis, pStreamShared, pStreamR3, RT_MIN(cbStreamFree, cbPeriod), tsNowNs);
2415
2416	/*
2417	* Should we push data to down thru the mixer to and to the host drivers?
2418	*
2419	* We initially delay this by pThis->msInitialDelay, but after than we'll
2420	* kick the AIO thread every time we've put more data in the buffer (which is
2421	* every time) as the host audio device needs to get data in a timely manner.
2422	*
2423	* (We used to try only wake up the AIO thread according to pThis->uIoTimer
2424	* and host wall clock, but that meant we would miss a wakup after the DMA
2425	* timer was called a little late or if TM entered into catch-up mode.)
2426	*/
2427	bool fKickAioThread;
2428	if (!pStreamShared->State.tsAioDelayEnd)
2429	fKickAioThread = pStreamShared->State.offWrite > offWriteBefore
2430	\|\| hdaR3StreamGetFree(pStreamR3) < pStreamShared->State.cbAvgTransfer * 2;
2431	else if (PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer) >= pStreamShared->State.tsAioDelayEnd)
2432	{
2433	Log3Func(("Initial delay done: Passed tsAioDelayEnd.\n"));
2434	pStreamShared->State.tsAioDelayEnd = 0;
2435	fKickAioThread = true;
2436	}
2437	else if (hdaR3StreamGetFree(pStreamR3) < pStreamShared->State.cbAvgTransfer * 2)
2438	{
2439	Log3Func(("Initial delay done: Passed running short on buffer.\n"));
2440	pStreamShared->State.tsAioDelayEnd = 0;
2441	fKickAioThread = true;
2442	}
2443	else
2444	{
2445	Log3Func(("Initial delay pending...\n"));
2446	fKickAioThread = false;
2447	}
2448
2449	Log3Func(("msDelta=%RU64 (vs %u) cbStreamFree=%#x (vs %#x) => fKickAioThread=%RTbool\n",
2450	(tsNowNs - pStreamShared->State.tsLastReadNs) / RT_NS_1MS,
2451	pStreamShared->State.Cfg.Device.cMsSchedulingHint, cbStreamFree,
2452	pStreamShared->State.cbAvgTransfer * 2, fKickAioThread));
2453
2454	if (fKickAioThread)
2455	{
2456	/* Notify the async I/O worker thread that there's work to do. */
2457	Log5Func(("Notifying AIO thread\n"));
2458	rc2 = AudioMixerSinkSignalUpdateJob(pSink);
2459	AssertRC(rc2);
2460	/* Update last read timestamp for logging/debugging. */
2461	pStreamShared->State.tsLastReadNs = tsNowNs;
2462	}
2463	}
2464	/*
2465	* Input stream (SDI).
2466	*/
2467	else
2468	{
2469	Assert(hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_IN);
2470
2471	/*
2472	* See how much data we've got buffered...
2473	*/
2474	bool fWriteSilence = false;
2475	uint32_t cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2476	if (pStreamShared->State.fInputPreBuffered && cbStreamUsed >= cbPeriod)
2477	{ /likely/ }
2478	/*
2479	* Because it may take a while for the input stream to get going (at
2480	* least with pulseaudio), we feed the guest silence till we've
2481	* pre-buffer a reasonable amount of audio.
2482	*/
2483	else if (!pStreamShared->State.fInputPreBuffered)
2484	{
2485	if (cbStreamUsed < pStreamShared->State.cbInputPreBuffer)
2486	{
2487	Log3(("hdaR3StreamUpdateDma: Pre-buffering (got %#x out of %#x bytes)...\n",
2488	cbStreamUsed, pStreamShared->State.cbInputPreBuffer));
2489	fWriteSilence = true;
2490	}
2491	else
2492	{
2493	Log3(("hdaR3StreamUpdateDma: Completed pre-buffering (got %#x, needed %#x bytes).\n",
2494	cbStreamUsed, pStreamShared->State.cbInputPreBuffer));
2495	pStreamShared->State.fInputPreBuffered = true;
2496	fWriteSilence = true; /* For now, just do the most conservative thing. */
2497	}
2498	cbStreamUsed = cbPeriod;
2499	}
2500	/*
2501	* When we're low on data, we must really try fetch some ourselves
2502	* as buffer underruns must not happen.
2503	*/
2504	else
2505	{
2506	/** @todo We're ending up here to frequently with pulse audio at least (just
2507	* watch the stream stats in the statistcs viewer, and way to often we
2508	* have to inject silence bytes. I suspect part of the problem is
2509	* that the HDA device require a much better latency than what the
2510	* pulse audio is configured for by default (10 ms vs 150ms). */
2511	STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowProblems);
2512	Log(("hdaR3StreamUpdateDma: Warning! Stream #%u has insufficient data available: %u bytes, need %u. Will try move pull more data into the buffer...\n",
2513	pStreamShared->u8SD, cbStreamUsed, cbPeriod));
2514	int rc = AudioMixerSinkTryLock(pSink);
2515	if (RT_SUCCESS(rc))
2516	{
2517	AudioMixerSinkUpdate(pSink, cbStreamUsed, cbPeriod);
2518	hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2519	AudioMixerSinkUnlock(pSink);
2520	}
2521	else
2522	RTThreadYield();
2523	Log(("hdaR3StreamUpdateDma: Gained %u bytes.\n", hdaR3StreamGetUsed(pStreamR3) - cbStreamUsed));
2524	cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2525	if (cbStreamUsed < cbPeriod)
2526	{
2527	/* Unable to find sufficient input data by simple prodding.
2528	In order to keep a constant byte stream following thru the DMA
2529	engine into the guest, we will try again and then fall back on
2530	filling the gap with silence. */
2531	uint32_t cbSilence = 0;
2532	do
2533	{
2534	AudioMixerSinkLock(pSink);
2535
2536	cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2537	if (cbStreamUsed < cbPeriod)
2538	{
2539	hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2540	cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2541	while (cbStreamUsed < cbPeriod)
2542	{
2543	void *pvDstBuf;
2544	size_t cbDstBuf;
2545	RTCircBufAcquireWriteBlock(pStreamR3->State.pCircBuf, cbPeriod - cbStreamUsed,
2546	&pvDstBuf, &cbDstBuf);
2547	RT_BZERO(pvDstBuf, cbDstBuf);
2548	RTCircBufReleaseWriteBlock(pStreamR3->State.pCircBuf, cbDstBuf);
2549	cbSilence += (uint32_t)cbDstBuf;
2550	cbStreamUsed += (uint32_t)cbDstBuf;
2551	}
2552	}
2553
2554	AudioMixerSinkUnlock(pSink);
2555	} while (cbStreamUsed < cbPeriod);
2556	if (cbSilence > 0)
2557	{
2558	STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowErrors);
2559	STAM_REL_COUNTER_ADD(&pStreamR3->State.StatDmaFlowErrorBytes, cbSilence);
2560	LogRel2(("HDA: Warning: Stream #%RU8 underrun, added %u bytes of silence (%u us)\n", pStreamShared->u8SD,
2561	cbSilence, PDMAudioPropsBytesToMicro(&pStreamShared->State.Cfg.Props, cbSilence)));
2562	}
2563	}
2564	}
2565
2566	/*
2567	* Do the DMA'ing.
2568	*/
2569	if (cbStreamUsed)
2570	hdaR3StreamDoDmaInput(pDevIns, pThis, pStreamShared, pStreamR3,
2571	RT_MIN(cbStreamUsed, cbPeriod), fWriteSilence, tsNowNs);
2572
2573	/*
2574	* We should always kick the AIO thread.
2575	*/
2576	/** @todo This isn't entirely ideal. If we get into an underrun situation,
2577	* we ideally want the AIO thread to run right before the DMA timer
2578	* rather than right after it ran. */
2579	Log5Func(("Notifying AIO thread\n"));
2580	rc2 = AudioMixerSinkSignalUpdateJob(pSink);
2581	AssertRC(rc2);
2582	pStreamShared->State.tsLastReadNs = tsNowNs;
2583	}
2584	}
2585
2586
2587	/**
2588	* @callback_method_impl{FNAUDMIXSINKUPDATE}
2589	*
2590	* For output streams this moves data from the internal DMA buffer (in which
2591	* hdaR3StreamUpdateDma put it), thru the mixer and to the various backend audio
2592	* devices.
2593	*
2594	* For input streams this pulls data from the backend audio device(s), thru the
2595	* mixer and puts it in the internal DMA buffer ready for hdaR3StreamUpdateDma
2596	* to pump into guest memory.
2597	*/
2598	DECLCALLBACK(void) hdaR3StreamUpdateAsyncIoJob(PPDMDEVINS pDevIns, PAUDMIXSINK pSink, void *pvUser)
2599	{
2600	PHDASTATE const pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
2601	PHDASTATER3 const pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
2602	PHDASTREAMR3 const pStreamR3 = (PHDASTREAMR3)pvUser;
2603	PHDASTREAM const pStreamShared = &pThis->aStreams[pStreamR3 - &pThisCC->aStreams[0]];
2604	Assert(pStreamR3 - &pThisCC->aStreams[0] == pStreamR3->u8SD);
2605	Assert(pStreamShared->u8SD == pStreamR3->u8SD);
2606	RT_NOREF(pSink);
2607
2608	/*
2609	* Make sure we haven't change sink and that it's still active (it
2610	* should be or we wouldn't have been called).
2611	*/
2612	AssertReturnVoid(pStreamR3->pMixSink && pSink == pStreamR3->pMixSink->pMixSink);
2613	AssertReturnVoid(AudioMixerSinkIsActive(pSink));
2614
2615	/*
2616	* Output streams (SDO).
2617	*/
2618	if (hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_OUT)
2619	hdaR3StreamPushToMixer(pStreamShared, pStreamR3, pSink, RTTimeNanoTS());
2620	/*
2621	* Input stream (SDI).
2622	*/
2623	else
2624	{
2625	Assert(hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_IN);
2626	hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2627	}
2628	}
2629
2630
2631	# if 0 /* unused - no prototype even */
2632	/**
2633	* Updates an HDA stream's current read or write buffer position (depending on the stream type) by
2634	* updating its associated LPIB register and DMA position buffer (if enabled).
2635	*
2636	* @returns Set LPIB value.
2637	* @param pDevIns The device instance.
2638	* @param pStream HDA stream to update read / write position for.
2639	* @param u32LPIB New LPIB (position) value to set.
2640	*/
2641	uint32_t hdaR3StreamUpdateLPIB(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint32_t u32LPIB)
2642	{
2643	AssertMsg(u32LPIB <= pStreamShared->u32CBL,
2644	("[SD%RU8] New LPIB (%RU32) exceeds CBL (%RU32)\n", pStreamShared->u8SD, u32LPIB, pStreamShared->u32CBL));
2645
2646	u32LPIB = RT_MIN(u32LPIB, pStreamShared->u32CBL);
2647
2648	LogFlowFunc(("[SD%RU8] LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n",
2649	pStreamShared->u8SD, u32LPIB, pThis->fDMAPosition));
2650
2651	/* Update LPIB in any case. */
2652	HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) = u32LPIB;
2653
2654	/* Do we need to tell the current DMA position? */
2655	if (pThis->fDMAPosition)
2656	{
2657	int rc2 = PDMDevHlpPCIPhysWrite(pDevIns,
2658	pThis->u64DPBase + (pStreamShared->u8SD * 2 * sizeof(uint32_t)),
2659	(void *)&u32LPIB, sizeof(uint32_t));
2660	AssertRC(rc2);
2661	}
2662
2663	return u32LPIB;
2664	}
2665	# endif
2666
2667	# ifdef HDA_USE_DMA_ACCESS_HANDLER
2668	/**
2669	* Registers access handlers for a stream's BDLE DMA accesses.
2670	*
2671	* @returns true if registration was successful, false if not.
2672	* @param pStream HDA stream to register BDLE access handlers for.
2673	*/
2674	bool hdaR3StreamRegisterDMAHandlers(PHDASTREAM pStream)
2675	{
2676	/* At least LVI and the BDL base must be set. */
2677	if ( !pStreamShared->u16LVI
2678	\|\| !pStreamShared->u64BDLBase)
2679	{
2680	return false;
2681	}
2682
2683	hdaR3StreamUnregisterDMAHandlers(pStream);
2684
2685	LogFunc(("Registering ...\n"));
2686
2687	int rc = VINF_SUCCESS;
2688
2689	/*
2690	* Create BDLE ranges.
2691	*/
2692
2693	struct BDLERANGE
2694	{
2695	RTGCPHYS uAddr;
2696	uint32_t uSize;
2697	} arrRanges[16]; /** @todo Use a define. */
2698
2699	size_t cRanges = 0;
2700
2701	for (uint16_t i = 0; i < pStreamShared->u16LVI + 1; i++)
2702	{
2703	HDABDLE BDLE;
2704	rc = hdaR3BDLEFetch(pDevIns, &BDLE, pStreamShared->u64BDLBase, i /* Index */);
2705	if (RT_FAILURE(rc))
2706	break;
2707
2708	bool fAddRange = true;
2709	BDLERANGE *pRange;
2710
2711	if (cRanges)
2712	{
2713	pRange = &arrRanges[cRanges - 1];
2714
2715	/* Is the current range a direct neighbor of the current BLDE? */
2716	if ((pRange->uAddr + pRange->uSize) == BDLE.Desc.u64BufAddr)
2717	{
2718	/* Expand the current range by the current BDLE's size. */
2719	pRange->uSize += BDLE.Desc.u32BufSize;
2720
2721	/* Adding a new range in this case is not needed anymore. */
2722	fAddRange = false;
2723
2724	LogFunc(("Expanding range %zu by %RU32 (%RU32 total now)\n", cRanges - 1, BDLE.Desc.u32BufSize, pRange->uSize));
2725	}
2726	}
2727
2728	/* Do we need to add a new range? */
2729	if ( fAddRange
2730	&& cRanges < RT_ELEMENTS(arrRanges))
2731	{
2732	pRange = &arrRanges[cRanges];
2733
2734	pRange->uAddr = BDLE.Desc.u64BufAddr;
2735	pRange->uSize = BDLE.Desc.u32BufSize;
2736
2737	LogFunc(("Adding range %zu - 0x%x (%RU32)\n", cRanges, pRange->uAddr, pRange->uSize));
2738
2739	cRanges++;
2740	}
2741	}
2742
2743	LogFunc(("%zu ranges total\n", cRanges));
2744
2745	/*
2746	* Register all ranges as DMA access handlers.
2747	*/
2748
2749	for (size_t i = 0; i < cRanges; i++)
2750	{
2751	BDLERANGE *pRange = &arrRanges[i];
2752
2753	PHDADMAACCESSHANDLER pHandler = (PHDADMAACCESSHANDLER)RTMemAllocZ(sizeof(HDADMAACCESSHANDLER));
2754	if (!pHandler)
2755	{
2756	rc = VERR_NO_MEMORY;
2757	break;
2758	}
2759
2760	RTListAppend(&pStream->State.lstDMAHandlers, &pHandler->Node);
2761
2762	pHandler->pStream = pStream; /* Save a back reference to the owner. */
2763
2764	char szDesc[32];
2765	RTStrPrintf(szDesc, sizeof(szDesc), "HDA[SD%RU8 - RANGE%02zu]", pStream->u8SD, i);
2766
2767	int rc2 = PGMR3HandlerPhysicalTypeRegister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3), PGMPHYSHANDLERKIND_WRITE,
2768	hdaDMAAccessHandler,
2769	NULL, NULL, NULL,
2770	NULL, NULL, NULL,
2771	szDesc, &pHandler->hAccessHandlerType);
2772	AssertRCBreak(rc2);
2773
2774	pHandler->BDLEAddr = pRange->uAddr;
2775	pHandler->BDLESize = pRange->uSize;
2776
2777	/* Get first and last pages of the BDLE range. */
2778	RTGCPHYS pgFirst = pRange->uAddr & ~PAGE_OFFSET_MASK;
2779	RTGCPHYS pgLast = RT_ALIGN(pgFirst + pRange->uSize, PAGE_SIZE);
2780
2781	/* Calculate the region size (in pages). */
2782	RTGCPHYS regionSize = RT_ALIGN(pgLast - pgFirst, PAGE_SIZE);
2783
2784	pHandler->GCPhysFirst = pgFirst;
2785	pHandler->GCPhysLast = pHandler->GCPhysFirst + (regionSize - 1);
2786
2787	LogFunc((" Registering region '%s': %#RGp - %#RGp (region size: %#zx)\n",
2788	szDesc, pHandler->GCPhysFirst, pHandler->GCPhysLast, regionSize));
2789	LogFunc((" BDLE @ %#RGp - %#RGp (%#RX32)\n",
2790	pHandler->BDLEAddr, pHandler->BDLEAddr + pHandler->BDLESize, pHandler->BDLESize));
2791
2792	rc2 = PGMHandlerPhysicalRegister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3),
2793	pHandler->GCPhysFirst, pHandler->GCPhysLast,
2794	pHandler->hAccessHandlerType, pHandler, NIL_RTR0PTR, NIL_RTRCPTR,
2795	szDesc);
2796	AssertRCBreak(rc2);
2797
2798	pHandler->fRegistered = true;
2799	}
2800
2801	LogFunc(("Registration ended with rc=%Rrc\n", rc));
2802
2803	return RT_SUCCESS(rc);
2804	}
2805
2806	/**
2807	* Unregisters access handlers of a stream's BDLEs.
2808	*
2809	* @param pStream HDA stream to unregister BDLE access handlers for.
2810	*/
2811	void hdaR3StreamUnregisterDMAHandlers(PHDASTREAM pStream)
2812	{
2813	LogFunc(("\n"));
2814
2815	PHDADMAACCESSHANDLER pHandler, pHandlerNext;
2816	RTListForEachSafe(&pStream->State.lstDMAHandlers, pHandler, pHandlerNext, HDADMAACCESSHANDLER, Node)
2817	{
2818	if (!pHandler->fRegistered) /* Handler not registered? Skip. */
2819	continue;
2820
2821	LogFunc(("Unregistering 0x%x - 0x%x (%zu)\n",
2822	pHandler->GCPhysFirst, pHandler->GCPhysLast, pHandler->GCPhysLast - pHandler->GCPhysFirst));
2823
2824	int rc2 = PGMHandlerPhysicalDeregister(PDMDevHlpGetVM(pStream->pHDAState->pDevInsR3),
2825	pHandler->GCPhysFirst);
2826	AssertRC(rc2);
2827
2828	RTListNodeRemove(&pHandler->Node);
2829
2830	RTMemFree(pHandler);
2831	pHandler = NULL;
2832	}
2833
2834	Assert(RTListIsEmpty(&pStream->State.lstDMAHandlers));
2835	}
2836
2837	# endif /* HDA_USE_DMA_ACCESS_HANDLER */
2838
2839	#endif /* IN_RING3 */

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source: vbox/trunk/src/VBox/Devices/Audio/DevHdaStream.cpp@ 89874

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