VirtualBox

source: vbox/trunk/src/VBox/Devices/Audio/DevHdaStream.cpp@ 89884

Last change on this file since 89884 was 89884, checked in by vboxsync, 4 years ago

DevHda: Cleaned up the write-silence bits of hdaR3StreamDoDmaInput. bugref:9890
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File size: 101.6 KB
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1/* $Id: DevHdaStream.cpp 89884 2021-06-24 11:14:59Z vboxsync $ */
2/** @file
3 * Intel HD Audio Controller Emulation - Streams.
4 */
5
6/*
7 * Copyright (C) 2017-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DEV_HDA
23#include <VBox/log.h>
24
25#include <iprt/mem.h>
26#include <iprt/semaphore.h>
27#include <iprt/zero.h>
28
29#include <VBox/AssertGuest.h>
30#include <VBox/vmm/pdmdev.h>
31#include <VBox/vmm/pdmaudioifs.h>
32#include <VBox/vmm/pdmaudioinline.h>
33
34#include "AudioHlp.h"
35
36#include "DevHda.h"
37
38#ifdef VBOX_WITH_DTRACE
39# include "dtrace/VBoxDD.h"
40#endif
41
42
43/*********************************************************************************************************************************
44* Internal Functions *
45*********************************************************************************************************************************/
46#if defined(IN_RING3) || defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA)
47static void hdaStreamSetPositionAbs(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uLPIB);
48#endif
49#ifdef IN_RING3
50# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
51static void hdaR3StreamFlushDmaBounceBufferOutput(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
52# endif
53static uint32_t hdaR3StreamHandleDmaBufferOverrun(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink,
54 uint32_t cbNeeded, uint64_t nsNow,
55 const char *pszCaller, uint32_t const cbStreamFree);
56static void hdaR3StreamUpdateDma(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
57 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
58#endif
59
60
61#ifdef IN_RING3
62
63/**
64 * Creates an HDA stream.
65 *
66 * @returns VBox status code.
67 * @param pStreamShared The HDA stream to construct - shared bits.
68 * @param pStreamR3 The HDA stream to construct - ring-3 bits.
69 * @param pThis The shared HDA device instance.
70 * @param pThisCC The ring-3 HDA device instance.
71 * @param uSD Stream descriptor number to assign.
72 */
73int hdaR3StreamConstruct(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PHDASTATE pThis, PHDASTATER3 pThisCC, uint8_t uSD)
74{
75 pStreamR3->u8SD = uSD;
76 pStreamShared->u8SD = uSD;
77 pStreamR3->pMixSink = NULL;
78 pStreamR3->pHDAStateShared = pThis;
79 pStreamR3->pHDAStateR3 = pThisCC;
80 Assert(pStreamShared->hTimer != NIL_TMTIMERHANDLE); /* hdaR3Construct initalized this one already. */
81
82 pStreamShared->State.fInReset = false;
83 pStreamShared->State.fRunning = false;
84
85 AssertPtr(pStreamR3->pHDAStateR3);
86 AssertPtr(pStreamR3->pHDAStateR3->pDevIns);
87
88# ifdef DEBUG
89 int rc = RTCritSectInit(&pStreamR3->Dbg.CritSect);
90 AssertRCReturn(rc, rc);
91# endif
92
93 const bool fIsInput = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN;
94
95 if (fIsInput)
96 {
97 pStreamShared->State.Cfg.enmPath = PDMAUDIOPATH_UNKNOWN;
98 pStreamShared->State.Cfg.enmDir = PDMAUDIODIR_IN;
99 }
100 else
101 {
102 pStreamShared->State.Cfg.enmPath = PDMAUDIOPATH_UNKNOWN;
103 pStreamShared->State.Cfg.enmDir = PDMAUDIODIR_OUT;
104 }
105
106 pStreamR3->Dbg.Runtime.fEnabled = pThisCC->Dbg.fEnabled;
107
108 if (pStreamR3->Dbg.Runtime.fEnabled)
109 {
110 char szFile[64];
111 char szPath[RTPATH_MAX];
112
113 /* pFileStream */
114 if (fIsInput)
115 RTStrPrintf(szFile, sizeof(szFile), "hdaStreamWriteSD%RU8", uSD);
116 else
117 RTStrPrintf(szFile, sizeof(szFile), "hdaStreamReadSD%RU8", uSD);
118
119 int rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
120 0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
121 AssertRC(rc2);
122
123 rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileStream);
124 AssertRC(rc2);
125
126 /* pFileDMARaw */
127 if (fIsInput)
128 RTStrPrintf(szFile, sizeof(szFile), "hdaDMARawWriteSD%RU8", uSD);
129 else
130 RTStrPrintf(szFile, sizeof(szFile), "hdaDMARawReadSD%RU8", uSD);
131
132 rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
133 0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
134 AssertRC(rc2);
135
136 rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileDMARaw);
137 AssertRC(rc2);
138
139 /* pFileDMAMapped */
140 if (fIsInput)
141 RTStrPrintf(szFile, sizeof(szFile), "hdaDMAWriteMappedSD%RU8", uSD);
142 else
143 RTStrPrintf(szFile, sizeof(szFile), "hdaDMAReadMappedSD%RU8", uSD);
144
145 rc2 = AudioHlpFileNameGet(szPath, sizeof(szPath), pThisCC->Dbg.pszOutPath, szFile,
146 0 /* uInst */, AUDIOHLPFILETYPE_WAV, AUDIOHLPFILENAME_FLAGS_NONE);
147 AssertRC(rc2);
148
149 rc2 = AudioHlpFileCreate(AUDIOHLPFILETYPE_WAV, szPath, AUDIOHLPFILE_FLAGS_NONE, &pStreamR3->Dbg.Runtime.pFileDMAMapped);
150 AssertRC(rc2);
151
152 /* Delete stale debugging files from a former run. */
153 AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileStream);
154 AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileDMARaw);
155 AudioHlpFileDelete(pStreamR3->Dbg.Runtime.pFileDMAMapped);
156 }
157
158 return VINF_SUCCESS;
159}
160
161/**
162 * Destroys an HDA stream.
163 *
164 * @param pStreamR3 The HDA stream to destroy - ring-3 bits.
165 */
166void hdaR3StreamDestroy(PHDASTREAMR3 pStreamR3)
167{
168 LogFlowFunc(("[SD%RU8] Destroying ...\n", pStreamR3->u8SD));
169 int rc2;
170
171 if (pStreamR3->State.pAioRegSink)
172 {
173 rc2 = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
174 AssertRC(rc2);
175 pStreamR3->State.pAioRegSink = NULL;
176 }
177
178 if (pStreamR3->State.pCircBuf)
179 {
180 RTCircBufDestroy(pStreamR3->State.pCircBuf);
181 pStreamR3->State.pCircBuf = NULL;
182 pStreamR3->State.StatDmaBufSize = 0;
183 pStreamR3->State.StatDmaBufUsed = 0;
184 }
185
186# ifdef DEBUG
187 if (RTCritSectIsInitialized(&pStreamR3->Dbg.CritSect))
188 {
189 rc2 = RTCritSectDelete(&pStreamR3->Dbg.CritSect);
190 AssertRC(rc2);
191 }
192# endif
193
194 if (pStreamR3->Dbg.Runtime.fEnabled)
195 {
196 AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileStream);
197 pStreamR3->Dbg.Runtime.pFileStream = NULL;
198
199 AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileDMARaw);
200 pStreamR3->Dbg.Runtime.pFileDMARaw = NULL;
201
202 AudioHlpFileDestroy(pStreamR3->Dbg.Runtime.pFileDMAMapped);
203 pStreamR3->Dbg.Runtime.pFileDMAMapped = NULL;
204 }
205
206 LogFlowFuncLeave();
207}
208
209
210/**
211 * Appends a item to the scheduler.
212 *
213 * @returns VBox status code.
214 * @param pStreamShared The stream which scheduler should be modified.
215 * @param cbCur The period length in guest bytes.
216 * @param cbMaxPeriod The max period in guest bytes.
217 * @param idxLastBdle The last BDLE in the period.
218 * @param pProps The PCM properties.
219 * @param pcbBorrow Where to account for bytes borrowed across buffers
220 * to align scheduling items on frame boundraries.
221 */
222static int hdaR3StreamAddScheduleItem(PHDASTREAM pStreamShared, uint32_t cbCur, uint32_t cbMaxPeriod,
223 uint32_t idxLastBdle, PCPDMAUDIOPCMPROPS pProps, uint32_t *pcbBorrow)
224{
225 /* Check that we've got room (shouldn't ever be a problem). */
226 size_t idx = pStreamShared->State.cSchedule;
227 AssertLogRelReturn(idx + 1 < RT_ELEMENTS(pStreamShared->State.aSchedule), VERR_INTERNAL_ERROR_5);
228
229 /* Figure out the BDLE range for this period. */
230 uint32_t const idxFirstBdle = idx == 0 ? 0
231 : RT_MIN((uint32_t)( pStreamShared->State.aSchedule[idx - 1].idxFirst
232 + pStreamShared->State.aSchedule[idx - 1].cEntries),
233 idxLastBdle);
234
235 pStreamShared->State.aSchedule[idx].idxFirst = (uint8_t)idxFirstBdle;
236 pStreamShared->State.aSchedule[idx].cEntries = idxLastBdle >= idxFirstBdle
237 ? idxLastBdle - idxFirstBdle + 1
238 : pStreamShared->State.cBdles - idxFirstBdle + idxLastBdle + 1;
239
240 /* Deal with borrowing due to unaligned IOC buffers. */
241 uint32_t const cbBorrowed = *pcbBorrow;
242 if (cbBorrowed < cbCur)
243 cbCur -= cbBorrowed;
244 else
245 {
246 /* Note. We can probably gloss over this, but it's not a situation a sane guest would put us, so don't bother for now. */
247 ASSERT_GUEST_MSG_FAILED(("#%u: cbBorrow=%#x cbCur=%#x BDLE[%u..%u]\n",
248 pStreamShared->u8SD, cbBorrowed, cbCur, idxFirstBdle, idxLastBdle));
249 LogRelMax(32, ("HDA: Stream #%u has a scheduling error: cbBorrow=%#x cbCur=%#x BDLE[%u..%u]\n",
250 pStreamShared->u8SD, cbBorrowed, cbCur, idxFirstBdle, idxLastBdle));
251 return VERR_OUT_OF_RANGE;
252 }
253
254 uint32_t cbCurAligned = PDMAudioPropsRoundUpBytesToFrame(pProps, cbCur);
255 *pcbBorrow = cbCurAligned - cbCur;
256
257 /* Do we need to split up the period? */
258 if (cbCurAligned <= cbMaxPeriod)
259 {
260 pStreamShared->State.aSchedule[idx].cbPeriod = cbCurAligned;
261 pStreamShared->State.aSchedule[idx].cLoops = 1;
262 }
263 else
264 {
265 /* Reduce till we've below the threshold. */
266 uint32_t cbLoop = cbCurAligned;
267 do
268 cbLoop = cbCurAligned / 2;
269 while (cbLoop > cbMaxPeriod);
270 cbLoop = PDMAudioPropsRoundUpBytesToFrame(pProps, cbLoop);
271
272 /* Complete the scheduling item. */
273 pStreamShared->State.aSchedule[idx].cbPeriod = cbLoop;
274 pStreamShared->State.aSchedule[idx].cLoops = cbCurAligned / cbLoop;
275
276 /* If there is a remainder, add it as a separate entry (this is
277 why the schedule must be more than twice the size of the BDL).*/
278 cbCurAligned %= cbLoop;
279 if (cbCurAligned)
280 {
281 pStreamShared->State.aSchedule[idx + 1] = pStreamShared->State.aSchedule[idx];
282 idx++;
283 pStreamShared->State.aSchedule[idx].cbPeriod = cbCurAligned;
284 pStreamShared->State.aSchedule[idx].cLoops = 1;
285 }
286 }
287
288 /* Done. */
289 pStreamShared->State.cSchedule = (uint16_t)(idx + 1);
290
291 return VINF_SUCCESS;
292}
293
294/**
295 * Creates the DMA timer schedule for the stream
296 *
297 * This is called from the stream setup code.
298 *
299 * @returns VBox status code.
300 * @param pStreamShared The stream to create a schedule for. The BDL
301 * must be loaded.
302 * @param cSegments Number of BDL segments.
303 * @param cBufferIrqs Number of the BDLEs with IOC=1.
304 * @param cbTotal The total BDL length in guest bytes.
305 * @param cbMaxPeriod Max period in guest bytes. This is in case the
306 * guest want to play the whole "Der Ring des
307 * Nibelungen" cycle in one go.
308 * @param cTimerTicksPerSec The DMA timer frequency.
309 * @param pProps The PCM properties.
310 */
311static int hdaR3StreamCreateSchedule(PHDASTREAM pStreamShared, uint32_t cSegments, uint32_t cBufferIrqs, uint32_t cbTotal,
312 uint32_t cbMaxPeriod, uint64_t cTimerTicksPerSec, PCPDMAUDIOPCMPROPS pProps)
313{
314 int rc;
315
316 /*
317 * Reset scheduling state.
318 */
319 RT_ZERO(pStreamShared->State.aSchedule);
320 pStreamShared->State.cSchedule = 0;
321 pStreamShared->State.cSchedulePrologue = 0;
322 pStreamShared->State.idxSchedule = 0;
323 pStreamShared->State.idxScheduleLoop = 0;
324
325 /*
326 * Do the basic schedule compilation.
327 */
328 uint32_t cPotentialPrologue = 0;
329 uint32_t cbBorrow = 0;
330 uint32_t cbCur = 0;
331 uint32_t cbMin = UINT32_MAX;
332 pStreamShared->State.aSchedule[0].idxFirst = 0;
333 for (uint32_t i = 0; i < cSegments; i++)
334 {
335 cbCur += pStreamShared->State.aBdl[i].cb;
336 if (pStreamShared->State.aBdl[i].cb < cbMin)
337 cbMin = pStreamShared->State.aBdl[i].cb;
338 if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
339 {
340 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur, cbMaxPeriod, i, pProps, &cbBorrow);
341 ASSERT_GUEST_RC_RETURN(rc, rc);
342
343 if (cPotentialPrologue == 0)
344 cPotentialPrologue = pStreamShared->State.cSchedule;
345 cbCur = 0;
346 }
347 }
348
349 /*
350 * Deal with any loose ends.
351 */
352 if (cbCur && cBufferIrqs == 0)
353 {
354 /*
355 * No IOC. Vista ends up here, typically with three buffers configured.
356 *
357 * The perferred option here is to aim at processing one average BDLE with
358 * each DMA timer period, since that best matches how we update LPIB at
359 * present.
360 *
361 * The second alternative is to divide the whole span up into 3-4 periods
362 * to try increase our chances of keeping ahead of the guest. We may need
363 * to pick this if there are too few buffer descriptor or they are too small.
364 *
365 * However, what we probably should be doing is to do real DMA work whenever
366 * the guest reads a DMA related register (like LPIB) and just do 3-4 DMA
367 * timer periods, however we'll be postponing the DMA timer every time we
368 * return to ring-3 and signal the AIO, so in the end we'd probably not use
369 * the timer callback at all. (This is assuming a small shared per-stream
370 * buffer for keeping the DMA data in and that it's size will force a return
371 * to ring-3 often enough to keep the AIO thread going at a reasonable rate.)
372 */
373 Assert(cbCur == cbTotal);
374
375 /* Match the BDLEs 1:1 if there are 3 or more and that the smallest one
376 is at least 5ms big. */
377 if (cSegments >= 3 && PDMAudioPropsBytesToMilli(pProps, cbMin) >= 5 /*ms*/)
378 {
379 for (uint32_t i = 0; i < cSegments; i++)
380 {
381 rc = hdaR3StreamAddScheduleItem(pStreamShared, pStreamShared->State.aBdl[i].cb, cbMaxPeriod, i, pProps, &cbBorrow);
382 ASSERT_GUEST_RC_RETURN(rc, rc);
383 }
384 }
385 /* Otherwise, just divide the work into 3 or 4 portions and hope for the best.
386 It seems, though, that this only really work for windows vista if we avoid
387 working accross buffer lines. */
388 /** @todo This can be simplified/relaxed/uncluttered if we do DMA work when LPIB
389 * is read, assuming ofc that LPIB is read before each buffer update. */
390 else
391 {
392 uint32_t const cPeriods = cSegments != 3 && PDMAudioPropsBytesToMilli(pProps, cbCur) >= 4 * 5 /*ms*/
393 ? 4 : cSegments != 2 ? 3 : 2;
394 uint32_t const cbPeriod = PDMAudioPropsFloorBytesToFrame(pProps, cbCur / cPeriods);
395 uint32_t iBdle = 0;
396 uint32_t offBdle = 0;
397 for (uint32_t iPeriod = 0; iPeriod < cPeriods; iPeriod++)
398 {
399 if (iPeriod + 1 < cPeriods)
400 {
401 offBdle += cbPeriod;
402 while (iBdle < cSegments && offBdle >= pStreamShared->State.aBdl[iBdle].cb)
403 offBdle -= pStreamShared->State.aBdl[iBdle++].cb;
404 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbPeriod, cbMaxPeriod, offBdle != 0 ? iBdle : iBdle - 1,
405 pProps, &cbBorrow);
406 }
407 else
408 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur - iPeriod * cbPeriod, cbMaxPeriod, cSegments - 1,
409 pProps, &cbBorrow);
410 ASSERT_GUEST_RC_RETURN(rc, rc);
411 }
412
413 }
414 }
415 else if (cbCur)
416 {
417 /* The last BDLE didn't have IOC set, so we must continue processing
418 from the start till we hit one that has. */
419 uint32_t i;
420 for (i = 0; i < cSegments; i++)
421 {
422 cbCur += pStreamShared->State.aBdl[i].cb;
423 if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
424 break;
425 }
426 rc = hdaR3StreamAddScheduleItem(pStreamShared, cbCur, cbMaxPeriod, i, pProps, &cbBorrow);
427 ASSERT_GUEST_RC_RETURN(rc, rc);
428
429 /* The initial scheduling items covering the wrap around area are
430 considered a prologue and must not repeated later. */
431 Assert(cPotentialPrologue);
432 pStreamShared->State.cSchedulePrologue = (uint8_t)cPotentialPrologue;
433 }
434
435 AssertLogRelMsgReturn(cbBorrow == 0, ("HDA: Internal scheduling error on stream #%u: cbBorrow=%#x cbTotal=%#x cbCur=%#x\n",
436 pStreamShared->u8SD, cbBorrow, cbTotal, cbCur),
437 VERR_INTERNAL_ERROR_3);
438
439 /*
440 * If there is just one BDLE with IOC set, we have to make sure
441 * we've got at least two periods scheduled, otherwise there is
442 * a very good chance the guest will overwrite the start of the
443 * buffer before we ever get around to reading it.
444 */
445 if (cBufferIrqs == 1)
446 {
447 uint32_t i = pStreamShared->State.cSchedulePrologue;
448 Assert(i < pStreamShared->State.cSchedule);
449 if ( i + 1 == pStreamShared->State.cSchedule
450 && pStreamShared->State.aSchedule[i].cLoops == 1)
451 {
452 uint32_t const cbFirstHalf = PDMAudioPropsFloorBytesToFrame(pProps, pStreamShared->State.aSchedule[i].cbPeriod / 2);
453 uint32_t const cbOtherHalf = pStreamShared->State.aSchedule[i].cbPeriod - cbFirstHalf;
454 pStreamShared->State.aSchedule[i].cbPeriod = cbFirstHalf;
455 if (cbFirstHalf == cbOtherHalf)
456 pStreamShared->State.aSchedule[i].cLoops = 2;
457 else
458 {
459 pStreamShared->State.aSchedule[i + 1] = pStreamShared->State.aSchedule[i];
460 pStreamShared->State.aSchedule[i].cbPeriod = cbOtherHalf;
461 pStreamShared->State.cSchedule++;
462 }
463 }
464 }
465
466 /*
467 * Go over the schduling entries and calculate the timer ticks for each period.
468 */
469 LogRel2(("HDA: Stream #%u schedule: %u items, %u prologue\n",
470 pStreamShared->u8SD, pStreamShared->State.cSchedule, pStreamShared->State.cSchedulePrologue));
471 uint64_t const cbPerSec = PDMAudioPropsFramesToBytes(pProps, pProps->uHz);
472 for (uint32_t i = 0; i < pStreamShared->State.cSchedule; i++)
473 {
474 uint64_t const cTicks = ASMMultU64ByU32DivByU32(cTimerTicksPerSec, pStreamShared->State.aSchedule[i].cbPeriod, cbPerSec);
475 AssertLogRelMsgReturn((uint32_t)cTicks == cTicks, ("cTicks=%RU64 (%#RX64)\n", cTicks, cTicks), VERR_INTERNAL_ERROR_4);
476 pStreamShared->State.aSchedule[i].cPeriodTicks = RT_MAX((uint32_t)cTicks, 16);
477 LogRel2(("HDA: #%u: %u ticks / %u bytes, %u loops, BDLE%u L %u\n", i, pStreamShared->State.aSchedule[i].cPeriodTicks,
478 pStreamShared->State.aSchedule[i].cbPeriod, pStreamShared->State.aSchedule[i].cLoops,
479 pStreamShared->State.aSchedule[i].idxFirst, pStreamShared->State.aSchedule[i].cEntries));
480 }
481
482 return VINF_SUCCESS;
483}
484
485
486/**
487 * Sets up ((re-)iniitalizes) an HDA stream.
488 *
489 * @returns VBox status code. VINF_NO_CHANGE if the stream does not need
490 * be set-up again because the stream's (hardware) parameters did
491 * not change.
492 * @param pDevIns The device instance.
493 * @param pThis The shared HDA device state (for HW register
494 * parameters).
495 * @param pStreamShared HDA stream to set up, shared portion.
496 * @param pStreamR3 HDA stream to set up, ring-3 portion.
497 * @param uSD Stream descriptor number to assign it.
498 */
499int hdaR3StreamSetUp(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD)
500{
501 /* This must be valid all times. */
502 AssertReturn(uSD < HDA_MAX_STREAMS, VERR_INVALID_PARAMETER);
503
504 /* These member can only change on data corruption, despite what the code does further down (bird). */
505 AssertReturn(pStreamShared->u8SD == uSD, VERR_WRONG_ORDER);
506 AssertReturn(pStreamR3->u8SD == uSD, VERR_WRONG_ORDER);
507
508 const uint64_t u64BDLBase = RT_MAKE_U64(HDA_STREAM_REG(pThis, BDPL, uSD),
509 HDA_STREAM_REG(pThis, BDPU, uSD));
510 const uint16_t u16LVI = HDA_STREAM_REG(pThis, LVI, uSD);
511 const uint32_t u32CBL = HDA_STREAM_REG(pThis, CBL, uSD);
512 const uint8_t u8FIFOS = HDA_STREAM_REG(pThis, FIFOS, uSD) + 1;
513 uint8_t u8FIFOW = hdaSDFIFOWToBytes(HDA_STREAM_REG(pThis, FIFOW, uSD));
514 const uint16_t u16FMT = HDA_STREAM_REG(pThis, FMT, uSD);
515
516 /* Is the bare minimum set of registers configured for the stream?
517 * If not, bail out early, as there's nothing to do here for us (yet). */
518 if ( !u64BDLBase
519 || !u16LVI
520 || !u32CBL
521 || !u8FIFOS
522 || !u8FIFOW
523 || !u16FMT)
524 {
525 LogFunc(("[SD%RU8] Registers not set up yet, skipping (re-)initialization\n", uSD));
526 return VINF_SUCCESS;
527 }
528
529 /*
530 * Convert the config to PDM PCM properties and configure the stream.
531 */
532 PPDMAUDIOSTREAMCFG pCfg = &pStreamShared->State.Cfg;
533 int rc = hdaR3SDFMTToPCMProps(u16FMT, &pCfg->Props);
534 if (RT_SUCCESS(rc))
535 pCfg->enmDir = hdaGetDirFromSD(uSD);
536 else
537 {
538 LogRelMax(32, ("HDA: Warning: Format 0x%x for stream #%RU8 not supported\n", HDA_STREAM_REG(pThis, FMT, uSD), uSD));
539 return rc;
540 }
541
542 ASSERT_GUEST_LOGREL_MSG_RETURN( PDMAudioPropsFrameSize(&pCfg->Props) > 0
543 && u32CBL % PDMAudioPropsFrameSize(&pCfg->Props) == 0,
544 ("CBL for stream #%RU8 does not align to frame size (u32CBL=%u cbFrameSize=%u)\n",
545 uSD, u32CBL, PDMAudioPropsFrameSize(&pCfg->Props)),
546 VERR_INVALID_PARAMETER);
547
548 /* Make sure the guest behaves regarding the stream's FIFO. */
549 ASSERT_GUEST_LOGREL_MSG_STMT(u8FIFOW <= u8FIFOS,
550 ("Guest tried setting a bigger FIFOW (%RU8) than FIFOS (%RU8), limiting\n", u8FIFOW, u8FIFOS),
551 u8FIFOW = u8FIFOS /* ASSUMES that u8FIFOS has been validated. */);
552
553 pStreamShared->u8SD = uSD;
554
555 /* Update all register copies so that we later know that something has changed. */
556 pStreamShared->u64BDLBase = u64BDLBase;
557 pStreamShared->u16LVI = u16LVI;
558 pStreamShared->u32CBL = u32CBL;
559 pStreamShared->u8FIFOS = u8FIFOS;
560 pStreamShared->u8FIFOW = u8FIFOW;
561 pStreamShared->u16FMT = u16FMT;
562
563 /* The the stream's name, based on the direction. */
564 switch (pCfg->enmDir)
565 {
566 case PDMAUDIODIR_IN:
567# ifdef VBOX_WITH_AUDIO_HDA_MIC_IN
568# error "Implement me!"
569# else
570 pCfg->enmPath = PDMAUDIOPATH_IN_LINE;
571 RTStrCopy(pCfg->szName, sizeof(pCfg->szName), "Line In");
572# endif
573 break;
574
575 case PDMAUDIODIR_OUT:
576 /* Destination(s) will be set in hdaR3AddStreamOut(),
577 * based on the channels / stream layout. */
578 break;
579
580 default:
581 AssertFailedReturn(VERR_NOT_SUPPORTED);
582 break;
583 }
584
585 LogRel2(("HDA: Stream #%RU8 DMA @ 0x%x (%RU32 bytes = %RU64ms total)\n", uSD, pStreamShared->u64BDLBase,
586 pStreamShared->u32CBL, PDMAudioPropsBytesToMilli(&pCfg->Props, pStreamShared->u32CBL)));
587
588 /*
589 * Load the buffer descriptor list.
590 *
591 * Section 3.6.2 states that "the BDL should not be modified unless the RUN
592 * bit is 0", so it should be within the specs to read it once here and not
593 * re-read any BDLEs later.
594 */
595 /* Reset BDL state. */
596 RT_ZERO(pStreamShared->State.aBdl);
597 pStreamShared->State.offCurBdle = 0;
598 pStreamShared->State.idxCurBdle = 0;
599
600 uint32_t /*const*/ cTransferFragments = (pStreamShared->u16LVI & 0xff) + 1;
601 if (cTransferFragments <= 1)
602 LogRel(("HDA: Warning: Stream #%RU8 transfer buffer count invalid: (%RU16)! Buggy guest audio driver!\n", uSD, pStreamShared->u16LVI));
603 AssertLogRelReturn(cTransferFragments <= RT_ELEMENTS(pStreamShared->State.aBdl), VERR_INTERNAL_ERROR_5);
604 pStreamShared->State.cBdles = cTransferFragments;
605
606 /* Load them. */
607 rc = PDMDevHlpPCIPhysRead(pDevIns, u64BDLBase, pStreamShared->State.aBdl,
608 sizeof(pStreamShared->State.aBdl[0]) * cTransferFragments);
609 AssertRC(rc);
610
611 /* Check what we just loaded. Refuse overly large buffer lists. */
612 uint64_t cbTotal = 0;
613 uint32_t cBufferIrqs = 0;
614 for (uint32_t i = 0; i < cTransferFragments; i++)
615 {
616 if (pStreamShared->State.aBdl[i].fFlags & HDA_BDLE_F_IOC)
617 cBufferIrqs++;
618 cbTotal += pStreamShared->State.aBdl[i].cb;
619 }
620 ASSERT_GUEST_STMT_RETURN(cbTotal < _2G,
621 LogRelMax(32, ("HDA: Error: Stream #%u is configured with an insane amount of buffer space - refusing do work with it: %RU64 (%#RX64) bytes.\n",
622 uSD, cbTotal, cbTotal)),
623 VERR_NOT_SUPPORTED);
624 ASSERT_GUEST_STMT_RETURN(cbTotal == u32CBL,
625 LogRelMax(32, ("HDA: Warning: Stream #%u has a mismatch between CBL and configured buffer space: %RU32 (%#RX32) vs %RU64 (%#RX64)\n",
626 uSD, u32CBL, u32CBL, cbTotal, cbTotal)),
627 VERR_NOT_SUPPORTED);
628
629 /*
630 * Create a DMA timer schedule.
631 */
632 rc = hdaR3StreamCreateSchedule(pStreamShared, cTransferFragments, cBufferIrqs, (uint32_t)cbTotal,
633 PDMAudioPropsMilliToBytes(&pCfg->Props, 100 /** @todo make configurable */),
634 PDMDevHlpTimerGetFreq(pDevIns, pStreamShared->hTimer), &pCfg->Props);
635 if (RT_FAILURE(rc))
636 return rc;
637
638 pStreamShared->State.cbCurDmaPeriod = pStreamShared->State.aSchedule[0].cbPeriod;
639
640 /*
641 * Calculate the transfer Hz for use in the circular buffer calculation
642 * and the average period for the scheduling hint.
643 */
644 uint32_t cbMaxPeriod = 0;
645 uint32_t cbMinPeriod = UINT32_MAX;
646 uint64_t cTicks = 0;
647 uint32_t cPeriods = 0;
648 for (uint32_t i = pStreamShared->State.cSchedulePrologue; i < pStreamShared->State.cSchedule; i++)
649 {
650 uint32_t cbPeriod = pStreamShared->State.aSchedule[i].cbPeriod;
651 cbMaxPeriod = RT_MAX(cbMaxPeriod, cbPeriod);
652 cbMinPeriod = RT_MIN(cbMinPeriod, cbPeriod);
653 cPeriods += pStreamShared->State.aSchedule[i].cLoops;
654 cTicks += pStreamShared->State.aSchedule[i].cPeriodTicks * pStreamShared->State.aSchedule[i].cLoops;
655 }
656 /* Only consider the prologue in relation to the max period. */
657 for (uint32_t i = 0; i < pStreamShared->State.cSchedulePrologue; i++)
658 cbMaxPeriod = RT_MAX(cbMaxPeriod, pStreamShared->State.aSchedule[i].cbPeriod);
659
660 AssertLogRelReturn(cPeriods > 0, VERR_INTERNAL_ERROR_3);
661 uint64_t const cbTransferPerSec = RT_MAX(PDMAudioPropsFramesToBytes(&pCfg->Props, pCfg->Props.uHz),
662 4096 /* zero div prevention: min is 6kHz, picked 4k in case I'm mistaken */);
663 unsigned uTransferHz = cbTransferPerSec * 1000 / cbMaxPeriod;
664 LogRel2(("HDA: Stream #%RU8 needs a %u.%03u Hz timer rate (period: %u..%u host bytes)\n",
665 uSD, uTransferHz / 1000, uTransferHz % 1000, cbMinPeriod, cbMaxPeriod));
666 uTransferHz /= 1000;
667
668 if (uTransferHz > 400) /* Anything above 400 Hz looks fishy -- tell the user. */
669 LogRelMax(32, ("HDA: Warning: Calculated transfer Hz rate for stream #%RU8 looks incorrect (%u), please re-run with audio debug mode and report a bug\n",
670 uSD, uTransferHz));
671
672 pStreamShared->State.cbAvgTransfer = (uint32_t)(cbTotal + cPeriods - 1) / cPeriods;
673
674 /* Calculate the average scheduling period length in nanoseconds. */
675 uint64_t const cTimerResolution = PDMDevHlpTimerGetFreq(pDevIns, pStreamShared->hTimer);
676 Assert(cTimerResolution <= UINT32_MAX);
677 uint64_t const cNsPerPeriod = ASMMultU64ByU32DivByU32(cTicks / cPeriods, RT_NS_1SEC, cTimerResolution);
678 AssertLogRelReturn(cNsPerPeriod > 0, VERR_INTERNAL_ERROR_3);
679
680 /* For input streams we must determin a pre-buffering requirement.
681 We use the initial delay as a basis here, though we must have at
682 least two max periods worth of data queued up due to the way we
683 work the AIO thread. */
684 pStreamShared->State.fInputPreBuffered = false;
685 pStreamShared->State.cbInputPreBuffer = PDMAudioPropsMilliToBytes(&pCfg->Props, pThis->msInitialDelay);
686 pStreamShared->State.cbInputPreBuffer = RT_MIN(cbMaxPeriod * 2, pStreamShared->State.cbInputPreBuffer);
687
688 /*
689 * Set up data transfer stuff.
690 */
691 /* Set I/O scheduling hint for the backends. */
692 pCfg->Device.cMsSchedulingHint = cNsPerPeriod > RT_NS_1MS ? (cNsPerPeriod + RT_NS_1MS / 2) / RT_NS_1MS : 1;
693 LogRel2(("HDA: Stream #%RU8 set scheduling hint for the backends to %RU32ms\n", uSD, pCfg->Device.cMsSchedulingHint));
694
695 /* Make sure to also update the stream's DMA counter (based on its current LPIB value). */
696 /** @todo r=bird: We use LPIB as-is here, so if it's not zero we have to
697 * locate the right place in the schedule and whatnot...
698 *
699 * This is a similar scenario as when loading state saved, btw.
700 */
701 if (HDA_STREAM_REG(pThis, LPIB, uSD) != 0)
702 LogRel2(("HDA: Warning! Stream #%RU8 is set up with LPIB=%#RX32 instead of zero!\n", uSD, HDA_STREAM_REG(pThis, LPIB, uSD)));
703 hdaStreamSetPositionAbs(pStreamShared, pDevIns, pThis, HDA_STREAM_REG(pThis, LPIB, uSD));
704
705# ifdef LOG_ENABLED
706 hdaR3BDLEDumpAll(pDevIns, pThis, pStreamShared->u64BDLBase, pStreamShared->u16LVI + 1);
707# endif
708
709 /*
710 * Set up internal ring buffer.
711 */
712
713 /* (Re-)Allocate the stream's internal DMA buffer,
714 * based on the timing *and* PCM properties we just got above. */
715 if (pStreamR3->State.pCircBuf)
716 {
717 RTCircBufDestroy(pStreamR3->State.pCircBuf);
718 pStreamR3->State.pCircBuf = NULL;
719 pStreamR3->State.StatDmaBufSize = 0;
720 pStreamR3->State.StatDmaBufUsed = 0;
721 }
722 pStreamShared->State.offWrite = 0;
723 pStreamShared->State.offRead = 0;
724
725 /*
726 * The default internal ring buffer size must be:
727 *
728 * - Large enough for at least three periodic DMA transfers.
729 *
730 * It is critically important that we don't experience underruns
731 * in the DMA OUT code, because it will cause the buffer processing
732 * to get skewed and possibly overlap with what the guest is updating.
733 * At the time of writing (2021-03-05) there is no code for getting
734 * back into sync there.
735 *
736 * - Large enough for at least three I/O scheduling hints.
737 *
738 * We want to lag behind a DMA period or two, but there must be
739 * sufficent space for the AIO thread to get schedule and shuffle
740 * data thru the mixer and onto the host audio hardware.
741 *
742 * - Both above with plenty to spare.
743 *
744 * So, just take the longest of the two periods and multipling it by 6.
745 * We aren't not talking about very large base buffers heres, so size isn't
746 * an issue.
747 *
748 * Note: Use pCfg->Props as PCM properties here, as we only want to store the
749 * samples we actually need, in other words, skipping the interleaved
750 * channels we don't support / need to save space.
751 */
752 uint32_t cbCircBuf = PDMAudioPropsMilliToBytes(&pCfg->Props, pThis->msInitialDelay + RT_MS_1SEC * 6 / uTransferHz);
753 LogRel2(("HDA: Stream #%RU8 default ring buffer size is %RU32 bytes / %RU64 ms\n",
754 uSD, cbCircBuf, PDMAudioPropsBytesToMilli(&pCfg->Props, cbCircBuf)));
755
756 uint32_t msCircBufCfg = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? pThis->cMsCircBufIn : pThis->cMsCircBufOut;
757 if (msCircBufCfg) /* Anything set via CFGM? */
758 {
759 cbCircBuf = PDMAudioPropsMilliToBytes(&pCfg->Props, msCircBufCfg);
760 LogRel2(("HDA: Stream #%RU8 is using a custom ring buffer size of %RU32 bytes / %RU64 ms\n",
761 uSD, cbCircBuf, PDMAudioPropsBytesToMilli(&pCfg->Props, cbCircBuf)));
762 }
763
764 /* Serious paranoia: */
765 ASSERT_GUEST_LOGREL_MSG_STMT(cbCircBuf % PDMAudioPropsFrameSize(&pCfg->Props) == 0,
766 ("Ring buffer size (%RU32) for stream #%RU8 not aligned to the (host) frame size (%RU8)\n",
767 cbCircBuf, uSD, PDMAudioPropsFrameSize(&pCfg->Props)),
768 rc = VERR_INVALID_PARAMETER);
769 ASSERT_GUEST_LOGREL_MSG_STMT(cbCircBuf, ("Ring buffer size for stream #%RU8 is invalid\n", uSD),
770 rc = VERR_INVALID_PARAMETER);
771 if (RT_SUCCESS(rc))
772 {
773 rc = RTCircBufCreate(&pStreamR3->State.pCircBuf, cbCircBuf);
774 if (RT_SUCCESS(rc))
775 {
776 pStreamR3->State.StatDmaBufSize = cbCircBuf;
777
778 /*
779 * Forward the timer frequency hint to TM as well for better accuracy on
780 * systems w/o preemption timers (also good for 'info timers').
781 */
782 PDMDevHlpTimerSetFrequencyHint(pDevIns, pStreamShared->hTimer, uTransferHz);
783 }
784 }
785
786 if (RT_FAILURE(rc))
787 LogRelMax(32, ("HDA: Initializing stream #%RU8 failed with %Rrc\n", uSD, rc));
788
789# ifdef VBOX_WITH_DTRACE
790 VBOXDD_HDA_STREAM_SETUP((uint32_t)uSD, rc, pStreamShared->State.Cfg.Props.uHz,
791 pStreamShared->State.aSchedule[pStreamShared->State.cSchedule - 1].cPeriodTicks,
792 pStreamShared->State.aSchedule[pStreamShared->State.cSchedule - 1].cbPeriod);
793# endif
794 return rc;
795}
796
797/**
798 * Resets an HDA stream.
799 *
800 * @param pThis The shared HDA device state.
801 * @param pThisCC The ring-3 HDA device state.
802 * @param pStreamShared HDA stream to reset (shared).
803 * @param pStreamR3 HDA stream to reset (ring-3).
804 * @param uSD Stream descriptor (SD) number to use for this stream.
805 */
806void hdaR3StreamReset(PHDASTATE pThis, PHDASTATER3 pThisCC, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD)
807{
808 LogFunc(("[SD%RU8] Reset\n", uSD));
809
810 /*
811 * Assert some sanity.
812 */
813 AssertPtr(pThis);
814 AssertPtr(pStreamShared);
815 AssertPtr(pStreamR3);
816 Assert(uSD < HDA_MAX_STREAMS);
817 Assert(pStreamShared->u8SD == uSD);
818 Assert(pStreamR3->u8SD == uSD);
819 AssertMsg(!pStreamShared->State.fRunning, ("[SD%RU8] Cannot reset stream while in running state\n", uSD));
820
821 /*
822 * Set reset state.
823 */
824 Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false); /* No nested calls. */
825 ASMAtomicXchgBool(&pStreamShared->State.fInReset, true);
826
827 /*
828 * Second, initialize the registers.
829 */
830 /* See 6.2.33: Clear on reset. */
831 HDA_STREAM_REG(pThis, STS, uSD) = 0;
832 /* According to the ICH6 datasheet, 0x40000 is the default value for stream descriptor register 23:20
833 * bits are reserved for stream number 18.2.33, resets SDnCTL except SRST bit. */
834 HDA_STREAM_REG(pThis, CTL, uSD) = HDA_SDCTL_TP | (HDA_STREAM_REG(pThis, CTL, uSD) & HDA_SDCTL_SRST);
835 /* ICH6 defines default values (120 bytes for input and 192 bytes for output descriptors) of FIFO size. 18.2.39. */
836 HDA_STREAM_REG(pThis, FIFOS, uSD) = hdaGetDirFromSD(uSD) == PDMAUDIODIR_IN ? HDA_SDIFIFO_120B : HDA_SDOFIFO_192B;
837 /* See 18.2.38: Always defaults to 0x4 (32 bytes). */
838 HDA_STREAM_REG(pThis, FIFOW, uSD) = HDA_SDFIFOW_32B;
839 HDA_STREAM_REG(pThis, LPIB, uSD) = 0;
840 HDA_STREAM_REG(pThis, CBL, uSD) = 0;
841 HDA_STREAM_REG(pThis, LVI, uSD) = 0;
842 HDA_STREAM_REG(pThis, FMT, uSD) = 0;
843 HDA_STREAM_REG(pThis, BDPU, uSD) = 0;
844 HDA_STREAM_REG(pThis, BDPL, uSD) = 0;
845
846 /* Assign the default mixer sink to the stream. */
847 pStreamR3->pMixSink = hdaR3GetDefaultSink(pThisCC, uSD);
848 if (pStreamR3->State.pAioRegSink)
849 {
850 int rc2 = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
851 AssertRC(rc2);
852 pStreamR3->State.pAioRegSink = NULL;
853 }
854
855 /* Reset transfer stuff. */
856 pStreamShared->State.cTransferPendingInterrupts = 0;
857 pStreamShared->State.tsTransferLast = 0;
858 pStreamShared->State.tsTransferNext = 0;
859
860 /* Initialize timestamps. */
861 pStreamShared->State.tsLastTransferNs = 0;
862 pStreamShared->State.tsLastReadNs = 0;
863 pStreamShared->State.tsAioDelayEnd = UINT64_MAX;
864 pStreamShared->State.tsStart = 0;
865
866 RT_ZERO(pStreamShared->State.aBdl);
867 RT_ZERO(pStreamShared->State.aSchedule);
868 pStreamShared->State.offCurBdle = 0;
869 pStreamShared->State.cBdles = 0;
870 pStreamShared->State.idxCurBdle = 0;
871 pStreamShared->State.cSchedulePrologue = 0;
872 pStreamShared->State.cSchedule = 0;
873 pStreamShared->State.idxSchedule = 0;
874 pStreamShared->State.idxScheduleLoop = 0;
875 pStreamShared->State.fInputPreBuffered = false;
876
877 if (pStreamR3->State.pCircBuf)
878 RTCircBufReset(pStreamR3->State.pCircBuf);
879 pStreamShared->State.offWrite = 0;
880 pStreamShared->State.offRead = 0;
881
882# ifdef DEBUG
883 pStreamR3->Dbg.cReadsTotal = 0;
884 pStreamR3->Dbg.cbReadTotal = 0;
885 pStreamR3->Dbg.tsLastReadNs = 0;
886 pStreamR3->Dbg.cWritesTotal = 0;
887 pStreamR3->Dbg.cbWrittenTotal = 0;
888 pStreamR3->Dbg.cWritesHz = 0;
889 pStreamR3->Dbg.cbWrittenHz = 0;
890 pStreamR3->Dbg.tsWriteSlotBegin = 0;
891# endif
892
893 /* Report that we're done resetting this stream. */
894 HDA_STREAM_REG(pThis, CTL, uSD) = 0;
895
896# ifdef VBOX_WITH_DTRACE
897 VBOXDD_HDA_STREAM_RESET((uint32_t)uSD);
898# endif
899 LogFunc(("[SD%RU8] Reset\n", uSD));
900
901 /* Exit reset mode. */
902 ASMAtomicXchgBool(&pStreamShared->State.fInReset, false);
903}
904
905/**
906 * Enables or disables an HDA audio stream.
907 *
908 * @returns VBox status code.
909 * @param pThis The shared HDA device state.
910 * @param pStreamShared HDA stream to enable or disable - shared bits.
911 * @param pStreamR3 HDA stream to enable or disable - ring-3 bits.
912 * @param fEnable Whether to enable or disble the stream.
913 */
914int hdaR3StreamEnable(PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, bool fEnable)
915{
916 AssertPtr(pStreamR3);
917 AssertPtr(pStreamShared);
918
919 LogFunc(("[SD%RU8] fEnable=%RTbool, pMixSink=%p\n", pStreamShared->u8SD, fEnable, pStreamR3->pMixSink));
920
921 /* First, enable or disable the stream and the stream's sink, if any. */
922 int rc = VINF_SUCCESS;
923 PAUDMIXSINK const pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
924 if (pSink)
925 {
926 if (fEnable)
927 {
928 if (pStreamR3->State.pAioRegSink != pSink)
929 {
930 if (pStreamR3->State.pAioRegSink)
931 {
932 rc = AudioMixerSinkRemoveUpdateJob(pStreamR3->State.pAioRegSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3);
933 AssertRC(rc);
934 }
935 rc = AudioMixerSinkAddUpdateJob(pSink, hdaR3StreamUpdateAsyncIoJob, pStreamR3,
936 pStreamShared->State.Cfg.Device.cMsSchedulingHint);
937 AssertLogRelRC(rc);
938 pStreamR3->State.pAioRegSink = RT_SUCCESS(rc) ? pSink : NULL;
939 }
940 rc = AudioMixerSinkStart(pSink);
941 }
942 else
943 rc = AudioMixerSinkDrainAndStop(pSink,
944 pStreamR3->State.pCircBuf ? (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf) : 0);
945 }
946 if ( RT_SUCCESS(rc)
947 && fEnable
948 && pStreamR3->Dbg.Runtime.fEnabled)
949 {
950 Assert(AudioHlpPcmPropsAreValid(&pStreamShared->State.Cfg.Props));
951
952 if (fEnable)
953 {
954 if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileStream))
955 {
956 int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileStream, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
957 &pStreamShared->State.Cfg.Props);
958 AssertRC(rc2);
959 }
960
961 if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileDMARaw))
962 {
963 int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileDMARaw, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
964 &pStreamShared->State.Cfg.Props);
965 AssertRC(rc2);
966 }
967
968 if (!AudioHlpFileIsOpen(pStreamR3->Dbg.Runtime.pFileDMAMapped))
969 {
970 int rc2 = AudioHlpFileOpen(pStreamR3->Dbg.Runtime.pFileDMAMapped, AUDIOHLPFILE_DEFAULT_OPEN_FLAGS,
971 &pStreamShared->State.Cfg.Props);
972 AssertRC(rc2);
973 }
974 }
975 }
976
977 if (RT_SUCCESS(rc))
978 {
979 if (fEnable)
980 pStreamShared->State.tsTransferLast = 0; /* Make sure it's not stale and messes up WALCLK calculations. */
981 pStreamShared->State.fRunning = fEnable;
982
983 /*
984 * Set the FIFORDY bit when we start running and clear it when stopping.
985 *
986 * This prevents Linux from timing out in snd_hdac_stream_sync when starting
987 * a stream. Technically, Linux also uses the SSYNC feature there, but we
988 * can get away with just setting the FIFORDY bit for now.
989 */
990 if (fEnable)
991 HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) |= HDA_SDSTS_FIFORDY;
992 else
993 HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) &= ~HDA_SDSTS_FIFORDY;
994 }
995
996 LogFunc(("[SD%RU8] rc=%Rrc\n", pStreamShared->u8SD, rc));
997 return rc;
998}
999
1000/**
1001 * Marks the stream as started.
1002 *
1003 * Used after the stream has been enabled and the DMA timer has been armed.
1004 */
1005void hdaR3StreamMarkStarted(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint64_t tsNow)
1006{
1007 pStreamShared->State.tsLastReadNs = RTTimeNanoTS();
1008 pStreamShared->State.tsStart = tsNow;
1009 pStreamShared->State.tsAioDelayEnd = tsNow + PDMDevHlpTimerFromMilli(pDevIns, pStreamShared->hTimer, pThis->msInitialDelay);
1010 Log3Func(("#%u: tsStart=%RU64 tsAioDelayEnd=%RU64 tsLastReadNs=%RU64\n", pStreamShared->u8SD,
1011 pStreamShared->State.tsStart, pStreamShared->State.tsAioDelayEnd, pStreamShared->State.tsLastReadNs));
1012
1013}
1014
1015/**
1016 * Marks the stream as stopped.
1017 */
1018void hdaR3StreamMarkStopped(PHDASTREAM pStreamShared)
1019{
1020 Log3Func(("#%u\n", pStreamShared->u8SD));
1021 pStreamShared->State.tsAioDelayEnd = UINT64_MAX;
1022}
1023
1024#endif /* IN_RING3 */
1025#if defined(IN_RING3) || defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA)
1026
1027/**
1028 * Updates an HDA stream's current read or write buffer position (depending on the stream type) by
1029 * setting its associated LPIB register and DMA position buffer (if enabled) to an absolute value.
1030 *
1031 * @param pStreamShared HDA stream to update read / write position for (shared).
1032 * @param pDevIns The device instance.
1033 * @param pThis The shared HDA device state.
1034 * @param uLPIB Absolute position (in bytes) to set current read / write position to.
1035 */
1036static void hdaStreamSetPositionAbs(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t uLPIB)
1037{
1038 AssertPtrReturnVoid(pStreamShared);
1039 AssertMsgStmt(uLPIB <= pStreamShared->u32CBL, ("%#x\n", uLPIB), uLPIB = pStreamShared->u32CBL);
1040
1041 Log3Func(("[SD%RU8] LPIB=%RU32 (DMA Position Buffer Enabled: %RTbool)\n", pStreamShared->u8SD, uLPIB, pThis->fDMAPosition));
1042
1043 /* Update LPIB in any case. */
1044 HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) = uLPIB;
1045
1046 /* Do we need to tell the current DMA position? */
1047 if (pThis->fDMAPosition)
1048 {
1049 /*
1050 * Linux switched to using the position buffers some time during 2.6.x.
1051 * 2.6.12 used LPIB, 2.6.17 defaulted to DMA position buffers, between
1052 * the two version things were being changing quite a bit.
1053 *
1054 * Since 2.6.17, they will treat a zero DMA position value during the first
1055 * period/IRQ as reason to fall back to LPIB mode (see azx_position_ok in
1056 * 2.6.27+, and azx_pcm_pointer before that). They later also added
1057 * UINT32_MAX to the values causing same.
1058 *
1059 * Since 2.6.35 azx_position_ok will read the wall clock register before
1060 * determining the position.
1061 */
1062 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns,
1063 pThis->u64DPBase + (pStreamShared->u8SD * 2 * sizeof(uint32_t)),
1064 (void *)&uLPIB, sizeof(uint32_t));
1065 AssertRC(rc2);
1066 }
1067}
1068
1069
1070/**
1071 * Updates an HDA stream's current read or write buffer position (depending on the stream type) by
1072 * adding a value to its associated LPIB register and DMA position buffer (if enabled).
1073 *
1074 * @note Handles automatic CBL wrap-around.
1075 *
1076 * @param pStreamShared HDA stream to update read / write position for (shared).
1077 * @param pDevIns The device instance.
1078 * @param pThis The shared HDA device state.
1079 * @param cbToAdd Position (in bytes) to add to the current read / write position.
1080 */
1081static void hdaStreamSetPositionAdd(PHDASTREAM pStreamShared, PPDMDEVINS pDevIns, PHDASTATE pThis, uint32_t cbToAdd)
1082{
1083 if (cbToAdd) /* No need to update anything if 0. */
1084 {
1085 uint32_t const uCBL = pStreamShared->u32CBL;
1086 if (uCBL) /* paranoia */
1087 {
1088 uint32_t uNewLpid = HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD) + cbToAdd;
1089# if 1 /** @todo r=bird: this is wrong according to the spec */
1090 uNewLpid %= uCBL;
1091# else
1092 /* The spec says it goes to CBL then wraps arpimd to 1, not back to zero. See 3.3.37. */
1093 if (uNewLpid > uCBL)
1094 uNewLpid %= uCBL;
1095# endif
1096 hdaStreamSetPositionAbs(pStreamShared, pDevIns, pThis, uNewLpid);
1097 }
1098 }
1099}
1100
1101#endif /* IN_RING3 || VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
1102#ifdef IN_RING3
1103
1104/**
1105 * Retrieves the available size of (buffered) audio data (in bytes) of a given HDA stream.
1106 *
1107 * @returns Available data (in bytes).
1108 * @param pStreamR3 HDA stream to retrieve size for (ring-3).
1109 */
1110static uint32_t hdaR3StreamGetUsed(PHDASTREAMR3 pStreamR3)
1111{
1112 AssertPtrReturn(pStreamR3, 0);
1113
1114 if (pStreamR3->State.pCircBuf)
1115 return (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1116 return 0;
1117}
1118
1119/**
1120 * Retrieves the free size of audio data (in bytes) of a given HDA stream.
1121 *
1122 * @returns Free data (in bytes).
1123 * @param pStreamR3 HDA stream to retrieve size for (ring-3).
1124 */
1125static uint32_t hdaR3StreamGetFree(PHDASTREAMR3 pStreamR3)
1126{
1127 AssertPtrReturn(pStreamR3, 0);
1128
1129 if (pStreamR3->State.pCircBuf)
1130 return (uint32_t)RTCircBufFree(pStreamR3->State.pCircBuf);
1131 return 0;
1132}
1133
1134#endif /* IN_RING3 */
1135#if defined(IN_RING3) || defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA)
1136
1137/**
1138 * Get the current address and number of bytes left in the current BDLE.
1139 *
1140 * @returns The current physical address.
1141 * @param pStreamShared The stream to check.
1142 * @param pcbLeft The number of bytes left at the returned address.
1143 */
1144DECLINLINE(RTGCPHYS) hdaStreamDmaBufGet(PHDASTREAM pStreamShared, uint32_t *pcbLeft)
1145{
1146 uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1147 AssertStmt(idxBdle < pStreamShared->State.cBdles, idxBdle = 0);
1148
1149 uint32_t const cbCurBdl = pStreamShared->State.aBdl[idxBdle].cb;
1150 uint32_t offCurBdle = pStreamShared->State.offCurBdle;
1151 AssertStmt(pStreamShared->State.offCurBdle <= cbCurBdl, offCurBdle = cbCurBdl);
1152
1153 *pcbLeft = cbCurBdl - offCurBdle;
1154 return pStreamShared->State.aBdl[idxBdle].GCPhys + offCurBdle;
1155}
1156
1157/**
1158 * Checks if the current BDLE is completed.
1159 *
1160 * @retval true if complete
1161 * @retval false if not.
1162 * @param pStreamShared The stream to check.
1163 */
1164DECLINLINE(bool) hdaStreamDmaBufIsComplete(PHDASTREAM pStreamShared)
1165{
1166 uint8_t const idxBdle = pStreamShared->State.idxCurBdle;
1167 AssertReturn(idxBdle < pStreamShared->State.cBdles, true);
1168
1169 uint32_t const cbCurBdl = pStreamShared->State.aBdl[idxBdle].cb;
1170 uint32_t const offCurBdle = pStreamShared->State.offCurBdle;
1171 Assert(offCurBdle <= cbCurBdl);
1172 return offCurBdle >= cbCurBdl;
1173}
1174
1175/**
1176 * Checks if the current BDLE needs a completion IRQ.
1177 *
1178 * @retval true if IRQ is needed.
1179 * @retval false if not.
1180 * @param pStreamShared The stream to check.
1181 */
1182DECLINLINE(bool) hdaStreamDmaBufNeedsIrq(PHDASTREAM pStreamShared)
1183{
1184 uint8_t const idxBdle = pStreamShared->State.idxCurBdle;
1185 AssertReturn(idxBdle < pStreamShared->State.cBdles, false);
1186 return (pStreamShared->State.aBdl[idxBdle].fFlags & HDA_BDLE_F_IOC) != 0;
1187}
1188
1189/**
1190 * Advances the DMA engine to the next BDLE.
1191 *
1192 * @param pStreamShared The stream which DMA engine is to be updated.
1193 */
1194DECLINLINE(void) hdaStreamDmaBufAdvanceToNext(PHDASTREAM pStreamShared)
1195{
1196 uint8_t idxBdle = pStreamShared->State.idxCurBdle;
1197 Assert(pStreamShared->State.offCurBdle == pStreamShared->State.aBdl[idxBdle].cb);
1198
1199 if (idxBdle < pStreamShared->State.cBdles - 1)
1200 idxBdle++;
1201 else
1202 idxBdle = 0;
1203 pStreamShared->State.idxCurBdle = idxBdle;
1204 pStreamShared->State.offCurBdle = 0;
1205}
1206
1207#endif /* defined(IN_RING3) || defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA) */
1208#ifdef IN_RING3
1209
1210/**
1211 * Common do-DMA prologue code.
1212 *
1213 * @retval true if DMA processing can take place
1214 * @retval false if caller should return immediately.
1215 * @param pThis The shared HDA device state.
1216 * @param pStreamShared HDA stream to update (shared).
1217 * @param pStreamR3 HDA stream to update (ring-3).
1218 * @param uSD The stream ID (for asserting).
1219 * @param tsNowNs The current RTTimeNano() value.
1220 * @param pszFunction The function name (for logging).
1221 */
1222DECLINLINE(bool) hdaR3StreamDoDmaPrologue(PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD,
1223 uint64_t tsNowNs, const char *pszFunction)
1224{
1225 RT_NOREF(uSD, pszFunction);
1226
1227 /*
1228 * Check if we should skip town...
1229 */
1230 /* Stream not running (anymore)? */
1231 if (pStreamShared->State.fRunning)
1232 { /* likely */ }
1233 else
1234 {
1235 Log3(("%s: [SD%RU8] Not running, skipping transfer\n", pszFunction, uSD));
1236 return false;
1237 }
1238
1239 if (!(HDA_STREAM_REG(pThis, STS, uSD) & HDA_SDSTS_BCIS))
1240 { /* likely */ }
1241 else
1242 {
1243 /** @todo r=bird: This is a bit fishy. We should make effort the reschedule
1244 * the transfer immediately after the guest clears the interrupt.
1245 * The same fishy code is present in AC'97 with just a little
1246 * explanation as here, see @bugref{9890#c95}.
1247 *
1248 * The reasoning is probably that the developer noticed some windows
1249 * versions don't like having their BCIS interrupts bundled. There were
1250 * comments to that effect elsewhere, probably as a result of a fixed
1251 * uTimerHz approach to DMA scheduling. However, pausing DMA for a
1252 * period isn't going to help us with the host backends, as they don't
1253 * pause and will want samples ASAP. So, we should at least unpause
1254 * DMA as quickly as we possible when BCIS is cleared. We might even
1255 * not skip it iff the DMA work here doesn't involve raising any IOC,
1256 * which is possible although unlikely. */
1257 Log3(("%s: [SD%RU8] BCIS bit set, skipping transfer\n", pszFunction, uSD));
1258 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaSkippedPendingBcis);
1259 Log(("%s: [SD%RU8] BCIS bit set, skipping transfer\n", pszFunction, uSD));
1260# ifdef HDA_STRICT
1261 /* Timing emulation bug or guest is misbehaving -- let me know. */
1262 AssertMsgFailed(("%s: BCIS bit for stream #%RU8 still set when it shouldn't\n", pszFunction, uSD));
1263# endif
1264 return false;
1265 }
1266
1267 /*
1268 * Stream sanity checks.
1269 */
1270 /* Register sanity checks. */
1271 Assert(uSD < HDA_MAX_STREAMS);
1272 Assert(pStreamShared->u64BDLBase);
1273 Assert(pStreamShared->u32CBL);
1274 Assert(pStreamShared->u8FIFOS);
1275
1276 /* State sanity checks. */
1277 Assert(ASMAtomicReadBool(&pStreamShared->State.fInReset) == false);
1278 Assert(ASMAtomicReadBool(&pStreamShared->State.fRunning));
1279
1280 /*
1281 * Some timestamp stuff for logging/debugging.
1282 */
1283 /*const uint64_t tsNowNs = RTTimeNanoTS();*/
1284 Log3(("%s: [SD%RU8] tsDeltaNs=%'RU64 ns\n", pszFunction, uSD, tsNowNs - pStreamShared->State.tsLastTransferNs));
1285 pStreamShared->State.tsLastTransferNs = tsNowNs;
1286
1287 return true;
1288}
1289
1290/**
1291 * Common do-DMA epilogue.
1292 *
1293 * @param pDevIns The device instance.
1294 * @param pStreamShared The HDA stream (shared).
1295 * @param pStreamR3 The HDA stream (ring-3).
1296 */
1297DECLINLINE(void) hdaR3StreamDoDmaEpilogue(PPDMDEVINS pDevIns, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
1298{
1299 /*
1300 * We must update this in the epilogue rather than in the prologue
1301 * as it is used for WALCLK calculation and we must make sure the
1302 * guest doesn't think we've processed the current period till we
1303 * actually have.
1304 */
1305 pStreamShared->State.tsTransferLast = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer);
1306
1307 /*
1308 * Update the buffer statistics.
1309 */
1310 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1311}
1312
1313#endif /* IN_RING3 */
1314
1315#if defined(IN_RING3) || defined(VBOX_HDA_WITH_ON_REG_ACCESS_DMA)
1316/**
1317 * Completes a BDLE at the end of a DMA loop iteration, if possible.
1318 *
1319 * @retval true if buffer completed and new loaded.
1320 * @retval false if buffer not completed.
1321 * @param pDevIns The device instance.
1322 * @param pThis The shared HDA device state.
1323 * @param pStreamShared HDA stream to update (shared).
1324 * @param pszFunction The function name (for logging).
1325 */
1326DECLINLINE(bool) hdaStreamDoDmaMaybeCompleteBuffer(PPDMDEVINS pDevIns, PHDASTATE pThis,
1327 PHDASTREAM pStreamShared, const char *pszFunction)
1328{
1329 RT_NOREF(pszFunction);
1330
1331 /*
1332 * Is the buffer descriptor complete.
1333 */
1334 if (hdaStreamDmaBufIsComplete(pStreamShared))
1335 {
1336 Log3(("%s: [SD%RU8] Completed BDLE%u %#RX64 LB %#RX32 fFlags=%#x\n", pszFunction, pStreamShared->u8SD,
1337 pStreamShared->State.idxCurBdle, pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].GCPhys,
1338 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].cb,
1339 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].fFlags));
1340
1341 /* Does the current BDLE require an interrupt to be sent? */
1342 if (hdaStreamDmaBufNeedsIrq(pStreamShared))
1343 {
1344 /* If the IOCE ("Interrupt On Completion Enable") bit of the SDCTL
1345 register is set we need to generate an interrupt. */
1346 if (HDA_STREAM_REG(pThis, CTL, pStreamShared->u8SD) & HDA_SDCTL_IOCE)
1347 {
1348 /* Assert the interrupt before actually fetching the next BDLE below. */
1349 pStreamShared->State.cTransferPendingInterrupts = 1;
1350 Log3(("%s: [SD%RU8] Scheduling interrupt\n", pszFunction, pStreamShared->u8SD));
1351
1352 /* Trigger an interrupt first and let hdaRegWriteSDSTS() deal with
1353 * ending / beginning of a period. */
1354 /** @todo r=bird: What does the above comment mean? */
1355 HDA_STREAM_REG(pThis, STS, pStreamShared->u8SD) |= HDA_SDSTS_BCIS;
1356 HDA_PROCESS_INTERRUPT(pDevIns, pThis);
1357 }
1358 }
1359
1360 /*
1361 * Advance to the next BDLE.
1362 */
1363 hdaStreamDmaBufAdvanceToNext(pStreamShared);
1364 return true;
1365 }
1366
1367 Log3(("%s: [SD%RU8] Incomplete BDLE%u %#RX64 LB %#RX32 fFlags=%#x: off=%#RX32\n", pszFunction, pStreamShared->u8SD,
1368 pStreamShared->State.idxCurBdle, pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].GCPhys,
1369 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].cb,
1370 pStreamShared->State.aBdl[pStreamShared->State.idxCurBdle].fFlags, pStreamShared->State.offCurBdle));
1371 return false;
1372}
1373#endif /* IN_RING3 || VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
1374
1375
1376#ifdef IN_RING3
1377
1378/**
1379 * Does DMA transfer for an HDA input stream.
1380 *
1381 * Reads audio data from the HDA stream's internal DMA buffer and writing to
1382 * guest memory.
1383 *
1384 * @param pDevIns The device instance.
1385 * @param pThis The shared HDA device state.
1386 * @param pStreamShared HDA stream to update (shared).
1387 * @param pStreamR3 HDA stream to update (ring-3).
1388 * @param cbToConsume The max amount of data to consume from the
1389 * internal DMA buffer. The caller will make sure
1390 * this is always the transfer size fo the current
1391 * period (unless something is seriously wrong).
1392 * @param fWriteSilence Whether to feed the guest silence rather than
1393 * fetching bytes from the internal DMA buffer.
1394 * This is set initially while we pre-buffer a
1395 * little bit of input, so we can better handle
1396 * time catch-ups and other schduling fun.
1397 * @param tsNowNs The current RTTimeNano() value.
1398 *
1399 * @remarks Caller owns the stream lock.
1400 */
1401static void hdaR3StreamDoDmaInput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
1402 PHDASTREAMR3 pStreamR3, uint32_t const cbToConsume, bool fWriteSilence, uint64_t tsNowNs)
1403{
1404 uint8_t const uSD = pStreamShared->u8SD;
1405 LogFlowFunc(("ENTER - #%u cbToConsume=%#x%s\n", uSD, cbToConsume, fWriteSilence ? " silence" : ""));
1406
1407 /*
1408 * Common prologue.
1409 */
1410 if (hdaR3StreamDoDmaPrologue(pThis, pStreamShared, pStreamR3, uSD, tsNowNs, "hdaR3StreamDoDmaInput"))
1411 { /* likely */ }
1412 else
1413 return;
1414
1415 /*
1416 *
1417 * The DMA copy loop.
1418 *
1419 * Note! Unaligned BDLEs shouldn't be a problem since the circular buffer
1420 * doesn't care about alignment. Only, we have to read the rest
1421 * of the incomplete frame from it ASAP.
1422 */
1423 PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1424 uint32_t cbLeft = cbToConsume;
1425 Assert(cbLeft == pStreamShared->State.cbCurDmaPeriod);
1426 Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1427
1428 while (cbLeft > 0)
1429 {
1430 STAM_PROFILE_START(&pThis->StatIn, a);
1431
1432 /*
1433 * Figure out how much we can read & write in this iteration.
1434 */
1435 uint32_t cbChunk = 0;
1436 RTGCPHYS GCPhys = hdaStreamDmaBufGet(pStreamShared, &cbChunk);
1437
1438 if (cbChunk <= cbLeft)
1439 { /* very likely */ }
1440 else
1441 cbChunk = cbLeft;
1442
1443 uint32_t cbWritten = 0;
1444 if (!fWriteSilence)
1445 {
1446 /*
1447 * Write the host data directly into the guest buffers.
1448 */
1449 while (cbChunk > 0)
1450 {
1451 /* Grab internal DMA buffer space and read into it. */
1452 void /*const*/ *pvBufSrc;
1453 size_t cbBufSrc;
1454 RTCircBufAcquireReadBlock(pCircBuf, cbChunk, &pvBufSrc, &cbBufSrc);
1455 AssertBreakStmt(cbBufSrc, RTCircBufReleaseReadBlock(pCircBuf, 0));
1456
1457 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, GCPhys, pvBufSrc, cbBufSrc);
1458 AssertRC(rc2);
1459
1460# ifdef HDA_DEBUG_SILENCE
1461 fix me if relevant;
1462# endif
1463 if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1464 { /* likely */ }
1465 else
1466 AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufSrc, cbBufSrc, 0 /* fFlags */);
1467
1468# ifdef VBOX_WITH_DTRACE
1469 VBOXDD_HDA_STREAM_DMA_IN((uint32_t)uSD, (uint32_t)cbBufSrc, pStreamShared->State.offRead);
1470# endif
1471 pStreamShared->State.offRead += cbBufSrc;
1472 RTCircBufReleaseReadBlock(pCircBuf, cbBufSrc);
1473 STAM_COUNTER_ADD(&pThis->StatBytesWritten, cbBufSrc);
1474
1475 /* advance */
1476 cbChunk -= (uint32_t)cbBufSrc;
1477 cbWritten += (uint32_t)cbBufSrc;
1478 GCPhys += cbBufSrc;
1479 pStreamShared->State.offCurBdle += (uint32_t)cbBufSrc;
1480 }
1481 }
1482 /*
1483 * Write silence. Since we only do signed formats, we can use the zero
1484 * buffers from IPRT as source here.
1485 */
1486 else
1487 {
1488 Assert(PDMAudioPropsIsSigned(&pStreamShared->State.Cfg.Props));
1489 while (cbChunk > 0)
1490 {
1491 /* Write it to the guest buffer. */
1492 uint32_t cbToWrite = RT_MIN(sizeof(g_abRTZero64K), cbChunk);
1493 int rc2 = PDMDevHlpPCIPhysWrite(pDevIns, GCPhys, g_abRTZero64K, cbToWrite);
1494 AssertRC(rc2);
1495 STAM_COUNTER_ADD(&pThis->StatBytesWritten, cbToWrite);
1496
1497 /* advance */
1498 cbWritten += cbToWrite;
1499 cbChunk -= cbToWrite;
1500 GCPhys += cbToWrite;
1501 pStreamShared->State.offCurBdle += cbToWrite;
1502 }
1503 }
1504
1505 cbLeft -= cbWritten;
1506 STAM_PROFILE_STOP(&pThis->StatIn, a);
1507
1508 /*
1509 * Complete the buffer if necessary (common with the output DMA code).
1510 *
1511 * Must update the DMA position before we do this as the buffer IRQ may
1512 * fire on another vCPU and run in parallel to us, although it is very
1513 * unlikely it can make much progress as long as we're sitting on the
1514 * lock, it could still read the DMA position (Linux won't, as it reads
1515 * WALCLK and possibly SDnSTS before the DMA position).
1516 */
1517 hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, cbWritten);
1518 hdaStreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaR3StreamDoDmaInput");
1519 }
1520
1521 Assert(cbLeft == 0); /* There shall be no break statements in the above loop, so cbLeft is always zero here! */
1522
1523 /*
1524 * Common epilogue.
1525 */
1526 hdaR3StreamDoDmaEpilogue(pDevIns, pStreamShared, pStreamR3);
1527
1528 /*
1529 * Log and leave.
1530 */
1531 Log3Func(("LEAVE - [SD%RU8] %#RX32/%#RX32 @ %#RX64 - cTransferPendingInterrupts=%RU8\n",
1532 uSD, cbToConsume, pStreamShared->State.cbCurDmaPeriod, pStreamShared->State.offRead - cbToConsume,
1533 pStreamShared->State.cTransferPendingInterrupts));
1534}
1535
1536
1537/**
1538 * Input streams: Pulls data from the mixer, putting it in the internal DMA
1539 * buffer.
1540 *
1541 * @param pStreamShared HDA stream to update (shared).
1542 * @param pStreamR3 HDA stream to update (ring-3 bits).
1543 * @param pSink The mixer sink to pull from.
1544 */
1545static void hdaR3StreamPullFromMixer(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink)
1546{
1547# ifdef LOG_ENABLED
1548 uint64_t const offWriteOld = pStreamShared->State.offWrite;
1549# endif
1550 pStreamShared->State.offWrite = AudioMixerSinkTransferToCircBuf(pSink,
1551 pStreamR3->State.pCircBuf,
1552 pStreamShared->State.offWrite,
1553 pStreamR3->u8SD,
1554 pStreamR3->Dbg.Runtime.fEnabled
1555 ? pStreamR3->Dbg.Runtime.pFileStream : NULL);
1556
1557 Log3Func(("[SD%RU8] transferred=%#RX64 bytes -> @%#RX64\n", pStreamR3->u8SD,
1558 pStreamShared->State.offWrite - offWriteOld, pStreamShared->State.offWrite));
1559
1560 /* Update buffer stats. */
1561 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1562}
1563
1564
1565/**
1566 * Does DMA transfer for an HDA output stream.
1567 *
1568 * This transfers one DMA timer period worth of data from the guest and into the
1569 * internal DMA buffer.
1570 *
1571 * @param pDevIns The device instance.
1572 * @param pThis The shared HDA device state.
1573 * @param pStreamShared HDA stream to update (shared).
1574 * @param pStreamR3 HDA stream to update (ring-3).
1575 * @param cbToProduce The max amount of data to produce (i.e. put into
1576 * the circular buffer). Unless something is going
1577 * seriously wrong, this will always be transfer
1578 * size for the current period.
1579 * @param tsNowNs The current RTTimeNano() value.
1580 *
1581 * @remarks Caller owns the stream lock.
1582 */
1583static void hdaR3StreamDoDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
1584 PHDASTREAMR3 pStreamR3, uint32_t const cbToProduce, uint64_t tsNowNs)
1585{
1586 uint8_t const uSD = pStreamShared->u8SD;
1587 LogFlowFunc(("ENTER - #%u cbToProduce=%#x\n", uSD, cbToProduce));
1588
1589 /*
1590 * Common prologue.
1591 */
1592 if (hdaR3StreamDoDmaPrologue(pThis, pStreamShared, pStreamR3, uSD, tsNowNs, "hdaR3StreamDoDmaOutput"))
1593 { /* likely */ }
1594 else
1595 return;
1596
1597 /*
1598 *
1599 * The DMA copy loop.
1600 *
1601 * Note! Unaligned BDLEs shouldn't be a problem since the circular buffer
1602 * doesn't care about alignment. Only, we have to write the rest
1603 * of the incomplete frame to it ASAP.
1604 */
1605 PRTCIRCBUF pCircBuf = pStreamR3->State.pCircBuf;
1606 uint32_t cbLeft = cbToProduce;
1607# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
1608 Assert(cbLeft <= pStreamShared->State.cbCurDmaPeriod); /* a little pointless with the DMA'ing on LPIB read. */
1609# else
1610 Assert(cbLeft == pStreamShared->State.cbCurDmaPeriod);
1611# endif
1612 Assert(PDMAudioPropsIsSizeAligned(&pStreamShared->State.Cfg.Props, cbLeft));
1613
1614 while (cbLeft > 0)
1615 {
1616 STAM_PROFILE_START(&pThis->StatOut, a);
1617
1618 /*
1619 * Figure out how much we can read & write in this iteration.
1620 */
1621 uint32_t cbChunk = 0;
1622 RTGCPHYS GCPhys = hdaStreamDmaBufGet(pStreamShared, &cbChunk);
1623
1624 if (cbChunk <= cbLeft)
1625 { /* very likely */ }
1626 else
1627 cbChunk = cbLeft;
1628
1629 /*
1630 * Read the guest data directly into the internal DMA buffer.
1631 */
1632 uint32_t cbRead = 0;
1633 while (cbChunk > 0)
1634 {
1635 /* Grab internal DMA buffer space and read into it. */
1636 void *pvBufDst;
1637 size_t cbBufDst;
1638 RTCircBufAcquireWriteBlock(pCircBuf, cbChunk, &pvBufDst, &cbBufDst);
1639 AssertBreakStmt(cbBufDst, RTCircBufReleaseWriteBlock(pCircBuf, 0));
1640
1641 int rc2 = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, pvBufDst, cbBufDst);
1642 AssertRC(rc2);
1643
1644# ifdef HDA_DEBUG_SILENCE
1645 fix me if relevant;
1646# endif
1647 if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
1648 { /* likely */ }
1649 else
1650 AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst, 0 /* fFlags */);
1651
1652# ifdef VBOX_WITH_DTRACE
1653 VBOXDD_HDA_STREAM_DMA_OUT((uint32_t)uSD, (uint32_t)cbBufDst, pStreamShared->State.offWrite);
1654# endif
1655 pStreamShared->State.offWrite += cbBufDst;
1656 RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
1657 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbBufDst);
1658
1659 /* advance */
1660 cbChunk -= (uint32_t)cbBufDst;
1661 cbRead += (uint32_t)cbBufDst;
1662 GCPhys += cbBufDst;
1663 pStreamShared->State.offCurBdle += (uint32_t)cbBufDst;
1664 }
1665
1666 cbLeft -= cbRead;
1667 STAM_PROFILE_STOP(&pThis->StatOut, a);
1668
1669 /*
1670 * Complete the buffer if necessary (common with the input DMA code).
1671 *
1672 * Must update the DMA position before we do this as the buffer IRQ may
1673 * fire on another vCPU and run in parallel to us, although it is very
1674 * unlikely it can make much progress as long as we're sitting on the
1675 * lock, it could still read the DMA position (Linux won't, as it reads
1676 * WALCLK and possibly SDnSTS before the DMA position).
1677 */
1678 hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, cbRead);
1679 hdaStreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaR3StreamDoDmaOutput");
1680 }
1681
1682 Assert(cbLeft == 0); /* There shall be no break statements in the above loop, so cbLeft is always zero here! */
1683
1684 /*
1685 * Common epilogue.
1686 */
1687 hdaR3StreamDoDmaEpilogue(pDevIns, pStreamShared, pStreamR3);
1688
1689 /*
1690 * Log and leave.
1691 */
1692 Log3Func(("LEAVE - [SD%RU8] %#RX32/%#RX32 @ %#RX64 - cTransferPendingInterrupts=%RU8\n",
1693 uSD, cbToProduce, pStreamShared->State.cbCurDmaPeriod, pStreamShared->State.offWrite - cbToProduce,
1694 pStreamShared->State.cTransferPendingInterrupts));
1695}
1696
1697#endif /* IN_RING3 */
1698#ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
1699
1700/**
1701 * Do DMA output transfer on LPIB/WALCLK register access.
1702 *
1703 * @returns VINF_SUCCESS or VINF_IOM_R3_MMIO_READ.
1704 * @param pDevIns The device instance.
1705 * @param pThis The shared instance data.
1706 * @param pStreamShared The shared stream data.
1707 * @param tsNow The current time on the timer clock.
1708 * @param cbToTransfer How much to transfer.
1709 */
1710VBOXSTRICTRC hdaStreamDoOnAccessDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
1711 uint64_t tsNow, uint32_t cbToTransfer)
1712{
1713 AssertReturn(cbToTransfer > 0, VINF_SUCCESS);
1714 int rc = VINF_SUCCESS;
1715
1716 /*
1717 * Check if we're exceeding the available buffer, go to ring-3 to
1718 * handle that (we would perhaps always take this path when in ring-3).
1719 */
1720 uint32_t cbDma = pStreamShared->State.cbDma;
1721 ASMCompilerBarrier();
1722 if ( cbDma >= sizeof(pStreamShared->State.abDma) /* paranoia */
1723 || cbToTransfer >= sizeof(pStreamShared->State.abDma) /* paranoia */
1724 || cbDma + cbToTransfer > sizeof(pStreamShared->State.abDma))
1725 {
1726# ifndef IN_RING3
1727 STAM_REL_COUNTER_INC(&pThis->StatAccessDmaOutputToR3);
1728 LogFlowFunc(("[SD%RU8] out of DMA buffer space (%#x, need %#x) -> VINF_IOM_R3_MMIO_READ\n",
1729 pStreamShared->u8SD, sizeof(pStreamShared->State.abDma) - pStreamShared->State.cbDma, cbToTransfer));
1730 return VINF_IOM_R3_MMIO_READ;
1731# else /* IN_RING3 */
1732 /*
1733 * Flush the bounce buffer, then do direct transfers to the
1734 * internal DMA buffer (updates LPIB).
1735 */
1736 PHDASTATER3 const pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
1737 uintptr_t const idxStream = pStreamShared->u8SD;
1738 AssertReturn(idxStream < RT_ELEMENTS(pThisCC->aStreams), VERR_INTERNAL_ERROR_4);
1739 PHDASTREAMR3 const pStreamR3 = &pThisCC->aStreams[idxStream];
1740
1741 hdaR3StreamFlushDmaBounceBufferOutput(pStreamShared, pStreamR3);
1742
1743 uint32_t cbStreamFree = hdaR3StreamGetFree(pStreamR3);
1744 if (cbStreamFree >= cbToTransfer)
1745 { /* likely */ }
1746 else
1747 {
1748 PAUDMIXSINK pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
1749 if (pSink)
1750 cbStreamFree = hdaR3StreamHandleDmaBufferOverrun(pStreamShared, pStreamR3, pSink, cbToTransfer, RTTimeNanoTS(),
1751 "hdaStreamDoOnAccessDmaOutput", cbStreamFree);
1752 else
1753 {
1754 LogFunc(("[SD%RU8] No sink and insufficient internal DMA buffer space (%#x) - won't do anything\n",
1755 pStreamShared->u8SD, cbStreamFree));
1756 return VINF_SUCCESS;
1757 }
1758 cbToTransfer = RT_MIN(cbToTransfer, cbStreamFree);
1759 if (cbToTransfer < PDMAudioPropsFrameSize(&pStreamShared->State.Cfg.Props))
1760 {
1761 LogFunc(("[SD%RU8] No internal DMA buffer space (%#x) - won't do anything\n", pStreamShared->u8SD, cbStreamFree));
1762 return VINF_SUCCESS;
1763 }
1764 }
1765 hdaR3StreamDoDmaOutput(pDevIns, pThis, pStreamShared, pStreamR3, cbToTransfer, RTTimeNanoTS());
1766 pStreamShared->State.cbDmaTotal += cbToTransfer;
1767# endif /* IN_RING3 */
1768 }
1769 else
1770 {
1771 /*
1772 * Transfer into the DMA bounce buffer.
1773 */
1774 LogFlowFunc(("[SD%RU8] Transfering %#x bytes to DMA bounce buffer (cbDma=%#x cbDmaTotal=%#x) (%p/%u)\n",
1775 pStreamShared->u8SD, cbToTransfer, cbDma, pStreamShared->State.cbDmaTotal, pStreamShared, pStreamShared->u8SD));
1776 uint32_t cbLeft = cbToTransfer;
1777 do
1778 {
1779 uint32_t cbChunk = 0;
1780 RTGCPHYS GCPhys = hdaStreamDmaBufGet(pStreamShared, &cbChunk);
1781
1782 bool fMustAdvanceBuffer;
1783 if (cbLeft < cbChunk)
1784 {
1785 fMustAdvanceBuffer = false;
1786 cbChunk = cbLeft;
1787 }
1788 else
1789 fMustAdvanceBuffer = true;
1790
1791 /* Read the guest data directly into the DMA bounce buffer. */
1792 int rc2 = PDMDevHlpPCIPhysRead(pDevIns, GCPhys, &pStreamShared->State.abDma[cbDma], cbChunk);
1793 AssertRC(rc2);
1794
1795 /* We update offWrite and StatBytesRead here even if we haven't moved the data
1796 to the internal DMA buffer yet, because we want the dtrace even to fire here. */
1797# ifdef VBOX_WITH_DTRACE
1798 VBOXDD_HDA_STREAM_DMA_OUT((uint32_t)pStreamShared->u8SD, cbChunk, pStreamShared->State.offWrite);
1799# endif
1800 pStreamShared->State.offWrite += cbChunk;
1801 STAM_COUNTER_ADD(&pThis->StatBytesRead, cbChunk);
1802
1803 /* advance */
1804 pStreamShared->State.offCurBdle += cbChunk;
1805 pStreamShared->State.cbDmaTotal += cbChunk;
1806 cbDma += cbChunk;
1807 pStreamShared->State.cbDma = cbDma;
1808 cbLeft -= cbChunk;
1809 Log6Func(("cbLeft=%#x cbDma=%#x cbDmaTotal=%#x offCurBdle=%#x idxCurBdle=%#x (%p/%u)\n",
1810 cbLeft, cbDma, pStreamShared->State.cbDmaTotal, pStreamShared->State.offCurBdle,
1811 pStreamShared->State.idxCurBdle, pStreamShared, pStreamShared->u8SD));
1812
1813 /* Next buffer. */
1814 bool fAdvanced = hdaStreamDoDmaMaybeCompleteBuffer(pDevIns, pThis, pStreamShared, "hdaStreamDoOnAccessDmaOutput");
1815 AssertMsgStmt(fMustAdvanceBuffer == fAdvanced, ("%d %d\n", fMustAdvanceBuffer, fAdvanced), rc = VERR_INTERNAL_ERROR_3);
1816 } while (cbLeft > 0);
1817
1818 /*
1819 * Advance LPIB and update the last transfer time (for WALCLK).
1820 */
1821 pStreamShared->State.tsTransferLast = tsNow;
1822 hdaStreamSetPositionAdd(pStreamShared, pDevIns, pThis, cbToTransfer - cbLeft);
1823 }
1824
1825# ifdef VBOX_STRICT
1826 uint32_t idxSched = pStreamShared->State.idxSchedule;
1827 AssertStmt(idxSched < RT_MIN(RT_ELEMENTS(pStreamShared->State.aSchedule), pStreamShared->State.cSchedule), idxSched = 0);
1828 uint32_t const cbPeriod = pStreamShared->State.aSchedule[idxSched].cbPeriod;
1829 AssertMsg(pStreamShared->State.cbDmaTotal < cbPeriod, ("%#x vs %#x\n", pStreamShared->State.cbDmaTotal, cbPeriod));
1830# endif
1831
1832 STAM_REL_COUNTER_INC(&pThis->StatAccessDmaOutput);
1833 return rc;
1834}
1835
1836
1837/**
1838 * Consider doing DMA output transfer on LPIB/WALCLK register access.
1839 *
1840 * @returns VINF_SUCCESS or VINF_IOM_R3_MMIO_READ.
1841 * @param pDevIns The device instance.
1842 * @param pThis The shared instance data.
1843 * @param pStreamShared The shared stream data.
1844 * @param tsNow The current time on the timer clock. Used to do the
1845 * calculation.
1846 */
1847VBOXSTRICTRC hdaStreamMaybeDoOnAccessDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint64_t tsNow)
1848{
1849 Assert(pStreamShared->State.fRunning); /* caller should check this */
1850
1851 /*
1852 * Calculate where the DMA engine should be according to the clock, if we can.
1853 */
1854 uint32_t const cbFrame = PDMAudioPropsFrameSize(&pStreamShared->State.Cfg.Props);
1855 uint32_t const cbPeriod = pStreamShared->State.cbCurDmaPeriod;
1856 if (cbPeriod > cbFrame)
1857 {
1858 AssertMsg(pStreamShared->State.cbDmaTotal < cbPeriod, ("%#x vs %#x\n", pStreamShared->State.cbDmaTotal, cbPeriod));
1859 uint64_t const tsTransferNext = pStreamShared->State.tsTransferNext;
1860 uint32_t cbFuture;
1861 if (tsNow < tsTransferNext)
1862 {
1863 /** @todo ASSUMES nanosecond clock ticks, need to make this
1864 * resolution independent. */
1865 cbFuture = PDMAudioPropsNanoToBytes(&pStreamShared->State.Cfg.Props, tsTransferNext - tsNow);
1866 cbFuture = RT_MIN(cbFuture, cbPeriod - cbFrame);
1867 }
1868 else
1869 {
1870 /* We've hit/overshot the timer deadline. Return to ring-3 if we're
1871 not already there to increase the chance that we'll help expidite
1872 the timer. If we're already in ring-3, do all but the last frame. */
1873# ifndef IN_RING3
1874 LogFunc(("[SD%RU8] DMA period expired: tsNow=%RU64 >= tsTransferNext=%RU64 -> VINF_IOM_R3_MMIO_READ\n",
1875 tsNow, tsTransferNext));
1876 return VINF_IOM_R3_MMIO_READ;
1877# else
1878 cbFuture = cbPeriod - cbFrame;
1879 LogFunc(("[SD%RU8] DMA period expired: tsNow=%RU64 >= tsTransferNext=%RU64 -> cbFuture=%#x (cbPeriod=%#x - cbFrame=%#x)\n",
1880 tsNow, tsTransferNext, cbFuture, cbPeriod, cbFrame));
1881# endif
1882 }
1883 uint32_t const offNow = PDMAudioPropsFloorBytesToFrame(&pStreamShared->State.Cfg.Props, cbPeriod - cbFuture);
1884
1885 /*
1886 * Should we transfer a little? Minimum is 64 bytes (semi-random,
1887 * suspect real hardware might be doing some cache aligned stuff,
1888 * which might soon get complicated if you take unaligned buffers
1889 * into consideration and which cache line size (128 bytes is just
1890 * as likely as 64 or 32 bytes)).
1891 */
1892 uint32_t cbDmaTotal = pStreamShared->State.cbDmaTotal;
1893 if (cbDmaTotal + 64 <= offNow)
1894 {
1895# ifdef LOG_ENABLED
1896 uint32_t const uOldLpib = HDA_STREAM_REG(pThis, CBL, pStreamShared->u8SD);
1897# endif
1898 VBOXSTRICTRC rcStrict = hdaStreamDoOnAccessDmaOutput(pDevIns, pThis, pStreamShared, tsNow, offNow - cbDmaTotal);
1899 LogFlowFunc(("[SD%RU8] LPIB=%#RX32 -> LPIB=%#RX32 offNow=%#x rcStrict=%Rrc\n", pStreamShared->u8SD,
1900 uOldLpib, HDA_STREAM_REG(pThis, LPIB, pStreamShared->u8SD), offNow, VBOXSTRICTRC_VAL(rcStrict) ));
1901 return rcStrict;
1902 }
1903
1904 /*
1905 * Do nothing.
1906 */
1907 LogFlowFunc(("[SD%RU8] Skipping DMA transfer: cbDmaTotal=%#x offNow=%#x\n", pStreamShared->u8SD, cbDmaTotal, offNow));
1908 }
1909 else
1910 LogFunc(("[SD%RU8] cbPeriod=%#x <= cbFrame=%#x\n", pStreamShared->u8SD, cbPeriod, cbFrame));
1911 return VINF_SUCCESS;
1912}
1913
1914#endif /* VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
1915#ifdef IN_RING3
1916
1917/**
1918 * Output streams: Pushes data to the mixer.
1919 *
1920 * @param pStreamShared HDA stream to update (shared bits).
1921 * @param pStreamR3 HDA stream to update (ring-3 bits).
1922 * @param pSink The mixer sink to push to.
1923 * @param nsNow The current RTTimeNanoTS() value.
1924 */
1925static void hdaR3StreamPushToMixer(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink, uint64_t nsNow)
1926{
1927# ifdef LOG_ENABLED
1928 uint64_t const offReadOld = pStreamShared->State.offRead;
1929# endif
1930 pStreamShared->State.offRead = AudioMixerSinkTransferFromCircBuf(pSink,
1931 pStreamR3->State.pCircBuf,
1932 pStreamShared->State.offRead,
1933 pStreamR3->u8SD,
1934 pStreamR3->Dbg.Runtime.fEnabled
1935 ? pStreamR3->Dbg.Runtime.pFileStream : NULL);
1936
1937 Assert(nsNow >= pStreamShared->State.tsLastReadNs);
1938 Log3Func(("[SD%RU8] nsDeltaLastRead=%RI64 transferred=%#RX64 bytes -> @%#RX64\n", pStreamR3->u8SD,
1939 nsNow - pStreamShared->State.tsLastReadNs, pStreamShared->State.offRead - offReadOld, pStreamShared->State.offRead));
1940 RT_NOREF(pStreamShared, nsNow);
1941
1942 /* Update buffer stats. */
1943 pStreamR3->State.StatDmaBufUsed = (uint32_t)RTCircBufUsed(pStreamR3->State.pCircBuf);
1944}
1945
1946
1947/**
1948 * Deals with a DMA buffer overrun.
1949 *
1950 * Makes sure we return with @a cbNeeded bytes of free space in pCircBuf.
1951 *
1952 * @returns Number of bytes free in the internal DMA buffer.
1953 * @param pStreamShared The shared data for the HDA stream.
1954 * @param pStreamR3 The ring-3 data for the HDA stream.
1955 * @param pSink The mixer sink (valid).
1956 * @param cbNeeded How much space we need (in bytes).
1957 * @param nsNow Current RTNanoTimeTS() timestamp.
1958 * @param cbStreamFree The current amount of free buffer space.
1959 * @param pszCaller The caller (for logging).
1960 */
1961static uint32_t hdaR3StreamHandleDmaBufferOverrun(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PAUDMIXSINK pSink,
1962 uint32_t cbNeeded, uint64_t nsNow,
1963 const char *pszCaller, uint32_t const cbStreamFree)
1964{
1965 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowProblems);
1966 Log(("%s: Warning! Stream #%u has insufficient space free: %#x bytes, need %#x. Will try move data out of the buffer...\n",
1967 pszCaller, pStreamShared->u8SD, cbStreamFree, cbNeeded));
1968 RT_NOREF(pszCaller, cbStreamFree);
1969
1970 int rc = AudioMixerSinkTryLock(pSink);
1971 if (RT_SUCCESS(rc))
1972 {
1973 hdaR3StreamPushToMixer(pStreamShared, pStreamR3, pSink, nsNow);
1974 AudioMixerSinkUpdate(pSink, 0, 0);
1975 AudioMixerSinkUnlock(pSink);
1976 }
1977 else
1978 RTThreadYield();
1979
1980 uint32_t const cbRet = hdaR3StreamGetFree(pStreamR3);
1981 Log(("%s: Gained %u bytes.\n", pszCaller, cbRet - cbStreamFree));
1982 if (cbRet >= cbNeeded)
1983 return cbRet;
1984
1985 /*
1986 * Unable to make sufficient space. Drop the whole buffer content.
1987 *
1988 * This is needed in order to keep the device emulation running at a
1989 * constant rate, at the cost of losing valid (but too much) data.
1990 */
1991 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowErrors);
1992 LogRel2(("HDA: Warning: Hit stream #%RU8 overflow, dropping %u bytes of audio data (%s)\n",
1993 pStreamShared->u8SD, hdaR3StreamGetUsed(pStreamR3), pszCaller));
1994# ifdef HDA_STRICT
1995 AssertMsgFailed(("Hit stream #%RU8 overflow -- timing bug?\n", pStreamShared->u8SD));
1996# endif
1997/**
1998 *
1999 * @todo r=bird: I don't think RTCircBufReset is entirely safe w/o
2000 * owning the AIO lock. See the note in the documentation about it not being
2001 * multi-threading aware (safe). Wish I'd verified this code much earlier.
2002 * Sigh^3!
2003 *
2004 */
2005 RTCircBufReset(pStreamR3->State.pCircBuf);
2006 pStreamShared->State.offWrite = 0;
2007 pStreamShared->State.offRead = 0;
2008 return hdaR3StreamGetFree(pStreamR3);
2009}
2010
2011
2012# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
2013/**
2014 * Flushes the DMA bounce buffer content to the internal DMA buffer.
2015 *
2016 * @param pStreamShared The shared data of the stream to have its DMA bounce
2017 * buffer flushed.
2018 * @param pStreamR3 The ring-3 stream data for same.
2019 */
2020static void hdaR3StreamFlushDmaBounceBufferOutput(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
2021{
2022 uint32_t cbDma = pStreamShared->State.cbDma;
2023 LogFlowFunc(("cbDma=%#x\n", cbDma));
2024 if (cbDma)
2025 {
2026 AssertReturnVoid(cbDma <= sizeof(pStreamShared->State.abDma));
2027 PRTCIRCBUF const pCircBuf = pStreamR3->State.pCircBuf;
2028 if (pCircBuf)
2029 {
2030 uint32_t offDma = 0;
2031 while (offDma < cbDma)
2032 {
2033 uint32_t const cbSrcLeft = cbDma - offDma;
2034
2035 /*
2036 * Grab a chunk of the internal DMA buffer.
2037 */
2038 void *pvBufDst = NULL;
2039 size_t cbBufDst = 0;
2040 RTCircBufAcquireWriteBlock(pCircBuf, cbSrcLeft, &pvBufDst, &cbBufDst);
2041 if (cbBufDst > 0)
2042 { /* likely */ }
2043 else
2044 {
2045 /* We've got buffering trouble. */
2046 RTCircBufReleaseWriteBlock(pCircBuf, 0);
2047
2048 PAUDMIXSINK pSink = pStreamR3->pMixSink ? pStreamR3->pMixSink->pMixSink : NULL;
2049 if (pSink)
2050 hdaR3StreamHandleDmaBufferOverrun(pStreamShared, pStreamR3, pSink, cbSrcLeft, RTTimeNanoTS(),
2051 "hdaR3StreamFlushDmaBounceBufferOutput", 0 /*cbStreamFree*/);
2052 else
2053 {
2054 LogFunc(("Stream #%u has no sink. Dropping the rest of the data\n", pStreamR3->u8SD));
2055 break;
2056 }
2057
2058 RTCircBufAcquireWriteBlock(pCircBuf, cbSrcLeft, &pvBufDst, &cbBufDst);
2059 AssertBreakStmt(cbBufDst, RTCircBufReleaseWriteBlock(pCircBuf, 0));
2060 }
2061
2062 /*
2063 * Copy the samples into it and write it to the debug file if open.
2064 *
2065 * We do not fire the dtrace probe here nor update offRead as that was
2066 * done already (not sure that was a good idea?).
2067 */
2068 memcpy(pvBufDst, &pStreamShared->State.abDma[offDma], cbBufDst);
2069
2070 if (RT_LIKELY(!pStreamR3->Dbg.Runtime.fEnabled))
2071 { /* likely */ }
2072 else
2073 AudioHlpFileWrite(pStreamR3->Dbg.Runtime.pFileDMARaw, pvBufDst, cbBufDst, 0 /* fFlags */);
2074
2075 RTCircBufReleaseWriteBlock(pCircBuf, cbBufDst);
2076
2077 offDma += (uint32_t)cbBufDst;
2078 }
2079 }
2080
2081 /*
2082 * Mark the buffer empty.
2083 */
2084 pStreamShared->State.cbDma = 0;
2085 }
2086}
2087# endif /* VBOX_HDA_WITH_ON_REG_ACCESS_DMA */
2088
2089
2090/**
2091 * The stream's main function when called by the timer.
2092 *
2093 * @note This function also will be called without timer invocation when
2094 * starting (enabling) the stream to minimize startup latency.
2095 *
2096 * @returns Current timer time if the timer is enabled, otherwise zero.
2097 * @param pDevIns The device instance.
2098 * @param pThis The shared HDA device state.
2099 * @param pThisCC The ring-3 HDA device state.
2100 * @param pStreamShared HDA stream to update (shared bits).
2101 * @param pStreamR3 HDA stream to update (ring-3 bits).
2102 */
2103uint64_t hdaR3StreamTimerMain(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
2104 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
2105{
2106 Assert(PDMDevHlpCritSectIsOwner(pDevIns, &pThis->CritSect));
2107 Assert(PDMDevHlpTimerIsLockOwner(pDevIns, pStreamShared->hTimer));
2108
2109 /* Do the work: */
2110 hdaR3StreamUpdateDma(pDevIns, pThis, pThisCC, pStreamShared, pStreamR3);
2111
2112 /* Re-arm the timer if the sink is still active: */
2113 if ( pStreamShared->State.fRunning
2114 && pStreamR3->pMixSink
2115 && AudioMixerSinkIsActive(pStreamR3->pMixSink->pMixSink))
2116 {
2117 /* Advance the schduling: */
2118 uint32_t idxSched = pStreamShared->State.idxSchedule;
2119 AssertStmt(idxSched < RT_ELEMENTS(pStreamShared->State.aSchedule), idxSched = 0);
2120 uint32_t idxLoop = pStreamShared->State.idxScheduleLoop + 1;
2121 if (idxLoop >= pStreamShared->State.aSchedule[idxSched].cLoops)
2122 {
2123 idxSched += 1;
2124 if ( idxSched >= pStreamShared->State.cSchedule
2125 || idxSched >= RT_ELEMENTS(pStreamShared->State.aSchedule) /*paranoia^2*/)
2126 {
2127 idxSched = pStreamShared->State.cSchedulePrologue;
2128 AssertStmt(idxSched < RT_ELEMENTS(pStreamShared->State.aSchedule), idxSched = 0);
2129 }
2130 pStreamShared->State.idxSchedule = idxSched;
2131 idxLoop = 0;
2132 }
2133 pStreamShared->State.idxScheduleLoop = (uint16_t)idxLoop;
2134
2135 /* Do the actual timer re-arming. */
2136 uint64_t const tsNow = PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer); /* (For virtual sync this remains the same for the whole callout IIRC) */
2137 uint64_t const tsTransferNext = tsNow + pStreamShared->State.aSchedule[idxSched].cPeriodTicks;
2138 Log3Func(("[SD%RU8] fSinkActive=true, tsTransferNext=%RU64 (in %RU64)\n",
2139 pStreamShared->u8SD, tsTransferNext, tsTransferNext - tsNow));
2140 int rc = PDMDevHlpTimerSet(pDevIns, pStreamShared->hTimer, tsTransferNext);
2141 AssertRC(rc);
2142
2143 /* Some legacy stuff: */
2144 pStreamShared->State.tsTransferNext = tsTransferNext;
2145 pStreamShared->State.cbCurDmaPeriod = pStreamShared->State.aSchedule[idxSched].cbPeriod;
2146
2147 return tsNow;
2148 }
2149
2150 Log3Func(("[SD%RU8] fSinkActive=false\n", pStreamShared->u8SD));
2151 return 0;
2152}
2153
2154
2155/**
2156 * Updates a HDA stream by doing DMA transfers.
2157 *
2158 * Will do mixer transfers too to try fix an overrun/underrun situation.
2159 *
2160 * The host sink(s) set the overall pace (bird: no it doesn't, the DMA timer
2161 * does - we just hope like heck it matches the speed at which the *backend*
2162 * host audio driver processes samples).
2163 *
2164 * @param pDevIns The device instance.
2165 * @param pThis The shared HDA device state.
2166 * @param pThisCC The ring-3 HDA device state.
2167 * @param pStreamShared HDA stream to update (shared bits).
2168 * @param pStreamR3 HDA stream to update (ring-3 bits).
2169 */
2170static void hdaR3StreamUpdateDma(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
2171 PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3)
2172{
2173 RT_NOREF(pThisCC);
2174 int rc2;
2175
2176 /*
2177 * Make sure we're running and got an active mixer sink.
2178 */
2179 if (RT_LIKELY(pStreamShared->State.fRunning))
2180 { /* likely */ }
2181 else
2182 return;
2183
2184 PAUDMIXSINK pSink = NULL;
2185 if (pStreamR3->pMixSink)
2186 pSink = pStreamR3->pMixSink->pMixSink;
2187 if (RT_LIKELY(AudioMixerSinkIsActive(pSink)))
2188 { /* likely */ }
2189 else
2190 return;
2191
2192 /*
2193 * Get scheduling info common to both input and output streams.
2194 */
2195 const uint64_t tsNowNs = RTTimeNanoTS();
2196 uint32_t idxSched = pStreamShared->State.idxSchedule;
2197 AssertStmt(idxSched < RT_MIN(RT_ELEMENTS(pStreamShared->State.aSchedule), pStreamShared->State.cSchedule), idxSched = 0);
2198 uint32_t cbPeriod = pStreamShared->State.aSchedule[idxSched].cbPeriod;
2199
2200 /*
2201 * Output streams (SDO).
2202 */
2203 if (hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_OUT)
2204 {
2205# ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
2206 /* Subtract already transferred bytes and flush the DMA bounce buffer. */
2207 uint32_t cbDmaTotal = pStreamShared->State.cbDmaTotal;
2208 if (cbDmaTotal > 0)
2209 {
2210 AssertStmt(cbDmaTotal < cbPeriod, cbDmaTotal = cbPeriod);
2211 cbPeriod -= cbDmaTotal;
2212 pStreamShared->State.cbDmaTotal = 0;
2213 hdaR3StreamFlushDmaBounceBufferOutput(pStreamShared, pStreamR3);
2214 }
2215 else
2216 Assert(pStreamShared->State.cbDma == 0);
2217# endif
2218
2219 /*
2220 * Check how much room we have in our DMA buffer. There should be at
2221 * least one period worth of space there or we're in an overflow situation.
2222 */
2223 uint32_t cbStreamFree = hdaR3StreamGetFree(pStreamR3);
2224 if (cbStreamFree >= cbPeriod)
2225 { /* likely */ }
2226 else
2227 cbStreamFree = hdaR3StreamHandleDmaBufferOverrun(pStreamShared, pStreamR3, pSink, cbPeriod, tsNowNs,
2228 "hdaR3StreamUpdateDma", cbStreamFree);
2229
2230 /*
2231 * Do the DMA transfer.
2232 */
2233 uint64_t const offWriteBefore = pStreamShared->State.offWrite;
2234 hdaR3StreamDoDmaOutput(pDevIns, pThis, pStreamShared, pStreamR3, RT_MIN(cbStreamFree, cbPeriod), tsNowNs);
2235
2236 /*
2237 * Should we push data to down thru the mixer to and to the host drivers?
2238 *
2239 * We initially delay this by pThis->msInitialDelay, but after than we'll
2240 * kick the AIO thread every time we've put more data in the buffer (which is
2241 * every time) as the host audio device needs to get data in a timely manner.
2242 *
2243 * (We used to try only wake up the AIO thread according to pThis->uIoTimer
2244 * and host wall clock, but that meant we would miss a wakup after the DMA
2245 * timer was called a little late or if TM entered into catch-up mode.)
2246 */
2247 bool fKickAioThread;
2248 if (!pStreamShared->State.tsAioDelayEnd)
2249 fKickAioThread = pStreamShared->State.offWrite > offWriteBefore
2250 || hdaR3StreamGetFree(pStreamR3) < pStreamShared->State.cbAvgTransfer * 2;
2251 else if (PDMDevHlpTimerGet(pDevIns, pStreamShared->hTimer) >= pStreamShared->State.tsAioDelayEnd)
2252 {
2253 Log3Func(("Initial delay done: Passed tsAioDelayEnd.\n"));
2254 pStreamShared->State.tsAioDelayEnd = 0;
2255 fKickAioThread = true;
2256 }
2257 else if (hdaR3StreamGetFree(pStreamR3) < pStreamShared->State.cbAvgTransfer * 2)
2258 {
2259 Log3Func(("Initial delay done: Passed running short on buffer.\n"));
2260 pStreamShared->State.tsAioDelayEnd = 0;
2261 fKickAioThread = true;
2262 }
2263 else
2264 {
2265 Log3Func(("Initial delay pending...\n"));
2266 fKickAioThread = false;
2267 }
2268
2269 Log3Func(("msDelta=%RU64 (vs %u) cbStreamFree=%#x (vs %#x) => fKickAioThread=%RTbool\n",
2270 (tsNowNs - pStreamShared->State.tsLastReadNs) / RT_NS_1MS,
2271 pStreamShared->State.Cfg.Device.cMsSchedulingHint, cbStreamFree,
2272 pStreamShared->State.cbAvgTransfer * 2, fKickAioThread));
2273
2274 if (fKickAioThread)
2275 {
2276 /* Notify the async I/O worker thread that there's work to do. */
2277 Log5Func(("Notifying AIO thread\n"));
2278 rc2 = AudioMixerSinkSignalUpdateJob(pSink);
2279 AssertRC(rc2);
2280 /* Update last read timestamp for logging/debugging. */
2281 pStreamShared->State.tsLastReadNs = tsNowNs;
2282 }
2283 }
2284 /*
2285 * Input stream (SDI).
2286 */
2287 else
2288 {
2289 Assert(hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_IN);
2290
2291 /*
2292 * See how much data we've got buffered...
2293 */
2294 bool fWriteSilence = false;
2295 uint32_t cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2296 if (pStreamShared->State.fInputPreBuffered && cbStreamUsed >= cbPeriod)
2297 { /*likely*/ }
2298 /*
2299 * Because it may take a while for the input stream to get going (at
2300 * least with pulseaudio), we feed the guest silence till we've
2301 * pre-buffer a reasonable amount of audio.
2302 */
2303 else if (!pStreamShared->State.fInputPreBuffered)
2304 {
2305 if (cbStreamUsed < pStreamShared->State.cbInputPreBuffer)
2306 {
2307 Log3(("hdaR3StreamUpdateDma: Pre-buffering (got %#x out of %#x bytes)...\n",
2308 cbStreamUsed, pStreamShared->State.cbInputPreBuffer));
2309 fWriteSilence = true;
2310 }
2311 else
2312 {
2313 Log3(("hdaR3StreamUpdateDma: Completed pre-buffering (got %#x, needed %#x bytes).\n",
2314 cbStreamUsed, pStreamShared->State.cbInputPreBuffer));
2315 pStreamShared->State.fInputPreBuffered = true;
2316 fWriteSilence = true; /* For now, just do the most conservative thing. */
2317 }
2318 cbStreamUsed = cbPeriod;
2319 }
2320 /*
2321 * When we're low on data, we must really try fetch some ourselves
2322 * as buffer underruns must not happen.
2323 */
2324 else
2325 {
2326 /** @todo We're ending up here to frequently with pulse audio at least (just
2327 * watch the stream stats in the statistcs viewer, and way to often we
2328 * have to inject silence bytes. I suspect part of the problem is
2329 * that the HDA device require a much better latency than what the
2330 * pulse audio is configured for by default (10 ms vs 150ms). */
2331 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowProblems);
2332 Log(("hdaR3StreamUpdateDma: Warning! Stream #%u has insufficient data available: %u bytes, need %u. Will try move pull more data into the buffer...\n",
2333 pStreamShared->u8SD, cbStreamUsed, cbPeriod));
2334 int rc = AudioMixerSinkTryLock(pSink);
2335 if (RT_SUCCESS(rc))
2336 {
2337 AudioMixerSinkUpdate(pSink, cbStreamUsed, cbPeriod);
2338 hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2339 AudioMixerSinkUnlock(pSink);
2340 }
2341 else
2342 RTThreadYield();
2343 Log(("hdaR3StreamUpdateDma: Gained %u bytes.\n", hdaR3StreamGetUsed(pStreamR3) - cbStreamUsed));
2344 cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2345 if (cbStreamUsed < cbPeriod)
2346 {
2347 /* Unable to find sufficient input data by simple prodding.
2348 In order to keep a constant byte stream following thru the DMA
2349 engine into the guest, we will try again and then fall back on
2350 filling the gap with silence. */
2351 uint32_t cbSilence = 0;
2352 do
2353 {
2354 AudioMixerSinkLock(pSink);
2355
2356 cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2357 if (cbStreamUsed < cbPeriod)
2358 {
2359 hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2360 cbStreamUsed = hdaR3StreamGetUsed(pStreamR3);
2361 while (cbStreamUsed < cbPeriod)
2362 {
2363 void *pvDstBuf;
2364 size_t cbDstBuf;
2365 RTCircBufAcquireWriteBlock(pStreamR3->State.pCircBuf, cbPeriod - cbStreamUsed,
2366 &pvDstBuf, &cbDstBuf);
2367 RT_BZERO(pvDstBuf, cbDstBuf);
2368 RTCircBufReleaseWriteBlock(pStreamR3->State.pCircBuf, cbDstBuf);
2369 cbSilence += (uint32_t)cbDstBuf;
2370 cbStreamUsed += (uint32_t)cbDstBuf;
2371 }
2372 }
2373
2374 AudioMixerSinkUnlock(pSink);
2375 } while (cbStreamUsed < cbPeriod);
2376 if (cbSilence > 0)
2377 {
2378 STAM_REL_COUNTER_INC(&pStreamR3->State.StatDmaFlowErrors);
2379 STAM_REL_COUNTER_ADD(&pStreamR3->State.StatDmaFlowErrorBytes, cbSilence);
2380 LogRel2(("HDA: Warning: Stream #%RU8 underrun, added %u bytes of silence (%u us)\n", pStreamShared->u8SD,
2381 cbSilence, PDMAudioPropsBytesToMicro(&pStreamShared->State.Cfg.Props, cbSilence)));
2382 }
2383 }
2384 }
2385
2386 /*
2387 * Do the DMA'ing.
2388 */
2389 if (cbStreamUsed)
2390 hdaR3StreamDoDmaInput(pDevIns, pThis, pStreamShared, pStreamR3,
2391 RT_MIN(cbStreamUsed, cbPeriod), fWriteSilence, tsNowNs);
2392
2393 /*
2394 * We should always kick the AIO thread.
2395 */
2396 /** @todo This isn't entirely ideal. If we get into an underrun situation,
2397 * we ideally want the AIO thread to run right before the DMA timer
2398 * rather than right after it ran. */
2399 Log5Func(("Notifying AIO thread\n"));
2400 rc2 = AudioMixerSinkSignalUpdateJob(pSink);
2401 AssertRC(rc2);
2402 pStreamShared->State.tsLastReadNs = tsNowNs;
2403 }
2404}
2405
2406
2407/**
2408 * @callback_method_impl{FNAUDMIXSINKUPDATE}
2409 *
2410 * For output streams this moves data from the internal DMA buffer (in which
2411 * hdaR3StreamUpdateDma put it), thru the mixer and to the various backend audio
2412 * devices.
2413 *
2414 * For input streams this pulls data from the backend audio device(s), thru the
2415 * mixer and puts it in the internal DMA buffer ready for hdaR3StreamUpdateDma
2416 * to pump into guest memory.
2417 */
2418DECLCALLBACK(void) hdaR3StreamUpdateAsyncIoJob(PPDMDEVINS pDevIns, PAUDMIXSINK pSink, void *pvUser)
2419{
2420 PHDASTATE const pThis = PDMDEVINS_2_DATA(pDevIns, PHDASTATE);
2421 PHDASTATER3 const pThisCC = PDMDEVINS_2_DATA_CC(pDevIns, PHDASTATER3);
2422 PHDASTREAMR3 const pStreamR3 = (PHDASTREAMR3)pvUser;
2423 PHDASTREAM const pStreamShared = &pThis->aStreams[pStreamR3 - &pThisCC->aStreams[0]];
2424 Assert(pStreamR3 - &pThisCC->aStreams[0] == pStreamR3->u8SD);
2425 Assert(pStreamShared->u8SD == pStreamR3->u8SD);
2426 RT_NOREF(pSink);
2427
2428 /*
2429 * Make sure we haven't change sink and that it's still active (it
2430 * should be or we wouldn't have been called).
2431 */
2432 AssertReturnVoid(pStreamR3->pMixSink && pSink == pStreamR3->pMixSink->pMixSink);
2433 AssertReturnVoid(AudioMixerSinkIsActive(pSink));
2434
2435 /*
2436 * Output streams (SDO).
2437 */
2438 if (hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_OUT)
2439 hdaR3StreamPushToMixer(pStreamShared, pStreamR3, pSink, RTTimeNanoTS());
2440 /*
2441 * Input stream (SDI).
2442 */
2443 else
2444 {
2445 Assert(hdaGetDirFromSD(pStreamShared->u8SD) == PDMAUDIODIR_IN);
2446 hdaR3StreamPullFromMixer(pStreamShared, pStreamR3, pSink);
2447 }
2448}
2449
2450#endif /* IN_RING3 */
2451
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