| 1 | /* $Id: DevHdaStream.h 98103 2023-01-17 14:15:46Z vboxsync $ */
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| 2 | /** @file
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| 3 | * Intel HD Audio Controller Emulation - Streams.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2017-2023 Oracle and/or its affiliates.
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| 8 | *
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| 9 | * This file is part of VirtualBox base platform packages, as
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| 10 | * available from https://www.virtualbox.org.
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| 11 | *
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| 12 | * This program is free software; you can redistribute it and/or
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| 13 | * modify it under the terms of the GNU General Public License
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| 14 | * as published by the Free Software Foundation, in version 3 of the
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| 15 | * License.
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| 16 | *
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| 17 | * This program is distributed in the hope that it will be useful, but
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| 18 | * WITHOUT ANY WARRANTY; without even the implied warranty of
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| 19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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| 20 | * General Public License for more details.
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| 21 | *
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| 22 | * You should have received a copy of the GNU General Public License
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| 23 | * along with this program; if not, see <https://www.gnu.org/licenses>.
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| 24 | *
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| 25 | * SPDX-License-Identifier: GPL-3.0-only
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| 26 | */
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| 27 |
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| 28 | #ifndef VBOX_INCLUDED_SRC_Audio_DevHdaStream_h
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| 29 | #define VBOX_INCLUDED_SRC_Audio_DevHdaStream_h
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| 30 | #ifndef RT_WITHOUT_PRAGMA_ONCE
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| 31 | # pragma once
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| 32 | #endif
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| 33 |
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| 34 | #ifndef VBOX_INCLUDED_SRC_Audio_DevHda_h
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| 35 | # error "Only include DevHda.h!"
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| 36 | #endif
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| 37 |
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| 38 |
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| 39 | /**
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| 40 | * Structure containing HDA stream debug stuff, configurable at runtime.
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| 41 | */
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| 42 | typedef struct HDASTREAMDEBUGRT
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| 43 | {
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| 44 | /** Whether debugging is enabled or not. */
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| 45 | bool fEnabled;
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| 46 | uint8_t Padding[7];
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| 47 | /** File for dumping stream reads / writes.
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| 48 | * For input streams, this dumps data being written to the device FIFO,
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| 49 | * whereas for output streams this dumps data being read from the device FIFO. */
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| 50 | R3PTRTYPE(PAUDIOHLPFILE) pFileStream;
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| 51 | /** File for dumping raw DMA reads / writes.
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| 52 | * For input streams, this dumps data being written to the device DMA,
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| 53 | * whereas for output streams this dumps data being read from the device DMA. */
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| 54 | R3PTRTYPE(PAUDIOHLPFILE) pFileDMARaw;
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| 55 | /** File for dumping mapped (that is, extracted) DMA reads / writes. */
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| 56 | R3PTRTYPE(PAUDIOHLPFILE) pFileDMAMapped;
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| 57 | } HDASTREAMDEBUGRT;
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| 58 |
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| 59 | /**
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| 60 | * Structure containing HDA stream debug information.
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| 61 | */
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| 62 | typedef struct HDASTREAMDEBUG
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| 63 | {
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| 64 | /** Runtime debug info. */
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| 65 | HDASTREAMDEBUGRT Runtime;
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| 66 | uint64_t au64Alignment[2];
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| 67 | } HDASTREAMDEBUG;
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| 68 |
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| 69 | /**
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| 70 | * Internal state of a HDA stream.
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| 71 | */
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| 72 | typedef struct HDASTREAMSTATE
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| 73 | {
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| 74 | /** Flag indicating whether this stream currently is
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| 75 | * in reset mode and therefore not acccessible by the guest. */
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| 76 | volatile bool fInReset;
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| 77 | /** Flag indicating if the stream is in running state or not. */
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| 78 | volatile bool fRunning;
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| 79 | /** How many interrupts are pending due to
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| 80 | * BDLE interrupt-on-completion (IOC) bits set. */
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| 81 | uint8_t cTransferPendingInterrupts;
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| 82 | /** Input streams only: Set when we switch from feeding the guest silence and
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| 83 | * commits to proving actual audio input bytes. */
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| 84 | bool fInputPreBuffered;
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| 85 | /** Input streams only: The number of bytes we need to prebuffer. */
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| 86 | uint32_t cbInputPreBuffer;
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| 87 | /** Timestamp (absolute, in timer ticks) of the last DMA data transfer.
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| 88 | * @note This is used for wall clock (WALCLK) calculations. */
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| 89 | uint64_t volatile tsTransferLast;
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| 90 | /** The stream's current configuration (matches SDnFMT). */
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| 91 | PDMAUDIOSTREAMCFG Cfg;
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| 92 | /** Timestamp (real time, in ns) of last DMA transfer. */
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| 93 | uint64_t tsLastTransferNs;
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| 94 | /** Timestamp (real time, in ns) of last stream read (to backends).
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| 95 | * When running in async I/O mode, this differs from \a tsLastTransferNs,
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| 96 | * because reading / processing will be done in a separate stream. */
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| 97 | uint64_t tsLastReadNs;
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| 98 |
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| 99 | /** The start time for the playback (on the timer clock). */
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| 100 | uint64_t tsStart;
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| 101 |
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| 102 | /** @name DMA engine
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| 103 | * @{ */
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| 104 | /** Timestamp (absolute, in timer ticks) of the next DMA data transfer.
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| 105 | * Next for determining the next scheduling window.
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| 106 | * Can be 0 if no next transfer is scheduled. */
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| 107 | uint64_t tsTransferNext;
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| 108 | /** The size of the current DMA transfer period. */
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| 109 | uint32_t cbCurDmaPeriod;
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| 110 | /** The size of an average transfer. */
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| 111 | uint32_t cbAvgTransfer;
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| 112 |
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| 113 | /** Current circular buffer read offset (for tracing & logging). */
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| 114 | uint64_t offRead;
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| 115 | /** Current circular buffer write offset (for tracing & logging). */
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| 116 | uint64_t offWrite;
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| 117 |
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| 118 | /** The offset into the current BDLE. */
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| 119 | uint32_t offCurBdle;
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| 120 | /** LVI + 1 */
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| 121 | uint16_t cBdles;
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| 122 | /** The index of the current BDLE.
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| 123 | * This is the entry which period is currently "running" on the DMA timer. */
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| 124 | uint8_t idxCurBdle;
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| 125 | /** The number of prologue scheduling steps.
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| 126 | * This is used when the tail BDLEs doesn't have IOC set. */
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| 127 | uint8_t cSchedulePrologue;
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| 128 | /** Number of scheduling steps. */
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| 129 | uint16_t cSchedule;
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| 130 | /** Current scheduling step. */
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| 131 | uint16_t idxSchedule;
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| 132 | /** Current loop number within the current scheduling step. */
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| 133 | uint32_t idxScheduleLoop;
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| 134 |
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| 135 | /** Buffer descriptors and additional timer scheduling state.
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| 136 | * (Same as HDABDLEDESC, with more sensible naming.) */
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| 137 | struct
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| 138 | {
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| 139 | /** The buffer address. */
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| 140 | uint64_t GCPhys;
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| 141 | /** The buffer size (guest bytes). */
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| 142 | uint32_t cb;
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| 143 | /** The flags (only bit 0 is defined). */
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| 144 | uint32_t fFlags;
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| 145 | } aBdl[256];
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| 146 | /** Scheduling steps. */
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| 147 | struct
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| 148 | {
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| 149 | /** Number of timer ticks per period.
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| 150 | * ASSUMES that we don't need a full second and that the timer resolution
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| 151 | * isn't much higher than nanoseconds. */
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| 152 | uint32_t cPeriodTicks;
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| 153 | /** The period length in host bytes. */
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| 154 | uint32_t cbPeriod;
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| 155 | /** Number of times to repeat the period. */
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| 156 | uint32_t cLoops;
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| 157 | /** The BDL index of the first entry. */
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| 158 | uint8_t idxFirst;
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| 159 | /** The number of BDL entries. */
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| 160 | uint8_t cEntries;
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| 161 | uint8_t abPadding[2];
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| 162 | } aSchedule[512+8];
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| 163 |
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| 164 | #ifdef VBOX_HDA_WITH_ON_REG_ACCESS_DMA
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| 165 | /** Number of valid bytes in abDma.
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| 166 | * @note Volatile to prevent the compiler from re-reading it after we've
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| 167 | * validated the value in ring-0. */
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| 168 | uint32_t volatile cbDma;
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| 169 | /** Total number of bytes going via abDma this timer period. */
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| 170 | uint32_t cbDmaTotal;
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| 171 | /** DMA bounce buffer for ring-0 register reads (LPIB). */
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| 172 | uint8_t abDma[2048 - 8];
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| 173 | #endif
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| 174 | /** @} */
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| 175 | } HDASTREAMSTATE;
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| 176 | AssertCompileSizeAlignment(HDASTREAMSTATE, 16);
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| 177 | AssertCompileMemberAlignment(HDASTREAMSTATE, aBdl, 8);
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| 178 | AssertCompileMemberAlignment(HDASTREAMSTATE, aBdl, 16);
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| 179 | AssertCompileMemberAlignment(HDASTREAMSTATE, aSchedule, 16);
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| 180 |
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| 181 | /**
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| 182 | * An HDA stream (SDI / SDO) - shared.
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| 183 | *
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| 184 | * @note This HDA stream has nothing to do with a regular audio stream handled
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| 185 | * by the audio connector or the audio mixer. This HDA stream is a serial
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| 186 | * data in/out stream (SDI/SDO) defined in hardware and can contain
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| 187 | * multiple audio streams in one single SDI/SDO (interleaving streams).
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| 188 | *
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| 189 | * Contains only register values which do *not* change until a stream reset
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| 190 | * occurs.
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| 191 | */
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| 192 | typedef struct HDASTREAM
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| 193 | {
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| 194 | /** Internal state of this stream. */
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| 195 | HDASTREAMSTATE State;
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| 196 |
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| 197 | /** Stream descriptor number (SDn). */
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| 198 | uint8_t u8SD;
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| 199 | /** Current channel index.
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| 200 | * For a stereo stream, this is u8Channel + 1. */
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| 201 | uint8_t u8Channel;
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| 202 | /** FIFO Watermark (checked + translated in bytes, FIFOW).
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| 203 | * This will be update from hdaRegWriteSDFIFOW() and also copied
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| 204 | * hdaR3StreamInit() for some reason. */
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| 205 | uint8_t u8FIFOW;
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| 206 |
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| 207 | /** @name Register values at stream setup.
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| 208 | * These will all be copied in hdaR3StreamInit().
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| 209 | * @{ */
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| 210 | /** FIFO Size (checked + translated in bytes, FIFOS).
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| 211 | * This is supposedly the max number of bytes we'll be DMA'ing in one chunk
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| 212 | * and correspondingly the LPIB & wall clock update jumps. However, we're
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| 213 | * not at all being honest with the guest about this. */
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| 214 | uint8_t u8FIFOS;
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| 215 | /** Cyclic Buffer Length (SDnCBL) - Represents the size of the ring buffer. */
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| 216 | uint32_t u32CBL;
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| 217 | /** Last Valid Index (SDnLVI). */
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| 218 | uint16_t u16LVI;
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| 219 | /** Format (SDnFMT). */
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| 220 | uint16_t u16FMT;
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| 221 | uint8_t abPadding[4];
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| 222 | /** DMA base address (SDnBDPU - SDnBDPL). */
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| 223 | uint64_t u64BDLBase;
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| 224 | /** @} */
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| 225 |
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| 226 | /** The timer for pumping data thru the attached LUN drivers. */
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| 227 | TMTIMERHANDLE hTimer;
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| 228 |
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| 229 | /** Pad the structure size to a 64 byte alignment. */
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| 230 | uint64_t au64Padding1[2];
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| 231 | } HDASTREAM;
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| 232 | AssertCompileMemberAlignment(HDASTREAM, State.aBdl, 16);
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| 233 | AssertCompileMemberAlignment(HDASTREAM, State.aSchedule, 16);
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| 234 | AssertCompileSizeAlignment(HDASTREAM, 64);
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| 235 | /** Pointer to an HDA stream (SDI / SDO). */
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| 236 | typedef HDASTREAM *PHDASTREAM;
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| 237 |
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| 238 |
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| 239 | /**
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| 240 | * An HDA stream (SDI / SDO) - ring-3 bits.
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| 241 | */
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| 242 | typedef struct HDASTREAMR3
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| 243 | {
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| 244 | /** Stream descriptor number (SDn). */
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| 245 | uint8_t u8SD;
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| 246 | uint8_t abPadding[7];
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| 247 | /** The shared state for the parent HDA device. */
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| 248 | R3PTRTYPE(PHDASTATE) pHDAStateShared;
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| 249 | /** The ring-3 state for the parent HDA device. */
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| 250 | R3PTRTYPE(PHDASTATER3) pHDAStateR3;
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| 251 | /** Pointer to HDA sink this stream is attached to. */
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| 252 | R3PTRTYPE(PHDAMIXERSINK) pMixSink;
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| 253 | /** Internal state of this stream. */
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| 254 | struct
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| 255 | {
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| 256 | /** Circular buffer (FIFO) for holding DMA'ed data. */
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| 257 | R3PTRTYPE(PRTCIRCBUF) pCircBuf;
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| 258 | /** The mixer sink this stream has registered AIO update callback with.
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| 259 | * This is NULL till we register it, typically in hdaR3StreamEnable.
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| 260 | * (The problem with following the pMixSink assignment is that hdaR3StreamReset
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| 261 | * sets it without updating the HDA sink structure, so things get out of
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| 262 | * wack in hdaR3MixerControl later in the initial device reset.) */
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| 263 | PAUDMIXSINK pAioRegSink;
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| 264 |
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| 265 | /** Size of the DMA buffer (pCircBuf) in bytes. */
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| 266 | uint32_t StatDmaBufSize;
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| 267 | /** Number of used bytes in the DMA buffer (pCircBuf). */
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| 268 | uint32_t StatDmaBufUsed;
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| 269 | /** Counter for all under/overflows problems. */
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| 270 | STAMCOUNTER StatDmaFlowProblems;
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| 271 | /** Counter for unresovled under/overflows problems. */
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| 272 | STAMCOUNTER StatDmaFlowErrors;
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| 273 | /** Number of bytes involved in unresolved flow errors. */
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| 274 | STAMCOUNTER StatDmaFlowErrorBytes;
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| 275 | /** DMA skipped because buffer interrupt pending. */
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| 276 | STAMCOUNTER StatDmaSkippedPendingBcis;
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| 277 |
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| 278 | STAMPROFILE StatStart;
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| 279 | STAMPROFILE StatReset;
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| 280 | STAMPROFILE StatStop;
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| 281 | } State;
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| 282 | /** Debug bits. */
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| 283 | HDASTREAMDEBUG Dbg;
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| 284 | uint64_t au64Alignment[3];
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| 285 | } HDASTREAMR3;
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| 286 | AssertCompileSizeAlignment(HDASTREAMR3, 64);
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| 287 | /** Pointer to an HDA stream (SDI / SDO). */
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| 288 | typedef HDASTREAMR3 *PHDASTREAMR3;
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| 289 |
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| 290 | /** @name Stream functions (all contexts).
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| 291 | * @{
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| 292 | */
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| 293 | VBOXSTRICTRC hdaStreamDoOnAccessDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
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| 294 | uint64_t tsNow, uint32_t cbToTransfer);
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| 295 | VBOXSTRICTRC hdaStreamMaybeDoOnAccessDmaOutput(PPDMDEVINS pDevIns, PHDASTATE pThis,
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| 296 | PHDASTREAM pStreamShared, uint64_t tsNow);
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| 297 | /** @} */
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| 298 |
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| 299 | #ifdef IN_RING3
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| 300 |
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| 301 | /** @name Stream functions (ring-3).
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| 302 | * @{
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| 303 | */
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| 304 | int hdaR3StreamConstruct(PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, PHDASTATE pThis,
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| 305 | PHDASTATER3 pThisCC, uint8_t uSD);
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| 306 | void hdaR3StreamDestroy(PHDASTREAMR3 pStreamR3);
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| 307 | int hdaR3StreamSetUp(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared,
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| 308 | PHDASTREAMR3 pStreamR3, uint8_t uSD);
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| 309 | void hdaR3StreamReset(PHDASTATE pThis, PHDASTATER3 pThisCC,
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| 310 | PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, uint8_t uSD);
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| 311 | int hdaR3StreamEnable(PHDASTATE pThis, PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3, bool fEnable);
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| 312 | void hdaR3StreamMarkStarted(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTREAM pStreamShared, uint64_t tsNow);
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| 313 | void hdaR3StreamMarkStopped(PHDASTREAM pStreamShared);
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| 314 |
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| 315 | uint64_t hdaR3StreamTimerMain(PPDMDEVINS pDevIns, PHDASTATE pThis, PHDASTATER3 pThisCC,
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| 316 | PHDASTREAM pStreamShared, PHDASTREAMR3 pStreamR3);
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| 317 | DECLCALLBACK(void) hdaR3StreamUpdateAsyncIoJob(PPDMDEVINS pDevIns, PAUDMIXSINK pSink, void *pvUser);
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| 318 | /** @} */
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| 319 |
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| 320 | /** @name Helper functions associated with the stream code.
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| 321 | * @{ */
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| 322 | int hdaR3SDFMTToPCMProps(uint16_t u16SDFMT, PPDMAUDIOPCMPROPS pProps);
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| 323 | # ifdef LOG_ENABLED
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| 324 | void hdaR3BDLEDumpAll(PPDMDEVINS pDevIns, PHDASTATE pThis, uint64_t u64BDLBase, uint16_t cBDLE);
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| 325 | # endif
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| 326 | /** @} */
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| 327 |
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| 328 | #endif /* IN_RING3 */
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| 329 | #endif /* !VBOX_INCLUDED_SRC_Audio_DevHdaStream_h */
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| 330 |
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